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Rev | Author | Line No. | Line |
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2327 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Keith Packard |
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25 | * |
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26 | */ |
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27 | |||
28 | #include |
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2330 | Serge | 29 | #include |
3031 | serge | 30 | #include |
31 | #include |
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32 | #include |
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33 | #include |
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34 | #include |
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2327 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2327 | Serge | 37 | #include "i915_drv.h" |
38 | |||
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
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40 | |||
41 | /** |
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42 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
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43 | * @intel_dp: DP struct |
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44 | * |
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45 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
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46 | * will return true, and false otherwise. |
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47 | */ |
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48 | static bool is_edp(struct intel_dp *intel_dp) |
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49 | { |
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3243 | Serge | 50 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
51 | |||
52 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
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2327 | Serge | 53 | } |
54 | |||
55 | /** |
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56 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? |
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57 | * @intel_dp: DP struct |
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58 | * |
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59 | * Returns true if the given DP struct corresponds to a PCH DP port attached |
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60 | * to an eDP panel, false otherwise. Helpful for determining whether we |
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61 | * may need FDI resources for a given DP output or not. |
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62 | */ |
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63 | static bool is_pch_edp(struct intel_dp *intel_dp) |
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64 | { |
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65 | return intel_dp->is_pch_edp; |
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66 | } |
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67 | |||
2342 | Serge | 68 | /** |
69 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? |
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70 | * @intel_dp: DP struct |
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71 | * |
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72 | * Returns true if the given DP struct corresponds to a CPU eDP port. |
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73 | */ |
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74 | static bool is_cpu_edp(struct intel_dp *intel_dp) |
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75 | { |
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76 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); |
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77 | } |
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78 | |||
3243 | Serge | 79 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
2327 | Serge | 80 | { |
3243 | Serge | 81 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
82 | |||
83 | return intel_dig_port->base.base.dev; |
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2327 | Serge | 84 | } |
85 | |||
2330 | Serge | 86 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
87 | { |
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3243 | Serge | 88 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
2330 | Serge | 89 | } |
2327 | Serge | 90 | |
91 | /** |
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92 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? |
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93 | * @encoder: DRM encoder |
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94 | * |
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95 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed |
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96 | * by intel_display.c. |
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97 | */ |
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98 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) |
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99 | { |
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100 | struct intel_dp *intel_dp; |
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101 | |||
102 | if (!encoder) |
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103 | return false; |
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104 | |||
105 | intel_dp = enc_to_intel_dp(encoder); |
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106 | |||
107 | return is_pch_edp(intel_dp); |
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108 | } |
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109 | |||
2330 | Serge | 110 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
111 | |||
2327 | Serge | 112 | void |
2342 | Serge | 113 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
2327 | Serge | 114 | int *lane_num, int *link_bw) |
115 | { |
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3243 | Serge | 116 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
2327 | Serge | 117 | |
118 | *lane_num = intel_dp->lane_count; |
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3243 | Serge | 119 | *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
2327 | Serge | 120 | } |
121 | |||
3031 | serge | 122 | int |
123 | intel_edp_target_clock(struct intel_encoder *intel_encoder, |
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124 | struct drm_display_mode *mode) |
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125 | { |
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3243 | Serge | 126 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
127 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
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3031 | serge | 128 | |
3243 | Serge | 129 | if (intel_connector->panel.fixed_mode) |
130 | return intel_connector->panel.fixed_mode->clock; |
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3031 | serge | 131 | else |
132 | return mode->clock; |
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133 | } |
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134 | |||
2330 | Serge | 135 | static int |
136 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
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137 | { |
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138 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
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2327 | Serge | 139 | |
2330 | Serge | 140 | switch (max_link_bw) { |
141 | case DP_LINK_BW_1_62: |
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142 | case DP_LINK_BW_2_7: |
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143 | break; |
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144 | default: |
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145 | max_link_bw = DP_LINK_BW_1_62; |
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146 | break; |
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147 | } |
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148 | return max_link_bw; |
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149 | } |
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2327 | Serge | 150 | |
2330 | Serge | 151 | static int |
152 | intel_dp_link_clock(uint8_t link_bw) |
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153 | { |
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154 | if (link_bw == DP_LINK_BW_2_7) |
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155 | return 270000; |
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156 | else |
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157 | return 162000; |
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158 | } |
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2327 | Serge | 159 | |
2342 | Serge | 160 | /* |
161 | * The units on the numbers in the next two are... bizarre. Examples will |
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162 | * make it clearer; this one parallels an example in the eDP spec. |
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163 | * |
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164 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
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165 | * |
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166 | * 270000 * 1 * 8 / 10 == 216000 |
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167 | * |
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168 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
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169 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
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170 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
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171 | * 119000. At 18bpp that's 2142000 kilobits per second. |
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172 | * |
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173 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
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174 | * get the result in decakilobits instead of kilobits. |
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175 | */ |
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176 | |||
2330 | Serge | 177 | static int |
2351 | Serge | 178 | intel_dp_link_required(int pixel_clock, int bpp) |
2330 | Serge | 179 | { |
2342 | Serge | 180 | return (pixel_clock * bpp + 9) / 10; |
2330 | Serge | 181 | } |
2327 | Serge | 182 | |
2330 | Serge | 183 | static int |
184 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
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185 | { |
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186 | return (max_link_clock * max_lanes * 8) / 10; |
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187 | } |
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2327 | Serge | 188 | |
3031 | serge | 189 | static bool |
190 | intel_dp_adjust_dithering(struct intel_dp *intel_dp, |
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191 | struct drm_display_mode *mode, |
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192 | bool adjust_mode) |
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193 | { |
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194 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
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3243 | Serge | 195 | int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
3031 | serge | 196 | int max_rate, mode_rate; |
197 | |||
198 | mode_rate = intel_dp_link_required(mode->clock, 24); |
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199 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
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200 | |||
201 | if (mode_rate > max_rate) { |
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202 | mode_rate = intel_dp_link_required(mode->clock, 18); |
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203 | if (mode_rate > max_rate) |
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204 | return false; |
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205 | |||
206 | if (adjust_mode) |
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207 | mode->private_flags |
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208 | |= INTEL_MODE_DP_FORCE_6BPC; |
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209 | |||
210 | return true; |
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211 | } |
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212 | |||
213 | return true; |
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214 | } |
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215 | |||
2330 | Serge | 216 | static int |
217 | intel_dp_mode_valid(struct drm_connector *connector, |
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218 | struct drm_display_mode *mode) |
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219 | { |
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220 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
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3243 | Serge | 221 | struct intel_connector *intel_connector = to_intel_connector(connector); |
222 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
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2327 | Serge | 223 | |
3243 | Serge | 224 | if (is_edp(intel_dp) && fixed_mode) { |
225 | if (mode->hdisplay > fixed_mode->hdisplay) |
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2330 | Serge | 226 | return MODE_PANEL; |
2327 | Serge | 227 | |
3243 | Serge | 228 | if (mode->vdisplay > fixed_mode->vdisplay) |
2330 | Serge | 229 | return MODE_PANEL; |
230 | } |
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2327 | Serge | 231 | |
3031 | serge | 232 | if (!intel_dp_adjust_dithering(intel_dp, mode, false)) |
2330 | Serge | 233 | return MODE_CLOCK_HIGH; |
2327 | Serge | 234 | |
2330 | Serge | 235 | if (mode->clock < 10000) |
236 | return MODE_CLOCK_LOW; |
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237 | |||
3031 | serge | 238 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
239 | return MODE_H_ILLEGAL; |
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240 | |||
2330 | Serge | 241 | return MODE_OK; |
242 | } |
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243 | |||
244 | static uint32_t |
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245 | pack_aux(uint8_t *src, int src_bytes) |
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246 | { |
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247 | int i; |
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248 | uint32_t v = 0; |
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249 | |||
250 | if (src_bytes > 4) |
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251 | src_bytes = 4; |
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252 | for (i = 0; i < src_bytes; i++) |
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253 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
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254 | return v; |
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255 | } |
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256 | |||
257 | static void |
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258 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
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259 | { |
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260 | int i; |
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261 | if (dst_bytes > 4) |
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262 | dst_bytes = 4; |
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263 | for (i = 0; i < dst_bytes; i++) |
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264 | dst[i] = src >> ((3-i) * 8); |
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265 | } |
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266 | |||
267 | /* hrawclock is 1/4 the FSB frequency */ |
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268 | static int |
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269 | intel_hrawclk(struct drm_device *dev) |
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270 | { |
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271 | struct drm_i915_private *dev_priv = dev->dev_private; |
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272 | uint32_t clkcfg; |
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273 | |||
3243 | Serge | 274 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
275 | if (IS_VALLEYVIEW(dev)) |
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276 | return 200; |
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277 | |||
2330 | Serge | 278 | clkcfg = I915_READ(CLKCFG); |
279 | switch (clkcfg & CLKCFG_FSB_MASK) { |
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280 | case CLKCFG_FSB_400: |
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281 | return 100; |
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282 | case CLKCFG_FSB_533: |
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283 | return 133; |
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284 | case CLKCFG_FSB_667: |
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285 | return 166; |
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286 | case CLKCFG_FSB_800: |
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287 | return 200; |
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288 | case CLKCFG_FSB_1067: |
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289 | return 266; |
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290 | case CLKCFG_FSB_1333: |
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291 | return 333; |
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292 | /* these two are just a guess; one of them might be right */ |
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293 | case CLKCFG_FSB_1600: |
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294 | case CLKCFG_FSB_1600_ALT: |
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295 | return 400; |
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296 | default: |
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297 | return 133; |
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298 | } |
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299 | } |
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300 | |||
2342 | Serge | 301 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
302 | { |
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3243 | Serge | 303 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 304 | struct drm_i915_private *dev_priv = dev->dev_private; |
305 | |||
306 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; |
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307 | } |
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308 | |||
309 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
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310 | { |
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3243 | Serge | 311 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 312 | struct drm_i915_private *dev_priv = dev->dev_private; |
313 | |||
314 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; |
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315 | } |
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316 | |||
317 | static void |
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318 | intel_dp_check_edp(struct intel_dp *intel_dp) |
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319 | { |
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3243 | Serge | 320 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 321 | struct drm_i915_private *dev_priv = dev->dev_private; |
322 | |||
323 | if (!is_edp(intel_dp)) |
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324 | return; |
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325 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
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326 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
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327 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
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328 | I915_READ(PCH_PP_STATUS), |
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329 | I915_READ(PCH_PP_CONTROL)); |
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330 | } |
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331 | } |
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332 | |||
2330 | Serge | 333 | static int |
334 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
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335 | uint8_t *send, int send_bytes, |
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336 | uint8_t *recv, int recv_size) |
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337 | { |
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338 | uint32_t output_reg = intel_dp->output_reg; |
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3243 | Serge | 339 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
340 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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2330 | Serge | 341 | struct drm_i915_private *dev_priv = dev->dev_private; |
342 | uint32_t ch_ctl = output_reg + 0x10; |
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343 | uint32_t ch_data = ch_ctl + 4; |
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344 | int i; |
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345 | int recv_bytes; |
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346 | uint32_t status; |
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347 | uint32_t aux_clock_divider; |
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348 | int try, precharge; |
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349 | |||
3243 | Serge | 350 | if (IS_HASWELL(dev)) { |
351 | switch (intel_dig_port->port) { |
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352 | case PORT_A: |
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353 | ch_ctl = DPA_AUX_CH_CTL; |
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354 | ch_data = DPA_AUX_CH_DATA1; |
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355 | break; |
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356 | case PORT_B: |
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357 | ch_ctl = PCH_DPB_AUX_CH_CTL; |
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358 | ch_data = PCH_DPB_AUX_CH_DATA1; |
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359 | break; |
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360 | case PORT_C: |
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361 | ch_ctl = PCH_DPC_AUX_CH_CTL; |
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362 | ch_data = PCH_DPC_AUX_CH_DATA1; |
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363 | break; |
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364 | case PORT_D: |
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365 | ch_ctl = PCH_DPD_AUX_CH_CTL; |
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366 | ch_data = PCH_DPD_AUX_CH_DATA1; |
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367 | break; |
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368 | default: |
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369 | BUG(); |
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370 | } |
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371 | } |
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372 | |||
2342 | Serge | 373 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 374 | /* The clock divider is based off the hrawclk, |
375 | * and would like to run at 2MHz. So, take the |
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376 | * hrawclk value and divide by 2 and use that |
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377 | * |
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378 | * Note that PCH attached eDP panels should use a 125MHz input |
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379 | * clock divider. |
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380 | */ |
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2342 | Serge | 381 | if (is_cpu_edp(intel_dp)) { |
3243 | Serge | 382 | if (IS_HASWELL(dev)) |
383 | aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; |
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384 | else if (IS_VALLEYVIEW(dev)) |
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385 | aux_clock_divider = 100; |
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386 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
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2342 | Serge | 387 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
2330 | Serge | 388 | else |
389 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
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390 | } else if (HAS_PCH_SPLIT(dev)) |
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3243 | Serge | 391 | aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2330 | Serge | 392 | else |
393 | aux_clock_divider = intel_hrawclk(dev) / 2; |
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394 | |||
395 | if (IS_GEN6(dev)) |
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396 | precharge = 3; |
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397 | else |
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398 | precharge = 5; |
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399 | |||
400 | /* Try to wait for any previous AUX channel activity */ |
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401 | for (try = 0; try < 3; try++) { |
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402 | status = I915_READ(ch_ctl); |
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403 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
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404 | break; |
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405 | msleep(1); |
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406 | } |
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407 | |||
408 | if (try == 3) { |
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409 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
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410 | I915_READ(ch_ctl)); |
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411 | return -EBUSY; |
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412 | } |
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413 | |||
414 | /* Must try at least 3 times according to DP spec */ |
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415 | for (try = 0; try < 5; try++) { |
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416 | /* Load the send data into the aux channel data registers */ |
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417 | for (i = 0; i < send_bytes; i += 4) |
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418 | I915_WRITE(ch_data + i, |
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419 | pack_aux(send + i, send_bytes - i)); |
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420 | |||
421 | /* Send the command and wait for it to complete */ |
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422 | I915_WRITE(ch_ctl, |
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423 | DP_AUX_CH_CTL_SEND_BUSY | |
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424 | DP_AUX_CH_CTL_TIME_OUT_400us | |
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425 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
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426 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
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427 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
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428 | DP_AUX_CH_CTL_DONE | |
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429 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
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430 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
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431 | for (;;) { |
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432 | status = I915_READ(ch_ctl); |
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433 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
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434 | break; |
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435 | udelay(100); |
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436 | } |
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437 | |||
438 | /* Clear done status and any errors */ |
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439 | I915_WRITE(ch_ctl, |
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440 | status | |
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441 | DP_AUX_CH_CTL_DONE | |
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442 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
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443 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
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3031 | serge | 444 | |
445 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
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446 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
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447 | continue; |
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2330 | Serge | 448 | if (status & DP_AUX_CH_CTL_DONE) |
449 | break; |
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450 | } |
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451 | |||
452 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
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453 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
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454 | return -EBUSY; |
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455 | } |
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456 | |||
457 | /* Check for timeout or receive error. |
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458 | * Timeouts occur when the sink is not connected |
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459 | */ |
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460 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
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461 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
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462 | return -EIO; |
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463 | } |
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464 | |||
465 | /* Timeouts occur when the device isn't connected, so they're |
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466 | * "normal" -- don't fill the kernel log with these */ |
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467 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
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468 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
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469 | return -ETIMEDOUT; |
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470 | } |
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471 | |||
472 | /* Unload any bytes sent back from the other side */ |
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473 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
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474 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
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475 | if (recv_bytes > recv_size) |
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476 | recv_bytes = recv_size; |
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477 | |||
478 | for (i = 0; i < recv_bytes; i += 4) |
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479 | unpack_aux(I915_READ(ch_data + i), |
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480 | recv + i, recv_bytes - i); |
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481 | |||
482 | return recv_bytes; |
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483 | } |
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484 | |||
485 | /* Write data to the aux channel in native mode */ |
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486 | static int |
||
487 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
||
488 | uint16_t address, uint8_t *send, int send_bytes) |
||
489 | { |
||
490 | int ret; |
||
491 | uint8_t msg[20]; |
||
492 | int msg_bytes; |
||
493 | uint8_t ack; |
||
494 | |||
2342 | Serge | 495 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 496 | if (send_bytes > 16) |
497 | return -1; |
||
498 | msg[0] = AUX_NATIVE_WRITE << 4; |
||
499 | msg[1] = address >> 8; |
||
500 | msg[2] = address & 0xff; |
||
501 | msg[3] = send_bytes - 1; |
||
502 | memcpy(&msg[4], send, send_bytes); |
||
503 | msg_bytes = send_bytes + 4; |
||
504 | for (;;) { |
||
505 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
||
506 | if (ret < 0) |
||
507 | return ret; |
||
508 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
||
509 | break; |
||
510 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
||
511 | udelay(100); |
||
512 | else |
||
513 | return -EIO; |
||
514 | } |
||
515 | return send_bytes; |
||
516 | } |
||
517 | |||
518 | /* Write a single byte to the aux channel in native mode */ |
||
519 | static int |
||
520 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
||
521 | uint16_t address, uint8_t byte) |
||
522 | { |
||
523 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
||
524 | } |
||
525 | |||
526 | /* read bytes from a native aux channel */ |
||
527 | static int |
||
528 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
||
529 | uint16_t address, uint8_t *recv, int recv_bytes) |
||
530 | { |
||
531 | uint8_t msg[4]; |
||
532 | int msg_bytes; |
||
533 | uint8_t reply[20]; |
||
534 | int reply_bytes; |
||
535 | uint8_t ack; |
||
536 | int ret; |
||
537 | |||
2342 | Serge | 538 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 539 | msg[0] = AUX_NATIVE_READ << 4; |
540 | msg[1] = address >> 8; |
||
541 | msg[2] = address & 0xff; |
||
542 | msg[3] = recv_bytes - 1; |
||
543 | |||
544 | msg_bytes = 4; |
||
545 | reply_bytes = recv_bytes + 1; |
||
546 | |||
547 | for (;;) { |
||
548 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
||
549 | reply, reply_bytes); |
||
550 | if (ret == 0) |
||
551 | return -EPROTO; |
||
552 | if (ret < 0) |
||
553 | return ret; |
||
554 | ack = reply[0]; |
||
555 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { |
||
556 | memcpy(recv, reply + 1, ret - 1); |
||
557 | return ret - 1; |
||
558 | } |
||
559 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
||
560 | udelay(100); |
||
561 | else |
||
562 | return -EIO; |
||
563 | } |
||
564 | } |
||
565 | |||
566 | static int |
||
567 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
||
568 | uint8_t write_byte, uint8_t *read_byte) |
||
569 | { |
||
570 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
||
571 | struct intel_dp *intel_dp = container_of(adapter, |
||
572 | struct intel_dp, |
||
573 | adapter); |
||
574 | uint16_t address = algo_data->address; |
||
575 | uint8_t msg[5]; |
||
576 | uint8_t reply[2]; |
||
577 | unsigned retry; |
||
578 | int msg_bytes; |
||
579 | int reply_bytes; |
||
580 | int ret; |
||
581 | |||
2342 | Serge | 582 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 583 | /* Set up the command byte */ |
584 | if (mode & MODE_I2C_READ) |
||
585 | msg[0] = AUX_I2C_READ << 4; |
||
586 | else |
||
587 | msg[0] = AUX_I2C_WRITE << 4; |
||
588 | |||
589 | if (!(mode & MODE_I2C_STOP)) |
||
590 | msg[0] |= AUX_I2C_MOT << 4; |
||
591 | |||
592 | msg[1] = address >> 8; |
||
593 | msg[2] = address; |
||
594 | |||
595 | switch (mode) { |
||
596 | case MODE_I2C_WRITE: |
||
597 | msg[3] = 0; |
||
598 | msg[4] = write_byte; |
||
599 | msg_bytes = 5; |
||
600 | reply_bytes = 1; |
||
601 | break; |
||
602 | case MODE_I2C_READ: |
||
603 | msg[3] = 0; |
||
604 | msg_bytes = 4; |
||
605 | reply_bytes = 2; |
||
606 | break; |
||
607 | default: |
||
608 | msg_bytes = 3; |
||
609 | reply_bytes = 1; |
||
610 | break; |
||
611 | } |
||
612 | |||
613 | for (retry = 0; retry < 5; retry++) { |
||
614 | ret = intel_dp_aux_ch(intel_dp, |
||
615 | msg, msg_bytes, |
||
616 | reply, reply_bytes); |
||
617 | if (ret < 0) { |
||
618 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
||
619 | return ret; |
||
620 | } |
||
621 | |||
622 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { |
||
623 | case AUX_NATIVE_REPLY_ACK: |
||
624 | /* I2C-over-AUX Reply field is only valid |
||
625 | * when paired with AUX ACK. |
||
626 | */ |
||
627 | break; |
||
628 | case AUX_NATIVE_REPLY_NACK: |
||
629 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
||
630 | return -EREMOTEIO; |
||
631 | case AUX_NATIVE_REPLY_DEFER: |
||
632 | udelay(100); |
||
633 | continue; |
||
634 | default: |
||
635 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
||
636 | reply[0]); |
||
637 | return -EREMOTEIO; |
||
638 | } |
||
639 | |||
640 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
||
641 | case AUX_I2C_REPLY_ACK: |
||
642 | if (mode == MODE_I2C_READ) { |
||
643 | *read_byte = reply[1]; |
||
644 | } |
||
645 | return reply_bytes - 1; |
||
646 | case AUX_I2C_REPLY_NACK: |
||
647 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
||
648 | return -EREMOTEIO; |
||
649 | case AUX_I2C_REPLY_DEFER: |
||
650 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
||
651 | udelay(100); |
||
652 | break; |
||
653 | default: |
||
654 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
||
655 | return -EREMOTEIO; |
||
656 | } |
||
657 | } |
||
658 | |||
659 | DRM_ERROR("too many retries, giving up\n"); |
||
660 | return -EREMOTEIO; |
||
661 | } |
||
662 | |||
663 | static int |
||
664 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
||
665 | struct intel_connector *intel_connector, const char *name) |
||
666 | { |
||
2342 | Serge | 667 | int ret; |
668 | |||
2330 | Serge | 669 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
670 | intel_dp->algo.running = false; |
||
671 | intel_dp->algo.address = 0; |
||
672 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; |
||
673 | |||
2342 | Serge | 674 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
3031 | serge | 675 | intel_dp->adapter.owner = THIS_MODULE; |
2330 | Serge | 676 | intel_dp->adapter.class = I2C_CLASS_DDC; |
2342 | Serge | 677 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
2330 | Serge | 678 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
679 | intel_dp->adapter.algo_data = &intel_dp->algo; |
||
680 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; |
||
681 | |||
2342 | Serge | 682 | ironlake_edp_panel_vdd_on(intel_dp); |
683 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
||
684 | ironlake_edp_panel_vdd_off(intel_dp, false); |
||
685 | return ret; |
||
2330 | Serge | 686 | } |
687 | |||
3243 | Serge | 688 | bool |
3031 | serge | 689 | intel_dp_mode_fixup(struct drm_encoder *encoder, |
690 | const struct drm_display_mode *mode, |
||
2330 | Serge | 691 | struct drm_display_mode *adjusted_mode) |
692 | { |
||
693 | struct drm_device *dev = encoder->dev; |
||
694 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
||
3243 | Serge | 695 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
2330 | Serge | 696 | int lane_count, clock; |
3243 | Serge | 697 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
2330 | Serge | 698 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
3031 | serge | 699 | int bpp, mode_rate; |
2330 | Serge | 700 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
701 | |||
3243 | Serge | 702 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
703 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
||
704 | adjusted_mode); |
||
705 | intel_pch_panel_fitting(dev, |
||
706 | intel_connector->panel.fitting_mode, |
||
2330 | Serge | 707 | mode, adjusted_mode); |
708 | } |
||
709 | |||
3031 | serge | 710 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
711 | return false; |
||
712 | |||
713 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
||
714 | "max bw %02x pixel clock %iKHz\n", |
||
715 | max_lane_count, bws[max_clock], adjusted_mode->clock); |
||
716 | |||
717 | if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) |
||
718 | return false; |
||
719 | |||
720 | bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; |
||
721 | mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); |
||
722 | |||
723 | for (clock = 0; clock <= max_clock; clock++) { |
||
2330 | Serge | 724 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
725 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
||
726 | |||
3031 | serge | 727 | if (mode_rate <= link_avail) { |
2330 | Serge | 728 | intel_dp->link_bw = bws[clock]; |
729 | intel_dp->lane_count = lane_count; |
||
730 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); |
||
3031 | serge | 731 | DRM_DEBUG_KMS("DP link bw %02x lane " |
732 | "count %d clock %d bpp %d\n", |
||
2330 | Serge | 733 | intel_dp->link_bw, intel_dp->lane_count, |
3031 | serge | 734 | adjusted_mode->clock, bpp); |
735 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
||
736 | mode_rate, link_avail); |
||
2330 | Serge | 737 | return true; |
738 | } |
||
739 | } |
||
740 | } |
||
741 | |||
742 | return false; |
||
743 | } |
||
744 | |||
2327 | Serge | 745 | struct intel_dp_m_n { |
746 | uint32_t tu; |
||
747 | uint32_t gmch_m; |
||
748 | uint32_t gmch_n; |
||
749 | uint32_t link_m; |
||
750 | uint32_t link_n; |
||
751 | }; |
||
752 | |||
753 | static void |
||
754 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
||
755 | { |
||
756 | while (*num > 0xffffff || *den > 0xffffff) { |
||
757 | *num >>= 1; |
||
758 | *den >>= 1; |
||
759 | } |
||
760 | } |
||
761 | |||
762 | static void |
||
763 | intel_dp_compute_m_n(int bpp, |
||
764 | int nlanes, |
||
765 | int pixel_clock, |
||
766 | int link_clock, |
||
767 | struct intel_dp_m_n *m_n) |
||
768 | { |
||
769 | m_n->tu = 64; |
||
770 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
||
771 | m_n->gmch_n = link_clock * nlanes; |
||
772 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
||
773 | m_n->link_m = pixel_clock; |
||
774 | m_n->link_n = link_clock; |
||
775 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
||
776 | } |
||
777 | |||
778 | void |
||
779 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
||
780 | struct drm_display_mode *adjusted_mode) |
||
781 | { |
||
782 | struct drm_device *dev = crtc->dev; |
||
3243 | Serge | 783 | struct intel_encoder *intel_encoder; |
784 | struct intel_dp *intel_dp; |
||
2327 | Serge | 785 | struct drm_i915_private *dev_priv = dev->dev_private; |
786 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
787 | int lane_count = 4; |
||
788 | struct intel_dp_m_n m_n; |
||
789 | int pipe = intel_crtc->pipe; |
||
3243 | Serge | 790 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
2327 | Serge | 791 | |
792 | /* |
||
793 | * Find the lane count in the intel_encoder private |
||
794 | */ |
||
3243 | Serge | 795 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
796 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
2327 | Serge | 797 | |
3243 | Serge | 798 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
799 | intel_encoder->type == INTEL_OUTPUT_EDP) |
||
2342 | Serge | 800 | { |
2327 | Serge | 801 | lane_count = intel_dp->lane_count; |
802 | break; |
||
803 | } |
||
804 | } |
||
805 | |||
806 | /* |
||
807 | * Compute the GMCH and Link ratios. The '3' here is |
||
808 | * the number of bytes_per_pixel post-LUT, which we always |
||
809 | * set up for 8-bits of R/G/B, or 3 bytes total. |
||
810 | */ |
||
811 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
||
812 | mode->clock, adjusted_mode->clock, &m_n); |
||
813 | |||
3243 | Serge | 814 | if (IS_HASWELL(dev)) { |
815 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |
||
816 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
||
817 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); |
||
818 | I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); |
||
819 | I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); |
||
820 | } else if (HAS_PCH_SPLIT(dev)) { |
||
821 | I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
||
2327 | Serge | 822 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |
823 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |
||
824 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); |
||
3243 | Serge | 825 | } else if (IS_VALLEYVIEW(dev)) { |
826 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
||
827 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
||
828 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
||
829 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
||
2327 | Serge | 830 | } else { |
831 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
||
3243 | Serge | 832 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
2327 | Serge | 833 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); |
834 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); |
||
835 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); |
||
836 | } |
||
837 | } |
||
838 | |||
3243 | Serge | 839 | void intel_dp_init_link_config(struct intel_dp *intel_dp) |
840 | { |
||
841 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
||
842 | intel_dp->link_configuration[0] = intel_dp->link_bw; |
||
843 | intel_dp->link_configuration[1] = intel_dp->lane_count; |
||
844 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
||
845 | /* |
||
846 | * Check for DPCD version > 1.1 and enhanced framing support |
||
847 | */ |
||
848 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
||
849 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
||
850 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
||
851 | } |
||
852 | } |
||
853 | |||
2330 | Serge | 854 | static void |
855 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
||
856 | struct drm_display_mode *adjusted_mode) |
||
857 | { |
||
858 | struct drm_device *dev = encoder->dev; |
||
2342 | Serge | 859 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 860 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
3243 | Serge | 861 | struct drm_crtc *crtc = encoder->crtc; |
2330 | Serge | 862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2327 | Serge | 863 | |
2342 | Serge | 864 | /* |
865 | * There are four kinds of DP registers: |
||
866 | * |
||
867 | * IBX PCH |
||
868 | * SNB CPU |
||
869 | * IVB CPU |
||
870 | * CPT PCH |
||
871 | * |
||
872 | * IBX PCH and CPU are the same for almost everything, |
||
873 | * except that the CPU DP PLL is configured in this |
||
874 | * register |
||
875 | * |
||
876 | * CPT PCH is quite different, having many bits moved |
||
877 | * to the TRANS_DP_CTL register instead. That |
||
878 | * configuration happens (oddly) in ironlake_pch_enable |
||
879 | */ |
||
2327 | Serge | 880 | |
2342 | Serge | 881 | /* Preserve the BIOS-computed detected bit. This is |
882 | * supposed to be read-only. |
||
883 | */ |
||
884 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
||
2327 | Serge | 885 | |
2342 | Serge | 886 | /* Handle DP bits in common between all three register formats */ |
887 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
||
888 | |||
2330 | Serge | 889 | switch (intel_dp->lane_count) { |
890 | case 1: |
||
891 | intel_dp->DP |= DP_PORT_WIDTH_1; |
||
892 | break; |
||
893 | case 2: |
||
894 | intel_dp->DP |= DP_PORT_WIDTH_2; |
||
895 | break; |
||
896 | case 4: |
||
897 | intel_dp->DP |= DP_PORT_WIDTH_4; |
||
898 | break; |
||
899 | } |
||
2342 | Serge | 900 | if (intel_dp->has_audio) { |
901 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
||
902 | pipe_name(intel_crtc->pipe)); |
||
2330 | Serge | 903 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
2342 | Serge | 904 | intel_write_eld(encoder, adjusted_mode); |
905 | } |
||
2327 | Serge | 906 | |
3243 | Serge | 907 | intel_dp_init_link_config(intel_dp); |
908 | |||
2342 | Serge | 909 | /* Split out the IBX/CPU vs CPT settings */ |
910 | |||
3243 | Serge | 911 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
2342 | Serge | 912 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
913 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
||
914 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
915 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
||
916 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
||
917 | |||
918 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
||
919 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
||
920 | |||
921 | intel_dp->DP |= intel_crtc->pipe << 29; |
||
922 | |||
923 | /* don't miss out required setting for eDP */ |
||
924 | if (adjusted_mode->clock < 200000) |
||
925 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
||
926 | else |
||
927 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
||
928 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
||
929 | intel_dp->DP |= intel_dp->color_range; |
||
930 | |||
931 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
||
932 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
||
933 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
934 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
||
935 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
||
936 | |||
937 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
||
938 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
||
939 | |||
940 | if (intel_crtc->pipe == 1) |
||
2330 | Serge | 941 | intel_dp->DP |= DP_PIPEB_SELECT; |
2327 | Serge | 942 | |
2342 | Serge | 943 | if (is_cpu_edp(intel_dp)) { |
2330 | Serge | 944 | /* don't miss out required setting for eDP */ |
945 | if (adjusted_mode->clock < 200000) |
||
946 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
||
947 | else |
||
948 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
||
949 | } |
||
2342 | Serge | 950 | } else { |
951 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
||
952 | } |
||
2330 | Serge | 953 | } |
2327 | Serge | 954 | |
2342 | Serge | 955 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
956 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
||
957 | |||
958 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
||
959 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
||
960 | |||
961 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
||
962 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
||
963 | |||
964 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, |
||
965 | u32 mask, |
||
966 | u32 value) |
||
967 | { |
||
3243 | Serge | 968 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 969 | struct drm_i915_private *dev_priv = dev->dev_private; |
970 | |||
971 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
||
972 | mask, value, |
||
973 | I915_READ(PCH_PP_STATUS), |
||
974 | I915_READ(PCH_PP_CONTROL)); |
||
975 | |||
976 | if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { |
||
977 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
||
978 | I915_READ(PCH_PP_STATUS), |
||
979 | I915_READ(PCH_PP_CONTROL)); |
||
980 | } |
||
981 | } |
||
982 | |||
983 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
||
984 | { |
||
985 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
||
986 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
||
987 | } |
||
988 | |||
989 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
||
990 | { |
||
991 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
||
992 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
||
993 | } |
||
994 | |||
995 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) |
||
996 | { |
||
997 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
||
998 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
||
999 | } |
||
1000 | |||
1001 | |||
1002 | /* Read the current pp_control value, unlocking the register if it |
||
1003 | * is locked |
||
1004 | */ |
||
1005 | |||
1006 | static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) |
||
1007 | { |
||
1008 | u32 control = I915_READ(PCH_PP_CONTROL); |
||
1009 | |||
1010 | control &= ~PANEL_UNLOCK_MASK; |
||
1011 | control |= PANEL_UNLOCK_REGS; |
||
1012 | return control; |
||
1013 | } |
||
1014 | |||
3243 | Serge | 1015 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
2330 | Serge | 1016 | { |
3243 | Serge | 1017 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1018 | struct drm_i915_private *dev_priv = dev->dev_private; |
1019 | u32 pp; |
||
2327 | Serge | 1020 | |
2342 | Serge | 1021 | if (!is_edp(intel_dp)) |
1022 | return; |
||
1023 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
||
2327 | Serge | 1024 | |
2342 | Serge | 1025 | WARN(intel_dp->want_panel_vdd, |
1026 | "eDP VDD already requested on\n"); |
||
1027 | |||
1028 | intel_dp->want_panel_vdd = true; |
||
1029 | |||
1030 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
||
1031 | DRM_DEBUG_KMS("eDP VDD already on\n"); |
||
1032 | return; |
||
1033 | } |
||
1034 | |||
1035 | if (!ironlake_edp_have_panel_power(intel_dp)) |
||
1036 | ironlake_wait_panel_power_cycle(intel_dp); |
||
1037 | |||
1038 | pp = ironlake_get_pp_control(dev_priv); |
||
2330 | Serge | 1039 | pp |= EDP_FORCE_VDD; |
1040 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
1041 | POSTING_READ(PCH_PP_CONTROL); |
||
2342 | Serge | 1042 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
1043 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); |
||
1044 | |||
1045 | /* |
||
1046 | * If the panel wasn't on, delay before accessing aux channel |
||
1047 | */ |
||
1048 | if (!ironlake_edp_have_panel_power(intel_dp)) { |
||
1049 | DRM_DEBUG_KMS("eDP was not running\n"); |
||
1050 | msleep(intel_dp->panel_power_up_delay); |
||
1051 | } |
||
2330 | Serge | 1052 | } |
2327 | Serge | 1053 | |
2342 | Serge | 1054 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
2330 | Serge | 1055 | { |
3243 | Serge | 1056 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1057 | struct drm_i915_private *dev_priv = dev->dev_private; |
1058 | u32 pp; |
||
2327 | Serge | 1059 | |
2342 | Serge | 1060 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
1061 | pp = ironlake_get_pp_control(dev_priv); |
||
2330 | Serge | 1062 | pp &= ~EDP_FORCE_VDD; |
1063 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
1064 | POSTING_READ(PCH_PP_CONTROL); |
||
2327 | Serge | 1065 | |
2330 | Serge | 1066 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2342 | Serge | 1067 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
1068 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); |
||
1069 | |||
1070 | msleep(intel_dp->panel_power_down_delay); |
||
1071 | } |
||
2330 | Serge | 1072 | } |
2327 | Serge | 1073 | |
3243 | Serge | 1074 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1075 | { |
||
1076 | // struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
||
1077 | // struct intel_dp, panel_vdd_work); |
||
1078 | // struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
1079 | // |
||
1080 | // mutex_lock(&dev->mode_config.mutex); |
||
1081 | // ironlake_panel_vdd_off_sync(intel_dp); |
||
1082 | // mutex_unlock(&dev->mode_config.mutex); |
||
1083 | } |
||
2342 | Serge | 1084 | |
3243 | Serge | 1085 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
2330 | Serge | 1086 | { |
2342 | Serge | 1087 | if (!is_edp(intel_dp)) |
1088 | return; |
||
1089 | |||
1090 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
||
1091 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
||
1092 | |||
1093 | intel_dp->want_panel_vdd = false; |
||
1094 | |||
1095 | if (sync) { |
||
1096 | ironlake_panel_vdd_off_sync(intel_dp); |
||
1097 | } else { |
||
1098 | /* |
||
1099 | * Queue the timer to fire a long |
||
1100 | * time from now (relative to the power down delay) |
||
1101 | * to keep the panel power up across a sequence of operations |
||
1102 | */ |
||
1103 | // schedule_delayed_work(&intel_dp->panel_vdd_work, |
||
1104 | // msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
||
1105 | } |
||
1106 | } |
||
1107 | |||
3243 | Serge | 1108 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
2342 | Serge | 1109 | { |
3243 | Serge | 1110 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1111 | struct drm_i915_private *dev_priv = dev->dev_private; |
2342 | Serge | 1112 | u32 pp; |
2327 | Serge | 1113 | |
2342 | Serge | 1114 | if (!is_edp(intel_dp)) |
1115 | return; |
||
2327 | Serge | 1116 | |
2342 | Serge | 1117 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
2327 | Serge | 1118 | |
2342 | Serge | 1119 | if (ironlake_edp_have_panel_power(intel_dp)) { |
1120 | DRM_DEBUG_KMS("eDP power already on\n"); |
||
1121 | return; |
||
1122 | } |
||
1123 | |||
1124 | ironlake_wait_panel_power_cycle(intel_dp); |
||
1125 | |||
1126 | pp = ironlake_get_pp_control(dev_priv); |
||
1127 | if (IS_GEN5(dev)) { |
||
2330 | Serge | 1128 | /* ILK workaround: disable reset around power sequence */ |
1129 | pp &= ~PANEL_POWER_RESET; |
||
1130 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
1131 | POSTING_READ(PCH_PP_CONTROL); |
||
2342 | Serge | 1132 | } |
2327 | Serge | 1133 | |
2342 | Serge | 1134 | pp |= POWER_TARGET_ON; |
1135 | if (!IS_GEN5(dev)) |
||
1136 | pp |= PANEL_POWER_RESET; |
||
1137 | |||
2330 | Serge | 1138 | I915_WRITE(PCH_PP_CONTROL, pp); |
1139 | POSTING_READ(PCH_PP_CONTROL); |
||
2327 | Serge | 1140 | |
2342 | Serge | 1141 | ironlake_wait_panel_on(intel_dp); |
2327 | Serge | 1142 | |
2342 | Serge | 1143 | if (IS_GEN5(dev)) { |
2330 | Serge | 1144 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1145 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
1146 | POSTING_READ(PCH_PP_CONTROL); |
||
2342 | Serge | 1147 | } |
2330 | Serge | 1148 | } |
2327 | Serge | 1149 | |
3243 | Serge | 1150 | void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
2330 | Serge | 1151 | { |
3243 | Serge | 1152 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1153 | struct drm_i915_private *dev_priv = dev->dev_private; |
2342 | Serge | 1154 | u32 pp; |
2327 | Serge | 1155 | |
2342 | Serge | 1156 | if (!is_edp(intel_dp)) |
1157 | return; |
||
2327 | Serge | 1158 | |
2342 | Serge | 1159 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
2327 | Serge | 1160 | |
3031 | serge | 1161 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
2342 | Serge | 1162 | |
1163 | pp = ironlake_get_pp_control(dev_priv); |
||
3031 | serge | 1164 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1165 | * panels get very unhappy and cease to work. */ |
||
2342 | Serge | 1166 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); |
2330 | Serge | 1167 | I915_WRITE(PCH_PP_CONTROL, pp); |
1168 | POSTING_READ(PCH_PP_CONTROL); |
||
2327 | Serge | 1169 | |
3031 | serge | 1170 | intel_dp->want_panel_vdd = false; |
1171 | |||
2342 | Serge | 1172 | ironlake_wait_panel_off(intel_dp); |
2330 | Serge | 1173 | } |
2327 | Serge | 1174 | |
3243 | Serge | 1175 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
2330 | Serge | 1176 | { |
3243 | Serge | 1177 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1178 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 1179 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 1180 | int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; |
2330 | Serge | 1181 | u32 pp; |
2327 | Serge | 1182 | |
2342 | Serge | 1183 | if (!is_edp(intel_dp)) |
1184 | return; |
||
1185 | |||
2330 | Serge | 1186 | DRM_DEBUG_KMS("\n"); |
1187 | /* |
||
1188 | * If we enable the backlight right away following a panel power |
||
1189 | * on, we may see slight flicker as the panel syncs with the eDP |
||
1190 | * link. So delay a bit to make sure the image is solid before |
||
1191 | * allowing it to appear. |
||
1192 | */ |
||
2342 | Serge | 1193 | msleep(intel_dp->backlight_on_delay); |
1194 | pp = ironlake_get_pp_control(dev_priv); |
||
2330 | Serge | 1195 | pp |= EDP_BLC_ENABLE; |
1196 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
2342 | Serge | 1197 | POSTING_READ(PCH_PP_CONTROL); |
3243 | Serge | 1198 | |
1199 | intel_panel_enable_backlight(dev, pipe); |
||
2330 | Serge | 1200 | } |
2327 | Serge | 1201 | |
3243 | Serge | 1202 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
2330 | Serge | 1203 | { |
3243 | Serge | 1204 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1205 | struct drm_i915_private *dev_priv = dev->dev_private; |
1206 | u32 pp; |
||
2327 | Serge | 1207 | |
2342 | Serge | 1208 | if (!is_edp(intel_dp)) |
1209 | return; |
||
1210 | |||
3243 | Serge | 1211 | intel_panel_disable_backlight(dev); |
1212 | |||
2330 | Serge | 1213 | DRM_DEBUG_KMS("\n"); |
2342 | Serge | 1214 | pp = ironlake_get_pp_control(dev_priv); |
2330 | Serge | 1215 | pp &= ~EDP_BLC_ENABLE; |
1216 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
2342 | Serge | 1217 | POSTING_READ(PCH_PP_CONTROL); |
1218 | msleep(intel_dp->backlight_off_delay); |
||
2330 | Serge | 1219 | } |
2327 | Serge | 1220 | |
3031 | serge | 1221 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2330 | Serge | 1222 | { |
3243 | Serge | 1223 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1224 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
||
1225 | struct drm_device *dev = crtc->dev; |
||
2330 | Serge | 1226 | struct drm_i915_private *dev_priv = dev->dev_private; |
1227 | u32 dpa_ctl; |
||
2327 | Serge | 1228 | |
3031 | serge | 1229 | assert_pipe_disabled(dev_priv, |
1230 | to_intel_crtc(crtc)->pipe); |
||
1231 | |||
2330 | Serge | 1232 | DRM_DEBUG_KMS("\n"); |
1233 | dpa_ctl = I915_READ(DP_A); |
||
3031 | serge | 1234 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1235 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
||
1236 | |||
1237 | /* We don't adjust intel_dp->DP while tearing down the link, to |
||
1238 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
||
1239 | * enable bits here to ensure that we don't enable too much. */ |
||
1240 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
||
1241 | intel_dp->DP |= DP_PLL_ENABLE; |
||
1242 | I915_WRITE(DP_A, intel_dp->DP); |
||
2330 | Serge | 1243 | POSTING_READ(DP_A); |
1244 | udelay(200); |
||
1245 | } |
||
2327 | Serge | 1246 | |
3031 | serge | 1247 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2330 | Serge | 1248 | { |
3243 | Serge | 1249 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1250 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
||
1251 | struct drm_device *dev = crtc->dev; |
||
2330 | Serge | 1252 | struct drm_i915_private *dev_priv = dev->dev_private; |
1253 | u32 dpa_ctl; |
||
2327 | Serge | 1254 | |
3031 | serge | 1255 | assert_pipe_disabled(dev_priv, |
1256 | to_intel_crtc(crtc)->pipe); |
||
1257 | |||
2330 | Serge | 1258 | dpa_ctl = I915_READ(DP_A); |
3031 | serge | 1259 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1260 | "dp pll off, should be on\n"); |
||
1261 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
||
1262 | |||
1263 | /* We can't rely on the value tracked for the DP register in |
||
1264 | * intel_dp->DP because link_down must not change that (otherwise link |
||
1265 | * re-training will fail. */ |
||
2330 | Serge | 1266 | dpa_ctl &= ~DP_PLL_ENABLE; |
1267 | I915_WRITE(DP_A, dpa_ctl); |
||
1268 | POSTING_READ(DP_A); |
||
1269 | udelay(200); |
||
1270 | } |
||
2327 | Serge | 1271 | |
2330 | Serge | 1272 | /* If the sink supports it, try to set the power state appropriately */ |
3243 | Serge | 1273 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2330 | Serge | 1274 | { |
1275 | int ret, i; |
||
2327 | Serge | 1276 | |
2330 | Serge | 1277 | /* Should have a valid DPCD by this point */ |
1278 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
||
1279 | return; |
||
2327 | Serge | 1280 | |
2330 | Serge | 1281 | if (mode != DRM_MODE_DPMS_ON) { |
1282 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
||
1283 | DP_SET_POWER_D3); |
||
1284 | if (ret != 1) |
||
1285 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
||
1286 | } else { |
||
1287 | /* |
||
1288 | * When turning on, we need to retry for 1ms to give the sink |
||
1289 | * time to wake up. |
||
1290 | */ |
||
1291 | for (i = 0; i < 3; i++) { |
||
1292 | ret = intel_dp_aux_native_write_1(intel_dp, |
||
1293 | DP_SET_POWER, |
||
1294 | DP_SET_POWER_D0); |
||
1295 | if (ret == 1) |
||
1296 | break; |
||
1297 | msleep(1); |
||
1298 | } |
||
1299 | } |
||
1300 | } |
||
2327 | Serge | 1301 | |
3031 | serge | 1302 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1303 | enum pipe *pipe) |
||
2330 | Serge | 1304 | { |
3031 | serge | 1305 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1306 | struct drm_device *dev = encoder->base.dev; |
||
1307 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1308 | u32 tmp = I915_READ(intel_dp->output_reg); |
||
2327 | Serge | 1309 | |
3031 | serge | 1310 | if (!(tmp & DP_PORT_EN)) |
1311 | return false; |
||
2342 | Serge | 1312 | |
3031 | serge | 1313 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { |
1314 | *pipe = PORT_TO_PIPE_CPT(tmp); |
||
1315 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
||
1316 | *pipe = PORT_TO_PIPE(tmp); |
||
1317 | } else { |
||
1318 | u32 trans_sel; |
||
1319 | u32 trans_dp; |
||
1320 | int i; |
||
2327 | Serge | 1321 | |
3031 | serge | 1322 | switch (intel_dp->output_reg) { |
1323 | case PCH_DP_B: |
||
1324 | trans_sel = TRANS_DP_PORT_SEL_B; |
||
1325 | break; |
||
1326 | case PCH_DP_C: |
||
1327 | trans_sel = TRANS_DP_PORT_SEL_C; |
||
1328 | break; |
||
1329 | case PCH_DP_D: |
||
1330 | trans_sel = TRANS_DP_PORT_SEL_D; |
||
1331 | break; |
||
1332 | default: |
||
1333 | return true; |
||
1334 | } |
||
1335 | |||
1336 | for_each_pipe(i) { |
||
1337 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
||
1338 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
||
1339 | *pipe = i; |
||
1340 | return true; |
||
1341 | } |
||
1342 | } |
||
3243 | Serge | 1343 | |
1344 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
||
1345 | intel_dp->output_reg); |
||
3031 | serge | 1346 | } |
1347 | |||
1348 | return true; |
||
2330 | Serge | 1349 | } |
2327 | Serge | 1350 | |
3031 | serge | 1351 | static void intel_disable_dp(struct intel_encoder *encoder) |
2330 | Serge | 1352 | { |
3031 | serge | 1353 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2327 | Serge | 1354 | |
3031 | serge | 1355 | /* Make sure the panel is off before trying to change the mode. But also |
1356 | * ensure that we have vdd while we switch off the panel. */ |
||
2330 | Serge | 1357 | ironlake_edp_panel_vdd_on(intel_dp); |
3031 | serge | 1358 | ironlake_edp_backlight_off(intel_dp); |
2342 | Serge | 1359 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
3031 | serge | 1360 | ironlake_edp_panel_off(intel_dp); |
2330 | Serge | 1361 | |
3031 | serge | 1362 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
1363 | if (!is_cpu_edp(intel_dp)) |
||
1364 | intel_dp_link_down(intel_dp); |
||
1365 | } |
||
2330 | Serge | 1366 | |
3031 | serge | 1367 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
1368 | { |
||
1369 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
1370 | |||
1371 | if (is_cpu_edp(intel_dp)) { |
||
1372 | intel_dp_link_down(intel_dp); |
||
1373 | ironlake_edp_pll_off(intel_dp); |
||
1374 | } |
||
2330 | Serge | 1375 | } |
1376 | |||
3031 | serge | 1377 | static void intel_enable_dp(struct intel_encoder *encoder) |
2330 | Serge | 1378 | { |
3031 | serge | 1379 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1380 | struct drm_device *dev = encoder->base.dev; |
||
2330 | Serge | 1381 | struct drm_i915_private *dev_priv = dev->dev_private; |
1382 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
||
1383 | |||
3031 | serge | 1384 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1385 | return; |
||
2342 | Serge | 1386 | |
1387 | ironlake_edp_panel_vdd_on(intel_dp); |
||
3031 | serge | 1388 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2330 | Serge | 1389 | intel_dp_start_link_train(intel_dp); |
1390 | ironlake_edp_panel_on(intel_dp); |
||
2342 | Serge | 1391 | ironlake_edp_panel_vdd_off(intel_dp, true); |
2330 | Serge | 1392 | intel_dp_complete_link_train(intel_dp); |
2342 | Serge | 1393 | ironlake_edp_backlight_on(intel_dp); |
2330 | Serge | 1394 | } |
1395 | |||
3031 | serge | 1396 | static void intel_pre_enable_dp(struct intel_encoder *encoder) |
1397 | { |
||
1398 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
1399 | |||
1400 | if (is_cpu_edp(intel_dp)) |
||
1401 | ironlake_edp_pll_on(intel_dp); |
||
1402 | } |
||
1403 | |||
2330 | Serge | 1404 | /* |
1405 | * Native read with retry for link status and receiver capability reads for |
||
1406 | * cases where the sink may still be asleep. |
||
1407 | */ |
||
1408 | static bool |
||
1409 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
||
1410 | uint8_t *recv, int recv_bytes) |
||
1411 | { |
||
1412 | int ret, i; |
||
1413 | |||
1414 | /* |
||
1415 | * Sinks are *supposed* to come up within 1ms from an off state, |
||
1416 | * but we're also supposed to retry 3 times per the spec. |
||
1417 | */ |
||
1418 | for (i = 0; i < 3; i++) { |
||
1419 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
||
1420 | recv_bytes); |
||
1421 | if (ret == recv_bytes) |
||
1422 | return true; |
||
1423 | msleep(1); |
||
1424 | } |
||
1425 | |||
1426 | return false; |
||
1427 | } |
||
1428 | |||
1429 | /* |
||
1430 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
||
1431 | * link status information |
||
1432 | */ |
||
1433 | static bool |
||
2342 | Serge | 1434 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2330 | Serge | 1435 | { |
1436 | return intel_dp_aux_native_read_retry(intel_dp, |
||
1437 | DP_LANE0_1_STATUS, |
||
2342 | Serge | 1438 | link_status, |
2330 | Serge | 1439 | DP_LINK_STATUS_SIZE); |
1440 | } |
||
1441 | |||
1442 | #if 0 |
||
1443 | static char *voltage_names[] = { |
||
1444 | "0.4V", "0.6V", "0.8V", "1.2V" |
||
1445 | }; |
||
1446 | static char *pre_emph_names[] = { |
||
1447 | "0dB", "3.5dB", "6dB", "9.5dB" |
||
1448 | }; |
||
1449 | static char *link_train_names[] = { |
||
1450 | "pattern 1", "pattern 2", "idle", "off" |
||
1451 | }; |
||
1452 | #endif |
||
1453 | |||
1454 | /* |
||
1455 | * These are source-specific values; current Intel hardware supports |
||
1456 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
||
1457 | */ |
||
1458 | |||
1459 | static uint8_t |
||
2342 | Serge | 1460 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
2330 | Serge | 1461 | { |
3243 | Serge | 1462 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 1463 | |
1464 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) |
||
1465 | return DP_TRAIN_VOLTAGE_SWING_800; |
||
1466 | else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
||
1467 | return DP_TRAIN_VOLTAGE_SWING_1200; |
||
1468 | else |
||
1469 | return DP_TRAIN_VOLTAGE_SWING_800; |
||
1470 | } |
||
1471 | |||
1472 | static uint8_t |
||
1473 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
||
1474 | { |
||
3243 | Serge | 1475 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 1476 | |
3243 | Serge | 1477 | if (IS_HASWELL(dev)) { |
2342 | Serge | 1478 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1479 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
3243 | Serge | 1480 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
1481 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2342 | Serge | 1482 | return DP_TRAIN_PRE_EMPHASIS_6; |
3243 | Serge | 1483 | case DP_TRAIN_VOLTAGE_SWING_800: |
1484 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
1485 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
1486 | default: |
||
1487 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
1488 | } |
||
1489 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
||
1490 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
1491 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
1492 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
2342 | Serge | 1493 | case DP_TRAIN_VOLTAGE_SWING_600: |
1494 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
1495 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
1496 | default: |
||
1497 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
1498 | } |
||
1499 | } else { |
||
2330 | Serge | 1500 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1501 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
1502 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
1503 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
1504 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
1505 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
1506 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
1507 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
1508 | default: |
||
1509 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
1510 | } |
||
2342 | Serge | 1511 | } |
2330 | Serge | 1512 | } |
1513 | |||
1514 | static void |
||
2342 | Serge | 1515 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2330 | Serge | 1516 | { |
1517 | uint8_t v = 0; |
||
1518 | uint8_t p = 0; |
||
1519 | int lane; |
||
2342 | Serge | 1520 | uint8_t voltage_max; |
1521 | uint8_t preemph_max; |
||
2330 | Serge | 1522 | |
1523 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
||
3243 | Serge | 1524 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
1525 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
||
2330 | Serge | 1526 | |
1527 | if (this_v > v) |
||
1528 | v = this_v; |
||
1529 | if (this_p > p) |
||
1530 | p = this_p; |
||
1531 | } |
||
1532 | |||
2342 | Serge | 1533 | voltage_max = intel_dp_voltage_max(intel_dp); |
1534 | if (v >= voltage_max) |
||
1535 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
||
2330 | Serge | 1536 | |
2342 | Serge | 1537 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
1538 | if (p >= preemph_max) |
||
1539 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
||
2330 | Serge | 1540 | |
1541 | for (lane = 0; lane < 4; lane++) |
||
1542 | intel_dp->train_set[lane] = v | p; |
||
1543 | } |
||
1544 | |||
1545 | static uint32_t |
||
2342 | Serge | 1546 | intel_dp_signal_levels(uint8_t train_set) |
2330 | Serge | 1547 | { |
1548 | uint32_t signal_levels = 0; |
||
1549 | |||
1550 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
1551 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
1552 | default: |
||
1553 | signal_levels |= DP_VOLTAGE_0_4; |
||
1554 | break; |
||
1555 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
1556 | signal_levels |= DP_VOLTAGE_0_6; |
||
1557 | break; |
||
1558 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
1559 | signal_levels |= DP_VOLTAGE_0_8; |
||
1560 | break; |
||
1561 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
1562 | signal_levels |= DP_VOLTAGE_1_2; |
||
1563 | break; |
||
1564 | } |
||
1565 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
||
1566 | case DP_TRAIN_PRE_EMPHASIS_0: |
||
1567 | default: |
||
1568 | signal_levels |= DP_PRE_EMPHASIS_0; |
||
1569 | break; |
||
1570 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1571 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
||
1572 | break; |
||
1573 | case DP_TRAIN_PRE_EMPHASIS_6: |
||
1574 | signal_levels |= DP_PRE_EMPHASIS_6; |
||
1575 | break; |
||
1576 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
||
1577 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
||
1578 | break; |
||
1579 | } |
||
1580 | return signal_levels; |
||
1581 | } |
||
1582 | |||
1583 | /* Gen6's DP voltage swing and pre-emphasis control */ |
||
1584 | static uint32_t |
||
1585 | intel_gen6_edp_signal_levels(uint8_t train_set) |
||
1586 | { |
||
1587 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
||
1588 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
1589 | switch (signal_levels) { |
||
1590 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1591 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1592 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
||
1593 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1594 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
||
1595 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1596 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1597 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
||
1598 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1599 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1600 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
||
1601 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1602 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1603 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
||
1604 | default: |
||
1605 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
1606 | "0x%x\n", signal_levels); |
||
1607 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
||
1608 | } |
||
1609 | } |
||
1610 | |||
2342 | Serge | 1611 | /* Gen7's DP voltage swing and pre-emphasis control */ |
1612 | static uint32_t |
||
1613 | intel_gen7_edp_signal_levels(uint8_t train_set) |
||
1614 | { |
||
1615 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
||
1616 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
1617 | switch (signal_levels) { |
||
1618 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1619 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
||
1620 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1621 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
||
1622 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1623 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
||
1624 | |||
1625 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1626 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
||
1627 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1628 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
||
1629 | |||
1630 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1631 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
||
1632 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1633 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
||
1634 | |||
1635 | default: |
||
1636 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
1637 | "0x%x\n", signal_levels); |
||
1638 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
||
1639 | } |
||
1640 | } |
||
1641 | |||
3243 | Serge | 1642 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
1643 | static uint32_t |
||
1644 | intel_dp_signal_levels_hsw(uint8_t train_set) |
||
2330 | Serge | 1645 | { |
3243 | Serge | 1646 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1647 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
1648 | switch (signal_levels) { |
||
1649 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1650 | return DDI_BUF_EMP_400MV_0DB_HSW; |
||
1651 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1652 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
||
1653 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1654 | return DDI_BUF_EMP_400MV_6DB_HSW; |
||
1655 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
||
1656 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
||
2330 | Serge | 1657 | |
3243 | Serge | 1658 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1659 | return DDI_BUF_EMP_600MV_0DB_HSW; |
||
1660 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1661 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
||
1662 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1663 | return DDI_BUF_EMP_600MV_6DB_HSW; |
||
2330 | Serge | 1664 | |
3243 | Serge | 1665 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
1666 | return DDI_BUF_EMP_800MV_0DB_HSW; |
||
1667 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1668 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
||
1669 | default: |
||
1670 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
1671 | "0x%x\n", signal_levels); |
||
1672 | return DDI_BUF_EMP_400MV_0DB_HSW; |
||
2330 | Serge | 1673 | } |
1674 | } |
||
1675 | |||
1676 | static bool |
||
1677 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
||
1678 | uint32_t dp_reg_value, |
||
1679 | uint8_t dp_train_pat) |
||
1680 | { |
||
3243 | Serge | 1681 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1682 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 1683 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 1684 | enum port port = intel_dig_port->port; |
2330 | Serge | 1685 | int ret; |
3243 | Serge | 1686 | uint32_t temp; |
2330 | Serge | 1687 | |
3243 | Serge | 1688 | if (IS_HASWELL(dev)) { |
1689 | temp = I915_READ(DP_TP_CTL(port)); |
||
1690 | |||
1691 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
||
1692 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
||
1693 | else |
||
1694 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
||
1695 | |||
1696 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
||
1697 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
1698 | case DP_TRAINING_PATTERN_DISABLE: |
||
1699 | temp |= DP_TP_CTL_LINK_TRAIN_IDLE; |
||
1700 | I915_WRITE(DP_TP_CTL(port), temp); |
||
1701 | |||
1702 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & |
||
1703 | DP_TP_STATUS_IDLE_DONE), 1)) |
||
1704 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
||
1705 | |||
1706 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
||
1707 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
||
1708 | |||
1709 | break; |
||
1710 | case DP_TRAINING_PATTERN_1: |
||
1711 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
||
1712 | break; |
||
1713 | case DP_TRAINING_PATTERN_2: |
||
1714 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
||
1715 | break; |
||
1716 | case DP_TRAINING_PATTERN_3: |
||
1717 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
||
1718 | break; |
||
1719 | } |
||
1720 | I915_WRITE(DP_TP_CTL(port), temp); |
||
1721 | |||
1722 | } else if (HAS_PCH_CPT(dev) && |
||
1723 | (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
||
3031 | serge | 1724 | dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; |
1725 | |||
1726 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
1727 | case DP_TRAINING_PATTERN_DISABLE: |
||
1728 | dp_reg_value |= DP_LINK_TRAIN_OFF_CPT; |
||
1729 | break; |
||
1730 | case DP_TRAINING_PATTERN_1: |
||
1731 | dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT; |
||
1732 | break; |
||
1733 | case DP_TRAINING_PATTERN_2: |
||
1734 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; |
||
1735 | break; |
||
1736 | case DP_TRAINING_PATTERN_3: |
||
1737 | DRM_ERROR("DP training pattern 3 not supported\n"); |
||
1738 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; |
||
1739 | break; |
||
1740 | } |
||
1741 | |||
1742 | } else { |
||
1743 | dp_reg_value &= ~DP_LINK_TRAIN_MASK; |
||
1744 | |||
1745 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
1746 | case DP_TRAINING_PATTERN_DISABLE: |
||
1747 | dp_reg_value |= DP_LINK_TRAIN_OFF; |
||
1748 | break; |
||
1749 | case DP_TRAINING_PATTERN_1: |
||
1750 | dp_reg_value |= DP_LINK_TRAIN_PAT_1; |
||
1751 | break; |
||
1752 | case DP_TRAINING_PATTERN_2: |
||
1753 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; |
||
1754 | break; |
||
1755 | case DP_TRAINING_PATTERN_3: |
||
1756 | DRM_ERROR("DP training pattern 3 not supported\n"); |
||
1757 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; |
||
1758 | break; |
||
1759 | } |
||
1760 | } |
||
1761 | |||
2330 | Serge | 1762 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1763 | POSTING_READ(intel_dp->output_reg); |
||
1764 | |||
1765 | intel_dp_aux_native_write_1(intel_dp, |
||
1766 | DP_TRAINING_PATTERN_SET, |
||
1767 | dp_train_pat); |
||
1768 | |||
3031 | serge | 1769 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != |
1770 | DP_TRAINING_PATTERN_DISABLE) { |
||
2330 | Serge | 1771 | ret = intel_dp_aux_native_write(intel_dp, |
1772 | DP_TRAINING_LANE0_SET, |
||
2342 | Serge | 1773 | intel_dp->train_set, |
1774 | intel_dp->lane_count); |
||
1775 | if (ret != intel_dp->lane_count) |
||
2330 | Serge | 1776 | return false; |
3031 | serge | 1777 | } |
2330 | Serge | 1778 | |
1779 | return true; |
||
1780 | } |
||
1781 | |||
1782 | /* Enable corresponding port and start training pattern 1 */ |
||
3243 | Serge | 1783 | void |
2330 | Serge | 1784 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
1785 | { |
||
3243 | Serge | 1786 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
1787 | struct drm_device *dev = encoder->dev; |
||
2330 | Serge | 1788 | int i; |
1789 | uint8_t voltage; |
||
1790 | bool clock_recovery = false; |
||
2342 | Serge | 1791 | int voltage_tries, loop_tries; |
2330 | Serge | 1792 | uint32_t DP = intel_dp->DP; |
1793 | |||
3243 | Serge | 1794 | if (IS_HASWELL(dev)) |
1795 | intel_ddi_prepare_link_retrain(encoder); |
||
1796 | |||
2330 | Serge | 1797 | /* Write the link configuration data */ |
1798 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
||
1799 | intel_dp->link_configuration, |
||
1800 | DP_LINK_CONFIGURATION_SIZE); |
||
1801 | |||
1802 | DP |= DP_PORT_EN; |
||
2342 | Serge | 1803 | |
2330 | Serge | 1804 | memset(intel_dp->train_set, 0, 4); |
1805 | voltage = 0xff; |
||
2342 | Serge | 1806 | voltage_tries = 0; |
1807 | loop_tries = 0; |
||
2330 | Serge | 1808 | clock_recovery = false; |
1809 | for (;;) { |
||
1810 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
||
2342 | Serge | 1811 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
2330 | Serge | 1812 | uint32_t signal_levels; |
2342 | Serge | 1813 | |
3243 | Serge | 1814 | if (IS_HASWELL(dev)) { |
1815 | signal_levels = intel_dp_signal_levels_hsw( |
||
1816 | intel_dp->train_set[0]); |
||
1817 | DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; |
||
1818 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
||
2342 | Serge | 1819 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
1820 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
||
1821 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
||
2330 | Serge | 1822 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
1823 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
||
1824 | } else { |
||
2342 | Serge | 1825 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
2330 | Serge | 1826 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1827 | } |
||
3243 | Serge | 1828 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", |
1829 | signal_levels); |
||
2330 | Serge | 1830 | |
3243 | Serge | 1831 | /* Set training pattern 1 */ |
3031 | serge | 1832 | if (!intel_dp_set_link_train(intel_dp, DP, |
2330 | Serge | 1833 | DP_TRAINING_PATTERN_1 | |
1834 | DP_LINK_SCRAMBLING_DISABLE)) |
||
1835 | break; |
||
1836 | |||
3243 | Serge | 1837 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
2342 | Serge | 1838 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1839 | DRM_ERROR("failed to get link status\n"); |
||
2330 | Serge | 1840 | break; |
2342 | Serge | 1841 | } |
2330 | Serge | 1842 | |
3243 | Serge | 1843 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2342 | Serge | 1844 | DRM_DEBUG_KMS("clock recovery OK\n"); |
2330 | Serge | 1845 | clock_recovery = true; |
1846 | break; |
||
1847 | } |
||
1848 | |||
1849 | /* Check to see if we've tried the max voltage */ |
||
1850 | for (i = 0; i < intel_dp->lane_count; i++) |
||
1851 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
||
1852 | break; |
||
3031 | serge | 1853 | if (i == intel_dp->lane_count && voltage_tries == 5) { |
2342 | Serge | 1854 | ++loop_tries; |
1855 | if (loop_tries == 5) { |
||
1856 | DRM_DEBUG_KMS("too many full retries, give up\n"); |
||
2330 | Serge | 1857 | break; |
2342 | Serge | 1858 | } |
1859 | memset(intel_dp->train_set, 0, 4); |
||
1860 | voltage_tries = 0; |
||
1861 | continue; |
||
1862 | } |
||
2330 | Serge | 1863 | |
1864 | /* Check to see if we've tried the same voltage 5 times */ |
||
1865 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
||
2342 | Serge | 1866 | ++voltage_tries; |
1867 | if (voltage_tries == 5) { |
||
1868 | DRM_DEBUG_KMS("too many voltage retries, give up\n"); |
||
2330 | Serge | 1869 | break; |
2342 | Serge | 1870 | } |
2330 | Serge | 1871 | } else |
2342 | Serge | 1872 | voltage_tries = 0; |
2330 | Serge | 1873 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
1874 | |||
1875 | /* Compute new intel_dp->train_set as requested by target */ |
||
2342 | Serge | 1876 | intel_get_adjust_train(intel_dp, link_status); |
2330 | Serge | 1877 | } |
1878 | |||
1879 | intel_dp->DP = DP; |
||
1880 | } |
||
1881 | |||
3243 | Serge | 1882 | void |
2330 | Serge | 1883 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
1884 | { |
||
3243 | Serge | 1885 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1886 | bool channel_eq = false; |
1887 | int tries, cr_tries; |
||
1888 | uint32_t DP = intel_dp->DP; |
||
1889 | |||
1890 | /* channel equalization */ |
||
1891 | tries = 0; |
||
1892 | cr_tries = 0; |
||
1893 | channel_eq = false; |
||
1894 | for (;;) { |
||
1895 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
||
1896 | uint32_t signal_levels; |
||
2342 | Serge | 1897 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
2330 | Serge | 1898 | |
1899 | if (cr_tries > 5) { |
||
1900 | DRM_ERROR("failed to train DP, aborting\n"); |
||
1901 | intel_dp_link_down(intel_dp); |
||
1902 | break; |
||
1903 | } |
||
1904 | |||
3243 | Serge | 1905 | if (IS_HASWELL(dev)) { |
1906 | signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]); |
||
1907 | DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; |
||
1908 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
||
2342 | Serge | 1909 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
1910 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
||
1911 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
||
2330 | Serge | 1912 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
1913 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
||
1914 | } else { |
||
2342 | Serge | 1915 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
2330 | Serge | 1916 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1917 | } |
||
1918 | |||
1919 | /* channel eq pattern */ |
||
3031 | serge | 1920 | if (!intel_dp_set_link_train(intel_dp, DP, |
2330 | Serge | 1921 | DP_TRAINING_PATTERN_2 | |
1922 | DP_LINK_SCRAMBLING_DISABLE)) |
||
1923 | break; |
||
1924 | |||
3243 | Serge | 1925 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
2342 | Serge | 1926 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
2330 | Serge | 1927 | break; |
1928 | |||
1929 | /* Make sure clock is still ok */ |
||
3243 | Serge | 1930 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 1931 | intel_dp_start_link_train(intel_dp); |
1932 | cr_tries++; |
||
1933 | continue; |
||
1934 | } |
||
1935 | |||
3243 | Serge | 1936 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 1937 | channel_eq = true; |
1938 | break; |
||
1939 | } |
||
1940 | |||
1941 | /* Try 5 times, then try clock recovery if that fails */ |
||
1942 | if (tries > 5) { |
||
1943 | intel_dp_link_down(intel_dp); |
||
1944 | intel_dp_start_link_train(intel_dp); |
||
1945 | tries = 0; |
||
1946 | cr_tries++; |
||
1947 | continue; |
||
1948 | } |
||
1949 | |||
1950 | /* Compute new intel_dp->train_set as requested by target */ |
||
2342 | Serge | 1951 | intel_get_adjust_train(intel_dp, link_status); |
2330 | Serge | 1952 | ++tries; |
1953 | } |
||
1954 | |||
3243 | Serge | 1955 | if (channel_eq) |
1956 | DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n"); |
||
1957 | |||
3031 | serge | 1958 | intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); |
2330 | Serge | 1959 | } |
1960 | |||
1961 | static void |
||
1962 | intel_dp_link_down(struct intel_dp *intel_dp) |
||
1963 | { |
||
3243 | Serge | 1964 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1965 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 1966 | struct drm_i915_private *dev_priv = dev->dev_private; |
1967 | uint32_t DP = intel_dp->DP; |
||
1968 | |||
3243 | Serge | 1969 | /* |
1970 | * DDI code has a strict mode set sequence and we should try to respect |
||
1971 | * it, otherwise we might hang the machine in many different ways. So we |
||
1972 | * really should be disabling the port only on a complete crtc_disable |
||
1973 | * sequence. This function is just called under two conditions on DDI |
||
1974 | * code: |
||
1975 | * - Link train failed while doing crtc_enable, and on this case we |
||
1976 | * really should respect the mode set sequence and wait for a |
||
1977 | * crtc_disable. |
||
1978 | * - Someone turned the monitor off and intel_dp_check_link_status |
||
1979 | * called us. We don't need to disable the whole port on this case, so |
||
1980 | * when someone turns the monitor on again, |
||
1981 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
||
1982 | * train. |
||
1983 | */ |
||
1984 | if (IS_HASWELL(dev)) |
||
1985 | return; |
||
1986 | |||
3031 | serge | 1987 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
2330 | Serge | 1988 | return; |
1989 | |||
1990 | DRM_DEBUG_KMS("\n"); |
||
1991 | |||
2342 | Serge | 1992 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
2330 | Serge | 1993 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1994 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
||
1995 | } else { |
||
1996 | DP &= ~DP_LINK_TRAIN_MASK; |
||
1997 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
||
1998 | } |
||
1999 | POSTING_READ(intel_dp->output_reg); |
||
2000 | |||
2001 | msleep(17); |
||
2002 | |||
3031 | serge | 2003 | if (HAS_PCH_IBX(dev) && |
2330 | Serge | 2004 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
3243 | Serge | 2005 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2330 | Serge | 2006 | |
2007 | /* Hardware workaround: leaving our transcoder select |
||
2008 | * set to transcoder B while it's off will prevent the |
||
2009 | * corresponding HDMI output on transcoder A. |
||
2010 | * |
||
2011 | * Combine this with another hardware workaround: |
||
2012 | * transcoder select bit can only be cleared while the |
||
2013 | * port is enabled. |
||
2014 | */ |
||
2015 | DP &= ~DP_PIPEB_SELECT; |
||
2016 | I915_WRITE(intel_dp->output_reg, DP); |
||
2017 | |||
2018 | /* Changes to enable or select take place the vblank |
||
2019 | * after being written. |
||
2020 | */ |
||
2021 | if (crtc == NULL) { |
||
2022 | /* We can arrive here never having been attached |
||
2023 | * to a CRTC, for instance, due to inheriting |
||
2024 | * random state from the BIOS. |
||
2025 | * |
||
2026 | * If the pipe is not running, play safe and |
||
2027 | * wait for the clocks to stabilise before |
||
2028 | * continuing. |
||
2029 | */ |
||
2030 | POSTING_READ(intel_dp->output_reg); |
||
2031 | msleep(50); |
||
2032 | } else |
||
2033 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
||
2034 | } |
||
2035 | |||
2342 | Serge | 2036 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
2330 | Serge | 2037 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
2038 | POSTING_READ(intel_dp->output_reg); |
||
2342 | Serge | 2039 | msleep(intel_dp->panel_power_down_delay); |
2330 | Serge | 2040 | } |
2041 | |||
2042 | static bool |
||
2043 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
||
2044 | { |
||
2045 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
||
3031 | serge | 2046 | sizeof(intel_dp->dpcd)) == 0) |
2047 | return false; /* aux transfer failed */ |
||
2048 | |||
2049 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
||
2050 | return false; /* DPCD not present */ |
||
2051 | |||
2052 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
||
2053 | DP_DWN_STRM_PORT_PRESENT)) |
||
2054 | return true; /* native DP sink */ |
||
2055 | |||
2056 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
||
2057 | return true; /* no per-port downstream info */ |
||
2058 | |||
2059 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, |
||
2060 | intel_dp->downstream_ports, |
||
2061 | DP_MAX_DOWNSTREAM_PORTS) == 0) |
||
2062 | return false; /* downstream port status fetch failed */ |
||
2063 | |||
2330 | Serge | 2064 | return true; |
3031 | serge | 2065 | } |
2330 | Serge | 2066 | |
3031 | serge | 2067 | static void |
2068 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
||
2069 | { |
||
2070 | u8 buf[3]; |
||
2071 | |||
2072 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
||
2073 | return; |
||
2074 | |||
2075 | ironlake_edp_panel_vdd_on(intel_dp); |
||
2076 | |||
2077 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
||
2078 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
||
2079 | buf[0], buf[1], buf[2]); |
||
2080 | |||
2081 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) |
||
2082 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
||
2083 | buf[0], buf[1], buf[2]); |
||
2084 | |||
2085 | ironlake_edp_panel_vdd_off(intel_dp, false); |
||
2330 | Serge | 2086 | } |
2087 | |||
2342 | Serge | 2088 | static bool |
2089 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
||
2090 | { |
||
2091 | int ret; |
||
2092 | |||
2093 | ret = intel_dp_aux_native_read_retry(intel_dp, |
||
2094 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
||
2095 | sink_irq_vector, 1); |
||
2096 | if (!ret) |
||
2097 | return false; |
||
2098 | |||
2099 | return true; |
||
2100 | } |
||
2101 | |||
2102 | static void |
||
2103 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
||
2104 | { |
||
2105 | /* NAK by default */ |
||
3243 | Serge | 2106 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
2342 | Serge | 2107 | } |
2108 | |||
2330 | Serge | 2109 | /* |
2110 | * According to DP spec |
||
2111 | * 5.1.2: |
||
2112 | * 1. Read DPCD |
||
2113 | * 2. Configure link according to Receiver Capabilities |
||
2114 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
||
2115 | * 4. Check link status on receipt of hot-plug interrupt |
||
2116 | */ |
||
2117 | |||
3243 | Serge | 2118 | void |
2330 | Serge | 2119 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
2120 | { |
||
3243 | Serge | 2121 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
2342 | Serge | 2122 | u8 sink_irq_vector; |
2123 | u8 link_status[DP_LINK_STATUS_SIZE]; |
||
2124 | |||
3243 | Serge | 2125 | if (!intel_encoder->connectors_active) |
2330 | Serge | 2126 | return; |
2127 | |||
3243 | Serge | 2128 | if (WARN_ON(!intel_encoder->base.crtc)) |
2330 | Serge | 2129 | return; |
2130 | |||
2131 | /* Try to read receiver status if the link appears to be up */ |
||
2342 | Serge | 2132 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2330 | Serge | 2133 | intel_dp_link_down(intel_dp); |
2134 | return; |
||
2135 | } |
||
2136 | |||
2137 | /* Now read the DPCD to see if it's actually running */ |
||
2138 | if (!intel_dp_get_dpcd(intel_dp)) { |
||
2139 | intel_dp_link_down(intel_dp); |
||
2140 | return; |
||
2141 | } |
||
2142 | |||
2342 | Serge | 2143 | /* Try to read the source of the interrupt */ |
2144 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
||
2145 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
||
2146 | /* Clear interrupt source */ |
||
2147 | intel_dp_aux_native_write_1(intel_dp, |
||
2148 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
||
2149 | sink_irq_vector); |
||
2150 | |||
2151 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
||
2152 | intel_dp_handle_test_request(intel_dp); |
||
2153 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
||
2154 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
||
2155 | } |
||
2156 | |||
3243 | Serge | 2157 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 2158 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
3243 | Serge | 2159 | drm_get_encoder_name(&intel_encoder->base)); |
2330 | Serge | 2160 | intel_dp_start_link_train(intel_dp); |
2161 | intel_dp_complete_link_train(intel_dp); |
||
2162 | } |
||
2163 | } |
||
2164 | |||
3031 | serge | 2165 | /* XXX this is probably wrong for multiple downstream ports */ |
2330 | Serge | 2166 | static enum drm_connector_status |
2167 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
||
2168 | { |
||
3031 | serge | 2169 | uint8_t *dpcd = intel_dp->dpcd; |
2170 | bool hpd; |
||
2171 | uint8_t type; |
||
2172 | |||
2173 | if (!intel_dp_get_dpcd(intel_dp)) |
||
2174 | return connector_status_disconnected; |
||
2175 | |||
2176 | /* if there's no downstream port, we're done */ |
||
2177 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
||
2330 | Serge | 2178 | return connector_status_connected; |
3031 | serge | 2179 | |
2180 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
||
2181 | hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD); |
||
2182 | if (hpd) { |
||
2183 | uint8_t reg; |
||
2184 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
||
2185 | ®, 1)) |
||
2186 | return connector_status_unknown; |
||
2187 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
||
2188 | : connector_status_disconnected; |
||
2189 | } |
||
2190 | |||
2191 | /* If no HPD, poke DDC gently */ |
||
2192 | if (drm_probe_ddc(&intel_dp->adapter)) |
||
2193 | return connector_status_connected; |
||
2194 | |||
2195 | /* Well we tried, say unknown for unreliable port types */ |
||
2196 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
||
2197 | if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID) |
||
2198 | return connector_status_unknown; |
||
2199 | |||
2200 | /* Anything else is out of spec, warn and ignore */ |
||
2201 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
||
2330 | Serge | 2202 | return connector_status_disconnected; |
2203 | } |
||
2204 | |||
2205 | static enum drm_connector_status |
||
2206 | ironlake_dp_detect(struct intel_dp *intel_dp) |
||
2207 | { |
||
3243 | Serge | 2208 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 2209 | enum drm_connector_status status; |
2210 | |||
2211 | /* Can't disconnect eDP, but you can close the lid... */ |
||
2212 | if (is_edp(intel_dp)) { |
||
3243 | Serge | 2213 | status = intel_panel_detect(dev); |
2330 | Serge | 2214 | if (status == connector_status_unknown) |
2215 | status = connector_status_connected; |
||
2216 | return status; |
||
2217 | } |
||
2218 | |||
2219 | return intel_dp_detect_dpcd(intel_dp); |
||
2220 | } |
||
2221 | |||
2222 | static enum drm_connector_status |
||
2223 | g4x_dp_detect(struct intel_dp *intel_dp) |
||
2224 | { |
||
3243 | Serge | 2225 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 2226 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 2227 | uint32_t bit; |
2330 | Serge | 2228 | |
2229 | switch (intel_dp->output_reg) { |
||
2230 | case DP_B: |
||
3031 | serge | 2231 | bit = DPB_HOTPLUG_LIVE_STATUS; |
2330 | Serge | 2232 | break; |
2233 | case DP_C: |
||
3031 | serge | 2234 | bit = DPC_HOTPLUG_LIVE_STATUS; |
2330 | Serge | 2235 | break; |
2236 | case DP_D: |
||
3031 | serge | 2237 | bit = DPD_HOTPLUG_LIVE_STATUS; |
2330 | Serge | 2238 | break; |
2239 | default: |
||
2240 | return connector_status_unknown; |
||
2241 | } |
||
2242 | |||
3031 | serge | 2243 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
2330 | Serge | 2244 | return connector_status_disconnected; |
2245 | |||
2246 | return intel_dp_detect_dpcd(intel_dp); |
||
2247 | } |
||
2248 | |||
2342 | Serge | 2249 | static struct edid * |
2250 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
||
2251 | { |
||
3243 | Serge | 2252 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2253 | |||
2254 | /* use cached edid if we have one */ |
||
2255 | if (intel_connector->edid) { |
||
2342 | Serge | 2256 | struct edid *edid; |
3031 | serge | 2257 | int size; |
2342 | Serge | 2258 | |
3243 | Serge | 2259 | /* invalid edid */ |
2260 | if (IS_ERR(intel_connector->edid)) |
||
3031 | serge | 2261 | return NULL; |
2262 | |||
3243 | Serge | 2263 | size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; |
3031 | serge | 2264 | edid = kmalloc(size, GFP_KERNEL); |
2265 | if (!edid) |
||
2266 | return NULL; |
||
2267 | |||
3243 | Serge | 2268 | memcpy(edid, intel_connector->edid, size); |
3031 | serge | 2269 | return edid; |
2270 | } |
||
2271 | |||
3243 | Serge | 2272 | return drm_get_edid(connector, adapter); |
2342 | Serge | 2273 | } |
2274 | |||
2275 | static int |
||
2276 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
||
2277 | { |
||
3243 | Serge | 2278 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2342 | Serge | 2279 | |
3243 | Serge | 2280 | /* use cached edid if we have one */ |
2281 | if (intel_connector->edid) { |
||
2282 | /* invalid edid */ |
||
2283 | if (IS_ERR(intel_connector->edid)) |
||
2284 | return 0; |
||
2285 | |||
2286 | return intel_connector_update_modes(connector, |
||
2287 | intel_connector->edid); |
||
3031 | serge | 2288 | } |
2289 | |||
3243 | Serge | 2290 | return intel_ddc_get_modes(connector, adapter); |
2342 | Serge | 2291 | } |
2292 | |||
2293 | |||
2330 | Serge | 2294 | /** |
2295 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. |
||
2296 | * |
||
2297 | * \return true if DP port is connected. |
||
2298 | * \return false if DP port is disconnected. |
||
2299 | */ |
||
2300 | static enum drm_connector_status |
||
2301 | intel_dp_detect(struct drm_connector *connector, bool force) |
||
2302 | { |
||
2303 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
3243 | Serge | 2304 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2305 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
2306 | struct drm_device *dev = connector->dev; |
||
2330 | Serge | 2307 | enum drm_connector_status status; |
2308 | struct edid *edid = NULL; |
||
3243 | Serge | 2309 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2330 | Serge | 2310 | |
2311 | intel_dp->has_audio = false; |
||
2312 | |||
2313 | if (HAS_PCH_SPLIT(dev)) |
||
2314 | status = ironlake_dp_detect(intel_dp); |
||
2315 | else |
||
2316 | status = g4x_dp_detect(intel_dp); |
||
2317 | |||
3243 | Serge | 2318 | // hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2319 | // 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
||
2320 | // DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
||
2330 | Serge | 2321 | |
2322 | if (status != connector_status_connected) |
||
2323 | return status; |
||
3031 | serge | 2324 | |
2325 | intel_dp_probe_oui(intel_dp); |
||
2326 | |||
3243 | Serge | 2327 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
2328 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
||
2330 | Serge | 2329 | } else { |
3031 | serge | 2330 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
2330 | Serge | 2331 | if (edid) { |
2332 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
||
2333 | kfree(edid); |
||
2334 | } |
||
2335 | } |
||
3243 | Serge | 2336 | |
2337 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
||
2338 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
||
2330 | Serge | 2339 | return connector_status_connected; |
2340 | } |
||
2341 | |||
2342 | static int intel_dp_get_modes(struct drm_connector *connector) |
||
2343 | { |
||
2344 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
3243 | Serge | 2345 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2346 | struct drm_device *dev = connector->dev; |
||
2330 | Serge | 2347 | int ret; |
2348 | |||
2349 | /* We should parse the EDID data and find out if it has an audio sink |
||
2350 | */ |
||
2351 | |||
2342 | Serge | 2352 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
3243 | Serge | 2353 | if (ret) |
2330 | Serge | 2354 | return ret; |
2355 | |||
3243 | Serge | 2356 | /* if eDP has no EDID, fall back to fixed mode */ |
2357 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
||
2330 | Serge | 2358 | struct drm_display_mode *mode; |
3243 | Serge | 2359 | mode = drm_mode_duplicate(dev, |
2360 | intel_connector->panel.fixed_mode); |
||
2361 | if (mode) { |
||
2330 | Serge | 2362 | drm_mode_probed_add(connector, mode); |
2363 | return 1; |
||
2364 | } |
||
2365 | } |
||
2366 | return 0; |
||
2367 | } |
||
2368 | |||
3243 | Serge | 2369 | static bool |
2370 | intel_dp_detect_audio(struct drm_connector *connector) |
||
2371 | { |
||
2372 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
2373 | struct edid *edid; |
||
2374 | bool has_audio = false; |
||
2330 | Serge | 2375 | |
3243 | Serge | 2376 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
2377 | if (edid) { |
||
2378 | has_audio = drm_detect_monitor_audio(edid); |
||
2379 | kfree(edid); |
||
2380 | } |
||
2330 | Serge | 2381 | |
3243 | Serge | 2382 | return has_audio; |
2383 | } |
||
2330 | Serge | 2384 | |
2385 | static int |
||
2386 | intel_dp_set_property(struct drm_connector *connector, |
||
2387 | struct drm_property *property, |
||
2388 | uint64_t val) |
||
2389 | { |
||
2390 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
3243 | Serge | 2391 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2392 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
||
2393 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
2330 | Serge | 2394 | int ret; |
2395 | |||
3243 | Serge | 2396 | ret = drm_object_property_set_value(&connector->base, property, val); |
2330 | Serge | 2397 | if (ret) |
2398 | return ret; |
||
2399 | #if 0 |
||
2400 | if (property == dev_priv->force_audio_property) { |
||
2401 | int i = val; |
||
2402 | bool has_audio; |
||
2403 | |||
2404 | if (i == intel_dp->force_audio) |
||
2405 | return 0; |
||
2406 | |||
2407 | intel_dp->force_audio = i; |
||
2408 | |||
3031 | serge | 2409 | if (i == HDMI_AUDIO_AUTO) |
2330 | Serge | 2410 | has_audio = intel_dp_detect_audio(connector); |
2411 | else |
||
3031 | serge | 2412 | has_audio = (i == HDMI_AUDIO_ON); |
2330 | Serge | 2413 | |
2414 | if (has_audio == intel_dp->has_audio) |
||
2415 | return 0; |
||
2416 | |||
2417 | intel_dp->has_audio = has_audio; |
||
2418 | goto done; |
||
2419 | } |
||
2420 | |||
2421 | if (property == dev_priv->broadcast_rgb_property) { |
||
2422 | if (val == !!intel_dp->color_range) |
||
2423 | return 0; |
||
2424 | |||
2425 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; |
||
2426 | goto done; |
||
2427 | } |
||
2428 | #endif |
||
2429 | |||
3243 | Serge | 2430 | if (is_edp(intel_dp) && |
2431 | property == connector->dev->mode_config.scaling_mode_property) { |
||
2432 | if (val == DRM_MODE_SCALE_NONE) { |
||
2433 | DRM_DEBUG_KMS("no scaling not supported\n"); |
||
2434 | return -EINVAL; |
||
2435 | } |
||
2436 | |||
2437 | if (intel_connector->panel.fitting_mode == val) { |
||
2438 | /* the eDP scaling property is not changed */ |
||
2439 | return 0; |
||
2440 | } |
||
2441 | intel_connector->panel.fitting_mode = val; |
||
2442 | |||
2443 | goto done; |
||
2444 | } |
||
2445 | |||
2330 | Serge | 2446 | return -EINVAL; |
2447 | |||
2448 | done: |
||
3243 | Serge | 2449 | if (intel_encoder->base.crtc) { |
2450 | struct drm_crtc *crtc = intel_encoder->base.crtc; |
||
3031 | serge | 2451 | intel_set_mode(crtc, &crtc->mode, |
2452 | crtc->x, crtc->y, crtc->fb); |
||
2330 | Serge | 2453 | } |
2454 | |||
2455 | return 0; |
||
2456 | } |
||
2457 | |||
2458 | static void |
||
2342 | Serge | 2459 | intel_dp_destroy(struct drm_connector *connector) |
2330 | Serge | 2460 | { |
2461 | struct drm_device *dev = connector->dev; |
||
3031 | serge | 2462 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3243 | Serge | 2463 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2330 | Serge | 2464 | |
3243 | Serge | 2465 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
2466 | kfree(intel_connector->edid); |
||
2467 | |||
2468 | if (is_edp(intel_dp)) { |
||
2330 | Serge | 2469 | intel_panel_destroy_backlight(dev); |
3243 | Serge | 2470 | intel_panel_fini(&intel_connector->panel); |
2471 | } |
||
2330 | Serge | 2472 | |
2473 | drm_sysfs_connector_remove(connector); |
||
2474 | drm_connector_cleanup(connector); |
||
2475 | kfree(connector); |
||
2476 | } |
||
2477 | |||
3243 | Serge | 2478 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2330 | Serge | 2479 | { |
3243 | Serge | 2480 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
2481 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
||
2330 | Serge | 2482 | |
3243 | Serge | 2483 | i2c_del_adapter(&intel_dp->adapter); |
2330 | Serge | 2484 | drm_encoder_cleanup(encoder); |
2342 | Serge | 2485 | if (is_edp(intel_dp)) { |
2486 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
||
2487 | ironlake_panel_vdd_off_sync(intel_dp); |
||
2488 | } |
||
3243 | Serge | 2489 | kfree(intel_dig_port); |
2330 | Serge | 2490 | } |
2491 | |||
2492 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
||
2493 | .mode_fixup = intel_dp_mode_fixup, |
||
2494 | .mode_set = intel_dp_mode_set, |
||
3031 | serge | 2495 | .disable = intel_encoder_noop, |
2330 | Serge | 2496 | }; |
2497 | |||
2498 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
||
3031 | serge | 2499 | .dpms = intel_connector_dpms, |
2330 | Serge | 2500 | .detect = intel_dp_detect, |
2501 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
2502 | .set_property = intel_dp_set_property, |
||
2503 | .destroy = intel_dp_destroy, |
||
2504 | }; |
||
2505 | |||
2506 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
||
2507 | .get_modes = intel_dp_get_modes, |
||
2508 | .mode_valid = intel_dp_mode_valid, |
||
2509 | .best_encoder = intel_best_encoder, |
||
2510 | }; |
||
2511 | |||
2512 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
||
2513 | .destroy = intel_dp_encoder_destroy, |
||
2514 | }; |
||
2515 | |||
2516 | static void |
||
2517 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
||
2518 | { |
||
3243 | Serge | 2519 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
2330 | Serge | 2520 | |
2521 | intel_dp_check_link_status(intel_dp); |
||
2522 | } |
||
2523 | |||
2327 | Serge | 2524 | /* Return which DP Port should be selected for Transcoder DP control */ |
2525 | int |
||
2342 | Serge | 2526 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
2327 | Serge | 2527 | { |
2528 | struct drm_device *dev = crtc->dev; |
||
3243 | Serge | 2529 | struct intel_encoder *intel_encoder; |
2530 | struct intel_dp *intel_dp; |
||
2327 | Serge | 2531 | |
3243 | Serge | 2532 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
2533 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
2327 | Serge | 2534 | |
3243 | Serge | 2535 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
2536 | intel_encoder->type == INTEL_OUTPUT_EDP) |
||
2327 | Serge | 2537 | return intel_dp->output_reg; |
2538 | } |
||
2539 | |||
2540 | return -1; |
||
2541 | } |
||
2330 | Serge | 2542 | |
2543 | /* check the VBT to see whether the eDP is on DP-D port */ |
||
2544 | bool intel_dpd_is_edp(struct drm_device *dev) |
||
2545 | { |
||
2546 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2547 | struct child_device_config *p_child; |
||
2548 | int i; |
||
2549 | |||
2550 | if (!dev_priv->child_dev_num) |
||
2551 | return false; |
||
2552 | |||
2553 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
||
2554 | p_child = dev_priv->child_dev + i; |
||
2555 | |||
2556 | if (p_child->dvo_port == PORT_IDPD && |
||
2557 | p_child->device_type == DEVICE_TYPE_eDP) |
||
2558 | return true; |
||
2559 | } |
||
2560 | return false; |
||
2561 | } |
||
2562 | |||
2563 | static void |
||
2564 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
||
2565 | { |
||
3243 | Serge | 2566 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2567 | |||
2330 | Serge | 2568 | intel_attach_force_audio_property(connector); |
2569 | intel_attach_broadcast_rgb_property(connector); |
||
3243 | Serge | 2570 | |
2571 | if (is_edp(intel_dp)) { |
||
2572 | drm_mode_create_scaling_mode_property(connector->dev); |
||
2573 | drm_object_attach_property( |
||
2574 | &connector->base, |
||
2575 | connector->dev->mode_config.scaling_mode_property, |
||
2576 | DRM_MODE_SCALE_ASPECT); |
||
2577 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
||
2578 | } |
||
2330 | Serge | 2579 | } |
2580 | |||
3243 | Serge | 2581 | static void |
2582 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
||
2583 | struct intel_dp *intel_dp, |
||
2584 | struct edp_power_seq *out) |
||
2585 | { |
||
2586 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2587 | struct edp_power_seq cur, vbt, spec, final; |
||
2588 | u32 pp_on, pp_off, pp_div, pp; |
||
2589 | |||
2590 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
||
2591 | * the very first thing. */ |
||
2592 | pp = ironlake_get_pp_control(dev_priv); |
||
2593 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
2594 | |||
2595 | pp_on = I915_READ(PCH_PP_ON_DELAYS); |
||
2596 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
||
2597 | pp_div = I915_READ(PCH_PP_DIVISOR); |
||
2598 | |||
2599 | /* Pull timing values out of registers */ |
||
2600 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
||
2601 | PANEL_POWER_UP_DELAY_SHIFT; |
||
2602 | |||
2603 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
||
2604 | PANEL_LIGHT_ON_DELAY_SHIFT; |
||
2605 | |||
2606 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
||
2607 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
||
2608 | |||
2609 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
||
2610 | PANEL_POWER_DOWN_DELAY_SHIFT; |
||
2611 | |||
2612 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
||
2613 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
||
2614 | |||
2615 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
||
2616 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
||
2617 | |||
2618 | vbt = dev_priv->edp.pps; |
||
2619 | |||
2620 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
||
2621 | * our hw here, which are all in 100usec. */ |
||
2622 | spec.t1_t3 = 210 * 10; |
||
2623 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
||
2624 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
||
2625 | spec.t10 = 500 * 10; |
||
2626 | /* This one is special and actually in units of 100ms, but zero |
||
2627 | * based in the hw (so we need to add 100 ms). But the sw vbt |
||
2628 | * table multiplies it with 1000 to make it in units of 100usec, |
||
2629 | * too. */ |
||
2630 | spec.t11_t12 = (510 + 100) * 10; |
||
2631 | |||
2632 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
||
2633 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
||
2634 | |||
2635 | /* Use the max of the register settings and vbt. If both are |
||
2636 | * unset, fall back to the spec limits. */ |
||
2637 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
||
2638 | spec.field : \ |
||
2639 | max(cur.field, vbt.field)) |
||
2640 | assign_final(t1_t3); |
||
2641 | assign_final(t8); |
||
2642 | assign_final(t9); |
||
2643 | assign_final(t10); |
||
2644 | assign_final(t11_t12); |
||
2645 | #undef assign_final |
||
2646 | |||
2647 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
||
2648 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
||
2649 | intel_dp->backlight_on_delay = get_delay(t8); |
||
2650 | intel_dp->backlight_off_delay = get_delay(t9); |
||
2651 | intel_dp->panel_power_down_delay = get_delay(t10); |
||
2652 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
||
2653 | #undef get_delay |
||
2654 | |||
2655 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
||
2656 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
||
2657 | intel_dp->panel_power_cycle_delay); |
||
2658 | |||
2659 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
||
2660 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
||
2661 | |||
2662 | if (out) |
||
2663 | *out = final; |
||
2664 | } |
||
2665 | |||
2666 | static void |
||
2667 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
||
2668 | struct intel_dp *intel_dp, |
||
2669 | struct edp_power_seq *seq) |
||
2670 | { |
||
2671 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2672 | u32 pp_on, pp_off, pp_div; |
||
2673 | |||
2674 | /* And finally store the new values in the power sequencer. */ |
||
2675 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
||
2676 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
||
2677 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
||
2678 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
||
2679 | /* Compute the divisor for the pp clock, simply match the Bspec |
||
2680 | * formula. */ |
||
2681 | pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1) |
||
2682 | << PP_REFERENCE_DIVIDER_SHIFT; |
||
2683 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
||
2684 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
||
2685 | |||
2686 | /* Haswell doesn't have any port selection bits for the panel |
||
2687 | * power sequencer any more. */ |
||
2688 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
||
2689 | if (is_cpu_edp(intel_dp)) |
||
2690 | pp_on |= PANEL_POWER_PORT_DP_A; |
||
2691 | else |
||
2692 | pp_on |= PANEL_POWER_PORT_DP_D; |
||
2693 | } |
||
2694 | |||
2695 | I915_WRITE(PCH_PP_ON_DELAYS, pp_on); |
||
2696 | I915_WRITE(PCH_PP_OFF_DELAYS, pp_off); |
||
2697 | I915_WRITE(PCH_PP_DIVISOR, pp_div); |
||
2698 | |||
2699 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
||
2700 | I915_READ(PCH_PP_ON_DELAYS), |
||
2701 | I915_READ(PCH_PP_OFF_DELAYS), |
||
2702 | I915_READ(PCH_PP_DIVISOR)); |
||
2703 | } |
||
2704 | |||
2330 | Serge | 2705 | void |
3243 | Serge | 2706 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
2707 | struct intel_connector *intel_connector) |
||
2330 | Serge | 2708 | { |
3243 | Serge | 2709 | struct drm_connector *connector = &intel_connector->base; |
2710 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
||
2711 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
2712 | struct drm_device *dev = intel_encoder->base.dev; |
||
2330 | Serge | 2713 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 2714 | struct drm_display_mode *fixed_mode = NULL; |
2715 | struct edp_power_seq power_seq = { 0 }; |
||
2716 | enum port port = intel_dig_port->port; |
||
2330 | Serge | 2717 | const char *name = NULL; |
2718 | int type; |
||
2719 | |||
3031 | serge | 2720 | /* Preserve the current hw state. */ |
2721 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
||
3243 | Serge | 2722 | intel_dp->attached_connector = intel_connector; |
2330 | Serge | 2723 | |
3243 | Serge | 2724 | if (HAS_PCH_SPLIT(dev) && port == PORT_D) |
2330 | Serge | 2725 | if (intel_dpd_is_edp(dev)) |
2726 | intel_dp->is_pch_edp = true; |
||
2727 | |||
3243 | Serge | 2728 | /* |
2729 | * FIXME : We need to initialize built-in panels before external panels. |
||
2730 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup |
||
2731 | */ |
||
2732 | if (IS_VALLEYVIEW(dev) && port == PORT_C) { |
||
2330 | Serge | 2733 | type = DRM_MODE_CONNECTOR_eDP; |
2734 | intel_encoder->type = INTEL_OUTPUT_EDP; |
||
3243 | Serge | 2735 | } else if (port == PORT_A || is_pch_edp(intel_dp)) { |
2736 | type = DRM_MODE_CONNECTOR_eDP; |
||
2737 | intel_encoder->type = INTEL_OUTPUT_EDP; |
||
2330 | Serge | 2738 | } else { |
3243 | Serge | 2739 | /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for |
2740 | * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't |
||
2741 | * rewrite it. |
||
2742 | */ |
||
2330 | Serge | 2743 | type = DRM_MODE_CONNECTOR_DisplayPort; |
2744 | } |
||
2745 | |||
2746 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
||
2747 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
||
2748 | |||
2749 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
||
2750 | connector->interlace_allowed = true; |
||
2751 | connector->doublescan_allowed = 0; |
||
2752 | |||
3243 | Serge | 2753 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2754 | ironlake_panel_vdd_work); |
||
2330 | Serge | 2755 | |
2756 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
2757 | drm_sysfs_connector_add(connector); |
||
2758 | |||
3243 | Serge | 2759 | if (IS_HASWELL(dev)) |
2760 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
||
2761 | else |
||
3031 | serge | 2762 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
2763 | |||
3243 | Serge | 2764 | |
2330 | Serge | 2765 | /* Set up the DDC bus. */ |
3031 | serge | 2766 | switch (port) { |
2767 | case PORT_A: |
||
2330 | Serge | 2768 | name = "DPDDC-A"; |
2769 | break; |
||
3031 | serge | 2770 | case PORT_B: |
2771 | dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS; |
||
2330 | Serge | 2772 | name = "DPDDC-B"; |
2773 | break; |
||
3031 | serge | 2774 | case PORT_C: |
2775 | dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS; |
||
2330 | Serge | 2776 | name = "DPDDC-C"; |
2777 | break; |
||
3031 | serge | 2778 | case PORT_D: |
2779 | dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS; |
||
2330 | Serge | 2780 | name = "DPDDC-D"; |
2781 | break; |
||
3031 | serge | 2782 | default: |
2783 | WARN(1, "Invalid port %c\n", port_name(port)); |
||
2784 | break; |
||
2330 | Serge | 2785 | } |
2786 | |||
3243 | Serge | 2787 | if (is_edp(intel_dp)) |
2788 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
||
2330 | Serge | 2789 | |
3031 | serge | 2790 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2791 | |||
3243 | Serge | 2792 | /* Cache DPCD and EDID for edp. */ |
3031 | serge | 2793 | if (is_edp(intel_dp)) { |
2794 | bool ret; |
||
3243 | Serge | 2795 | struct drm_display_mode *scan; |
3031 | serge | 2796 | struct edid *edid; |
2797 | |||
2330 | Serge | 2798 | ironlake_edp_panel_vdd_on(intel_dp); |
2799 | ret = intel_dp_get_dpcd(intel_dp); |
||
2342 | Serge | 2800 | ironlake_edp_panel_vdd_off(intel_dp, false); |
2801 | |||
2330 | Serge | 2802 | if (ret) { |
2803 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
||
2804 | dev_priv->no_aux_handshake = |
||
2805 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
||
2806 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
||
2807 | } else { |
||
2808 | /* if this fails, presume the device is a ghost */ |
||
2809 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
||
3243 | Serge | 2810 | intel_dp_encoder_destroy(&intel_encoder->base); |
2811 | intel_dp_destroy(connector); |
||
2330 | Serge | 2812 | return; |
2813 | } |
||
3031 | serge | 2814 | |
3243 | Serge | 2815 | /* We now know it's not a ghost, init power sequence regs. */ |
2816 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
||
2817 | &power_seq); |
||
2818 | |||
3031 | serge | 2819 | ironlake_edp_panel_vdd_on(intel_dp); |
2820 | edid = drm_get_edid(connector, &intel_dp->adapter); |
||
2821 | if (edid) { |
||
3243 | Serge | 2822 | if (drm_add_edid_modes(connector, edid)) { |
2823 | drm_mode_connector_update_edid_property(connector, edid); |
||
3031 | serge | 2824 | drm_edid_to_eld(connector, edid); |
3243 | Serge | 2825 | } else { |
2826 | kfree(edid); |
||
2827 | edid = ERR_PTR(-EINVAL); |
||
2828 | } |
||
2829 | } else { |
||
2830 | edid = ERR_PTR(-ENOENT); |
||
3031 | serge | 2831 | } |
3243 | Serge | 2832 | intel_connector->edid = edid; |
2833 | |||
2834 | /* prefer fixed mode from EDID if available */ |
||
2835 | list_for_each_entry(scan, &connector->probed_modes, head) { |
||
2836 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
||
2837 | fixed_mode = drm_mode_duplicate(dev, scan); |
||
2838 | break; |
||
2839 | } |
||
2840 | } |
||
2841 | |||
2842 | /* fallback to VBT if available for eDP */ |
||
2843 | if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) { |
||
2844 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
||
2845 | if (fixed_mode) |
||
2846 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
||
2847 | } |
||
2848 | |||
3031 | serge | 2849 | ironlake_edp_panel_vdd_off(intel_dp, false); |
2330 | Serge | 2850 | } |
2851 | |||
2852 | if (is_edp(intel_dp)) { |
||
3243 | Serge | 2853 | intel_panel_init(&intel_connector->panel, fixed_mode); |
2854 | intel_panel_setup_backlight(connector); |
||
2330 | Serge | 2855 | } |
2856 | |||
2857 | intel_dp_add_properties(intel_dp, connector); |
||
2858 | |||
2859 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
2860 | * 0xd. Failure to do so will result in spurious interrupts being |
||
2861 | * generated on the port when a cable is not attached. |
||
2862 | */ |
||
2863 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
2864 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
2865 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
||
2866 | } |
||
2867 | } |
||
3243 | Serge | 2868 | |
2869 | void |
||
2870 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
||
2871 | { |
||
2872 | struct intel_digital_port *intel_dig_port; |
||
2873 | struct intel_encoder *intel_encoder; |
||
2874 | struct drm_encoder *encoder; |
||
2875 | struct intel_connector *intel_connector; |
||
2876 | |||
2877 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); |
||
2878 | if (!intel_dig_port) |
||
2879 | return; |
||
2880 | |||
2881 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
||
2882 | if (!intel_connector) { |
||
2883 | kfree(intel_dig_port); |
||
2884 | return; |
||
2885 | } |
||
2886 | |||
2887 | intel_encoder = &intel_dig_port->base; |
||
2888 | encoder = &intel_encoder->base; |
||
2889 | |||
2890 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
||
2891 | DRM_MODE_ENCODER_TMDS); |
||
2892 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
||
2893 | |||
2894 | intel_encoder->enable = intel_enable_dp; |
||
2895 | intel_encoder->pre_enable = intel_pre_enable_dp; |
||
2896 | intel_encoder->disable = intel_disable_dp; |
||
2897 | intel_encoder->post_disable = intel_post_disable_dp; |
||
2898 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
||
2899 | |||
2900 | intel_dig_port->port = port; |
||
2901 | intel_dig_port->dp.output_reg = output_reg; |
||
2902 | |||
2903 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
||
2904 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
2905 | intel_encoder->cloneable = false; |
||
2906 | intel_encoder->hot_plug = intel_dp_hot_plug; |
||
2907 | |||
2908 | intel_dp_init_connector(intel_dig_port, intel_connector); |
||
2909 | }><>><>><>><>><>><>><>><>><>>>>>>>>>>><>=>=><=>=>=>>>><>><>><>>><>>><>>><>><>><>>>>>><>>> |