WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
6084	serge	24	* Eric Anholt
2327	Serge	25	*/
		26
5097	serge	27	#include
2327	Serge	28	#include
6088	serge	29	#include
2327	Serge	30	#include
		31	#include
2330	Serge	32	#include
5354	serge	33	#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
6084	serge	40	#include
		41	#include
3031	serge	42	#include
		43	#include
5060	serge	44	#include
		45	#include
		46	#include
2327	Serge	47
5060	serge	48	/* Primary plane formats for gen <= 3 */
6084	serge	49	static const uint32_t i8xx_primary_formats[] = {
		50	DRM_FORMAT_C8,
		51	DRM_FORMAT_RGB565,
5060	serge	52	DRM_FORMAT_XRGB1555,
6084	serge	53	DRM_FORMAT_XRGB8888,
5060	serge	54	};
		55
		56	/* Primary plane formats for gen >= 4 */
6084	serge	57	static const uint32_t i965_primary_formats[] = {
		58	DRM_FORMAT_C8,
		59	DRM_FORMAT_RGB565,
		60	DRM_FORMAT_XRGB8888,
5060	serge	61	DRM_FORMAT_XBGR8888,
6084	serge	62	DRM_FORMAT_XRGB2101010,
		63	DRM_FORMAT_XBGR2101010,
		64	};
		65
		66	static const uint32_t skl_primary_formats[] = {
		67	DRM_FORMAT_C8,
		68	DRM_FORMAT_RGB565,
		69	DRM_FORMAT_XRGB8888,
		70	DRM_FORMAT_XBGR8888,
		71	DRM_FORMAT_ARGB8888,
5060	serge	72	DRM_FORMAT_ABGR8888,
		73	DRM_FORMAT_XRGB2101010,
		74	DRM_FORMAT_XBGR2101010,
6084	serge	75	DRM_FORMAT_YUYV,
		76	DRM_FORMAT_YVYU,
		77	DRM_FORMAT_UYVY,
		78	DRM_FORMAT_VYUY,
5060	serge	79	};
		80
		81	/* Cursor formats */
		82	static const uint32_t intel_cursor_formats[] = {
		83	DRM_FORMAT_ARGB8888,
		84	};
		85
		86	void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	87
4104	Serge	88	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6084	serge	89	struct intel_crtc_state *pipe_config);
4560	Serge	90	static void ironlake_pch_clock_get(struct intel_crtc *crtc,
6084	serge	91	struct intel_crtc_state *pipe_config);
2327	Serge	92
5060	serge	93	static int intel_framebuffer_init(struct drm_device *dev,
		94	struct intel_framebuffer *ifb,
		95	struct drm_mode_fb_cmd2 *mode_cmd,
		96	struct drm_i915_gem_object *obj);
		97	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
		98	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
		99	static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5354	serge	100	struct intel_link_m_n *m_n,
		101	struct intel_link_m_n *m2_n2);
5060	serge	102	static void ironlake_set_pipeconf(struct drm_crtc *crtc);
		103	static void haswell_set_pipeconf(struct drm_crtc *crtc);
		104	static void intel_set_pipe_csc(struct drm_crtc *crtc);
5354	serge	105	static void vlv_prepare_pll(struct intel_crtc *crtc,
6084	serge	106	const struct intel_crtc_state *pipe_config);
5354	serge	107	static void chv_prepare_pll(struct intel_crtc *crtc,
6084	serge	108	const struct intel_crtc_state *pipe_config);
		109	static void intel_begin_crtc_commit(struct drm_crtc , struct drm_crtc_state );
		110	static void intel_finish_crtc_commit(struct drm_crtc , struct drm_crtc_state );
		111	static void skl_init_scalers(struct drm_device dev, struct intel_crtc intel_crtc,
		112	struct intel_crtc_state *crtc_state);
		113	static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
		114	int num_connectors);
		115	static void skylake_pfit_enable(struct intel_crtc *crtc);
		116	static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
		117	static void ironlake_pfit_enable(struct intel_crtc *crtc);
		118	static void intel_modeset_setup_hw_state(struct drm_device *dev);
		119	static void intel_pre_disable_primary(struct drm_crtc *crtc);
4104	Serge	120
2327	Serge	121	typedef struct {
6084	serge	122	int min, max;
2327	Serge	123	} intel_range_t;
		124
		125	typedef struct {
6084	serge	126	int dot_limit;
		127	int p2_slow, p2_fast;
2327	Serge	128	} intel_p2_t;
		129
		130	typedef struct intel_limit intel_limit_t;
		131	struct intel_limit {
6084	serge	132	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		133	intel_p2_t p2;
2327	Serge	134	};
		135
6084	serge	136	/* returns HPLL frequency in kHz */
		137	static int valleyview_get_vco(struct drm_i915_private *dev_priv)
		138	{
		139	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
		140
		141	/* Obtain SKU information */
		142	mutex_lock(&dev_priv->sb_lock);
		143	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
		144	CCK_FUSE_HPLL_FREQ_MASK;
		145	mutex_unlock(&dev_priv->sb_lock);
		146
		147	return vco_freq[hpll_freq] * 1000;
		148	}
		149
		150	static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
		151	const char *name, u32 reg)
		152	{
		153	u32 val;
		154	int divider;
		155
		156	if (dev_priv->hpll_freq == 0)
		157	dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
		158
		159	mutex_lock(&dev_priv->sb_lock);
		160	val = vlv_cck_read(dev_priv, reg);
		161	mutex_unlock(&dev_priv->sb_lock);
		162
		163	divider = val & CCK_FREQUENCY_VALUES;
		164
		165	WARN((val & CCK_FREQUENCY_STATUS) !=
		166	(divider << CCK_FREQUENCY_STATUS_SHIFT),
		167	"%s change in progress\n", name);
		168
		169	return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
		170	}
		171
3243	Serge	172	int
		173	intel_pch_rawclk(struct drm_device *dev)
		174	{
		175	struct drm_i915_private *dev_priv = dev->dev_private;
		176
		177	WARN_ON(!HAS_PCH_SPLIT(dev));
		178
		179	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
		180	}
		181
6084	serge	182	/* hrawclock is 1/4 the FSB frequency */
		183	int intel_hrawclk(struct drm_device *dev)
		184	{
		185	struct drm_i915_private *dev_priv = dev->dev_private;
		186	uint32_t clkcfg;
		187
		188	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
		189	if (IS_VALLEYVIEW(dev))
		190	return 200;
		191
		192	clkcfg = I915_READ(CLKCFG);
		193	switch (clkcfg & CLKCFG_FSB_MASK) {
		194	case CLKCFG_FSB_400:
		195	return 100;
		196	case CLKCFG_FSB_533:
		197	return 133;
		198	case CLKCFG_FSB_667:
		199	return 166;
		200	case CLKCFG_FSB_800:
		201	return 200;
		202	case CLKCFG_FSB_1067:
		203	return 266;
		204	case CLKCFG_FSB_1333:
		205	return 333;
		206	/* these two are just a guess; one of them might be right */
		207	case CLKCFG_FSB_1600:
		208	case CLKCFG_FSB_1600_ALT:
		209	return 400;
		210	default:
		211	return 133;
		212	}
		213	}
		214
		215	static void intel_update_czclk(struct drm_i915_private *dev_priv)
		216	{
		217	if (!IS_VALLEYVIEW(dev_priv))
		218	return;
		219
		220	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
		221	CCK_CZ_CLOCK_CONTROL);
		222
		223	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
		224	}
		225
2327	Serge	226	static inline u32 /* units of 100MHz */
		227	intel_fdi_link_freq(struct drm_device *dev)
		228	{
		229	if (IS_GEN5(dev)) {
		230	struct drm_i915_private *dev_priv = dev->dev_private;
		231	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		232	} else
		233	return 27;
		234	}
		235
4104	Serge	236	static const intel_limit_t intel_limits_i8xx_dac = {
		237	.dot = { .min = 25000, .max = 350000 },
4560	Serge	238	.vco = { .min = 908000, .max = 1512000 },
		239	.n = { .min = 2, .max = 16 },
4104	Serge	240	.m = { .min = 96, .max = 140 },
		241	.m1 = { .min = 18, .max = 26 },
		242	.m2 = { .min = 6, .max = 16 },
		243	.p = { .min = 4, .max = 128 },
		244	.p1 = { .min = 2, .max = 33 },
		245	.p2 = { .dot_limit = 165000,
		246	.p2_slow = 4, .p2_fast = 2 },
		247	};
		248
2327	Serge	249	static const intel_limit_t intel_limits_i8xx_dvo = {
6084	serge	250	.dot = { .min = 25000, .max = 350000 },
4560	Serge	251	.vco = { .min = 908000, .max = 1512000 },
		252	.n = { .min = 2, .max = 16 },
6084	serge	253	.m = { .min = 96, .max = 140 },
		254	.m1 = { .min = 18, .max = 26 },
		255	.m2 = { .min = 6, .max = 16 },
		256	.p = { .min = 4, .max = 128 },
		257	.p1 = { .min = 2, .max = 33 },
2327	Serge	258	.p2 = { .dot_limit = 165000,
4104	Serge	259	.p2_slow = 4, .p2_fast = 4 },
2327	Serge	260	};
		261
		262	static const intel_limit_t intel_limits_i8xx_lvds = {
6084	serge	263	.dot = { .min = 25000, .max = 350000 },
4560	Serge	264	.vco = { .min = 908000, .max = 1512000 },
		265	.n = { .min = 2, .max = 16 },
6084	serge	266	.m = { .min = 96, .max = 140 },
		267	.m1 = { .min = 18, .max = 26 },
		268	.m2 = { .min = 6, .max = 16 },
		269	.p = { .min = 4, .max = 128 },
		270	.p1 = { .min = 1, .max = 6 },
2327	Serge	271	.p2 = { .dot_limit = 165000,
		272	.p2_slow = 14, .p2_fast = 7 },
		273	};
		274
		275	static const intel_limit_t intel_limits_i9xx_sdvo = {
6084	serge	276	.dot = { .min = 20000, .max = 400000 },
		277	.vco = { .min = 1400000, .max = 2800000 },
		278	.n = { .min = 1, .max = 6 },
		279	.m = { .min = 70, .max = 120 },
3480	Serge	280	.m1 = { .min = 8, .max = 18 },
		281	.m2 = { .min = 3, .max = 7 },
6084	serge	282	.p = { .min = 5, .max = 80 },
		283	.p1 = { .min = 1, .max = 8 },
2327	Serge	284	.p2 = { .dot_limit = 200000,
		285	.p2_slow = 10, .p2_fast = 5 },
		286	};
		287
		288	static const intel_limit_t intel_limits_i9xx_lvds = {
6084	serge	289	.dot = { .min = 20000, .max = 400000 },
		290	.vco = { .min = 1400000, .max = 2800000 },
		291	.n = { .min = 1, .max = 6 },
		292	.m = { .min = 70, .max = 120 },
3480	Serge	293	.m1 = { .min = 8, .max = 18 },
		294	.m2 = { .min = 3, .max = 7 },
6084	serge	295	.p = { .min = 7, .max = 98 },
		296	.p1 = { .min = 1, .max = 8 },
2327	Serge	297	.p2 = { .dot_limit = 112000,
		298	.p2_slow = 14, .p2_fast = 7 },
		299	};
		300
		301
		302	static const intel_limit_t intel_limits_g4x_sdvo = {
		303	.dot = { .min = 25000, .max = 270000 },
		304	.vco = { .min = 1750000, .max = 3500000},
		305	.n = { .min = 1, .max = 4 },
		306	.m = { .min = 104, .max = 138 },
		307	.m1 = { .min = 17, .max = 23 },
		308	.m2 = { .min = 5, .max = 11 },
		309	.p = { .min = 10, .max = 30 },
		310	.p1 = { .min = 1, .max = 3},
		311	.p2 = { .dot_limit = 270000,
		312	.p2_slow = 10,
		313	.p2_fast = 10
		314	},
		315	};
		316
		317	static const intel_limit_t intel_limits_g4x_hdmi = {
		318	.dot = { .min = 22000, .max = 400000 },
		319	.vco = { .min = 1750000, .max = 3500000},
		320	.n = { .min = 1, .max = 4 },
		321	.m = { .min = 104, .max = 138 },
		322	.m1 = { .min = 16, .max = 23 },
		323	.m2 = { .min = 5, .max = 11 },
		324	.p = { .min = 5, .max = 80 },
		325	.p1 = { .min = 1, .max = 8},
		326	.p2 = { .dot_limit = 165000,
		327	.p2_slow = 10, .p2_fast = 5 },
		328	};
		329
		330	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		331	.dot = { .min = 20000, .max = 115000 },
		332	.vco = { .min = 1750000, .max = 3500000 },
		333	.n = { .min = 1, .max = 3 },
		334	.m = { .min = 104, .max = 138 },
		335	.m1 = { .min = 17, .max = 23 },
		336	.m2 = { .min = 5, .max = 11 },
		337	.p = { .min = 28, .max = 112 },
		338	.p1 = { .min = 2, .max = 8 },
		339	.p2 = { .dot_limit = 0,
		340	.p2_slow = 14, .p2_fast = 14
		341	},
		342	};
		343
		344	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		345	.dot = { .min = 80000, .max = 224000 },
		346	.vco = { .min = 1750000, .max = 3500000 },
		347	.n = { .min = 1, .max = 3 },
		348	.m = { .min = 104, .max = 138 },
		349	.m1 = { .min = 17, .max = 23 },
		350	.m2 = { .min = 5, .max = 11 },
		351	.p = { .min = 14, .max = 42 },
		352	.p1 = { .min = 2, .max = 6 },
		353	.p2 = { .dot_limit = 0,
		354	.p2_slow = 7, .p2_fast = 7
		355	},
		356	};
		357
		358	static const intel_limit_t intel_limits_pineview_sdvo = {
6084	serge	359	.dot = { .min = 20000, .max = 400000},
		360	.vco = { .min = 1700000, .max = 3500000 },
2327	Serge	361	/* Pineview's Ncounter is a ring counter */
6084	serge	362	.n = { .min = 3, .max = 6 },
		363	.m = { .min = 2, .max = 256 },
2327	Serge	364	/* Pineview only has one combined m divider, which we treat as m2. */
6084	serge	365	.m1 = { .min = 0, .max = 0 },
		366	.m2 = { .min = 0, .max = 254 },
		367	.p = { .min = 5, .max = 80 },
		368	.p1 = { .min = 1, .max = 8 },
2327	Serge	369	.p2 = { .dot_limit = 200000,
		370	.p2_slow = 10, .p2_fast = 5 },
		371	};
		372
		373	static const intel_limit_t intel_limits_pineview_lvds = {
6084	serge	374	.dot = { .min = 20000, .max = 400000 },
		375	.vco = { .min = 1700000, .max = 3500000 },
		376	.n = { .min = 3, .max = 6 },
		377	.m = { .min = 2, .max = 256 },
		378	.m1 = { .min = 0, .max = 0 },
		379	.m2 = { .min = 0, .max = 254 },
		380	.p = { .min = 7, .max = 112 },
		381	.p1 = { .min = 1, .max = 8 },
2327	Serge	382	.p2 = { .dot_limit = 112000,
		383	.p2_slow = 14, .p2_fast = 14 },
		384	};
		385
		386	/* Ironlake / Sandybridge
		387	*
		388	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		389	* the range value for them is (actual_value - 2).
		390	*/
		391	static const intel_limit_t intel_limits_ironlake_dac = {
		392	.dot = { .min = 25000, .max = 350000 },
		393	.vco = { .min = 1760000, .max = 3510000 },
		394	.n = { .min = 1, .max = 5 },
		395	.m = { .min = 79, .max = 127 },
		396	.m1 = { .min = 12, .max = 22 },
		397	.m2 = { .min = 5, .max = 9 },
		398	.p = { .min = 5, .max = 80 },
		399	.p1 = { .min = 1, .max = 8 },
		400	.p2 = { .dot_limit = 225000,
		401	.p2_slow = 10, .p2_fast = 5 },
		402	};
		403
		404	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		405	.dot = { .min = 25000, .max = 350000 },
		406	.vco = { .min = 1760000, .max = 3510000 },
		407	.n = { .min = 1, .max = 3 },
		408	.m = { .min = 79, .max = 118 },
		409	.m1 = { .min = 12, .max = 22 },
		410	.m2 = { .min = 5, .max = 9 },
		411	.p = { .min = 28, .max = 112 },
		412	.p1 = { .min = 2, .max = 8 },
		413	.p2 = { .dot_limit = 225000,
		414	.p2_slow = 14, .p2_fast = 14 },
		415	};
		416
		417	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		418	.dot = { .min = 25000, .max = 350000 },
		419	.vco = { .min = 1760000, .max = 3510000 },
		420	.n = { .min = 1, .max = 3 },
		421	.m = { .min = 79, .max = 127 },
		422	.m1 = { .min = 12, .max = 22 },
		423	.m2 = { .min = 5, .max = 9 },
		424	.p = { .min = 14, .max = 56 },
		425	.p1 = { .min = 2, .max = 8 },
		426	.p2 = { .dot_limit = 225000,
		427	.p2_slow = 7, .p2_fast = 7 },
		428	};
		429
		430	/* LVDS 100mhz refclk limits. */
		431	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		432	.dot = { .min = 25000, .max = 350000 },
		433	.vco = { .min = 1760000, .max = 3510000 },
		434	.n = { .min = 1, .max = 2 },
		435	.m = { .min = 79, .max = 126 },
		436	.m1 = { .min = 12, .max = 22 },
		437	.m2 = { .min = 5, .max = 9 },
		438	.p = { .min = 28, .max = 112 },
2342	Serge	439	.p1 = { .min = 2, .max = 8 },
2327	Serge	440	.p2 = { .dot_limit = 225000,
		441	.p2_slow = 14, .p2_fast = 14 },
		442	};
		443
		444	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		445	.dot = { .min = 25000, .max = 350000 },
		446	.vco = { .min = 1760000, .max = 3510000 },
		447	.n = { .min = 1, .max = 3 },
		448	.m = { .min = 79, .max = 126 },
		449	.m1 = { .min = 12, .max = 22 },
		450	.m2 = { .min = 5, .max = 9 },
		451	.p = { .min = 14, .max = 42 },
2342	Serge	452	.p1 = { .min = 2, .max = 6 },
2327	Serge	453	.p2 = { .dot_limit = 225000,
		454	.p2_slow = 7, .p2_fast = 7 },
		455	};
		456
4560	Serge	457	static const intel_limit_t intel_limits_vlv = {
		458	/*
		459	* These are the data rate limits (measured in fast clocks)
		460	* since those are the strictest limits we have. The fast
		461	* clock and actual rate limits are more relaxed, so checking
		462	* them would make no difference.
		463	*/
		464	.dot = { .min = 25000 * 5, .max = 270000 * 5 },
3031	serge	465	.vco = { .min = 4000000, .max = 6000000 },
		466	.n = { .min = 1, .max = 7 },
		467	.m1 = { .min = 2, .max = 3 },
		468	.m2 = { .min = 11, .max = 156 },
		469	.p1 = { .min = 2, .max = 3 },
4560	Serge	470	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
3031	serge	471	};
		472
5060	serge	473	static const intel_limit_t intel_limits_chv = {
		474	/*
		475	* These are the data rate limits (measured in fast clocks)
		476	* since those are the strictest limits we have. The fast
		477	* clock and actual rate limits are more relaxed, so checking
		478	* them would make no difference.
		479	*/
		480	.dot = { .min = 25000 * 5, .max = 540000 * 5},
6084	serge	481	.vco = { .min = 4800000, .max = 6480000 },
5060	serge	482	.n = { .min = 1, .max = 1 },
		483	.m1 = { .min = 2, .max = 2 },
		484	.m2 = { .min = 24 << 22, .max = 175 << 22 },
		485	.p1 = { .min = 2, .max = 4 },
		486	.p2 = { .p2_slow = 1, .p2_fast = 14 },
		487	};
		488
6084	serge	489	static const intel_limit_t intel_limits_bxt = {
		490	/* FIXME: find real dot limits */
		491	.dot = { .min = 0, .max = INT_MAX },
		492	.vco = { .min = 4800000, .max = 6700000 },
		493	.n = { .min = 1, .max = 1 },
		494	.m1 = { .min = 2, .max = 2 },
		495	/* FIXME: find real m2 limits */
		496	.m2 = { .min = 2 << 22, .max = 255 << 22 },
		497	.p1 = { .min = 2, .max = 4 },
		498	.p2 = { .p2_slow = 1, .p2_fast = 20 },
		499	};
		500
		501	static bool
		502	needs_modeset(struct drm_crtc_state *state)
4560	Serge	503	{
6084	serge	504	return drm_atomic_crtc_needs_modeset(state);
4560	Serge	505	}
3031	serge	506
4560	Serge	507	/**
		508	* Returns whether any output on the specified pipe is of the specified type
		509	*/
5354	serge	510	bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
4560	Serge	511	{
5354	serge	512	struct drm_device *dev = crtc->base.dev;
4560	Serge	513	struct intel_encoder *encoder;
		514
5354	serge	515	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4560	Serge	516	if (encoder->type == type)
		517	return true;
		518
		519	return false;
		520	}
		521
5354	serge	522	/**
		523	* Returns whether any output on the specified pipe will have the specified
		524	* type after a staged modeset is complete, i.e., the same as
		525	* intel_pipe_has_type() but looking at encoder->new_crtc instead of
		526	* encoder->crtc.
		527	*/
6084	serge	528	static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
		529	int type)
5354	serge	530	{
6084	serge	531	struct drm_atomic_state *state = crtc_state->base.state;
		532	struct drm_connector *connector;
		533	struct drm_connector_state *connector_state;
5354	serge	534	struct intel_encoder *encoder;
6084	serge	535	int i, num_connectors = 0;
5354	serge	536
6084	serge	537	for_each_connector_in_state(state, connector, connector_state, i) {
		538	if (connector_state->crtc != crtc_state->base.crtc)
		539	continue;
		540
		541	num_connectors++;
		542
		543	encoder = to_intel_encoder(connector_state->best_encoder);
		544	if (encoder->type == type)
5354	serge	545	return true;
6084	serge	546	}
5354	serge	547
6084	serge	548	WARN_ON(num_connectors == 0);
		549
5354	serge	550	return false;
		551	}
		552
6084	serge	553	static const intel_limit_t *
		554	intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2327	Serge	555	{
6084	serge	556	struct drm_device *dev = crtc_state->base.crtc->dev;
2327	Serge	557	const intel_limit_t *limit;
		558
6084	serge	559	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
3480	Serge	560	if (intel_is_dual_link_lvds(dev)) {
2327	Serge	561	if (refclk == 100000)
		562	limit = &intel_limits_ironlake_dual_lvds_100m;
		563	else
		564	limit = &intel_limits_ironlake_dual_lvds;
		565	} else {
		566	if (refclk == 100000)
		567	limit = &intel_limits_ironlake_single_lvds_100m;
		568	else
		569	limit = &intel_limits_ironlake_single_lvds;
		570	}
4104	Serge	571	} else
2327	Serge	572	limit = &intel_limits_ironlake_dac;
		573
		574	return limit;
		575	}
		576
6084	serge	577	static const intel_limit_t *
		578	intel_g4x_limit(struct intel_crtc_state *crtc_state)
2327	Serge	579	{
6084	serge	580	struct drm_device *dev = crtc_state->base.crtc->dev;
2327	Serge	581	const intel_limit_t *limit;
		582
6084	serge	583	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
3480	Serge	584	if (intel_is_dual_link_lvds(dev))
2327	Serge	585	limit = &intel_limits_g4x_dual_channel_lvds;
		586	else
		587	limit = &intel_limits_g4x_single_channel_lvds;
6084	serge	588	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) \|\|
		589	intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
2327	Serge	590	limit = &intel_limits_g4x_hdmi;
6084	serge	591	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
2327	Serge	592	limit = &intel_limits_g4x_sdvo;
		593	} else /* The option is for other outputs */
		594	limit = &intel_limits_i9xx_sdvo;
		595
		596	return limit;
		597	}
		598
6084	serge	599	static const intel_limit_t *
		600	intel_limit(struct intel_crtc_state *crtc_state, int refclk)
2327	Serge	601	{
6084	serge	602	struct drm_device *dev = crtc_state->base.crtc->dev;
2327	Serge	603	const intel_limit_t *limit;
		604
6084	serge	605	if (IS_BROXTON(dev))
		606	limit = &intel_limits_bxt;
		607	else if (HAS_PCH_SPLIT(dev))
		608	limit = intel_ironlake_limit(crtc_state, refclk);
2327	Serge	609	else if (IS_G4X(dev)) {
6084	serge	610	limit = intel_g4x_limit(crtc_state);
2327	Serge	611	} else if (IS_PINEVIEW(dev)) {
6084	serge	612	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
2327	Serge	613	limit = &intel_limits_pineview_lvds;
		614	else
		615	limit = &intel_limits_pineview_sdvo;
5060	serge	616	} else if (IS_CHERRYVIEW(dev)) {
		617	limit = &intel_limits_chv;
3031	serge	618	} else if (IS_VALLEYVIEW(dev)) {
4560	Serge	619	limit = &intel_limits_vlv;
2327	Serge	620	} else if (!IS_GEN2(dev)) {
6084	serge	621	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
2327	Serge	622	limit = &intel_limits_i9xx_lvds;
		623	else
		624	limit = &intel_limits_i9xx_sdvo;
		625	} else {
6084	serge	626	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
2327	Serge	627	limit = &intel_limits_i8xx_lvds;
6084	serge	628	else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4104	Serge	629	limit = &intel_limits_i8xx_dvo;
2327	Serge	630	else
4104	Serge	631	limit = &intel_limits_i8xx_dac;
2327	Serge	632	}
		633	return limit;
		634	}
		635
6084	serge	636	/*
		637	* Platform specific helpers to calculate the port PLL loopback- (clock.m),
		638	* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
		639	* (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
		640	* The helpers' return value is the rate of the clock that is fed to the
		641	* display engine's pipe which can be the above fast dot clock rate or a
		642	* divided-down version of it.
		643	*/
2327	Serge	644	/* m1 is reserved as 0 in Pineview, n is a ring counter */
6084	serge	645	static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
2327	Serge	646	{
		647	clock->m = clock->m2 + 2;
		648	clock->p = clock->p1 * clock->p2;
4560	Serge	649	if (WARN_ON(clock->n == 0 \|\| clock->p == 0))
6084	serge	650	return 0;
4560	Serge	651	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
		652	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6084	serge	653
		654	return clock->dot;
2327	Serge	655	}
		656
4104	Serge	657	static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
2327	Serge	658	{
4104	Serge	659	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
		660	}
		661
6084	serge	662	static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
4104	Serge	663	{
		664	clock->m = i9xx_dpll_compute_m(clock);
2327	Serge	665	clock->p = clock->p1 * clock->p2;
4560	Serge	666	if (WARN_ON(clock->n + 2 == 0 \|\| clock->p == 0))
6084	serge	667	return 0;
4560	Serge	668	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
		669	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6084	serge	670
		671	return clock->dot;
2327	Serge	672	}
		673
6084	serge	674	static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
5060	serge	675	{
		676	clock->m = clock->m1 * clock->m2;
		677	clock->p = clock->p1 * clock->p2;
		678	if (WARN_ON(clock->n == 0 \|\| clock->p == 0))
6084	serge	679	return 0;
		680	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
		681	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
		682
		683	return clock->dot / 5;
		684	}
		685
		686	int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
		687	{
		688	clock->m = clock->m1 * clock->m2;
		689	clock->p = clock->p1 * clock->p2;
		690	if (WARN_ON(clock->n == 0 \|\| clock->p == 0))
		691	return 0;
5060	serge	692	clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
		693	clock->n << 22);
		694	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6084	serge	695
		696	return clock->dot / 5;
5060	serge	697	}
		698
2327	Serge	699	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		700	/**
		701	* Returns whether the given set of divisors are valid for a given refclk with
		702	* the given connectors.
		703	*/
		704
		705	static bool intel_PLL_is_valid(struct drm_device *dev,
		706	const intel_limit_t *limit,
		707	const intel_clock_t *clock)
		708	{
4560	Serge	709	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
		710	INTELPllInvalid("n out of range\n");
2327	Serge	711	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	712	INTELPllInvalid("p1 out of range\n");
2327	Serge	713	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	714	INTELPllInvalid("m2 out of range\n");
2327	Serge	715	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	716	INTELPllInvalid("m1 out of range\n");
4560	Serge	717
6084	serge	718	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
4560	Serge	719	if (clock->m1 <= clock->m2)
6084	serge	720	INTELPllInvalid("m1 <= m2\n");
4560	Serge	721
6084	serge	722	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
4560	Serge	723	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
		724	INTELPllInvalid("p out of range\n");
6084	serge	725	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
		726	INTELPllInvalid("m out of range\n");
4560	Serge	727	}
		728
2327	Serge	729	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	730	INTELPllInvalid("vco out of range\n");
2327	Serge	731	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		732	* connector, etc., rather than just a single range.
		733	*/
		734	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	735	INTELPllInvalid("dot out of range\n");
2327	Serge	736
		737	return true;
		738	}
		739
6084	serge	740	static int
		741	i9xx_select_p2_div(const intel_limit_t *limit,
		742	const struct intel_crtc_state *crtc_state,
		743	int target)
2327	Serge	744	{
6084	serge	745	struct drm_device *dev = crtc_state->base.crtc->dev;
2327	Serge	746
6084	serge	747	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
2327	Serge	748	/*
3480	Serge	749	* For LVDS just rely on its current settings for dual-channel.
		750	* We haven't figured out how to reliably set up different
		751	* single/dual channel state, if we even can.
2327	Serge	752	*/
3480	Serge	753	if (intel_is_dual_link_lvds(dev))
6084	serge	754	return limit->p2.p2_fast;
2327	Serge	755	else
6084	serge	756	return limit->p2.p2_slow;
2327	Serge	757	} else {
		758	if (target < limit->p2.dot_limit)
6084	serge	759	return limit->p2.p2_slow;
2327	Serge	760	else
6084	serge	761	return limit->p2.p2_fast;
2327	Serge	762	}
6084	serge	763	}
2327	Serge	764
6084	serge	765	static bool
		766	i9xx_find_best_dpll(const intel_limit_t *limit,
		767	struct intel_crtc_state *crtc_state,
		768	int target, int refclk, intel_clock_t *match_clock,
		769	intel_clock_t *best_clock)
		770	{
		771	struct drm_device *dev = crtc_state->base.crtc->dev;
		772	intel_clock_t clock;
		773	int err = target;
		774
2342	Serge	775	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	776
6084	serge	777	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
		778
2327	Serge	779	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		780	clock.m1++) {
		781	for (clock.m2 = limit->m2.min;
		782	clock.m2 <= limit->m2.max; clock.m2++) {
4104	Serge	783	if (clock.m2 >= clock.m1)
2327	Serge	784	break;
		785	for (clock.n = limit->n.min;
		786	clock.n <= limit->n.max; clock.n++) {
		787	for (clock.p1 = limit->p1.min;
		788	clock.p1 <= limit->p1.max; clock.p1++) {
		789	int this_err;
		790
6084	serge	791	i9xx_calc_dpll_params(refclk, &clock);
2327	Serge	792	if (!intel_PLL_is_valid(dev, limit,
		793	&clock))
		794	continue;
3031	serge	795	if (match_clock &&
		796	clock.p != match_clock->p)
		797	continue;
2327	Serge	798
		799	this_err = abs(clock.dot - target);
		800	if (this_err < err) {
		801	*best_clock = clock;
		802	err = this_err;
		803	}
		804	}
		805	}
		806	}
		807	}
		808
		809	return (err != target);
		810	}
		811
		812	static bool
6084	serge	813	pnv_find_best_dpll(const intel_limit_t *limit,
		814	struct intel_crtc_state *crtc_state,
4104	Serge	815	int target, int refclk, intel_clock_t *match_clock,
		816	intel_clock_t *best_clock)
		817	{
6084	serge	818	struct drm_device *dev = crtc_state->base.crtc->dev;
4104	Serge	819	intel_clock_t clock;
		820	int err = target;
		821
		822	memset(best_clock, 0, sizeof(*best_clock));
		823
6084	serge	824	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
		825
4104	Serge	826	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		827	clock.m1++) {
		828	for (clock.m2 = limit->m2.min;
		829	clock.m2 <= limit->m2.max; clock.m2++) {
		830	for (clock.n = limit->n.min;
		831	clock.n <= limit->n.max; clock.n++) {
		832	for (clock.p1 = limit->p1.min;
		833	clock.p1 <= limit->p1.max; clock.p1++) {
		834	int this_err;
		835
6084	serge	836	pnv_calc_dpll_params(refclk, &clock);
4104	Serge	837	if (!intel_PLL_is_valid(dev, limit,
		838	&clock))
		839	continue;
		840	if (match_clock &&
		841	clock.p != match_clock->p)
		842	continue;
		843
		844	this_err = abs(clock.dot - target);
		845	if (this_err < err) {
		846	*best_clock = clock;
		847	err = this_err;
		848	}
		849	}
		850	}
		851	}
		852	}
		853
		854	return (err != target);
		855	}
		856
		857	static bool
6084	serge	858	g4x_find_best_dpll(const intel_limit_t *limit,
		859	struct intel_crtc_state *crtc_state,
		860	int target, int refclk, intel_clock_t *match_clock,
		861	intel_clock_t *best_clock)
2327	Serge	862	{
6084	serge	863	struct drm_device *dev = crtc_state->base.crtc->dev;
2327	Serge	864	intel_clock_t clock;
		865	int max_n;
6084	serge	866	bool found = false;
2327	Serge	867	/* approximately equals target * 0.00585 */
		868	int err_most = (target >> 8) + (target >> 9);
		869
6084	serge	870	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	871
6084	serge	872	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
		873
2327	Serge	874	max_n = limit->n.max;
		875	/* based on hardware requirement, prefer smaller n to precision */
		876	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		877	/* based on hardware requirement, prefere larger m1,m2 */
		878	for (clock.m1 = limit->m1.max;
		879	clock.m1 >= limit->m1.min; clock.m1--) {
		880	for (clock.m2 = limit->m2.max;
		881	clock.m2 >= limit->m2.min; clock.m2--) {
		882	for (clock.p1 = limit->p1.max;
		883	clock.p1 >= limit->p1.min; clock.p1--) {
		884	int this_err;
		885
6084	serge	886	i9xx_calc_dpll_params(refclk, &clock);
2327	Serge	887	if (!intel_PLL_is_valid(dev, limit,
		888	&clock))
		889	continue;
		890
		891	this_err = abs(clock.dot - target);
		892	if (this_err < err_most) {
		893	*best_clock = clock;
		894	err_most = this_err;
		895	max_n = clock.n;
		896	found = true;
		897	}
		898	}
		899	}
		900	}
		901	}
		902	return found;
		903	}
		904
6084	serge	905	/*
		906	* Check if the calculated PLL configuration is more optimal compared to the
		907	* best configuration and error found so far. Return the calculated error.
		908	*/
		909	static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
		910	const intel_clock_t *calculated_clock,
		911	const intel_clock_t *best_clock,
		912	unsigned int best_error_ppm,
		913	unsigned int *error_ppm)
		914	{
		915	/*
		916	* For CHV ignore the error and consider only the P value.
		917	* Prefer a bigger P value based on HW requirements.
		918	*/
		919	if (IS_CHERRYVIEW(dev)) {
		920	*error_ppm = 0;
		921
		922	return calculated_clock->p > best_clock->p;
		923	}
		924
		925	if (WARN_ON_ONCE(!target_freq))
		926	return false;
		927
		928	error_ppm = div_u64(1000000ULL
		929	abs(target_freq - calculated_clock->dot),
		930	target_freq);
		931	/*
		932	* Prefer a better P value over a better (smaller) error if the error
		933	* is small. Ensure this preference for future configurations too by
		934	* setting the error to 0.
		935	*/
		936	if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
		937	*error_ppm = 0;
		938
		939	return true;
		940	}
		941
		942	return *error_ppm + 10 < best_error_ppm;
		943	}
		944
2327	Serge	945	static bool
6084	serge	946	vlv_find_best_dpll(const intel_limit_t *limit,
		947	struct intel_crtc_state *crtc_state,
		948	int target, int refclk, intel_clock_t *match_clock,
		949	intel_clock_t *best_clock)
3031	serge	950	{
6084	serge	951	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5354	serge	952	struct drm_device *dev = crtc->base.dev;
4560	Serge	953	intel_clock_t clock;
		954	unsigned int bestppm = 1000000;
		955	/* min update 19.2 MHz */
		956	int max_n = min(limit->n.max, refclk / 19200);
		957	bool found = false;
2327	Serge	958
4560	Serge	959	target = 5; / fast clock */
3031	serge	960
4560	Serge	961	memset(best_clock, 0, sizeof(*best_clock));
		962
3031	serge	963	/* based on hardware requirement, prefer smaller n to precision */
4560	Serge	964	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		965	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
		966	for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
		967	clock.p2 -= clock.p2 > 10 ? 2 : 1) {
		968	clock.p = clock.p1 * clock.p2;
3031	serge	969	/* based on hardware requirement, prefer bigger m1,m2 values */
4560	Serge	970	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
6084	serge	971	unsigned int ppm;
4560	Serge	972
		973	clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
		974	refclk * clock.m1);
		975
6084	serge	976	vlv_calc_dpll_params(refclk, &clock);
4560	Serge	977
		978	if (!intel_PLL_is_valid(dev, limit,
		979	&clock))
		980	continue;
		981
6084	serge	982	if (!vlv_PLL_is_optimal(dev, target,
		983	&clock,
		984	best_clock,
		985	bestppm, &ppm))
		986	continue;
4560	Serge	987
6084	serge	988	*best_clock = clock;
		989	bestppm = ppm;
		990	found = true;
3031	serge	991	}
		992	}
6084	serge	993	}
		994	}
3031	serge	995
4560	Serge	996	return found;
3031	serge	997	}
		998
5060	serge	999	static bool
6084	serge	1000	chv_find_best_dpll(const intel_limit_t *limit,
		1001	struct intel_crtc_state *crtc_state,
5060	serge	1002	int target, int refclk, intel_clock_t *match_clock,
		1003	intel_clock_t *best_clock)
		1004	{
6084	serge	1005	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5354	serge	1006	struct drm_device *dev = crtc->base.dev;
6084	serge	1007	unsigned int best_error_ppm;
5060	serge	1008	intel_clock_t clock;
		1009	uint64_t m2;
		1010	int found = false;
		1011
		1012	memset(best_clock, 0, sizeof(*best_clock));
6084	serge	1013	best_error_ppm = 1000000;
5060	serge	1014
		1015	/*
		1016	* Based on hardware doc, the n always set to 1, and m1 always
		1017	* set to 2. If requires to support 200Mhz refclk, we need to
		1018	* revisit this because n may not 1 anymore.
		1019	*/
		1020	clock.n = 1, clock.m1 = 2;
		1021	target = 5; / fast clock */
		1022
		1023	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
		1024	for (clock.p2 = limit->p2.p2_fast;
		1025	clock.p2 >= limit->p2.p2_slow;
		1026	clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6084	serge	1027	unsigned int error_ppm;
5060	serge	1028
		1029	clock.p = clock.p1 * clock.p2;
		1030
		1031	m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
		1032	clock.n) << 22, refclk * clock.m1);
		1033
		1034	if (m2 > INT_MAX/clock.m1)
		1035	continue;
		1036
		1037	clock.m2 = m2;
		1038
6084	serge	1039	chv_calc_dpll_params(refclk, &clock);
5060	serge	1040
		1041	if (!intel_PLL_is_valid(dev, limit, &clock))
		1042	continue;
		1043
6084	serge	1044	if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
		1045	best_error_ppm, &error_ppm))
		1046	continue;
		1047
		1048	*best_clock = clock;
		1049	best_error_ppm = error_ppm;
		1050	found = true;
5060	serge	1051	}
		1052	}
		1053
		1054	return found;
		1055	}
		1056
6084	serge	1057	bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
		1058	intel_clock_t *best_clock)
		1059	{
		1060	int refclk = i9xx_get_refclk(crtc_state, 0);
		1061
		1062	return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
		1063	target_clock, refclk, NULL, best_clock);
		1064	}
		1065
4560	Serge	1066	bool intel_crtc_active(struct drm_crtc *crtc)
		1067	{
		1068	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1069
		1070	/* Be paranoid as we can arrive here with only partial
		1071	* state retrieved from the hardware during setup.
		1072	*
		1073	* We can ditch the adjusted_mode.crtc_clock check as soon
		1074	* as Haswell has gained clock readout/fastboot support.
		1075	*
5060	serge	1076	* We can ditch the crtc->primary->fb check as soon as we can
4560	Serge	1077	* properly reconstruct framebuffers.
6084	serge	1078	*
		1079	* FIXME: The intel_crtc->active here should be switched to
		1080	* crtc->state->active once we have proper CRTC states wired up
		1081	* for atomic.
4560	Serge	1082	*/
6084	serge	1083	return intel_crtc->active && crtc->primary->state->fb &&
		1084	intel_crtc->config->base.adjusted_mode.crtc_clock;
4560	Serge	1085	}
		1086
3243	Serge	1087	enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
		1088	enum pipe pipe)
		1089	{
		1090	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		1091	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1092
6084	serge	1093	return intel_crtc->config->cpu_transcoder;
3243	Serge	1094	}
		1095
4560	Serge	1096	static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
		1097	{
		1098	struct drm_i915_private *dev_priv = dev->dev_private;
		1099	u32 reg = PIPEDSL(pipe);
		1100	u32 line1, line2;
		1101	u32 line_mask;
		1102
		1103	if (IS_GEN2(dev))
		1104	line_mask = DSL_LINEMASK_GEN2;
		1105	else
		1106	line_mask = DSL_LINEMASK_GEN3;
		1107
		1108	line1 = I915_READ(reg) & line_mask;
6084	serge	1109	msleep(5);
4560	Serge	1110	line2 = I915_READ(reg) & line_mask;
		1111
		1112	return line1 == line2;
		1113	}
		1114
2327	Serge	1115	/*
		1116	* intel_wait_for_pipe_off - wait for pipe to turn off
5354	serge	1117	* @crtc: crtc whose pipe to wait for
2327	Serge	1118	*
		1119	* After disabling a pipe, we can't wait for vblank in the usual way,
		1120	* spinning on the vblank interrupt status bit, since we won't actually
		1121	* see an interrupt when the pipe is disabled.
		1122	*
		1123	* On Gen4 and above:
		1124	* wait for the pipe register state bit to turn off
		1125	*
		1126	* Otherwise:
		1127	* wait for the display line value to settle (it usually
		1128	* ends up stopping at the start of the next frame).
		1129	*
		1130	*/
5354	serge	1131	static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
2327	Serge	1132	{
5354	serge	1133	struct drm_device *dev = crtc->base.dev;
2327	Serge	1134	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	1135	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
5354	serge	1136	enum pipe pipe = crtc->pipe;
2327	Serge	1137
		1138	if (INTEL_INFO(dev)->gen >= 4) {
3243	Serge	1139	int reg = PIPECONF(cpu_transcoder);
2327	Serge	1140
		1141	/* Wait for the Pipe State to go off */
		1142	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		1143	100))
3031	serge	1144	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1145	} else {
		1146	/* Wait for the display line to settle */
4560	Serge	1147	if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
3031	serge	1148	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1149	}
		1150	}
		1151
		1152	static const char *state_string(bool enabled)
		1153	{
		1154	return enabled ? "on" : "off";
		1155	}
		1156
		1157	/* Only for pre-ILK configs */
4104	Serge	1158	void assert_pll(struct drm_i915_private *dev_priv,
6084	serge	1159	enum pipe pipe, bool state)
2327	Serge	1160	{
		1161	u32 val;
		1162	bool cur_state;
		1163
6084	serge	1164	val = I915_READ(DPLL(pipe));
2327	Serge	1165	cur_state = !!(val & DPLL_VCO_ENABLE);
6084	serge	1166	I915_STATE_WARN(cur_state != state,
2327	Serge	1167	"PLL state assertion failure (expected %s, current %s)\n",
		1168	state_string(state), state_string(cur_state));
		1169	}
		1170
4560	Serge	1171	/* XXX: the dsi pll is shared between MIPI DSI ports */
		1172	static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
		1173	{
		1174	u32 val;
		1175	bool cur_state;
		1176
6084	serge	1177	mutex_lock(&dev_priv->sb_lock);
4560	Serge	1178	val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
6084	serge	1179	mutex_unlock(&dev_priv->sb_lock);
4560	Serge	1180
		1181	cur_state = val & DSI_PLL_VCO_EN;
6084	serge	1182	I915_STATE_WARN(cur_state != state,
4560	Serge	1183	"DSI PLL state assertion failure (expected %s, current %s)\n",
		1184	state_string(state), state_string(cur_state));
		1185	}
		1186	#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
		1187	#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
		1188
4104	Serge	1189	struct intel_shared_dpll *
		1190	intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
		1191	{
		1192	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1193
6084	serge	1194	if (crtc->config->shared_dpll < 0)
4104	Serge	1195	return NULL;
		1196
6084	serge	1197	return &dev_priv->shared_dplls[crtc->config->shared_dpll];
4104	Serge	1198	}
		1199
2327	Serge	1200	/* For ILK+ */
4104	Serge	1201	void assert_shared_dpll(struct drm_i915_private *dev_priv,
6084	serge	1202	struct intel_shared_dpll *pll,
		1203	bool state)
2327	Serge	1204	{
		1205	bool cur_state;
4104	Serge	1206	struct intel_dpll_hw_state hw_state;
2327	Serge	1207
3031	serge	1208	if (WARN (!pll,
4104	Serge	1209	"asserting DPLL %s with no DPLL\n", state_string(state)))
3031	serge	1210	return;
2342	Serge	1211
4104	Serge	1212	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
6084	serge	1213	I915_STATE_WARN(cur_state != state,
4104	Serge	1214	"%s assertion failure (expected %s, current %s)\n",
		1215	pll->name, state_string(state), state_string(cur_state));
2327	Serge	1216	}
		1217
		1218	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		1219	enum pipe pipe, bool state)
		1220	{
		1221	bool cur_state;
3243	Serge	1222	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1223	pipe);
2327	Serge	1224
3480	Serge	1225	if (HAS_DDI(dev_priv->dev)) {
		1226	/* DDI does not have a specific FDI_TX register */
6084	serge	1227	u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3243	Serge	1228	cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
3031	serge	1229	} else {
6084	serge	1230	u32 val = I915_READ(FDI_TX_CTL(pipe));
		1231	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	1232	}
6084	serge	1233	I915_STATE_WARN(cur_state != state,
2327	Serge	1234	"FDI TX state assertion failure (expected %s, current %s)\n",
		1235	state_string(state), state_string(cur_state));
		1236	}
		1237	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		1238	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		1239
		1240	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		1241	enum pipe pipe, bool state)
		1242	{
		1243	u32 val;
		1244	bool cur_state;
		1245
6084	serge	1246	val = I915_READ(FDI_RX_CTL(pipe));
2327	Serge	1247	cur_state = !!(val & FDI_RX_ENABLE);
6084	serge	1248	I915_STATE_WARN(cur_state != state,
2327	Serge	1249	"FDI RX state assertion failure (expected %s, current %s)\n",
		1250	state_string(state), state_string(cur_state));
		1251	}
		1252	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1253	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1254
		1255	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1256	enum pipe pipe)
		1257	{
		1258	u32 val;
		1259
		1260	/* ILK FDI PLL is always enabled */
5060	serge	1261	if (INTEL_INFO(dev_priv->dev)->gen == 5)
2327	Serge	1262	return;
		1263
3031	serge	1264	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
3480	Serge	1265	if (HAS_DDI(dev_priv->dev))
3031	serge	1266	return;
		1267
6084	serge	1268	val = I915_READ(FDI_TX_CTL(pipe));
		1269	I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
2327	Serge	1270	}
		1271
4104	Serge	1272	void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		1273	enum pipe pipe, bool state)
2327	Serge	1274	{
		1275	u32 val;
4104	Serge	1276	bool cur_state;
2327	Serge	1277
6084	serge	1278	val = I915_READ(FDI_RX_CTL(pipe));
4104	Serge	1279	cur_state = !!(val & FDI_RX_PLL_ENABLE);
6084	serge	1280	I915_STATE_WARN(cur_state != state,
4104	Serge	1281	"FDI RX PLL assertion failure (expected %s, current %s)\n",
		1282	state_string(state), state_string(cur_state));
2327	Serge	1283	}
		1284
5354	serge	1285	void assert_panel_unlocked(struct drm_i915_private *dev_priv,
6084	serge	1286	enum pipe pipe)
2327	Serge	1287	{
5354	serge	1288	struct drm_device *dev = dev_priv->dev;
		1289	int pp_reg;
2327	Serge	1290	u32 val;
		1291	enum pipe panel_pipe = PIPE_A;
		1292	bool locked = true;
		1293
5354	serge	1294	if (WARN_ON(HAS_DDI(dev)))
		1295	return;
		1296
		1297	if (HAS_PCH_SPLIT(dev)) {
		1298	u32 port_sel;
		1299
2327	Serge	1300	pp_reg = PCH_PP_CONTROL;
5354	serge	1301	port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
		1302
		1303	if (port_sel == PANEL_PORT_SELECT_LVDS &&
		1304	I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
		1305	panel_pipe = PIPE_B;
		1306	/* XXX: else fix for eDP */
		1307	} else if (IS_VALLEYVIEW(dev)) {
		1308	/* presumably write lock depends on pipe, not port select */
		1309	pp_reg = VLV_PIPE_PP_CONTROL(pipe);
		1310	panel_pipe = pipe;
2327	Serge	1311	} else {
		1312	pp_reg = PP_CONTROL;
5354	serge	1313	if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
		1314	panel_pipe = PIPE_B;
2327	Serge	1315	}
		1316
		1317	val = I915_READ(pp_reg);
		1318	if (!(val & PANEL_POWER_ON) \|\|
5354	serge	1319	((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
2327	Serge	1320	locked = false;
		1321
6084	serge	1322	I915_STATE_WARN(panel_pipe == pipe && locked,
2327	Serge	1323	"panel assertion failure, pipe %c regs locked\n",
		1324	pipe_name(pipe));
		1325	}
		1326
4560	Serge	1327	static void assert_cursor(struct drm_i915_private *dev_priv,
		1328	enum pipe pipe, bool state)
		1329	{
		1330	struct drm_device *dev = dev_priv->dev;
		1331	bool cur_state;
		1332
5060	serge	1333	if (IS_845G(dev) \|\| IS_I865G(dev))
6084	serge	1334	cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
4560	Serge	1335	else
		1336	cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
		1337
6084	serge	1338	I915_STATE_WARN(cur_state != state,
4560	Serge	1339	"cursor on pipe %c assertion failure (expected %s, current %s)\n",
		1340	pipe_name(pipe), state_string(state), state_string(cur_state));
		1341	}
		1342	#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
		1343	#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
		1344
2342	Serge	1345	void assert_pipe(struct drm_i915_private *dev_priv,
6084	serge	1346	enum pipe pipe, bool state)
2327	Serge	1347	{
		1348	bool cur_state;
3243	Serge	1349	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1350	pipe);
2327	Serge	1351
5354	serge	1352	/* if we need the pipe quirk it must be always on */
		1353	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) \|\|
		1354	(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
3031	serge	1355	state = true;
		1356
5354	serge	1357	if (!intel_display_power_is_enabled(dev_priv,
4104	Serge	1358	POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
3480	Serge	1359	cur_state = false;
		1360	} else {
6084	serge	1361	u32 val = I915_READ(PIPECONF(cpu_transcoder));
		1362	cur_state = !!(val & PIPECONF_ENABLE);
3480	Serge	1363	}
		1364
6084	serge	1365	I915_STATE_WARN(cur_state != state,
2327	Serge	1366	"pipe %c assertion failure (expected %s, current %s)\n",
		1367	pipe_name(pipe), state_string(state), state_string(cur_state));
		1368	}
		1369
3031	serge	1370	static void assert_plane(struct drm_i915_private *dev_priv,
		1371	enum plane plane, bool state)
2327	Serge	1372	{
		1373	u32 val;
3031	serge	1374	bool cur_state;
2327	Serge	1375
6084	serge	1376	val = I915_READ(DSPCNTR(plane));
3031	serge	1377	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
6084	serge	1378	I915_STATE_WARN(cur_state != state,
3031	serge	1379	"plane %c assertion failure (expected %s, current %s)\n",
		1380	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1381	}
		1382
3031	serge	1383	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1384	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1385
2327	Serge	1386	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1387	enum pipe pipe)
		1388	{
4104	Serge	1389	struct drm_device *dev = dev_priv->dev;
6084	serge	1390	int i;
2327	Serge	1391
4104	Serge	1392	/* Primary planes are fixed to pipes on gen4+ */
		1393	if (INTEL_INFO(dev)->gen >= 4) {
6084	serge	1394	u32 val = I915_READ(DSPCNTR(pipe));
		1395	I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
3031	serge	1396	"plane %c assertion failure, should be disabled but not\n",
		1397	plane_name(pipe));
2327	Serge	1398	return;
3031	serge	1399	}
2327	Serge	1400
		1401	/* Need to check both planes against the pipe */
5354	serge	1402	for_each_pipe(dev_priv, i) {
6084	serge	1403	u32 val = I915_READ(DSPCNTR(i));
		1404	enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
2327	Serge	1405	DISPPLANE_SEL_PIPE_SHIFT;
6084	serge	1406	I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
2327	Serge	1407	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1408	plane_name(i), pipe_name(pipe));
		1409	}
		1410	}
		1411
3746	Serge	1412	static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
		1413	enum pipe pipe)
		1414	{
4104	Serge	1415	struct drm_device *dev = dev_priv->dev;
6084	serge	1416	int sprite;
3746	Serge	1417
5354	serge	1418	if (INTEL_INFO(dev)->gen >= 9) {
6084	serge	1419	for_each_sprite(dev_priv, pipe, sprite) {
		1420	u32 val = I915_READ(PLANE_CTL(pipe, sprite));
		1421	I915_STATE_WARN(val & PLANE_CTL_ENABLE,
5354	serge	1422	"plane %d assertion failure, should be off on pipe %c but is still active\n",
		1423	sprite, pipe_name(pipe));
		1424	}
		1425	} else if (IS_VALLEYVIEW(dev)) {
6084	serge	1426	for_each_sprite(dev_priv, pipe, sprite) {
		1427	u32 val = I915_READ(SPCNTR(pipe, sprite));
		1428	I915_STATE_WARN(val & SP_ENABLE,
4104	Serge	1429	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
5060	serge	1430	sprite_name(pipe, sprite), pipe_name(pipe));
4104	Serge	1431	}
		1432	} else if (INTEL_INFO(dev)->gen >= 7) {
6084	serge	1433	u32 val = I915_READ(SPRCTL(pipe));
		1434	I915_STATE_WARN(val & SPRITE_ENABLE,
4104	Serge	1435	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1436	plane_name(pipe), pipe_name(pipe));
		1437	} else if (INTEL_INFO(dev)->gen >= 5) {
6084	serge	1438	u32 val = I915_READ(DVSCNTR(pipe));
		1439	I915_STATE_WARN(val & DVS_ENABLE,
4104	Serge	1440	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1441	plane_name(pipe), pipe_name(pipe));
3746	Serge	1442	}
		1443	}
		1444
5354	serge	1445	static void assert_vblank_disabled(struct drm_crtc *crtc)
		1446	{
6084	serge	1447	if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
5354	serge	1448	drm_crtc_vblank_put(crtc);
		1449	}
		1450
4560	Serge	1451	static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
2327	Serge	1452	{
		1453	u32 val;
		1454	bool enabled;
		1455
6084	serge	1456	I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) \|\| HAS_PCH_CPT(dev_priv->dev)));
3031	serge	1457
2327	Serge	1458	val = I915_READ(PCH_DREF_CONTROL);
		1459	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1460	DREF_SUPERSPREAD_SOURCE_MASK));
6084	serge	1461	I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
2327	Serge	1462	}
		1463
4104	Serge	1464	static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
6084	serge	1465	enum pipe pipe)
2327	Serge	1466	{
		1467	u32 val;
		1468	bool enabled;
		1469
6084	serge	1470	val = I915_READ(PCH_TRANSCONF(pipe));
2327	Serge	1471	enabled = !!(val & TRANS_ENABLE);
6084	serge	1472	I915_STATE_WARN(enabled,
2327	Serge	1473	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1474	pipe_name(pipe));
		1475	}
		1476
		1477	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1478	enum pipe pipe, u32 port_sel, u32 val)
		1479	{
		1480	if ((val & DP_PORT_EN) == 0)
		1481	return false;
		1482
		1483	if (HAS_PCH_CPT(dev_priv->dev)) {
		1484	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1485	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1486	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1487	return false;
5060	serge	1488	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
		1489	if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
		1490	return false;
2327	Serge	1491	} else {
		1492	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1493	return false;
		1494	}
		1495	return true;
		1496	}
		1497
		1498	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1499	enum pipe pipe, u32 val)
		1500	{
3746	Serge	1501	if ((val & SDVO_ENABLE) == 0)
2327	Serge	1502	return false;
		1503
		1504	if (HAS_PCH_CPT(dev_priv->dev)) {
3746	Serge	1505	if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
2327	Serge	1506	return false;
5060	serge	1507	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
		1508	if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
		1509	return false;
2327	Serge	1510	} else {
3746	Serge	1511	if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
2327	Serge	1512	return false;
		1513	}
		1514	return true;
		1515	}
		1516
		1517	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1518	enum pipe pipe, u32 val)
		1519	{
		1520	if ((val & LVDS_PORT_EN) == 0)
		1521	return false;
		1522
		1523	if (HAS_PCH_CPT(dev_priv->dev)) {
		1524	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1525	return false;
		1526	} else {
		1527	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1528	return false;
		1529	}
		1530	return true;
		1531	}
		1532
		1533	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1534	enum pipe pipe, u32 val)
		1535	{
		1536	if ((val & ADPA_DAC_ENABLE) == 0)
		1537	return false;
		1538	if (HAS_PCH_CPT(dev_priv->dev)) {
		1539	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1540	return false;
		1541	} else {
		1542	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1543	return false;
		1544	}
		1545	return true;
		1546	}
		1547
		1548	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1549	enum pipe pipe, int reg, u32 port_sel)
		1550	{
		1551	u32 val = I915_READ(reg);
6084	serge	1552	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
2327	Serge	1553	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1554	reg, pipe_name(pipe));
3031	serge	1555
6084	serge	1556	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
3031	serge	1557	&& (val & DP_PIPEB_SELECT),
		1558	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1559	}
		1560
		1561	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1562	enum pipe pipe, int reg)
		1563	{
		1564	u32 val = I915_READ(reg);
6084	serge	1565	I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
3031	serge	1566	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1567	reg, pipe_name(pipe));
3031	serge	1568
6084	serge	1569	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
3031	serge	1570	&& (val & SDVO_PIPE_B_SELECT),
		1571	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1572	}
		1573
		1574	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1575	enum pipe pipe)
		1576	{
		1577	u32 val;
		1578
		1579	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1580	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1581	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1582
6084	serge	1583	val = I915_READ(PCH_ADPA);
		1584	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1585	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1586	pipe_name(pipe));
		1587
6084	serge	1588	val = I915_READ(PCH_LVDS);
		1589	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1590	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1591	pipe_name(pipe));
		1592
3746	Serge	1593	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
		1594	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
		1595	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
2327	Serge	1596	}
		1597
5354	serge	1598	static void vlv_enable_pll(struct intel_crtc *crtc,
6084	serge	1599	const struct intel_crtc_state *pipe_config)
4560	Serge	1600	{
4104	Serge	1601	struct drm_device *dev = crtc->base.dev;
		1602	struct drm_i915_private *dev_priv = dev->dev_private;
		1603	int reg = DPLL(crtc->pipe);
5354	serge	1604	u32 dpll = pipe_config->dpll_hw_state.dpll;
2327	Serge	1605
4104	Serge	1606	assert_pipe_disabled(dev_priv, crtc->pipe);
		1607
6084	serge	1608	/* No really, not for ILK+ */
4104	Serge	1609	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
2327	Serge	1610
6084	serge	1611	/* PLL is protected by panel, make sure we can write it */
5354	serge	1612	if (IS_MOBILE(dev_priv->dev))
4104	Serge	1613	assert_panel_unlocked(dev_priv, crtc->pipe);
2327	Serge	1614
4104	Serge	1615	I915_WRITE(reg, dpll);
		1616	POSTING_READ(reg);
		1617	udelay(150);
2327	Serge	1618
4104	Serge	1619	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		1620	DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
		1621
5354	serge	1622	I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
4104	Serge	1623	POSTING_READ(DPLL_MD(crtc->pipe));
		1624
		1625	/* We do this three times for luck */
		1626	I915_WRITE(reg, dpll);
		1627	POSTING_READ(reg);
		1628	udelay(150); /* wait for warmup */
		1629	I915_WRITE(reg, dpll);
		1630	POSTING_READ(reg);
		1631	udelay(150); /* wait for warmup */
		1632	I915_WRITE(reg, dpll);
		1633	POSTING_READ(reg);
		1634	udelay(150); /* wait for warmup */
		1635	}
		1636
5354	serge	1637	static void chv_enable_pll(struct intel_crtc *crtc,
6084	serge	1638	const struct intel_crtc_state *pipe_config)
5060	serge	1639	{
		1640	struct drm_device *dev = crtc->base.dev;
		1641	struct drm_i915_private *dev_priv = dev->dev_private;
		1642	int pipe = crtc->pipe;
		1643	enum dpio_channel port = vlv_pipe_to_channel(pipe);
		1644	u32 tmp;
		1645
		1646	assert_pipe_disabled(dev_priv, crtc->pipe);
		1647
		1648	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
		1649
6084	serge	1650	mutex_lock(&dev_priv->sb_lock);
5060	serge	1651
		1652	/* Enable back the 10bit clock to display controller */
		1653	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
		1654	tmp \|= DPIO_DCLKP_EN;
		1655	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
		1656
6084	serge	1657	mutex_unlock(&dev_priv->sb_lock);
		1658
5060	serge	1659	/*
		1660	* Need to wait > 100ns between dclkp clock enable bit and PLL enable.
		1661	*/
		1662	udelay(1);
		1663
		1664	/* Enable PLL */
5354	serge	1665	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
5060	serge	1666
		1667	/* Check PLL is locked */
		1668	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		1669	DRM_ERROR("PLL %d failed to lock\n", pipe);
		1670
		1671	/* not sure when this should be written */
5354	serge	1672	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
5060	serge	1673	POSTING_READ(DPLL_MD(pipe));
		1674	}
		1675
5354	serge	1676	static int intel_num_dvo_pipes(struct drm_device *dev)
		1677	{
		1678	struct intel_crtc *crtc;
		1679	int count = 0;
		1680
		1681	for_each_intel_crtc(dev, crtc)
6084	serge	1682	count += crtc->base.state->active &&
5354	serge	1683	intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
		1684
		1685	return count;
		1686	}
		1687
4104	Serge	1688	static void i9xx_enable_pll(struct intel_crtc *crtc)
		1689	{
		1690	struct drm_device *dev = crtc->base.dev;
		1691	struct drm_i915_private *dev_priv = dev->dev_private;
		1692	int reg = DPLL(crtc->pipe);
6084	serge	1693	u32 dpll = crtc->config->dpll_hw_state.dpll;
4104	Serge	1694
		1695	assert_pipe_disabled(dev_priv, crtc->pipe);
		1696
		1697	/* No really, not for ILK+ */
5060	serge	1698	BUG_ON(INTEL_INFO(dev)->gen >= 5);
4104	Serge	1699
		1700	/* PLL is protected by panel, make sure we can write it */
		1701	if (IS_MOBILE(dev) && !IS_I830(dev))
		1702	assert_panel_unlocked(dev_priv, crtc->pipe);
		1703
5354	serge	1704	/* Enable DVO 2x clock on both PLLs if necessary */
		1705	if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
		1706	/*
		1707	* It appears to be important that we don't enable this
		1708	* for the current pipe before otherwise configuring the
		1709	* PLL. No idea how this should be handled if multiple
		1710	* DVO outputs are enabled simultaneosly.
		1711	*/
		1712	dpll \|= DPLL_DVO_2X_MODE;
		1713	I915_WRITE(DPLL(!crtc->pipe),
		1714	I915_READ(DPLL(!crtc->pipe)) \| DPLL_DVO_2X_MODE);
		1715	}
4104	Serge	1716
6084	serge	1717	/*
		1718	* Apparently we need to have VGA mode enabled prior to changing
		1719	* the P1/P2 dividers. Otherwise the DPLL will keep using the old
		1720	* dividers, even though the register value does change.
		1721	*/
		1722	I915_WRITE(reg, 0);
		1723
		1724	I915_WRITE(reg, dpll);
		1725
4104	Serge	1726	/* Wait for the clocks to stabilize. */
		1727	POSTING_READ(reg);
		1728	udelay(150);
		1729
		1730	if (INTEL_INFO(dev)->gen >= 4) {
		1731	I915_WRITE(DPLL_MD(crtc->pipe),
6084	serge	1732	crtc->config->dpll_hw_state.dpll_md);
4104	Serge	1733	} else {
		1734	/* The pixel multiplier can only be updated once the
		1735	* DPLL is enabled and the clocks are stable.
		1736	*
		1737	* So write it again.
		1738	*/
		1739	I915_WRITE(reg, dpll);
		1740	}
		1741
6084	serge	1742	/* We do this three times for luck */
4104	Serge	1743	I915_WRITE(reg, dpll);
6084	serge	1744	POSTING_READ(reg);
		1745	udelay(150); /* wait for warmup */
4104	Serge	1746	I915_WRITE(reg, dpll);
6084	serge	1747	POSTING_READ(reg);
		1748	udelay(150); /* wait for warmup */
4104	Serge	1749	I915_WRITE(reg, dpll);
6084	serge	1750	POSTING_READ(reg);
		1751	udelay(150); /* wait for warmup */
2327	Serge	1752	}
		1753
		1754	/**
4104	Serge	1755	* i9xx_disable_pll - disable a PLL
2327	Serge	1756	* @dev_priv: i915 private structure
		1757	* @pipe: pipe PLL to disable
		1758	*
		1759	* Disable the PLL for @pipe, making sure the pipe is off first.
		1760	*
		1761	* Note! This is for pre-ILK only.
		1762	*/
5354	serge	1763	static void i9xx_disable_pll(struct intel_crtc *crtc)
2327	Serge	1764	{
5354	serge	1765	struct drm_device *dev = crtc->base.dev;
		1766	struct drm_i915_private *dev_priv = dev->dev_private;
		1767	enum pipe pipe = crtc->pipe;
		1768
		1769	/* Disable DVO 2x clock on both PLLs if necessary */
		1770	if (IS_I830(dev) &&
		1771	intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
6084	serge	1772	!intel_num_dvo_pipes(dev)) {
5354	serge	1773	I915_WRITE(DPLL(PIPE_B),
		1774	I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
		1775	I915_WRITE(DPLL(PIPE_A),
		1776	I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
		1777	}
		1778
		1779	/* Don't disable pipe or pipe PLLs if needed */
		1780	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) \|\|
		1781	(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2327	Serge	1782	return;
		1783
		1784	/* Make sure the pipe isn't still relying on us */
		1785	assert_pipe_disabled(dev_priv, pipe);
		1786
6084	serge	1787	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
4104	Serge	1788	POSTING_READ(DPLL(pipe));
2327	Serge	1789	}
		1790
4539	Serge	1791	static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1792	{
6084	serge	1793	u32 val;
4539	Serge	1794
		1795	/* Make sure the pipe isn't still relying on us */
		1796	assert_pipe_disabled(dev_priv, pipe);
		1797
4560	Serge	1798	/*
		1799	* Leave integrated clock source and reference clock enabled for pipe B.
		1800	* The latter is needed for VGA hotplug / manual detection.
		1801	*/
6084	serge	1802	val = DPLL_VGA_MODE_DIS;
4539	Serge	1803	if (pipe == PIPE_B)
6084	serge	1804	val = DPLL_INTEGRATED_CRI_CLK_VLV \| DPLL_REF_CLK_ENABLE_VLV;
4539	Serge	1805	I915_WRITE(DPLL(pipe), val);
		1806	POSTING_READ(DPLL(pipe));
5060	serge	1807
4539	Serge	1808	}
		1809
5060	serge	1810	static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1811	{
		1812	enum dpio_channel port = vlv_pipe_to_channel(pipe);
		1813	u32 val;
		1814
		1815	/* Make sure the pipe isn't still relying on us */
		1816	assert_pipe_disabled(dev_priv, pipe);
		1817
		1818	/* Set PLL en = 0 */
6084	serge	1819	val = DPLL_SSC_REF_CLK_CHV \|
		1820	DPLL_REF_CLK_ENABLE_VLV \| DPLL_VGA_MODE_DIS;
5060	serge	1821	if (pipe != PIPE_A)
		1822	val \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		1823	I915_WRITE(DPLL(pipe), val);
		1824	POSTING_READ(DPLL(pipe));
		1825
6084	serge	1826	mutex_lock(&dev_priv->sb_lock);
5060	serge	1827
		1828	/* Disable 10bit clock to display controller */
		1829	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
		1830	val &= ~DPIO_DCLKP_EN;
		1831	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
		1832
6084	serge	1833	mutex_unlock(&dev_priv->sb_lock);
5060	serge	1834	}
		1835
4560	Serge	1836	void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
6084	serge	1837	struct intel_digital_port *dport,
		1838	unsigned int expected_mask)
3031	serge	1839	{
4104	Serge	1840	u32 port_mask;
5060	serge	1841	int dpll_reg;
3031	serge	1842
4560	Serge	1843	switch (dport->port) {
		1844	case PORT_B:
4104	Serge	1845	port_mask = DPLL_PORTB_READY_MASK;
5060	serge	1846	dpll_reg = DPLL(0);
4560	Serge	1847	break;
		1848	case PORT_C:
4104	Serge	1849	port_mask = DPLL_PORTC_READY_MASK;
5060	serge	1850	dpll_reg = DPLL(0);
6084	serge	1851	expected_mask <<= 4;
4560	Serge	1852	break;
5060	serge	1853	case PORT_D:
		1854	port_mask = DPLL_PORTD_READY_MASK;
		1855	dpll_reg = DPIO_PHY_STATUS;
		1856	break;
4560	Serge	1857	default:
		1858	BUG();
		1859	}
3243	Serge	1860
6084	serge	1861	if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
		1862	WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
		1863	port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
3031	serge	1864	}
		1865
5060	serge	1866	static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
		1867	{
		1868	struct drm_device *dev = crtc->base.dev;
		1869	struct drm_i915_private *dev_priv = dev->dev_private;
		1870	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
		1871
		1872	if (WARN_ON(pll == NULL))
		1873	return;
		1874
5354	serge	1875	WARN_ON(!pll->config.crtc_mask);
5060	serge	1876	if (pll->active == 0) {
		1877	DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
		1878	WARN_ON(pll->on);
		1879	assert_shared_dpll_disabled(dev_priv, pll);
		1880
		1881	pll->mode_set(dev_priv, pll);
		1882	}
		1883	}
		1884
2327	Serge	1885	/**
5060	serge	1886	* intel_enable_shared_dpll - enable PCH PLL
2327	Serge	1887	* @dev_priv: i915 private structure
		1888	* @pipe: pipe PLL to enable
		1889	*
		1890	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1891	* drives the transcoder clock.
		1892	*/
5060	serge	1893	static void intel_enable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1894	{
5060	serge	1895	struct drm_device *dev = crtc->base.dev;
		1896	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1897	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1898
4104	Serge	1899	if (WARN_ON(pll == NULL))
2342	Serge	1900	return;
		1901
5354	serge	1902	if (WARN_ON(pll->config.crtc_mask == 0))
3031	serge	1903	return;
2327	Serge	1904
5354	serge	1905	DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
4104	Serge	1906	pll->name, pll->active, pll->on,
		1907	crtc->base.base.id);
3031	serge	1908
4104	Serge	1909	if (pll->active++) {
		1910	WARN_ON(!pll->on);
		1911	assert_shared_dpll_enabled(dev_priv, pll);
3031	serge	1912	return;
		1913	}
4104	Serge	1914	WARN_ON(pll->on);
3031	serge	1915
5060	serge	1916	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
		1917
4104	Serge	1918	DRM_DEBUG_KMS("enabling %s\n", pll->name);
		1919	pll->enable(dev_priv, pll);
3031	serge	1920	pll->on = true;
2327	Serge	1921	}
		1922
5354	serge	1923	static void intel_disable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1924	{
5060	serge	1925	struct drm_device *dev = crtc->base.dev;
		1926	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1927	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1928
		1929	/* PCH only available on ILK+ */
6084	serge	1930	if (INTEL_INFO(dev)->gen < 5)
		1931	return;
2327	Serge	1932
6084	serge	1933	if (pll == NULL)
3031	serge	1934	return;
2327	Serge	1935
6084	serge	1936	if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
		1937	return;
		1938
4104	Serge	1939	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
		1940	pll->name, pll->active, pll->on,
		1941	crtc->base.base.id);
2342	Serge	1942
3031	serge	1943	if (WARN_ON(pll->active == 0)) {
4104	Serge	1944	assert_shared_dpll_disabled(dev_priv, pll);
3031	serge	1945	return;
		1946	}
2342	Serge	1947
4104	Serge	1948	assert_shared_dpll_enabled(dev_priv, pll);
		1949	WARN_ON(!pll->on);
		1950	if (--pll->active)
2342	Serge	1951	return;
		1952
4104	Serge	1953	DRM_DEBUG_KMS("disabling %s\n", pll->name);
		1954	pll->disable(dev_priv, pll);
3031	serge	1955	pll->on = false;
5060	serge	1956
		1957	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2327	Serge	1958	}
		1959
3243	Serge	1960	static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
6084	serge	1961	enum pipe pipe)
2327	Serge	1962	{
3243	Serge	1963	struct drm_device *dev = dev_priv->dev;
3031	serge	1964	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4104	Serge	1965	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	1966	uint32_t reg, val, pipeconf_val;
2327	Serge	1967
		1968	/* PCH only available on ILK+ */
5354	serge	1969	BUG_ON(!HAS_PCH_SPLIT(dev));
2327	Serge	1970
		1971	/* Make sure PCH DPLL is enabled */
4104	Serge	1972	assert_shared_dpll_enabled(dev_priv,
		1973	intel_crtc_to_shared_dpll(intel_crtc));
2327	Serge	1974
		1975	/* FDI must be feeding us bits for PCH ports */
		1976	assert_fdi_tx_enabled(dev_priv, pipe);
		1977	assert_fdi_rx_enabled(dev_priv, pipe);
		1978
3243	Serge	1979	if (HAS_PCH_CPT(dev)) {
		1980	/* Workaround: Set the timing override bit before enabling the
		1981	* pch transcoder. */
		1982	reg = TRANS_CHICKEN2(pipe);
		1983	val = I915_READ(reg);
		1984	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1985	I915_WRITE(reg, val);
3031	serge	1986	}
3243	Serge	1987
4104	Serge	1988	reg = PCH_TRANSCONF(pipe);
2327	Serge	1989	val = I915_READ(reg);
3031	serge	1990	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1991
		1992	if (HAS_PCH_IBX(dev_priv->dev)) {
		1993	/*
6084	serge	1994	* Make the BPC in transcoder be consistent with
		1995	* that in pipeconf reg. For HDMI we must use 8bpc
		1996	* here for both 8bpc and 12bpc.
2327	Serge	1997	*/
3480	Serge	1998	val &= ~PIPECONF_BPC_MASK;
6084	serge	1999	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
		2000	val \|= PIPECONF_8BPC;
		2001	else
		2002	val \|= pipeconf_val & PIPECONF_BPC_MASK;
2327	Serge	2003	}
3031	serge	2004
		2005	val &= ~TRANS_INTERLACE_MASK;
		2006	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		2007	if (HAS_PCH_IBX(dev_priv->dev) &&
5354	serge	2008	intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
3031	serge	2009	val \|= TRANS_LEGACY_INTERLACED_ILK;
		2010	else
		2011	val \|= TRANS_INTERLACED;
		2012	else
		2013	val \|= TRANS_PROGRESSIVE;
		2014
2327	Serge	2015	I915_WRITE(reg, val \| TRANS_ENABLE);
		2016	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4104	Serge	2017	DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2327	Serge	2018	}
		2019
3243	Serge	2020	static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
		2021	enum transcoder cpu_transcoder)
		2022	{
		2023	u32 val, pipeconf_val;
		2024
		2025	/* PCH only available on ILK+ */
5354	serge	2026	BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
3243	Serge	2027
		2028	/* FDI must be feeding us bits for PCH ports */
3480	Serge	2029	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
3243	Serge	2030	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
		2031
		2032	/* Workaround: set timing override bit. */
6084	serge	2033	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
3243	Serge	2034	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
6084	serge	2035	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
3243	Serge	2036
		2037	val = TRANS_ENABLE;
		2038	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
		2039
		2040	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
		2041	PIPECONF_INTERLACED_ILK)
		2042	val \|= TRANS_INTERLACED;
		2043	else
		2044	val \|= TRANS_PROGRESSIVE;
		2045
4104	Serge	2046	I915_WRITE(LPT_TRANSCONF, val);
		2047	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
3243	Serge	2048	DRM_ERROR("Failed to enable PCH transcoder\n");
		2049	}
		2050
		2051	static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
6084	serge	2052	enum pipe pipe)
2327	Serge	2053	{
3243	Serge	2054	struct drm_device *dev = dev_priv->dev;
		2055	uint32_t reg, val;
2327	Serge	2056
		2057	/* FDI relies on the transcoder */
		2058	assert_fdi_tx_disabled(dev_priv, pipe);
		2059	assert_fdi_rx_disabled(dev_priv, pipe);
		2060
		2061	/* Ports must be off as well */
		2062	assert_pch_ports_disabled(dev_priv, pipe);
		2063
4104	Serge	2064	reg = PCH_TRANSCONF(pipe);
2327	Serge	2065	val = I915_READ(reg);
		2066	val &= ~TRANS_ENABLE;
		2067	I915_WRITE(reg, val);
		2068	/* wait for PCH transcoder off, transcoder state */
		2069	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4104	Serge	2070	DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
3243	Serge	2071
		2072	if (!HAS_PCH_IBX(dev)) {
		2073	/* Workaround: Clear the timing override chicken bit again. */
		2074	reg = TRANS_CHICKEN2(pipe);
		2075	val = I915_READ(reg);
		2076	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		2077	I915_WRITE(reg, val);
		2078	}
2327	Serge	2079	}
		2080
3243	Serge	2081	static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
		2082	{
		2083	u32 val;
		2084
4104	Serge	2085	val = I915_READ(LPT_TRANSCONF);
3243	Serge	2086	val &= ~TRANS_ENABLE;
4104	Serge	2087	I915_WRITE(LPT_TRANSCONF, val);
3243	Serge	2088	/* wait for PCH transcoder off, transcoder state */
4104	Serge	2089	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
3243	Serge	2090	DRM_ERROR("Failed to disable PCH transcoder\n");
		2091
		2092	/* Workaround: clear timing override bit. */
6084	serge	2093	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
3243	Serge	2094	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
6084	serge	2095	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
3243	Serge	2096	}
		2097
2327	Serge	2098	/**
		2099	* intel_enable_pipe - enable a pipe, asserting requirements
5060	serge	2100	* @crtc: crtc responsible for the pipe
2327	Serge	2101	*
5060	serge	2102	* Enable @crtc's pipe, making sure that various hardware specific requirements
2327	Serge	2103	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		2104	*/
5060	serge	2105	static void intel_enable_pipe(struct intel_crtc *crtc)
2327	Serge	2106	{
5060	serge	2107	struct drm_device *dev = crtc->base.dev;
		2108	struct drm_i915_private *dev_priv = dev->dev_private;
		2109	enum pipe pipe = crtc->pipe;
3243	Serge	2110	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		2111	pipe);
3480	Serge	2112	enum pipe pch_transcoder;
2327	Serge	2113	int reg;
		2114	u32 val;
		2115
6084	serge	2116	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
		2117
4104	Serge	2118	assert_planes_disabled(dev_priv, pipe);
4560	Serge	2119	assert_cursor_disabled(dev_priv, pipe);
4104	Serge	2120	assert_sprites_disabled(dev_priv, pipe);
		2121
3480	Serge	2122	if (HAS_PCH_LPT(dev_priv->dev))
3243	Serge	2123	pch_transcoder = TRANSCODER_A;
		2124	else
		2125	pch_transcoder = pipe;
		2126
2327	Serge	2127	/*
		2128	* A pipe without a PLL won't actually be able to drive bits from
		2129	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		2130	* need the check.
		2131	*/
6084	serge	2132	if (HAS_GMCH_DISPLAY(dev_priv->dev))
5354	serge	2133	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4560	Serge	2134	assert_dsi_pll_enabled(dev_priv);
		2135	else
6084	serge	2136	assert_pll_enabled(dev_priv, pipe);
2327	Serge	2137	else {
6084	serge	2138	if (crtc->config->has_pch_encoder) {
2327	Serge	2139	/* if driving the PCH, we need FDI enabled */
3243	Serge	2140	assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
3480	Serge	2141	assert_fdi_tx_pll_enabled(dev_priv,
		2142	(enum pipe) cpu_transcoder);
2327	Serge	2143	}
		2144	/* FIXME: assert CPU port conditions for SNB+ */
		2145	}
		2146
3243	Serge	2147	reg = PIPECONF(cpu_transcoder);
2327	Serge	2148	val = I915_READ(reg);
5060	serge	2149	if (val & PIPECONF_ENABLE) {
5354	serge	2150	WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) \|\|
		2151	(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2327	Serge	2152	return;
5060	serge	2153	}
2327	Serge	2154
		2155	I915_WRITE(reg, val \| PIPECONF_ENABLE);
5060	serge	2156	POSTING_READ(reg);
2327	Serge	2157	}
		2158
		2159	/**
		2160	* intel_disable_pipe - disable a pipe, asserting requirements
5354	serge	2161	* @crtc: crtc whose pipes is to be disabled
2327	Serge	2162	*
5354	serge	2163	* Disable the pipe of @crtc, making sure that various hardware
		2164	* specific requirements are met, if applicable, e.g. plane
		2165	* disabled, panel fitter off, etc.
2327	Serge	2166	*
		2167	* Will wait until the pipe has shut down before returning.
		2168	*/
5354	serge	2169	static void intel_disable_pipe(struct intel_crtc *crtc)
2327	Serge	2170	{
5354	serge	2171	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6084	serge	2172	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
5354	serge	2173	enum pipe pipe = crtc->pipe;
2327	Serge	2174	int reg;
		2175	u32 val;
		2176
6084	serge	2177	DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
		2178
		2179	/*
2327	Serge	2180	* Make sure planes won't keep trying to pump pixels to us,
		2181	* or we might hang the display.
		2182	*/
		2183	assert_planes_disabled(dev_priv, pipe);
4560	Serge	2184	assert_cursor_disabled(dev_priv, pipe);
3746	Serge	2185	assert_sprites_disabled(dev_priv, pipe);
2327	Serge	2186
3243	Serge	2187	reg = PIPECONF(cpu_transcoder);
2327	Serge	2188	val = I915_READ(reg);
		2189	if ((val & PIPECONF_ENABLE) == 0)
		2190	return;
		2191
5354	serge	2192	/*
		2193	* Double wide has implications for planes
		2194	* so best keep it disabled when not needed.
		2195	*/
6084	serge	2196	if (crtc->config->double_wide)
5354	serge	2197	val &= ~PIPECONF_DOUBLE_WIDE;
		2198
		2199	/* Don't disable pipe or pipe PLLs if needed */
		2200	if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
		2201	!(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
		2202	val &= ~PIPECONF_ENABLE;
		2203
		2204	I915_WRITE(reg, val);
		2205	if ((val & PIPECONF_ENABLE) == 0)
		2206	intel_wait_for_pipe_off(crtc);
2327	Serge	2207	}
		2208
6084	serge	2209	static bool need_vtd_wa(struct drm_device *dev)
2327	Serge	2210	{
6084	serge	2211	#ifdef CONFIG_INTEL_IOMMU
		2212	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		2213	return true;
		2214	#endif
		2215	return false;
2327	Serge	2216	}
		2217
6084	serge	2218	unsigned int
		2219	intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
		2220	uint64_t fb_format_modifier, unsigned int plane)
2327	Serge	2221	{
6084	serge	2222	unsigned int tile_height;
		2223	uint32_t pixel_bytes;
2327	Serge	2224
6084	serge	2225	switch (fb_format_modifier) {
		2226	case DRM_FORMAT_MOD_NONE:
		2227	tile_height = 1;
		2228	break;
		2229	case I915_FORMAT_MOD_X_TILED:
		2230	tile_height = IS_GEN2(dev) ? 16 : 8;
		2231	break;
		2232	case I915_FORMAT_MOD_Y_TILED:
		2233	tile_height = 32;
		2234	break;
		2235	case I915_FORMAT_MOD_Yf_TILED:
		2236	pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
		2237	switch (pixel_bytes) {
		2238	default:
		2239	case 1:
		2240	tile_height = 64;
		2241	break;
		2242	case 2:
		2243	case 4:
		2244	tile_height = 32;
		2245	break;
		2246	case 8:
		2247	tile_height = 16;
		2248	break;
		2249	case 16:
		2250	WARN_ONCE(1,
		2251	"128-bit pixels are not supported for display!");
		2252	tile_height = 16;
		2253	break;
		2254	}
		2255	break;
		2256	default:
		2257	MISSING_CASE(fb_format_modifier);
		2258	tile_height = 1;
		2259	break;
		2260	}
2327	Serge	2261
6084	serge	2262	return tile_height;
		2263	}
4560	Serge	2264
6084	serge	2265	unsigned int
		2266	intel_fb_align_height(struct drm_device *dev, unsigned int height,
		2267	uint32_t pixel_format, uint64_t fb_format_modifier)
		2268	{
		2269	return ALIGN(height, intel_tile_height(dev, pixel_format,
		2270	fb_format_modifier, 0));
2327	Serge	2271	}
		2272
6084	serge	2273	static int
		2274	intel_fill_fb_ggtt_view(struct i915_ggtt_view view, struct drm_framebuffer fb,
		2275	const struct drm_plane_state *plane_state)
2327	Serge	2276	{
6084	serge	2277	struct intel_rotation_info *info = &view->rotation_info;
		2278	unsigned int tile_height, tile_pitch;
2327	Serge	2279
6084	serge	2280	*view = i915_ggtt_view_normal;
5354	serge	2281
6084	serge	2282	if (!plane_state)
		2283	return 0;
4560	Serge	2284
6084	serge	2285	if (!intel_rotation_90_or_270(plane_state->rotation))
		2286	return 0;
4560	Serge	2287
6084	serge	2288	*view = i915_ggtt_view_rotated;
2327	Serge	2289
6084	serge	2290	info->height = fb->height;
		2291	info->pixel_format = fb->pixel_format;
		2292	info->pitch = fb->pitches[0];
		2293	info->uv_offset = fb->offsets[1];
		2294	info->fb_modifier = fb->modifier[0];
		2295
		2296	tile_height = intel_tile_height(fb->dev, fb->pixel_format,
		2297	fb->modifier[0], 0);
		2298	tile_pitch = PAGE_SIZE / tile_height;
		2299	info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
		2300	info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
		2301	info->size = info->width_pages * info->height_pages * PAGE_SIZE;
		2302
		2303	if (info->pixel_format == DRM_FORMAT_NV12) {
		2304	tile_height = intel_tile_height(fb->dev, fb->pixel_format,
		2305	fb->modifier[0], 1);
		2306	tile_pitch = PAGE_SIZE / tile_height;
		2307	info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
		2308	info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
		2309	tile_height);
		2310	info->size_uv = info->width_pages_uv * info->height_pages_uv *
		2311	PAGE_SIZE;
		2312	}
		2313
		2314	return 0;
3746	Serge	2315	}
		2316
6084	serge	2317	static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
5060	serge	2318	{
6084	serge	2319	if (INTEL_INFO(dev_priv)->gen >= 9)
		2320	return 256 * 1024;
		2321	else if (IS_BROADWATER(dev_priv) \|\| IS_CRESTLINE(dev_priv) \|\|
		2322	IS_VALLEYVIEW(dev_priv))
		2323	return 128 * 1024;
		2324	else if (INTEL_INFO(dev_priv)->gen >= 4)
		2325	return 4 * 1024;
		2326	else
		2327	return 0;
5060	serge	2328	}
		2329
2335	Serge	2330	int
5354	serge	2331	intel_pin_and_fence_fb_obj(struct drm_plane *plane,
		2332	struct drm_framebuffer *fb,
6084	serge	2333	const struct drm_plane_state *plane_state,
		2334	struct intel_engine_cs *pipelined,
		2335	struct drm_i915_gem_request **pipelined_request)
2335	Serge	2336	{
5354	serge	2337	struct drm_device *dev = fb->dev;
2335	Serge	2338	struct drm_i915_private *dev_priv = dev->dev_private;
5354	serge	2339	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6084	serge	2340	struct i915_ggtt_view view;
2335	Serge	2341	u32 alignment;
		2342	int ret;
2327	Serge	2343
5060	serge	2344	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
		2345
6084	serge	2346	switch (fb->modifier[0]) {
		2347	case DRM_FORMAT_MOD_NONE:
		2348	alignment = intel_linear_alignment(dev_priv);
2335	Serge	2349	break;
6084	serge	2350	case I915_FORMAT_MOD_X_TILED:
5354	serge	2351	if (INTEL_INFO(dev)->gen >= 9)
		2352	alignment = 256 * 1024;
		2353	else {
6084	serge	2354	/* pin() will align the object as required by fence */
		2355	alignment = 0;
5354	serge	2356	}
2335	Serge	2357	break;
6084	serge	2358	case I915_FORMAT_MOD_Y_TILED:
		2359	case I915_FORMAT_MOD_Yf_TILED:
		2360	if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
		2361	"Y tiling bo slipped through, driver bug!\n"))
		2362	return -EINVAL;
		2363	alignment = 1 * 1024 * 1024;
		2364	break;
		2365	default:
		2366	MISSING_CASE(fb->modifier[0]);
2335	Serge	2367	return -EINVAL;
		2368	}
2327	Serge	2369
6084	serge	2370	ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
		2371	if (ret)
		2372	return ret;
		2373
3746	Serge	2374	/* Note that the w/a also requires 64 PTE of padding following the
		2375	* bo. We currently fill all unused PTE with the shadow page and so
		2376	* we should always have valid PTE following the scanout preventing
		2377	* the VT-d warning.
		2378	*/
		2379	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		2380	alignment = 256 * 1024;
		2381
5097	serge	2382	/*
		2383	* Global gtt pte registers are special registers which actually forward
		2384	* writes to a chunk of system memory. Which means that there is no risk
		2385	* that the register values disappear as soon as we call
		2386	* intel_runtime_pm_put(), so it is correct to wrap only the
		2387	* pin/unpin/fence and not more.
		2388	*/
		2389	intel_runtime_pm_get(dev_priv);
		2390
2335	Serge	2391	dev_priv->mm.interruptible = false;
6084	serge	2392	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
		2393	pipelined_request, &view);
2335	Serge	2394	if (ret)
		2395	goto err_interruptible;
2327	Serge	2396
2335	Serge	2397	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		2398	* fence, whereas 965+ only requires a fence if using
		2399	* framebuffer compression. For simplicity, we always install
		2400	* a fence as the cost is not that onerous.
		2401	*/
6084	serge	2402	if (view.type == I915_GGTT_VIEW_NORMAL) {
		2403	ret = i915_gem_object_get_fence(obj);
		2404	if (ret == -EDEADLK) {
		2405	/*
		2406	* -EDEADLK means there are no free fences
		2407	* no pending flips.
		2408	*
		2409	* This is propagated to atomic, but it uses
		2410	* -EDEADLK to force a locking recovery, so
		2411	* change the returned error to -EBUSY.
		2412	*/
		2413	ret = -EBUSY;
		2414	goto err_unpin;
		2415	} else if (ret)
		2416	goto err_unpin;
2327	Serge	2417
6084	serge	2418	i915_gem_object_pin_fence(obj);
		2419	}
3480	Serge	2420
2335	Serge	2421	dev_priv->mm.interruptible = true;
5097	serge	2422	intel_runtime_pm_put(dev_priv);
2335	Serge	2423	return 0;
2327	Serge	2424
2335	Serge	2425	err_unpin:
6084	serge	2426	i915_gem_object_unpin_from_display_plane(obj, &view);
2335	Serge	2427	err_interruptible:
		2428	dev_priv->mm.interruptible = true;
5097	serge	2429	intel_runtime_pm_put(dev_priv);
2335	Serge	2430	return ret;
		2431	}
2327	Serge	2432
6084	serge	2433	static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
		2434	const struct drm_plane_state *plane_state)
3031	serge	2435	{
6084	serge	2436	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
		2437	struct i915_ggtt_view view;
		2438	int ret;
		2439
5060	serge	2440	WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
		2441
6084	serge	2442	ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
		2443	WARN_ONCE(ret, "Couldn't get view from plane state!");
		2444
		2445	if (view.type == I915_GGTT_VIEW_NORMAL)
		2446	i915_gem_object_unpin_fence(obj);
		2447
		2448	i915_gem_object_unpin_from_display_plane(obj, &view);
3031	serge	2449	}
		2450
		2451	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		2452	* is assumed to be a power-of-two. */
6084	serge	2453	unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
		2454	int x, int y,
3480	Serge	2455	unsigned int tiling_mode,
		2456	unsigned int cpp,
6084	serge	2457	unsigned int pitch)
3031	serge	2458	{
3480	Serge	2459	if (tiling_mode != I915_TILING_NONE) {
		2460	unsigned int tile_rows, tiles;
3031	serge	2461
6084	serge	2462	tile_rows = *y / 8;
		2463	*y %= 8;
3031	serge	2464
3480	Serge	2465	tiles = *x / (512/cpp);
		2466	*x %= 512/cpp;
		2467
6084	serge	2468	return tile_rows * pitch * 8 + tiles * 4096;
3480	Serge	2469	} else {
6084	serge	2470	unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
3480	Serge	2471	unsigned int offset;
		2472
		2473	offset = y pitch + x cpp;
6084	serge	2474	*y = (offset & alignment) / pitch;
		2475	x = ((offset & alignment) - y * pitch) / cpp;
		2476	return offset & ~alignment;
3480	Serge	2477	}
3031	serge	2478	}
		2479
6084	serge	2480	static int i9xx_format_to_fourcc(int format)
2327	Serge	2481	{
5060	serge	2482	switch (format) {
		2483	case DISPPLANE_8BPP:
		2484	return DRM_FORMAT_C8;
		2485	case DISPPLANE_BGRX555:
		2486	return DRM_FORMAT_XRGB1555;
		2487	case DISPPLANE_BGRX565:
		2488	return DRM_FORMAT_RGB565;
		2489	default:
		2490	case DISPPLANE_BGRX888:
		2491	return DRM_FORMAT_XRGB8888;
		2492	case DISPPLANE_RGBX888:
		2493	return DRM_FORMAT_XBGR8888;
		2494	case DISPPLANE_BGRX101010:
		2495	return DRM_FORMAT_XRGB2101010;
		2496	case DISPPLANE_RGBX101010:
		2497	return DRM_FORMAT_XBGR2101010;
		2498	}
		2499	}
		2500
6084	serge	2501	static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
5060	serge	2502	{
6084	serge	2503	switch (format) {
		2504	case PLANE_CTL_FORMAT_RGB_565:
		2505	return DRM_FORMAT_RGB565;
		2506	default:
		2507	case PLANE_CTL_FORMAT_XRGB_8888:
		2508	if (rgb_order) {
		2509	if (alpha)
		2510	return DRM_FORMAT_ABGR8888;
		2511	else
		2512	return DRM_FORMAT_XBGR8888;
		2513	} else {
		2514	if (alpha)
		2515	return DRM_FORMAT_ARGB8888;
		2516	else
		2517	return DRM_FORMAT_XRGB8888;
		2518	}
		2519	case PLANE_CTL_FORMAT_XRGB_2101010:
		2520	if (rgb_order)
		2521	return DRM_FORMAT_XBGR2101010;
		2522	else
		2523	return DRM_FORMAT_XRGB2101010;
		2524	}
		2525	}
		2526
		2527	static bool
		2528	intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
		2529	struct intel_initial_plane_config *plane_config)
		2530	{
5060	serge	2531	struct drm_device *dev = crtc->base.dev;
6084	serge	2532	struct drm_i915_private *dev_priv = to_i915(dev);
5060	serge	2533	struct drm_i915_gem_object *obj = NULL;
		2534	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6084	serge	2535	struct drm_framebuffer *fb = &plane_config->fb->base;
		2536	u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
		2537	u32 size_aligned = round_up(plane_config->base + plane_config->size,
		2538	PAGE_SIZE);
5060	serge	2539
6084	serge	2540	size_aligned -= base_aligned;
		2541
5060	serge	2542	if (plane_config->size == 0)
		2543	return false;
		2544
6084	serge	2545	/* If the FB is too big, just don't use it since fbdev is not very
		2546	* important and we should probably use that space with FBC or other
		2547	* features. */
		2548	if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
		2549	return false;
		2550
		2551	obj = i915_gem_object_create_stolen_for_preallocated(dev,
		2552	base_aligned,
		2553	base_aligned,
		2554	size_aligned);
5060	serge	2555	if (!obj)
		2556	return false;
		2557
6084	serge	2558	obj->tiling_mode = plane_config->tiling;
		2559	if (obj->tiling_mode == I915_TILING_X)
		2560	obj->stride = fb->pitches[0];
5060	serge	2561
6084	serge	2562	mode_cmd.pixel_format = fb->pixel_format;
		2563	mode_cmd.width = fb->width;
		2564	mode_cmd.height = fb->height;
		2565	mode_cmd.pitches[0] = fb->pitches[0];
		2566	mode_cmd.modifier[0] = fb->modifier[0];
		2567	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
5060	serge	2568
		2569	mutex_lock(&dev->struct_mutex);
6084	serge	2570	if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
5060	serge	2571	&mode_cmd, obj)) {
		2572	DRM_DEBUG_KMS("intel fb init failed\n");
		2573	goto out_unref_obj;
		2574	}
		2575	mutex_unlock(&dev->struct_mutex);
		2576
6084	serge	2577	DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
5060	serge	2578	return true;
		2579
		2580	out_unref_obj:
		2581	drm_gem_object_unreference(&obj->base);
		2582	mutex_unlock(&dev->struct_mutex);
		2583	return false;
		2584	}
		2585
6084	serge	2586	/* Update plane->state->fb to match plane->fb after driver-internal updates */
		2587	static void
		2588	update_state_fb(struct drm_plane *plane)
5060	serge	2589	{
6084	serge	2590	if (plane->fb == plane->state->fb)
		2591	return;
		2592
		2593	if (plane->state->fb)
		2594	drm_framebuffer_unreference(plane->state->fb);
		2595	plane->state->fb = plane->fb;
		2596	if (plane->state->fb)
		2597	drm_framebuffer_reference(plane->state->fb);
		2598	}
		2599
		2600	static void
		2601	intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
		2602	struct intel_initial_plane_config *plane_config)
		2603	{
5060	serge	2604	struct drm_device *dev = intel_crtc->base.dev;
5354	serge	2605	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	2606	struct drm_crtc *c;
		2607	struct intel_crtc *i;
		2608	struct drm_i915_gem_object *obj;
6084	serge	2609	struct drm_plane *primary = intel_crtc->base.primary;
		2610	struct drm_plane_state *plane_state = primary->state;
		2611	struct drm_crtc_state *crtc_state = intel_crtc->base.state;
		2612	struct intel_plane *intel_plane = to_intel_plane(primary);
		2613	struct drm_framebuffer *fb;
5060	serge	2614
6084	serge	2615	if (!plane_config->fb)
5060	serge	2616	return;
		2617
6084	serge	2618	if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
		2619	fb = &plane_config->fb->base;
		2620	goto valid_fb;
		2621	}
5060	serge	2622
6084	serge	2623	kfree(plane_config->fb);
5060	serge	2624
		2625	/*
		2626	* Failed to alloc the obj, check to see if we should share
		2627	* an fb with another CRTC instead
		2628	*/
		2629	for_each_crtc(dev, c) {
		2630	i = to_intel_crtc(c);
		2631
		2632	if (c == &intel_crtc->base)
		2633	continue;
		2634
		2635	if (!i->active)
		2636	continue;
		2637
6084	serge	2638	fb = c->primary->fb;
		2639	if (!fb)
5060	serge	2640	continue;
		2641
6084	serge	2642	obj = intel_fb_obj(fb);
5060	serge	2643	if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
6084	serge	2644	drm_framebuffer_reference(fb);
		2645	goto valid_fb;
5060	serge	2646	}
		2647	}
6084	serge	2648
		2649	/*
		2650	* We've failed to reconstruct the BIOS FB. Current display state
		2651	* indicates that the primary plane is visible, but has a NULL FB,
		2652	* which will lead to problems later if we don't fix it up. The
		2653	* simplest solution is to just disable the primary plane now and
		2654	* pretend the BIOS never had it enabled.
		2655	*/
		2656	to_intel_plane_state(plane_state)->visible = false;
		2657	crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
		2658	intel_pre_disable_primary(&intel_crtc->base);
		2659	intel_plane->disable_plane(primary, &intel_crtc->base);
		2660
		2661	return;
		2662
		2663	valid_fb:
		2664	plane_state->src_x = 0;
		2665	plane_state->src_y = 0;
		2666	plane_state->src_w = fb->width << 16;
		2667	plane_state->src_h = fb->height << 16;
		2668
		2669	plane_state->crtc_x = 0;
		2670	plane_state->crtc_y = 0;
		2671	plane_state->crtc_w = fb->width;
		2672	plane_state->crtc_h = fb->height;
		2673
		2674	obj = intel_fb_obj(fb);
		2675	if (obj->tiling_mode != I915_TILING_NONE)
		2676	dev_priv->preserve_bios_swizzle = true;
		2677
		2678	drm_framebuffer_reference(fb);
		2679	primary->fb = primary->state->fb = fb;
		2680	primary->crtc = primary->state->crtc = &intel_crtc->base;
		2681	intel_crtc->base.state->plane_mask \|= (1 << drm_plane_index(primary));
		2682	obj->frontbuffer_bits \|= to_intel_plane(primary)->frontbuffer_bit;
5060	serge	2683	}
		2684
		2685	static void i9xx_update_primary_plane(struct drm_crtc *crtc,
6084	serge	2686	struct drm_framebuffer *fb,
		2687	int x, int y)
5060	serge	2688	{
6084	serge	2689	struct drm_device *dev = crtc->dev;
		2690	struct drm_i915_private *dev_priv = dev->dev_private;
		2691	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2692	struct drm_plane *primary = crtc->primary;
		2693	bool visible = to_intel_plane_state(primary->state)->visible;
5354	serge	2694	struct drm_i915_gem_object *obj;
6084	serge	2695	int plane = intel_crtc->plane;
3031	serge	2696	unsigned long linear_offset;
6084	serge	2697	u32 dspcntr;
5354	serge	2698	u32 reg = DSPCNTR(plane);
		2699	int pixel_size;
2327	Serge	2700
6084	serge	2701	if (!visible \|\| !fb) {
5354	serge	2702	I915_WRITE(reg, 0);
		2703	if (INTEL_INFO(dev)->gen >= 4)
		2704	I915_WRITE(DSPSURF(plane), 0);
		2705	else
		2706	I915_WRITE(DSPADDR(plane), 0);
		2707	POSTING_READ(reg);
		2708	return;
		2709	}
		2710
		2711	obj = intel_fb_obj(fb);
		2712	if (WARN_ON(obj == NULL))
		2713	return;
		2714
		2715	pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
		2716
		2717	dspcntr = DISPPLANE_GAMMA_ENABLE;
		2718
		2719	dspcntr \|= DISPLAY_PLANE_ENABLE;
		2720
		2721	if (INTEL_INFO(dev)->gen < 4) {
		2722	if (intel_crtc->pipe == PIPE_B)
		2723	dspcntr \|= DISPPLANE_SEL_PIPE_B;
		2724
		2725	/* pipesrc and dspsize control the size that is scaled from,
		2726	* which should always be the user's requested size.
		2727	*/
		2728	I915_WRITE(DSPSIZE(plane),
6084	serge	2729	((intel_crtc->config->pipe_src_h - 1) << 16) \|
		2730	(intel_crtc->config->pipe_src_w - 1));
5354	serge	2731	I915_WRITE(DSPPOS(plane), 0);
		2732	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
		2733	I915_WRITE(PRIMSIZE(plane),
6084	serge	2734	((intel_crtc->config->pipe_src_h - 1) << 16) \|
		2735	(intel_crtc->config->pipe_src_w - 1));
5354	serge	2736	I915_WRITE(PRIMPOS(plane), 0);
		2737	I915_WRITE(PRIMCNSTALPHA(plane), 0);
		2738	}
		2739
3243	Serge	2740	switch (fb->pixel_format) {
		2741	case DRM_FORMAT_C8:
6084	serge	2742	dspcntr \|= DISPPLANE_8BPP;
		2743	break;
3243	Serge	2744	case DRM_FORMAT_XRGB1555:
		2745	dspcntr \|= DISPPLANE_BGRX555;
		2746	break;
		2747	case DRM_FORMAT_RGB565:
		2748	dspcntr \|= DISPPLANE_BGRX565;
		2749	break;
		2750	case DRM_FORMAT_XRGB8888:
		2751	dspcntr \|= DISPPLANE_BGRX888;
		2752	break;
		2753	case DRM_FORMAT_XBGR8888:
		2754	dspcntr \|= DISPPLANE_RGBX888;
		2755	break;
		2756	case DRM_FORMAT_XRGB2101010:
		2757	dspcntr \|= DISPPLANE_BGRX101010;
6084	serge	2758	break;
3243	Serge	2759	case DRM_FORMAT_XBGR2101010:
		2760	dspcntr \|= DISPPLANE_RGBX101010;
6084	serge	2761	break;
		2762	default:
3746	Serge	2763	BUG();
6084	serge	2764	}
3243	Serge	2765
5354	serge	2766	if (INTEL_INFO(dev)->gen >= 4 &&
		2767	obj->tiling_mode != I915_TILING_NONE)
6084	serge	2768	dspcntr \|= DISPPLANE_TILED;
2327	Serge	2769
4104	Serge	2770	if (IS_G4X(dev))
		2771	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2772
5354	serge	2773	linear_offset = y * fb->pitches[0] + x * pixel_size;
2327	Serge	2774
3031	serge	2775	if (INTEL_INFO(dev)->gen >= 4) {
		2776	intel_crtc->dspaddr_offset =
6084	serge	2777	intel_gen4_compute_page_offset(dev_priv,
		2778	&x, &y, obj->tiling_mode,
5354	serge	2779	pixel_size,
6084	serge	2780	fb->pitches[0]);
3031	serge	2781	linear_offset -= intel_crtc->dspaddr_offset;
		2782	} else {
		2783	intel_crtc->dspaddr_offset = linear_offset;
		2784	}
		2785
6084	serge	2786	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
5354	serge	2787	dspcntr \|= DISPPLANE_ROTATE_180;
		2788
6084	serge	2789	x += (intel_crtc->config->pipe_src_w - 1);
		2790	y += (intel_crtc->config->pipe_src_h - 1);
5354	serge	2791
		2792	/* Finding the last pixel of the last line of the display
		2793	data and adding to linear_offset*/
		2794	linear_offset +=
6084	serge	2795	(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
		2796	(intel_crtc->config->pipe_src_w - 1) * pixel_size;
5354	serge	2797	}
		2798
6084	serge	2799	intel_crtc->adjusted_x = x;
		2800	intel_crtc->adjusted_y = y;
		2801
5354	serge	2802	I915_WRITE(reg, dspcntr);
		2803
2342	Serge	2804	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
6084	serge	2805	if (INTEL_INFO(dev)->gen >= 4) {
4560	Serge	2806	I915_WRITE(DSPSURF(plane),
6084	serge	2807	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
		2808	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2809	I915_WRITE(DSPLINOFF(plane), linear_offset);
6084	serge	2810	} else
4104	Serge	2811	I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
6084	serge	2812	POSTING_READ(reg);
2327	Serge	2813	}
		2814
5060	serge	2815	static void ironlake_update_primary_plane(struct drm_crtc *crtc,
6084	serge	2816	struct drm_framebuffer *fb,
		2817	int x, int y)
2327	Serge	2818	{
6084	serge	2819	struct drm_device *dev = crtc->dev;
		2820	struct drm_i915_private *dev_priv = dev->dev_private;
		2821	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2822	struct drm_plane *primary = crtc->primary;
		2823	bool visible = to_intel_plane_state(primary->state)->visible;
5354	serge	2824	struct drm_i915_gem_object *obj;
6084	serge	2825	int plane = intel_crtc->plane;
3031	serge	2826	unsigned long linear_offset;
6084	serge	2827	u32 dspcntr;
5354	serge	2828	u32 reg = DSPCNTR(plane);
		2829	int pixel_size;
2327	Serge	2830
6084	serge	2831	if (!visible \|\| !fb) {
5354	serge	2832	I915_WRITE(reg, 0);
		2833	I915_WRITE(DSPSURF(plane), 0);
		2834	POSTING_READ(reg);
		2835	return;
		2836	}
		2837
		2838	obj = intel_fb_obj(fb);
		2839	if (WARN_ON(obj == NULL))
		2840	return;
		2841
		2842	pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
		2843
		2844	dspcntr = DISPPLANE_GAMMA_ENABLE;
		2845
		2846	dspcntr \|= DISPLAY_PLANE_ENABLE;
		2847
		2848	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
		2849	dspcntr \|= DISPPLANE_PIPE_CSC_ENABLE;
		2850
3243	Serge	2851	switch (fb->pixel_format) {
		2852	case DRM_FORMAT_C8:
6084	serge	2853	dspcntr \|= DISPPLANE_8BPP;
		2854	break;
3243	Serge	2855	case DRM_FORMAT_RGB565:
		2856	dspcntr \|= DISPPLANE_BGRX565;
6084	serge	2857	break;
3243	Serge	2858	case DRM_FORMAT_XRGB8888:
		2859	dspcntr \|= DISPPLANE_BGRX888;
		2860	break;
		2861	case DRM_FORMAT_XBGR8888:
		2862	dspcntr \|= DISPPLANE_RGBX888;
		2863	break;
		2864	case DRM_FORMAT_XRGB2101010:
		2865	dspcntr \|= DISPPLANE_BGRX101010;
		2866	break;
		2867	case DRM_FORMAT_XBGR2101010:
		2868	dspcntr \|= DISPPLANE_RGBX101010;
6084	serge	2869	break;
		2870	default:
3746	Serge	2871	BUG();
6084	serge	2872	}
2327	Serge	2873
3480	Serge	2874	if (obj->tiling_mode != I915_TILING_NONE)
		2875	dspcntr \|= DISPPLANE_TILED;
2327	Serge	2876
5354	serge	2877	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
6084	serge	2878	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
2327	Serge	2879
5354	serge	2880	linear_offset = y * fb->pitches[0] + x * pixel_size;
3031	serge	2881	intel_crtc->dspaddr_offset =
6084	serge	2882	intel_gen4_compute_page_offset(dev_priv,
		2883	&x, &y, obj->tiling_mode,
5354	serge	2884	pixel_size,
6084	serge	2885	fb->pitches[0]);
3031	serge	2886	linear_offset -= intel_crtc->dspaddr_offset;
6084	serge	2887	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
5354	serge	2888	dspcntr \|= DISPPLANE_ROTATE_180;
2327	Serge	2889
5354	serge	2890	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6084	serge	2891	x += (intel_crtc->config->pipe_src_w - 1);
		2892	y += (intel_crtc->config->pipe_src_h - 1);
5354	serge	2893
		2894	/* Finding the last pixel of the last line of the display
		2895	data and adding to linear_offset*/
		2896	linear_offset +=
6084	serge	2897	(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
		2898	(intel_crtc->config->pipe_src_w - 1) * pixel_size;
5354	serge	2899	}
		2900	}
		2901
6084	serge	2902	intel_crtc->adjusted_x = x;
		2903	intel_crtc->adjusted_y = y;
		2904
5354	serge	2905	I915_WRITE(reg, dspcntr);
		2906
2342	Serge	2907	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
4560	Serge	2908	I915_WRITE(DSPSURF(plane),
6084	serge	2909	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
4560	Serge	2910	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
3243	Serge	2911	I915_WRITE(DSPOFFSET(plane), (y << 16) \| x);
		2912	} else {
6084	serge	2913	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
		2914	I915_WRITE(DSPLINOFF(plane), linear_offset);
3243	Serge	2915	}
2330	Serge	2916	POSTING_READ(reg);
2327	Serge	2917	}
		2918
6084	serge	2919	u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
		2920	uint32_t pixel_format)
		2921	{
		2922	u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
		2923
		2924	/*
		2925	* The stride is either expressed as a multiple of 64 bytes
		2926	* chunks for linear buffers or in number of tiles for tiled
		2927	* buffers.
		2928	*/
		2929	switch (fb_modifier) {
		2930	case DRM_FORMAT_MOD_NONE:
		2931	return 64;
		2932	case I915_FORMAT_MOD_X_TILED:
		2933	if (INTEL_INFO(dev)->gen == 2)
		2934	return 128;
		2935	return 512;
		2936	case I915_FORMAT_MOD_Y_TILED:
		2937	/* No need to check for old gens and Y tiling since this is
		2938	* about the display engine and those will be blocked before
		2939	* we get here.
		2940	*/
		2941	return 128;
		2942	case I915_FORMAT_MOD_Yf_TILED:
		2943	if (bits_per_pixel == 8)
		2944	return 64;
		2945	else
		2946	return 128;
		2947	default:
		2948	MISSING_CASE(fb_modifier);
		2949	return 64;
		2950	}
		2951	}
		2952
		2953	unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
		2954	struct drm_i915_gem_object *obj,
		2955	unsigned int plane)
		2956	{
		2957	const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
		2958	struct i915_vma *vma;
		2959	unsigned char *offset;
		2960
		2961	if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
		2962	view = &i915_ggtt_view_rotated;
		2963
		2964	vma = i915_gem_obj_to_ggtt_view(obj, view);
		2965	if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
		2966	view->type))
		2967	return -1;
		2968
		2969	offset = (unsigned char *)vma->node.start;
		2970
		2971	if (plane == 1) {
		2972	offset += vma->ggtt_view.rotation_info.uv_start_page *
		2973	PAGE_SIZE;
		2974	}
		2975
		2976	return (unsigned long)offset;
		2977	}
		2978
		2979	static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
		2980	{
		2981	struct drm_device *dev = intel_crtc->base.dev;
		2982	struct drm_i915_private *dev_priv = dev->dev_private;
		2983
		2984	I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
		2985	I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
		2986	I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
		2987	}
		2988
		2989	/*
		2990	* This function detaches (aka. unbinds) unused scalers in hardware
		2991	*/
		2992	static void skl_detach_scalers(struct intel_crtc *intel_crtc)
		2993	{
		2994	struct intel_crtc_scaler_state *scaler_state;
		2995	int i;
		2996
		2997	scaler_state = &intel_crtc->config->scaler_state;
		2998
		2999	/* loop through and disable scalers that aren't in use */
		3000	for (i = 0; i < intel_crtc->num_scalers; i++) {
		3001	if (!scaler_state->scalers[i].in_use)
		3002	skl_detach_scaler(intel_crtc, i);
		3003	}
		3004	}
		3005
		3006	u32 skl_plane_ctl_format(uint32_t pixel_format)
		3007	{
		3008	switch (pixel_format) {
		3009	case DRM_FORMAT_C8:
		3010	return PLANE_CTL_FORMAT_INDEXED;
		3011	case DRM_FORMAT_RGB565:
		3012	return PLANE_CTL_FORMAT_RGB_565;
		3013	case DRM_FORMAT_XBGR8888:
		3014	return PLANE_CTL_FORMAT_XRGB_8888 \| PLANE_CTL_ORDER_RGBX;
		3015	case DRM_FORMAT_XRGB8888:
		3016	return PLANE_CTL_FORMAT_XRGB_8888;
		3017	/*
		3018	* XXX: For ARBG/ABGR formats we default to expecting scanout buffers
		3019	* to be already pre-multiplied. We need to add a knob (or a different
		3020	* DRM_FORMAT) for user-space to configure that.
		3021	*/
		3022	case DRM_FORMAT_ABGR8888:
		3023	return PLANE_CTL_FORMAT_XRGB_8888 \| PLANE_CTL_ORDER_RGBX \|
		3024	PLANE_CTL_ALPHA_SW_PREMULTIPLY;
		3025	case DRM_FORMAT_ARGB8888:
		3026	return PLANE_CTL_FORMAT_XRGB_8888 \|
		3027	PLANE_CTL_ALPHA_SW_PREMULTIPLY;
		3028	case DRM_FORMAT_XRGB2101010:
		3029	return PLANE_CTL_FORMAT_XRGB_2101010;
		3030	case DRM_FORMAT_XBGR2101010:
		3031	return PLANE_CTL_ORDER_RGBX \| PLANE_CTL_FORMAT_XRGB_2101010;
		3032	case DRM_FORMAT_YUYV:
		3033	return PLANE_CTL_FORMAT_YUV422 \| PLANE_CTL_YUV422_YUYV;
		3034	case DRM_FORMAT_YVYU:
		3035	return PLANE_CTL_FORMAT_YUV422 \| PLANE_CTL_YUV422_YVYU;
		3036	case DRM_FORMAT_UYVY:
		3037	return PLANE_CTL_FORMAT_YUV422 \| PLANE_CTL_YUV422_UYVY;
		3038	case DRM_FORMAT_VYUY:
		3039	return PLANE_CTL_FORMAT_YUV422 \| PLANE_CTL_YUV422_VYUY;
		3040	default:
		3041	MISSING_CASE(pixel_format);
		3042	}
		3043
		3044	return 0;
		3045	}
		3046
		3047	u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
		3048	{
		3049	switch (fb_modifier) {
		3050	case DRM_FORMAT_MOD_NONE:
		3051	break;
		3052	case I915_FORMAT_MOD_X_TILED:
		3053	return PLANE_CTL_TILED_X;
		3054	case I915_FORMAT_MOD_Y_TILED:
		3055	return PLANE_CTL_TILED_Y;
		3056	case I915_FORMAT_MOD_Yf_TILED:
		3057	return PLANE_CTL_TILED_YF;
		3058	default:
		3059	MISSING_CASE(fb_modifier);
		3060	}
		3061
		3062	return 0;
		3063	}
		3064
		3065	u32 skl_plane_ctl_rotation(unsigned int rotation)
		3066	{
		3067	switch (rotation) {
		3068	case BIT(DRM_ROTATE_0):
		3069	break;
		3070	/*
		3071	* DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
		3072	* while i915 HW rotation is clockwise, thats why this swapping.
		3073	*/
		3074	case BIT(DRM_ROTATE_90):
		3075	return PLANE_CTL_ROTATE_270;
		3076	case BIT(DRM_ROTATE_180):
		3077	return PLANE_CTL_ROTATE_180;
		3078	case BIT(DRM_ROTATE_270):
		3079	return PLANE_CTL_ROTATE_90;
		3080	default:
		3081	MISSING_CASE(rotation);
		3082	}
		3083
		3084	return 0;
		3085	}
		3086
5354	serge	3087	static void skylake_update_primary_plane(struct drm_crtc *crtc,
		3088	struct drm_framebuffer *fb,
		3089	int x, int y)
		3090	{
		3091	struct drm_device *dev = crtc->dev;
		3092	struct drm_i915_private *dev_priv = dev->dev_private;
		3093	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084	serge	3094	struct drm_plane *plane = crtc->primary;
		3095	bool visible = to_intel_plane_state(plane->state)->visible;
5354	serge	3096	struct drm_i915_gem_object *obj;
		3097	int pipe = intel_crtc->pipe;
6084	serge	3098	u32 plane_ctl, stride_div, stride;
		3099	u32 tile_height, plane_offset, plane_size;
		3100	unsigned int rotation;
		3101	int x_offset, y_offset;
		3102	unsigned long surf_addr;
		3103	struct intel_crtc_state *crtc_state = intel_crtc->config;
		3104	struct intel_plane_state *plane_state;
		3105	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
		3106	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
		3107	int scaler_id = -1;
5354	serge	3108
6084	serge	3109	plane_state = to_intel_plane_state(plane->state);
		3110
		3111	if (!visible \|\| !fb) {
5354	serge	3112	I915_WRITE(PLANE_CTL(pipe, 0), 0);
		3113	I915_WRITE(PLANE_SURF(pipe, 0), 0);
		3114	POSTING_READ(PLANE_CTL(pipe, 0));
		3115	return;
		3116	}
		3117
		3118	plane_ctl = PLANE_CTL_ENABLE \|
		3119	PLANE_CTL_PIPE_GAMMA_ENABLE \|
		3120	PLANE_CTL_PIPE_CSC_ENABLE;
		3121
6084	serge	3122	plane_ctl \|= skl_plane_ctl_format(fb->pixel_format);
		3123	plane_ctl \|= skl_plane_ctl_tiling(fb->modifier[0]);
		3124	plane_ctl \|= PLANE_CTL_PLANE_GAMMA_DISABLE;
5354	serge	3125
6084	serge	3126	rotation = plane->state->rotation;
		3127	plane_ctl \|= skl_plane_ctl_rotation(rotation);
5354	serge	3128
6084	serge	3129	obj = intel_fb_obj(fb);
		3130	stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
		3131	fb->pixel_format);
		3132	surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
		3133
		3134	WARN_ON(drm_rect_width(&plane_state->src) == 0);
		3135
		3136	scaler_id = plane_state->scaler_id;
		3137	src_x = plane_state->src.x1 >> 16;
		3138	src_y = plane_state->src.y1 >> 16;
		3139	src_w = drm_rect_width(&plane_state->src) >> 16;
		3140	src_h = drm_rect_height(&plane_state->src) >> 16;
		3141	dst_x = plane_state->dst.x1;
		3142	dst_y = plane_state->dst.y1;
		3143	dst_w = drm_rect_width(&plane_state->dst);
		3144	dst_h = drm_rect_height(&plane_state->dst);
		3145
		3146	WARN_ON(x != src_x \|\| y != src_y);
		3147
		3148	if (intel_rotation_90_or_270(rotation)) {
		3149	/* stride = Surface height in tiles */
		3150	tile_height = intel_tile_height(dev, fb->pixel_format,
		3151	fb->modifier[0], 0);
		3152	stride = DIV_ROUND_UP(fb->height, tile_height);
		3153	x_offset = stride * tile_height - y - src_h;
		3154	y_offset = x;
		3155	plane_size = (src_w - 1) << 16 \| (src_h - 1);
		3156	} else {
		3157	stride = fb->pitches[0] / stride_div;
		3158	x_offset = x;
		3159	y_offset = y;
		3160	plane_size = (src_h - 1) << 16 \| (src_w - 1);
5354	serge	3161	}
6084	serge	3162	plane_offset = y_offset << 16 \| x_offset;
5354	serge	3163
6084	serge	3164	intel_crtc->adjusted_x = x_offset;
		3165	intel_crtc->adjusted_y = y_offset;
5354	serge	3166
		3167	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
6084	serge	3168	I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
		3169	I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
		3170	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
5354	serge	3171
6084	serge	3172	if (scaler_id >= 0) {
		3173	uint32_t ps_ctrl = 0;
5354	serge	3174
6084	serge	3175	WARN_ON(!dst_w \|\| !dst_h);
		3176	ps_ctrl = PS_SCALER_EN \| PS_PLANE_SEL(0) \|
		3177	crtc_state->scaler_state.scalers[scaler_id].mode;
		3178	I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
		3179	I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
		3180	I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) \| dst_y);
		3181	I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) \| dst_h);
		3182	I915_WRITE(PLANE_POS(pipe, 0), 0);
		3183	} else {
		3184	I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) \| dst_x);
		3185	}
5354	serge	3186
6084	serge	3187	I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
		3188
5354	serge	3189	POSTING_READ(PLANE_SURF(pipe, 0));
		3190	}
		3191
2327	Serge	3192	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		3193	static int
		3194	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		3195	int x, int y, enum mode_set_atomic state)
		3196	{
		3197	struct drm_device *dev = crtc->dev;
		3198	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	3199
6084	serge	3200	if (dev_priv->fbc.disable_fbc)
		3201	dev_priv->fbc.disable_fbc(dev_priv);
3031	serge	3202
5060	serge	3203	dev_priv->display.update_primary_plane(crtc, fb, x, y);
		3204
		3205	return 0;
3031	serge	3206	}
		3207
5354	serge	3208	static void intel_complete_page_flips(struct drm_device *dev)
4104	Serge	3209	{
		3210	struct drm_crtc *crtc;
		3211
5060	serge	3212	for_each_crtc(dev, crtc) {
4104	Serge	3213	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3214	enum plane plane = intel_crtc->plane;
		3215
		3216	intel_prepare_page_flip(dev, plane);
		3217	intel_finish_page_flip_plane(dev, plane);
		3218	}
5354	serge	3219	}
4104	Serge	3220
5354	serge	3221	static void intel_update_primary_planes(struct drm_device *dev)
		3222	{
		3223	struct drm_crtc *crtc;
		3224
5060	serge	3225	for_each_crtc(dev, crtc) {
6084	serge	3226	struct intel_plane *plane = to_intel_plane(crtc->primary);
		3227	struct intel_plane_state *plane_state;
4104	Serge	3228
6084	serge	3229	drm_modeset_lock_crtc(crtc, &plane->base);
		3230
		3231	plane_state = to_intel_plane_state(plane->base.state);
		3232
		3233	if (plane_state->base.fb)
		3234	plane->commit_plane(&plane->base, plane_state);
		3235
		3236	drm_modeset_unlock_crtc(crtc);
4104	Serge	3237	}
		3238	}
		3239
5354	serge	3240	void intel_prepare_reset(struct drm_device *dev)
		3241	{
		3242	/* no reset support for gen2 */
		3243	if (IS_GEN2(dev))
		3244	return;
		3245
		3246	/* reset doesn't touch the display */
		3247	if (INTEL_INFO(dev)->gen >= 5 \|\| IS_G4X(dev))
		3248	return;
		3249
		3250	drm_modeset_lock_all(dev);
		3251	/*
		3252	* Disabling the crtcs gracefully seems nicer. Also the
		3253	* g33 docs say we should at least disable all the planes.
		3254	*/
6084	serge	3255	intel_display_suspend(dev);
5354	serge	3256	}
		3257
		3258	void intel_finish_reset(struct drm_device *dev)
		3259	{
		3260	struct drm_i915_private *dev_priv = to_i915(dev);
		3261
		3262	/*
		3263	* Flips in the rings will be nuked by the reset,
		3264	* so complete all pending flips so that user space
		3265	* will get its events and not get stuck.
		3266	*/
		3267	intel_complete_page_flips(dev);
		3268
		3269	/* no reset support for gen2 */
		3270	if (IS_GEN2(dev))
		3271	return;
		3272
		3273	/* reset doesn't touch the display */
		3274	if (INTEL_INFO(dev)->gen >= 5 \|\| IS_G4X(dev)) {
		3275	/*
		3276	* Flips in the rings have been nuked by the reset,
		3277	* so update the base address of all primary
		3278	* planes to the the last fb to make sure we're
		3279	* showing the correct fb after a reset.
6084	serge	3280	*
		3281	* FIXME: Atomic will make this obsolete since we won't schedule
		3282	* CS-based flips (which might get lost in gpu resets) any more.
5354	serge	3283	*/
		3284	intel_update_primary_planes(dev);
		3285	return;
		3286	}
		3287
		3288	/*
		3289	* The display has been reset as well,
		3290	* so need a full re-initialization.
		3291	*/
		3292	intel_runtime_pm_disable_interrupts(dev_priv);
		3293	intel_runtime_pm_enable_interrupts(dev_priv);
		3294
		3295	intel_modeset_init_hw(dev);
		3296
		3297	spin_lock_irq(&dev_priv->irq_lock);
		3298	if (dev_priv->display.hpd_irq_setup)
		3299	dev_priv->display.hpd_irq_setup(dev);
		3300	spin_unlock_irq(&dev_priv->irq_lock);
		3301
6084	serge	3302	intel_display_resume(dev);
5354	serge	3303
6296	serge	3304	intel_hpd_init(dev_priv);
5354	serge	3305
		3306	drm_modeset_unlock_all(dev);
		3307	}
		3308
6084	serge	3309	static void
3031	serge	3310	intel_finish_fb(struct drm_framebuffer *old_fb)
		3311	{
5060	serge	3312	struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
6084	serge	3313	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3031	serge	3314	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	3315	int ret;
		3316
3031	serge	3317	/* Big Hammer, we also need to ensure that any pending
		3318	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		3319	* current scanout is retired before unpinning the old
6084	serge	3320	* framebuffer. Note that we rely on userspace rendering
		3321	* into the buffer attached to the pipe they are waiting
		3322	* on. If not, userspace generates a GPU hang with IPEHR
		3323	* point to the MI_WAIT_FOR_EVENT.
3031	serge	3324	*
		3325	* This should only fail upon a hung GPU, in which case we
		3326	* can safely continue.
		3327	*/
		3328	dev_priv->mm.interruptible = false;
6084	serge	3329	ret = i915_gem_object_wait_rendering(obj, true);
3031	serge	3330	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	3331
6084	serge	3332	WARN_ON(ret);
2327	Serge	3333	}
4104	Serge	3334
5060	serge	3335	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
4104	Serge	3336	{
		3337	struct drm_device *dev = crtc->dev;
5060	serge	3338	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	3339	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	3340	bool pending;
4104	Serge	3341
5060	serge	3342	if (i915_reset_in_progress(&dev_priv->gpu_error) \|\|
		3343	intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
		3344	return false;
4104	Serge	3345
5354	serge	3346	spin_lock_irq(&dev->event_lock);
5060	serge	3347	pending = to_intel_crtc(crtc)->unpin_work != NULL;
5354	serge	3348	spin_unlock_irq(&dev->event_lock);
4104	Serge	3349
5060	serge	3350	return pending;
4104	Serge	3351	}
2327	Serge	3352
6084	serge	3353	static void intel_update_pipe_config(struct intel_crtc *crtc,
		3354	struct intel_crtc_state *old_crtc_state)
5354	serge	3355	{
		3356	struct drm_device *dev = crtc->base.dev;
		3357	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	3358	struct intel_crtc_state *pipe_config =
		3359	to_intel_crtc_state(crtc->base.state);
5354	serge	3360
6084	serge	3361	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
		3362	crtc->base.mode = crtc->base.state->mode;
5354	serge	3363
6084	serge	3364	DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
		3365	old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
		3366	pipe_config->pipe_src_w, pipe_config->pipe_src_h);
		3367
		3368	if (HAS_DDI(dev))
		3369	intel_set_pipe_csc(&crtc->base);
		3370
5354	serge	3371	/*
		3372	* Update pipe size and adjust fitter if needed: the reason for this is
		3373	* that in compute_mode_changes we check the native mode (not the pfit
		3374	* mode) to see if we can flip rather than do a full mode set. In the
		3375	* fastboot case, we'll flip, but if we don't update the pipesrc and
		3376	* pfit state, we'll end up with a big fb scanned out into the wrong
		3377	* sized surface.
		3378	*/
		3379
		3380	I915_WRITE(PIPESRC(crtc->pipe),
6084	serge	3381	((pipe_config->pipe_src_w - 1) << 16) \|
		3382	(pipe_config->pipe_src_h - 1));
5354	serge	3383
6084	serge	3384	/* on skylake this is done by detaching scalers */
		3385	if (INTEL_INFO(dev)->gen >= 9) {
		3386	skl_detach_scalers(crtc);
2327	Serge	3387
6084	serge	3388	if (pipe_config->pch_pfit.enabled)
		3389	skylake_pfit_enable(crtc);
		3390	} else if (HAS_PCH_SPLIT(dev)) {
		3391	if (pipe_config->pch_pfit.enabled)
		3392	ironlake_pfit_enable(crtc);
		3393	else if (old_crtc_state->pch_pfit.enabled)
		3394	ironlake_pfit_disable(crtc, true);
2327	Serge	3395	}
		3396	}
		3397
		3398	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		3399	{
		3400	struct drm_device *dev = crtc->dev;
		3401	struct drm_i915_private *dev_priv = dev->dev_private;
		3402	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3403	int pipe = intel_crtc->pipe;
		3404	u32 reg, temp;
		3405
		3406	/* enable normal train */
		3407	reg = FDI_TX_CTL(pipe);
		3408	temp = I915_READ(reg);
		3409	if (IS_IVYBRIDGE(dev)) {
		3410	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		3411	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		3412	} else {
		3413	temp &= ~FDI_LINK_TRAIN_NONE;
		3414	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		3415	}
		3416	I915_WRITE(reg, temp);
		3417
		3418	reg = FDI_RX_CTL(pipe);
		3419	temp = I915_READ(reg);
		3420	if (HAS_PCH_CPT(dev)) {
		3421	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3422	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		3423	} else {
		3424	temp &= ~FDI_LINK_TRAIN_NONE;
		3425	temp \|= FDI_LINK_TRAIN_NONE;
		3426	}
		3427	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		3428
		3429	/* wait one idle pattern time */
		3430	POSTING_READ(reg);
		3431	udelay(1000);
		3432
		3433	/* IVB wants error correction enabled */
		3434	if (IS_IVYBRIDGE(dev))
		3435	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		3436	FDI_FE_ERRC_ENABLE);
		3437	}
		3438
		3439	/* The FDI link training functions for ILK/Ibexpeak. */
		3440	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		3441	{
6084	serge	3442	struct drm_device *dev = crtc->dev;
		3443	struct drm_i915_private *dev_priv = dev->dev_private;
		3444	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3445	int pipe = intel_crtc->pipe;
		3446	u32 reg, temp, tries;
2327	Serge	3447
5060	serge	3448	/* FDI needs bits from pipe first */
6084	serge	3449	assert_pipe_enabled(dev_priv, pipe);
2327	Serge	3450
6084	serge	3451	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		3452	for train result */
		3453	reg = FDI_RX_IMR(pipe);
		3454	temp = I915_READ(reg);
		3455	temp &= ~FDI_RX_SYMBOL_LOCK;
		3456	temp &= ~FDI_RX_BIT_LOCK;
		3457	I915_WRITE(reg, temp);
		3458	I915_READ(reg);
		3459	udelay(150);
2327	Serge	3460
6084	serge	3461	/* enable CPU FDI TX and PCH FDI RX */
		3462	reg = FDI_TX_CTL(pipe);
		3463	temp = I915_READ(reg);
4104	Serge	3464	temp &= ~FDI_DP_PORT_WIDTH_MASK;
6084	serge	3465	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
		3466	temp &= ~FDI_LINK_TRAIN_NONE;
		3467	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		3468	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
2327	Serge	3469
6084	serge	3470	reg = FDI_RX_CTL(pipe);
		3471	temp = I915_READ(reg);
		3472	temp &= ~FDI_LINK_TRAIN_NONE;
		3473	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		3474	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
2327	Serge	3475
6084	serge	3476	POSTING_READ(reg);
		3477	udelay(150);
2327	Serge	3478
6084	serge	3479	/* Ironlake workaround, enable clock pointer after FDI enable*/
		3480	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		3481	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		3482	FDI_RX_PHASE_SYNC_POINTER_EN);
2327	Serge	3483
6084	serge	3484	reg = FDI_RX_IIR(pipe);
		3485	for (tries = 0; tries < 5; tries++) {
		3486	temp = I915_READ(reg);
		3487	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2327	Serge	3488
6084	serge	3489	if ((temp & FDI_RX_BIT_LOCK)) {
		3490	DRM_DEBUG_KMS("FDI train 1 done.\n");
		3491	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		3492	break;
		3493	}
		3494	}
		3495	if (tries == 5)
		3496	DRM_ERROR("FDI train 1 fail!\n");
2327	Serge	3497
6084	serge	3498	/* Train 2 */
		3499	reg = FDI_TX_CTL(pipe);
		3500	temp = I915_READ(reg);
		3501	temp &= ~FDI_LINK_TRAIN_NONE;
		3502	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		3503	I915_WRITE(reg, temp);
2327	Serge	3504
6084	serge	3505	reg = FDI_RX_CTL(pipe);
		3506	temp = I915_READ(reg);
		3507	temp &= ~FDI_LINK_TRAIN_NONE;
		3508	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		3509	I915_WRITE(reg, temp);
2327	Serge	3510
6084	serge	3511	POSTING_READ(reg);
		3512	udelay(150);
2327	Serge	3513
6084	serge	3514	reg = FDI_RX_IIR(pipe);
		3515	for (tries = 0; tries < 5; tries++) {
		3516	temp = I915_READ(reg);
		3517	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2327	Serge	3518
6084	serge	3519	if (temp & FDI_RX_SYMBOL_LOCK) {
		3520	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		3521	DRM_DEBUG_KMS("FDI train 2 done.\n");
		3522	break;
		3523	}
		3524	}
		3525	if (tries == 5)
		3526	DRM_ERROR("FDI train 2 fail!\n");
2327	Serge	3527
6084	serge	3528	DRM_DEBUG_KMS("FDI train done\n");
2327	Serge	3529
		3530	}
		3531
2342	Serge	3532	static const int snb_b_fdi_train_param[] = {
6084	serge	3533	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		3534	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		3535	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		3536	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2327	Serge	3537	};
		3538
		3539	/* The FDI link training functions for SNB/Cougarpoint. */
		3540	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		3541	{
6084	serge	3542	struct drm_device *dev = crtc->dev;
		3543	struct drm_i915_private *dev_priv = dev->dev_private;
		3544	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3545	int pipe = intel_crtc->pipe;
3031	serge	3546	u32 reg, temp, i, retry;
2327	Serge	3547
6084	serge	3548	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		3549	for train result */
		3550	reg = FDI_RX_IMR(pipe);
		3551	temp = I915_READ(reg);
		3552	temp &= ~FDI_RX_SYMBOL_LOCK;
		3553	temp &= ~FDI_RX_BIT_LOCK;
		3554	I915_WRITE(reg, temp);
2327	Serge	3555
6084	serge	3556	POSTING_READ(reg);
		3557	udelay(150);
2327	Serge	3558
6084	serge	3559	/* enable CPU FDI TX and PCH FDI RX */
		3560	reg = FDI_TX_CTL(pipe);
		3561	temp = I915_READ(reg);
4104	Serge	3562	temp &= ~FDI_DP_PORT_WIDTH_MASK;
6084	serge	3563	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
		3564	temp &= ~FDI_LINK_TRAIN_NONE;
		3565	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		3566	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		3567	/* SNB-B */
		3568	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		3569	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
2327	Serge	3570
3243	Serge	3571	I915_WRITE(FDI_RX_MISC(pipe),
		3572	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		3573
6084	serge	3574	reg = FDI_RX_CTL(pipe);
		3575	temp = I915_READ(reg);
		3576	if (HAS_PCH_CPT(dev)) {
		3577	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3578	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		3579	} else {
		3580	temp &= ~FDI_LINK_TRAIN_NONE;
		3581	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		3582	}
		3583	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
2327	Serge	3584
6084	serge	3585	POSTING_READ(reg);
		3586	udelay(150);
2327	Serge	3587
2342	Serge	3588	for (i = 0; i < 4; i++) {
6084	serge	3589	reg = FDI_TX_CTL(pipe);
		3590	temp = I915_READ(reg);
		3591	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		3592	temp \|= snb_b_fdi_train_param[i];
		3593	I915_WRITE(reg, temp);
2327	Serge	3594
6084	serge	3595	POSTING_READ(reg);
		3596	udelay(500);
2327	Serge	3597
3031	serge	3598	for (retry = 0; retry < 5; retry++) {
6084	serge	3599	reg = FDI_RX_IIR(pipe);
		3600	temp = I915_READ(reg);
		3601	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		3602	if (temp & FDI_RX_BIT_LOCK) {
		3603	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		3604	DRM_DEBUG_KMS("FDI train 1 done.\n");
		3605	break;
		3606	}
3031	serge	3607	udelay(50);
		3608	}
		3609	if (retry < 5)
		3610	break;
6084	serge	3611	}
		3612	if (i == 4)
		3613	DRM_ERROR("FDI train 1 fail!\n");
2327	Serge	3614
6084	serge	3615	/* Train 2 */
		3616	reg = FDI_TX_CTL(pipe);
		3617	temp = I915_READ(reg);
		3618	temp &= ~FDI_LINK_TRAIN_NONE;
		3619	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		3620	if (IS_GEN6(dev)) {
		3621	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		3622	/* SNB-B */
		3623	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		3624	}
		3625	I915_WRITE(reg, temp);
2327	Serge	3626
6084	serge	3627	reg = FDI_RX_CTL(pipe);
		3628	temp = I915_READ(reg);
		3629	if (HAS_PCH_CPT(dev)) {
		3630	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3631	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		3632	} else {
		3633	temp &= ~FDI_LINK_TRAIN_NONE;
		3634	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		3635	}
		3636	I915_WRITE(reg, temp);
2327	Serge	3637
6084	serge	3638	POSTING_READ(reg);
		3639	udelay(150);
2327	Serge	3640
2342	Serge	3641	for (i = 0; i < 4; i++) {
6084	serge	3642	reg = FDI_TX_CTL(pipe);
		3643	temp = I915_READ(reg);
		3644	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		3645	temp \|= snb_b_fdi_train_param[i];
		3646	I915_WRITE(reg, temp);
2327	Serge	3647
6084	serge	3648	POSTING_READ(reg);
		3649	udelay(500);
2327	Serge	3650
3031	serge	3651	for (retry = 0; retry < 5; retry++) {
6084	serge	3652	reg = FDI_RX_IIR(pipe);
		3653	temp = I915_READ(reg);
		3654	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		3655	if (temp & FDI_RX_SYMBOL_LOCK) {
		3656	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		3657	DRM_DEBUG_KMS("FDI train 2 done.\n");
		3658	break;
		3659	}
3031	serge	3660	udelay(50);
		3661	}
		3662	if (retry < 5)
		3663	break;
6084	serge	3664	}
		3665	if (i == 4)
		3666	DRM_ERROR("FDI train 2 fail!\n");
2327	Serge	3667
6084	serge	3668	DRM_DEBUG_KMS("FDI train done.\n");
2327	Serge	3669	}
		3670
		3671	/* Manual link training for Ivy Bridge A0 parts */
		3672	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		3673	{
6084	serge	3674	struct drm_device *dev = crtc->dev;
		3675	struct drm_i915_private *dev_priv = dev->dev_private;
		3676	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3677	int pipe = intel_crtc->pipe;
4104	Serge	3678	u32 reg, temp, i, j;
2327	Serge	3679
6084	serge	3680	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		3681	for train result */
		3682	reg = FDI_RX_IMR(pipe);
		3683	temp = I915_READ(reg);
		3684	temp &= ~FDI_RX_SYMBOL_LOCK;
		3685	temp &= ~FDI_RX_BIT_LOCK;
		3686	I915_WRITE(reg, temp);
2327	Serge	3687
6084	serge	3688	POSTING_READ(reg);
		3689	udelay(150);
2327	Serge	3690
3243	Serge	3691	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		3692	I915_READ(FDI_RX_IIR(pipe)));
		3693
4104	Serge	3694	/* Try each vswing and preemphasis setting twice before moving on */
		3695	for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
		3696	/* disable first in case we need to retry */
		3697	reg = FDI_TX_CTL(pipe);
		3698	temp = I915_READ(reg);
		3699	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		3700	temp &= ~FDI_TX_ENABLE;
		3701	I915_WRITE(reg, temp);
		3702
		3703	reg = FDI_RX_CTL(pipe);
		3704	temp = I915_READ(reg);
		3705	temp &= ~FDI_LINK_TRAIN_AUTO;
		3706	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3707	temp &= ~FDI_RX_ENABLE;
		3708	I915_WRITE(reg, temp);
		3709
6084	serge	3710	/* enable CPU FDI TX and PCH FDI RX */
		3711	reg = FDI_TX_CTL(pipe);
		3712	temp = I915_READ(reg);
		3713	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		3714	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
		3715	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		3716	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4104	Serge	3717	temp \|= snb_b_fdi_train_param[j/2];
6084	serge	3718	temp \|= FDI_COMPOSITE_SYNC;
		3719	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
2327	Serge	3720
6084	serge	3721	I915_WRITE(FDI_RX_MISC(pipe),
		3722	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
3243	Serge	3723
6084	serge	3724	reg = FDI_RX_CTL(pipe);
		3725	temp = I915_READ(reg);
		3726	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		3727	temp \|= FDI_COMPOSITE_SYNC;
		3728	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
2327	Serge	3729
6084	serge	3730	POSTING_READ(reg);
4104	Serge	3731	udelay(1); /* should be 0.5us */
2327	Serge	3732
6084	serge	3733	for (i = 0; i < 4; i++) {
		3734	reg = FDI_RX_IIR(pipe);
		3735	temp = I915_READ(reg);
		3736	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2327	Serge	3737
6084	serge	3738	if (temp & FDI_RX_BIT_LOCK \|\|
		3739	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		3740	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
4104	Serge	3741	DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
		3742	i);
6084	serge	3743	break;
		3744	}
4104	Serge	3745	udelay(1); /* should be 0.5us */
		3746	}
		3747	if (i == 4) {
		3748	DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
		3749	continue;
6084	serge	3750	}
2327	Serge	3751
6084	serge	3752	/* Train 2 */
		3753	reg = FDI_TX_CTL(pipe);
		3754	temp = I915_READ(reg);
		3755	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		3756	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		3757	I915_WRITE(reg, temp);
2327	Serge	3758
6084	serge	3759	reg = FDI_RX_CTL(pipe);
		3760	temp = I915_READ(reg);
		3761	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3762	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		3763	I915_WRITE(reg, temp);
2327	Serge	3764
6084	serge	3765	POSTING_READ(reg);
4104	Serge	3766	udelay(2); /* should be 1.5us */
2327	Serge	3767
6084	serge	3768	for (i = 0; i < 4; i++) {
		3769	reg = FDI_RX_IIR(pipe);
		3770	temp = I915_READ(reg);
		3771	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2327	Serge	3772
4104	Serge	3773	if (temp & FDI_RX_SYMBOL_LOCK \|\|
		3774	(I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
6084	serge	3775	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
4104	Serge	3776	DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
		3777	i);
		3778	goto train_done;
6084	serge	3779	}
4104	Serge	3780	udelay(2); /* should be 1.5us */
6084	serge	3781	}
		3782	if (i == 4)
4104	Serge	3783	DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
		3784	}
2327	Serge	3785
4104	Serge	3786	train_done:
6084	serge	3787	DRM_DEBUG_KMS("FDI train done.\n");
2327	Serge	3788	}
		3789
3031	serge	3790	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	3791	{
3031	serge	3792	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	3793	struct drm_i915_private *dev_priv = dev->dev_private;
		3794	int pipe = intel_crtc->pipe;
		3795	u32 reg, temp;
		3796
		3797
		3798	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		3799	reg = FDI_RX_CTL(pipe);
		3800	temp = I915_READ(reg);
4104	Serge	3801	temp &= ~(FDI_DP_PORT_WIDTH_MASK \| (0x7 << 16));
6084	serge	3802	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3480	Serge	3803	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	3804	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		3805
		3806	POSTING_READ(reg);
		3807	udelay(200);
		3808
		3809	/* Switch from Rawclk to PCDclk */
		3810	temp = I915_READ(reg);
		3811	I915_WRITE(reg, temp \| FDI_PCDCLK);
		3812
		3813	POSTING_READ(reg);
		3814	udelay(200);
		3815
		3816	/* Enable CPU FDI TX PLL, always on for Ironlake */
		3817	reg = FDI_TX_CTL(pipe);
		3818	temp = I915_READ(reg);
		3819	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		3820	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		3821
		3822	POSTING_READ(reg);
		3823	udelay(100);
		3824	}
		3825	}
		3826
3031	serge	3827	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		3828	{
		3829	struct drm_device *dev = intel_crtc->base.dev;
		3830	struct drm_i915_private *dev_priv = dev->dev_private;
		3831	int pipe = intel_crtc->pipe;
		3832	u32 reg, temp;
		3833
		3834	/* Switch from PCDclk to Rawclk */
		3835	reg = FDI_RX_CTL(pipe);
		3836	temp = I915_READ(reg);
		3837	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		3838
		3839	/* Disable CPU FDI TX PLL */
		3840	reg = FDI_TX_CTL(pipe);
		3841	temp = I915_READ(reg);
		3842	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		3843
		3844	POSTING_READ(reg);
		3845	udelay(100);
		3846
		3847	reg = FDI_RX_CTL(pipe);
		3848	temp = I915_READ(reg);
		3849	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		3850
		3851	/* Wait for the clocks to turn off. */
		3852	POSTING_READ(reg);
		3853	udelay(100);
		3854	}
		3855
2327	Serge	3856	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		3857	{
		3858	struct drm_device *dev = crtc->dev;
		3859	struct drm_i915_private *dev_priv = dev->dev_private;
		3860	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3861	int pipe = intel_crtc->pipe;
		3862	u32 reg, temp;
		3863
		3864	/* disable CPU FDI tx and PCH FDI rx */
		3865	reg = FDI_TX_CTL(pipe);
		3866	temp = I915_READ(reg);
		3867	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		3868	POSTING_READ(reg);
		3869
		3870	reg = FDI_RX_CTL(pipe);
		3871	temp = I915_READ(reg);
		3872	temp &= ~(0x7 << 16);
3480	Serge	3873	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	3874	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		3875
		3876	POSTING_READ(reg);
		3877	udelay(100);
		3878
		3879	/* Ironlake workaround, disable clock pointer after downing FDI */
5060	serge	3880	if (HAS_PCH_IBX(dev))
2327	Serge	3881	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		3882
		3883	/* still set train pattern 1 */
		3884	reg = FDI_TX_CTL(pipe);
		3885	temp = I915_READ(reg);
		3886	temp &= ~FDI_LINK_TRAIN_NONE;
		3887	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		3888	I915_WRITE(reg, temp);
		3889
		3890	reg = FDI_RX_CTL(pipe);
		3891	temp = I915_READ(reg);
		3892	if (HAS_PCH_CPT(dev)) {
		3893	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3894	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		3895	} else {
		3896	temp &= ~FDI_LINK_TRAIN_NONE;
		3897	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		3898	}
		3899	/* BPC in FDI rx is consistent with that in PIPECONF */
		3900	temp &= ~(0x07 << 16);
3480	Serge	3901	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	3902	I915_WRITE(reg, temp);
		3903
		3904	POSTING_READ(reg);
		3905	udelay(100);
		3906	}
		3907
5060	serge	3908	bool intel_has_pending_fb_unpin(struct drm_device *dev)
2327	Serge	3909	{
5060	serge	3910	struct intel_crtc *crtc;
2327	Serge	3911
5060	serge	3912	/* Note that we don't need to be called with mode_config.lock here
		3913	* as our list of CRTC objects is static for the lifetime of the
		3914	* device and so cannot disappear as we iterate. Similarly, we can
		3915	* happily treat the predicates as racy, atomic checks as userspace
		3916	* cannot claim and pin a new fb without at least acquring the
		3917	* struct_mutex and so serialising with us.
		3918	*/
		3919	for_each_intel_crtc(dev, crtc) {
		3920	if (atomic_read(&crtc->unpin_work_count) == 0)
		3921	continue;
2327	Serge	3922
5060	serge	3923	if (crtc->unpin_work)
		3924	intel_wait_for_vblank(dev, crtc->pipe);
3031	serge	3925
5060	serge	3926	return true;
		3927	}
		3928
		3929	return false;
2327	Serge	3930	}
		3931
6283	serge	3932	static void page_flip_completed(struct intel_crtc *intel_crtc)
		3933	{
		3934	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
		3935	struct intel_unpin_work *work = intel_crtc->unpin_work;
		3936
		3937	/* ensure that the unpin work is consistent wrt ->pending. */
		3938	smp_rmb();
		3939	intel_crtc->unpin_work = NULL;
		3940
		3941	if (work->event)
		3942	drm_send_vblank_event(intel_crtc->base.dev,
		3943	intel_crtc->pipe,
		3944	work->event);
		3945
		3946	drm_crtc_vblank_put(&intel_crtc->base);
		3947
6320	serge	3948	wake_up_all(&dev_priv->pending_flip_queue);
		3949	queue_work(dev_priv->wq, &work->work);
6283	serge	3950
6320	serge	3951	trace_i915_flip_complete(intel_crtc->plane,
		3952	work->pending_flip_obj);
6283	serge	3953	}
6320	serge	3954
5060	serge	3955	void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2327	Serge	3956	{
3031	serge	3957	struct drm_device *dev = crtc->dev;
		3958	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	3959
3480	Serge	3960	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5354	serge	3961	if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
		3962	!intel_crtc_has_pending_flip(crtc),
		3963	60*HZ) == 0)) {
		3964	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480	Serge	3965
5354	serge	3966	spin_lock_irq(&dev->event_lock);
		3967	if (intel_crtc->unpin_work) {
		3968	WARN_ONCE(1, "Removing stuck page flip\n");
		3969	page_flip_completed(intel_crtc);
		3970	}
		3971	spin_unlock_irq(&dev->event_lock);
		3972	}
3031	serge	3973
5354	serge	3974	if (crtc->primary->fb) {
6084	serge	3975	mutex_lock(&dev->struct_mutex);
		3976	intel_finish_fb(crtc->primary->fb);
		3977	mutex_unlock(&dev->struct_mutex);
5354	serge	3978	}
2327	Serge	3979	}
		3980
3031	serge	3981	/* Program iCLKIP clock to the desired frequency */
		3982	static void lpt_program_iclkip(struct drm_crtc *crtc)
		3983	{
		3984	struct drm_device *dev = crtc->dev;
		3985	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	3986	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3031	serge	3987	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		3988	u32 temp;
		3989
6084	serge	3990	mutex_lock(&dev_priv->sb_lock);
3480	Serge	3991
3031	serge	3992	/* It is necessary to ungate the pixclk gate prior to programming
		3993	* the divisors, and gate it back when it is done.
		3994	*/
		3995	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		3996
		3997	/* Disable SSCCTL */
		3998	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3243	Serge	3999	intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) \|
		4000	SBI_SSCCTL_DISABLE,
		4001	SBI_ICLK);
3031	serge	4002
		4003	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
4560	Serge	4004	if (clock == 20000) {
3031	serge	4005	auxdiv = 1;
		4006	divsel = 0x41;
		4007	phaseinc = 0x20;
		4008	} else {
		4009	/* The iCLK virtual clock root frequency is in MHz,
4560	Serge	4010	* but the adjusted_mode->crtc_clock in in KHz. To get the
		4011	* divisors, it is necessary to divide one by another, so we
3031	serge	4012	* convert the virtual clock precision to KHz here for higher
		4013	* precision.
		4014	*/
		4015	u32 iclk_virtual_root_freq = 172800 * 1000;
		4016	u32 iclk_pi_range = 64;
		4017	u32 desired_divisor, msb_divisor_value, pi_value;
		4018
4560	Serge	4019	desired_divisor = (iclk_virtual_root_freq / clock);
3031	serge	4020	msb_divisor_value = desired_divisor / iclk_pi_range;
		4021	pi_value = desired_divisor % iclk_pi_range;
		4022
		4023	auxdiv = 0;
		4024	divsel = msb_divisor_value - 2;
		4025	phaseinc = pi_value;
		4026	}
		4027
		4028	/* This should not happen with any sane values */
		4029	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		4030	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		4031	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		4032	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		4033
		4034	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4560	Serge	4035	clock,
3031	serge	4036	auxdiv,
		4037	divsel,
		4038	phasedir,
		4039	phaseinc);
		4040
		4041	/* Program SSCDIVINTPHASE6 */
3243	Serge	4042	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3031	serge	4043	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		4044	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		4045	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		4046	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		4047	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		4048	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
3243	Serge	4049	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031	serge	4050
		4051	/* Program SSCAUXDIV */
3243	Serge	4052	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3031	serge	4053	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		4054	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3243	Serge	4055	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3031	serge	4056
		4057	/* Enable modulator and associated divider */
3243	Serge	4058	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3031	serge	4059	temp &= ~SBI_SSCCTL_DISABLE;
3243	Serge	4060	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3031	serge	4061
		4062	/* Wait for initialization time */
		4063	udelay(24);
		4064
		4065	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3480	Serge	4066
6084	serge	4067	mutex_unlock(&dev_priv->sb_lock);
3031	serge	4068	}
		4069
4104	Serge	4070	static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
		4071	enum pipe pch_transcoder)
		4072	{
		4073	struct drm_device *dev = crtc->base.dev;
		4074	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	4075	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4104	Serge	4076
		4077	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
		4078	I915_READ(HTOTAL(cpu_transcoder)));
		4079	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
		4080	I915_READ(HBLANK(cpu_transcoder)));
		4081	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
		4082	I915_READ(HSYNC(cpu_transcoder)));
		4083
		4084	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
		4085	I915_READ(VTOTAL(cpu_transcoder)));
		4086	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
		4087	I915_READ(VBLANK(cpu_transcoder)));
		4088	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
		4089	I915_READ(VSYNC(cpu_transcoder)));
		4090	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
		4091	I915_READ(VSYNCSHIFT(cpu_transcoder)));
		4092	}
		4093
6084	serge	4094	static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4280	Serge	4095	{
		4096	struct drm_i915_private *dev_priv = dev->dev_private;
		4097	uint32_t temp;
		4098
		4099	temp = I915_READ(SOUTH_CHICKEN1);
6084	serge	4100	if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4280	Serge	4101	return;
		4102
		4103	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		4104	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		4105
6084	serge	4106	temp &= ~FDI_BC_BIFURCATION_SELECT;
		4107	if (enable)
		4108	temp \|= FDI_BC_BIFURCATION_SELECT;
		4109
		4110	DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4280	Serge	4111	I915_WRITE(SOUTH_CHICKEN1, temp);
		4112	POSTING_READ(SOUTH_CHICKEN1);
		4113	}
		4114
		4115	static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
		4116	{
		4117	struct drm_device *dev = intel_crtc->base.dev;
		4118
		4119	switch (intel_crtc->pipe) {
		4120	case PIPE_A:
		4121	break;
		4122	case PIPE_B:
6084	serge	4123	if (intel_crtc->config->fdi_lanes > 2)
		4124	cpt_set_fdi_bc_bifurcation(dev, false);
4280	Serge	4125	else
6084	serge	4126	cpt_set_fdi_bc_bifurcation(dev, true);
4280	Serge	4127
		4128	break;
		4129	case PIPE_C:
6084	serge	4130	cpt_set_fdi_bc_bifurcation(dev, true);
4280	Serge	4131
		4132	break;
		4133	default:
		4134	BUG();
		4135	}
		4136	}
		4137
2327	Serge	4138	/*
		4139	* Enable PCH resources required for PCH ports:
		4140	* - PCH PLLs
		4141	* - FDI training & RX/TX
		4142	* - update transcoder timings
		4143	* - DP transcoding bits
		4144	* - transcoder
		4145	*/
		4146	static void ironlake_pch_enable(struct drm_crtc *crtc)
		4147	{
		4148	struct drm_device *dev = crtc->dev;
		4149	struct drm_i915_private *dev_priv = dev->dev_private;
		4150	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4151	int pipe = intel_crtc->pipe;
3031	serge	4152	u32 reg, temp;
2327	Serge	4153
4104	Serge	4154	assert_pch_transcoder_disabled(dev_priv, pipe);
3031	serge	4155
4280	Serge	4156	if (IS_IVYBRIDGE(dev))
		4157	ivybridge_update_fdi_bc_bifurcation(intel_crtc);
		4158
3243	Serge	4159	/* Write the TU size bits before fdi link training, so that error
		4160	* detection works. */
		4161	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		4162	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		4163
2327	Serge	4164	/* For PCH output, training FDI link */
		4165	dev_priv->display.fdi_link_train(crtc);
		4166
4104	Serge	4167	/* We need to program the right clock selection before writing the pixel
		4168	* mutliplier into the DPLL. */
3243	Serge	4169	if (HAS_PCH_CPT(dev)) {
3031	serge	4170	u32 sel;
2342	Serge	4171
2327	Serge	4172	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	4173	temp \|= TRANS_DPLL_ENABLE(pipe);
		4174	sel = TRANS_DPLLB_SEL(pipe);
6084	serge	4175	if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3031	serge	4176	temp \|= sel;
		4177	else
		4178	temp &= ~sel;
2327	Serge	4179	I915_WRITE(PCH_DPLL_SEL, temp);
		4180	}
		4181
4104	Serge	4182	/* XXX: pch pll's can be enabled any time before we enable the PCH
		4183	* transcoder, and we actually should do this to not upset any PCH
		4184	* transcoder that already use the clock when we share it.
		4185	*
		4186	* Note that enable_shared_dpll tries to do the right thing, but
		4187	* get_shared_dpll unconditionally resets the pll - we need that to have
		4188	* the right LVDS enable sequence. */
5060	serge	4189	intel_enable_shared_dpll(intel_crtc);
4104	Serge	4190
2327	Serge	4191	/* set transcoder timing, panel must allow it */
		4192	assert_panel_unlocked(dev_priv, pipe);
4104	Serge	4193	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2327	Serge	4194
		4195	intel_fdi_normal_train(crtc);
		4196
		4197	/* For PCH DP, enable TRANS_DP_CTL */
6084	serge	4198	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3480	Serge	4199	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2327	Serge	4200	reg = TRANS_DP_CTL(pipe);
		4201	temp = I915_READ(reg);
		4202	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		4203	TRANS_DP_SYNC_MASK \|
		4204	TRANS_DP_BPC_MASK);
6084	serge	4205	temp \|= TRANS_DP_OUTPUT_ENABLE;
2327	Serge	4206	temp \|= bpc << 9; /* same format but at 11:9 */
		4207
		4208	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		4209	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		4210	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		4211	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		4212
		4213	switch (intel_trans_dp_port_sel(crtc)) {
		4214	case PCH_DP_B:
		4215	temp \|= TRANS_DP_PORT_SEL_B;
		4216	break;
		4217	case PCH_DP_C:
		4218	temp \|= TRANS_DP_PORT_SEL_C;
		4219	break;
		4220	case PCH_DP_D:
		4221	temp \|= TRANS_DP_PORT_SEL_D;
		4222	break;
		4223	default:
3243	Serge	4224	BUG();
2327	Serge	4225	}
		4226
		4227	I915_WRITE(reg, temp);
		4228	}
		4229
3243	Serge	4230	ironlake_enable_pch_transcoder(dev_priv, pipe);
2327	Serge	4231	}
		4232
3243	Serge	4233	static void lpt_pch_enable(struct drm_crtc *crtc)
		4234	{
		4235	struct drm_device *dev = crtc->dev;
		4236	struct drm_i915_private *dev_priv = dev->dev_private;
		4237	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084	serge	4238	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	4239
4104	Serge	4240	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3243	Serge	4241
		4242	lpt_program_iclkip(crtc);
		4243
		4244	/* Set transcoder timing. */
4104	Serge	4245	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3243	Serge	4246
		4247	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
		4248	}
		4249
6084	serge	4250	struct intel_shared_dpll intel_get_shared_dpll(struct intel_crtc crtc,
		4251	struct intel_crtc_state *crtc_state)
3031	serge	4252	{
4104	Serge	4253	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
5354	serge	4254	struct intel_shared_dpll *pll;
6084	serge	4255	struct intel_shared_dpll_config *shared_dpll;
4104	Serge	4256	enum intel_dpll_id i;
6084	serge	4257	int max = dev_priv->num_shared_dpll;
3031	serge	4258
6084	serge	4259	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
		4260
3031	serge	4261	if (HAS_PCH_IBX(dev_priv->dev)) {
		4262	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4104	Serge	4263	i = (enum intel_dpll_id) crtc->pipe;
		4264	pll = &dev_priv->shared_dplls[i];
3031	serge	4265
4104	Serge	4266	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
		4267	crtc->base.base.id, pll->name);
3031	serge	4268
6084	serge	4269	WARN_ON(shared_dpll[i].crtc_mask);
5060	serge	4270
3031	serge	4271	goto found;
		4272	}
		4273
6084	serge	4274	if (IS_BROXTON(dev_priv->dev)) {
		4275	/* PLL is attached to port in bxt */
		4276	struct intel_encoder *encoder;
		4277	struct intel_digital_port *intel_dig_port;
		4278
		4279	encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
		4280	if (WARN_ON(!encoder))
		4281	return NULL;
		4282
		4283	intel_dig_port = enc_to_dig_port(&encoder->base);
		4284	/* 1:1 mapping between ports and PLLs */
		4285	i = (enum intel_dpll_id)intel_dig_port->port;
4104	Serge	4286	pll = &dev_priv->shared_dplls[i];
6084	serge	4287	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
		4288	crtc->base.base.id, pll->name);
		4289	WARN_ON(shared_dpll[i].crtc_mask);
3031	serge	4290
6084	serge	4291	goto found;
		4292	} else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
		4293	/* Do not consider SPLL */
		4294	max = 2;
		4295
		4296	for (i = 0; i < max; i++) {
		4297	pll = &dev_priv->shared_dplls[i];
		4298
3031	serge	4299	/* Only want to check enabled timings first */
6084	serge	4300	if (shared_dpll[i].crtc_mask == 0)
3031	serge	4301	continue;
		4302
6084	serge	4303	if (memcmp(&crtc_state->dpll_hw_state,
		4304	&shared_dpll[i].hw_state,
		4305	sizeof(crtc_state->dpll_hw_state)) == 0) {
5354	serge	4306	DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
		4307	crtc->base.base.id, pll->name,
6084	serge	4308	shared_dpll[i].crtc_mask,
5354	serge	4309	pll->active);
3031	serge	4310	goto found;
		4311	}
		4312	}
		4313
		4314	/* Ok no matching timings, maybe there's a free one? */
4104	Serge	4315	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		4316	pll = &dev_priv->shared_dplls[i];
6084	serge	4317	if (shared_dpll[i].crtc_mask == 0) {
4104	Serge	4318	DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
		4319	crtc->base.base.id, pll->name);
3031	serge	4320	goto found;
		4321	}
		4322	}
		4323
		4324	return NULL;
		4325
		4326	found:
6084	serge	4327	if (shared_dpll[i].crtc_mask == 0)
		4328	shared_dpll[i].hw_state =
		4329	crtc_state->dpll_hw_state;
5060	serge	4330
6084	serge	4331	crtc_state->shared_dpll = i;
4104	Serge	4332	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
		4333	pipe_name(crtc->pipe));
		4334
6084	serge	4335	shared_dpll[i].crtc_mask \|= 1 << crtc->pipe;
3031	serge	4336
		4337	return pll;
		4338	}
		4339
6084	serge	4340	static void intel_shared_dpll_commit(struct drm_atomic_state *state)
5354	serge	4341	{
6084	serge	4342	struct drm_i915_private *dev_priv = to_i915(state->dev);
		4343	struct intel_shared_dpll_config *shared_dpll;
5354	serge	4344	struct intel_shared_dpll *pll;
		4345	enum intel_dpll_id i;
		4346
6084	serge	4347	if (!to_intel_atomic_state(state)->dpll_set)
		4348	return;
		4349
		4350	shared_dpll = to_intel_atomic_state(state)->shared_dpll;
5354	serge	4351	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		4352	pll = &dev_priv->shared_dplls[i];
6084	serge	4353	pll->config = shared_dpll[i];
		4354	}
		4355	}
5354	serge	4356
6084	serge	4357	static void cpt_verify_modeset(struct drm_device *dev, int pipe)
		4358	{
		4359	struct drm_i915_private *dev_priv = dev->dev_private;
		4360	int dslreg = PIPEDSL(pipe);
		4361	u32 temp;
5354	serge	4362
6084	serge	4363	temp = I915_READ(dslreg);
		4364	udelay(500);
		4365	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		4366	if (wait_for(I915_READ(dslreg) != temp, 5))
		4367	DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5354	serge	4368	}
6084	serge	4369	}
5354	serge	4370
6084	serge	4371	static int
		4372	skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
		4373	unsigned scaler_user, int *scaler_id, unsigned int rotation,
		4374	int src_w, int src_h, int dst_w, int dst_h)
		4375	{
		4376	struct intel_crtc_scaler_state *scaler_state =
		4377	&crtc_state->scaler_state;
		4378	struct intel_crtc *intel_crtc =
		4379	to_intel_crtc(crtc_state->base.crtc);
		4380	int need_scaling;
5354	serge	4381
6084	serge	4382	need_scaling = intel_rotation_90_or_270(rotation) ?
		4383	(src_h != dst_w \|\| src_w != dst_h):
		4384	(src_w != dst_w \|\| src_h != dst_h);
		4385
		4386	/*
		4387	* if plane is being disabled or scaler is no more required or force detach
		4388	* - free scaler binded to this plane/crtc
		4389	* - in order to do this, update crtc->scaler_usage
		4390	*
		4391	* Here scaler state in crtc_state is set free so that
		4392	* scaler can be assigned to other user. Actual register
		4393	* update to free the scaler is done in plane/panel-fit programming.
		4394	* For this purpose crtc/plane_state->scaler_id isn't reset here.
		4395	*/
		4396	if (force_detach \|\| !need_scaling) {
		4397	if (*scaler_id >= 0) {
		4398	scaler_state->scaler_users &= ~(1 << scaler_user);
		4399	scaler_state->scalers[*scaler_id].in_use = 0;
		4400
		4401	DRM_DEBUG_KMS("scaler_user index %u.%u: "
		4402	"Staged freeing scaler id %d scaler_users = 0x%x\n",
		4403	intel_crtc->pipe, scaler_user, *scaler_id,
		4404	scaler_state->scaler_users);
		4405	*scaler_id = -1;
		4406	}
		4407	return 0;
5354	serge	4408	}
		4409
6084	serge	4410	/* range checks */
		4411	if (src_w < SKL_MIN_SRC_W \|\| src_h < SKL_MIN_SRC_H \|\|
		4412	dst_w < SKL_MIN_DST_W \|\| dst_h < SKL_MIN_DST_H \|\|
		4413
		4414	src_w > SKL_MAX_SRC_W \|\| src_h > SKL_MAX_SRC_H \|\|
		4415	dst_w > SKL_MAX_DST_W \|\| dst_h > SKL_MAX_DST_H) {
		4416	DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
		4417	"size is out of scaler range\n",
		4418	intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
		4419	return -EINVAL;
		4420	}
		4421
		4422	/* mark this plane as a scaler user in crtc_state */
		4423	scaler_state->scaler_users \|= (1 << scaler_user);
		4424	DRM_DEBUG_KMS("scaler_user index %u.%u: "
		4425	"staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
		4426	intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
		4427	scaler_state->scaler_users);
		4428
		4429	return 0;
5354	serge	4430	}
		4431
6084	serge	4432	/**
		4433	* skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
		4434	*
		4435	* @state: crtc's scaler state
		4436	*
		4437	* Return
		4438	* 0 - scaler_usage updated successfully
		4439	* error - requested scaling cannot be supported or other error condition
		4440	*/
		4441	int skl_update_scaler_crtc(struct intel_crtc_state *state)
5354	serge	4442	{
6084	serge	4443	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
		4444	const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5354	serge	4445
6084	serge	4446	DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
		4447	intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
5354	serge	4448
6084	serge	4449	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
		4450	&state->scaler_state.scaler_id, DRM_ROTATE_0,
		4451	state->pipe_src_w, state->pipe_src_h,
		4452	adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
5354	serge	4453	}
		4454
6084	serge	4455	/**
		4456	* skl_update_scaler_plane - Stages update to scaler state for a given plane.
		4457	*
		4458	* @state: crtc's scaler state
		4459	* @plane_state: atomic plane state to update
		4460	*
		4461	* Return
		4462	* 0 - scaler_usage updated successfully
		4463	* error - requested scaling cannot be supported or other error condition
		4464	*/
		4465	static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
		4466	struct intel_plane_state *plane_state)
5354	serge	4467	{
		4468
6084	serge	4469	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
		4470	struct intel_plane *intel_plane =
		4471	to_intel_plane(plane_state->base.plane);
		4472	struct drm_framebuffer *fb = plane_state->base.fb;
		4473	int ret;
5354	serge	4474
6084	serge	4475	bool force_detach = !fb \|\| !plane_state->visible;
5354	serge	4476
6084	serge	4477	DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
		4478	intel_plane->base.base.id, intel_crtc->pipe,
		4479	drm_plane_index(&intel_plane->base));
		4480
		4481	ret = skl_update_scaler(crtc_state, force_detach,
		4482	drm_plane_index(&intel_plane->base),
		4483	&plane_state->scaler_id,
		4484	plane_state->base.rotation,
		4485	drm_rect_width(&plane_state->src) >> 16,
		4486	drm_rect_height(&plane_state->src) >> 16,
		4487	drm_rect_width(&plane_state->dst),
		4488	drm_rect_height(&plane_state->dst));
		4489
		4490	if (ret \|\| plane_state->scaler_id < 0)
		4491	return ret;
		4492
		4493	/* check colorkey */
		4494	if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
		4495	DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
		4496	intel_plane->base.base.id);
		4497	return -EINVAL;
5354	serge	4498	}
6084	serge	4499
		4500	/* Check src format */
		4501	switch (fb->pixel_format) {
		4502	case DRM_FORMAT_RGB565:
		4503	case DRM_FORMAT_XBGR8888:
		4504	case DRM_FORMAT_XRGB8888:
		4505	case DRM_FORMAT_ABGR8888:
		4506	case DRM_FORMAT_ARGB8888:
		4507	case DRM_FORMAT_XRGB2101010:
		4508	case DRM_FORMAT_XBGR2101010:
		4509	case DRM_FORMAT_YUYV:
		4510	case DRM_FORMAT_YVYU:
		4511	case DRM_FORMAT_UYVY:
		4512	case DRM_FORMAT_VYUY:
		4513	break;
		4514	default:
		4515	DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
		4516	intel_plane->base.base.id, fb->base.id, fb->pixel_format);
		4517	return -EINVAL;
		4518	}
		4519
		4520	return 0;
5354	serge	4521	}
		4522
6084	serge	4523	static void skylake_scaler_disable(struct intel_crtc *crtc)
2342	Serge	4524	{
6084	serge	4525	int i;
2342	Serge	4526
6084	serge	4527	for (i = 0; i < crtc->num_scalers; i++)
		4528	skl_detach_scaler(crtc, i);
2342	Serge	4529	}
		4530
5354	serge	4531	static void skylake_pfit_enable(struct intel_crtc *crtc)
		4532	{
		4533	struct drm_device *dev = crtc->base.dev;
		4534	struct drm_i915_private *dev_priv = dev->dev_private;
		4535	int pipe = crtc->pipe;
6084	serge	4536	struct intel_crtc_scaler_state *scaler_state =
		4537	&crtc->config->scaler_state;
5354	serge	4538
6084	serge	4539	DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
		4540
		4541	if (crtc->config->pch_pfit.enabled) {
		4542	int id;
		4543
		4544	if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
		4545	DRM_ERROR("Requesting pfit without getting a scaler first\n");
		4546	return;
		4547	}
		4548
		4549	id = scaler_state->scaler_id;
		4550	I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN \|
		4551	PS_FILTER_MEDIUM \| scaler_state->scalers[id].mode);
		4552	I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
		4553	I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
		4554
		4555	DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
5354	serge	4556	}
		4557	}
		4558
4104	Serge	4559	static void ironlake_pfit_enable(struct intel_crtc *crtc)
		4560	{
		4561	struct drm_device *dev = crtc->base.dev;
		4562	struct drm_i915_private *dev_priv = dev->dev_private;
		4563	int pipe = crtc->pipe;
		4564
6084	serge	4565	if (crtc->config->pch_pfit.enabled) {
4104	Serge	4566	/* Force use of hard-coded filter coefficients
		4567	* as some pre-programmed values are broken,
		4568	* e.g. x201.
		4569	*/
		4570	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		4571	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3 \|
		4572	PF_PIPE_SEL_IVB(pipe));
		4573	else
		4574	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
6084	serge	4575	I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
		4576	I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4104	Serge	4577	}
		4578	}
		4579
4560	Serge	4580	void hsw_enable_ips(struct intel_crtc *crtc)
		4581	{
5060	serge	4582	struct drm_device *dev = crtc->base.dev;
		4583	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	4584
6084	serge	4585	if (!crtc->config->ips_enabled)
4560	Serge	4586	return;
		4587
5060	serge	4588	/* We can only enable IPS after we enable a plane and wait for a vblank */
		4589	intel_wait_for_vblank(dev, crtc->pipe);
		4590
4560	Serge	4591	assert_plane_enabled(dev_priv, crtc->plane);
5060	serge	4592	if (IS_BROADWELL(dev)) {
4560	Serge	4593	mutex_lock(&dev_priv->rps.hw_lock);
		4594	WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
		4595	mutex_unlock(&dev_priv->rps.hw_lock);
		4596	/* Quoting Art Runyan: "its not safe to expect any particular
		4597	* value in IPS_CTL bit 31 after enabling IPS through the
		4598	* mailbox." Moreover, the mailbox may return a bogus state,
		4599	* so we need to just enable it and continue on.
		4600	*/
		4601	} else {
		4602	I915_WRITE(IPS_CTL, IPS_ENABLE);
		4603	/* The bit only becomes 1 in the next vblank, so this wait here
		4604	* is essentially intel_wait_for_vblank. If we don't have this
		4605	* and don't wait for vblanks until the end of crtc_enable, then
		4606	* the HW state readout code will complain that the expected
		4607	* IPS_CTL value is not the one we read. */
		4608	if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
		4609	DRM_ERROR("Timed out waiting for IPS enable\n");
		4610	}
		4611	}
		4612
		4613	void hsw_disable_ips(struct intel_crtc *crtc)
		4614	{
		4615	struct drm_device *dev = crtc->base.dev;
		4616	struct drm_i915_private *dev_priv = dev->dev_private;
		4617
6084	serge	4618	if (!crtc->config->ips_enabled)
4560	Serge	4619	return;
		4620
		4621	assert_plane_enabled(dev_priv, crtc->plane);
5060	serge	4622	if (IS_BROADWELL(dev)) {
4560	Serge	4623	mutex_lock(&dev_priv->rps.hw_lock);
		4624	WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
		4625	mutex_unlock(&dev_priv->rps.hw_lock);
5060	serge	4626	/* wait for pcode to finish disabling IPS, which may take up to 42ms */
		4627	if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
		4628	DRM_ERROR("Timed out waiting for IPS disable\n");
4560	Serge	4629	} else {
		4630	I915_WRITE(IPS_CTL, 0);
		4631	POSTING_READ(IPS_CTL);
		4632	}
		4633
		4634	/* We need to wait for a vblank before we can disable the plane. */
		4635	intel_wait_for_vblank(dev, crtc->pipe);
		4636	}
		4637
		4638	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		4639	static void intel_crtc_load_lut(struct drm_crtc *crtc)
		4640	{
		4641	struct drm_device *dev = crtc->dev;
		4642	struct drm_i915_private *dev_priv = dev->dev_private;
		4643	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4644	enum pipe pipe = intel_crtc->pipe;
		4645	int i;
		4646	bool reenable_ips = false;
		4647
		4648	/* The clocks have to be on to load the palette. */
6084	serge	4649	if (!crtc->state->active)
4560	Serge	4650	return;
		4651
6084	serge	4652	if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
5354	serge	4653	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4560	Serge	4654	assert_dsi_pll_enabled(dev_priv);
		4655	else
		4656	assert_pll_enabled(dev_priv, pipe);
		4657	}
		4658
		4659	/* Workaround : Do not read or write the pipe palette/gamma data while
		4660	* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
		4661	*/
6084	serge	4662	if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4560	Serge	4663	((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
		4664	GAMMA_MODE_MODE_SPLIT)) {
		4665	hsw_disable_ips(intel_crtc);
		4666	reenable_ips = true;
		4667	}
		4668
		4669	for (i = 0; i < 256; i++) {
6084	serge	4670	u32 palreg;
		4671
		4672	if (HAS_GMCH_DISPLAY(dev))
		4673	palreg = PALETTE(pipe, i);
		4674	else
		4675	palreg = LGC_PALETTE(pipe, i);
		4676
		4677	I915_WRITE(palreg,
4560	Serge	4678	(intel_crtc->lut_r[i] << 16) \|
		4679	(intel_crtc->lut_g[i] << 8) \|
		4680	intel_crtc->lut_b[i]);
		4681	}
		4682
		4683	if (reenable_ips)
		4684	hsw_enable_ips(intel_crtc);
		4685	}
		4686
6084	serge	4687	static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5060	serge	4688	{
6084	serge	4689	if (intel_crtc->overlay) {
5060	serge	4690	struct drm_device *dev = intel_crtc->base.dev;
		4691	struct drm_i915_private *dev_priv = dev->dev_private;
		4692
		4693	mutex_lock(&dev->struct_mutex);
		4694	dev_priv->mm.interruptible = false;
5354	serge	4695	// (void) intel_overlay_switch_off(intel_crtc->overlay);
6084	serge	4696	dev_priv->mm.interruptible = true;
5060	serge	4697	mutex_unlock(&dev->struct_mutex);
		4698	}
		4699
		4700	/* Let userspace switch the overlay on again. In most cases userspace
		4701	* has to recompute where to put it anyway.
		4702	*/
		4703	}
		4704
6084	serge	4705	/**
		4706	* intel_post_enable_primary - Perform operations after enabling primary plane
		4707	* @crtc: the CRTC whose primary plane was just enabled
		4708	*
		4709	* Performs potentially sleeping operations that must be done after the primary
		4710	* plane is enabled, such as updating FBC and IPS. Note that this may be
		4711	* called due to an explicit primary plane update, or due to an implicit
		4712	* re-enable that is caused when a sprite plane is updated to no longer
		4713	* completely hide the primary plane.
		4714	*/
		4715	static void
		4716	intel_post_enable_primary(struct drm_crtc *crtc)
5060	serge	4717	{
		4718	struct drm_device *dev = crtc->dev;
6084	serge	4719	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	4720	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4721	int pipe = intel_crtc->pipe;
		4722
6084	serge	4723	/*
		4724	* BDW signals flip done immediately if the plane
		4725	* is disabled, even if the plane enable is already
		4726	* armed to occur at the next vblank :(
		4727	*/
		4728	if (IS_BROADWELL(dev))
		4729	intel_wait_for_vblank(dev, pipe);
5060	serge	4730
6084	serge	4731	/*
		4732	* FIXME IPS should be fine as long as one plane is
		4733	* enabled, but in practice it seems to have problems
		4734	* when going from primary only to sprite only and vice
		4735	* versa.
		4736	*/
5060	serge	4737	hsw_enable_ips(intel_crtc);
		4738
5354	serge	4739	/*
6084	serge	4740	* Gen2 reports pipe underruns whenever all planes are disabled.
		4741	* So don't enable underrun reporting before at least some planes
		4742	* are enabled.
		4743	* FIXME: Need to fix the logic to work when we turn off all planes
		4744	* but leave the pipe running.
5354	serge	4745	*/
6084	serge	4746	if (IS_GEN2(dev))
		4747	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
		4748
		4749	/* Underruns don't raise interrupts, so check manually. */
		4750	if (HAS_GMCH_DISPLAY(dev))
		4751	i9xx_check_fifo_underruns(dev_priv);
5060	serge	4752	}
		4753
6084	serge	4754	/**
		4755	* intel_pre_disable_primary - Perform operations before disabling primary plane
		4756	* @crtc: the CRTC whose primary plane is to be disabled
		4757	*
		4758	* Performs potentially sleeping operations that must be done before the
		4759	* primary plane is disabled, such as updating FBC and IPS. Note that this may
		4760	* be called due to an explicit primary plane update, or due to an implicit
		4761	* disable that is caused when a sprite plane completely hides the primary
		4762	* plane.
		4763	*/
		4764	static void
		4765	intel_pre_disable_primary(struct drm_crtc *crtc)
5060	serge	4766	{
		4767	struct drm_device *dev = crtc->dev;
		4768	struct drm_i915_private *dev_priv = dev->dev_private;
		4769	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4770	int pipe = intel_crtc->pipe;
		4771
6084	serge	4772	/*
		4773	* Gen2 reports pipe underruns whenever all planes are disabled.
		4774	* So diasble underrun reporting before all the planes get disabled.
		4775	* FIXME: Need to fix the logic to work when we turn off all planes
		4776	* but leave the pipe running.
		4777	*/
		4778	if (IS_GEN2(dev))
		4779	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5060	serge	4780
6084	serge	4781	/*
		4782	* Vblank time updates from the shadow to live plane control register
		4783	* are blocked if the memory self-refresh mode is active at that
		4784	* moment. So to make sure the plane gets truly disabled, disable
		4785	* first the self-refresh mode. The self-refresh enable bit in turn
		4786	* will be checked/applied by the HW only at the next frame start
		4787	* event which is after the vblank start event, so we need to have a
		4788	* wait-for-vblank between disabling the plane and the pipe.
		4789	*/
		4790	if (HAS_GMCH_DISPLAY(dev)) {
		4791	intel_set_memory_cxsr(dev_priv, false);
		4792	dev_priv->wm.vlv.cxsr = false;
		4793	intel_wait_for_vblank(dev, pipe);
		4794	}
5060	serge	4795
6084	serge	4796	/*
		4797	* FIXME IPS should be fine as long as one plane is
		4798	* enabled, but in practice it seems to have problems
		4799	* when going from primary only to sprite only and vice
		4800	* versa.
		4801	*/
5060	serge	4802	hsw_disable_ips(intel_crtc);
6084	serge	4803	}
5060	serge	4804
6084	serge	4805	static void intel_post_plane_update(struct intel_crtc *crtc)
		4806	{
		4807	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
		4808	struct drm_device *dev = crtc->base.dev;
		4809	struct drm_i915_private *dev_priv = dev->dev_private;
		4810	struct drm_plane *plane;
5354	serge	4811
6084	serge	4812	if (atomic->wait_vblank)
		4813	intel_wait_for_vblank(dev, crtc->pipe);
		4814
		4815	intel_frontbuffer_flip(dev, atomic->fb_bits);
		4816
		4817	if (atomic->disable_cxsr)
		4818	crtc->wm.cxsr_allowed = true;
		4819
		4820	if (crtc->atomic.update_wm_post)
		4821	intel_update_watermarks(&crtc->base);
		4822
		4823	if (atomic->update_fbc)
		4824	intel_fbc_update(dev_priv);
		4825
		4826	if (atomic->post_enable_primary)
		4827	intel_post_enable_primary(&crtc->base);
		4828
		4829	drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
		4830	intel_update_sprite_watermarks(plane, &crtc->base,
		4831	0, 0, 0, false, false);
		4832
		4833	memset(atomic, 0, sizeof(*atomic));
		4834	}
		4835
		4836	static void intel_pre_plane_update(struct intel_crtc *crtc)
		4837	{
		4838	struct drm_device *dev = crtc->base.dev;
		4839	struct drm_i915_private *dev_priv = dev->dev_private;
		4840	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
		4841	struct drm_plane *p;
		4842
		4843	/* Track fb's for any planes being disabled */
		4844	drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
		4845	struct intel_plane *plane = to_intel_plane(p);
		4846
		4847	mutex_lock(&dev->struct_mutex);
		4848	i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
		4849	plane->frontbuffer_bit);
		4850	mutex_unlock(&dev->struct_mutex);
		4851	}
		4852
6320	serge	4853	if (atomic->wait_for_flips)
		4854	intel_crtc_wait_for_pending_flips(&crtc->base);
		4855
6084	serge	4856	if (atomic->disable_fbc)
		4857	intel_fbc_disable_crtc(crtc);
		4858
		4859	if (crtc->atomic.disable_ips)
		4860	hsw_disable_ips(crtc);
		4861
		4862	if (atomic->pre_disable_primary)
		4863	intel_pre_disable_primary(&crtc->base);
		4864
		4865	if (atomic->disable_cxsr) {
		4866	crtc->wm.cxsr_allowed = false;
		4867	intel_set_memory_cxsr(dev_priv, false);
		4868	}
		4869	}
		4870
		4871	static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
		4872	{
		4873	struct drm_device *dev = crtc->dev;
		4874	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4875	struct drm_plane *p;
		4876	int pipe = intel_crtc->pipe;
		4877
		4878	intel_crtc_dpms_overlay_disable(intel_crtc);
		4879
		4880	drm_for_each_plane_mask(p, dev, plane_mask)
		4881	to_intel_plane(p)->disable_plane(p, crtc);
		4882
5354	serge	4883	/*
		4884	* FIXME: Once we grow proper nuclear flip support out of this we need
		4885	* to compute the mask of flip planes precisely. For the time being
		4886	* consider this a flip to a NULL plane.
		4887	*/
6320	serge	4888	intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
5060	serge	4889	}
		4890
2327	Serge	4891	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		4892	{
6084	serge	4893	struct drm_device *dev = crtc->dev;
		4894	struct drm_i915_private *dev_priv = dev->dev_private;
		4895	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	4896	struct intel_encoder *encoder;
6084	serge	4897	int pipe = intel_crtc->pipe;
2327	Serge	4898
6084	serge	4899	if (WARN_ON(intel_crtc->active))
		4900	return;
3031	serge	4901
6084	serge	4902	if (intel_crtc->config->has_pch_encoder)
5060	serge	4903	intel_prepare_shared_dpll(intel_crtc);
		4904
6084	serge	4905	if (intel_crtc->config->has_dp_encoder)
		4906	intel_dp_set_m_n(intel_crtc, M1_N1);
5060	serge	4907
		4908	intel_set_pipe_timings(intel_crtc);
		4909
6084	serge	4910	if (intel_crtc->config->has_pch_encoder) {
5060	serge	4911	intel_cpu_transcoder_set_m_n(intel_crtc,
6084	serge	4912	&intel_crtc->config->fdi_m_n, NULL);
5060	serge	4913	}
		4914
		4915	ironlake_set_pipeconf(crtc);
		4916
6084	serge	4917	intel_crtc->active = true;
4104	Serge	4918
5354	serge	4919	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
		4920	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4104	Serge	4921
		4922	for_each_encoder_on_crtc(dev, crtc, encoder)
		4923	if (encoder->pre_enable)
		4924	encoder->pre_enable(encoder);
2327	Serge	4925
6084	serge	4926	if (intel_crtc->config->has_pch_encoder) {
3243	Serge	4927	/* Note: FDI PLL enabling _must_ be done before we enable the
		4928	* cpu pipes, hence this is separate from all the other fdi/pch
		4929	* enabling. */
3031	serge	4930	ironlake_fdi_pll_enable(intel_crtc);
		4931	} else {
		4932	assert_fdi_tx_disabled(dev_priv, pipe);
		4933	assert_fdi_rx_disabled(dev_priv, pipe);
		4934	}
2327	Serge	4935
4104	Serge	4936	ironlake_pfit_enable(intel_crtc);
3031	serge	4937
6084	serge	4938	/*
		4939	* On ILK+ LUT must be loaded before the pipe is running but with
		4940	* clocks enabled
		4941	*/
		4942	intel_crtc_load_lut(crtc);
2327	Serge	4943
4560	Serge	4944	intel_update_watermarks(crtc);
5060	serge	4945	intel_enable_pipe(intel_crtc);
2327	Serge	4946
6084	serge	4947	if (intel_crtc->config->has_pch_encoder)
		4948	ironlake_pch_enable(crtc);
2327	Serge	4949
6084	serge	4950	assert_vblank_disabled(crtc);
		4951	drm_crtc_vblank_on(crtc);
		4952
3031	serge	4953	for_each_encoder_on_crtc(dev, crtc, encoder)
		4954	encoder->enable(encoder);
		4955
		4956	if (HAS_PCH_CPT(dev))
4104	Serge	4957	cpt_verify_modeset(dev, intel_crtc->pipe);
2327	Serge	4958	}
		4959
4104	Serge	4960	/* IPS only exists on ULT machines and is tied to pipe A. */
		4961	static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
		4962	{
		4963	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
		4964	}
		4965
3243	Serge	4966	static void haswell_crtc_enable(struct drm_crtc *crtc)
		4967	{
		4968	struct drm_device *dev = crtc->dev;
		4969	struct drm_i915_private *dev_priv = dev->dev_private;
		4970	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4971	struct intel_encoder *encoder;
6084	serge	4972	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
		4973	struct intel_crtc_state *pipe_config =
		4974	to_intel_crtc_state(crtc->state);
		4975	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
3243	Serge	4976
6084	serge	4977	if (WARN_ON(intel_crtc->active))
3243	Serge	4978	return;
		4979
5060	serge	4980	if (intel_crtc_to_shared_dpll(intel_crtc))
		4981	intel_enable_shared_dpll(intel_crtc);
		4982
6084	serge	4983	if (intel_crtc->config->has_dp_encoder)
		4984	intel_dp_set_m_n(intel_crtc, M1_N1);
5060	serge	4985
		4986	intel_set_pipe_timings(intel_crtc);
		4987
6084	serge	4988	if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
		4989	I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
		4990	intel_crtc->config->pixel_multiplier - 1);
5354	serge	4991	}
		4992
6084	serge	4993	if (intel_crtc->config->has_pch_encoder) {
5060	serge	4994	intel_cpu_transcoder_set_m_n(intel_crtc,
6084	serge	4995	&intel_crtc->config->fdi_m_n, NULL);
5060	serge	4996	}
		4997
		4998	haswell_set_pipeconf(crtc);
		4999
		5000	intel_set_pipe_csc(crtc);
		5001
3243	Serge	5002	intel_crtc->active = true;
4104	Serge	5003
5354	serge	5004	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6084	serge	5005	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5006	if (encoder->pre_pll_enable)
		5007	encoder->pre_pll_enable(encoder);
3243	Serge	5008	if (encoder->pre_enable)
		5009	encoder->pre_enable(encoder);
6084	serge	5010	}
3243	Serge	5011
6084	serge	5012	if (intel_crtc->config->has_pch_encoder) {
5354	serge	5013	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
		5014	true);
5060	serge	5015	dev_priv->display.fdi_link_train(crtc);
		5016	}
		5017
6084	serge	5018	if (!is_dsi)
		5019	intel_ddi_enable_pipe_clock(intel_crtc);
3243	Serge	5020
6084	serge	5021	if (INTEL_INFO(dev)->gen >= 9)
5354	serge	5022	skylake_pfit_enable(intel_crtc);
		5023	else
6084	serge	5024	ironlake_pfit_enable(intel_crtc);
3243	Serge	5025
		5026	/*
		5027	* On ILK+ LUT must be loaded before the pipe is running but with
		5028	* clocks enabled
		5029	*/
		5030	intel_crtc_load_lut(crtc);
		5031
		5032	intel_ddi_set_pipe_settings(crtc);
6084	serge	5033	if (!is_dsi)
		5034	intel_ddi_enable_transcoder_func(crtc);
3243	Serge	5035
4560	Serge	5036	intel_update_watermarks(crtc);
5060	serge	5037	intel_enable_pipe(intel_crtc);
3243	Serge	5038
6084	serge	5039	if (intel_crtc->config->has_pch_encoder)
3243	Serge	5040	lpt_pch_enable(crtc);
		5041
6084	serge	5042	if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5060	serge	5043	intel_ddi_set_vc_payload_alloc(crtc, true);
		5044
6084	serge	5045	assert_vblank_disabled(crtc);
		5046	drm_crtc_vblank_on(crtc);
		5047
4560	Serge	5048	for_each_encoder_on_crtc(dev, crtc, encoder) {
3243	Serge	5049	encoder->enable(encoder);
4560	Serge	5050	intel_opregion_notify_encoder(encoder, true);
		5051	}
3243	Serge	5052
4560	Serge	5053	/* If we change the relative order between pipe/planes enabling, we need
		5054	* to change the workaround. */
6084	serge	5055	hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
		5056	if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
		5057	intel_wait_for_vblank(dev, hsw_workaround_pipe);
		5058	intel_wait_for_vblank(dev, hsw_workaround_pipe);
5354	serge	5059	}
		5060	}
		5061
6084	serge	5062	static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4104	Serge	5063	{
		5064	struct drm_device *dev = crtc->base.dev;
		5065	struct drm_i915_private *dev_priv = dev->dev_private;
		5066	int pipe = crtc->pipe;
		5067
		5068	/* To avoid upsetting the power well on haswell only disable the pfit if
		5069	* it's in use. The hw state code will make sure we get this right. */
6084	serge	5070	if (force \|\| crtc->config->pch_pfit.enabled) {
4104	Serge	5071	I915_WRITE(PF_CTL(pipe), 0);
		5072	I915_WRITE(PF_WIN_POS(pipe), 0);
		5073	I915_WRITE(PF_WIN_SZ(pipe), 0);
		5074	}
		5075	}
		5076
2327	Serge	5077	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		5078	{
6084	serge	5079	struct drm_device *dev = crtc->dev;
		5080	struct drm_i915_private *dev_priv = dev->dev_private;
		5081	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	5082	struct intel_encoder *encoder;
6084	serge	5083	int pipe = intel_crtc->pipe;
		5084	u32 reg, temp;
2327	Serge	5085
6084	serge	5086	for_each_encoder_on_crtc(dev, crtc, encoder)
		5087	encoder->disable(encoder);
2327	Serge	5088
5354	serge	5089	drm_crtc_vblank_off(crtc);
		5090	assert_vblank_disabled(crtc);
		5091
6084	serge	5092	if (intel_crtc->config->has_pch_encoder)
5354	serge	5093	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
2327	Serge	5094
5354	serge	5095	intel_disable_pipe(intel_crtc);
		5096
6084	serge	5097	ironlake_pfit_disable(intel_crtc, false);
2327	Serge	5098
6084	serge	5099	if (intel_crtc->config->has_pch_encoder)
		5100	ironlake_fdi_disable(crtc);
		5101
3031	serge	5102	for_each_encoder_on_crtc(dev, crtc, encoder)
		5103	if (encoder->post_disable)
		5104	encoder->post_disable(encoder);
		5105
6084	serge	5106	if (intel_crtc->config->has_pch_encoder) {
		5107	ironlake_disable_pch_transcoder(dev_priv, pipe);
2327	Serge	5108
6084	serge	5109	if (HAS_PCH_CPT(dev)) {
		5110	/* disable TRANS_DP_CTL */
		5111	reg = TRANS_DP_CTL(pipe);
		5112	temp = I915_READ(reg);
4104	Serge	5113	temp &= ~(TRANS_DP_OUTPUT_ENABLE \|
		5114	TRANS_DP_PORT_SEL_MASK);
6084	serge	5115	temp \|= TRANS_DP_PORT_SEL_NONE;
		5116	I915_WRITE(reg, temp);
2327	Serge	5117
6084	serge	5118	/* disable DPLL_SEL */
		5119	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	5120	temp &= ~(TRANS_DPLL_ENABLE(pipe) \| TRANS_DPLLB_SEL(pipe));
6084	serge	5121	I915_WRITE(PCH_DPLL_SEL, temp);
		5122	}
2327	Serge	5123
6084	serge	5124	ironlake_fdi_pll_disable(intel_crtc);
4104	Serge	5125	}
2327	Serge	5126	}
		5127
3243	Serge	5128	static void haswell_crtc_disable(struct drm_crtc *crtc)
		5129	{
		5130	struct drm_device *dev = crtc->dev;
		5131	struct drm_i915_private *dev_priv = dev->dev_private;
		5132	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5133	struct intel_encoder *encoder;
6084	serge	5134	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
		5135	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
3243	Serge	5136
4560	Serge	5137	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5138	intel_opregion_notify_encoder(encoder, false);
3243	Serge	5139	encoder->disable(encoder);
4560	Serge	5140	}
3243	Serge	5141
6084	serge	5142	drm_crtc_vblank_off(crtc);
		5143	assert_vblank_disabled(crtc);
		5144
		5145	if (intel_crtc->config->has_pch_encoder)
5354	serge	5146	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
		5147	false);
		5148	intel_disable_pipe(intel_crtc);
3243	Serge	5149
6084	serge	5150	if (intel_crtc->config->dp_encoder_is_mst)
5097	serge	5151	intel_ddi_set_vc_payload_alloc(crtc, false);
		5152
6084	serge	5153	if (!is_dsi)
		5154	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3243	Serge	5155
6084	serge	5156	if (INTEL_INFO(dev)->gen >= 9)
		5157	skylake_scaler_disable(intel_crtc);
5354	serge	5158	else
6084	serge	5159	ironlake_pfit_disable(intel_crtc, false);
3243	Serge	5160
6084	serge	5161	if (!is_dsi)
		5162	intel_ddi_disable_pipe_clock(intel_crtc);
3243	Serge	5163
6084	serge	5164	if (intel_crtc->config->has_pch_encoder) {
3243	Serge	5165	lpt_disable_pch_transcoder(dev_priv);
		5166	intel_ddi_fdi_disable(crtc);
		5167	}
		5168
5060	serge	5169	for_each_encoder_on_crtc(dev, crtc, encoder)
		5170	if (encoder->post_disable)
		5171	encoder->post_disable(encoder);
3243	Serge	5172	}
		5173
4104	Serge	5174	static void i9xx_pfit_enable(struct intel_crtc *crtc)
		5175	{
		5176	struct drm_device *dev = crtc->base.dev;
		5177	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	5178	struct intel_crtc_state *pipe_config = crtc->config;
4104	Serge	5179
6084	serge	5180	if (!pipe_config->gmch_pfit.control)
4104	Serge	5181	return;
		5182
		5183	/*
		5184	* The panel fitter should only be adjusted whilst the pipe is disabled,
		5185	* according to register description and PRM.
		5186	*/
		5187	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
		5188	assert_pipe_disabled(dev_priv, crtc->pipe);
		5189
		5190	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
		5191	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
		5192
		5193	/* Border color in case we don't scale up to the full screen. Black by
		5194	* default, change to something else for debugging. */
		5195	I915_WRITE(BCLRPAT(crtc->pipe), 0);
		5196	}
		5197
5060	serge	5198	static enum intel_display_power_domain port_to_power_domain(enum port port)
4560	Serge	5199	{
5060	serge	5200	switch (port) {
		5201	case PORT_A:
		5202	return POWER_DOMAIN_PORT_DDI_A_4_LANES;
		5203	case PORT_B:
		5204	return POWER_DOMAIN_PORT_DDI_B_4_LANES;
		5205	case PORT_C:
		5206	return POWER_DOMAIN_PORT_DDI_C_4_LANES;
		5207	case PORT_D:
		5208	return POWER_DOMAIN_PORT_DDI_D_4_LANES;
6084	serge	5209	case PORT_E:
		5210	return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5060	serge	5211	default:
6084	serge	5212	MISSING_CASE(port);
5060	serge	5213	return POWER_DOMAIN_PORT_OTHER;
		5214	}
		5215	}
		5216
6084	serge	5217	static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
		5218	{
		5219	switch (port) {
		5220	case PORT_A:
		5221	return POWER_DOMAIN_AUX_A;
		5222	case PORT_B:
		5223	return POWER_DOMAIN_AUX_B;
		5224	case PORT_C:
		5225	return POWER_DOMAIN_AUX_C;
		5226	case PORT_D:
		5227	return POWER_DOMAIN_AUX_D;
		5228	case PORT_E:
		5229	/* FIXME: Check VBT for actual wiring of PORT E */
		5230	return POWER_DOMAIN_AUX_D;
		5231	default:
		5232	MISSING_CASE(port);
		5233	return POWER_DOMAIN_AUX_A;
		5234	}
		5235	}
		5236
5060	serge	5237	#define for_each_power_domain(domain, mask) \
		5238	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
		5239	if ((1 << (domain)) & (mask))
		5240
		5241	enum intel_display_power_domain
		5242	intel_display_port_power_domain(struct intel_encoder *intel_encoder)
		5243	{
		5244	struct drm_device *dev = intel_encoder->base.dev;
		5245	struct intel_digital_port *intel_dig_port;
		5246
		5247	switch (intel_encoder->type) {
		5248	case INTEL_OUTPUT_UNKNOWN:
		5249	/* Only DDI platforms should ever use this output type */
		5250	WARN_ON_ONCE(!HAS_DDI(dev));
		5251	case INTEL_OUTPUT_DISPLAYPORT:
		5252	case INTEL_OUTPUT_HDMI:
		5253	case INTEL_OUTPUT_EDP:
		5254	intel_dig_port = enc_to_dig_port(&intel_encoder->base);
		5255	return port_to_power_domain(intel_dig_port->port);
		5256	case INTEL_OUTPUT_DP_MST:
		5257	intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
		5258	return port_to_power_domain(intel_dig_port->port);
		5259	case INTEL_OUTPUT_ANALOG:
		5260	return POWER_DOMAIN_PORT_CRT;
		5261	case INTEL_OUTPUT_DSI:
		5262	return POWER_DOMAIN_PORT_DSI;
		5263	default:
		5264	return POWER_DOMAIN_PORT_OTHER;
		5265	}
		5266	}
		5267
6084	serge	5268	enum intel_display_power_domain
		5269	intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
		5270	{
		5271	struct drm_device *dev = intel_encoder->base.dev;
		5272	struct intel_digital_port *intel_dig_port;
		5273
		5274	switch (intel_encoder->type) {
		5275	case INTEL_OUTPUT_UNKNOWN:
		5276	case INTEL_OUTPUT_HDMI:
		5277	/*
		5278	* Only DDI platforms should ever use these output types.
		5279	* We can get here after the HDMI detect code has already set
		5280	* the type of the shared encoder. Since we can't be sure
		5281	* what's the status of the given connectors, play safe and
		5282	* run the DP detection too.
		5283	*/
		5284	WARN_ON_ONCE(!HAS_DDI(dev));
		5285	case INTEL_OUTPUT_DISPLAYPORT:
		5286	case INTEL_OUTPUT_EDP:
		5287	intel_dig_port = enc_to_dig_port(&intel_encoder->base);
		5288	return port_to_aux_power_domain(intel_dig_port->port);
		5289	case INTEL_OUTPUT_DP_MST:
		5290	intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
		5291	return port_to_aux_power_domain(intel_dig_port->port);
		5292	default:
		5293	MISSING_CASE(intel_encoder->type);
		5294	return POWER_DOMAIN_AUX_A;
		5295	}
		5296	}
		5297
5060	serge	5298	static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
		5299	{
		5300	struct drm_device *dev = crtc->dev;
		5301	struct intel_encoder *intel_encoder;
		5302	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5303	enum pipe pipe = intel_crtc->pipe;
		5304	unsigned long mask;
		5305	enum transcoder transcoder;
		5306
6084	serge	5307	if (!crtc->state->active)
		5308	return 0;
		5309
5060	serge	5310	transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
		5311
		5312	mask = BIT(POWER_DOMAIN_PIPE(pipe));
		5313	mask \|= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6084	serge	5314	if (intel_crtc->config->pch_pfit.enabled \|\|
		5315	intel_crtc->config->pch_pfit.force_thru)
5060	serge	5316	mask \|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
		5317
		5318	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		5319	mask \|= BIT(intel_display_port_power_domain(intel_encoder));
		5320
		5321	return mask;
		5322	}
		5323
6084	serge	5324	static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5060	serge	5325	{
6084	serge	5326	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5327	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5328	enum intel_display_power_domain domain;
		5329	unsigned long domains, new_domains, old_domains;
5060	serge	5330
6084	serge	5331	old_domains = intel_crtc->enabled_power_domains;
		5332	intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5060	serge	5333
6084	serge	5334	domains = new_domains & ~old_domains;
5060	serge	5335
6084	serge	5336	for_each_power_domain(domain, domains)
		5337	intel_display_power_get(dev_priv, domain);
5060	serge	5338
6084	serge	5339	return old_domains & ~new_domains;
		5340	}
5060	serge	5341
6084	serge	5342	static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
		5343	unsigned long domains)
		5344	{
		5345	enum intel_display_power_domain domain;
5354	serge	5346
6084	serge	5347	for_each_power_domain(domain, domains)
		5348	intel_display_power_put(dev_priv, domain);
		5349	}
5060	serge	5350
6084	serge	5351	static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
		5352	{
		5353	struct drm_device *dev = state->dev;
		5354	struct drm_i915_private *dev_priv = dev->dev_private;
		5355	unsigned long put_domains[I915_MAX_PIPES] = {};
		5356	struct drm_crtc_state *crtc_state;
		5357	struct drm_crtc *crtc;
		5358	int i;
5060	serge	5359
6084	serge	5360	for_each_crtc_in_state(state, crtc, crtc_state, i) {
		5361	if (needs_modeset(crtc->state))
		5362	put_domains[to_intel_crtc(crtc)->pipe] =
		5363	modeset_get_crtc_power_domains(crtc);
5060	serge	5364	}
		5365
6084	serge	5366	if (dev_priv->display.modeset_commit_cdclk) {
		5367	unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
		5368
		5369	if (cdclk != dev_priv->cdclk_freq &&
		5370	!WARN_ON(!state->allow_modeset))
		5371	dev_priv->display.modeset_commit_cdclk(state);
		5372	}
		5373
		5374	for (i = 0; i < I915_MAX_PIPES; i++)
		5375	if (put_domains[i])
		5376	modeset_put_power_domains(dev_priv, put_domains[i]);
5060	serge	5377	}
		5378
6084	serge	5379	static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5060	serge	5380	{
6084	serge	5381	int max_cdclk_freq = dev_priv->max_cdclk_freq;
4560	Serge	5382
6084	serge	5383	if (INTEL_INFO(dev_priv)->gen >= 9 \|\|
		5384	IS_HASWELL(dev_priv) \|\| IS_BROADWELL(dev_priv))
		5385	return max_cdclk_freq;
		5386	else if (IS_CHERRYVIEW(dev_priv))
		5387	return max_cdclk_freq*95/100;
		5388	else if (INTEL_INFO(dev_priv)->gen < 4)
		5389	return 2max_cdclk_freq90/100;
		5390	else
		5391	return max_cdclk_freq*90/100;
		5392	}
4560	Serge	5393
6084	serge	5394	static void intel_update_max_cdclk(struct drm_device *dev)
		5395	{
		5396	struct drm_i915_private *dev_priv = dev->dev_private;
		5397
		5398	if (IS_SKYLAKE(dev)) {
		5399	u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
		5400
		5401	if (limit == SKL_DFSM_CDCLK_LIMIT_675)
		5402	dev_priv->max_cdclk_freq = 675000;
		5403	else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
		5404	dev_priv->max_cdclk_freq = 540000;
		5405	else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
		5406	dev_priv->max_cdclk_freq = 450000;
		5407	else
		5408	dev_priv->max_cdclk_freq = 337500;
		5409	} else if (IS_BROADWELL(dev)) {
		5410	/*
		5411	* FIXME with extra cooling we can allow
		5412	* 540 MHz for ULX and 675 Mhz for ULT.
		5413	* How can we know if extra cooling is
		5414	* available? PCI ID, VTB, something else?
		5415	*/
		5416	if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
		5417	dev_priv->max_cdclk_freq = 450000;
		5418	else if (IS_BDW_ULX(dev))
		5419	dev_priv->max_cdclk_freq = 450000;
		5420	else if (IS_BDW_ULT(dev))
		5421	dev_priv->max_cdclk_freq = 540000;
		5422	else
		5423	dev_priv->max_cdclk_freq = 675000;
		5424	} else if (IS_CHERRYVIEW(dev)) {
		5425	dev_priv->max_cdclk_freq = 320000;
		5426	} else if (IS_VALLEYVIEW(dev)) {
		5427	dev_priv->max_cdclk_freq = 400000;
		5428	} else {
		5429	/* otherwise assume cdclk is fixed */
		5430	dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
		5431	}
		5432
		5433	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
		5434
		5435	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
		5436	dev_priv->max_cdclk_freq);
		5437
		5438	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
		5439	dev_priv->max_dotclk_freq);
4560	Serge	5440	}
		5441
6084	serge	5442	static void intel_update_cdclk(struct drm_device *dev)
5060	serge	5443	{
		5444	struct drm_i915_private *dev_priv = dev->dev_private;
		5445
6084	serge	5446	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5354	serge	5447	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
6084	serge	5448	dev_priv->cdclk_freq);
5060	serge	5449
		5450	/*
		5451	* Program the gmbus_freq based on the cdclk frequency.
		5452	* BSpec erroneously claims we should aim for 4MHz, but
		5453	* in fact 1MHz is the correct frequency.
		5454	*/
6084	serge	5455	if (IS_VALLEYVIEW(dev)) {
		5456	/*
		5457	* Program the gmbus_freq based on the cdclk frequency.
		5458	* BSpec erroneously claims we should aim for 4MHz, but
		5459	* in fact 1MHz is the correct frequency.
		5460	*/
		5461	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
		5462	}
		5463
		5464	if (dev_priv->max_cdclk_freq == 0)
		5465	intel_update_max_cdclk(dev);
5060	serge	5466	}
		5467
6084	serge	5468	static void broxton_set_cdclk(struct drm_device *dev, int frequency)
		5469	{
		5470	struct drm_i915_private *dev_priv = dev->dev_private;
		5471	uint32_t divider;
		5472	uint32_t ratio;
		5473	uint32_t current_freq;
		5474	int ret;
		5475
		5476	/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
		5477	switch (frequency) {
		5478	case 144000:
		5479	divider = BXT_CDCLK_CD2X_DIV_SEL_4;
		5480	ratio = BXT_DE_PLL_RATIO(60);
		5481	break;
		5482	case 288000:
		5483	divider = BXT_CDCLK_CD2X_DIV_SEL_2;
		5484	ratio = BXT_DE_PLL_RATIO(60);
		5485	break;
		5486	case 384000:
		5487	divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
		5488	ratio = BXT_DE_PLL_RATIO(60);
		5489	break;
		5490	case 576000:
		5491	divider = BXT_CDCLK_CD2X_DIV_SEL_1;
		5492	ratio = BXT_DE_PLL_RATIO(60);
		5493	break;
		5494	case 624000:
		5495	divider = BXT_CDCLK_CD2X_DIV_SEL_1;
		5496	ratio = BXT_DE_PLL_RATIO(65);
		5497	break;
		5498	case 19200:
		5499	/*
		5500	* Bypass frequency with DE PLL disabled. Init ratio, divider
		5501	* to suppress GCC warning.
		5502	*/
		5503	ratio = 0;
		5504	divider = 0;
		5505	break;
		5506	default:
		5507	DRM_ERROR("unsupported CDCLK freq %d", frequency);
		5508
		5509	return;
		5510	}
		5511
		5512	mutex_lock(&dev_priv->rps.hw_lock);
		5513	/* Inform power controller of upcoming frequency change */
		5514	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
		5515	0x80000000);
		5516	mutex_unlock(&dev_priv->rps.hw_lock);
		5517
		5518	if (ret) {
		5519	DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
		5520	ret, frequency);
		5521	return;
		5522	}
		5523
		5524	current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
		5525	/* convert from .1 fixpoint MHz with -1MHz offset to kHz */
		5526	current_freq = current_freq * 500 + 1000;
		5527
		5528	/*
		5529	* DE PLL has to be disabled when
		5530	* - setting to 19.2MHz (bypass, PLL isn't used)
		5531	* - before setting to 624MHz (PLL needs toggling)
		5532	* - before setting to any frequency from 624MHz (PLL needs toggling)
		5533	*/
		5534	if (frequency == 19200 \|\| frequency == 624000 \|\|
		5535	current_freq == 624000) {
		5536	I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
		5537	/* Timeout 200us */
		5538	if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
		5539	1))
		5540	DRM_ERROR("timout waiting for DE PLL unlock\n");
		5541	}
		5542
		5543	if (frequency != 19200) {
		5544	uint32_t val;
		5545
		5546	val = I915_READ(BXT_DE_PLL_CTL);
		5547	val &= ~BXT_DE_PLL_RATIO_MASK;
		5548	val \|= ratio;
		5549	I915_WRITE(BXT_DE_PLL_CTL, val);
		5550
		5551	I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
		5552	/* Timeout 200us */
		5553	if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
		5554	DRM_ERROR("timeout waiting for DE PLL lock\n");
		5555
		5556	val = I915_READ(CDCLK_CTL);
		5557	val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
		5558	val \|= divider;
		5559	/*
		5560	* Disable SSA Precharge when CD clock frequency < 500 MHz,
		5561	* enable otherwise.
		5562	*/
		5563	val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
		5564	if (frequency >= 500000)
		5565	val \|= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
		5566
		5567	val &= ~CDCLK_FREQ_DECIMAL_MASK;
		5568	/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
		5569	val \|= (frequency - 1000) / 500;
		5570	I915_WRITE(CDCLK_CTL, val);
		5571	}
		5572
		5573	mutex_lock(&dev_priv->rps.hw_lock);
		5574	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
		5575	DIV_ROUND_UP(frequency, 25000));
		5576	mutex_unlock(&dev_priv->rps.hw_lock);
		5577
		5578	if (ret) {
		5579	DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
		5580	ret, frequency);
		5581	return;
		5582	}
		5583
		5584	intel_update_cdclk(dev);
		5585	}
		5586
		5587	void broxton_init_cdclk(struct drm_device *dev)
		5588	{
		5589	struct drm_i915_private *dev_priv = dev->dev_private;
		5590	uint32_t val;
		5591
		5592	/*
		5593	* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
		5594	* or else the reset will hang because there is no PCH to respond.
		5595	* Move the handshake programming to initialization sequence.
		5596	* Previously was left up to BIOS.
		5597	*/
		5598	val = I915_READ(HSW_NDE_RSTWRN_OPT);
		5599	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
		5600	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
		5601
		5602	/* Enable PG1 for cdclk */
		5603	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
		5604
		5605	/* check if cd clock is enabled */
		5606	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
		5607	DRM_DEBUG_KMS("Display already initialized\n");
		5608	return;
		5609	}
		5610
		5611	/*
		5612	* FIXME:
		5613	* - The initial CDCLK needs to be read from VBT.
		5614	* Need to make this change after VBT has changes for BXT.
		5615	* - check if setting the max (or any) cdclk freq is really necessary
		5616	* here, it belongs to modeset time
		5617	*/
		5618	broxton_set_cdclk(dev, 624000);
		5619
		5620	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) \| DBUF_POWER_REQUEST);
		5621	POSTING_READ(DBUF_CTL);
		5622
		5623	udelay(10);
		5624
		5625	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
		5626	DRM_ERROR("DBuf power enable timeout!\n");
		5627	}
		5628
		5629	void broxton_uninit_cdclk(struct drm_device *dev)
		5630	{
		5631	struct drm_i915_private *dev_priv = dev->dev_private;
		5632
		5633	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
		5634	POSTING_READ(DBUF_CTL);
		5635
		5636	udelay(10);
		5637
		5638	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
		5639	DRM_ERROR("DBuf power disable timeout!\n");
		5640
		5641	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
		5642	broxton_set_cdclk(dev, 19200);
		5643
		5644	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
		5645	}
		5646
		5647	static const struct skl_cdclk_entry {
		5648	unsigned int freq;
		5649	unsigned int vco;
		5650	} skl_cdclk_frequencies[] = {
		5651	{ .freq = 308570, .vco = 8640 },
		5652	{ .freq = 337500, .vco = 8100 },
		5653	{ .freq = 432000, .vco = 8640 },
		5654	{ .freq = 450000, .vco = 8100 },
		5655	{ .freq = 540000, .vco = 8100 },
		5656	{ .freq = 617140, .vco = 8640 },
		5657	{ .freq = 675000, .vco = 8100 },
		5658	};
		5659
		5660	static unsigned int skl_cdclk_decimal(unsigned int freq)
		5661	{
		5662	return (freq - 1000) / 500;
		5663	}
		5664
		5665	static unsigned int skl_cdclk_get_vco(unsigned int freq)
		5666	{
		5667	unsigned int i;
		5668
		5669	for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
		5670	const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
		5671
		5672	if (e->freq == freq)
		5673	return e->vco;
		5674	}
		5675
		5676	return 8100;
		5677	}
		5678
		5679	static void
		5680	skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
		5681	{
		5682	unsigned int min_freq;
		5683	u32 val;
		5684
		5685	/* select the minimum CDCLK before enabling DPLL 0 */
		5686	val = I915_READ(CDCLK_CTL);
		5687	val &= ~CDCLK_FREQ_SEL_MASK \| ~CDCLK_FREQ_DECIMAL_MASK;
		5688	val \|= CDCLK_FREQ_337_308;
		5689
		5690	if (required_vco == 8640)
		5691	min_freq = 308570;
		5692	else
		5693	min_freq = 337500;
		5694
		5695	val = CDCLK_FREQ_337_308 \| skl_cdclk_decimal(min_freq);
		5696
		5697	I915_WRITE(CDCLK_CTL, val);
		5698	POSTING_READ(CDCLK_CTL);
		5699
		5700	/*
		5701	* We always enable DPLL0 with the lowest link rate possible, but still
		5702	* taking into account the VCO required to operate the eDP panel at the
		5703	* desired frequency. The usual DP link rates operate with a VCO of
		5704	* 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
		5705	* The modeset code is responsible for the selection of the exact link
		5706	* rate later on, with the constraint of choosing a frequency that
		5707	* works with required_vco.
		5708	*/
		5709	val = I915_READ(DPLL_CTRL1);
		5710
		5711	val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) \| DPLL_CTRL1_SSC(SKL_DPLL0) \|
		5712	DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
		5713	val \|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
		5714	if (required_vco == 8640)
		5715	val \|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
		5716	SKL_DPLL0);
		5717	else
		5718	val \|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
		5719	SKL_DPLL0);
		5720
		5721	I915_WRITE(DPLL_CTRL1, val);
		5722	POSTING_READ(DPLL_CTRL1);
		5723
		5724	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) \| LCPLL_PLL_ENABLE);
		5725
		5726	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
		5727	DRM_ERROR("DPLL0 not locked\n");
		5728	}
		5729
		5730	static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
		5731	{
		5732	int ret;
		5733	u32 val;
		5734
		5735	/* inform PCU we want to change CDCLK */
		5736	val = SKL_CDCLK_PREPARE_FOR_CHANGE;
		5737	mutex_lock(&dev_priv->rps.hw_lock);
		5738	ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
		5739	mutex_unlock(&dev_priv->rps.hw_lock);
		5740
		5741	return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
		5742	}
		5743
		5744	static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
		5745	{
		5746	unsigned int i;
		5747
		5748	for (i = 0; i < 15; i++) {
		5749	if (skl_cdclk_pcu_ready(dev_priv))
		5750	return true;
		5751	udelay(10);
		5752	}
		5753
		5754	return false;
		5755	}
		5756
		5757	static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
		5758	{
		5759	struct drm_device *dev = dev_priv->dev;
		5760	u32 freq_select, pcu_ack;
		5761
		5762	DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
		5763
		5764	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
		5765	DRM_ERROR("failed to inform PCU about cdclk change\n");
		5766	return;
		5767	}
		5768
		5769	/* set CDCLK_CTL */
		5770	switch(freq) {
		5771	case 450000:
		5772	case 432000:
		5773	freq_select = CDCLK_FREQ_450_432;
		5774	pcu_ack = 1;
		5775	break;
		5776	case 540000:
		5777	freq_select = CDCLK_FREQ_540;
		5778	pcu_ack = 2;
		5779	break;
		5780	case 308570:
		5781	case 337500:
		5782	default:
		5783	freq_select = CDCLK_FREQ_337_308;
		5784	pcu_ack = 0;
		5785	break;
		5786	case 617140:
		5787	case 675000:
		5788	freq_select = CDCLK_FREQ_675_617;
		5789	pcu_ack = 3;
		5790	break;
		5791	}
		5792
		5793	I915_WRITE(CDCLK_CTL, freq_select \| skl_cdclk_decimal(freq));
		5794	POSTING_READ(CDCLK_CTL);
		5795
		5796	/* inform PCU of the change */
		5797	mutex_lock(&dev_priv->rps.hw_lock);
		5798	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
		5799	mutex_unlock(&dev_priv->rps.hw_lock);
		5800
		5801	intel_update_cdclk(dev);
		5802	}
		5803
		5804	void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
		5805	{
		5806	/* disable DBUF power */
		5807	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
		5808	POSTING_READ(DBUF_CTL);
		5809
		5810	udelay(10);
		5811
		5812	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
		5813	DRM_ERROR("DBuf power disable timeout\n");
		5814
		5815	/*
		5816	* DMC assumes ownership of LCPLL and will get confused if we touch it.
		5817	*/
		5818	if (dev_priv->csr.dmc_payload) {
		5819	/* disable DPLL0 */
		5820	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
		5821	~LCPLL_PLL_ENABLE);
		5822	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
		5823	DRM_ERROR("Couldn't disable DPLL0\n");
		5824	}
		5825
		5826	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
		5827	}
		5828
		5829	void skl_init_cdclk(struct drm_i915_private *dev_priv)
		5830	{
		5831	u32 val;
		5832	unsigned int required_vco;
		5833
		5834	/* enable PCH reset handshake */
		5835	val = I915_READ(HSW_NDE_RSTWRN_OPT);
		5836	I915_WRITE(HSW_NDE_RSTWRN_OPT, val \| RESET_PCH_HANDSHAKE_ENABLE);
		5837
		5838	/* enable PG1 and Misc I/O */
		5839	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
		5840
		5841	/* DPLL0 not enabled (happens on early BIOS versions) */
		5842	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
		5843	/* enable DPLL0 */
		5844	required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
		5845	skl_dpll0_enable(dev_priv, required_vco);
		5846	}
		5847
		5848	/* set CDCLK to the frequency the BIOS chose */
		5849	skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
		5850
		5851	/* enable DBUF power */
		5852	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) \| DBUF_POWER_REQUEST);
		5853	POSTING_READ(DBUF_CTL);
		5854
		5855	udelay(10);
		5856
		5857	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
		5858	DRM_ERROR("DBuf power enable timeout\n");
		5859	}
		5860
4560	Serge	5861	/* Adjust CDclk dividers to allow high res or save power if possible */
		5862	static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
		5863	{
		5864	struct drm_i915_private *dev_priv = dev->dev_private;
		5865	u32 val, cmd;
		5866
6084	serge	5867	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
		5868	!= dev_priv->cdclk_freq);
5060	serge	5869
		5870	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4560	Serge	5871	cmd = 2;
5060	serge	5872	else if (cdclk == 266667)
4560	Serge	5873	cmd = 1;
		5874	else
		5875	cmd = 0;
		5876
		5877	mutex_lock(&dev_priv->rps.hw_lock);
		5878	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
		5879	val &= ~DSPFREQGUAR_MASK;
		5880	val \|= (cmd << DSPFREQGUAR_SHIFT);
		5881	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
		5882	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
		5883	DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
		5884	50)) {
		5885	DRM_ERROR("timed out waiting for CDclk change\n");
		5886	}
		5887	mutex_unlock(&dev_priv->rps.hw_lock);
		5888
6084	serge	5889	mutex_lock(&dev_priv->sb_lock);
		5890
5060	serge	5891	if (cdclk == 400000) {
5354	serge	5892	u32 divider;
4560	Serge	5893
5354	serge	5894	divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4560	Serge	5895
		5896	/* adjust cdclk divider */
		5897	val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6084	serge	5898	val &= ~CCK_FREQUENCY_VALUES;
4560	Serge	5899	val \|= divider;
		5900	vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5060	serge	5901
		5902	if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6084	serge	5903	CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5060	serge	5904	50))
		5905	DRM_ERROR("timed out waiting for CDclk change\n");
4560	Serge	5906	}
		5907
		5908	/* adjust self-refresh exit latency value */
		5909	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
		5910	val &= ~0x7f;
		5911
		5912	/*
		5913	* For high bandwidth configs, we set a higher latency in the bunit
		5914	* so that the core display fetch happens in time to avoid underruns.
		5915	*/
5060	serge	5916	if (cdclk == 400000)
4560	Serge	5917	val \|= 4500 / 250; /* 4.5 usec */
		5918	else
		5919	val \|= 3000 / 250; /* 3.0 usec */
		5920	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
		5921
6084	serge	5922	mutex_unlock(&dev_priv->sb_lock);
		5923
		5924	intel_update_cdclk(dev);
4560	Serge	5925	}
		5926
5354	serge	5927	static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
		5928	{
		5929	struct drm_i915_private *dev_priv = dev->dev_private;
		5930	u32 val, cmd;
		5931
6084	serge	5932	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
		5933	!= dev_priv->cdclk_freq);
5354	serge	5934
		5935	switch (cdclk) {
		5936	case 333333:
		5937	case 320000:
		5938	case 266667:
		5939	case 200000:
		5940	break;
		5941	default:
6084	serge	5942	MISSING_CASE(cdclk);
5354	serge	5943	return;
		5944	}
		5945
6084	serge	5946	/*
		5947	* Specs are full of misinformation, but testing on actual
		5948	* hardware has shown that we just need to write the desired
		5949	* CCK divider into the Punit register.
		5950	*/
		5951	cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
		5952
5354	serge	5953	mutex_lock(&dev_priv->rps.hw_lock);
		5954	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
		5955	val &= ~DSPFREQGUAR_MASK_CHV;
		5956	val \|= (cmd << DSPFREQGUAR_SHIFT_CHV);
		5957	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
		5958	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
		5959	DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
		5960	50)) {
		5961	DRM_ERROR("timed out waiting for CDclk change\n");
		5962	}
		5963	mutex_unlock(&dev_priv->rps.hw_lock);
		5964
6084	serge	5965	intel_update_cdclk(dev);
5354	serge	5966	}
		5967
4560	Serge	5968	static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
		5969	int max_pixclk)
		5970	{
5354	serge	5971	int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6084	serge	5972	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
4560	Serge	5973
		5974	/*
		5975	* Really only a few cases to deal with, as only 4 CDclks are supported:
		5976	* 200MHz
		5977	* 267MHz
5060	serge	5978	* 320/333MHz (depends on HPLL freq)
6084	serge	5979	* 400MHz (VLV only)
		5980	* So we check to see whether we're above 90% (VLV) or 95% (CHV)
		5981	* of the lower bin and adjust if needed.
5060	serge	5982	*
		5983	* We seem to get an unstable or solid color picture at 200MHz.
		5984	* Not sure what's wrong. For now use 200MHz only when all pipes
		5985	* are off.
4560	Serge	5986	*/
6084	serge	5987	if (!IS_CHERRYVIEW(dev_priv) &&
		5988	max_pixclk > freq_320*limit/100)
5060	serge	5989	return 400000;
6084	serge	5990	else if (max_pixclk > 266667*limit/100)
5060	serge	5991	return freq_320;
		5992	else if (max_pixclk > 0)
		5993	return 266667;
		5994	else
		5995	return 200000;
4560	Serge	5996	}
		5997
6084	serge	5998	static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
		5999	int max_pixclk)
4560	Serge	6000	{
6084	serge	6001	/*
		6002	* FIXME:
		6003	* - remove the guardband, it's not needed on BXT
		6004	* - set 19.2MHz bypass frequency if there are no active pipes
		6005	*/
		6006	if (max_pixclk > 576000*9/10)
		6007	return 624000;
		6008	else if (max_pixclk > 384000*9/10)
		6009	return 576000;
		6010	else if (max_pixclk > 288000*9/10)
		6011	return 384000;
		6012	else if (max_pixclk > 144000*9/10)
		6013	return 288000;
		6014	else
		6015	return 144000;
		6016	}
		6017
		6018	/* Compute the max pixel clock for new configuration. Uses atomic state if
		6019	* that's non-NULL, look at current state otherwise. */
		6020	static int intel_mode_max_pixclk(struct drm_device *dev,
		6021	struct drm_atomic_state *state)
		6022	{
4560	Serge	6023	struct intel_crtc *intel_crtc;
6084	serge	6024	struct intel_crtc_state *crtc_state;
4560	Serge	6025	int max_pixclk = 0;
		6026
5060	serge	6027	for_each_intel_crtc(dev, intel_crtc) {
6084	serge	6028	crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
		6029	if (IS_ERR(crtc_state))
		6030	return PTR_ERR(crtc_state);
		6031
		6032	if (!crtc_state->base.enable)
		6033	continue;
		6034
		6035	max_pixclk = max(max_pixclk,
		6036	crtc_state->base.adjusted_mode.crtc_clock);
4560	Serge	6037	}
		6038
		6039	return max_pixclk;
		6040	}
		6041
6084	serge	6042	static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
4560	Serge	6043	{
6084	serge	6044	struct drm_device *dev = state->dev;
4560	Serge	6045	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	6046	int max_pixclk = intel_mode_max_pixclk(dev, state);
4560	Serge	6047
6084	serge	6048	if (max_pixclk < 0)
		6049	return max_pixclk;
4560	Serge	6050
6084	serge	6051	to_intel_atomic_state(state)->cdclk =
		6052	valleyview_calc_cdclk(dev_priv, max_pixclk);
		6053
		6054	return 0;
4560	Serge	6055	}
		6056
6084	serge	6057	static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
4560	Serge	6058	{
6084	serge	6059	struct drm_device *dev = state->dev;
4560	Serge	6060	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	6061	int max_pixclk = intel_mode_max_pixclk(dev, state);
4560	Serge	6062
6084	serge	6063	if (max_pixclk < 0)
		6064	return max_pixclk;
5354	serge	6065
6084	serge	6066	to_intel_atomic_state(state)->cdclk =
		6067	broxton_calc_cdclk(dev_priv, max_pixclk);
		6068
		6069	return 0;
		6070	}
		6071
		6072	static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
		6073	{
		6074	unsigned int credits, default_credits;
		6075
		6076	if (IS_CHERRYVIEW(dev_priv))
		6077	default_credits = PFI_CREDIT(12);
		6078	else
		6079	default_credits = PFI_CREDIT(8);
		6080
		6081	if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
		6082	/* CHV suggested value is 31 or 63 */
		6083	if (IS_CHERRYVIEW(dev_priv))
		6084	credits = PFI_CREDIT_63;
5354	serge	6085	else
6084	serge	6086	credits = PFI_CREDIT(15);
		6087	} else {
		6088	credits = default_credits;
		6089	}
		6090
		6091	/*
		6092	* WA - write default credits before re-programming
		6093	* FIXME: should we also set the resend bit here?
		6094	*/
		6095	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE \|
		6096	default_credits);
		6097
		6098	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE \|
		6099	credits \| PFI_CREDIT_RESEND);
		6100
		6101	/*
		6102	* FIXME is this guaranteed to clear
		6103	* immediately or should we poll for it?
		6104	*/
		6105	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
		6106	}
		6107
		6108	static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
		6109	{
		6110	struct drm_device *dev = old_state->dev;
		6111	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
		6112	struct drm_i915_private *dev_priv = dev->dev_private;
		6113
		6114	/*
		6115	* FIXME: We can end up here with all power domains off, yet
		6116	* with a CDCLK frequency other than the minimum. To account
		6117	* for this take the PIPE-A power domain, which covers the HW
		6118	* blocks needed for the following programming. This can be
		6119	* removed once it's guaranteed that we get here either with
		6120	* the minimum CDCLK set, or the required power domains
		6121	* enabled.
		6122	*/
		6123	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
		6124
		6125	if (IS_CHERRYVIEW(dev))
		6126	cherryview_set_cdclk(dev, req_cdclk);
		6127	else
4560	Serge	6128	valleyview_set_cdclk(dev, req_cdclk);
5354	serge	6129
6084	serge	6130	vlv_program_pfi_credits(dev_priv);
		6131
		6132	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4560	Serge	6133	}
		6134
4104	Serge	6135	static void valleyview_crtc_enable(struct drm_crtc *crtc)
		6136	{
		6137	struct drm_device *dev = crtc->dev;
5354	serge	6138	struct drm_i915_private *dev_priv = to_i915(dev);
4104	Serge	6139	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6140	struct intel_encoder *encoder;
		6141	int pipe = intel_crtc->pipe;
4560	Serge	6142	bool is_dsi;
4104	Serge	6143
6084	serge	6144	if (WARN_ON(intel_crtc->active))
4104	Serge	6145	return;
		6146
5354	serge	6147	is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5060	serge	6148
6084	serge	6149	if (intel_crtc->config->has_dp_encoder)
		6150	intel_dp_set_m_n(intel_crtc, M1_N1);
5060	serge	6151
		6152	intel_set_pipe_timings(intel_crtc);
		6153
5354	serge	6154	if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
		6155	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	6156
5354	serge	6157	I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
		6158	I915_WRITE(CHV_CANVAS(pipe), 0);
		6159	}
		6160
5060	serge	6161	i9xx_set_pipeconf(intel_crtc);
		6162
4104	Serge	6163	intel_crtc->active = true;
		6164
5354	serge	6165	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5060	serge	6166
4104	Serge	6167	for_each_encoder_on_crtc(dev, crtc, encoder)
		6168	if (encoder->pre_pll_enable)
		6169	encoder->pre_pll_enable(encoder);
		6170
5060	serge	6171	if (!is_dsi) {
6084	serge	6172	if (IS_CHERRYVIEW(dev)) {
		6173	chv_prepare_pll(intel_crtc, intel_crtc->config);
		6174	chv_enable_pll(intel_crtc, intel_crtc->config);
		6175	} else {
		6176	vlv_prepare_pll(intel_crtc, intel_crtc->config);
		6177	vlv_enable_pll(intel_crtc, intel_crtc->config);
		6178	}
5060	serge	6179	}
4104	Serge	6180
		6181	for_each_encoder_on_crtc(dev, crtc, encoder)
		6182	if (encoder->pre_enable)
		6183	encoder->pre_enable(encoder);
		6184
		6185	i9xx_pfit_enable(intel_crtc);
		6186
		6187	intel_crtc_load_lut(crtc);
		6188
5060	serge	6189	intel_enable_pipe(intel_crtc);
4104	Serge	6190
5354	serge	6191	assert_vblank_disabled(crtc);
		6192	drm_crtc_vblank_on(crtc);
		6193
6084	serge	6194	for_each_encoder_on_crtc(dev, crtc, encoder)
		6195	encoder->enable(encoder);
4104	Serge	6196	}
		6197
5060	serge	6198	static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
		6199	{
		6200	struct drm_device *dev = crtc->base.dev;
		6201	struct drm_i915_private *dev_priv = dev->dev_private;
		6202
6084	serge	6203	I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
		6204	I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5060	serge	6205	}
		6206
2327	Serge	6207	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		6208	{
6084	serge	6209	struct drm_device *dev = crtc->dev;
5354	serge	6210	struct drm_i915_private *dev_priv = to_i915(dev);
6084	serge	6211	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	6212	struct intel_encoder *encoder;
6084	serge	6213	int pipe = intel_crtc->pipe;
2327	Serge	6214
6084	serge	6215	if (WARN_ON(intel_crtc->active))
		6216	return;
3031	serge	6217
5060	serge	6218	i9xx_set_pll_dividers(intel_crtc);
		6219
6084	serge	6220	if (intel_crtc->config->has_dp_encoder)
		6221	intel_dp_set_m_n(intel_crtc, M1_N1);
5060	serge	6222
		6223	intel_set_pipe_timings(intel_crtc);
		6224
		6225	i9xx_set_pipeconf(intel_crtc);
		6226
6084	serge	6227	intel_crtc->active = true;
2327	Serge	6228
5060	serge	6229	if (!IS_GEN2(dev))
5354	serge	6230	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5060	serge	6231
3480	Serge	6232	for_each_encoder_on_crtc(dev, crtc, encoder)
		6233	if (encoder->pre_enable)
		6234	encoder->pre_enable(encoder);
		6235
4104	Serge	6236	i9xx_enable_pll(intel_crtc);
		6237
		6238	i9xx_pfit_enable(intel_crtc);
		6239
		6240	intel_crtc_load_lut(crtc);
		6241
4560	Serge	6242	intel_update_watermarks(crtc);
5060	serge	6243	intel_enable_pipe(intel_crtc);
2327	Serge	6244
5354	serge	6245	assert_vblank_disabled(crtc);
		6246	drm_crtc_vblank_on(crtc);
		6247
6084	serge	6248	for_each_encoder_on_crtc(dev, crtc, encoder)
		6249	encoder->enable(encoder);
2327	Serge	6250	}
		6251
3746	Serge	6252	static void i9xx_pfit_disable(struct intel_crtc *crtc)
		6253	{
		6254	struct drm_device *dev = crtc->base.dev;
		6255	struct drm_i915_private *dev_priv = dev->dev_private;
		6256
6084	serge	6257	if (!crtc->config->gmch_pfit.control)
4104	Serge	6258	return;
		6259
3746	Serge	6260	assert_pipe_disabled(dev_priv, crtc->pipe);
		6261
4104	Serge	6262	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
		6263	I915_READ(PFIT_CONTROL));
6084	serge	6264	I915_WRITE(PFIT_CONTROL, 0);
3746	Serge	6265	}
		6266
2327	Serge	6267	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		6268	{
6084	serge	6269	struct drm_device *dev = crtc->dev;
		6270	struct drm_i915_private *dev_priv = dev->dev_private;
		6271	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	6272	struct intel_encoder *encoder;
6084	serge	6273	int pipe = intel_crtc->pipe;
2327	Serge	6274
5060	serge	6275	/*
		6276	* On gen2 planes are double buffered but the pipe isn't, so we must
		6277	* wait for planes to fully turn off before disabling the pipe.
		6278	* We also need to wait on all gmch platforms because of the
		6279	* self-refresh mode constraint explained above.
		6280	*/
6084	serge	6281	intel_wait_for_vblank(dev, pipe);
2327	Serge	6282
6084	serge	6283	for_each_encoder_on_crtc(dev, crtc, encoder)
		6284	encoder->disable(encoder);
		6285
5354	serge	6286	drm_crtc_vblank_off(crtc);
		6287	assert_vblank_disabled(crtc);
3480	Serge	6288
5354	serge	6289	intel_disable_pipe(intel_crtc);
		6290
3746	Serge	6291	i9xx_pfit_disable(intel_crtc);
3480	Serge	6292
4104	Serge	6293	for_each_encoder_on_crtc(dev, crtc, encoder)
		6294	if (encoder->post_disable)
		6295	encoder->post_disable(encoder);
2327	Serge	6296
5354	serge	6297	if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5060	serge	6298	if (IS_CHERRYVIEW(dev))
		6299	chv_disable_pll(dev_priv, pipe);
		6300	else if (IS_VALLEYVIEW(dev))
6084	serge	6301	vlv_disable_pll(dev_priv, pipe);
5060	serge	6302	else
5354	serge	6303	i9xx_disable_pll(intel_crtc);
5060	serge	6304	}
4104	Serge	6305
6084	serge	6306	for_each_encoder_on_crtc(dev, crtc, encoder)
		6307	if (encoder->post_pll_disable)
		6308	encoder->post_pll_disable(encoder);
		6309
5060	serge	6310	if (!IS_GEN2(dev))
5354	serge	6311	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2327	Serge	6312	}
		6313
6084	serge	6314	static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
2327	Serge	6315	{
5060	serge	6316	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084	serge	6317	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5060	serge	6318	enum intel_display_power_domain domain;
		6319	unsigned long domains;
		6320
6084	serge	6321	if (!intel_crtc->active)
		6322	return;
5060	serge	6323
6084	serge	6324	if (to_intel_plane_state(crtc->primary->state)->visible) {
6320	serge	6325	intel_crtc_wait_for_pending_flips(crtc);
6084	serge	6326	intel_pre_disable_primary(crtc);
5060	serge	6327
6084	serge	6328	intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
		6329	to_intel_plane_state(crtc->primary->state)->visible = false;
5060	serge	6330	}
6084	serge	6331
		6332	dev_priv->display.crtc_disable(crtc);
		6333	intel_crtc->active = false;
		6334	intel_update_watermarks(crtc);
		6335	intel_disable_shared_dpll(intel_crtc);
		6336
		6337	domains = intel_crtc->enabled_power_domains;
		6338	for_each_power_domain(domain, domains)
		6339	intel_display_power_put(dev_priv, domain);
		6340	intel_crtc->enabled_power_domains = 0;
2330	Serge	6341	}
2327	Serge	6342
6084	serge	6343	/*
		6344	* turn all crtc's off, but do not adjust state
		6345	* This has to be paired with a call to intel_modeset_setup_hw_state.
3031	serge	6346	*/
6084	serge	6347	int intel_display_suspend(struct drm_device *dev)
3031	serge	6348	{
6084	serge	6349	struct drm_mode_config *config = &dev->mode_config;
		6350	struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
		6351	struct drm_atomic_state *state;
		6352	struct drm_crtc *crtc;
		6353	unsigned crtc_mask = 0;
		6354	int ret = 0;
3031	serge	6355
6084	serge	6356	if (WARN_ON(!ctx))
		6357	return 0;
3031	serge	6358
6084	serge	6359	lockdep_assert_held(&ctx->ww_ctx);
		6360	state = drm_atomic_state_alloc(dev);
		6361	if (WARN_ON(!state))
		6362	return -ENOMEM;
3031	serge	6363
6084	serge	6364	state->acquire_ctx = ctx;
		6365	state->allow_modeset = true;
2327	Serge	6366
6084	serge	6367	for_each_crtc(dev, crtc) {
		6368	struct drm_crtc_state *crtc_state =
		6369	drm_atomic_get_crtc_state(state, crtc);
2327	Serge	6370
6084	serge	6371	ret = PTR_ERR_OR_ZERO(crtc_state);
		6372	if (ret)
		6373	goto free;
3031	serge	6374
6084	serge	6375	if (!crtc_state->active)
		6376	continue;
		6377
		6378	crtc_state->active = false;
		6379	crtc_mask \|= 1 << drm_crtc_index(crtc);
4280	Serge	6380	}
3031	serge	6381
6084	serge	6382	if (crtc_mask) {
		6383	ret = drm_atomic_commit(state);
3031	serge	6384
6084	serge	6385	if (!ret) {
		6386	for_each_crtc(dev, crtc)
		6387	if (crtc_mask & (1 << drm_crtc_index(crtc)))
		6388	crtc->state->active = true;
3031	serge	6389
6084	serge	6390	return ret;
		6391	}
2330	Serge	6392	}
6084	serge	6393
		6394	free:
		6395	if (ret)
		6396	DRM_ERROR("Suspending crtc's failed with %i\n", ret);
		6397	drm_atomic_state_free(state);
		6398	return ret;
2330	Serge	6399	}
2327	Serge	6400
3031	serge	6401	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	6402	{
3031	serge	6403	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		6404
		6405	drm_encoder_cleanup(encoder);
		6406	kfree(intel_encoder);
2330	Serge	6407	}
2327	Serge	6408
3031	serge	6409	/* Cross check the actual hw state with our own modeset state tracking (and it's
		6410	* internal consistency). */
		6411	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	6412	{
6084	serge	6413	struct drm_crtc *crtc = connector->base.state->crtc;
		6414
		6415	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		6416	connector->base.base.id,
		6417	connector->base.name);
		6418
3031	serge	6419	if (connector->get_hw_state(connector)) {
		6420	struct intel_encoder *encoder = connector->encoder;
6084	serge	6421	struct drm_connector_state *conn_state = connector->base.state;
3031	serge	6422
6084	serge	6423	I915_STATE_WARN(!crtc,
		6424	"connector enabled without attached crtc\n");
3031	serge	6425
6084	serge	6426	if (!crtc)
5060	serge	6427	return;
		6428
6084	serge	6429	I915_STATE_WARN(!crtc->state->active,
		6430	"connector is active, but attached crtc isn't\n");
5060	serge	6431
6084	serge	6432	if (!encoder \|\| encoder->type == INTEL_OUTPUT_DP_MST)
3031	serge	6433	return;
		6434
6084	serge	6435	I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
		6436	"atomic encoder doesn't match attached encoder\n");
3031	serge	6437
6084	serge	6438	I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
		6439	"attached encoder crtc differs from connector crtc\n");
		6440	} else {
		6441	I915_STATE_WARN(crtc && crtc->state->active,
		6442	"attached crtc is active, but connector isn't\n");
		6443	I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
		6444	"best encoder set without crtc!\n");
3031	serge	6445	}
2330	Serge	6446	}
2327	Serge	6447
6084	serge	6448	int intel_connector_init(struct intel_connector *connector)
2330	Serge	6449	{
6084	serge	6450	struct drm_connector_state *connector_state;
2342	Serge	6451
6084	serge	6452	connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
		6453	if (!connector_state)
		6454	return -ENOMEM;
3031	serge	6455
6084	serge	6456	connector->base.state = connector_state;
		6457	return 0;
		6458	}
3031	serge	6459
6084	serge	6460	struct intel_connector *intel_connector_alloc(void)
		6461	{
		6462	struct intel_connector *connector;
3031	serge	6463
6084	serge	6464	connector = kzalloc(sizeof *connector, GFP_KERNEL);
		6465	if (!connector)
		6466	return NULL;
		6467
		6468	if (intel_connector_init(connector) < 0) {
		6469	kfree(connector);
		6470	return NULL;
		6471	}
		6472
		6473	return connector;
2330	Serge	6474	}
2327	Serge	6475
3031	serge	6476	/* Simple connector->get_hw_state implementation for encoders that support only
		6477	* one connector and no cloning and hence the encoder state determines the state
		6478	* of the connector. */
		6479	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	6480	{
3031	serge	6481	enum pipe pipe = 0;
		6482	struct intel_encoder *encoder = connector->encoder;
2330	Serge	6483
3031	serge	6484	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	6485	}
		6486
6084	serge	6487	static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
4104	Serge	6488	{
6084	serge	6489	if (crtc_state->base.enable && crtc_state->has_pch_encoder)
		6490	return crtc_state->fdi_lanes;
4104	Serge	6491
6084	serge	6492	return 0;
		6493	}
		6494
		6495	static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
		6496	struct intel_crtc_state *pipe_config)
		6497	{
		6498	struct drm_atomic_state *state = pipe_config->base.state;
		6499	struct intel_crtc *other_crtc;
		6500	struct intel_crtc_state *other_crtc_state;
		6501
4104	Serge	6502	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
		6503	pipe_name(pipe), pipe_config->fdi_lanes);
		6504	if (pipe_config->fdi_lanes > 4) {
		6505	DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
		6506	pipe_name(pipe), pipe_config->fdi_lanes);
6084	serge	6507	return -EINVAL;
4104	Serge	6508	}
		6509
4560	Serge	6510	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
4104	Serge	6511	if (pipe_config->fdi_lanes > 2) {
		6512	DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
		6513	pipe_config->fdi_lanes);
6084	serge	6514	return -EINVAL;
4104	Serge	6515	} else {
6084	serge	6516	return 0;
4104	Serge	6517	}
		6518	}
		6519
		6520	if (INTEL_INFO(dev)->num_pipes == 2)
6084	serge	6521	return 0;
4104	Serge	6522
		6523	/* Ivybridge 3 pipe is really complicated */
		6524	switch (pipe) {
		6525	case PIPE_A:
6084	serge	6526	return 0;
4104	Serge	6527	case PIPE_B:
6084	serge	6528	if (pipe_config->fdi_lanes <= 2)
		6529	return 0;
		6530
		6531	other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
		6532	other_crtc_state =
		6533	intel_atomic_get_crtc_state(state, other_crtc);
		6534	if (IS_ERR(other_crtc_state))
		6535	return PTR_ERR(other_crtc_state);
		6536
		6537	if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
4104	Serge	6538	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		6539	pipe_name(pipe), pipe_config->fdi_lanes);
6084	serge	6540	return -EINVAL;
4104	Serge	6541	}
6084	serge	6542	return 0;
4104	Serge	6543	case PIPE_C:
6084	serge	6544	if (pipe_config->fdi_lanes > 2) {
		6545	DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
		6546	pipe_name(pipe), pipe_config->fdi_lanes);
		6547	return -EINVAL;
		6548	}
		6549
		6550	other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
		6551	other_crtc_state =
		6552	intel_atomic_get_crtc_state(state, other_crtc);
		6553	if (IS_ERR(other_crtc_state))
		6554	return PTR_ERR(other_crtc_state);
		6555
		6556	if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
4104	Serge	6557	DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6084	serge	6558	return -EINVAL;
4104	Serge	6559	}
6084	serge	6560	return 0;
4104	Serge	6561	default:
		6562	BUG();
		6563	}
		6564	}
		6565
		6566	#define RETRY 1
		6567	static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6084	serge	6568	struct intel_crtc_state *pipe_config)
2330	Serge	6569	{
4104	Serge	6570	struct drm_device *dev = intel_crtc->base.dev;
6084	serge	6571	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
		6572	int lane, link_bw, fdi_dotclock, ret;
		6573	bool needs_recompute = false;
2330	Serge	6574
4104	Serge	6575	retry:
		6576	/* FDI is a binary signal running at ~2.7GHz, encoding
		6577	* each output octet as 10 bits. The actual frequency
		6578	* is stored as a divider into a 100MHz clock, and the
		6579	* mode pixel clock is stored in units of 1KHz.
		6580	* Hence the bw of each lane in terms of the mode signal
		6581	* is:
		6582	*/
		6583	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		6584
4560	Serge	6585	fdi_dotclock = adjusted_mode->crtc_clock;
4104	Serge	6586
		6587	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
		6588	pipe_config->pipe_bpp);
		6589
		6590	pipe_config->fdi_lanes = lane;
		6591
		6592	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
		6593	link_bw, &pipe_config->fdi_m_n);
		6594
6084	serge	6595	ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
		6596	intel_crtc->pipe, pipe_config);
		6597	if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
4104	Serge	6598	pipe_config->pipe_bpp -= 2*3;
		6599	DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
		6600	pipe_config->pipe_bpp);
		6601	needs_recompute = true;
		6602	pipe_config->bw_constrained = true;
		6603
		6604	goto retry;
		6605	}
		6606
		6607	if (needs_recompute)
		6608	return RETRY;
		6609
6084	serge	6610	return ret;
4104	Serge	6611	}
		6612
6084	serge	6613	static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
		6614	struct intel_crtc_state *pipe_config)
		6615	{
		6616	if (pipe_config->pipe_bpp > 24)
		6617	return false;
		6618
		6619	/* HSW can handle pixel rate up to cdclk? */
		6620	if (IS_HASWELL(dev_priv->dev))
		6621	return true;
		6622
		6623	/*
		6624	* We compare against max which means we must take
		6625	* the increased cdclk requirement into account when
		6626	* calculating the new cdclk.
		6627	*
		6628	* Should measure whether using a lower cdclk w/o IPS
		6629	*/
		6630	return ilk_pipe_pixel_rate(pipe_config) <=
		6631	dev_priv->max_cdclk_freq * 95 / 100;
		6632	}
		6633
4104	Serge	6634	static void hsw_compute_ips_config(struct intel_crtc *crtc,
6084	serge	6635	struct intel_crtc_state *pipe_config)
4104	Serge	6636	{
6084	serge	6637	struct drm_device *dev = crtc->base.dev;
		6638	struct drm_i915_private *dev_priv = dev->dev_private;
		6639
5060	serge	6640	pipe_config->ips_enabled = i915.enable_ips &&
6084	serge	6641	hsw_crtc_supports_ips(crtc) &&
		6642	pipe_config_supports_ips(dev_priv, pipe_config);
4104	Serge	6643	}
		6644
		6645	static int intel_crtc_compute_config(struct intel_crtc *crtc,
6084	serge	6646	struct intel_crtc_state *pipe_config)
4104	Serge	6647	{
		6648	struct drm_device *dev = crtc->base.dev;
5354	serge	6649	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	6650	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
4104	Serge	6651
4560	Serge	6652	/* FIXME should check pixel clock limits on all platforms */
		6653	if (INTEL_INFO(dev)->gen < 4) {
6084	serge	6654	int clock_limit = dev_priv->max_cdclk_freq;
4560	Serge	6655
		6656	/*
		6657	* Enable pixel doubling when the dot clock
		6658	* is > 90% of the (display) core speed.
		6659	*
		6660	* GDG double wide on either pipe,
		6661	* otherwise pipe A only.
		6662	*/
		6663	if ((crtc->pipe == PIPE_A \|\| IS_I915G(dev)) &&
		6664	adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
		6665	clock_limit *= 2;
		6666	pipe_config->double_wide = true;
		6667	}
		6668
		6669	if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4104	Serge	6670	return -EINVAL;
2330	Serge	6671	}
		6672
4560	Serge	6673	/*
		6674	* Pipe horizontal size must be even in:
		6675	* - DVO ganged mode
		6676	* - LVDS dual channel mode
		6677	* - Double wide pipe
		6678	*/
6084	serge	6679	if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
4560	Serge	6680	intel_is_dual_link_lvds(dev)) \|\| pipe_config->double_wide)
		6681	pipe_config->pipe_src_w &= ~1;
		6682
4104	Serge	6683	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
		6684	* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
3031	serge	6685	*/
		6686	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
6084	serge	6687	adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
4104	Serge	6688	return -EINVAL;
3031	serge	6689
4104	Serge	6690	if (HAS_IPS(dev))
		6691	hsw_compute_ips_config(crtc, pipe_config);
		6692
		6693	if (pipe_config->has_pch_encoder)
		6694	return ironlake_fdi_compute_config(crtc, pipe_config);
		6695
		6696	return 0;
2330	Serge	6697	}
		6698
6084	serge	6699	static int skylake_get_display_clock_speed(struct drm_device *dev)
3031	serge	6700	{
6084	serge	6701	struct drm_i915_private *dev_priv = to_i915(dev);
		6702	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
		6703	uint32_t cdctl = I915_READ(CDCLK_CTL);
		6704	uint32_t linkrate;
5060	serge	6705
6084	serge	6706	if (!(lcpll1 & LCPLL_PLL_ENABLE))
		6707	return 24000; /* 24MHz is the cd freq with NSSC ref */
5354	serge	6708
6084	serge	6709	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
		6710	return 540000;
5354	serge	6711
6084	serge	6712	linkrate = (I915_READ(DPLL_CTRL1) &
		6713	DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
5060	serge	6714
6084	serge	6715	if (linkrate == DPLL_CTRL1_LINK_RATE_2160 \|\|
		6716	linkrate == DPLL_CTRL1_LINK_RATE_1080) {
		6717	/* vco 8640 */
		6718	switch (cdctl & CDCLK_FREQ_SEL_MASK) {
		6719	case CDCLK_FREQ_450_432:
		6720	return 432000;
		6721	case CDCLK_FREQ_337_308:
		6722	return 308570;
		6723	case CDCLK_FREQ_675_617:
		6724	return 617140;
		6725	default:
		6726	WARN(1, "Unknown cd freq selection\n");
		6727	}
		6728	} else {
		6729	/* vco 8100 */
		6730	switch (cdctl & CDCLK_FREQ_SEL_MASK) {
		6731	case CDCLK_FREQ_450_432:
		6732	return 450000;
		6733	case CDCLK_FREQ_337_308:
		6734	return 337500;
		6735	case CDCLK_FREQ_675_617:
		6736	return 675000;
		6737	default:
		6738	WARN(1, "Unknown cd freq selection\n");
		6739	}
		6740	}
5060	serge	6741
6084	serge	6742	/* error case, do as if DPLL0 isn't enabled */
		6743	return 24000;
		6744	}
5060	serge	6745
6084	serge	6746	static int broxton_get_display_clock_speed(struct drm_device *dev)
		6747	{
		6748	struct drm_i915_private *dev_priv = to_i915(dev);
		6749	uint32_t cdctl = I915_READ(CDCLK_CTL);
		6750	uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
		6751	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
		6752	int cdclk;
		6753
		6754	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
		6755	return 19200;
		6756
		6757	cdclk = 19200 * pll_ratio / 2;
		6758
		6759	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
		6760	case BXT_CDCLK_CD2X_DIV_SEL_1:
		6761	return cdclk; /* 576MHz or 624MHz */
		6762	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
		6763	return cdclk * 2 / 3; /* 384MHz */
		6764	case BXT_CDCLK_CD2X_DIV_SEL_2:
		6765	return cdclk / 2; /* 288MHz */
		6766	case BXT_CDCLK_CD2X_DIV_SEL_4:
		6767	return cdclk / 4; /* 144MHz */
		6768	}
		6769
		6770	/* error case, do as if DE PLL isn't enabled */
		6771	return 19200;
3031	serge	6772	}
		6773
6084	serge	6774	static int broadwell_get_display_clock_speed(struct drm_device *dev)
		6775	{
		6776	struct drm_i915_private *dev_priv = dev->dev_private;
		6777	uint32_t lcpll = I915_READ(LCPLL_CTL);
		6778	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
		6779
		6780	if (lcpll & LCPLL_CD_SOURCE_FCLK)
		6781	return 800000;
		6782	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
		6783	return 450000;
		6784	else if (freq == LCPLL_CLK_FREQ_450)
		6785	return 450000;
		6786	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
		6787	return 540000;
		6788	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
		6789	return 337500;
		6790	else
		6791	return 675000;
		6792	}
		6793
		6794	static int haswell_get_display_clock_speed(struct drm_device *dev)
		6795	{
		6796	struct drm_i915_private *dev_priv = dev->dev_private;
		6797	uint32_t lcpll = I915_READ(LCPLL_CTL);
		6798	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
		6799
		6800	if (lcpll & LCPLL_CD_SOURCE_FCLK)
		6801	return 800000;
		6802	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
		6803	return 450000;
		6804	else if (freq == LCPLL_CLK_FREQ_450)
		6805	return 450000;
		6806	else if (IS_HSW_ULT(dev))
		6807	return 337500;
		6808	else
		6809	return 540000;
		6810	}
		6811
		6812	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		6813	{
		6814	return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
		6815	CCK_DISPLAY_CLOCK_CONTROL);
		6816	}
		6817
		6818	static int ilk_get_display_clock_speed(struct drm_device *dev)
		6819	{
		6820	return 450000;
		6821	}
		6822
2327	Serge	6823	static int i945_get_display_clock_speed(struct drm_device *dev)
		6824	{
		6825	return 400000;
		6826	}
		6827
		6828	static int i915_get_display_clock_speed(struct drm_device *dev)
		6829	{
6084	serge	6830	return 333333;
2327	Serge	6831	}
		6832
		6833	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		6834	{
		6835	return 200000;
		6836	}
		6837
4104	Serge	6838	static int pnv_get_display_clock_speed(struct drm_device *dev)
		6839	{
		6840	u16 gcfgc = 0;
		6841
		6842	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		6843
		6844	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		6845	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6084	serge	6846	return 266667;
4104	Serge	6847	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6084	serge	6848	return 333333;
4104	Serge	6849	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6084	serge	6850	return 444444;
4104	Serge	6851	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
		6852	return 200000;
		6853	default:
		6854	DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
		6855	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6084	serge	6856	return 133333;
4104	Serge	6857	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6084	serge	6858	return 166667;
4104	Serge	6859	}
		6860	}
		6861
2327	Serge	6862	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		6863	{
		6864	u16 gcfgc = 0;
		6865
		6866	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		6867
		6868	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6084	serge	6869	return 133333;
2327	Serge	6870	else {
		6871	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		6872	case GC_DISPLAY_CLOCK_333_MHZ:
6084	serge	6873	return 333333;
2327	Serge	6874	default:
		6875	case GC_DISPLAY_CLOCK_190_200_MHZ:
		6876	return 190000;
		6877	}
		6878	}
		6879	}
		6880
		6881	static int i865_get_display_clock_speed(struct drm_device *dev)
		6882	{
6084	serge	6883	return 266667;
2327	Serge	6884	}
		6885
6084	serge	6886	static int i85x_get_display_clock_speed(struct drm_device *dev)
2327	Serge	6887	{
		6888	u16 hpllcc = 0;
6084	serge	6889
		6890	/*
		6891	* 852GM/852GMV only supports 133 MHz and the HPLLCC
		6892	* encoding is different :(
		6893	* FIXME is this the right way to detect 852GM/852GMV?
		6894	*/
		6895	if (dev->pdev->revision == 0x1)
		6896	return 133333;
		6897
		6898	// pci_bus_read_config_word(dev->pdev->bus,
		6899	// PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
		6900
2327	Serge	6901	/* Assume that the hardware is in the high speed state. This
		6902	* should be the default.
		6903	*/
		6904	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		6905	case GC_CLOCK_133_200:
6084	serge	6906	case GC_CLOCK_133_200_2:
2327	Serge	6907	case GC_CLOCK_100_200:
		6908	return 200000;
		6909	case GC_CLOCK_166_250:
		6910	return 250000;
		6911	case GC_CLOCK_100_133:
6084	serge	6912	return 133333;
		6913	case GC_CLOCK_133_266:
		6914	case GC_CLOCK_133_266_2:
		6915	case GC_CLOCK_166_266:
		6916	return 266667;
2327	Serge	6917	}
		6918
		6919	/* Shouldn't happen */
		6920	return 0;
		6921	}
		6922
		6923	static int i830_get_display_clock_speed(struct drm_device *dev)
		6924	{
6084	serge	6925	return 133333;
2327	Serge	6926	}
		6927
6084	serge	6928	static unsigned int intel_hpll_vco(struct drm_device *dev)
		6929	{
		6930	struct drm_i915_private *dev_priv = dev->dev_private;
		6931	static const unsigned int blb_vco[8] = {
		6932	[0] = 3200000,
		6933	[1] = 4000000,
		6934	[2] = 5333333,
		6935	[3] = 4800000,
		6936	[4] = 6400000,
		6937	};
		6938	static const unsigned int pnv_vco[8] = {
		6939	[0] = 3200000,
		6940	[1] = 4000000,
		6941	[2] = 5333333,
		6942	[3] = 4800000,
		6943	[4] = 2666667,
		6944	};
		6945	static const unsigned int cl_vco[8] = {
		6946	[0] = 3200000,
		6947	[1] = 4000000,
		6948	[2] = 5333333,
		6949	[3] = 6400000,
		6950	[4] = 3333333,
		6951	[5] = 3566667,
		6952	[6] = 4266667,
		6953	};
		6954	static const unsigned int elk_vco[8] = {
		6955	[0] = 3200000,
		6956	[1] = 4000000,
		6957	[2] = 5333333,
		6958	[3] = 4800000,
		6959	};
		6960	static const unsigned int ctg_vco[8] = {
		6961	[0] = 3200000,
		6962	[1] = 4000000,
		6963	[2] = 5333333,
		6964	[3] = 6400000,
		6965	[4] = 2666667,
		6966	[5] = 4266667,
		6967	};
		6968	const unsigned int *vco_table;
		6969	unsigned int vco;
		6970	uint8_t tmp = 0;
		6971
		6972	/* FIXME other chipsets? */
		6973	if (IS_GM45(dev))
		6974	vco_table = ctg_vco;
		6975	else if (IS_G4X(dev))
		6976	vco_table = elk_vco;
		6977	else if (IS_CRESTLINE(dev))
		6978	vco_table = cl_vco;
		6979	else if (IS_PINEVIEW(dev))
		6980	vco_table = pnv_vco;
		6981	else if (IS_G33(dev))
		6982	vco_table = blb_vco;
		6983	else
		6984	return 0;
		6985
		6986	tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
		6987
		6988	vco = vco_table[tmp & 0x7];
		6989	if (vco == 0)
		6990	DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
		6991	else
		6992	DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
		6993
		6994	return vco;
		6995	}
		6996
		6997	static int gm45_get_display_clock_speed(struct drm_device *dev)
		6998	{
		6999	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
		7000	uint16_t tmp = 0;
		7001
		7002	pci_read_config_word(dev->pdev, GCFGC, &tmp);
		7003
		7004	cdclk_sel = (tmp >> 12) & 0x1;
		7005
		7006	switch (vco) {
		7007	case 2666667:
		7008	case 4000000:
		7009	case 5333333:
		7010	return cdclk_sel ? 333333 : 222222;
		7011	case 3200000:
		7012	return cdclk_sel ? 320000 : 228571;
		7013	default:
		7014	DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
		7015	return 222222;
		7016	}
		7017	}
		7018
		7019	static int i965gm_get_display_clock_speed(struct drm_device *dev)
		7020	{
		7021	static const uint8_t div_3200[] = { 16, 10, 8 };
		7022	static const uint8_t div_4000[] = { 20, 12, 10 };
		7023	static const uint8_t div_5333[] = { 24, 16, 14 };
		7024	const uint8_t *div_table;
		7025	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
		7026	uint16_t tmp = 0;
		7027
		7028	pci_read_config_word(dev->pdev, GCFGC, &tmp);
		7029
		7030	cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
		7031
		7032	if (cdclk_sel >= ARRAY_SIZE(div_3200))
		7033	goto fail;
		7034
		7035	switch (vco) {
		7036	case 3200000:
		7037	div_table = div_3200;
		7038	break;
		7039	case 4000000:
		7040	div_table = div_4000;
		7041	break;
		7042	case 5333333:
		7043	div_table = div_5333;
		7044	break;
		7045	default:
		7046	goto fail;
		7047	}
		7048
		7049	return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
		7050
		7051	fail:
		7052	DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
		7053	return 200000;
		7054	}
		7055
		7056	static int g33_get_display_clock_speed(struct drm_device *dev)
		7057	{
		7058	static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
		7059	static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
		7060	static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
		7061	static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
		7062	const uint8_t *div_table;
		7063	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
		7064	uint16_t tmp = 0;
		7065
		7066	pci_read_config_word(dev->pdev, GCFGC, &tmp);
		7067
		7068	cdclk_sel = (tmp >> 4) & 0x7;
		7069
		7070	if (cdclk_sel >= ARRAY_SIZE(div_3200))
		7071	goto fail;
		7072
		7073	switch (vco) {
		7074	case 3200000:
		7075	div_table = div_3200;
		7076	break;
		7077	case 4000000:
		7078	div_table = div_4000;
		7079	break;
		7080	case 4800000:
		7081	div_table = div_4800;
		7082	break;
		7083	case 5333333:
		7084	div_table = div_5333;
		7085	break;
		7086	default:
		7087	goto fail;
		7088	}
		7089
		7090	return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
		7091
		7092	fail:
		7093	DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
		7094	return 190476;
		7095	}
		7096
2327	Serge	7097	static void
3746	Serge	7098	intel_reduce_m_n_ratio(uint32_t num, uint32_t den)
2327	Serge	7099	{
3746	Serge	7100	while (*num > DATA_LINK_M_N_MASK \|\|
		7101	*den > DATA_LINK_M_N_MASK) {
2327	Serge	7102	*num >>= 1;
		7103	*den >>= 1;
		7104	}
		7105	}
		7106
3746	Serge	7107	static void compute_m_n(unsigned int m, unsigned int n,
		7108	uint32_t ret_m, uint32_t ret_n)
		7109	{
		7110	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
		7111	ret_m = div_u64((uint64_t) m *ret_n, n);
		7112	intel_reduce_m_n_ratio(ret_m, ret_n);
		7113	}
		7114
3480	Serge	7115	void
		7116	intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		7117	int pixel_clock, int link_clock,
		7118	struct intel_link_m_n *m_n)
2327	Serge	7119	{
3480	Serge	7120	m_n->tu = 64;
3746	Serge	7121
		7122	compute_m_n(bits_per_pixel * pixel_clock,
		7123	link_clock * nlanes * 8,
		7124	&m_n->gmch_m, &m_n->gmch_n);
		7125
		7126	compute_m_n(pixel_clock, link_clock,
		7127	&m_n->link_m, &m_n->link_n);
2327	Serge	7128	}
		7129
		7130	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		7131	{
5060	serge	7132	if (i915.panel_use_ssc >= 0)
		7133	return i915.panel_use_ssc != 0;
4104	Serge	7134	return dev_priv->vbt.lvds_use_ssc
2327	Serge	7135	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		7136	}
		7137
6084	serge	7138	static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
		7139	int num_connectors)
3031	serge	7140	{
6084	serge	7141	struct drm_device *dev = crtc_state->base.crtc->dev;
3031	serge	7142	struct drm_i915_private *dev_priv = dev->dev_private;
		7143	int refclk;
2327	Serge	7144
6084	serge	7145	WARN_ON(!crtc_state->base.state);
		7146
		7147	if (IS_VALLEYVIEW(dev) \|\| IS_BROXTON(dev)) {
4560	Serge	7148	refclk = 100000;
6084	serge	7149	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
3031	serge	7150	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4560	Serge	7151	refclk = dev_priv->vbt.lvds_ssc_freq;
		7152	DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
3031	serge	7153	} else if (!IS_GEN2(dev)) {
		7154	refclk = 96000;
		7155	} else {
		7156	refclk = 48000;
		7157	}
2327	Serge	7158
3031	serge	7159	return refclk;
		7160	}
2327	Serge	7161
4104	Serge	7162	static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
3031	serge	7163	{
4104	Serge	7164	return (1 << dpll->n) << 16 \| dpll->m2;
		7165	}
3746	Serge	7166
4104	Serge	7167	static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
		7168	{
		7169	return dpll->n << 16 \| dpll->m1 << 8 \| dpll->m2;
3031	serge	7170	}
2327	Serge	7171
3746	Serge	7172	static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6084	serge	7173	struct intel_crtc_state *crtc_state,
3031	serge	7174	intel_clock_t *reduced_clock)
		7175	{
3746	Serge	7176	struct drm_device *dev = crtc->base.dev;
3031	serge	7177	u32 fp, fp2 = 0;
2327	Serge	7178
3031	serge	7179	if (IS_PINEVIEW(dev)) {
6084	serge	7180	fp = pnv_dpll_compute_fp(&crtc_state->dpll);
3031	serge	7181	if (reduced_clock)
4104	Serge	7182	fp2 = pnv_dpll_compute_fp(reduced_clock);
3031	serge	7183	} else {
6084	serge	7184	fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
3031	serge	7185	if (reduced_clock)
4104	Serge	7186	fp2 = i9xx_dpll_compute_fp(reduced_clock);
3031	serge	7187	}
2327	Serge	7188
6084	serge	7189	crtc_state->dpll_hw_state.fp0 = fp;
2327	Serge	7190
3746	Serge	7191	crtc->lowfreq_avail = false;
6084	serge	7192	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
		7193	reduced_clock) {
		7194	crtc_state->dpll_hw_state.fp1 = fp2;
3746	Serge	7195	crtc->lowfreq_avail = true;
3031	serge	7196	} else {
6084	serge	7197	crtc_state->dpll_hw_state.fp1 = fp;
3031	serge	7198	}
		7199	}
2327	Serge	7200
4560	Serge	7201	static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
		7202	pipe)
4104	Serge	7203	{
		7204	u32 reg_val;
		7205
		7206	/*
		7207	* PLLB opamp always calibrates to max value of 0x3f, force enable it
		7208	* and set it to a reasonable value instead.
		7209	*/
4560	Serge	7210	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4104	Serge	7211	reg_val &= 0xffffff00;
		7212	reg_val \|= 0x00000030;
4560	Serge	7213	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4104	Serge	7214
4560	Serge	7215	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4104	Serge	7216	reg_val &= 0x8cffffff;
		7217	reg_val = 0x8c000000;
4560	Serge	7218	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4104	Serge	7219
4560	Serge	7220	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4104	Serge	7221	reg_val &= 0xffffff00;
4560	Serge	7222	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4104	Serge	7223
4560	Serge	7224	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4104	Serge	7225	reg_val &= 0x00ffffff;
		7226	reg_val \|= 0xb0000000;
4560	Serge	7227	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4104	Serge	7228	}
		7229
		7230	static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
		7231	struct intel_link_m_n *m_n)
		7232	{
		7233	struct drm_device *dev = crtc->base.dev;
		7234	struct drm_i915_private *dev_priv = dev->dev_private;
		7235	int pipe = crtc->pipe;
		7236
		7237	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		7238	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
		7239	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
		7240	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
		7241	}
		7242
		7243	static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5354	serge	7244	struct intel_link_m_n *m_n,
		7245	struct intel_link_m_n *m2_n2)
4104	Serge	7246	{
		7247	struct drm_device *dev = crtc->base.dev;
		7248	struct drm_i915_private *dev_priv = dev->dev_private;
		7249	int pipe = crtc->pipe;
6084	serge	7250	enum transcoder transcoder = crtc->config->cpu_transcoder;
4104	Serge	7251
		7252	if (INTEL_INFO(dev)->gen >= 5) {
		7253	I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		7254	I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		7255	I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		7256	I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5354	serge	7257	/* M2_N2 registers to be set only for gen < 8 (M2_N2 available
		7258	* for gen < 8) and if DRRS is supported (to make sure the
		7259	* registers are not unnecessarily accessed).
		7260	*/
6084	serge	7261	if (m2_n2 && (IS_CHERRYVIEW(dev) \|\| INTEL_INFO(dev)->gen < 8) &&
		7262	crtc->config->has_drrs) {
5354	serge	7263	I915_WRITE(PIPE_DATA_M2(transcoder),
		7264	TU_SIZE(m2_n2->tu) \| m2_n2->gmch_m);
		7265	I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
		7266	I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
		7267	I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
		7268	}
4104	Serge	7269	} else {
		7270	I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		7271	I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
		7272	I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
		7273	I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
		7274	}
		7275	}
		7276
6084	serge	7277	void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
3031	serge	7278	{
6084	serge	7279	struct intel_link_m_n dp_m_n, dp_m2_n2 = NULL;
		7280
		7281	if (m_n == M1_N1) {
		7282	dp_m_n = &crtc->config->dp_m_n;
		7283	dp_m2_n2 = &crtc->config->dp_m2_n2;
		7284	} else if (m_n == M2_N2) {
		7285
		7286	/*
		7287	* M2_N2 registers are not supported. Hence m2_n2 divider value
		7288	* needs to be programmed into M1_N1.
		7289	*/
		7290	dp_m_n = &crtc->config->dp_m2_n2;
		7291	} else {
		7292	DRM_ERROR("Unsupported divider value\n");
		7293	return;
		7294	}
		7295
		7296	if (crtc->config->has_pch_encoder)
		7297	intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
3746	Serge	7298	else
6084	serge	7299	intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
3746	Serge	7300	}
		7301
6084	serge	7302	static void vlv_compute_dpll(struct intel_crtc *crtc,
		7303	struct intel_crtc_state *pipe_config)
3746	Serge	7304	{
5060	serge	7305	u32 dpll, dpll_md;
		7306
		7307	/*
		7308	* Enable DPIO clock input. We should never disable the reference
		7309	* clock for pipe B, since VGA hotplug / manual detection depends
		7310	* on it.
		7311	*/
6084	serge	7312	dpll = DPLL_EXT_BUFFER_ENABLE_VLV \| DPLL_REF_CLK_ENABLE_VLV \|
		7313	DPLL_VGA_MODE_DIS \| DPLL_INTEGRATED_REF_CLK_VLV;
5060	serge	7314	/* We should never disable this, set it here for state tracking */
		7315	if (crtc->pipe == PIPE_B)
		7316	dpll \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		7317	dpll \|= DPLL_VCO_ENABLE;
5354	serge	7318	pipe_config->dpll_hw_state.dpll = dpll;
5060	serge	7319
5354	serge	7320	dpll_md = (pipe_config->pixel_multiplier - 1)
5060	serge	7321	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
5354	serge	7322	pipe_config->dpll_hw_state.dpll_md = dpll_md;
5060	serge	7323	}
		7324
5354	serge	7325	static void vlv_prepare_pll(struct intel_crtc *crtc,
6084	serge	7326	const struct intel_crtc_state *pipe_config)
5060	serge	7327	{
3746	Serge	7328	struct drm_device *dev = crtc->base.dev;
3031	serge	7329	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	7330	int pipe = crtc->pipe;
5060	serge	7331	u32 mdiv;
3031	serge	7332	u32 bestn, bestm1, bestm2, bestp1, bestp2;
5060	serge	7333	u32 coreclk, reg_val;
2327	Serge	7334
6084	serge	7335	mutex_lock(&dev_priv->sb_lock);
3480	Serge	7336
5354	serge	7337	bestn = pipe_config->dpll.n;
		7338	bestm1 = pipe_config->dpll.m1;
		7339	bestm2 = pipe_config->dpll.m2;
		7340	bestp1 = pipe_config->dpll.p1;
		7341	bestp2 = pipe_config->dpll.p2;
3031	serge	7342
4104	Serge	7343	/* See eDP HDMI DPIO driver vbios notes doc */
		7344
		7345	/* PLL B needs special handling */
5060	serge	7346	if (pipe == PIPE_B)
4560	Serge	7347	vlv_pllb_recal_opamp(dev_priv, pipe);
4104	Serge	7348
		7349	/* Set up Tx target for periodic Rcomp update */
4560	Serge	7350	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4104	Serge	7351
		7352	/* Disable target IRef on PLL */
4560	Serge	7353	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4104	Serge	7354	reg_val &= 0x00ffffff;
4560	Serge	7355	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4104	Serge	7356
		7357	/* Disable fast lock */
4560	Serge	7358	vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4104	Serge	7359
		7360	/* Set idtafcrecal before PLL is enabled */
3031	serge	7361	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		7362	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		7363	mdiv \|= ((bestn << DPIO_N_SHIFT));
		7364	mdiv \|= (1 << DPIO_K_SHIFT);
4104	Serge	7365
		7366	/*
		7367	* Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
		7368	* but we don't support that).
		7369	* Note: don't use the DAC post divider as it seems unstable.
		7370	*/
		7371	mdiv \|= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4560	Serge	7372	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4104	Serge	7373
3031	serge	7374	mdiv \|= DPIO_ENABLE_CALIBRATION;
4560	Serge	7375	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
3031	serge	7376
4104	Serge	7377	/* Set HBR and RBR LPF coefficients */
5354	serge	7378	if (pipe_config->port_clock == 162000 \|\|
		7379	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) \|\|
		7380	intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4560	Serge	7381	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4104	Serge	7382	0x009f0003);
		7383	else
4560	Serge	7384	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4104	Serge	7385	0x00d0000f);
3031	serge	7386
6084	serge	7387	if (pipe_config->has_dp_encoder) {
4104	Serge	7388	/* Use SSC source */
5060	serge	7389	if (pipe == PIPE_A)
4560	Serge	7390	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104	Serge	7391	0x0df40000);
		7392	else
4560	Serge	7393	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104	Serge	7394	0x0df70000);
		7395	} else { /* HDMI or VGA */
		7396	/* Use bend source */
5060	serge	7397	if (pipe == PIPE_A)
4560	Serge	7398	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104	Serge	7399	0x0df70000);
		7400	else
4560	Serge	7401	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104	Serge	7402	0x0df40000);
		7403	}
3031	serge	7404
4560	Serge	7405	coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4104	Serge	7406	coreclk = (coreclk & 0x0000ff00) \| 0x01c00000;
5354	serge	7407	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		7408	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4104	Serge	7409	coreclk \|= 0x01000000;
4560	Serge	7410	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
3031	serge	7411
4560	Serge	7412	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6084	serge	7413	mutex_unlock(&dev_priv->sb_lock);
5060	serge	7414	}
4104	Serge	7415
6084	serge	7416	static void chv_compute_dpll(struct intel_crtc *crtc,
		7417	struct intel_crtc_state *pipe_config)
5060	serge	7418	{
6084	serge	7419	pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV \|
		7420	DPLL_REF_CLK_ENABLE_VLV \| DPLL_VGA_MODE_DIS \|
5354	serge	7421	DPLL_VCO_ENABLE;
		7422	if (crtc->pipe != PIPE_A)
		7423	pipe_config->dpll_hw_state.dpll \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		7424
		7425	pipe_config->dpll_hw_state.dpll_md =
		7426	(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		7427	}
		7428
		7429	static void chv_prepare_pll(struct intel_crtc *crtc,
6084	serge	7430	const struct intel_crtc_state *pipe_config)
5354	serge	7431	{
5060	serge	7432	struct drm_device *dev = crtc->base.dev;
		7433	struct drm_i915_private *dev_priv = dev->dev_private;
		7434	int pipe = crtc->pipe;
		7435	int dpll_reg = DPLL(crtc->pipe);
		7436	enum dpio_channel port = vlv_pipe_to_channel(pipe);
6084	serge	7437	u32 loopfilter, tribuf_calcntr;
5060	serge	7438	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6084	serge	7439	u32 dpio_val;
		7440	int vco;
5060	serge	7441
5354	serge	7442	bestn = pipe_config->dpll.n;
		7443	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
		7444	bestm1 = pipe_config->dpll.m1;
		7445	bestm2 = pipe_config->dpll.m2 >> 22;
		7446	bestp1 = pipe_config->dpll.p1;
		7447	bestp2 = pipe_config->dpll.p2;
6084	serge	7448	vco = pipe_config->dpll.vco;
		7449	dpio_val = 0;
		7450	loopfilter = 0;
5060	serge	7451
4560	Serge	7452	/*
5060	serge	7453	* Enable Refclk and SSC
4560	Serge	7454	*/
5060	serge	7455	I915_WRITE(dpll_reg,
5354	serge	7456	pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
3031	serge	7457
6084	serge	7458	mutex_lock(&dev_priv->sb_lock);
3031	serge	7459
5060	serge	7460	/* p1 and p2 divider */
		7461	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
		7462	5 << DPIO_CHV_S1_DIV_SHIFT \|
		7463	bestp1 << DPIO_CHV_P1_DIV_SHIFT \|
		7464	bestp2 << DPIO_CHV_P2_DIV_SHIFT \|
		7465	1 << DPIO_CHV_K_DIV_SHIFT);
3243	Serge	7466
5060	serge	7467	/* Feedback post-divider - m2 */
		7468	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
		7469
		7470	/* Feedback refclk divider - n and m1 */
		7471	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
		7472	DPIO_CHV_M1_DIV_BY_2 \|
		7473	1 << DPIO_CHV_N_DIV_SHIFT);
		7474
		7475	/* M2 fraction division */
		7476	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
		7477
		7478	/* M2 fraction division enable */
6084	serge	7479	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
		7480	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK \| DPIO_CHV_FRAC_DIV_EN);
		7481	dpio_val \|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
		7482	if (bestm2_frac)
		7483	dpio_val \|= DPIO_CHV_FRAC_DIV_EN;
		7484	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
5060	serge	7485
6084	serge	7486	/* Program digital lock detect threshold */
		7487	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
		7488	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK \|
		7489	DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
		7490	dpio_val \|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
		7491	if (!bestm2_frac)
		7492	dpio_val \|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
		7493	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
		7494
5060	serge	7495	/* Loop filter */
6084	serge	7496	if (vco == 5400000) {
		7497	loopfilter \|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
		7498	loopfilter \|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
		7499	loopfilter \|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
		7500	tribuf_calcntr = 0x9;
		7501	} else if (vco <= 6200000) {
		7502	loopfilter \|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
		7503	loopfilter \|= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
		7504	loopfilter \|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
		7505	tribuf_calcntr = 0x9;
		7506	} else if (vco <= 6480000) {
		7507	loopfilter \|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
		7508	loopfilter \|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
		7509	loopfilter \|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
		7510	tribuf_calcntr = 0x8;
		7511	} else {
		7512	/* Not supported. Apply the same limits as in the max case */
		7513	loopfilter \|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
		7514	loopfilter \|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
		7515	loopfilter \|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
		7516	tribuf_calcntr = 0;
		7517	}
5060	serge	7518	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
		7519
6084	serge	7520	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
		7521	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
		7522	dpio_val \|= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
		7523	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
		7524
5060	serge	7525	/* AFC Recal */
		7526	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
		7527	vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) \|
		7528	DPIO_AFC_RECAL);
		7529
6084	serge	7530	mutex_unlock(&dev_priv->sb_lock);
3031	serge	7531	}
		7532
5354	serge	7533	/**
		7534	* vlv_force_pll_on - forcibly enable just the PLL
		7535	* @dev_priv: i915 private structure
		7536	* @pipe: pipe PLL to enable
		7537	* @dpll: PLL configuration
		7538	*
		7539	* Enable the PLL for @pipe using the supplied @dpll config. To be used
		7540	* in cases where we need the PLL enabled even when @pipe is not going to
		7541	* be enabled.
		7542	*/
		7543	void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
		7544	const struct dpll *dpll)
		7545	{
		7546	struct intel_crtc *crtc =
		7547	to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6084	serge	7548	struct intel_crtc_state pipe_config = {
		7549	.base.crtc = &crtc->base,
5354	serge	7550	.pixel_multiplier = 1,
		7551	.dpll = *dpll,
		7552	};
		7553
		7554	if (IS_CHERRYVIEW(dev)) {
6084	serge	7555	chv_compute_dpll(crtc, &pipe_config);
5354	serge	7556	chv_prepare_pll(crtc, &pipe_config);
		7557	chv_enable_pll(crtc, &pipe_config);
		7558	} else {
6084	serge	7559	vlv_compute_dpll(crtc, &pipe_config);
5354	serge	7560	vlv_prepare_pll(crtc, &pipe_config);
		7561	vlv_enable_pll(crtc, &pipe_config);
		7562	}
		7563	}
		7564
		7565	/**
		7566	* vlv_force_pll_off - forcibly disable just the PLL
		7567	* @dev_priv: i915 private structure
		7568	* @pipe: pipe PLL to disable
		7569	*
		7570	* Disable the PLL for @pipe. To be used in cases where we need
		7571	* the PLL enabled even when @pipe is not going to be enabled.
		7572	*/
		7573	void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
		7574	{
		7575	if (IS_CHERRYVIEW(dev))
		7576	chv_disable_pll(to_i915(dev), pipe);
		7577	else
		7578	vlv_disable_pll(to_i915(dev), pipe);
		7579	}
		7580
6084	serge	7581	static void i9xx_compute_dpll(struct intel_crtc *crtc,
		7582	struct intel_crtc_state *crtc_state,
		7583	intel_clock_t *reduced_clock,
		7584	int num_connectors)
3031	serge	7585	{
3746	Serge	7586	struct drm_device *dev = crtc->base.dev;
3031	serge	7587	struct drm_i915_private *dev_priv = dev->dev_private;
		7588	u32 dpll;
		7589	bool is_sdvo;
6084	serge	7590	struct dpll *clock = &crtc_state->dpll;
3031	serge	7591
6084	serge	7592	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
3243	Serge	7593
6084	serge	7594	is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) \|\|
		7595	intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
3031	serge	7596
		7597	dpll = DPLL_VGA_MODE_DIS;
		7598
6084	serge	7599	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
3031	serge	7600	dpll \|= DPLLB_MODE_LVDS;
		7601	else
		7602	dpll \|= DPLLB_MODE_DAC_SERIAL;
3746	Serge	7603
4104	Serge	7604	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
6084	serge	7605	dpll \|= (crtc_state->pixel_multiplier - 1)
		7606	<< SDVO_MULTIPLIER_SHIFT_HIRES;
		7607	}
4104	Serge	7608
		7609	if (is_sdvo)
		7610	dpll \|= DPLL_SDVO_HIGH_SPEED;
		7611
6084	serge	7612	if (crtc_state->has_dp_encoder)
4104	Serge	7613	dpll \|= DPLL_SDVO_HIGH_SPEED;
2342	Serge	7614
3031	serge	7615	/* compute bitmask from p1 value */
		7616	if (IS_PINEVIEW(dev))
		7617	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		7618	else {
		7619	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		7620	if (IS_G4X(dev) && reduced_clock)
		7621	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		7622	}
		7623	switch (clock->p2) {
		7624	case 5:
		7625	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		7626	break;
		7627	case 7:
		7628	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		7629	break;
		7630	case 10:
		7631	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		7632	break;
		7633	case 14:
		7634	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		7635	break;
		7636	}
		7637	if (INTEL_INFO(dev)->gen >= 4)
		7638	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	7639
6084	serge	7640	if (crtc_state->sdvo_tv_clock)
3031	serge	7641	dpll \|= PLL_REF_INPUT_TVCLKINBC;
6084	serge	7642	else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
3031	serge	7643	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		7644	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		7645	else
		7646	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	7647
3031	serge	7648	dpll \|= DPLL_VCO_ENABLE;
6084	serge	7649	crtc_state->dpll_hw_state.dpll = dpll;
2327	Serge	7650
4104	Serge	7651	if (INTEL_INFO(dev)->gen >= 4) {
6084	serge	7652	u32 dpll_md = (crtc_state->pixel_multiplier - 1)
		7653	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		7654	crtc_state->dpll_hw_state.dpll_md = dpll_md;
4104	Serge	7655	}
3031	serge	7656	}
2327	Serge	7657
6084	serge	7658	static void i8xx_compute_dpll(struct intel_crtc *crtc,
		7659	struct intel_crtc_state *crtc_state,
		7660	intel_clock_t *reduced_clock,
		7661	int num_connectors)
3031	serge	7662	{
3746	Serge	7663	struct drm_device *dev = crtc->base.dev;
3031	serge	7664	struct drm_i915_private *dev_priv = dev->dev_private;
		7665	u32 dpll;
6084	serge	7666	struct dpll *clock = &crtc_state->dpll;
2327	Serge	7667
6084	serge	7668	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
3243	Serge	7669
3031	serge	7670	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	7671
6084	serge	7672	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
3031	serge	7673	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		7674	} else {
		7675	if (clock->p1 == 2)
		7676	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		7677	else
		7678	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		7679	if (clock->p2 == 4)
		7680	dpll \|= PLL_P2_DIVIDE_BY_4;
		7681	}
2327	Serge	7682
6084	serge	7683	if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4104	Serge	7684	dpll \|= DPLL_DVO_2X_MODE;
		7685
6084	serge	7686	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
3031	serge	7687	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		7688	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		7689	else
		7690	dpll \|= PLL_REF_INPUT_DREFCLK;
		7691
		7692	dpll \|= DPLL_VCO_ENABLE;
6084	serge	7693	crtc_state->dpll_hw_state.dpll = dpll;
3031	serge	7694	}
		7695
4104	Serge	7696	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
3243	Serge	7697	{
		7698	struct drm_device *dev = intel_crtc->base.dev;
		7699	struct drm_i915_private *dev_priv = dev->dev_private;
		7700	enum pipe pipe = intel_crtc->pipe;
6084	serge	7701	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
		7702	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
5060	serge	7703	uint32_t crtc_vtotal, crtc_vblank_end;
		7704	int vsyncshift = 0;
3243	Serge	7705
4104	Serge	7706	/* We need to be careful not to changed the adjusted mode, for otherwise
		7707	* the hw state checker will get angry at the mismatch. */
		7708	crtc_vtotal = adjusted_mode->crtc_vtotal;
		7709	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
		7710
5060	serge	7711	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3243	Serge	7712	/* the chip adds 2 halflines automatically */
4104	Serge	7713	crtc_vtotal -= 1;
		7714	crtc_vblank_end -= 1;
5060	serge	7715
5354	serge	7716	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
5060	serge	7717	vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
		7718	else
		7719	vsyncshift = adjusted_mode->crtc_hsync_start -
		7720	adjusted_mode->crtc_htotal / 2;
		7721	if (vsyncshift < 0)
		7722	vsyncshift += adjusted_mode->crtc_htotal;
3243	Serge	7723	}
		7724
		7725	if (INTEL_INFO(dev)->gen > 3)
		7726	I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
		7727
		7728	I915_WRITE(HTOTAL(cpu_transcoder),
		7729	(adjusted_mode->crtc_hdisplay - 1) \|
		7730	((adjusted_mode->crtc_htotal - 1) << 16));
		7731	I915_WRITE(HBLANK(cpu_transcoder),
		7732	(adjusted_mode->crtc_hblank_start - 1) \|
		7733	((adjusted_mode->crtc_hblank_end - 1) << 16));
		7734	I915_WRITE(HSYNC(cpu_transcoder),
		7735	(adjusted_mode->crtc_hsync_start - 1) \|
		7736	((adjusted_mode->crtc_hsync_end - 1) << 16));
		7737
		7738	I915_WRITE(VTOTAL(cpu_transcoder),
		7739	(adjusted_mode->crtc_vdisplay - 1) \|
4104	Serge	7740	((crtc_vtotal - 1) << 16));
3243	Serge	7741	I915_WRITE(VBLANK(cpu_transcoder),
		7742	(adjusted_mode->crtc_vblank_start - 1) \|
4104	Serge	7743	((crtc_vblank_end - 1) << 16));
3243	Serge	7744	I915_WRITE(VSYNC(cpu_transcoder),
		7745	(adjusted_mode->crtc_vsync_start - 1) \|
		7746	((adjusted_mode->crtc_vsync_end - 1) << 16));
		7747
		7748	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
		7749	* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
		7750	* documented on the DDI_FUNC_CTL register description, EDP Input Select
		7751	* bits. */
		7752	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
		7753	(pipe == PIPE_B \|\| pipe == PIPE_C))
		7754	I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
		7755
		7756	/* pipesrc controls the size that is scaled from, which should
		7757	* always be the user's requested size.
		7758	*/
		7759	I915_WRITE(PIPESRC(pipe),
6084	serge	7760	((intel_crtc->config->pipe_src_w - 1) << 16) \|
		7761	(intel_crtc->config->pipe_src_h - 1));
3243	Serge	7762	}
		7763
4104	Serge	7764	static void intel_get_pipe_timings(struct intel_crtc *crtc,
6084	serge	7765	struct intel_crtc_state *pipe_config)
4104	Serge	7766	{
		7767	struct drm_device *dev = crtc->base.dev;
		7768	struct drm_i915_private *dev_priv = dev->dev_private;
		7769	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		7770	uint32_t tmp;
		7771
		7772	tmp = I915_READ(HTOTAL(cpu_transcoder));
6084	serge	7773	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
		7774	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4104	Serge	7775	tmp = I915_READ(HBLANK(cpu_transcoder));
6084	serge	7776	pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
		7777	pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4104	Serge	7778	tmp = I915_READ(HSYNC(cpu_transcoder));
6084	serge	7779	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
		7780	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4104	Serge	7781
		7782	tmp = I915_READ(VTOTAL(cpu_transcoder));
6084	serge	7783	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
		7784	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4104	Serge	7785	tmp = I915_READ(VBLANK(cpu_transcoder));
6084	serge	7786	pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
		7787	pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4104	Serge	7788	tmp = I915_READ(VSYNC(cpu_transcoder));
6084	serge	7789	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
		7790	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4104	Serge	7791
		7792	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6084	serge	7793	pipe_config->base.adjusted_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		7794	pipe_config->base.adjusted_mode.crtc_vtotal += 1;
		7795	pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
4104	Serge	7796	}
		7797
		7798	tmp = I915_READ(PIPESRC(crtc->pipe));
4560	Serge	7799	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
		7800	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
		7801
6084	serge	7802	pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
		7803	pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
4104	Serge	7804	}
		7805
5060	serge	7806	void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6084	serge	7807	struct intel_crtc_state *pipe_config)
4104	Serge	7808	{
6084	serge	7809	mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
		7810	mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
		7811	mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
		7812	mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
4104	Serge	7813
6084	serge	7814	mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
		7815	mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
		7816	mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
		7817	mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
4104	Serge	7818
6084	serge	7819	mode->flags = pipe_config->base.adjusted_mode.flags;
		7820	mode->type = DRM_MODE_TYPE_DRIVER;
4104	Serge	7821
6084	serge	7822	mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
		7823	mode->flags \|= pipe_config->base.adjusted_mode.flags;
		7824
		7825	mode->hsync = drm_mode_hsync(mode);
		7826	mode->vrefresh = drm_mode_vrefresh(mode);
		7827	drm_mode_set_name(mode);
4104	Serge	7828	}
		7829
3746	Serge	7830	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
		7831	{
		7832	struct drm_device *dev = intel_crtc->base.dev;
		7833	struct drm_i915_private *dev_priv = dev->dev_private;
		7834	uint32_t pipeconf;
		7835
4104	Serge	7836	pipeconf = 0;
3746	Serge	7837
5354	serge	7838	if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) \|\|
		7839	(intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
		7840	pipeconf \|= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
4104	Serge	7841
6084	serge	7842	if (intel_crtc->config->double_wide)
		7843	pipeconf \|= PIPECONF_DOUBLE_WIDE;
3746	Serge	7844
4104	Serge	7845	/* only g4x and later have fancy bpc/dither controls */
		7846	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		7847	/* Bspec claims that we can't use dithering for 30bpp pipes. */
6084	serge	7848	if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
4104	Serge	7849	pipeconf \|= PIPECONF_DITHER_EN \|
3746	Serge	7850	PIPECONF_DITHER_TYPE_SP;
		7851
6084	serge	7852	switch (intel_crtc->config->pipe_bpp) {
4104	Serge	7853	case 18:
		7854	pipeconf \|= PIPECONF_6BPC;
		7855	break;
		7856	case 24:
		7857	pipeconf \|= PIPECONF_8BPC;
		7858	break;
		7859	case 30:
		7860	pipeconf \|= PIPECONF_10BPC;
		7861	break;
		7862	default:
		7863	/* Case prevented by intel_choose_pipe_bpp_dither. */
		7864	BUG();
3746	Serge	7865	}
		7866	}
		7867
		7868	if (HAS_PIPE_CXSR(dev)) {
		7869	if (intel_crtc->lowfreq_avail) {
		7870	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		7871	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		7872	} else {
		7873	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		7874	}
		7875	}
		7876
6084	serge	7877	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5060	serge	7878	if (INTEL_INFO(dev)->gen < 4 \|\|
5354	serge	7879	intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6084	serge	7880	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		7881	else
5060	serge	7882	pipeconf \|= PIPECONF_INTERLACE_W_SYNC_SHIFT;
		7883	} else
3746	Serge	7884	pipeconf \|= PIPECONF_PROGRESSIVE;
		7885
6084	serge	7886	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
		7887	pipeconf \|= PIPECONF_COLOR_RANGE_SELECT;
3746	Serge	7888
		7889	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
		7890	POSTING_READ(PIPECONF(intel_crtc->pipe));
		7891	}
		7892
6084	serge	7893	static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
		7894	struct intel_crtc_state *crtc_state)
3031	serge	7895	{
5354	serge	7896	struct drm_device *dev = crtc->base.dev;
3031	serge	7897	struct drm_i915_private *dev_priv = dev->dev_private;
		7898	int refclk, num_connectors = 0;
6084	serge	7899	intel_clock_t clock;
		7900	bool ok;
		7901	bool is_dsi = false;
3031	serge	7902	struct intel_encoder *encoder;
		7903	const intel_limit_t *limit;
6084	serge	7904	struct drm_atomic_state *state = crtc_state->base.state;
		7905	struct drm_connector *connector;
		7906	struct drm_connector_state *connector_state;
		7907	int i;
3031	serge	7908
6084	serge	7909	memset(&crtc_state->dpll_hw_state, 0,
		7910	sizeof(crtc_state->dpll_hw_state));
		7911
		7912	for_each_connector_in_state(state, connector, connector_state, i) {
		7913	if (connector_state->crtc != &crtc->base)
5354	serge	7914	continue;
		7915
6084	serge	7916	encoder = to_intel_encoder(connector_state->best_encoder);
		7917
3031	serge	7918	switch (encoder->type) {
4560	Serge	7919	case INTEL_OUTPUT_DSI:
		7920	is_dsi = true;
		7921	break;
5354	serge	7922	default:
		7923	break;
3031	serge	7924	}
		7925
		7926	num_connectors++;
		7927	}
		7928
4560	Serge	7929	if (is_dsi)
5060	serge	7930	return 0;
4560	Serge	7931
6084	serge	7932	if (!crtc_state->clock_set) {
		7933	refclk = i9xx_get_refclk(crtc_state, num_connectors);
3031	serge	7934
6084	serge	7935	/*
4560	Serge	7936	* Returns a set of divisors for the desired target clock with
		7937	* the given refclk, or FALSE. The returned values represent
		7938	* the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
		7939	* 2) / p1 / p2.
6084	serge	7940	*/
		7941	limit = intel_limit(crtc_state, refclk);
		7942	ok = dev_priv->display.find_dpll(limit, crtc_state,
		7943	crtc_state->port_clock,
		7944	refclk, NULL, &clock);
4560	Serge	7945	if (!ok) {
6084	serge	7946	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		7947	return -EINVAL;
		7948	}
3031	serge	7949
6084	serge	7950	/* Compat-code for transition, will disappear. */
		7951	crtc_state->dpll.n = clock.n;
		7952	crtc_state->dpll.m1 = clock.m1;
		7953	crtc_state->dpll.m2 = clock.m2;
		7954	crtc_state->dpll.p1 = clock.p1;
		7955	crtc_state->dpll.p2 = clock.p2;
3031	serge	7956	}
		7957
4560	Serge	7958	if (IS_GEN2(dev)) {
6084	serge	7959	i8xx_compute_dpll(crtc, crtc_state, NULL,
		7960	num_connectors);
5060	serge	7961	} else if (IS_CHERRYVIEW(dev)) {
6084	serge	7962	chv_compute_dpll(crtc, crtc_state);
4560	Serge	7963	} else if (IS_VALLEYVIEW(dev)) {
6084	serge	7964	vlv_compute_dpll(crtc, crtc_state);
4560	Serge	7965	} else {
6084	serge	7966	i9xx_compute_dpll(crtc, crtc_state, NULL,
		7967	num_connectors);
4560	Serge	7968	}
3031	serge	7969
5060	serge	7970	return 0;
2327	Serge	7971	}
		7972
4104	Serge	7973	static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6084	serge	7974	struct intel_crtc_state *pipe_config)
4104	Serge	7975	{
		7976	struct drm_device *dev = crtc->base.dev;
		7977	struct drm_i915_private *dev_priv = dev->dev_private;
		7978	uint32_t tmp;
		7979
4560	Serge	7980	if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) \|\| !IS_MOBILE(dev)))
		7981	return;
		7982
4104	Serge	7983	tmp = I915_READ(PFIT_CONTROL);
		7984	if (!(tmp & PFIT_ENABLE))
		7985	return;
		7986
		7987	/* Check whether the pfit is attached to our pipe. */
		7988	if (INTEL_INFO(dev)->gen < 4) {
		7989	if (crtc->pipe != PIPE_B)
		7990	return;
		7991	} else {
		7992	if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
		7993	return;
		7994	}
		7995
		7996	pipe_config->gmch_pfit.control = tmp;
		7997	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
		7998	if (INTEL_INFO(dev)->gen < 5)
		7999	pipe_config->gmch_pfit.lvds_border_bits =
		8000	I915_READ(LVDS) & LVDS_BORDER_ENABLE;
		8001	}
		8002
4398	Serge	8003	static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6084	serge	8004	struct intel_crtc_state *pipe_config)
4398	Serge	8005	{
		8006	struct drm_device *dev = crtc->base.dev;
		8007	struct drm_i915_private *dev_priv = dev->dev_private;
		8008	int pipe = pipe_config->cpu_transcoder;
		8009	intel_clock_t clock;
		8010	u32 mdiv;
		8011	int refclk = 100000;
		8012
5060	serge	8013	/* In case of MIPI DPLL will not even be used */
		8014	if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
		8015	return;
		8016
6084	serge	8017	mutex_lock(&dev_priv->sb_lock);
4560	Serge	8018	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6084	serge	8019	mutex_unlock(&dev_priv->sb_lock);
4398	Serge	8020
		8021	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
		8022	clock.m2 = mdiv & DPIO_M2DIV_MASK;
		8023	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
		8024	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
		8025	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
		8026
6084	serge	8027	pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
4398	Serge	8028	}
		8029
6084	serge	8030	static void
		8031	i9xx_get_initial_plane_config(struct intel_crtc *crtc,
		8032	struct intel_initial_plane_config *plane_config)
5060	serge	8033	{
		8034	struct drm_device *dev = crtc->base.dev;
		8035	struct drm_i915_private *dev_priv = dev->dev_private;
		8036	u32 val, base, offset;
		8037	int pipe = crtc->pipe, plane = crtc->plane;
		8038	int fourcc, pixel_format;
6084	serge	8039	unsigned int aligned_height;
		8040	struct drm_framebuffer *fb;
		8041	struct intel_framebuffer *intel_fb;
5060	serge	8042
6084	serge	8043	val = I915_READ(DSPCNTR(plane));
		8044	if (!(val & DISPLAY_PLANE_ENABLE))
		8045	return;
		8046
		8047	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		8048	if (!intel_fb) {
5060	serge	8049	DRM_DEBUG_KMS("failed to alloc fb\n");
		8050	return;
		8051	}
		8052
6084	serge	8053	fb = &intel_fb->base;
5060	serge	8054
6084	serge	8055	if (INTEL_INFO(dev)->gen >= 4) {
		8056	if (val & DISPPLANE_TILED) {
		8057	plane_config->tiling = I915_TILING_X;
		8058	fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
		8059	}
		8060	}
5060	serge	8061
		8062	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6084	serge	8063	fourcc = i9xx_format_to_fourcc(pixel_format);
		8064	fb->pixel_format = fourcc;
		8065	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
5060	serge	8066
		8067	if (INTEL_INFO(dev)->gen >= 4) {
6084	serge	8068	if (plane_config->tiling)
5060	serge	8069	offset = I915_READ(DSPTILEOFF(plane));
		8070	else
		8071	offset = I915_READ(DSPLINOFF(plane));
		8072	base = I915_READ(DSPSURF(plane)) & 0xfffff000;
		8073	} else {
		8074	base = I915_READ(DSPADDR(plane));
		8075	}
		8076	plane_config->base = base;
		8077
		8078	val = I915_READ(PIPESRC(pipe));
6084	serge	8079	fb->width = ((val >> 16) & 0xfff) + 1;
		8080	fb->height = ((val >> 0) & 0xfff) + 1;
5060	serge	8081
		8082	val = I915_READ(DSPSTRIDE(pipe));
6283	serge	8083	fb->pitches[0] = val & 0xffffffc0;
5060	serge	8084
6084	serge	8085	aligned_height = intel_fb_align_height(dev, fb->height,
		8086	fb->pixel_format,
		8087	fb->modifier[0]);
5060	serge	8088
6283	serge	8089	plane_config->size = fb->pitches[0] * aligned_height;
5060	serge	8090
6084	serge	8091	DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
		8092	pipe_name(pipe), plane, fb->width, fb->height,
		8093	fb->bits_per_pixel, base, fb->pitches[0],
5060	serge	8094	plane_config->size);
		8095
6084	serge	8096	plane_config->fb = intel_fb;
5060	serge	8097	}
		8098
		8099	static void chv_crtc_clock_get(struct intel_crtc *crtc,
6084	serge	8100	struct intel_crtc_state *pipe_config)
5060	serge	8101	{
		8102	struct drm_device *dev = crtc->base.dev;
		8103	struct drm_i915_private *dev_priv = dev->dev_private;
		8104	int pipe = pipe_config->cpu_transcoder;
		8105	enum dpio_channel port = vlv_pipe_to_channel(pipe);
		8106	intel_clock_t clock;
6084	serge	8107	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
5060	serge	8108	int refclk = 100000;
		8109
6084	serge	8110	mutex_lock(&dev_priv->sb_lock);
5060	serge	8111	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
		8112	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
		8113	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
		8114	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6084	serge	8115	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
		8116	mutex_unlock(&dev_priv->sb_lock);
5060	serge	8117
		8118	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6084	serge	8119	clock.m2 = (pll_dw0 & 0xff) << 22;
		8120	if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
		8121	clock.m2 \|= pll_dw2 & 0x3fffff;
5060	serge	8122	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
		8123	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
		8124	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
		8125
6084	serge	8126	pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
5060	serge	8127	}
		8128
3746	Serge	8129	static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6084	serge	8130	struct intel_crtc_state *pipe_config)
3746	Serge	8131	{
		8132	struct drm_device *dev = crtc->base.dev;
		8133	struct drm_i915_private *dev_priv = dev->dev_private;
		8134	uint32_t tmp;
		8135
5354	serge	8136	if (!intel_display_power_is_enabled(dev_priv,
6084	serge	8137	POWER_DOMAIN_PIPE(crtc->pipe)))
5060	serge	8138	return false;
		8139
4104	Serge	8140	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		8141	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		8142
3746	Serge	8143	tmp = I915_READ(PIPECONF(crtc->pipe));
		8144	if (!(tmp & PIPECONF_ENABLE))
		8145	return false;
		8146
4280	Serge	8147	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		8148	switch (tmp & PIPECONF_BPC_MASK) {
		8149	case PIPECONF_6BPC:
		8150	pipe_config->pipe_bpp = 18;
		8151	break;
		8152	case PIPECONF_8BPC:
		8153	pipe_config->pipe_bpp = 24;
		8154	break;
		8155	case PIPECONF_10BPC:
		8156	pipe_config->pipe_bpp = 30;
		8157	break;
		8158	default:
		8159	break;
		8160	}
		8161	}
		8162
5060	serge	8163	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
		8164	pipe_config->limited_color_range = true;
		8165
4560	Serge	8166	if (INTEL_INFO(dev)->gen < 4)
		8167	pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
		8168
4104	Serge	8169	intel_get_pipe_timings(crtc, pipe_config);
		8170
		8171	i9xx_get_pfit_config(crtc, pipe_config);
		8172
		8173	if (INTEL_INFO(dev)->gen >= 4) {
		8174	tmp = I915_READ(DPLL_MD(crtc->pipe));
		8175	pipe_config->pixel_multiplier =
		8176	((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
		8177	>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
		8178	pipe_config->dpll_hw_state.dpll_md = tmp;
		8179	} else if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
		8180	tmp = I915_READ(DPLL(crtc->pipe));
		8181	pipe_config->pixel_multiplier =
		8182	((tmp & SDVO_MULTIPLIER_MASK)
		8183	>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
		8184	} else {
		8185	/* Note that on i915G/GM the pixel multiplier is in the sdvo
		8186	* port and will be fixed up in the encoder->get_config
		8187	* function. */
		8188	pipe_config->pixel_multiplier = 1;
		8189	}
		8190	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
		8191	if (!IS_VALLEYVIEW(dev)) {
5354	serge	8192	/*
		8193	* DPLL_DVO_2X_MODE must be enabled for both DPLLs
		8194	* on 830. Filter it out here so that we don't
		8195	* report errors due to that.
		8196	*/
		8197	if (IS_I830(dev))
		8198	pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
		8199
4104	Serge	8200	pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
		8201	pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
		8202	} else {
		8203	/* Mask out read-only status bits. */
		8204	pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV \|
		8205	DPLL_PORTC_READY_MASK \|
		8206	DPLL_PORTB_READY_MASK);
		8207	}
		8208
5060	serge	8209	if (IS_CHERRYVIEW(dev))
		8210	chv_crtc_clock_get(crtc, pipe_config);
		8211	else if (IS_VALLEYVIEW(dev))
4560	Serge	8212	vlv_crtc_clock_get(crtc, pipe_config);
		8213	else
		8214	i9xx_crtc_clock_get(crtc, pipe_config);
		8215
6084	serge	8216	/*
		8217	* Normally the dotclock is filled in by the encoder .get_config()
		8218	* but in case the pipe is enabled w/o any ports we need a sane
		8219	* default.
		8220	*/
		8221	pipe_config->base.adjusted_mode.crtc_clock =
		8222	pipe_config->port_clock / pipe_config->pixel_multiplier;
		8223
3746	Serge	8224	return true;
		8225	}
		8226
3243	Serge	8227	static void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	8228	{
		8229	struct drm_i915_private *dev_priv = dev->dev_private;
		8230	struct intel_encoder *encoder;
3746	Serge	8231	u32 val, final;
2327	Serge	8232	bool has_lvds = false;
2342	Serge	8233	bool has_cpu_edp = false;
		8234	bool has_panel = false;
		8235	bool has_ck505 = false;
		8236	bool can_ssc = false;
2327	Serge	8237
		8238	/* We need to take the global config into account */
5354	serge	8239	for_each_intel_encoder(dev, encoder) {
6084	serge	8240	switch (encoder->type) {
		8241	case INTEL_OUTPUT_LVDS:
2342	Serge	8242	has_panel = true;
6084	serge	8243	has_lvds = true;
2342	Serge	8244	break;
6084	serge	8245	case INTEL_OUTPUT_EDP:
2342	Serge	8246	has_panel = true;
4104	Serge	8247	if (enc_to_dig_port(&encoder->base)->port == PORT_A)
2342	Serge	8248	has_cpu_edp = true;
6084	serge	8249	break;
5354	serge	8250	default:
		8251	break;
2327	Serge	8252	}
6084	serge	8253	}
2342	Serge	8254
		8255	if (HAS_PCH_IBX(dev)) {
4104	Serge	8256	has_ck505 = dev_priv->vbt.display_clock_mode;
2342	Serge	8257	can_ssc = has_ck505;
		8258	} else {
		8259	has_ck505 = false;
		8260	can_ssc = true;
2327	Serge	8261	}
		8262
4104	Serge	8263	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
		8264	has_panel, has_lvds, has_ck505);
2342	Serge	8265
2327	Serge	8266	/* Ironlake: try to setup display ref clock before DPLL
		8267	* enabling. This is only under driver's control after
		8268	* PCH B stepping, previous chipset stepping should be
		8269	* ignoring this setting.
		8270	*/
3746	Serge	8271	val = I915_READ(PCH_DREF_CONTROL);
		8272
		8273	/* As we must carefully and slowly disable/enable each source in turn,
		8274	* compute the final state we want first and check if we need to
		8275	* make any changes at all.
		8276	*/
		8277	final = val;
		8278	final &= ~DREF_NONSPREAD_SOURCE_MASK;
		8279	if (has_ck505)
		8280	final \|= DREF_NONSPREAD_CK505_ENABLE;
		8281	else
		8282	final \|= DREF_NONSPREAD_SOURCE_ENABLE;
		8283
		8284	final &= ~DREF_SSC_SOURCE_MASK;
		8285	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		8286	final &= ~DREF_SSC1_ENABLE;
		8287
		8288	if (has_panel) {
		8289	final \|= DREF_SSC_SOURCE_ENABLE;
		8290
		8291	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		8292	final \|= DREF_SSC1_ENABLE;
		8293
		8294	if (has_cpu_edp) {
		8295	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		8296	final \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		8297	else
		8298	final \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		8299	} else
		8300	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		8301	} else {
		8302	final \|= DREF_SSC_SOURCE_DISABLE;
		8303	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		8304	}
		8305
		8306	if (final == val)
		8307	return;
		8308
2327	Serge	8309	/* Always enable nonspread source */
3746	Serge	8310	val &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	8311
		8312	if (has_ck505)
3746	Serge	8313	val \|= DREF_NONSPREAD_CK505_ENABLE;
2342	Serge	8314	else
3746	Serge	8315	val \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	8316
		8317	if (has_panel) {
3746	Serge	8318	val &= ~DREF_SSC_SOURCE_MASK;
		8319	val \|= DREF_SSC_SOURCE_ENABLE;
2327	Serge	8320
2342	Serge	8321	/* SSC must be turned on before enabling the CPU output */
		8322	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		8323	DRM_DEBUG_KMS("Using SSC on panel\n");
3746	Serge	8324	val \|= DREF_SSC1_ENABLE;
3031	serge	8325	} else
3746	Serge	8326	val &= ~DREF_SSC1_ENABLE;
2327	Serge	8327
2342	Serge	8328	/* Get SSC going before enabling the outputs */
3746	Serge	8329	I915_WRITE(PCH_DREF_CONTROL, val);
6084	serge	8330	POSTING_READ(PCH_DREF_CONTROL);
		8331	udelay(200);
2342	Serge	8332
3746	Serge	8333	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2327	Serge	8334
		8335	/* Enable CPU source on CPU attached eDP */
2342	Serge	8336	if (has_cpu_edp) {
		8337	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		8338	DRM_DEBUG_KMS("Using SSC on eDP\n");
3746	Serge	8339	val \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5060	serge	8340	} else
3746	Serge	8341	val \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	8342	} else
3746	Serge	8343	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	8344
3746	Serge	8345	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	8346	POSTING_READ(PCH_DREF_CONTROL);
		8347	udelay(200);
6084	serge	8348	} else {
2342	Serge	8349	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		8350
3746	Serge	8351	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2342	Serge	8352
		8353	/* Turn off CPU output */
3746	Serge	8354	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	8355
3746	Serge	8356	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	8357	POSTING_READ(PCH_DREF_CONTROL);
		8358	udelay(200);
2342	Serge	8359
		8360	/* Turn off the SSC source */
3746	Serge	8361	val &= ~DREF_SSC_SOURCE_MASK;
		8362	val \|= DREF_SSC_SOURCE_DISABLE;
2342	Serge	8363
		8364	/* Turn off SSC1 */
3746	Serge	8365	val &= ~DREF_SSC1_ENABLE;
2342	Serge	8366
3746	Serge	8367	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	8368	POSTING_READ(PCH_DREF_CONTROL);
		8369	udelay(200);
2327	Serge	8370	}
3746	Serge	8371
		8372	BUG_ON(val != final);
2327	Serge	8373	}
		8374
4104	Serge	8375	static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
3243	Serge	8376	{
4104	Serge	8377	uint32_t tmp;
3243	Serge	8378
6084	serge	8379	tmp = I915_READ(SOUTH_CHICKEN2);
		8380	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;
		8381	I915_WRITE(SOUTH_CHICKEN2, tmp);
3243	Serge	8382
6084	serge	8383	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
		8384	FDI_MPHY_IOSFSB_RESET_STATUS, 100))
		8385	DRM_ERROR("FDI mPHY reset assert timeout\n");
3243	Serge	8386
6084	serge	8387	tmp = I915_READ(SOUTH_CHICKEN2);
		8388	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		8389	I915_WRITE(SOUTH_CHICKEN2, tmp);
3243	Serge	8390
6084	serge	8391	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4104	Serge	8392	FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6084	serge	8393	DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4539	Serge	8394	}
3243	Serge	8395
4104	Serge	8396	/* WaMPhyProgramming:hsw */
		8397	static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
		8398	{
		8399	uint32_t tmp;
		8400
3243	Serge	8401	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
		8402	tmp &= ~(0xFF << 24);
		8403	tmp \|= (0x12 << 24);
		8404	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
		8405
		8406	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
		8407	tmp \|= (1 << 11);
		8408	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
		8409
		8410	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
		8411	tmp \|= (1 << 11);
		8412	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
		8413
		8414	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
		8415	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		8416	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
		8417
		8418	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
		8419	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		8420	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
		8421
6084	serge	8422	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		8423	tmp &= ~(7 << 13);
		8424	tmp \|= (5 << 13);
		8425	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
3243	Serge	8426
6084	serge	8427	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		8428	tmp &= ~(7 << 13);
		8429	tmp \|= (5 << 13);
		8430	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
3243	Serge	8431
		8432	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
		8433	tmp &= ~0xFF;
		8434	tmp \|= 0x1C;
		8435	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
		8436
		8437	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
		8438	tmp &= ~0xFF;
		8439	tmp \|= 0x1C;
		8440	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
		8441
		8442	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
		8443	tmp &= ~(0xFF << 16);
		8444	tmp \|= (0x1C << 16);
		8445	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
		8446
		8447	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
		8448	tmp &= ~(0xFF << 16);
		8449	tmp \|= (0x1C << 16);
		8450	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
		8451
6084	serge	8452	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		8453	tmp \|= (1 << 27);
		8454	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
3243	Serge	8455
6084	serge	8456	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		8457	tmp \|= (1 << 27);
		8458	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
3243	Serge	8459
6084	serge	8460	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		8461	tmp &= ~(0xF << 28);
		8462	tmp \|= (4 << 28);
		8463	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
3243	Serge	8464
6084	serge	8465	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		8466	tmp &= ~(0xF << 28);
		8467	tmp \|= (4 << 28);
		8468	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
4539	Serge	8469	}
3243	Serge	8470
4104	Serge	8471	/* Implements 3 different sequences from BSpec chapter "Display iCLK
		8472	* Programming" based on the parameters passed:
		8473	* - Sequence to enable CLKOUT_DP
		8474	* - Sequence to enable CLKOUT_DP without spread
		8475	* - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
		8476	*/
		8477	static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
		8478	bool with_fdi)
		8479	{
		8480	struct drm_i915_private *dev_priv = dev->dev_private;
		8481	uint32_t reg, tmp;
3480	Serge	8482
4104	Serge	8483	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
		8484	with_spread = true;
6084	serge	8485	if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
4104	Serge	8486	with_fdi = false;
		8487
6084	serge	8488	mutex_lock(&dev_priv->sb_lock);
4104	Serge	8489
		8490	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		8491	tmp &= ~SBI_SSCCTL_DISABLE;
		8492	tmp \|= SBI_SSCCTL_PATHALT;
		8493	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		8494
		8495	udelay(24);
		8496
		8497	if (with_spread) {
		8498	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		8499	tmp &= ~SBI_SSCCTL_PATHALT;
		8500	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		8501
		8502	if (with_fdi) {
		8503	lpt_reset_fdi_mphy(dev_priv);
		8504	lpt_program_fdi_mphy(dev_priv);
		8505	}
		8506	}
		8507
6084	serge	8508	reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
4104	Serge	8509	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		8510	tmp \|= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		8511	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		8512
6084	serge	8513	mutex_unlock(&dev_priv->sb_lock);
3243	Serge	8514	}
		8515
4104	Serge	8516	/* Sequence to disable CLKOUT_DP */
		8517	static void lpt_disable_clkout_dp(struct drm_device *dev)
		8518	{
		8519	struct drm_i915_private *dev_priv = dev->dev_private;
		8520	uint32_t reg, tmp;
		8521
6084	serge	8522	mutex_lock(&dev_priv->sb_lock);
4104	Serge	8523
6084	serge	8524	reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
4104	Serge	8525	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		8526	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		8527	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		8528
		8529	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		8530	if (!(tmp & SBI_SSCCTL_DISABLE)) {
		8531	if (!(tmp & SBI_SSCCTL_PATHALT)) {
		8532	tmp \|= SBI_SSCCTL_PATHALT;
		8533	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		8534	udelay(32);
		8535	}
		8536	tmp \|= SBI_SSCCTL_DISABLE;
		8537	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		8538	}
		8539
6084	serge	8540	mutex_unlock(&dev_priv->sb_lock);
4104	Serge	8541	}
		8542
		8543	static void lpt_init_pch_refclk(struct drm_device *dev)
		8544	{
		8545	struct intel_encoder *encoder;
		8546	bool has_vga = false;
		8547
5354	serge	8548	for_each_intel_encoder(dev, encoder) {
4104	Serge	8549	switch (encoder->type) {
		8550	case INTEL_OUTPUT_ANALOG:
		8551	has_vga = true;
		8552	break;
5354	serge	8553	default:
		8554	break;
4104	Serge	8555	}
		8556	}
		8557
		8558	if (has_vga)
		8559	lpt_enable_clkout_dp(dev, true, true);
		8560	else
		8561	lpt_disable_clkout_dp(dev);
		8562	}
		8563
3243	Serge	8564	/*
		8565	* Initialize reference clocks when the driver loads
		8566	*/
		8567	void intel_init_pch_refclk(struct drm_device *dev)
		8568	{
		8569	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		8570	ironlake_init_pch_refclk(dev);
		8571	else if (HAS_PCH_LPT(dev))
		8572	lpt_init_pch_refclk(dev);
		8573	}
		8574
6084	serge	8575	static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
2342	Serge	8576	{
6084	serge	8577	struct drm_device *dev = crtc_state->base.crtc->dev;
2342	Serge	8578	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	8579	struct drm_atomic_state *state = crtc_state->base.state;
		8580	struct drm_connector *connector;
		8581	struct drm_connector_state *connector_state;
2342	Serge	8582	struct intel_encoder *encoder;
6084	serge	8583	int num_connectors = 0, i;
2342	Serge	8584	bool is_lvds = false;
		8585
6084	serge	8586	for_each_connector_in_state(state, connector, connector_state, i) {
		8587	if (connector_state->crtc != crtc_state->base.crtc)
5354	serge	8588	continue;
		8589
6084	serge	8590	encoder = to_intel_encoder(connector_state->best_encoder);
		8591
2342	Serge	8592	switch (encoder->type) {
		8593	case INTEL_OUTPUT_LVDS:
		8594	is_lvds = true;
		8595	break;
5354	serge	8596	default:
		8597	break;
2342	Serge	8598	}
		8599	num_connectors++;
		8600	}
		8601
		8602	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4560	Serge	8603	DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
4104	Serge	8604	dev_priv->vbt.lvds_ssc_freq);
4560	Serge	8605	return dev_priv->vbt.lvds_ssc_freq;
2342	Serge	8606	}
		8607
		8608	return 120000;
		8609	}
		8610
4104	Serge	8611	static void ironlake_set_pipeconf(struct drm_crtc *crtc)
3031	serge	8612	{
		8613	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		8614	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		8615	int pipe = intel_crtc->pipe;
		8616	uint32_t val;
		8617
4104	Serge	8618	val = 0;
3031	serge	8619
6084	serge	8620	switch (intel_crtc->config->pipe_bpp) {
3031	serge	8621	case 18:
3480	Serge	8622	val \|= PIPECONF_6BPC;
3031	serge	8623	break;
		8624	case 24:
3480	Serge	8625	val \|= PIPECONF_8BPC;
3031	serge	8626	break;
		8627	case 30:
3480	Serge	8628	val \|= PIPECONF_10BPC;
3031	serge	8629	break;
		8630	case 36:
3480	Serge	8631	val \|= PIPECONF_12BPC;
3031	serge	8632	break;
		8633	default:
3243	Serge	8634	/* Case prevented by intel_choose_pipe_bpp_dither. */
		8635	BUG();
3031	serge	8636	}
		8637
6084	serge	8638	if (intel_crtc->config->dither)
3031	serge	8639	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		8640
6084	serge	8641	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3031	serge	8642	val \|= PIPECONF_INTERLACED_ILK;
		8643	else
		8644	val \|= PIPECONF_PROGRESSIVE;
		8645
6084	serge	8646	if (intel_crtc->config->limited_color_range)
3480	Serge	8647	val \|= PIPECONF_COLOR_RANGE_SELECT;
		8648
3031	serge	8649	I915_WRITE(PIPECONF(pipe), val);
		8650	POSTING_READ(PIPECONF(pipe));
		8651	}
		8652
3480	Serge	8653	/*
		8654	* Set up the pipe CSC unit.
		8655	*
		8656	* Currently only full range RGB to limited range RGB conversion
		8657	* is supported, but eventually this should handle various
		8658	* RGB<->YCbCr scenarios as well.
		8659	*/
3746	Serge	8660	static void intel_set_pipe_csc(struct drm_crtc *crtc)
3480	Serge	8661	{
		8662	struct drm_device *dev = crtc->dev;
		8663	struct drm_i915_private *dev_priv = dev->dev_private;
		8664	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		8665	int pipe = intel_crtc->pipe;
		8666	uint16_t coeff = 0x7800; /* 1.0 */
		8667
		8668	/*
		8669	* TODO: Check what kind of values actually come out of the pipe
		8670	* with these coeff/postoff values and adjust to get the best
		8671	* accuracy. Perhaps we even need to take the bpc value into
		8672	* consideration.
		8673	*/
		8674
6084	serge	8675	if (intel_crtc->config->limited_color_range)
3480	Serge	8676	coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
		8677
		8678	/*
		8679	* GY/GU and RY/RU should be the other way around according
		8680	* to BSpec, but reality doesn't agree. Just set them up in
		8681	* a way that results in the correct picture.
		8682	*/
		8683	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
		8684	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
		8685
		8686	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
		8687	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
		8688
		8689	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
		8690	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
		8691
		8692	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
		8693	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
		8694	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
		8695
		8696	if (INTEL_INFO(dev)->gen > 6) {
		8697	uint16_t postoff = 0;
		8698
6084	serge	8699	if (intel_crtc->config->limited_color_range)
4398	Serge	8700	postoff = (16 * (1 << 12) / 255) & 0x1fff;
3480	Serge	8701
		8702	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		8703	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		8704	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
		8705
		8706	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
		8707	} else {
		8708	uint32_t mode = CSC_MODE_YUV_TO_RGB;
		8709
6084	serge	8710	if (intel_crtc->config->limited_color_range)
3480	Serge	8711	mode \|= CSC_BLACK_SCREEN_OFFSET;
		8712
		8713	I915_WRITE(PIPE_CSC_MODE(pipe), mode);
		8714	}
		8715	}
		8716
4104	Serge	8717	static void haswell_set_pipeconf(struct drm_crtc *crtc)
3243	Serge	8718	{
4560	Serge	8719	struct drm_device *dev = crtc->dev;
		8720	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	8721	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4560	Serge	8722	enum pipe pipe = intel_crtc->pipe;
6084	serge	8723	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	8724	uint32_t val;
		8725
4104	Serge	8726	val = 0;
3243	Serge	8727
6084	serge	8728	if (IS_HASWELL(dev) && intel_crtc->config->dither)
3243	Serge	8729	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		8730
6084	serge	8731	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3243	Serge	8732	val \|= PIPECONF_INTERLACED_ILK;
		8733	else
		8734	val \|= PIPECONF_PROGRESSIVE;
		8735
		8736	I915_WRITE(PIPECONF(cpu_transcoder), val);
		8737	POSTING_READ(PIPECONF(cpu_transcoder));
4104	Serge	8738
		8739	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
		8740	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
4560	Serge	8741
5354	serge	8742	if (IS_BROADWELL(dev) \|\| INTEL_INFO(dev)->gen >= 9) {
4560	Serge	8743	val = 0;
		8744
6084	serge	8745	switch (intel_crtc->config->pipe_bpp) {
4560	Serge	8746	case 18:
		8747	val \|= PIPEMISC_DITHER_6_BPC;
		8748	break;
		8749	case 24:
		8750	val \|= PIPEMISC_DITHER_8_BPC;
		8751	break;
		8752	case 30:
		8753	val \|= PIPEMISC_DITHER_10_BPC;
		8754	break;
		8755	case 36:
		8756	val \|= PIPEMISC_DITHER_12_BPC;
		8757	break;
		8758	default:
		8759	/* Case prevented by pipe_config_set_bpp. */
		8760	BUG();
		8761	}
		8762
6084	serge	8763	if (intel_crtc->config->dither)
4560	Serge	8764	val \|= PIPEMISC_DITHER_ENABLE \| PIPEMISC_DITHER_TYPE_SP;
		8765
		8766	I915_WRITE(PIPEMISC(pipe), val);
		8767	}
3243	Serge	8768	}
		8769
3031	serge	8770	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6084	serge	8771	struct intel_crtc_state *crtc_state,
3031	serge	8772	intel_clock_t *clock,
		8773	bool *has_reduced_clock,
		8774	intel_clock_t *reduced_clock)
		8775	{
		8776	struct drm_device *dev = crtc->dev;
		8777	struct drm_i915_private *dev_priv = dev->dev_private;
		8778	int refclk;
		8779	const intel_limit_t *limit;
6084	serge	8780	bool ret;
3031	serge	8781
6084	serge	8782	refclk = ironlake_get_refclk(crtc_state);
3031	serge	8783
		8784	/*
		8785	* Returns a set of divisors for the desired target clock with the given
		8786	* refclk, or FALSE. The returned values represent the clock equation:
		8787	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		8788	*/
6084	serge	8789	limit = intel_limit(crtc_state, refclk);
		8790	ret = dev_priv->display.find_dpll(limit, crtc_state,
		8791	crtc_state->port_clock,
4104	Serge	8792	refclk, NULL, clock);
3031	serge	8793	if (!ret)
		8794	return false;
		8795
		8796	return true;
		8797	}
		8798
3243	Serge	8799	int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
		8800	{
		8801	/*
		8802	* Account for spread spectrum to avoid
		8803	* oversubscribing the link. Max center spread
		8804	* is 2.5%; use 5% for safety's sake.
		8805	*/
		8806	u32 bps = target_clock * bpp * 21 / 20;
5060	serge	8807	return DIV_ROUND_UP(bps, link_bw * 8);
3243	Serge	8808	}
		8809
4104	Serge	8810	static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
2327	Serge	8811	{
4104	Serge	8812	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
3746	Serge	8813	}
		8814
3243	Serge	8815	static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6084	serge	8816	struct intel_crtc_state *crtc_state,
4104	Serge	8817	u32 *fp,
3746	Serge	8818	intel_clock_t reduced_clock, u32 fp2)
3243	Serge	8819	{
		8820	struct drm_crtc *crtc = &intel_crtc->base;
		8821	struct drm_device *dev = crtc->dev;
		8822	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	8823	struct drm_atomic_state *state = crtc_state->base.state;
		8824	struct drm_connector *connector;
		8825	struct drm_connector_state *connector_state;
		8826	struct intel_encoder *encoder;
3243	Serge	8827	uint32_t dpll;
6084	serge	8828	int factor, num_connectors = 0, i;
4104	Serge	8829	bool is_lvds = false, is_sdvo = false;
3243	Serge	8830
6084	serge	8831	for_each_connector_in_state(state, connector, connector_state, i) {
		8832	if (connector_state->crtc != crtc_state->base.crtc)
5354	serge	8833	continue;
		8834
6084	serge	8835	encoder = to_intel_encoder(connector_state->best_encoder);
		8836
		8837	switch (encoder->type) {
3243	Serge	8838	case INTEL_OUTPUT_LVDS:
		8839	is_lvds = true;
		8840	break;
		8841	case INTEL_OUTPUT_SDVO:
		8842	case INTEL_OUTPUT_HDMI:
		8843	is_sdvo = true;
		8844	break;
5354	serge	8845	default:
		8846	break;
3243	Serge	8847	}
		8848
		8849	num_connectors++;
		8850	}
		8851
6084	serge	8852	/* Enable autotuning of the PLL clock (if permissible) */
		8853	factor = 21;
		8854	if (is_lvds) {
		8855	if ((intel_panel_use_ssc(dev_priv) &&
4560	Serge	8856	dev_priv->vbt.lvds_ssc_freq == 100000) \|\|
3746	Serge	8857	(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6084	serge	8858	factor = 25;
		8859	} else if (crtc_state->sdvo_tv_clock)
		8860	factor = 20;
2327	Serge	8861
6084	serge	8862	if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
3746	Serge	8863	*fp \|= FP_CB_TUNE;
2327	Serge	8864
3746	Serge	8865	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		8866	*fp2 \|= FP_CB_TUNE;
		8867
6084	serge	8868	dpll = 0;
2327	Serge	8869
6084	serge	8870	if (is_lvds)
		8871	dpll \|= DPLLB_MODE_LVDS;
		8872	else
		8873	dpll \|= DPLLB_MODE_DAC_SERIAL;
4104	Serge	8874
6084	serge	8875	dpll \|= (crtc_state->pixel_multiplier - 1)
		8876	<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2327	Serge	8877
4104	Serge	8878	if (is_sdvo)
		8879	dpll \|= DPLL_SDVO_HIGH_SPEED;
6084	serge	8880	if (crtc_state->has_dp_encoder)
4104	Serge	8881	dpll \|= DPLL_SDVO_HIGH_SPEED;
		8882
6084	serge	8883	/* compute bitmask from p1 value */
		8884	dpll \|= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		8885	/* also FPA1 */
		8886	dpll \|= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2327	Serge	8887
6084	serge	8888	switch (crtc_state->dpll.p2) {
		8889	case 5:
		8890	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		8891	break;
		8892	case 7:
		8893	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		8894	break;
		8895	case 10:
		8896	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		8897	break;
		8898	case 14:
		8899	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		8900	break;
		8901	}
2327	Serge	8902
4104	Serge	8903	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6084	serge	8904	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		8905	else
		8906	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	8907
4104	Serge	8908	return dpll \| DPLL_VCO_ENABLE;
3243	Serge	8909	}
		8910
6084	serge	8911	static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
		8912	struct intel_crtc_state *crtc_state)
3243	Serge	8913	{
5354	serge	8914	struct drm_device *dev = crtc->base.dev;
3243	Serge	8915	intel_clock_t clock, reduced_clock;
4104	Serge	8916	u32 dpll = 0, fp = 0, fp2 = 0;
3243	Serge	8917	bool ok, has_reduced_clock = false;
3746	Serge	8918	bool is_lvds = false;
4104	Serge	8919	struct intel_shared_dpll *pll;
3243	Serge	8920
6084	serge	8921	memset(&crtc_state->dpll_hw_state, 0,
		8922	sizeof(crtc_state->dpll_hw_state));
		8923
5354	serge	8924	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
3243	Serge	8925
		8926	WARN(!(HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)),
		8927	"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
		8928
6084	serge	8929	ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
3243	Serge	8930	&has_reduced_clock, &reduced_clock);
6084	serge	8931	if (!ok && !crtc_state->clock_set) {
3243	Serge	8932	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		8933	return -EINVAL;
		8934	}
3746	Serge	8935	/* Compat-code for transition, will disappear. */
6084	serge	8936	if (!crtc_state->clock_set) {
		8937	crtc_state->dpll.n = clock.n;
		8938	crtc_state->dpll.m1 = clock.m1;
		8939	crtc_state->dpll.m2 = clock.m2;
		8940	crtc_state->dpll.p1 = clock.p1;
		8941	crtc_state->dpll.p2 = clock.p2;
3746	Serge	8942	}
3243	Serge	8943
4104	Serge	8944	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6084	serge	8945	if (crtc_state->has_pch_encoder) {
		8946	fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
		8947	if (has_reduced_clock)
4104	Serge	8948	fp2 = i9xx_dpll_compute_fp(&reduced_clock);
3243	Serge	8949
6084	serge	8950	dpll = ironlake_compute_dpll(crtc, crtc_state,
4104	Serge	8951	&fp, &reduced_clock,
5060	serge	8952	has_reduced_clock ? &fp2 : NULL);
3243	Serge	8953
6084	serge	8954	crtc_state->dpll_hw_state.dpll = dpll;
		8955	crtc_state->dpll_hw_state.fp0 = fp;
4104	Serge	8956	if (has_reduced_clock)
6084	serge	8957	crtc_state->dpll_hw_state.fp1 = fp2;
4104	Serge	8958	else
6084	serge	8959	crtc_state->dpll_hw_state.fp1 = fp;
2327	Serge	8960
6084	serge	8961	pll = intel_get_shared_dpll(crtc, crtc_state);
3031	serge	8962	if (pll == NULL) {
4104	Serge	8963	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5354	serge	8964	pipe_name(crtc->pipe));
2342	Serge	8965	return -EINVAL;
6084	serge	8966	}
5354	serge	8967	}
2327	Serge	8968
6084	serge	8969	if (is_lvds && has_reduced_clock)
5354	serge	8970	crtc->lowfreq_avail = true;
4104	Serge	8971	else
5354	serge	8972	crtc->lowfreq_avail = false;
2327	Serge	8973
5060	serge	8974	return 0;
4104	Serge	8975	}
3243	Serge	8976
4560	Serge	8977	static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
		8978	struct intel_link_m_n *m_n)
4104	Serge	8979	{
		8980	struct drm_device *dev = crtc->base.dev;
		8981	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	8982	enum pipe pipe = crtc->pipe;
4104	Serge	8983
4560	Serge	8984	m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
		8985	m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
		8986	m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
		8987	& ~TU_SIZE_MASK;
		8988	m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
		8989	m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
		8990	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
		8991	}
		8992
		8993	static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
		8994	enum transcoder transcoder,
5354	serge	8995	struct intel_link_m_n *m_n,
		8996	struct intel_link_m_n *m2_n2)
4560	Serge	8997	{
		8998	struct drm_device *dev = crtc->base.dev;
		8999	struct drm_i915_private *dev_priv = dev->dev_private;
		9000	enum pipe pipe = crtc->pipe;
		9001
		9002	if (INTEL_INFO(dev)->gen >= 5) {
		9003	m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
		9004	m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
		9005	m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6084	serge	9006	& ~TU_SIZE_MASK;
4560	Serge	9007	m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
		9008	m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6084	serge	9009	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5354	serge	9010	/* Read M2_N2 registers only for gen < 8 (M2_N2 available for
		9011	* gen < 8) and if DRRS is supported (to make sure the
		9012	* registers are not unnecessarily read).
		9013	*/
		9014	if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6084	serge	9015	crtc->config->has_drrs) {
5354	serge	9016	m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
		9017	m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
		9018	m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
		9019	& ~TU_SIZE_MASK;
		9020	m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
		9021	m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
		9022	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
		9023	}
4560	Serge	9024	} else {
		9025	m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
		9026	m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
		9027	m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
		9028	& ~TU_SIZE_MASK;
		9029	m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
		9030	m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
		9031	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
		9032	}
3243	Serge	9033	}
		9034
4560	Serge	9035	void intel_dp_get_m_n(struct intel_crtc *crtc,
6084	serge	9036	struct intel_crtc_state *pipe_config)
4560	Serge	9037	{
6084	serge	9038	if (pipe_config->has_pch_encoder)
4560	Serge	9039	intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
		9040	else
		9041	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5354	serge	9042	&pipe_config->dp_m_n,
		9043	&pipe_config->dp_m2_n2);
4560	Serge	9044	}
		9045
		9046	static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6084	serge	9047	struct intel_crtc_state *pipe_config)
4560	Serge	9048	{
		9049	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5354	serge	9050	&pipe_config->fdi_m_n, NULL);
4560	Serge	9051	}
		9052
5354	serge	9053	static void skylake_get_pfit_config(struct intel_crtc *crtc,
6084	serge	9054	struct intel_crtc_state *pipe_config)
5354	serge	9055	{
		9056	struct drm_device *dev = crtc->base.dev;
		9057	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	9058	struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
		9059	uint32_t ps_ctrl = 0;
		9060	int id = -1;
		9061	int i;
5354	serge	9062
6084	serge	9063	/* find scaler attached to this pipe */
		9064	for (i = 0; i < crtc->num_scalers; i++) {
		9065	ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
		9066	if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
		9067	id = i;
		9068	pipe_config->pch_pfit.enabled = true;
		9069	pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
		9070	pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
		9071	break;
		9072	}
		9073	}
5354	serge	9074
6084	serge	9075	scaler_state->scaler_id = id;
		9076	if (id >= 0) {
		9077	scaler_state->scaler_users \|= (1 << SKL_CRTC_INDEX);
		9078	} else {
		9079	scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
5354	serge	9080	}
		9081	}
		9082
6084	serge	9083	static void
		9084	skylake_get_initial_plane_config(struct intel_crtc *crtc,
		9085	struct intel_initial_plane_config *plane_config)
		9086	{
		9087	struct drm_device *dev = crtc->base.dev;
		9088	struct drm_i915_private *dev_priv = dev->dev_private;
		9089	u32 val, base, offset, stride_mult, tiling;
		9090	int pipe = crtc->pipe;
		9091	int fourcc, pixel_format;
		9092	unsigned int aligned_height;
		9093	struct drm_framebuffer *fb;
		9094	struct intel_framebuffer *intel_fb;
		9095
		9096	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		9097	if (!intel_fb) {
		9098	DRM_DEBUG_KMS("failed to alloc fb\n");
		9099	return;
		9100	}
		9101
		9102	fb = &intel_fb->base;
		9103
		9104	val = I915_READ(PLANE_CTL(pipe, 0));
		9105	if (!(val & PLANE_CTL_ENABLE))
		9106	goto error;
		9107
		9108	pixel_format = val & PLANE_CTL_FORMAT_MASK;
		9109	fourcc = skl_format_to_fourcc(pixel_format,
		9110	val & PLANE_CTL_ORDER_RGBX,
		9111	val & PLANE_CTL_ALPHA_MASK);
		9112	fb->pixel_format = fourcc;
		9113	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
		9114
		9115	tiling = val & PLANE_CTL_TILED_MASK;
		9116	switch (tiling) {
		9117	case PLANE_CTL_TILED_LINEAR:
		9118	fb->modifier[0] = DRM_FORMAT_MOD_NONE;
		9119	break;
		9120	case PLANE_CTL_TILED_X:
		9121	plane_config->tiling = I915_TILING_X;
		9122	fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
		9123	break;
		9124	case PLANE_CTL_TILED_Y:
		9125	fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
		9126	break;
		9127	case PLANE_CTL_TILED_YF:
		9128	fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
		9129	break;
		9130	default:
		9131	MISSING_CASE(tiling);
		9132	goto error;
		9133	}
		9134
		9135	base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
		9136	plane_config->base = base;
		9137
		9138	offset = I915_READ(PLANE_OFFSET(pipe, 0));
		9139
		9140	val = I915_READ(PLANE_SIZE(pipe, 0));
		9141	fb->height = ((val >> 16) & 0xfff) + 1;
		9142	fb->width = ((val >> 0) & 0x1fff) + 1;
		9143
		9144	val = I915_READ(PLANE_STRIDE(pipe, 0));
		9145	stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
		9146	fb->pixel_format);
6283	serge	9147	fb->pitches[0] = (val & 0x3ff) * stride_mult;
6084	serge	9148
		9149	aligned_height = intel_fb_align_height(dev, fb->height,
		9150	fb->pixel_format,
		9151	fb->modifier[0]);
		9152
6283	serge	9153	plane_config->size = fb->pitches[0] * aligned_height;
6084	serge	9154
		9155	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
		9156	pipe_name(pipe), fb->width, fb->height,
		9157	fb->bits_per_pixel, base, fb->pitches[0],
		9158	plane_config->size);
		9159
		9160	plane_config->fb = intel_fb;
		9161	return;
		9162
		9163	error:
		9164	kfree(fb);
		9165	}
		9166
4104	Serge	9167	static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6084	serge	9168	struct intel_crtc_state *pipe_config)
4104	Serge	9169	{
		9170	struct drm_device *dev = crtc->base.dev;
		9171	struct drm_i915_private *dev_priv = dev->dev_private;
		9172	uint32_t tmp;
		9173
		9174	tmp = I915_READ(PF_CTL(crtc->pipe));
		9175
		9176	if (tmp & PF_ENABLE) {
		9177	pipe_config->pch_pfit.enabled = true;
		9178	pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
		9179	pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
		9180
		9181	/* We currently do not free assignements of panel fitters on
		9182	* ivb/hsw (since we don't use the higher upscaling modes which
		9183	* differentiates them) so just WARN about this case for now. */
		9184	if (IS_GEN7(dev)) {
		9185	WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
		9186	PF_PIPE_SEL_IVB(crtc->pipe));
		9187	}
		9188	}
		9189	}
		9190
6084	serge	9191	static void
		9192	ironlake_get_initial_plane_config(struct intel_crtc *crtc,
		9193	struct intel_initial_plane_config *plane_config)
5060	serge	9194	{
		9195	struct drm_device *dev = crtc->base.dev;
		9196	struct drm_i915_private *dev_priv = dev->dev_private;
		9197	u32 val, base, offset;
6084	serge	9198	int pipe = crtc->pipe;
5060	serge	9199	int fourcc, pixel_format;
6084	serge	9200	unsigned int aligned_height;
		9201	struct drm_framebuffer *fb;
		9202	struct intel_framebuffer *intel_fb;
5060	serge	9203
6084	serge	9204	val = I915_READ(DSPCNTR(pipe));
		9205	if (!(val & DISPLAY_PLANE_ENABLE))
		9206	return;
		9207
		9208	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		9209	if (!intel_fb) {
5060	serge	9210	DRM_DEBUG_KMS("failed to alloc fb\n");
		9211	return;
		9212	}
		9213
6084	serge	9214	fb = &intel_fb->base;
5060	serge	9215
6084	serge	9216	if (INTEL_INFO(dev)->gen >= 4) {
		9217	if (val & DISPPLANE_TILED) {
		9218	plane_config->tiling = I915_TILING_X;
		9219	fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
		9220	}
		9221	}
5060	serge	9222
		9223	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6084	serge	9224	fourcc = i9xx_format_to_fourcc(pixel_format);
		9225	fb->pixel_format = fourcc;
		9226	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
5060	serge	9227
6084	serge	9228	base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
5060	serge	9229	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
6084	serge	9230	offset = I915_READ(DSPOFFSET(pipe));
5060	serge	9231	} else {
6084	serge	9232	if (plane_config->tiling)
		9233	offset = I915_READ(DSPTILEOFF(pipe));
5060	serge	9234	else
6084	serge	9235	offset = I915_READ(DSPLINOFF(pipe));
5060	serge	9236	}
		9237	plane_config->base = base;
		9238
		9239	val = I915_READ(PIPESRC(pipe));
6084	serge	9240	fb->width = ((val >> 16) & 0xfff) + 1;
		9241	fb->height = ((val >> 0) & 0xfff) + 1;
5060	serge	9242
		9243	val = I915_READ(DSPSTRIDE(pipe));
6283	serge	9244	fb->pitches[0] = val & 0xffffffc0;
5060	serge	9245
6084	serge	9246	aligned_height = intel_fb_align_height(dev, fb->height,
		9247	fb->pixel_format,
		9248	fb->modifier[0]);
5060	serge	9249
6283	serge	9250	plane_config->size = fb->pitches[0] * aligned_height;
5060	serge	9251
6084	serge	9252	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
		9253	pipe_name(pipe), fb->width, fb->height,
		9254	fb->bits_per_pixel, base, fb->pitches[0],
5060	serge	9255	plane_config->size);
6084	serge	9256
		9257	plane_config->fb = intel_fb;
5060	serge	9258	}
		9259
3746	Serge	9260	static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6084	serge	9261	struct intel_crtc_state *pipe_config)
3746	Serge	9262	{
		9263	struct drm_device *dev = crtc->base.dev;
		9264	struct drm_i915_private *dev_priv = dev->dev_private;
		9265	uint32_t tmp;
		9266
5354	serge	9267	if (!intel_display_power_is_enabled(dev_priv,
6084	serge	9268	POWER_DOMAIN_PIPE(crtc->pipe)))
5060	serge	9269	return false;
		9270
4104	Serge	9271	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		9272	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		9273
3746	Serge	9274	tmp = I915_READ(PIPECONF(crtc->pipe));
		9275	if (!(tmp & PIPECONF_ENABLE))
		9276	return false;
		9277
4280	Serge	9278	switch (tmp & PIPECONF_BPC_MASK) {
		9279	case PIPECONF_6BPC:
		9280	pipe_config->pipe_bpp = 18;
		9281	break;
		9282	case PIPECONF_8BPC:
		9283	pipe_config->pipe_bpp = 24;
		9284	break;
		9285	case PIPECONF_10BPC:
		9286	pipe_config->pipe_bpp = 30;
		9287	break;
		9288	case PIPECONF_12BPC:
		9289	pipe_config->pipe_bpp = 36;
		9290	break;
		9291	default:
		9292	break;
		9293	}
		9294
5060	serge	9295	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
		9296	pipe_config->limited_color_range = true;
		9297
4104	Serge	9298	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
		9299	struct intel_shared_dpll *pll;
		9300
3746	Serge	9301	pipe_config->has_pch_encoder = true;
		9302
4104	Serge	9303	tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
		9304	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		9305	FDI_DP_PORT_WIDTH_SHIFT) + 1;
		9306
		9307	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		9308
		9309	if (HAS_PCH_IBX(dev_priv->dev)) {
		9310	pipe_config->shared_dpll =
		9311	(enum intel_dpll_id) crtc->pipe;
		9312	} else {
		9313	tmp = I915_READ(PCH_DPLL_SEL);
		9314	if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
		9315	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
		9316	else
		9317	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
		9318	}
		9319
		9320	pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
		9321
		9322	WARN_ON(!pll->get_hw_state(dev_priv, pll,
		9323	&pipe_config->dpll_hw_state));
		9324
		9325	tmp = pipe_config->dpll_hw_state.dpll;
		9326	pipe_config->pixel_multiplier =
		9327	((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
		9328	>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
4560	Serge	9329
		9330	ironlake_pch_clock_get(crtc, pipe_config);
4104	Serge	9331	} else {
		9332	pipe_config->pixel_multiplier = 1;
		9333	}
		9334
		9335	intel_get_pipe_timings(crtc, pipe_config);
		9336
		9337	ironlake_get_pfit_config(crtc, pipe_config);
		9338
3746	Serge	9339	return true;
		9340	}
		9341
4104	Serge	9342	static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
		9343	{
		9344	struct drm_device *dev = dev_priv->dev;
		9345	struct intel_crtc *crtc;
		9346
5060	serge	9347	for_each_intel_crtc(dev, crtc)
6084	serge	9348	I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
4104	Serge	9349	pipe_name(crtc->pipe));
		9350
6084	serge	9351	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
		9352	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
		9353	I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
		9354	I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
		9355	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
		9356	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
4104	Serge	9357	"CPU PWM1 enabled\n");
5060	serge	9358	if (IS_HASWELL(dev))
6084	serge	9359	I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
		9360	"CPU PWM2 enabled\n");
		9361	I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
4104	Serge	9362	"PCH PWM1 enabled\n");
6084	serge	9363	I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
4104	Serge	9364	"Utility pin enabled\n");
6084	serge	9365	I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
4104	Serge	9366
5060	serge	9367	/*
		9368	* In theory we can still leave IRQs enabled, as long as only the HPD
		9369	* interrupts remain enabled. We used to check for that, but since it's
		9370	* gen-specific and since we only disable LCPLL after we fully disable
		9371	* the interrupts, the check below should be enough.
		9372	*/
6084	serge	9373	I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
4104	Serge	9374	}
		9375
5060	serge	9376	static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
		9377	{
		9378	struct drm_device *dev = dev_priv->dev;
		9379
		9380	if (IS_HASWELL(dev))
		9381	return I915_READ(D_COMP_HSW);
		9382	else
		9383	return I915_READ(D_COMP_BDW);
		9384	}
		9385
		9386	static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
		9387	{
		9388	struct drm_device *dev = dev_priv->dev;
		9389
		9390	if (IS_HASWELL(dev)) {
		9391	mutex_lock(&dev_priv->rps.hw_lock);
		9392	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
		9393	val))
		9394	DRM_ERROR("Failed to write to D_COMP\n");
		9395	mutex_unlock(&dev_priv->rps.hw_lock);
		9396	} else {
		9397	I915_WRITE(D_COMP_BDW, val);
		9398	POSTING_READ(D_COMP_BDW);
		9399	}
		9400	}
		9401
4104	Serge	9402	/*
		9403	* This function implements pieces of two sequences from BSpec:
		9404	* - Sequence for display software to disable LCPLL
		9405	* - Sequence for display software to allow package C8+
		9406	* The steps implemented here are just the steps that actually touch the LCPLL
		9407	* register. Callers should take care of disabling all the display engine
		9408	* functions, doing the mode unset, fixing interrupts, etc.
		9409	*/
4560	Serge	9410	static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6084	serge	9411	bool switch_to_fclk, bool allow_power_down)
4104	Serge	9412	{
		9413	uint32_t val;
		9414
		9415	assert_can_disable_lcpll(dev_priv);
		9416
		9417	val = I915_READ(LCPLL_CTL);
		9418
		9419	if (switch_to_fclk) {
		9420	val \|= LCPLL_CD_SOURCE_FCLK;
		9421	I915_WRITE(LCPLL_CTL, val);
		9422
		9423	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
		9424	LCPLL_CD_SOURCE_FCLK_DONE, 1))
		9425	DRM_ERROR("Switching to FCLK failed\n");
		9426
		9427	val = I915_READ(LCPLL_CTL);
		9428	}
		9429
		9430	val \|= LCPLL_PLL_DISABLE;
		9431	I915_WRITE(LCPLL_CTL, val);
		9432	POSTING_READ(LCPLL_CTL);
		9433
		9434	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
		9435	DRM_ERROR("LCPLL still locked\n");
		9436
5060	serge	9437	val = hsw_read_dcomp(dev_priv);
4104	Serge	9438	val \|= D_COMP_COMP_DISABLE;
5060	serge	9439	hsw_write_dcomp(dev_priv, val);
		9440	ndelay(100);
4104	Serge	9441
5060	serge	9442	if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
		9443	1))
4104	Serge	9444	DRM_ERROR("D_COMP RCOMP still in progress\n");
		9445
		9446	if (allow_power_down) {
		9447	val = I915_READ(LCPLL_CTL);
		9448	val \|= LCPLL_POWER_DOWN_ALLOW;
		9449	I915_WRITE(LCPLL_CTL, val);
		9450	POSTING_READ(LCPLL_CTL);
		9451	}
		9452	}
		9453
		9454	/*
		9455	* Fully restores LCPLL, disallowing power down and switching back to LCPLL
		9456	* source.
		9457	*/
4560	Serge	9458	static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
4104	Serge	9459	{
		9460	uint32_t val;
		9461
		9462	val = I915_READ(LCPLL_CTL);
		9463
		9464	if ((val & (LCPLL_PLL_LOCK \| LCPLL_PLL_DISABLE \| LCPLL_CD_SOURCE_FCLK \|
		9465	LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
		9466	return;
		9467
5060	serge	9468	/*
		9469	* Make sure we're not on PC8 state before disabling PC8, otherwise
		9470	* we'll hang the machine. To prevent PC8 state, just enable force_wake.
		9471	*/
6084	serge	9472	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4104	Serge	9473
		9474	if (val & LCPLL_POWER_DOWN_ALLOW) {
		9475	val &= ~LCPLL_POWER_DOWN_ALLOW;
		9476	I915_WRITE(LCPLL_CTL, val);
		9477	POSTING_READ(LCPLL_CTL);
		9478	}
		9479
5060	serge	9480	val = hsw_read_dcomp(dev_priv);
4104	Serge	9481	val \|= D_COMP_COMP_FORCE;
		9482	val &= ~D_COMP_COMP_DISABLE;
5060	serge	9483	hsw_write_dcomp(dev_priv, val);
4104	Serge	9484
		9485	val = I915_READ(LCPLL_CTL);
		9486	val &= ~LCPLL_PLL_DISABLE;
		9487	I915_WRITE(LCPLL_CTL, val);
		9488
		9489	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
		9490	DRM_ERROR("LCPLL not locked yet\n");
		9491
		9492	if (val & LCPLL_CD_SOURCE_FCLK) {
		9493	val = I915_READ(LCPLL_CTL);
		9494	val &= ~LCPLL_CD_SOURCE_FCLK;
		9495	I915_WRITE(LCPLL_CTL, val);
		9496
		9497	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
		9498	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
		9499	DRM_ERROR("Switching back to LCPLL failed\n");
		9500	}
		9501
6084	serge	9502	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
		9503	intel_update_cdclk(dev_priv->dev);
4104	Serge	9504	}
		9505
5060	serge	9506	/*
		9507	* Package states C8 and deeper are really deep PC states that can only be
		9508	* reached when all the devices on the system allow it, so even if the graphics
		9509	* device allows PC8+, it doesn't mean the system will actually get to these
		9510	* states. Our driver only allows PC8+ when going into runtime PM.
		9511	*
		9512	* The requirements for PC8+ are that all the outputs are disabled, the power
		9513	* well is disabled and most interrupts are disabled, and these are also
		9514	* requirements for runtime PM. When these conditions are met, we manually do
		9515	* the other conditions: disable the interrupts, clocks and switch LCPLL refclk
		9516	* to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
		9517	* hang the machine.
		9518	*
		9519	* When we really reach PC8 or deeper states (not just when we allow it) we lose
		9520	* the state of some registers, so when we come back from PC8+ we need to
		9521	* restore this state. We don't get into PC8+ if we're not in RC6, so we don't
		9522	* need to take care of the registers kept by RC6. Notice that this happens even
		9523	* if we don't put the device in PCI D3 state (which is what currently happens
		9524	* because of the runtime PM support).
		9525	*
		9526	* For more, read "Display Sequences for Package C8" on the hardware
		9527	* documentation.
		9528	*/
		9529	void hsw_enable_pc8(struct drm_i915_private *dev_priv)
4104	Serge	9530	{
		9531	struct drm_device *dev = dev_priv->dev;
		9532	uint32_t val;
		9533
		9534	DRM_DEBUG_KMS("Enabling package C8+\n");
		9535
6084	serge	9536	if (HAS_PCH_LPT_LP(dev)) {
4104	Serge	9537	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		9538	val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
		9539	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		9540	}
		9541
		9542	lpt_disable_clkout_dp(dev);
		9543	hsw_disable_lcpll(dev_priv, true, true);
		9544	}
		9545
5060	serge	9546	void hsw_disable_pc8(struct drm_i915_private *dev_priv)
4104	Serge	9547	{
		9548	struct drm_device *dev = dev_priv->dev;
		9549	uint32_t val;
		9550
		9551	DRM_DEBUG_KMS("Disabling package C8+\n");
		9552
		9553	hsw_restore_lcpll(dev_priv);
		9554	lpt_init_pch_refclk(dev);
		9555
6084	serge	9556	if (HAS_PCH_LPT_LP(dev)) {
4104	Serge	9557	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		9558	val \|= PCH_LP_PARTITION_LEVEL_DISABLE;
		9559	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		9560	}
		9561
		9562	intel_prepare_ddi(dev);
		9563	}
		9564
6084	serge	9565	static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
4104	Serge	9566	{
6084	serge	9567	struct drm_device *dev = old_state->dev;
		9568	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
		9569
		9570	broxton_set_cdclk(dev, req_cdclk);
		9571	}
		9572
		9573	/* compute the max rate for new configuration */
		9574	static int ilk_max_pixel_rate(struct drm_atomic_state *state)
		9575	{
		9576	struct intel_crtc *intel_crtc;
		9577	struct intel_crtc_state *crtc_state;
		9578	int max_pixel_rate = 0;
		9579
		9580	for_each_intel_crtc(state->dev, intel_crtc) {
		9581	int pixel_rate;
		9582
		9583	crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
		9584	if (IS_ERR(crtc_state))
		9585	return PTR_ERR(crtc_state);
		9586
		9587	if (!crtc_state->base.enable)
		9588	continue;
		9589
		9590	pixel_rate = ilk_pipe_pixel_rate(crtc_state);
		9591
		9592	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
		9593	if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
		9594	pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
		9595
		9596	max_pixel_rate = max(max_pixel_rate, pixel_rate);
		9597	}
		9598
		9599	return max_pixel_rate;
		9600	}
		9601
		9602	static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
		9603	{
		9604	struct drm_i915_private *dev_priv = dev->dev_private;
		9605	uint32_t val, data;
		9606	int ret;
		9607
		9608	if (WARN((I915_READ(LCPLL_CTL) &
		9609	(LCPLL_PLL_DISABLE \| LCPLL_PLL_LOCK \|
		9610	LCPLL_CD_CLOCK_DISABLE \| LCPLL_ROOT_CD_CLOCK_DISABLE \|
		9611	LCPLL_CD2X_CLOCK_DISABLE \| LCPLL_POWER_DOWN_ALLOW \|
		9612	LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
		9613	"trying to change cdclk frequency with cdclk not enabled\n"))
		9614	return;
		9615
		9616	mutex_lock(&dev_priv->rps.hw_lock);
		9617	ret = sandybridge_pcode_write(dev_priv,
		9618	BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
		9619	mutex_unlock(&dev_priv->rps.hw_lock);
		9620	if (ret) {
		9621	DRM_ERROR("failed to inform pcode about cdclk change\n");
		9622	return;
		9623	}
		9624
		9625	val = I915_READ(LCPLL_CTL);
		9626	val \|= LCPLL_CD_SOURCE_FCLK;
		9627	I915_WRITE(LCPLL_CTL, val);
		9628
		9629	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
		9630	LCPLL_CD_SOURCE_FCLK_DONE, 1))
		9631	DRM_ERROR("Switching to FCLK failed\n");
		9632
		9633	val = I915_READ(LCPLL_CTL);
		9634	val &= ~LCPLL_CLK_FREQ_MASK;
		9635
		9636	switch (cdclk) {
		9637	case 450000:
		9638	val \|= LCPLL_CLK_FREQ_450;
		9639	data = 0;
		9640	break;
		9641	case 540000:
		9642	val \|= LCPLL_CLK_FREQ_54O_BDW;
		9643	data = 1;
		9644	break;
		9645	case 337500:
		9646	val \|= LCPLL_CLK_FREQ_337_5_BDW;
		9647	data = 2;
		9648	break;
		9649	case 675000:
		9650	val \|= LCPLL_CLK_FREQ_675_BDW;
		9651	data = 3;
		9652	break;
		9653	default:
		9654	WARN(1, "invalid cdclk frequency\n");
		9655	return;
		9656	}
		9657
		9658	I915_WRITE(LCPLL_CTL, val);
		9659
		9660	val = I915_READ(LCPLL_CTL);
		9661	val &= ~LCPLL_CD_SOURCE_FCLK;
		9662	I915_WRITE(LCPLL_CTL, val);
		9663
		9664	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
		9665	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
		9666	DRM_ERROR("Switching back to LCPLL failed\n");
		9667
		9668	mutex_lock(&dev_priv->rps.hw_lock);
		9669	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
		9670	mutex_unlock(&dev_priv->rps.hw_lock);
		9671
		9672	intel_update_cdclk(dev);
		9673
		9674	WARN(cdclk != dev_priv->cdclk_freq,
		9675	"cdclk requested %d kHz but got %d kHz\n",
		9676	cdclk, dev_priv->cdclk_freq);
		9677	}
		9678
		9679	static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
		9680	{
		9681	struct drm_i915_private *dev_priv = to_i915(state->dev);
		9682	int max_pixclk = ilk_max_pixel_rate(state);
		9683	int cdclk;
		9684
		9685	/*
		9686	* FIXME should also account for plane ratio
		9687	* once 64bpp pixel formats are supported.
		9688	*/
		9689	if (max_pixclk > 540000)
		9690	cdclk = 675000;
		9691	else if (max_pixclk > 450000)
		9692	cdclk = 540000;
		9693	else if (max_pixclk > 337500)
		9694	cdclk = 450000;
		9695	else
		9696	cdclk = 337500;
		9697
		9698	/*
		9699	* FIXME move the cdclk caclulation to
		9700	* compute_config() so we can fail gracegully.
		9701	*/
		9702	if (cdclk > dev_priv->max_cdclk_freq) {
		9703	DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
		9704	cdclk, dev_priv->max_cdclk_freq);
		9705	cdclk = dev_priv->max_cdclk_freq;
		9706	}
		9707
		9708	to_intel_atomic_state(state)->cdclk = cdclk;
		9709
		9710	return 0;
		9711	}
		9712
		9713	static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
		9714	{
		9715	struct drm_device *dev = old_state->dev;
		9716	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
		9717
		9718	broadwell_set_cdclk(dev, req_cdclk);
		9719	}
		9720
		9721	static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
		9722	struct intel_crtc_state *crtc_state)
		9723	{
		9724	if (!intel_ddi_pll_select(crtc, crtc_state))
5354	serge	9725	return -EINVAL;
		9726
		9727	crtc->lowfreq_avail = false;
		9728
		9729	return 0;
4104	Serge	9730	}
		9731
6084	serge	9732	static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
		9733	enum port port,
		9734	struct intel_crtc_state *pipe_config)
		9735	{
		9736	switch (port) {
		9737	case PORT_A:
		9738	pipe_config->ddi_pll_sel = SKL_DPLL0;
		9739	pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
		9740	break;
		9741	case PORT_B:
		9742	pipe_config->ddi_pll_sel = SKL_DPLL1;
		9743	pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
		9744	break;
		9745	case PORT_C:
		9746	pipe_config->ddi_pll_sel = SKL_DPLL2;
		9747	pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
		9748	break;
		9749	default:
		9750	DRM_ERROR("Incorrect port type\n");
		9751	}
		9752	}
		9753
5354	serge	9754	static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
		9755	enum port port,
6084	serge	9756	struct intel_crtc_state *pipe_config)
4104	Serge	9757	{
6084	serge	9758	u32 temp, dpll_ctl1;
5354	serge	9759
		9760	temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
		9761	pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
		9762
		9763	switch (pipe_config->ddi_pll_sel) {
6084	serge	9764	case SKL_DPLL0:
		9765	/*
		9766	* On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
		9767	* of the shared DPLL framework and thus needs to be read out
		9768	* separately
		9769	*/
		9770	dpll_ctl1 = I915_READ(DPLL_CTRL1);
		9771	pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
		9772	break;
5354	serge	9773	case SKL_DPLL1:
		9774	pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
		9775	break;
		9776	case SKL_DPLL2:
		9777	pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
		9778	break;
		9779	case SKL_DPLL3:
		9780	pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
		9781	break;
		9782	}
4104	Serge	9783	}
		9784
5354	serge	9785	static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
		9786	enum port port,
6084	serge	9787	struct intel_crtc_state *pipe_config)
4104	Serge	9788	{
5354	serge	9789	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
4104	Serge	9790
5354	serge	9791	switch (pipe_config->ddi_pll_sel) {
		9792	case PORT_CLK_SEL_WRPLL1:
		9793	pipe_config->shared_dpll = DPLL_ID_WRPLL1;
		9794	break;
		9795	case PORT_CLK_SEL_WRPLL2:
		9796	pipe_config->shared_dpll = DPLL_ID_WRPLL2;
		9797	break;
6084	serge	9798	case PORT_CLK_SEL_SPLL:
		9799	pipe_config->shared_dpll = DPLL_ID_SPLL;
5354	serge	9800	}
4104	Serge	9801	}
		9802
5060	serge	9803	static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
6084	serge	9804	struct intel_crtc_state *pipe_config)
4104	Serge	9805	{
5060	serge	9806	struct drm_device *dev = crtc->base.dev;
4104	Serge	9807	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	9808	struct intel_shared_dpll *pll;
		9809	enum port port;
		9810	uint32_t tmp;
4104	Serge	9811
5060	serge	9812	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
4560	Serge	9813
5060	serge	9814	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
4104	Serge	9815
5354	serge	9816	if (IS_SKYLAKE(dev))
		9817	skylake_get_ddi_pll(dev_priv, port, pipe_config);
6084	serge	9818	else if (IS_BROXTON(dev))
		9819	bxt_get_ddi_pll(dev_priv, port, pipe_config);
5354	serge	9820	else
		9821	haswell_get_ddi_pll(dev_priv, port, pipe_config);
4104	Serge	9822
5060	serge	9823	if (pipe_config->shared_dpll >= 0) {
		9824	pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
4560	Serge	9825
5060	serge	9826	WARN_ON(!pll->get_hw_state(dev_priv, pll,
		9827	&pipe_config->dpll_hw_state));
4104	Serge	9828	}
		9829
4560	Serge	9830	/*
5060	serge	9831	* Haswell has only FDI/PCH transcoder A. It is which is connected to
		9832	* DDI E. So just check whether this pipe is wired to DDI E and whether
		9833	* the PCH transcoder is on.
4560	Serge	9834	*/
5354	serge	9835	if (INTEL_INFO(dev)->gen < 9 &&
		9836	(port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5060	serge	9837	pipe_config->has_pch_encoder = true;
4560	Serge	9838
5060	serge	9839	tmp = I915_READ(FDI_RX_CTL(PIPE_A));
		9840	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		9841	FDI_DP_PORT_WIDTH_SHIFT) + 1;
3480	Serge	9842
5060	serge	9843	ironlake_get_fdi_m_n_config(crtc, pipe_config);
3480	Serge	9844	}
4560	Serge	9845	}
		9846
3746	Serge	9847	static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6084	serge	9848	struct intel_crtc_state *pipe_config)
3746	Serge	9849	{
		9850	struct drm_device *dev = crtc->base.dev;
		9851	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	9852	enum intel_display_power_domain pfit_domain;
3746	Serge	9853	uint32_t tmp;
		9854
5354	serge	9855	if (!intel_display_power_is_enabled(dev_priv,
5060	serge	9856	POWER_DOMAIN_PIPE(crtc->pipe)))
		9857	return false;
		9858
4104	Serge	9859	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		9860	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		9861
		9862	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
		9863	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		9864	enum pipe trans_edp_pipe;
		9865	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		9866	default:
		9867	WARN(1, "unknown pipe linked to edp transcoder\n");
		9868	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		9869	case TRANS_DDI_EDP_INPUT_A_ON:
		9870	trans_edp_pipe = PIPE_A;
		9871	break;
		9872	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		9873	trans_edp_pipe = PIPE_B;
		9874	break;
		9875	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		9876	trans_edp_pipe = PIPE_C;
		9877	break;
		9878	}
		9879
		9880	if (trans_edp_pipe == crtc->pipe)
		9881	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		9882	}
		9883
5354	serge	9884	if (!intel_display_power_is_enabled(dev_priv,
4104	Serge	9885	POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
		9886	return false;
		9887
		9888	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
3746	Serge	9889	if (!(tmp & PIPECONF_ENABLE))
		9890	return false;
		9891
5060	serge	9892	haswell_get_ddi_port_state(crtc, pipe_config);
3746	Serge	9893
4104	Serge	9894	intel_get_pipe_timings(crtc, pipe_config);
		9895
6084	serge	9896	if (INTEL_INFO(dev)->gen >= 9) {
		9897	skl_init_scalers(dev, crtc, pipe_config);
		9898	}
		9899
4104	Serge	9900	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6084	serge	9901
		9902	if (INTEL_INFO(dev)->gen >= 9) {
		9903	pipe_config->scaler_state.scaler_id = -1;
		9904	pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
		9905	}
		9906
5354	serge	9907	if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
6084	serge	9908	if (INTEL_INFO(dev)->gen >= 9)
5354	serge	9909	skylake_get_pfit_config(crtc, pipe_config);
		9910	else
6084	serge	9911	ironlake_get_pfit_config(crtc, pipe_config);
5354	serge	9912	}
4104	Serge	9913
4560	Serge	9914	if (IS_HASWELL(dev))
6084	serge	9915	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
		9916	(I915_READ(IPS_CTL) & IPS_ENABLE);
4104	Serge	9917
5354	serge	9918	if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
		9919	pipe_config->pixel_multiplier =
		9920	I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
		9921	} else {
6084	serge	9922	pipe_config->pixel_multiplier = 1;
4560	Serge	9923	}
		9924
2342	Serge	9925	return true;
		9926	}
		9927
6084	serge	9928	static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
2342	Serge	9929	{
5354	serge	9930	struct drm_device *dev = crtc->dev;
		9931	struct drm_i915_private *dev_priv = dev->dev_private;
		9932	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		9933	uint32_t cntl = 0, size = 0;
2342	Serge	9934
6084	serge	9935	if (on) {
		9936	unsigned int width = intel_crtc->base.cursor->state->crtc_w;
		9937	unsigned int height = intel_crtc->base.cursor->state->crtc_h;
5354	serge	9938	unsigned int stride = roundup_pow_of_two(width) * 4;
2342	Serge	9939
5354	serge	9940	switch (stride) {
		9941	default:
		9942	WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
		9943	width, stride);
		9944	stride = 256;
		9945	/* fallthrough */
		9946	case 256:
		9947	case 512:
		9948	case 1024:
		9949	case 2048:
		9950	break;
6084	serge	9951	}
3031	serge	9952
5354	serge	9953	cntl \|= CURSOR_ENABLE \|
		9954	CURSOR_GAMMA_ENABLE \|
		9955	CURSOR_FORMAT_ARGB \|
		9956	CURSOR_STRIDE(stride);
3031	serge	9957
5354	serge	9958	size = (height << 12) \| width;
2342	Serge	9959	}
		9960
5354	serge	9961	if (intel_crtc->cursor_cntl != 0 &&
		9962	(intel_crtc->cursor_base != base \|\|
		9963	intel_crtc->cursor_size != size \|\|
		9964	intel_crtc->cursor_cntl != cntl)) {
		9965	/* On these chipsets we can only modify the base/size/stride
		9966	* whilst the cursor is disabled.
3031	serge	9967	*/
6084	serge	9968	I915_WRITE(CURCNTR(PIPE_A), 0);
		9969	POSTING_READ(CURCNTR(PIPE_A));
		9970	intel_crtc->cursor_cntl = 0;
		9971	}
5060	serge	9972
5354	serge	9973	if (intel_crtc->cursor_base != base) {
6084	serge	9974	I915_WRITE(CURBASE(PIPE_A), base);
5354	serge	9975	intel_crtc->cursor_base = base;
5060	serge	9976	}
2327	Serge	9977
5354	serge	9978	if (intel_crtc->cursor_size != size) {
		9979	I915_WRITE(CURSIZE, size);
		9980	intel_crtc->cursor_size = size;
		9981	}
		9982
5060	serge	9983	if (intel_crtc->cursor_cntl != cntl) {
6084	serge	9984	I915_WRITE(CURCNTR(PIPE_A), cntl);
		9985	POSTING_READ(CURCNTR(PIPE_A));
5060	serge	9986	intel_crtc->cursor_cntl = cntl;
		9987	}
3031	serge	9988	}
2327	Serge	9989
6084	serge	9990	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
3031	serge	9991	{
		9992	struct drm_device *dev = crtc->dev;
		9993	struct drm_i915_private *dev_priv = dev->dev_private;
		9994	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		9995	int pipe = intel_crtc->pipe;
6084	serge	9996	uint32_t cntl = 0;
2327	Serge	9997
6084	serge	9998	if (on) {
5060	serge	9999	cntl = MCURSOR_GAMMA_ENABLE;
6084	serge	10000	switch (intel_crtc->base.cursor->state->crtc_w) {
5060	serge	10001	case 64:
		10002	cntl \|= CURSOR_MODE_64_ARGB_AX;
		10003	break;
		10004	case 128:
		10005	cntl \|= CURSOR_MODE_128_ARGB_AX;
		10006	break;
		10007	case 256:
		10008	cntl \|= CURSOR_MODE_256_ARGB_AX;
		10009	break;
		10010	default:
6084	serge	10011	MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
5060	serge	10012	return;
6084	serge	10013	}
		10014	cntl \|= pipe << 28; /* Connect to correct pipe */
2327	Serge	10015
6084	serge	10016	if (HAS_DDI(dev))
3480	Serge	10017	cntl \|= CURSOR_PIPE_CSC_ENABLE;
5354	serge	10018	}
5060	serge	10019
6084	serge	10020	if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
5354	serge	10021	cntl \|= CURSOR_ROTATE_180;
		10022
5060	serge	10023	if (intel_crtc->cursor_cntl != cntl) {
		10024	I915_WRITE(CURCNTR(pipe), cntl);
		10025	POSTING_READ(CURCNTR(pipe));
		10026	intel_crtc->cursor_cntl = cntl;
6084	serge	10027	}
2327	Serge	10028
3031	serge	10029	/* and commit changes on next vblank */
5060	serge	10030	I915_WRITE(CURBASE(pipe), base);
		10031	POSTING_READ(CURBASE(pipe));
5354	serge	10032
		10033	intel_crtc->cursor_base = base;
3031	serge	10034	}
2327	Serge	10035
3031	serge	10036	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5060	serge	10037	void intel_crtc_update_cursor(struct drm_crtc *crtc,
3031	serge	10038	bool on)
		10039	{
		10040	struct drm_device *dev = crtc->dev;
		10041	struct drm_i915_private *dev_priv = dev->dev_private;
		10042	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		10043	int pipe = intel_crtc->pipe;
6084	serge	10044	struct drm_plane_state *cursor_state = crtc->cursor->state;
		10045	int x = cursor_state->crtc_x;
		10046	int y = cursor_state->crtc_y;
4560	Serge	10047	u32 base = 0, pos = 0;
2327	Serge	10048
6084	serge	10049	base = intel_crtc->cursor_addr;
2327	Serge	10050
6084	serge	10051	if (x >= intel_crtc->config->pipe_src_w)
		10052	on = false;
2327	Serge	10053
6084	serge	10054	if (y >= intel_crtc->config->pipe_src_h)
		10055	on = false;
2327	Serge	10056
3031	serge	10057	if (x < 0) {
6084	serge	10058	if (x + cursor_state->crtc_w <= 0)
		10059	on = false;
2327	Serge	10060
3031	serge	10061	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		10062	x = -x;
		10063	}
		10064	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	10065
3031	serge	10066	if (y < 0) {
6084	serge	10067	if (y + cursor_state->crtc_h <= 0)
		10068	on = false;
2327	Serge	10069
3031	serge	10070	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		10071	y = -y;
		10072	}
		10073	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	10074
5060	serge	10075	I915_WRITE(CURPOS(pipe), pos);
		10076
5354	serge	10077	/* ILK+ do this automagically */
		10078	if (HAS_GMCH_DISPLAY(dev) &&
6084	serge	10079	crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
		10080	base += (cursor_state->crtc_h *
		10081	cursor_state->crtc_w - 1) * 4;
5354	serge	10082	}
		10083
		10084	if (IS_845G(dev) \|\| IS_I865G(dev))
6084	serge	10085	i845_update_cursor(crtc, base, on);
5060	serge	10086	else
6084	serge	10087	i9xx_update_cursor(crtc, base, on);
3031	serge	10088	}
2327	Serge	10089
5354	serge	10090	static bool cursor_size_ok(struct drm_device *dev,
		10091	uint32_t width, uint32_t height)
		10092	{
		10093	if (width == 0 \|\| height == 0)
		10094	return false;
		10095
		10096	/*
		10097	* 845g/865g are special in that they are only limited by
		10098	* the width of their cursors, the height is arbitrary up to
		10099	* the precision of the register. Everything else requires
		10100	* square cursors, limited to a few power-of-two sizes.
6084	serge	10101	*/
5354	serge	10102	if (IS_845G(dev) \|\| IS_I865G(dev)) {
		10103	if ((width & 63) != 0)
		10104	return false;
		10105
		10106	if (width > (IS_845G(dev) ? 64 : 512))
		10107	return false;
		10108
		10109	if (height > 1023)
		10110	return false;
		10111	} else {
		10112	switch (width \| height) {
		10113	case 256:
		10114	case 128:
		10115	if (IS_GEN2(dev))
		10116	return false;
		10117	case 64:
		10118	break;
		10119	default:
		10120	return false;
		10121	}
		10122	}
		10123
		10124	return true;
		10125	}
		10126
2330	Serge	10127	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		10128	u16 *blue, uint32_t start, uint32_t size)
		10129	{
		10130	int end = (start + size > 256) ? 256 : start + size, i;
		10131	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	10132
2330	Serge	10133	for (i = start; i < end; i++) {
		10134	intel_crtc->lut_r[i] = red[i] >> 8;
		10135	intel_crtc->lut_g[i] = green[i] >> 8;
		10136	intel_crtc->lut_b[i] = blue[i] >> 8;
		10137	}
2327	Serge	10138
2330	Serge	10139	intel_crtc_load_lut(crtc);
		10140	}
2327	Serge	10141
2330	Serge	10142	/* VESA 640x480x72Hz mode to set on the pipe */
		10143	static struct drm_display_mode load_detect_mode = {
		10144	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		10145	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		10146	};
2327	Serge	10147
4560	Serge	10148	struct drm_framebuffer *
5060	serge	10149	__intel_framebuffer_create(struct drm_device *dev,
6084	serge	10150	struct drm_mode_fb_cmd2 *mode_cmd,
		10151	struct drm_i915_gem_object *obj)
3031	serge	10152	{
		10153	struct intel_framebuffer *intel_fb;
		10154	int ret;
2327	Serge	10155
3031	serge	10156	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		10157	if (!intel_fb) {
5354	serge	10158	drm_gem_object_unreference(&obj->base);
3031	serge	10159	return ERR_PTR(-ENOMEM);
		10160	}
2327	Serge	10161
3031	serge	10162	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
4560	Serge	10163	if (ret)
		10164	goto err;
		10165
		10166	return &intel_fb->base;
		10167	err:
5354	serge	10168	drm_gem_object_unreference(&obj->base);
6084	serge	10169	kfree(intel_fb);
4560	Serge	10170
6084	serge	10171	return ERR_PTR(ret);
3031	serge	10172	}
2327	Serge	10173
5060	serge	10174	static struct drm_framebuffer *
		10175	intel_framebuffer_create(struct drm_device *dev,
		10176	struct drm_mode_fb_cmd2 *mode_cmd,
		10177	struct drm_i915_gem_object *obj)
		10178	{
		10179	struct drm_framebuffer *fb;
		10180	int ret;
		10181
		10182	ret = i915_mutex_lock_interruptible(dev);
		10183	if (ret)
		10184	return ERR_PTR(ret);
		10185	fb = __intel_framebuffer_create(dev, mode_cmd, obj);
		10186	mutex_unlock(&dev->struct_mutex);
		10187
		10188	return fb;
		10189	}
		10190
2330	Serge	10191	static u32
		10192	intel_framebuffer_pitch_for_width(int width, int bpp)
		10193	{
		10194	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		10195	return ALIGN(pitch, 64);
		10196	}
2327	Serge	10197
2330	Serge	10198	static u32
		10199	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		10200	{
		10201	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5060	serge	10202	return PAGE_ALIGN(pitch * mode->vdisplay);
2330	Serge	10203	}
2327	Serge	10204
2330	Serge	10205	static struct drm_framebuffer *
		10206	intel_framebuffer_create_for_mode(struct drm_device *dev,
		10207	struct drm_display_mode *mode,
		10208	int depth, int bpp)
		10209	{
		10210	struct drm_i915_gem_object *obj;
3243	Serge	10211	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327	Serge	10212
5060	serge	10213	obj = i915_gem_alloc_object(dev,
		10214	intel_framebuffer_size_for_mode(mode, bpp));
		10215	if (obj == NULL)
		10216	return ERR_PTR(-ENOMEM);
		10217
		10218	mode_cmd.width = mode->hdisplay;
		10219	mode_cmd.height = mode->vdisplay;
		10220	mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
		10221	bpp);
		10222	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
		10223
		10224	return intel_framebuffer_create(dev, &mode_cmd, obj);
2330	Serge	10225	}
2327	Serge	10226
2330	Serge	10227	static struct drm_framebuffer *
		10228	mode_fits_in_fbdev(struct drm_device *dev,
		10229	struct drm_display_mode *mode)
		10230	{
6084	serge	10231	#ifdef CONFIG_DRM_FBDEV_EMULATION
2330	Serge	10232	struct drm_i915_private *dev_priv = dev->dev_private;
		10233	struct drm_i915_gem_object *obj;
		10234	struct drm_framebuffer *fb;
2327	Serge	10235
5060	serge	10236	if (!dev_priv->fbdev)
4280	Serge	10237	return NULL;
2327	Serge	10238
5060	serge	10239	if (!dev_priv->fbdev->fb)
2330	Serge	10240	return NULL;
2327	Serge	10241
5060	serge	10242	obj = dev_priv->fbdev->fb->obj;
		10243	BUG_ON(!obj);
		10244
		10245	fb = &dev_priv->fbdev->fb->base;
3031	serge	10246	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		10247	fb->bits_per_pixel))
4280	Serge	10248	return NULL;
2327	Serge	10249
3031	serge	10250	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		10251	return NULL;
		10252
4280	Serge	10253	return fb;
4560	Serge	10254	#else
		10255	return NULL;
		10256	#endif
2330	Serge	10257	}
2327	Serge	10258
6084	serge	10259	static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
		10260	struct drm_crtc *crtc,
		10261	struct drm_display_mode *mode,
		10262	struct drm_framebuffer *fb,
		10263	int x, int y)
		10264	{
		10265	struct drm_plane_state *plane_state;
		10266	int hdisplay, vdisplay;
		10267	int ret;
		10268
		10269	plane_state = drm_atomic_get_plane_state(state, crtc->primary);
		10270	if (IS_ERR(plane_state))
		10271	return PTR_ERR(plane_state);
		10272
		10273	if (mode)
		10274	drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
		10275	else
		10276	hdisplay = vdisplay = 0;
		10277
		10278	ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
		10279	if (ret)
		10280	return ret;
		10281	drm_atomic_set_fb_for_plane(plane_state, fb);
		10282	plane_state->crtc_x = 0;
		10283	plane_state->crtc_y = 0;
		10284	plane_state->crtc_w = hdisplay;
		10285	plane_state->crtc_h = vdisplay;
		10286	plane_state->src_x = x << 16;
		10287	plane_state->src_y = y << 16;
		10288	plane_state->src_w = hdisplay << 16;
		10289	plane_state->src_h = vdisplay << 16;
		10290
		10291	return 0;
		10292	}
		10293
3031	serge	10294	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	10295	struct drm_display_mode *mode,
5060	serge	10296	struct intel_load_detect_pipe *old,
		10297	struct drm_modeset_acquire_ctx *ctx)
2330	Serge	10298	{
		10299	struct intel_crtc *intel_crtc;
3031	serge	10300	struct intel_encoder *intel_encoder =
		10301	intel_attached_encoder(connector);
2330	Serge	10302	struct drm_crtc *possible_crtc;
		10303	struct drm_encoder *encoder = &intel_encoder->base;
		10304	struct drm_crtc *crtc = NULL;
		10305	struct drm_device *dev = encoder->dev;
3031	serge	10306	struct drm_framebuffer *fb;
5060	serge	10307	struct drm_mode_config *config = &dev->mode_config;
6084	serge	10308	struct drm_atomic_state *state = NULL;
		10309	struct drm_connector_state *connector_state;
		10310	struct intel_crtc_state *crtc_state;
5060	serge	10311	int ret, i = -1;
2327	Serge	10312
2330	Serge	10313	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5060	serge	10314	connector->base.id, connector->name,
		10315	encoder->base.id, encoder->name);
2327	Serge	10316
5060	serge	10317	retry:
		10318	ret = drm_modeset_lock(&config->connection_mutex, ctx);
		10319	if (ret)
6084	serge	10320	goto fail;
5060	serge	10321
2330	Serge	10322	/*
		10323	* Algorithm gets a little messy:
		10324	*
		10325	* - if the connector already has an assigned crtc, use it (but make
		10326	* sure it's on first)
		10327	*
		10328	* - try to find the first unused crtc that can drive this connector,
		10329	* and use that if we find one
		10330	*/
2327	Serge	10331
2330	Serge	10332	/* See if we already have a CRTC for this connector */
		10333	if (encoder->crtc) {
		10334	crtc = encoder->crtc;
2327	Serge	10335
5060	serge	10336	ret = drm_modeset_lock(&crtc->mutex, ctx);
		10337	if (ret)
6084	serge	10338	goto fail;
5354	serge	10339	ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
		10340	if (ret)
6084	serge	10341	goto fail;
3480	Serge	10342
3031	serge	10343	old->dpms_mode = connector->dpms;
2330	Serge	10344	old->load_detect_temp = false;
2327	Serge	10345
2330	Serge	10346	/* Make sure the crtc and connector are running */
3031	serge	10347	if (connector->dpms != DRM_MODE_DPMS_ON)
		10348	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	10349
2330	Serge	10350	return true;
		10351	}
2327	Serge	10352
2330	Serge	10353	/* Find an unused one (if possible) */
5060	serge	10354	for_each_crtc(dev, possible_crtc) {
2330	Serge	10355	i++;
		10356	if (!(encoder->possible_crtcs & (1 << i)))
		10357	continue;
6084	serge	10358	if (possible_crtc->state->enable)
5060	serge	10359	continue;
		10360
6084	serge	10361	crtc = possible_crtc;
		10362	break;
		10363	}
2327	Serge	10364
2330	Serge	10365	/*
		10366	* If we didn't find an unused CRTC, don't use any.
		10367	*/
		10368	if (!crtc) {
		10369	DRM_DEBUG_KMS("no pipe available for load-detect\n");
6084	serge	10370	goto fail;
2330	Serge	10371	}
2327	Serge	10372
5060	serge	10373	ret = drm_modeset_lock(&crtc->mutex, ctx);
		10374	if (ret)
6084	serge	10375	goto fail;
5354	serge	10376	ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
		10377	if (ret)
6084	serge	10378	goto fail;
2327	Serge	10379
2330	Serge	10380	intel_crtc = to_intel_crtc(crtc);
3031	serge	10381	old->dpms_mode = connector->dpms;
2330	Serge	10382	old->load_detect_temp = true;
		10383	old->release_fb = NULL;
2327	Serge	10384
6084	serge	10385	state = drm_atomic_state_alloc(dev);
		10386	if (!state)
		10387	return false;
		10388
		10389	state->acquire_ctx = ctx;
		10390
		10391	connector_state = drm_atomic_get_connector_state(state, connector);
		10392	if (IS_ERR(connector_state)) {
		10393	ret = PTR_ERR(connector_state);
		10394	goto fail;
		10395	}
		10396
		10397	connector_state->crtc = crtc;
		10398	connector_state->best_encoder = &intel_encoder->base;
		10399
		10400	crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
		10401	if (IS_ERR(crtc_state)) {
		10402	ret = PTR_ERR(crtc_state);
		10403	goto fail;
		10404	}
		10405
		10406	crtc_state->base.active = crtc_state->base.enable = true;
		10407
2330	Serge	10408	if (!mode)
		10409	mode = &load_detect_mode;
2327	Serge	10410
2330	Serge	10411	/* We need a framebuffer large enough to accommodate all accesses
		10412	* that the plane may generate whilst we perform load detection.
		10413	* We can not rely on the fbcon either being present (we get called
		10414	* during its initialisation to detect all boot displays, or it may
		10415	* not even exist) or that it is large enough to satisfy the
		10416	* requested mode.
		10417	*/
3031	serge	10418	fb = mode_fits_in_fbdev(dev, mode);
		10419	if (fb == NULL) {
2330	Serge	10420	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	10421	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		10422	old->release_fb = fb;
2330	Serge	10423	} else
		10424	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	10425	if (IS_ERR(fb)) {
2330	Serge	10426	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5060	serge	10427	goto fail;
2330	Serge	10428	}
2327	Serge	10429
6084	serge	10430	ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
		10431	if (ret)
		10432	goto fail;
		10433
		10434	drm_mode_copy(&crtc_state->base.mode, mode);
		10435
		10436	if (drm_atomic_commit(state)) {
2330	Serge	10437	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		10438	if (old->release_fb)
		10439	old->release_fb->funcs->destroy(old->release_fb);
5060	serge	10440	goto fail;
2330	Serge	10441	}
6084	serge	10442	crtc->primary->crtc = crtc;
2327	Serge	10443
2330	Serge	10444	/* let the connector get through one full cycle before testing */
		10445	intel_wait_for_vblank(dev, intel_crtc->pipe);
		10446	return true;
5060	serge	10447
6084	serge	10448	fail:
		10449	drm_atomic_state_free(state);
		10450	state = NULL;
		10451
5060	serge	10452	if (ret == -EDEADLK) {
		10453	drm_modeset_backoff(ctx);
		10454	goto retry;
		10455	}
		10456
		10457	return false;
2330	Serge	10458	}
2327	Serge	10459
3031	serge	10460	void intel_release_load_detect_pipe(struct drm_connector *connector,
6084	serge	10461	struct intel_load_detect_pipe *old,
		10462	struct drm_modeset_acquire_ctx *ctx)
2330	Serge	10463	{
6084	serge	10464	struct drm_device *dev = connector->dev;
3031	serge	10465	struct intel_encoder *intel_encoder =
		10466	intel_attached_encoder(connector);
2330	Serge	10467	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	10468	struct drm_crtc *crtc = encoder->crtc;
5060	serge	10469	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084	serge	10470	struct drm_atomic_state *state;
		10471	struct drm_connector_state *connector_state;
		10472	struct intel_crtc_state *crtc_state;
		10473	int ret;
2327	Serge	10474
2330	Serge	10475	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5060	serge	10476	connector->base.id, connector->name,
		10477	encoder->base.id, encoder->name);
2327	Serge	10478
2330	Serge	10479	if (old->load_detect_temp) {
6084	serge	10480	state = drm_atomic_state_alloc(dev);
		10481	if (!state)
		10482	goto fail;
3031	serge	10483
6084	serge	10484	state->acquire_ctx = ctx;
		10485
		10486	connector_state = drm_atomic_get_connector_state(state, connector);
		10487	if (IS_ERR(connector_state))
		10488	goto fail;
		10489
		10490	crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
		10491	if (IS_ERR(crtc_state))
		10492	goto fail;
		10493
		10494	connector_state->best_encoder = NULL;
		10495	connector_state->crtc = NULL;
		10496
		10497	crtc_state->base.enable = crtc_state->base.active = false;
		10498
		10499	ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
		10500	0, 0);
		10501	if (ret)
		10502	goto fail;
		10503
		10504	ret = drm_atomic_commit(state);
		10505	if (ret)
		10506	goto fail;
		10507
3480	Serge	10508	if (old->release_fb) {
		10509	drm_framebuffer_unregister_private(old->release_fb);
		10510	drm_framebuffer_unreference(old->release_fb);
		10511	}
2327	Serge	10512
2330	Serge	10513	return;
		10514	}
2327	Serge	10515
2330	Serge	10516	/* Switch crtc and encoder back off if necessary */
3031	serge	10517	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		10518	connector->funcs->dpms(connector, old->dpms_mode);
6084	serge	10519
		10520	return;
		10521	fail:
		10522	DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
		10523	drm_atomic_state_free(state);
2330	Serge	10524	}
2327	Serge	10525
4560	Serge	10526	static int i9xx_pll_refclk(struct drm_device *dev,
6084	serge	10527	const struct intel_crtc_state *pipe_config)
4560	Serge	10528	{
		10529	struct drm_i915_private *dev_priv = dev->dev_private;
		10530	u32 dpll = pipe_config->dpll_hw_state.dpll;
		10531
		10532	if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
		10533	return dev_priv->vbt.lvds_ssc_freq;
		10534	else if (HAS_PCH_SPLIT(dev))
		10535	return 120000;
		10536	else if (!IS_GEN2(dev))
		10537	return 96000;
		10538	else
		10539	return 48000;
		10540	}
		10541
2330	Serge	10542	/* Returns the clock of the currently programmed mode of the given pipe. */
4104	Serge	10543	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6084	serge	10544	struct intel_crtc_state *pipe_config)
2330	Serge	10545	{
4104	Serge	10546	struct drm_device *dev = crtc->base.dev;
2330	Serge	10547	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	10548	int pipe = pipe_config->cpu_transcoder;
4560	Serge	10549	u32 dpll = pipe_config->dpll_hw_state.dpll;
2330	Serge	10550	u32 fp;
		10551	intel_clock_t clock;
6084	serge	10552	int port_clock;
4560	Serge	10553	int refclk = i9xx_pll_refclk(dev, pipe_config);
2327	Serge	10554
2330	Serge	10555	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4560	Serge	10556	fp = pipe_config->dpll_hw_state.fp0;
2330	Serge	10557	else
4560	Serge	10558	fp = pipe_config->dpll_hw_state.fp1;
2327	Serge	10559
2330	Serge	10560	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		10561	if (IS_PINEVIEW(dev)) {
		10562	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		10563	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		10564	} else {
		10565	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		10566	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		10567	}
2327	Serge	10568
2330	Serge	10569	if (!IS_GEN2(dev)) {
		10570	if (IS_PINEVIEW(dev))
		10571	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		10572	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		10573	else
		10574	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		10575	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	10576
2330	Serge	10577	switch (dpll & DPLL_MODE_MASK) {
		10578	case DPLLB_MODE_DAC_SERIAL:
		10579	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		10580	5 : 10;
		10581	break;
		10582	case DPLLB_MODE_LVDS:
		10583	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		10584	7 : 14;
		10585	break;
		10586	default:
		10587	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		10588	"mode\n", (int)(dpll & DPLL_MODE_MASK));
4104	Serge	10589	return;
2330	Serge	10590	}
2327	Serge	10591
4104	Serge	10592	if (IS_PINEVIEW(dev))
6084	serge	10593	port_clock = pnv_calc_dpll_params(refclk, &clock);
4104	Serge	10594	else
6084	serge	10595	port_clock = i9xx_calc_dpll_params(refclk, &clock);
2330	Serge	10596	} else {
4560	Serge	10597	u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
		10598	bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
2327	Serge	10599
2330	Serge	10600	if (is_lvds) {
		10601	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		10602	DPLL_FPA01_P1_POST_DIV_SHIFT);
4560	Serge	10603
		10604	if (lvds & LVDS_CLKB_POWER_UP)
		10605	clock.p2 = 7;
		10606	else
6084	serge	10607	clock.p2 = 14;
2330	Serge	10608	} else {
		10609	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		10610	clock.p1 = 2;
		10611	else {
		10612	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		10613	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		10614	}
		10615	if (dpll & PLL_P2_DIVIDE_BY_4)
		10616	clock.p2 = 4;
		10617	else
		10618	clock.p2 = 2;
4560	Serge	10619	}
2327	Serge	10620
6084	serge	10621	port_clock = i9xx_calc_dpll_params(refclk, &clock);
2330	Serge	10622	}
2327	Serge	10623
4560	Serge	10624	/*
		10625	* This value includes pixel_multiplier. We will use
		10626	* port_clock to compute adjusted_mode.crtc_clock in the
		10627	* encoder's get_config() function.
		10628	*/
6084	serge	10629	pipe_config->port_clock = port_clock;
4104	Serge	10630	}
		10631
4560	Serge	10632	int intel_dotclock_calculate(int link_freq,
		10633	const struct intel_link_m_n *m_n)
4104	Serge	10634	{
		10635	/*
		10636	* The calculation for the data clock is:
4560	Serge	10637	* pixel_clock = ((m/n)(link_clock nr_lanes))/bpp
4104	Serge	10638	* But we want to avoid losing precison if possible, so:
4560	Serge	10639	* pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4104	Serge	10640	*
		10641	* and the link clock is simpler:
4560	Serge	10642	* link_clock = (m * link_clock) / n
2330	Serge	10643	*/
2327	Serge	10644
4560	Serge	10645	if (!m_n->link_n)
		10646	return 0;
4104	Serge	10647
4560	Serge	10648	return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
		10649	}
4104	Serge	10650
4560	Serge	10651	static void ironlake_pch_clock_get(struct intel_crtc *crtc,
6084	serge	10652	struct intel_crtc_state *pipe_config)
4560	Serge	10653	{
		10654	struct drm_device *dev = crtc->base.dev;
4104	Serge	10655
4560	Serge	10656	/* read out port_clock from the DPLL */
		10657	i9xx_crtc_clock_get(crtc, pipe_config);
4104	Serge	10658
4560	Serge	10659	/*
		10660	* This value does not include pixel_multiplier.
		10661	* We will check that port_clock and adjusted_mode.crtc_clock
		10662	* agree once we know their relationship in the encoder's
		10663	* get_config() function.
		10664	*/
6084	serge	10665	pipe_config->base.adjusted_mode.crtc_clock =
4560	Serge	10666	intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
		10667	&pipe_config->fdi_m_n);
2330	Serge	10668	}
2327	Serge	10669
2330	Serge	10670	/** Returns the currently programmed mode of the given pipe. */
		10671	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		10672	struct drm_crtc *crtc)
		10673	{
		10674	struct drm_i915_private *dev_priv = dev->dev_private;
		10675	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084	serge	10676	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2330	Serge	10677	struct drm_display_mode *mode;
6084	serge	10678	struct intel_crtc_state pipe_config;
3243	Serge	10679	int htot = I915_READ(HTOTAL(cpu_transcoder));
		10680	int hsync = I915_READ(HSYNC(cpu_transcoder));
		10681	int vtot = I915_READ(VTOTAL(cpu_transcoder));
		10682	int vsync = I915_READ(VSYNC(cpu_transcoder));
4560	Serge	10683	enum pipe pipe = intel_crtc->pipe;
2327	Serge	10684
2330	Serge	10685	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		10686	if (!mode)
		10687	return NULL;
		10688
4104	Serge	10689	/*
		10690	* Construct a pipe_config sufficient for getting the clock info
		10691	* back out of crtc_clock_get.
		10692	*
		10693	* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
		10694	* to use a real value here instead.
		10695	*/
4560	Serge	10696	pipe_config.cpu_transcoder = (enum transcoder) pipe;
4104	Serge	10697	pipe_config.pixel_multiplier = 1;
4560	Serge	10698	pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
		10699	pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
		10700	pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
4104	Serge	10701	i9xx_crtc_clock_get(intel_crtc, &pipe_config);
		10702
4560	Serge	10703	mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
2330	Serge	10704	mode->hdisplay = (htot & 0xffff) + 1;
		10705	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		10706	mode->hsync_start = (hsync & 0xffff) + 1;
		10707	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		10708	mode->vdisplay = (vtot & 0xffff) + 1;
		10709	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		10710	mode->vsync_start = (vsync & 0xffff) + 1;
		10711	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		10712
		10713	drm_mode_set_name(mode);
		10714
		10715	return mode;
		10716	}
		10717
3031	serge	10718	void intel_mark_busy(struct drm_device *dev)
		10719	{
4104	Serge	10720	struct drm_i915_private *dev_priv = dev->dev_private;
		10721
5060	serge	10722	if (dev_priv->mm.busy)
		10723	return;
		10724
		10725	intel_runtime_pm_get(dev_priv);
4104	Serge	10726	i915_update_gfx_val(dev_priv);
6084	serge	10727	if (INTEL_INFO(dev)->gen >= 6)
		10728	gen6_rps_busy(dev_priv);
5060	serge	10729	dev_priv->mm.busy = true;
3031	serge	10730	}
2327	Serge	10731
3031	serge	10732	void intel_mark_idle(struct drm_device *dev)
		10733	{
4104	Serge	10734	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	10735
5060	serge	10736	if (!dev_priv->mm.busy)
3031	serge	10737	return;
2327	Serge	10738
5060	serge	10739	dev_priv->mm.busy = false;
		10740
		10741	if (INTEL_INFO(dev)->gen >= 6)
4560	Serge	10742	gen6_rps_idle(dev->dev_private);
5060	serge	10743
		10744	intel_runtime_pm_put(dev_priv);
3031	serge	10745	}
2327	Serge	10746
2330	Serge	10747	static void intel_crtc_destroy(struct drm_crtc *crtc)
		10748	{
		10749	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		10750	struct drm_device *dev = crtc->dev;
		10751	struct intel_unpin_work *work;
2327	Serge	10752
5354	serge	10753	spin_lock_irq(&dev->event_lock);
2330	Serge	10754	work = intel_crtc->unpin_work;
		10755	intel_crtc->unpin_work = NULL;
5354	serge	10756	spin_unlock_irq(&dev->event_lock);
2327	Serge	10757
2330	Serge	10758	if (work) {
4293	Serge	10759	cancel_work_sync(&work->work);
2330	Serge	10760	kfree(work);
		10761	}
2327	Serge	10762
2330	Serge	10763	drm_crtc_cleanup(crtc);
2327	Serge	10764
2330	Serge	10765	kfree(intel_crtc);
		10766	}
2327	Serge	10767
3031	serge	10768	static void intel_unpin_work_fn(struct work_struct *__work)
		10769	{
		10770	struct intel_unpin_work *work =
		10771	container_of(__work, struct intel_unpin_work, work);
6084	serge	10772	struct intel_crtc *crtc = to_intel_crtc(work->crtc);
		10773	struct drm_device *dev = crtc->base.dev;
		10774	struct drm_plane *primary = crtc->base.primary;
2327	Serge	10775
3243	Serge	10776	mutex_lock(&dev->struct_mutex);
6084	serge	10777	intel_unpin_fb_obj(work->old_fb, primary->state);
3031	serge	10778	drm_gem_object_unreference(&work->pending_flip_obj->base);
2327	Serge	10779
6084	serge	10780	if (work->flip_queued_req)
		10781	i915_gem_request_assign(&work->flip_queued_req, NULL);
3243	Serge	10782	mutex_unlock(&dev->struct_mutex);
		10783
6084	serge	10784	intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
		10785	drm_framebuffer_unreference(work->old_fb);
5354	serge	10786
6084	serge	10787	BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
		10788	atomic_dec(&crtc->unpin_work_count);
3243	Serge	10789
3031	serge	10790	kfree(work);
		10791	}
2327	Serge	10792
3031	serge	10793	static void do_intel_finish_page_flip(struct drm_device *dev,
		10794	struct drm_crtc *crtc)
		10795	{
		10796	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		10797	struct intel_unpin_work *work;
		10798	unsigned long flags;
2327	Serge	10799
3031	serge	10800	/* Ignore early vblank irqs */
		10801	if (intel_crtc == NULL)
		10802	return;
2327	Serge	10803
5354	serge	10804	/*
		10805	* This is called both by irq handlers and the reset code (to complete
		10806	* lost pageflips) so needs the full irqsave spinlocks.
		10807	*/
3031	serge	10808	spin_lock_irqsave(&dev->event_lock, flags);
		10809	work = intel_crtc->unpin_work;
3243	Serge	10810
		10811	/* Ensure we don't miss a work->pending update ... */
		10812	smp_rmb();
		10813
		10814	if (work == NULL \|\| atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
3031	serge	10815	spin_unlock_irqrestore(&dev->event_lock, flags);
		10816	return;
		10817	}
2327	Serge	10818
5354	serge	10819	page_flip_completed(intel_crtc);
3243	Serge	10820
3031	serge	10821	spin_unlock_irqrestore(&dev->event_lock, flags);
		10822	}
2327	Serge	10823
3031	serge	10824	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		10825	{
5060	serge	10826	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10827	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	10828
3031	serge	10829	do_intel_finish_page_flip(dev, crtc);
		10830	}
2327	Serge	10831
3031	serge	10832	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		10833	{
5060	serge	10834	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10835	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	10836
3031	serge	10837	do_intel_finish_page_flip(dev, crtc);
		10838	}
2327	Serge	10839
5060	serge	10840	/* Is 'a' after or equal to 'b'? */
		10841	static bool g4x_flip_count_after_eq(u32 a, u32 b)
		10842	{
		10843	return !((a - b) & 0x80000000);
		10844	}
		10845
		10846	static bool page_flip_finished(struct intel_crtc *crtc)
		10847	{
		10848	struct drm_device *dev = crtc->base.dev;
		10849	struct drm_i915_private *dev_priv = dev->dev_private;
		10850
5354	serge	10851	if (i915_reset_in_progress(&dev_priv->gpu_error) \|\|
		10852	crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
		10853	return true;
		10854
5060	serge	10855	/*
		10856	* The relevant registers doen't exist on pre-ctg.
		10857	* As the flip done interrupt doesn't trigger for mmio
		10858	* flips on gmch platforms, a flip count check isn't
		10859	* really needed there. But since ctg has the registers,
		10860	* include it in the check anyway.
		10861	*/
		10862	if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
		10863	return true;
		10864
		10865	/*
		10866	* A DSPSURFLIVE check isn't enough in case the mmio and CS flips
		10867	* used the same base address. In that case the mmio flip might
		10868	* have completed, but the CS hasn't even executed the flip yet.
		10869	*
		10870	* A flip count check isn't enough as the CS might have updated
		10871	* the base address just after start of vblank, but before we
		10872	* managed to process the interrupt. This means we'd complete the
		10873	* CS flip too soon.
		10874	*
		10875	* Combining both checks should get us a good enough result. It may
		10876	* still happen that the CS flip has been executed, but has not
		10877	* yet actually completed. But in case the base address is the same
		10878	* anyway, we don't really care.
		10879	*/
		10880	return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
		10881	crtc->unpin_work->gtt_offset &&
6084	serge	10882	g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
5060	serge	10883	crtc->unpin_work->flip_count);
		10884	}
		10885
3031	serge	10886	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		10887	{
5060	serge	10888	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10889	struct intel_crtc *intel_crtc =
		10890	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		10891	unsigned long flags;
2327	Serge	10892
5354	serge	10893
		10894	/*
		10895	* This is called both by irq handlers and the reset code (to complete
		10896	* lost pageflips) so needs the full irqsave spinlocks.
		10897	*
		10898	* NB: An MMIO update of the plane base pointer will also
3243	Serge	10899	* generate a page-flip completion irq, i.e. every modeset
		10900	* is also accompanied by a spurious intel_prepare_page_flip().
		10901	*/
3031	serge	10902	spin_lock_irqsave(&dev->event_lock, flags);
5060	serge	10903	if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
3243	Serge	10904	atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
3031	serge	10905	spin_unlock_irqrestore(&dev->event_lock, flags);
		10906	}
2327	Serge	10907
6084	serge	10908	static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
3243	Serge	10909	{
		10910	/* Ensure that the work item is consistent when activating it ... */
		10911	smp_wmb();
6084	serge	10912	atomic_set(&work->pending, INTEL_FLIP_PENDING);
3243	Serge	10913	/* and that it is marked active as soon as the irq could fire. */
		10914	smp_wmb();
		10915	}
6320	serge	10916
3031	serge	10917	static int intel_gen2_queue_flip(struct drm_device *dev,
		10918	struct drm_crtc *crtc,
		10919	struct drm_framebuffer *fb,
4104	Serge	10920	struct drm_i915_gem_object *obj,
6084	serge	10921	struct drm_i915_gem_request *req,
4104	Serge	10922	uint32_t flags)
3031	serge	10923	{
6084	serge	10924	struct intel_engine_cs *ring = req->ring;
3031	serge	10925	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		10926	u32 flip_mask;
		10927	int ret;
2327	Serge	10928
6084	serge	10929	ret = intel_ring_begin(req, 6);
3031	serge	10930	if (ret)
5060	serge	10931	return ret;
2327	Serge	10932
3031	serge	10933	/* Can't queue multiple flips, so wait for the previous
		10934	* one to finish before executing the next.
		10935	*/
		10936	if (intel_crtc->plane)
		10937	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		10938	else
		10939	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		10940	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		10941	intel_ring_emit(ring, MI_NOOP);
		10942	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		10943	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		10944	intel_ring_emit(ring, fb->pitches[0]);
5060	serge	10945	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031	serge	10946	intel_ring_emit(ring, 0); /* aux display base address, unused */
3243	Serge	10947
6084	serge	10948	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031	serge	10949	return 0;
		10950	}
2327	Serge	10951
3031	serge	10952	static int intel_gen3_queue_flip(struct drm_device *dev,
		10953	struct drm_crtc *crtc,
		10954	struct drm_framebuffer *fb,
4104	Serge	10955	struct drm_i915_gem_object *obj,
6084	serge	10956	struct drm_i915_gem_request *req,
4104	Serge	10957	uint32_t flags)
3031	serge	10958	{
6084	serge	10959	struct intel_engine_cs *ring = req->ring;
3031	serge	10960	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		10961	u32 flip_mask;
		10962	int ret;
2327	Serge	10963
6084	serge	10964	ret = intel_ring_begin(req, 6);
3031	serge	10965	if (ret)
5060	serge	10966	return ret;
2327	Serge	10967
3031	serge	10968	if (intel_crtc->plane)
		10969	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		10970	else
		10971	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		10972	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		10973	intel_ring_emit(ring, MI_NOOP);
		10974	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		10975	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		10976	intel_ring_emit(ring, fb->pitches[0]);
5060	serge	10977	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031	serge	10978	intel_ring_emit(ring, MI_NOOP);
2327	Serge	10979
6084	serge	10980	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031	serge	10981	return 0;
		10982	}
2327	Serge	10983
3031	serge	10984	static int intel_gen4_queue_flip(struct drm_device *dev,
		10985	struct drm_crtc *crtc,
		10986	struct drm_framebuffer *fb,
4104	Serge	10987	struct drm_i915_gem_object *obj,
6084	serge	10988	struct drm_i915_gem_request *req,
4104	Serge	10989	uint32_t flags)
3031	serge	10990	{
6084	serge	10991	struct intel_engine_cs *ring = req->ring;
3031	serge	10992	struct drm_i915_private *dev_priv = dev->dev_private;
		10993	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		10994	uint32_t pf, pipesrc;
		10995	int ret;
2327	Serge	10996
6084	serge	10997	ret = intel_ring_begin(req, 4);
3031	serge	10998	if (ret)
5060	serge	10999	return ret;
2327	Serge	11000
3031	serge	11001	/* i965+ uses the linear or tiled offsets from the
		11002	* Display Registers (which do not change across a page-flip)
		11003	* so we need only reprogram the base address.
		11004	*/
		11005	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		11006	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		11007	intel_ring_emit(ring, fb->pitches[0]);
5060	serge	11008	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset \|
3031	serge	11009	obj->tiling_mode);
2327	Serge	11010
3031	serge	11011	/* XXX Enabling the panel-fitter across page-flip is so far
		11012	* untested on non-native modes, so ignore it for now.
		11013	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		11014	*/
		11015	pf = 0;
		11016	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		11017	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	11018
6084	serge	11019	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031	serge	11020	return 0;
		11021	}
2327	Serge	11022
3031	serge	11023	static int intel_gen6_queue_flip(struct drm_device *dev,
		11024	struct drm_crtc *crtc,
		11025	struct drm_framebuffer *fb,
4104	Serge	11026	struct drm_i915_gem_object *obj,
6084	serge	11027	struct drm_i915_gem_request *req,
4104	Serge	11028	uint32_t flags)
3031	serge	11029	{
6084	serge	11030	struct intel_engine_cs *ring = req->ring;
3031	serge	11031	struct drm_i915_private *dev_priv = dev->dev_private;
		11032	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		11033	uint32_t pf, pipesrc;
		11034	int ret;
2327	Serge	11035
6084	serge	11036	ret = intel_ring_begin(req, 4);
3031	serge	11037	if (ret)
5060	serge	11038	return ret;
2327	Serge	11039
3031	serge	11040	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		11041	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		11042	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
5060	serge	11043	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
2327	Serge	11044
3031	serge	11045	/* Contrary to the suggestions in the documentation,
		11046	* "Enable Panel Fitter" does not seem to be required when page
		11047	* flipping with a non-native mode, and worse causes a normal
		11048	* modeset to fail.
		11049	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		11050	*/
		11051	pf = 0;
		11052	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		11053	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	11054
6084	serge	11055	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031	serge	11056	return 0;
		11057	}
2327	Serge	11058
3031	serge	11059	static int intel_gen7_queue_flip(struct drm_device *dev,
		11060	struct drm_crtc *crtc,
		11061	struct drm_framebuffer *fb,
4104	Serge	11062	struct drm_i915_gem_object *obj,
6084	serge	11063	struct drm_i915_gem_request *req,
4104	Serge	11064	uint32_t flags)
3031	serge	11065	{
6084	serge	11066	struct intel_engine_cs *ring = req->ring;
3031	serge	11067	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		11068	uint32_t plane_bit = 0;
4104	Serge	11069	int len, ret;
2327	Serge	11070
5060	serge	11071	switch (intel_crtc->plane) {
3031	serge	11072	case PLANE_A:
		11073	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		11074	break;
		11075	case PLANE_B:
		11076	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		11077	break;
		11078	case PLANE_C:
		11079	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		11080	break;
		11081	default:
		11082	WARN_ONCE(1, "unknown plane in flip command\n");
5060	serge	11083	return -ENODEV;
3031	serge	11084	}
2327	Serge	11085
4104	Serge	11086	len = 4;
5060	serge	11087	if (ring->id == RCS) {
4104	Serge	11088	len += 6;
5060	serge	11089	/*
		11090	* On Gen 8, SRM is now taking an extra dword to accommodate
		11091	* 48bits addresses, and we need a NOOP for the batch size to
		11092	* stay even.
		11093	*/
		11094	if (IS_GEN8(dev))
		11095	len += 2;
		11096	}
4104	Serge	11097
5060	serge	11098	/*
		11099	* BSpec MI_DISPLAY_FLIP for IVB:
		11100	* "The full packet must be contained within the same cache line."
		11101	*
		11102	* Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
		11103	* cacheline, if we ever start emitting more commands before
		11104	* the MI_DISPLAY_FLIP we may need to first emit everything else,
		11105	* then do the cacheline alignment, and finally emit the
		11106	* MI_DISPLAY_FLIP.
		11107	*/
6084	serge	11108	ret = intel_ring_cacheline_align(req);
5060	serge	11109	if (ret)
		11110	return ret;
		11111
6084	serge	11112	ret = intel_ring_begin(req, len);
3031	serge	11113	if (ret)
5060	serge	11114	return ret;
2327	Serge	11115
4104	Serge	11116	/* Unmask the flip-done completion message. Note that the bspec says that
		11117	* we should do this for both the BCS and RCS, and that we must not unmask
		11118	* more than one flip event at any time (or ensure that one flip message
		11119	* can be sent by waiting for flip-done prior to queueing new flips).
		11120	* Experimentation says that BCS works despite DERRMR masking all
		11121	* flip-done completion events and that unmasking all planes at once
		11122	* for the RCS also doesn't appear to drop events. Setting the DERRMR
		11123	* to zero does lead to lockups within MI_DISPLAY_FLIP.
		11124	*/
		11125	if (ring->id == RCS) {
		11126	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		11127	intel_ring_emit(ring, DERRMR);
		11128	intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE \|
		11129	DERRMR_PIPEB_PRI_FLIP_DONE \|
		11130	DERRMR_PIPEC_PRI_FLIP_DONE));
5060	serge	11131	if (IS_GEN8(dev))
6084	serge	11132	intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 \|
5060	serge	11133	MI_SRM_LRM_GLOBAL_GTT);
		11134	else
6084	serge	11135	intel_ring_emit(ring, MI_STORE_REGISTER_MEM \|
		11136	MI_SRM_LRM_GLOBAL_GTT);
4104	Serge	11137	intel_ring_emit(ring, DERRMR);
		11138	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
5060	serge	11139	if (IS_GEN8(dev)) {
		11140	intel_ring_emit(ring, 0);
		11141	intel_ring_emit(ring, MI_NOOP);
		11142	}
4104	Serge	11143	}
		11144
3031	serge	11145	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		11146	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
5060	serge	11147	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031	serge	11148	intel_ring_emit(ring, (MI_NOOP));
3243	Serge	11149
6084	serge	11150	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031	serge	11151	return 0;
		11152	}
2327	Serge	11153
6084	serge	11154	static bool use_mmio_flip(struct intel_engine_cs *ring,
		11155	struct drm_i915_gem_object *obj)
		11156	{
		11157	/*
		11158	* This is not being used for older platforms, because
		11159	* non-availability of flip done interrupt forces us to use
		11160	* CS flips. Older platforms derive flip done using some clever
		11161	* tricks involving the flip_pending status bits and vblank irqs.
		11162	* So using MMIO flips there would disrupt this mechanism.
		11163	*/
		11164
		11165	if (ring == NULL)
		11166	return true;
		11167
		11168	if (INTEL_INFO(ring->dev)->gen < 5)
		11169	return false;
		11170
		11171	if (i915.use_mmio_flip < 0)
		11172	return false;
		11173	else if (i915.use_mmio_flip > 0)
		11174	return true;
		11175	else if (i915.enable_execlists)
		11176	return true;
		11177	else
		11178	return ring != i915_gem_request_get_ring(obj->last_write_req);
		11179	}
		11180
		11181	static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
		11182	struct intel_unpin_work *work)
		11183	{
		11184	struct drm_device *dev = intel_crtc->base.dev;
		11185	struct drm_i915_private *dev_priv = dev->dev_private;
		11186	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
		11187	const enum pipe pipe = intel_crtc->pipe;
		11188	u32 ctl, stride;
		11189
		11190	ctl = I915_READ(PLANE_CTL(pipe, 0));
		11191	ctl &= ~PLANE_CTL_TILED_MASK;
		11192	switch (fb->modifier[0]) {
		11193	case DRM_FORMAT_MOD_NONE:
		11194	break;
		11195	case I915_FORMAT_MOD_X_TILED:
		11196	ctl \|= PLANE_CTL_TILED_X;
		11197	break;
		11198	case I915_FORMAT_MOD_Y_TILED:
		11199	ctl \|= PLANE_CTL_TILED_Y;
		11200	break;
		11201	case I915_FORMAT_MOD_Yf_TILED:
		11202	ctl \|= PLANE_CTL_TILED_YF;
		11203	break;
		11204	default:
		11205	MISSING_CASE(fb->modifier[0]);
		11206	}
		11207
		11208	/*
		11209	* The stride is either expressed as a multiple of 64 bytes chunks for
		11210	* linear buffers or in number of tiles for tiled buffers.
		11211	*/
		11212	stride = fb->pitches[0] /
		11213	intel_fb_stride_alignment(dev, fb->modifier[0],
		11214	fb->pixel_format);
		11215
		11216	/*
		11217	* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
		11218	* PLANE_SURF updates, the update is then guaranteed to be atomic.
		11219	*/
		11220	I915_WRITE(PLANE_CTL(pipe, 0), ctl);
		11221	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
		11222
		11223	I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
		11224	POSTING_READ(PLANE_SURF(pipe, 0));
		11225	}
		11226
		11227	static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
		11228	struct intel_unpin_work *work)
		11229	{
		11230	struct drm_device *dev = intel_crtc->base.dev;
		11231	struct drm_i915_private *dev_priv = dev->dev_private;
		11232	struct intel_framebuffer *intel_fb =
		11233	to_intel_framebuffer(intel_crtc->base.primary->fb);
		11234	struct drm_i915_gem_object *obj = intel_fb->obj;
		11235	u32 dspcntr;
		11236	u32 reg;
		11237
		11238	reg = DSPCNTR(intel_crtc->plane);
		11239	dspcntr = I915_READ(reg);
		11240
		11241	if (obj->tiling_mode != I915_TILING_NONE)
		11242	dspcntr \|= DISPPLANE_TILED;
		11243	else
		11244	dspcntr &= ~DISPPLANE_TILED;
		11245
		11246	I915_WRITE(reg, dspcntr);
		11247
		11248	I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
		11249	POSTING_READ(DSPSURF(intel_crtc->plane));
		11250	}
		11251
		11252	/*
		11253	* XXX: This is the temporary way to update the plane registers until we get
		11254	* around to using the usual plane update functions for MMIO flips
		11255	*/
		11256	static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
		11257	{
		11258	struct intel_crtc *crtc = mmio_flip->crtc;
		11259	struct intel_unpin_work *work;
		11260
		11261	spin_lock_irq(&crtc->base.dev->event_lock);
		11262	work = crtc->unpin_work;
		11263	spin_unlock_irq(&crtc->base.dev->event_lock);
		11264	if (work == NULL)
		11265	return;
		11266
		11267	intel_mark_page_flip_active(work);
		11268
		11269	intel_pipe_update_start(crtc);
		11270
		11271	if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
		11272	skl_do_mmio_flip(crtc, work);
		11273	else
		11274	/* use_mmio_flip() retricts MMIO flips to ilk+ */
		11275	ilk_do_mmio_flip(crtc, work);
		11276
		11277	intel_pipe_update_end(crtc);
		11278	}
		11279
		11280	static void intel_mmio_flip_work_func(struct work_struct *work)
		11281	{
		11282	struct intel_mmio_flip *mmio_flip =
		11283	container_of(work, struct intel_mmio_flip, work);
		11284
		11285	if (mmio_flip->req) {
		11286	WARN_ON(__i915_wait_request(mmio_flip->req,
		11287	mmio_flip->crtc->reset_counter,
		11288	false, NULL,
		11289	&mmio_flip->i915->rps.mmioflips));
		11290	i915_gem_request_unreference__unlocked(mmio_flip->req);
		11291	}
		11292
		11293	intel_do_mmio_flip(mmio_flip);
		11294	kfree(mmio_flip);
		11295	}
		11296
		11297	static int intel_queue_mmio_flip(struct drm_device *dev,
		11298	struct drm_crtc *crtc,
		11299	struct drm_framebuffer *fb,
		11300	struct drm_i915_gem_object *obj,
		11301	struct intel_engine_cs *ring,
		11302	uint32_t flags)
		11303	{
		11304	struct intel_mmio_flip *mmio_flip;
		11305
		11306	mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
		11307	if (mmio_flip == NULL)
		11308	return -ENOMEM;
		11309
		11310	mmio_flip->i915 = to_i915(dev);
		11311	mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
		11312	mmio_flip->crtc = to_intel_crtc(crtc);
		11313
		11314	INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
		11315	schedule_work(&mmio_flip->work);
		11316
		11317	return 0;
		11318	}
		11319
3031	serge	11320	static int intel_default_queue_flip(struct drm_device *dev,
		11321	struct drm_crtc *crtc,
		11322	struct drm_framebuffer *fb,
4104	Serge	11323	struct drm_i915_gem_object *obj,
6084	serge	11324	struct drm_i915_gem_request *req,
4104	Serge	11325	uint32_t flags)
3031	serge	11326	{
		11327	return -ENODEV;
		11328	}
2327	Serge	11329
6084	serge	11330	static bool __intel_pageflip_stall_check(struct drm_device *dev,
		11331	struct drm_crtc *crtc)
		11332	{
		11333	struct drm_i915_private *dev_priv = dev->dev_private;
		11334	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		11335	struct intel_unpin_work *work = intel_crtc->unpin_work;
		11336	u32 addr;
		11337
		11338	if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
		11339	return true;
		11340
		11341	if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
		11342	return false;
		11343
		11344	if (!work->enable_stall_check)
		11345	return false;
		11346
		11347	if (work->flip_ready_vblank == 0) {
		11348	if (work->flip_queued_req &&
		11349	!i915_gem_request_completed(work->flip_queued_req, true))
		11350	return false;
		11351
		11352	work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
		11353	}
		11354
		11355	if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
		11356	return false;
		11357
		11358	/* Potential stall - if we see that the flip has happened,
		11359	* assume a missed interrupt. */
		11360	if (INTEL_INFO(dev)->gen >= 4)
		11361	addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
		11362	else
		11363	addr = I915_READ(DSPADDR(intel_crtc->plane));
		11364
		11365	/* There is a potential issue here with a false positive after a flip
		11366	* to the same address. We could address this by checking for a
		11367	* non-incrementing frame counter.
		11368	*/
		11369	return addr == work->gtt_offset;
		11370	}
		11371
		11372	void intel_check_page_flip(struct drm_device *dev, int pipe)
		11373	{
		11374	struct drm_i915_private *dev_priv = dev->dev_private;
		11375	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		11376	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		11377	struct intel_unpin_work *work;
		11378
		11379	if (crtc == NULL)
		11380	return;
		11381
		11382	spin_lock(&dev->event_lock);
		11383	work = intel_crtc->unpin_work;
		11384	if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
		11385	WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
		11386	work->flip_queued_vblank, drm_vblank_count(dev, pipe));
		11387	page_flip_completed(intel_crtc);
		11388	work = NULL;
		11389	}
		11390	if (work != NULL &&
		11391	drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
		11392	intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
		11393	spin_unlock(&dev->event_lock);
		11394	}
6320	serge	11395
3031	serge	11396	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		11397	struct drm_framebuffer *fb,
4104	Serge	11398	struct drm_pending_vblank_event *event,
		11399	uint32_t page_flip_flags)
3031	serge	11400	{
		11401	struct drm_device *dev = crtc->dev;
		11402	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	11403	struct drm_framebuffer *old_fb = crtc->primary->fb;
		11404	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3031	serge	11405	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084	serge	11406	struct drm_plane *primary = crtc->primary;
5060	serge	11407	enum pipe pipe = intel_crtc->pipe;
3031	serge	11408	struct intel_unpin_work *work;
5060	serge	11409	struct intel_engine_cs *ring;
6084	serge	11410	bool mmio_flip;
		11411	struct drm_i915_gem_request *request = NULL;
3031	serge	11412	int ret;
2327	Serge	11413
5060	serge	11414	/*
		11415	* drm_mode_page_flip_ioctl() should already catch this, but double
		11416	* check to be safe. In the future we may enable pageflipping from
		11417	* a disabled primary plane.
		11418	*/
		11419	if (WARN_ON(intel_fb_obj(old_fb) == NULL))
		11420	return -EBUSY;
		11421
3031	serge	11422	/* Can't change pixel format via MI display flips. */
5060	serge	11423	if (fb->pixel_format != crtc->primary->fb->pixel_format)
3031	serge	11424	return -EINVAL;
2327	Serge	11425
3031	serge	11426	/*
		11427	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		11428	* Note that pitch changes could also affect these register.
		11429	*/
		11430	if (INTEL_INFO(dev)->gen > 3 &&
5060	serge	11431	(fb->offsets[0] != crtc->primary->fb->offsets[0] \|\|
		11432	fb->pitches[0] != crtc->primary->fb->pitches[0]))
3031	serge	11433	return -EINVAL;
2327	Serge	11434
5354	serge	11435	if (i915_terminally_wedged(&dev_priv->gpu_error))
		11436	goto out_hang;
		11437
4560	Serge	11438	work = kzalloc(sizeof(*work), GFP_KERNEL);
3031	serge	11439	if (work == NULL)
		11440	return -ENOMEM;
2327	Serge	11441
3031	serge	11442	work->event = event;
3243	Serge	11443	work->crtc = crtc;
6084	serge	11444	work->old_fb = old_fb;
6320	serge	11445	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	11446
5060	serge	11447	ret = drm_crtc_vblank_get(crtc);
3031	serge	11448	if (ret)
		11449	goto free_work;
2327	Serge	11450
3031	serge	11451	/* We borrow the event spin lock for protecting unpin_work */
5354	serge	11452	spin_lock_irq(&dev->event_lock);
3031	serge	11453	if (intel_crtc->unpin_work) {
5354	serge	11454	/* Before declaring the flip queue wedged, check if
		11455	* the hardware completed the operation behind our backs.
		11456	*/
		11457	if (__intel_pageflip_stall_check(dev, crtc)) {
		11458	DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
		11459	page_flip_completed(intel_crtc);
		11460	} else {
		11461	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		11462	spin_unlock_irq(&dev->event_lock);
		11463
		11464	drm_crtc_vblank_put(crtc);
6084	serge	11465	kfree(work);
		11466	return -EBUSY;
		11467	}
3031	serge	11468	}
		11469	intel_crtc->unpin_work = work;
5354	serge	11470	spin_unlock_irq(&dev->event_lock);
2327	Serge	11471
6320	serge	11472	// if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		11473	// flush_workqueue(dev_priv->wq);
3243	Serge	11474
3031	serge	11475	/* Reference the objects for the scheduled work. */
6084	serge	11476	drm_framebuffer_reference(work->old_fb);
3031	serge	11477	drm_gem_object_reference(&obj->base);
2327	Serge	11478
5060	serge	11479	crtc->primary->fb = fb;
6084	serge	11480	update_state_fb(crtc->primary);
2327	Serge	11481
3031	serge	11482	work->pending_flip_obj = obj;
2327	Serge	11483
6084	serge	11484	ret = i915_mutex_lock_interruptible(dev);
		11485	if (ret)
		11486	goto cleanup;
		11487
3243	Serge	11488	atomic_inc(&intel_crtc->unpin_work_count);
3480	Serge	11489	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3031	serge	11490
5060	serge	11491	if (INTEL_INFO(dev)->gen >= 5 \|\| IS_G4X(dev))
6084	serge	11492	work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
5060	serge	11493
		11494	if (IS_VALLEYVIEW(dev)) {
		11495	ring = &dev_priv->ring[BCS];
6084	serge	11496	if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
5060	serge	11497	/* vlv: DISPLAY_FLIP fails to change tiling */
		11498	ring = NULL;
6084	serge	11499	} else if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev)) {
5060	serge	11500	ring = &dev_priv->ring[BCS];
		11501	} else if (INTEL_INFO(dev)->gen >= 7) {
6084	serge	11502	ring = i915_gem_request_get_ring(obj->last_write_req);
5060	serge	11503	if (ring == NULL \|\| ring->id != RCS)
		11504	ring = &dev_priv->ring[BCS];
		11505	} else {
		11506	ring = &dev_priv->ring[RCS];
		11507	}
		11508
6084	serge	11509	mmio_flip = use_mmio_flip(ring, obj);
		11510
		11511	/* When using CS flips, we want to emit semaphores between rings.
		11512	* However, when using mmio flips we will create a task to do the
		11513	* synchronisation, so all we want here is to pin the framebuffer
		11514	* into the display plane and skip any waits.
		11515	*/
		11516	ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
		11517	crtc->primary->state,
		11518	mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
3031	serge	11519	if (ret)
		11520	goto cleanup_pending;
		11521
6084	serge	11522	work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
		11523	obj, 0);
		11524	work->gtt_offset += intel_crtc->dspaddr_offset;
5060	serge	11525
6084	serge	11526	if (mmio_flip) {
5060	serge	11527	ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
		11528	page_flip_flags);
5354	serge	11529	if (ret)
		11530	goto cleanup_unpin;
		11531
6084	serge	11532	i915_gem_request_assign(&work->flip_queued_req,
		11533	obj->last_write_req);
5354	serge	11534	} else {
6084	serge	11535	if (!request) {
		11536	ret = i915_gem_request_alloc(ring, ring->default_context, &request);
		11537	if (ret)
		11538	goto cleanup_unpin;
		11539	}
5060	serge	11540
6084	serge	11541	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
		11542	page_flip_flags);
		11543	if (ret)
		11544	goto cleanup_unpin;
		11545
		11546	i915_gem_request_assign(&work->flip_queued_req, request);
5354	serge	11547	}
		11548
6084	serge	11549	if (request)
		11550	i915_add_request_no_flush(request);
		11551
		11552	work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
5354	serge	11553	work->enable_stall_check = true;
		11554
6084	serge	11555	i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
		11556	to_intel_plane(primary)->frontbuffer_bit);
3031	serge	11557	mutex_unlock(&dev->struct_mutex);
		11558
6084	serge	11559	intel_fbc_disable_crtc(intel_crtc);
		11560	intel_frontbuffer_flip_prepare(dev,
		11561	to_intel_plane(primary)->frontbuffer_bit);
		11562
3031	serge	11563	trace_i915_flip_request(intel_crtc->plane, obj);
		11564
		11565	return 0;
		11566
5060	serge	11567	cleanup_unpin:
6084	serge	11568	intel_unpin_fb_obj(fb, crtc->primary->state);
3031	serge	11569	cleanup_pending:
6084	serge	11570	if (request)
		11571	i915_gem_request_cancel(request);
3243	Serge	11572	atomic_dec(&intel_crtc->unpin_work_count);
6084	serge	11573	mutex_unlock(&dev->struct_mutex);
		11574	cleanup:
5060	serge	11575	crtc->primary->fb = old_fb;
6084	serge	11576	update_state_fb(crtc->primary);
3031	serge	11577
6084	serge	11578	drm_gem_object_unreference_unlocked(&obj->base);
		11579	drm_framebuffer_unreference(work->old_fb);
		11580
5354	serge	11581	spin_lock_irq(&dev->event_lock);
3031	serge	11582	intel_crtc->unpin_work = NULL;
5354	serge	11583	spin_unlock_irq(&dev->event_lock);
3031	serge	11584
5060	serge	11585	drm_crtc_vblank_put(crtc);
3031	serge	11586	free_work:
		11587	kfree(work);
		11588
5060	serge	11589	if (ret == -EIO) {
6084	serge	11590	struct drm_atomic_state *state;
		11591	struct drm_plane_state *plane_state;
		11592
5060	serge	11593	out_hang:
6084	serge	11594	state = drm_atomic_state_alloc(dev);
		11595	if (!state)
		11596	return -ENOMEM;
		11597	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
		11598
		11599	retry:
		11600	plane_state = drm_atomic_get_plane_state(state, primary);
		11601	ret = PTR_ERR_OR_ZERO(plane_state);
		11602	if (!ret) {
		11603	drm_atomic_set_fb_for_plane(plane_state, fb);
		11604
		11605	ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
		11606	if (!ret)
		11607	ret = drm_atomic_commit(state);
		11608	}
		11609
		11610	if (ret == -EDEADLK) {
		11611	drm_modeset_backoff(state->acquire_ctx);
		11612	drm_atomic_state_clear(state);
		11613	goto retry;
		11614	}
		11615
		11616	if (ret)
		11617	drm_atomic_state_free(state);
		11618
5354	serge	11619	if (ret == 0 && event) {
		11620	spin_lock_irq(&dev->event_lock);
5060	serge	11621	drm_send_vblank_event(dev, pipe, event);
5354	serge	11622	spin_unlock_irq(&dev->event_lock);
		11623	}
5060	serge	11624	}
3031	serge	11625	return ret;
		11626	}
		11627
		11628
		11629	/**
6084	serge	11630	* intel_wm_need_update - Check whether watermarks need updating
		11631	* @plane: drm plane
		11632	* @state: new plane state
3031	serge	11633	*
6084	serge	11634	* Check current plane state versus the new one to determine whether
		11635	* watermarks need to be recalculated.
		11636	*
		11637	* Returns true or false.
3031	serge	11638	*/
6084	serge	11639	static bool intel_wm_need_update(struct drm_plane *plane,
		11640	struct drm_plane_state *state)
3031	serge	11641	{
6084	serge	11642	/* Update watermarks on tiling changes. */
		11643	if (!plane->state->fb \|\| !state->fb \|\|
		11644	plane->state->fb->modifier[0] != state->fb->modifier[0] \|\|
		11645	plane->state->rotation != state->rotation)
		11646	return true;
3031	serge	11647
6084	serge	11648	if (plane->state->crtc_w != state->crtc_w)
		11649	return true;
		11650
		11651	return false;
		11652	}
		11653
		11654	int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
		11655	struct drm_plane_state *plane_state)
		11656	{
		11657	struct drm_crtc *crtc = crtc_state->crtc;
		11658	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		11659	struct drm_plane *plane = plane_state->plane;
		11660	struct drm_device *dev = crtc->dev;
		11661	struct drm_i915_private *dev_priv = dev->dev_private;
		11662	struct intel_plane_state *old_plane_state =
		11663	to_intel_plane_state(plane->state);
		11664	int idx = intel_crtc->base.base.id, ret;
		11665	int i = drm_plane_index(plane);
		11666	bool mode_changed = needs_modeset(crtc_state);
		11667	bool was_crtc_enabled = crtc->state->active;
		11668	bool is_crtc_enabled = crtc_state->active;
		11669
		11670	bool turn_off, turn_on, visible, was_visible;
		11671	struct drm_framebuffer *fb = plane_state->fb;
		11672
		11673	if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
		11674	plane->type != DRM_PLANE_TYPE_CURSOR) {
		11675	ret = skl_update_scaler_plane(
		11676	to_intel_crtc_state(crtc_state),
		11677	to_intel_plane_state(plane_state));
		11678	if (ret)
		11679	return ret;
3031	serge	11680	}
		11681
6084	serge	11682	/*
		11683	* Disabling a plane is always okay; we just need to update
		11684	* fb tracking in a special way since cleanup_fb() won't
		11685	* get called by the plane helpers.
		11686	*/
		11687	if (old_plane_state->base.fb && !fb)
		11688	intel_crtc->atomic.disabled_planes \|= 1 << i;
		11689
		11690	was_visible = old_plane_state->visible;
		11691	visible = to_intel_plane_state(plane_state)->visible;
		11692
		11693	if (!was_crtc_enabled && WARN_ON(was_visible))
		11694	was_visible = false;
		11695
		11696	if (!is_crtc_enabled && WARN_ON(visible))
		11697	visible = false;
		11698
		11699	if (!was_visible && !visible)
		11700	return 0;
		11701
		11702	turn_off = was_visible && (!visible \|\| mode_changed);
		11703	turn_on = visible && (!was_visible \|\| mode_changed);
		11704
		11705	DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
		11706	plane->base.id, fb ? fb->base.id : -1);
		11707
		11708	DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
		11709	plane->base.id, was_visible, visible,
		11710	turn_off, turn_on, mode_changed);
		11711
		11712	if (turn_on) {
		11713	intel_crtc->atomic.update_wm_pre = true;
		11714	/* must disable cxsr around plane enable/disable */
		11715	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
		11716	intel_crtc->atomic.disable_cxsr = true;
		11717	/* to potentially re-enable cxsr */
		11718	intel_crtc->atomic.wait_vblank = true;
		11719	intel_crtc->atomic.update_wm_post = true;
		11720	}
		11721	} else if (turn_off) {
		11722	intel_crtc->atomic.update_wm_post = true;
		11723	/* must disable cxsr around plane enable/disable */
		11724	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
		11725	if (is_crtc_enabled)
		11726	intel_crtc->atomic.wait_vblank = true;
		11727	intel_crtc->atomic.disable_cxsr = true;
		11728	}
		11729	} else if (intel_wm_need_update(plane, plane_state)) {
		11730	intel_crtc->atomic.update_wm_pre = true;
3031	serge	11731	}
5060	serge	11732
6084	serge	11733	if (visible \|\| was_visible)
		11734	intel_crtc->atomic.fb_bits \|=
		11735	to_intel_plane(plane)->frontbuffer_bit;
5060	serge	11736
6084	serge	11737	switch (plane->type) {
		11738	case DRM_PLANE_TYPE_PRIMARY:
		11739	intel_crtc->atomic.wait_for_flips = true;
		11740	intel_crtc->atomic.pre_disable_primary = turn_off;
		11741	intel_crtc->atomic.post_enable_primary = turn_on;
		11742
		11743	if (turn_off) {
		11744	/*
		11745	* FIXME: Actually if we will still have any other
		11746	* plane enabled on the pipe we could let IPS enabled
		11747	* still, but for now lets consider that when we make
		11748	* primary invisible by setting DSPCNTR to 0 on
		11749	* update_primary_plane function IPS needs to be
		11750	* disable.
		11751	*/
		11752	intel_crtc->atomic.disable_ips = true;
		11753
		11754	intel_crtc->atomic.disable_fbc = true;
		11755	}
		11756
		11757	/*
		11758	* FBC does not work on some platforms for rotated
		11759	* planes, so disable it when rotation is not 0 and
		11760	* update it when rotation is set back to 0.
		11761	*
		11762	* FIXME: This is redundant with the fbc update done in
		11763	* the primary plane enable function except that that
		11764	* one is done too late. We eventually need to unify
		11765	* this.
		11766	*/
		11767
		11768	if (visible &&
		11769	INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
		11770	dev_priv->fbc.crtc == intel_crtc &&
		11771	plane_state->rotation != BIT(DRM_ROTATE_0))
		11772	intel_crtc->atomic.disable_fbc = true;
		11773
		11774	/*
		11775	* BDW signals flip done immediately if the plane
		11776	* is disabled, even if the plane enable is already
		11777	* armed to occur at the next vblank :(
		11778	*/
		11779	if (turn_on && IS_BROADWELL(dev))
		11780	intel_crtc->atomic.wait_vblank = true;
		11781
		11782	intel_crtc->atomic.update_fbc \|= visible \|\| mode_changed;
		11783	break;
		11784	case DRM_PLANE_TYPE_CURSOR:
		11785	break;
		11786	case DRM_PLANE_TYPE_OVERLAY:
		11787	if (turn_off && !mode_changed) {
		11788	intel_crtc->atomic.wait_vblank = true;
		11789	intel_crtc->atomic.update_sprite_watermarks \|=
		11790	1 << i;
		11791	}
5060	serge	11792	}
6084	serge	11793	return 0;
3031	serge	11794	}
		11795
6084	serge	11796	static bool encoders_cloneable(const struct intel_encoder *a,
		11797	const struct intel_encoder *b)
3031	serge	11798	{
6084	serge	11799	/* masks could be asymmetric, so check both ways */
		11800	return a == b \|\| (a->cloneable & (1 << b->type) &&
		11801	b->cloneable & (1 << a->type));
		11802	}
		11803
		11804	static bool check_single_encoder_cloning(struct drm_atomic_state *state,
		11805	struct intel_crtc *crtc,
		11806	struct intel_encoder *encoder)
		11807	{
		11808	struct intel_encoder *source_encoder;
		11809	struct drm_connector *connector;
		11810	struct drm_connector_state *connector_state;
		11811	int i;
		11812
		11813	for_each_connector_in_state(state, connector, connector_state, i) {
		11814	if (connector_state->crtc != &crtc->base)
		11815	continue;
		11816
		11817	source_encoder =
		11818	to_intel_encoder(connector_state->best_encoder);
		11819	if (!encoders_cloneable(encoder, source_encoder))
		11820	return false;
		11821	}
		11822
		11823	return true;
		11824	}
		11825
		11826	static bool check_encoder_cloning(struct drm_atomic_state *state,
		11827	struct intel_crtc *crtc)
		11828	{
3031	serge	11829	struct intel_encoder *encoder;
6084	serge	11830	struct drm_connector *connector;
		11831	struct drm_connector_state *connector_state;
		11832	int i;
3031	serge	11833
6084	serge	11834	for_each_connector_in_state(state, connector, connector_state, i) {
		11835	if (connector_state->crtc != &crtc->base)
		11836	continue;
		11837
		11838	encoder = to_intel_encoder(connector_state->best_encoder);
		11839	if (!check_single_encoder_cloning(state, crtc, encoder))
		11840	return false;
3031	serge	11841	}
		11842
6084	serge	11843	return true;
		11844	}
		11845
		11846	static int intel_crtc_atomic_check(struct drm_crtc *crtc,
		11847	struct drm_crtc_state *crtc_state)
		11848	{
		11849	struct drm_device *dev = crtc->dev;
		11850	struct drm_i915_private *dev_priv = dev->dev_private;
		11851	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		11852	struct intel_crtc_state *pipe_config =
		11853	to_intel_crtc_state(crtc_state);
		11854	struct drm_atomic_state *state = crtc_state->state;
		11855	int ret;
		11856	bool mode_changed = needs_modeset(crtc_state);
		11857
		11858	if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
		11859	DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
		11860	return -EINVAL;
3031	serge	11861	}
5060	serge	11862
6084	serge	11863	if (mode_changed && !crtc_state->active)
		11864	intel_crtc->atomic.update_wm_post = true;
		11865
		11866	if (mode_changed && crtc_state->enable &&
		11867	dev_priv->display.crtc_compute_clock &&
		11868	!WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
		11869	ret = dev_priv->display.crtc_compute_clock(intel_crtc,
		11870	pipe_config);
		11871	if (ret)
		11872	return ret;
5060	serge	11873	}
6084	serge	11874
		11875	ret = 0;
		11876	if (INTEL_INFO(dev)->gen >= 9) {
		11877	if (mode_changed)
		11878	ret = skl_update_scaler_crtc(pipe_config);
		11879
		11880	if (!ret)
		11881	ret = intel_atomic_setup_scalers(dev, intel_crtc,
		11882	pipe_config);
		11883	}
		11884
		11885	return ret;
3031	serge	11886	}
		11887
6084	serge	11888	static const struct drm_crtc_helper_funcs intel_helper_funcs = {
		11889	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		11890	.load_lut = intel_crtc_load_lut,
		11891	.atomic_begin = intel_begin_crtc_commit,
		11892	.atomic_flush = intel_finish_crtc_commit,
		11893	.atomic_check = intel_crtc_atomic_check,
		11894	};
		11895
		11896	static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
		11897	{
		11898	struct intel_connector *connector;
		11899
		11900	for_each_intel_connector(dev, connector) {
		11901	if (connector->base.encoder) {
		11902	connector->base.state->best_encoder =
		11903	connector->base.encoder;
		11904	connector->base.state->crtc =
		11905	connector->base.encoder->crtc;
		11906	} else {
		11907	connector->base.state->best_encoder = NULL;
		11908	connector->base.state->crtc = NULL;
		11909	}
		11910	}
		11911	}
		11912
4104	Serge	11913	static void
5060	serge	11914	connected_sink_compute_bpp(struct intel_connector *connector,
6084	serge	11915	struct intel_crtc_state *pipe_config)
4104	Serge	11916	{
		11917	int bpp = pipe_config->pipe_bpp;
		11918
		11919	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
		11920	connector->base.base.id,
5060	serge	11921	connector->base.name);
4104	Serge	11922
		11923	/* Don't use an invalid EDID bpc value */
		11924	if (connector->base.display_info.bpc &&
		11925	connector->base.display_info.bpc * 3 < bpp) {
		11926	DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
		11927	bpp, connector->base.display_info.bpc*3);
		11928	pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
		11929	}
		11930
6320	serge	11931	/* Clamp bpp to default limit on screens without EDID 1.4 */
		11932	if (connector->base.display_info.bpc == 0) {
		11933	int type = connector->base.connector_type;
		11934	int clamp_bpp = 24;
		11935
		11936	/* Fall back to 18 bpp when DP sink capability is unknown. */
		11937	if (type == DRM_MODE_CONNECTOR_DisplayPort \|\|
		11938	type == DRM_MODE_CONNECTOR_eDP)
		11939	clamp_bpp = 18;
		11940
		11941	if (bpp > clamp_bpp) {
		11942	DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
		11943	bpp, clamp_bpp);
		11944	pipe_config->pipe_bpp = clamp_bpp;
		11945	}
4104	Serge	11946	}
		11947	}
		11948
3746	Serge	11949	static int
4104	Serge	11950	compute_baseline_pipe_bpp(struct intel_crtc *crtc,
6084	serge	11951	struct intel_crtc_state *pipe_config)
3746	Serge	11952	{
4104	Serge	11953	struct drm_device *dev = crtc->base.dev;
6084	serge	11954	struct drm_atomic_state *state;
		11955	struct drm_connector *connector;
		11956	struct drm_connector_state *connector_state;
		11957	int bpp, i;
3746	Serge	11958
6084	serge	11959	if ((IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)))
		11960	bpp = 10*3;
		11961	else if (INTEL_INFO(dev)->gen >= 5)
		11962	bpp = 12*3;
		11963	else
3746	Serge	11964	bpp = 8*3;
		11965
6084	serge	11966
3746	Serge	11967	pipe_config->pipe_bpp = bpp;
		11968
6084	serge	11969	state = pipe_config->base.state;
		11970
3746	Serge	11971	/* Clamp display bpp to EDID value */
6084	serge	11972	for_each_connector_in_state(state, connector, connector_state, i) {
		11973	if (connector_state->crtc != &crtc->base)
3746	Serge	11974	continue;
		11975
6084	serge	11976	connected_sink_compute_bpp(to_intel_connector(connector),
		11977	pipe_config);
3746	Serge	11978	}
		11979
		11980	return bpp;
		11981	}
		11982
4560	Serge	11983	static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
		11984	{
		11985	DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
		11986	"type: 0x%x flags: 0x%x\n",
		11987	mode->crtc_clock,
		11988	mode->crtc_hdisplay, mode->crtc_hsync_start,
		11989	mode->crtc_hsync_end, mode->crtc_htotal,
		11990	mode->crtc_vdisplay, mode->crtc_vsync_start,
		11991	mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
		11992	}
		11993
4104	Serge	11994	static void intel_dump_pipe_config(struct intel_crtc *crtc,
6084	serge	11995	struct intel_crtc_state *pipe_config,
4104	Serge	11996	const char *context)
		11997	{
6084	serge	11998	struct drm_device *dev = crtc->base.dev;
		11999	struct drm_plane *plane;
		12000	struct intel_plane *intel_plane;
		12001	struct intel_plane_state *state;
		12002	struct drm_framebuffer *fb;
4104	Serge	12003
6084	serge	12004	DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
		12005	context, pipe_config, pipe_name(crtc->pipe));
		12006
4104	Serge	12007	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
		12008	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
		12009	pipe_config->pipe_bpp, pipe_config->dither);
		12010	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		12011	pipe_config->has_pch_encoder,
		12012	pipe_config->fdi_lanes,
		12013	pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
		12014	pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
		12015	pipe_config->fdi_m_n.tu);
6084	serge	12016	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
4560	Serge	12017	pipe_config->has_dp_encoder,
6084	serge	12018	pipe_config->lane_count,
4560	Serge	12019	pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
		12020	pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
		12021	pipe_config->dp_m_n.tu);
5354	serge	12022
6084	serge	12023	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
5354	serge	12024	pipe_config->has_dp_encoder,
6084	serge	12025	pipe_config->lane_count,
5354	serge	12026	pipe_config->dp_m2_n2.gmch_m,
		12027	pipe_config->dp_m2_n2.gmch_n,
		12028	pipe_config->dp_m2_n2.link_m,
		12029	pipe_config->dp_m2_n2.link_n,
		12030	pipe_config->dp_m2_n2.tu);
		12031
		12032	DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
		12033	pipe_config->has_audio,
		12034	pipe_config->has_infoframe);
		12035
4104	Serge	12036	DRM_DEBUG_KMS("requested mode:\n");
6084	serge	12037	drm_mode_debug_printmodeline(&pipe_config->base.mode);
4104	Serge	12038	DRM_DEBUG_KMS("adjusted mode:\n");
6084	serge	12039	drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
		12040	intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
4560	Serge	12041	DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
		12042	DRM_DEBUG_KMS("pipe src size: %dx%d\n",
		12043	pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6084	serge	12044	DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
		12045	crtc->num_scalers,
		12046	pipe_config->scaler_state.scaler_users,
		12047	pipe_config->scaler_state.scaler_id);
4104	Serge	12048	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
		12049	pipe_config->gmch_pfit.control,
		12050	pipe_config->gmch_pfit.pgm_ratios,
		12051	pipe_config->gmch_pfit.lvds_border_bits);
		12052	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
		12053	pipe_config->pch_pfit.pos,
		12054	pipe_config->pch_pfit.size,
		12055	pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
		12056	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
4560	Serge	12057	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
4104	Serge	12058
6084	serge	12059	if (IS_BROXTON(dev)) {
		12060	DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
		12061	"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
		12062	"pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
		12063	pipe_config->ddi_pll_sel,
		12064	pipe_config->dpll_hw_state.ebb0,
		12065	pipe_config->dpll_hw_state.ebb4,
		12066	pipe_config->dpll_hw_state.pll0,
		12067	pipe_config->dpll_hw_state.pll1,
		12068	pipe_config->dpll_hw_state.pll2,
		12069	pipe_config->dpll_hw_state.pll3,
		12070	pipe_config->dpll_hw_state.pll6,
		12071	pipe_config->dpll_hw_state.pll8,
		12072	pipe_config->dpll_hw_state.pll9,
		12073	pipe_config->dpll_hw_state.pll10,
		12074	pipe_config->dpll_hw_state.pcsdw12);
		12075	} else if (IS_SKYLAKE(dev)) {
		12076	DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
		12077	"ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
		12078	pipe_config->ddi_pll_sel,
		12079	pipe_config->dpll_hw_state.ctrl1,
		12080	pipe_config->dpll_hw_state.cfgcr1,
		12081	pipe_config->dpll_hw_state.cfgcr2);
		12082	} else if (HAS_DDI(dev)) {
		12083	DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
		12084	pipe_config->ddi_pll_sel,
		12085	pipe_config->dpll_hw_state.wrpll,
		12086	pipe_config->dpll_hw_state.spll);
		12087	} else {
		12088	DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
		12089	"fp0: 0x%x, fp1: 0x%x\n",
		12090	pipe_config->dpll_hw_state.dpll,
		12091	pipe_config->dpll_hw_state.dpll_md,
		12092	pipe_config->dpll_hw_state.fp0,
		12093	pipe_config->dpll_hw_state.fp1);
		12094	}
5060	serge	12095
6084	serge	12096	DRM_DEBUG_KMS("planes on this crtc\n");
		12097	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
		12098	intel_plane = to_intel_plane(plane);
		12099	if (intel_plane->pipe != crtc->pipe)
5060	serge	12100	continue;
		12101
6084	serge	12102	state = to_intel_plane_state(plane->state);
		12103	fb = state->base.fb;
		12104	if (!fb) {
		12105	DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
		12106	"disabled, scaler_id = %d\n",
		12107	plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
		12108	plane->base.id, intel_plane->pipe,
		12109	(crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
		12110	drm_plane_index(plane), state->scaler_id);
4104	Serge	12111	continue;
6084	serge	12112	}
4104	Serge	12113
6084	serge	12114	DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
		12115	plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
		12116	plane->base.id, intel_plane->pipe,
		12117	crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
		12118	drm_plane_index(plane));
		12119	DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
		12120	fb->base.id, fb->width, fb->height, fb->pixel_format);
		12121	DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
		12122	state->scaler_id,
		12123	state->src.x1 >> 16, state->src.y1 >> 16,
		12124	drm_rect_width(&state->src) >> 16,
		12125	drm_rect_height(&state->src) >> 16,
		12126	state->dst.x1, state->dst.y1,
		12127	drm_rect_width(&state->dst), drm_rect_height(&state->dst));
4104	Serge	12128	}
		12129	}
		12130
6084	serge	12131	static bool check_digital_port_conflicts(struct drm_atomic_state *state)
5354	serge	12132	{
6084	serge	12133	struct drm_device *dev = state->dev;
		12134	struct drm_connector *connector;
5354	serge	12135	unsigned int used_ports = 0;
		12136
		12137	/*
		12138	* Walk the connector list instead of the encoder
		12139	* list to detect the problem on ddi platforms
		12140	* where there's just one encoder per digital port.
		12141	*/
6084	serge	12142	drm_for_each_connector(connector, dev) {
		12143	struct drm_connector_state *connector_state;
		12144	struct intel_encoder *encoder;
5354	serge	12145
6084	serge	12146	connector_state = drm_atomic_get_existing_connector_state(state, connector);
		12147	if (!connector_state)
		12148	connector_state = connector->state;
		12149
		12150	if (!connector_state->best_encoder)
5354	serge	12151	continue;
		12152
6084	serge	12153	encoder = to_intel_encoder(connector_state->best_encoder);
5354	serge	12154
6084	serge	12155	WARN_ON(!connector_state->crtc);
		12156
5354	serge	12157	switch (encoder->type) {
		12158	unsigned int port_mask;
		12159	case INTEL_OUTPUT_UNKNOWN:
		12160	if (WARN_ON(!HAS_DDI(dev)))
		12161	break;
		12162	case INTEL_OUTPUT_DISPLAYPORT:
		12163	case INTEL_OUTPUT_HDMI:
		12164	case INTEL_OUTPUT_EDP:
		12165	port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
		12166
		12167	/* the same port mustn't appear more than once */
		12168	if (used_ports & port_mask)
		12169	return false;
		12170
		12171	used_ports \|= port_mask;
		12172	default:
		12173	break;
		12174	}
		12175	}
		12176
		12177	return true;
		12178	}
		12179
6084	serge	12180	static void
		12181	clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
		12182	{
		12183	struct drm_crtc_state tmp_state;
		12184	struct intel_crtc_scaler_state scaler_state;
		12185	struct intel_dpll_hw_state dpll_hw_state;
		12186	enum intel_dpll_id shared_dpll;
		12187	uint32_t ddi_pll_sel;
		12188	bool force_thru;
		12189
		12190	/* FIXME: before the switch to atomic started, a new pipe_config was
		12191	* kzalloc'd. Code that depends on any field being zero should be
		12192	* fixed, so that the crtc_state can be safely duplicated. For now,
		12193	* only fields that are know to not cause problems are preserved. */
		12194
		12195	tmp_state = crtc_state->base;
		12196	scaler_state = crtc_state->scaler_state;
		12197	shared_dpll = crtc_state->shared_dpll;
		12198	dpll_hw_state = crtc_state->dpll_hw_state;
		12199	ddi_pll_sel = crtc_state->ddi_pll_sel;
		12200	force_thru = crtc_state->pch_pfit.force_thru;
		12201
		12202	memset(crtc_state, 0, sizeof *crtc_state);
		12203
		12204	crtc_state->base = tmp_state;
		12205	crtc_state->scaler_state = scaler_state;
		12206	crtc_state->shared_dpll = shared_dpll;
		12207	crtc_state->dpll_hw_state = dpll_hw_state;
		12208	crtc_state->ddi_pll_sel = ddi_pll_sel;
		12209	crtc_state->pch_pfit.force_thru = force_thru;
		12210	}
		12211
		12212	static int
3746	Serge	12213	intel_modeset_pipe_config(struct drm_crtc *crtc,
6084	serge	12214	struct intel_crtc_state *pipe_config)
3031	serge	12215	{
6084	serge	12216	struct drm_atomic_state *state = pipe_config->base.state;
3031	serge	12217	struct intel_encoder *encoder;
6084	serge	12218	struct drm_connector *connector;
		12219	struct drm_connector_state *connector_state;
		12220	int base_bpp, ret = -EINVAL;
		12221	int i;
4104	Serge	12222	bool retry = true;
3031	serge	12223
6084	serge	12224	clear_intel_crtc_state(pipe_config);
4104	Serge	12225
		12226	pipe_config->cpu_transcoder =
		12227	(enum transcoder) to_intel_crtc(crtc)->pipe;
3746	Serge	12228
4104	Serge	12229	/*
		12230	* Sanitize sync polarity flags based on requested ones. If neither
		12231	* positive or negative polarity is requested, treat this as meaning
		12232	* negative polarity.
		12233	*/
6084	serge	12234	if (!(pipe_config->base.adjusted_mode.flags &
4104	Serge	12235	(DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NHSYNC)))
6084	serge	12236	pipe_config->base.adjusted_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
4104	Serge	12237
6084	serge	12238	if (!(pipe_config->base.adjusted_mode.flags &
4104	Serge	12239	(DRM_MODE_FLAG_PVSYNC \| DRM_MODE_FLAG_NVSYNC)))
6084	serge	12240	pipe_config->base.adjusted_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
4104	Serge	12241
6084	serge	12242	base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
		12243	pipe_config);
		12244	if (base_bpp < 0)
3746	Serge	12245	goto fail;
		12246
4560	Serge	12247	/*
		12248	* Determine the real pipe dimensions. Note that stereo modes can
		12249	* increase the actual pipe size due to the frame doubling and
		12250	* insertion of additional space for blanks between the frame. This
		12251	* is stored in the crtc timings. We use the requested mode to do this
		12252	* computation to clearly distinguish it from the adjusted mode, which
		12253	* can be changed by the connectors in the below retry loop.
		12254	*/
6084	serge	12255	drm_crtc_get_hv_timing(&pipe_config->base.mode,
		12256	&pipe_config->pipe_src_w,
		12257	&pipe_config->pipe_src_h);
4560	Serge	12258
4104	Serge	12259	encoder_retry:
		12260	/* Ensure the port clock defaults are reset when retrying. */
		12261	pipe_config->port_clock = 0;
		12262	pipe_config->pixel_multiplier = 1;
		12263
		12264	/* Fill in default crtc timings, allow encoders to overwrite them. */
6084	serge	12265	drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
		12266	CRTC_STEREO_DOUBLE);
4104	Serge	12267
3031	serge	12268	/* Pass our mode to the connectors and the CRTC to give them a chance to
		12269	* adjust it according to limitations or connector properties, and also
		12270	* a chance to reject the mode entirely.
2330	Serge	12271	*/
6084	serge	12272	for_each_connector_in_state(state, connector, connector_state, i) {
		12273	if (connector_state->crtc != crtc)
3031	serge	12274	continue;
3746	Serge	12275
6084	serge	12276	encoder = to_intel_encoder(connector_state->best_encoder);
		12277
		12278	if (!(encoder->compute_config(encoder, pipe_config))) {
		12279	DRM_DEBUG_KMS("Encoder config failure\n");
		12280	goto fail;
3746	Serge	12281	}
6084	serge	12282	}
3746	Serge	12283
4104	Serge	12284	/* Set default port clock if not overwritten by the encoder. Needs to be
		12285	* done afterwards in case the encoder adjusts the mode. */
		12286	if (!pipe_config->port_clock)
6084	serge	12287	pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
4560	Serge	12288	* pipe_config->pixel_multiplier;
2327	Serge	12289
4104	Serge	12290	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
		12291	if (ret < 0) {
3031	serge	12292	DRM_DEBUG_KMS("CRTC fixup failed\n");
		12293	goto fail;
		12294	}
2327	Serge	12295
4104	Serge	12296	if (ret == RETRY) {
		12297	if (WARN(!retry, "loop in pipe configuration computation\n")) {
		12298	ret = -EINVAL;
		12299	goto fail;
		12300	}
		12301
		12302	DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
		12303	retry = false;
		12304	goto encoder_retry;
		12305	}
		12306
6084	serge	12307	/* Dithering seems to not pass-through bits correctly when it should, so
		12308	* only enable it on 6bpc panels. */
		12309	pipe_config->dither = pipe_config->pipe_bpp == 6*3;
		12310	DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
		12311	base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
3746	Serge	12312
3031	serge	12313	fail:
6084	serge	12314	return ret;
3031	serge	12315	}
2327	Serge	12316
3031	serge	12317	static void
6084	serge	12318	intel_modeset_update_crtc_state(struct drm_atomic_state *state)
3031	serge	12319	{
6084	serge	12320	struct drm_crtc *crtc;
		12321	struct drm_crtc_state *crtc_state;
		12322	int i;
3031	serge	12323
6084	serge	12324	/* Double check state. */
		12325	for_each_crtc_in_state(state, crtc, crtc_state, i) {
		12326	to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
3031	serge	12327
6084	serge	12328	/* Update hwmode for vblank functions */
		12329	if (crtc->state->active)
		12330	crtc->hwmode = crtc->state->adjusted_mode;
5060	serge	12331	else
6084	serge	12332	crtc->hwmode.crtc_clock = 0;
3031	serge	12333	}
2330	Serge	12334	}
2327	Serge	12335
4560	Serge	12336	static bool intel_fuzzy_clock_check(int clock1, int clock2)
4104	Serge	12337	{
4560	Serge	12338	int diff;
4104	Serge	12339
		12340	if (clock1 == clock2)
		12341	return true;
		12342
		12343	if (!clock1 \|\| !clock2)
		12344	return false;
		12345
		12346	diff = abs(clock1 - clock2);
		12347
		12348	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
		12349	return true;
		12350
		12351	return false;
		12352	}
		12353
3031	serge	12354	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		12355	list_for_each_entry((intel_crtc), \
		12356	&(dev)->mode_config.crtc_list, \
		12357	base.head) \
4104	Serge	12358	if (mask & (1 <<(intel_crtc)->pipe))
3031	serge	12359
3746	Serge	12360	static bool
6084	serge	12361	intel_compare_m_n(unsigned int m, unsigned int n,
		12362	unsigned int m2, unsigned int n2,
		12363	bool exact)
		12364	{
		12365	if (m == m2 && n == n2)
		12366	return true;
		12367
		12368	if (exact \|\| !m \|\| !n \|\| !m2 \|\| !n2)
		12369	return false;
		12370
		12371	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
		12372
		12373	if (m > m2) {
		12374	while (m > m2) {
		12375	m2 <<= 1;
		12376	n2 <<= 1;
		12377	}
		12378	} else if (m < m2) {
		12379	while (m < m2) {
		12380	m <<= 1;
		12381	n <<= 1;
		12382	}
		12383	}
		12384
		12385	return m == m2 && n == n2;
		12386	}
		12387
		12388	static bool
		12389	intel_compare_link_m_n(const struct intel_link_m_n *m_n,
		12390	struct intel_link_m_n *m2_n2,
		12391	bool adjust)
		12392	{
		12393	if (m_n->tu == m2_n2->tu &&
		12394	intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
		12395	m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
		12396	intel_compare_m_n(m_n->link_m, m_n->link_n,
		12397	m2_n2->link_m, m2_n2->link_n, !adjust)) {
		12398	if (adjust)
		12399	m2_n2 = m_n;
		12400
		12401	return true;
		12402	}
		12403
		12404	return false;
		12405	}
		12406
		12407	static bool
4104	Serge	12408	intel_pipe_config_compare(struct drm_device *dev,
6084	serge	12409	struct intel_crtc_state *current_config,
		12410	struct intel_crtc_state *pipe_config,
		12411	bool adjust)
3746	Serge	12412	{
6084	serge	12413	bool ret = true;
		12414
		12415	#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
		12416	do { \
		12417	if (!adjust) \
		12418	DRM_ERROR(fmt, ##__VA_ARGS__); \
		12419	else \
		12420	DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
		12421	} while (0)
		12422
4104	Serge	12423	#define PIPE_CONF_CHECK_X(name) \
		12424	if (current_config->name != pipe_config->name) { \
6084	serge	12425	INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
4104	Serge	12426	"(expected 0x%08x, found 0x%08x)\n", \
		12427	current_config->name, \
		12428	pipe_config->name); \
6084	serge	12429	ret = false; \
3746	Serge	12430	}
		12431
4104	Serge	12432	#define PIPE_CONF_CHECK_I(name) \
		12433	if (current_config->name != pipe_config->name) { \
6084	serge	12434	INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
4104	Serge	12435	"(expected %i, found %i)\n", \
		12436	current_config->name, \
		12437	pipe_config->name); \
6084	serge	12438	ret = false; \
4104	Serge	12439	}
		12440
6084	serge	12441	#define PIPE_CONF_CHECK_M_N(name) \
		12442	if (!intel_compare_link_m_n(¤t_config->name, \
		12443	&pipe_config->name,\
		12444	adjust)) { \
		12445	INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
		12446	"(expected tu %i gmch %i/%i link %i/%i, " \
		12447	"found tu %i, gmch %i/%i link %i/%i)\n", \
		12448	current_config->name.tu, \
		12449	current_config->name.gmch_m, \
		12450	current_config->name.gmch_n, \
		12451	current_config->name.link_m, \
		12452	current_config->name.link_n, \
		12453	pipe_config->name.tu, \
		12454	pipe_config->name.gmch_m, \
		12455	pipe_config->name.gmch_n, \
		12456	pipe_config->name.link_m, \
		12457	pipe_config->name.link_n); \
		12458	ret = false; \
		12459	}
		12460
		12461	#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
		12462	if (!intel_compare_link_m_n(¤t_config->name, \
		12463	&pipe_config->name, adjust) && \
		12464	!intel_compare_link_m_n(¤t_config->alt_name, \
		12465	&pipe_config->name, adjust)) { \
		12466	INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
		12467	"(expected tu %i gmch %i/%i link %i/%i, " \
		12468	"or tu %i gmch %i/%i link %i/%i, " \
		12469	"found tu %i, gmch %i/%i link %i/%i)\n", \
		12470	current_config->name.tu, \
		12471	current_config->name.gmch_m, \
		12472	current_config->name.gmch_n, \
		12473	current_config->name.link_m, \
		12474	current_config->name.link_n, \
		12475	current_config->alt_name.tu, \
		12476	current_config->alt_name.gmch_m, \
		12477	current_config->alt_name.gmch_n, \
		12478	current_config->alt_name.link_m, \
		12479	current_config->alt_name.link_n, \
		12480	pipe_config->name.tu, \
		12481	pipe_config->name.gmch_m, \
		12482	pipe_config->name.gmch_n, \
		12483	pipe_config->name.link_m, \
		12484	pipe_config->name.link_n); \
		12485	ret = false; \
		12486	}
		12487
5354	serge	12488	/* This is required for BDW+ where there is only one set of registers for
		12489	* switching between high and low RR.
		12490	* This macro can be used whenever a comparison has to be made between one
		12491	* hw state and multiple sw state variables.
		12492	*/
		12493	#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
		12494	if ((current_config->name != pipe_config->name) && \
		12495	(current_config->alt_name != pipe_config->name)) { \
6084	serge	12496	INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5354	serge	12497	"(expected %i or %i, found %i)\n", \
		12498	current_config->name, \
		12499	current_config->alt_name, \
		12500	pipe_config->name); \
6084	serge	12501	ret = false; \
5354	serge	12502	}
		12503
4104	Serge	12504	#define PIPE_CONF_CHECK_FLAGS(name, mask) \
		12505	if ((current_config->name ^ pipe_config->name) & (mask)) { \
6084	serge	12506	INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
4104	Serge	12507	"(expected %i, found %i)\n", \
		12508	current_config->name & (mask), \
		12509	pipe_config->name & (mask)); \
6084	serge	12510	ret = false; \
4104	Serge	12511	}
		12512
4560	Serge	12513	#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
		12514	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
6084	serge	12515	INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
4560	Serge	12516	"(expected %i, found %i)\n", \
		12517	current_config->name, \
		12518	pipe_config->name); \
6084	serge	12519	ret = false; \
4560	Serge	12520	}
		12521
4104	Serge	12522	#define PIPE_CONF_QUIRK(quirk) \
		12523	((current_config->quirks \| pipe_config->quirks) & (quirk))
		12524
		12525	PIPE_CONF_CHECK_I(cpu_transcoder);
		12526
		12527	PIPE_CONF_CHECK_I(has_pch_encoder);
		12528	PIPE_CONF_CHECK_I(fdi_lanes);
6084	serge	12529	PIPE_CONF_CHECK_M_N(fdi_m_n);
4104	Serge	12530
4560	Serge	12531	PIPE_CONF_CHECK_I(has_dp_encoder);
6084	serge	12532	PIPE_CONF_CHECK_I(lane_count);
5354	serge	12533
		12534	if (INTEL_INFO(dev)->gen < 8) {
6084	serge	12535	PIPE_CONF_CHECK_M_N(dp_m_n);
4560	Serge	12536
6084	serge	12537	if (current_config->has_drrs)
		12538	PIPE_CONF_CHECK_M_N(dp_m2_n2);
		12539	} else
		12540	PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
5354	serge	12541
6084	serge	12542	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
		12543	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
		12544	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
		12545	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
		12546	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
		12547	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
4104	Serge	12548
6084	serge	12549	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
		12550	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
		12551	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
		12552	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
		12553	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
		12554	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
4104	Serge	12555
6084	serge	12556	PIPE_CONF_CHECK_I(pixel_multiplier);
5060	serge	12557	PIPE_CONF_CHECK_I(has_hdmi_sink);
		12558	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) \|\|
		12559	IS_VALLEYVIEW(dev))
		12560	PIPE_CONF_CHECK_I(limited_color_range);
5354	serge	12561	PIPE_CONF_CHECK_I(has_infoframe);
4104	Serge	12562
5060	serge	12563	PIPE_CONF_CHECK_I(has_audio);
		12564
6084	serge	12565	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104	Serge	12566	DRM_MODE_FLAG_INTERLACE);
		12567
		12568	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
6084	serge	12569	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104	Serge	12570	DRM_MODE_FLAG_PHSYNC);
6084	serge	12571	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104	Serge	12572	DRM_MODE_FLAG_NHSYNC);
6084	serge	12573	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104	Serge	12574	DRM_MODE_FLAG_PVSYNC);
6084	serge	12575	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104	Serge	12576	DRM_MODE_FLAG_NVSYNC);
		12577	}
		12578
6084	serge	12579	PIPE_CONF_CHECK_X(gmch_pfit.control);
4104	Serge	12580	/* pfit ratios are autocomputed by the hw on gen4+ */
		12581	if (INTEL_INFO(dev)->gen < 4)
		12582	PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
6084	serge	12583	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5060	serge	12584
6084	serge	12585	if (!adjust) {
		12586	PIPE_CONF_CHECK_I(pipe_src_w);
		12587	PIPE_CONF_CHECK_I(pipe_src_h);
		12588
		12589	PIPE_CONF_CHECK_I(pch_pfit.enabled);
		12590	if (current_config->pch_pfit.enabled) {
		12591	PIPE_CONF_CHECK_X(pch_pfit.pos);
		12592	PIPE_CONF_CHECK_X(pch_pfit.size);
		12593	}
		12594
		12595	PIPE_CONF_CHECK_I(scaler_state.scaler_id);
4104	Serge	12596	}
		12597
4560	Serge	12598	/* BDW+ don't expose a synchronous way to read the state */
		12599	if (IS_HASWELL(dev))
6084	serge	12600	PIPE_CONF_CHECK_I(ips_enabled);
4104	Serge	12601
4560	Serge	12602	PIPE_CONF_CHECK_I(double_wide);
		12603
5060	serge	12604	PIPE_CONF_CHECK_X(ddi_pll_sel);
		12605
4104	Serge	12606	PIPE_CONF_CHECK_I(shared_dpll);
		12607	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
		12608	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
		12609	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
		12610	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5060	serge	12611	PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
6084	serge	12612	PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5354	serge	12613	PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
		12614	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
		12615	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
4104	Serge	12616
4280	Serge	12617	if (IS_G4X(dev) \|\| INTEL_INFO(dev)->gen >= 5)
		12618	PIPE_CONF_CHECK_I(pipe_bpp);
		12619
6084	serge	12620	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
		12621	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
4560	Serge	12622
4104	Serge	12623	#undef PIPE_CONF_CHECK_X
		12624	#undef PIPE_CONF_CHECK_I
5354	serge	12625	#undef PIPE_CONF_CHECK_I_ALT
4104	Serge	12626	#undef PIPE_CONF_CHECK_FLAGS
4560	Serge	12627	#undef PIPE_CONF_CHECK_CLOCK_FUZZY
4104	Serge	12628	#undef PIPE_CONF_QUIRK
6084	serge	12629	#undef INTEL_ERR_OR_DBG_KMS
4104	Serge	12630
6084	serge	12631	return ret;
3746	Serge	12632	}
		12633
5354	serge	12634	static void check_wm_state(struct drm_device *dev)
		12635	{
		12636	struct drm_i915_private *dev_priv = dev->dev_private;
		12637	struct skl_ddb_allocation hw_ddb, *sw_ddb;
		12638	struct intel_crtc *intel_crtc;
		12639	int plane;
		12640
		12641	if (INTEL_INFO(dev)->gen < 9)
		12642	return;
		12643
		12644	skl_ddb_get_hw_state(dev_priv, &hw_ddb);
		12645	sw_ddb = &dev_priv->wm.skl_hw.ddb;
		12646
		12647	for_each_intel_crtc(dev, intel_crtc) {
		12648	struct skl_ddb_entry hw_entry, sw_entry;
		12649	const enum pipe pipe = intel_crtc->pipe;
		12650
		12651	if (!intel_crtc->active)
		12652	continue;
		12653
		12654	/* planes */
6084	serge	12655	for_each_plane(dev_priv, pipe, plane) {
5354	serge	12656	hw_entry = &hw_ddb.plane[pipe][plane];
		12657	sw_entry = &sw_ddb->plane[pipe][plane];
		12658
		12659	if (skl_ddb_entry_equal(hw_entry, sw_entry))
		12660	continue;
		12661
		12662	DRM_ERROR("mismatch in DDB state pipe %c plane %d "
		12663	"(expected (%u,%u), found (%u,%u))\n",
		12664	pipe_name(pipe), plane + 1,
		12665	sw_entry->start, sw_entry->end,
		12666	hw_entry->start, hw_entry->end);
		12667	}
		12668
		12669	/* cursor */
6084	serge	12670	hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
		12671	sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
5354	serge	12672
		12673	if (skl_ddb_entry_equal(hw_entry, sw_entry))
		12674	continue;
		12675
		12676	DRM_ERROR("mismatch in DDB state pipe %c cursor "
		12677	"(expected (%u,%u), found (%u,%u))\n",
		12678	pipe_name(pipe),
		12679	sw_entry->start, sw_entry->end,
		12680	hw_entry->start, hw_entry->end);
		12681	}
		12682	}
		12683
4104	Serge	12684	static void
6084	serge	12685	check_connector_state(struct drm_device *dev,
		12686	struct drm_atomic_state *old_state)
3031	serge	12687	{
6084	serge	12688	struct drm_connector_state *old_conn_state;
		12689	struct drm_connector *connector;
		12690	int i;
3031	serge	12691
6084	serge	12692	for_each_connector_in_state(old_state, connector, old_conn_state, i) {
		12693	struct drm_encoder *encoder = connector->encoder;
		12694	struct drm_connector_state *state = connector->state;
		12695
3031	serge	12696	/* This also checks the encoder/connector hw state with the
		12697	* ->get_hw_state callbacks. */
6084	serge	12698	intel_connector_check_state(to_intel_connector(connector));
3031	serge	12699
6084	serge	12700	I915_STATE_WARN(state->best_encoder != encoder,
		12701	"connector's atomic encoder doesn't match legacy encoder\n");
3031	serge	12702	}
4104	Serge	12703	}
3031	serge	12704
4104	Serge	12705	static void
		12706	check_encoder_state(struct drm_device *dev)
		12707	{
		12708	struct intel_encoder *encoder;
		12709	struct intel_connector *connector;
		12710
5354	serge	12711	for_each_intel_encoder(dev, encoder) {
3031	serge	12712	bool enabled = false;
6084	serge	12713	enum pipe pipe;
3031	serge	12714
		12715	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		12716	encoder->base.base.id,
5060	serge	12717	encoder->base.name);
3031	serge	12718
6084	serge	12719	for_each_intel_connector(dev, connector) {
		12720	if (connector->base.state->best_encoder != &encoder->base)
3031	serge	12721	continue;
		12722	enabled = true;
6084	serge	12723
		12724	I915_STATE_WARN(connector->base.state->crtc !=
		12725	encoder->base.crtc,
		12726	"connector's crtc doesn't match encoder crtc\n");
3031	serge	12727	}
5060	serge	12728
6084	serge	12729	I915_STATE_WARN(!!encoder->base.crtc != enabled,
3031	serge	12730	"encoder's enabled state mismatch "
		12731	"(expected %i, found %i)\n",
		12732	!!encoder->base.crtc, enabled);
		12733
6084	serge	12734	if (!encoder->base.crtc) {
		12735	bool active;
3031	serge	12736
6084	serge	12737	active = encoder->get_hw_state(encoder, &pipe);
		12738	I915_STATE_WARN(active,
		12739	"encoder detached but still enabled on pipe %c.\n",
		12740	pipe_name(pipe));
		12741	}
3031	serge	12742	}
4104	Serge	12743	}
3031	serge	12744
4104	Serge	12745	static void
6084	serge	12746	check_crtc_state(struct drm_device dev, struct drm_atomic_state old_state)
4104	Serge	12747	{
5060	serge	12748	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	12749	struct intel_encoder *encoder;
6084	serge	12750	struct drm_crtc_state *old_crtc_state;
		12751	struct drm_crtc *crtc;
		12752	int i;
4104	Serge	12753
6084	serge	12754	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
		12755	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		12756	struct intel_crtc_state pipe_config, sw_config;
		12757	bool active;
3031	serge	12758
6084	serge	12759	if (!needs_modeset(crtc->state) &&
		12760	!to_intel_crtc_state(crtc->state)->update_pipe)
		12761	continue;
4104	Serge	12762
6084	serge	12763	__drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
		12764	pipe_config = to_intel_crtc_state(old_crtc_state);
		12765	memset(pipe_config, 0, sizeof(*pipe_config));
		12766	pipe_config->base.crtc = crtc;
		12767	pipe_config->base.state = old_state;
		12768
3031	serge	12769	DRM_DEBUG_KMS("[CRTC:%d]\n",
6084	serge	12770	crtc->base.id);
3031	serge	12771
6084	serge	12772	active = dev_priv->display.get_pipe_config(intel_crtc,
		12773	pipe_config);
3031	serge	12774
6084	serge	12775	/* hw state is inconsistent with the pipe quirk */
		12776	if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) \|\|
		12777	(intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
		12778	active = crtc->state->active;
4104	Serge	12779
6084	serge	12780	I915_STATE_WARN(crtc->state->active != active,
		12781	"crtc active state doesn't match with hw state "
		12782	"(expected %i, found %i)\n", crtc->state->active, active);
3031	serge	12783
6084	serge	12784	I915_STATE_WARN(intel_crtc->active != crtc->state->active,
		12785	"transitional active state does not match atomic hw state "
		12786	"(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
3746	Serge	12787
6084	serge	12788	for_each_encoder_on_crtc(dev, crtc, encoder) {
		12789	enum pipe pipe;
3746	Serge	12790
6084	serge	12791	active = encoder->get_hw_state(encoder, &pipe);
		12792	I915_STATE_WARN(active != crtc->state->active,
		12793	"[ENCODER:%i] active %i with crtc active %i\n",
		12794	encoder->base.base.id, active, crtc->state->active);
		12795
		12796	I915_STATE_WARN(active && intel_crtc->pipe != pipe,
		12797	"Encoder connected to wrong pipe %c\n",
		12798	pipe_name(pipe));
		12799
		12800	if (active)
		12801	encoder->get_config(encoder, pipe_config);
4104	Serge	12802	}
		12803
6084	serge	12804	if (!crtc->state->active)
		12805	continue;
3746	Serge	12806
6084	serge	12807	sw_config = to_intel_crtc_state(crtc->state);
		12808	if (!intel_pipe_config_compare(dev, sw_config,
		12809	pipe_config, false)) {
		12810	I915_STATE_WARN(1, "pipe state doesn't match!\n");
		12811	intel_dump_pipe_config(intel_crtc, pipe_config,
4104	Serge	12812	"[hw state]");
6084	serge	12813	intel_dump_pipe_config(intel_crtc, sw_config,
4104	Serge	12814	"[sw state]");
		12815	}
3031	serge	12816	}
		12817	}
		12818
4104	Serge	12819	static void
		12820	check_shared_dpll_state(struct drm_device *dev)
		12821	{
5060	serge	12822	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	12823	struct intel_crtc *crtc;
		12824	struct intel_dpll_hw_state dpll_hw_state;
		12825	int i;
		12826
		12827	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		12828	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		12829	int enabled_crtcs = 0, active_crtcs = 0;
		12830	bool active;
		12831
		12832	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
		12833
		12834	DRM_DEBUG_KMS("%s\n", pll->name);
		12835
		12836	active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
		12837
6084	serge	12838	I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
4104	Serge	12839	"more active pll users than references: %i vs %i\n",
5354	serge	12840	pll->active, hweight32(pll->config.crtc_mask));
6084	serge	12841	I915_STATE_WARN(pll->active && !pll->on,
4104	Serge	12842	"pll in active use but not on in sw tracking\n");
6084	serge	12843	I915_STATE_WARN(pll->on && !pll->active,
4104	Serge	12844	"pll in on but not on in use in sw tracking\n");
6084	serge	12845	I915_STATE_WARN(pll->on != active,
4104	Serge	12846	"pll on state mismatch (expected %i, found %i)\n",
		12847	pll->on, active);
		12848
5060	serge	12849	for_each_intel_crtc(dev, crtc) {
6084	serge	12850	if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
4104	Serge	12851	enabled_crtcs++;
		12852	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		12853	active_crtcs++;
		12854	}
6084	serge	12855	I915_STATE_WARN(pll->active != active_crtcs,
4104	Serge	12856	"pll active crtcs mismatch (expected %i, found %i)\n",
		12857	pll->active, active_crtcs);
6084	serge	12858	I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
4104	Serge	12859	"pll enabled crtcs mismatch (expected %i, found %i)\n",
5354	serge	12860	hweight32(pll->config.crtc_mask), enabled_crtcs);
4104	Serge	12861
6084	serge	12862	I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
4104	Serge	12863	sizeof(dpll_hw_state)),
		12864	"pll hw state mismatch\n");
		12865	}
		12866	}
		12867
6084	serge	12868	static void
		12869	intel_modeset_check_state(struct drm_device *dev,
		12870	struct drm_atomic_state *old_state)
4104	Serge	12871	{
5354	serge	12872	check_wm_state(dev);
6084	serge	12873	check_connector_state(dev, old_state);
4104	Serge	12874	check_encoder_state(dev);
6084	serge	12875	check_crtc_state(dev, old_state);
4104	Serge	12876	check_shared_dpll_state(dev);
		12877	}
		12878
6084	serge	12879	void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
4560	Serge	12880	int dotclock)
		12881	{
		12882	/*
		12883	* FDI already provided one idea for the dotclock.
		12884	* Yell if the encoder disagrees.
		12885	*/
6084	serge	12886	WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
4560	Serge	12887	"FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
6084	serge	12888	pipe_config->base.adjusted_mode.crtc_clock, dotclock);
4560	Serge	12889	}
		12890
5060	serge	12891	static void update_scanline_offset(struct intel_crtc *crtc)
		12892	{
		12893	struct drm_device *dev = crtc->base.dev;
		12894
		12895	/*
		12896	* The scanline counter increments at the leading edge of hsync.
		12897	*
		12898	* On most platforms it starts counting from vtotal-1 on the
		12899	* first active line. That means the scanline counter value is
		12900	* always one less than what we would expect. Ie. just after
		12901	* start of vblank, which also occurs at start of hsync (on the
		12902	* last active line), the scanline counter will read vblank_start-1.
		12903	*
		12904	* On gen2 the scanline counter starts counting from 1 instead
		12905	* of vtotal-1, so we have to subtract one (or rather add vtotal-1
		12906	* to keep the value positive), instead of adding one.
		12907	*
		12908	* On HSW+ the behaviour of the scanline counter depends on the output
		12909	* type. For DP ports it behaves like most other platforms, but on HDMI
		12910	* there's an extra 1 line difference. So we need to add two instead of
		12911	* one to the value.
		12912	*/
		12913	if (IS_GEN2(dev)) {
6084	serge	12914	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
5060	serge	12915	int vtotal;
		12916
6084	serge	12917	vtotal = adjusted_mode->crtc_vtotal;
		12918	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5060	serge	12919	vtotal /= 2;
		12920
		12921	crtc->scanline_offset = vtotal - 1;
		12922	} else if (HAS_DDI(dev) &&
5354	serge	12923	intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
5060	serge	12924	crtc->scanline_offset = 2;
		12925	} else
		12926	crtc->scanline_offset = 1;
		12927	}
		12928
6084	serge	12929	static void intel_modeset_clear_plls(struct drm_atomic_state *state)
5354	serge	12930	{
6084	serge	12931	struct drm_device *dev = state->dev;
		12932	struct drm_i915_private *dev_priv = to_i915(dev);
		12933	struct intel_shared_dpll_config *shared_dpll = NULL;
		12934	struct intel_crtc *intel_crtc;
		12935	struct intel_crtc_state *intel_crtc_state;
		12936	struct drm_crtc *crtc;
		12937	struct drm_crtc_state *crtc_state;
		12938	int i;
5354	serge	12939
6084	serge	12940	if (!dev_priv->display.crtc_compute_clock)
		12941	return;
5354	serge	12942
6084	serge	12943	for_each_crtc_in_state(state, crtc, crtc_state, i) {
		12944	int dpll;
5354	serge	12945
6084	serge	12946	intel_crtc = to_intel_crtc(crtc);
		12947	intel_crtc_state = to_intel_crtc_state(crtc_state);
		12948	dpll = intel_crtc_state->shared_dpll;
		12949
		12950	if (!needs_modeset(crtc_state) \|\| dpll == DPLL_ID_PRIVATE)
		12951	continue;
		12952
		12953	intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
		12954
		12955	if (!shared_dpll)
		12956	shared_dpll = intel_atomic_get_shared_dpll_state(state);
		12957
		12958	shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
5354	serge	12959	}
		12960	}
		12961
6084	serge	12962	/*
		12963	* This implements the workaround described in the "notes" section of the mode
		12964	* set sequence documentation. When going from no pipes or single pipe to
		12965	* multiple pipes, and planes are enabled after the pipe, we need to wait at
		12966	* least 2 vblanks on the first pipe before enabling planes on the second pipe.
		12967	*/
		12968	static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
3031	serge	12969	{
6084	serge	12970	struct drm_crtc_state *crtc_state;
3031	serge	12971	struct intel_crtc *intel_crtc;
6084	serge	12972	struct drm_crtc *crtc;
		12973	struct intel_crtc_state *first_crtc_state = NULL;
		12974	struct intel_crtc_state *other_crtc_state = NULL;
		12975	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
		12976	int i;
3031	serge	12977
6084	serge	12978	/* look at all crtc's that are going to be enabled in during modeset */
		12979	for_each_crtc_in_state(state, crtc, crtc_state, i) {
		12980	intel_crtc = to_intel_crtc(crtc);
3480	Serge	12981
6084	serge	12982	if (!crtc_state->active \|\| !needs_modeset(crtc_state))
		12983	continue;
3031	serge	12984
6084	serge	12985	if (first_crtc_state) {
		12986	other_crtc_state = to_intel_crtc_state(crtc_state);
		12987	break;
		12988	} else {
		12989	first_crtc_state = to_intel_crtc_state(crtc_state);
		12990	first_pipe = intel_crtc->pipe;
		12991	}
		12992	}
3031	serge	12993
6084	serge	12994	/* No workaround needed? */
		12995	if (!first_crtc_state)
		12996	return 0;
4560	Serge	12997
6084	serge	12998	/* w/a possibly needed, check how many crtc's are already enabled. */
		12999	for_each_intel_crtc(state->dev, intel_crtc) {
		13000	struct intel_crtc_state *pipe_config;
4560	Serge	13001
6084	serge	13002	pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
		13003	if (IS_ERR(pipe_config))
		13004	return PTR_ERR(pipe_config);
5354	serge	13005
6084	serge	13006	pipe_config->hsw_workaround_pipe = INVALID_PIPE;
5354	serge	13007
6084	serge	13008	if (!pipe_config->base.active \|\|
		13009	needs_modeset(&pipe_config->base))
		13010	continue;
5354	serge	13011
6084	serge	13012	/* 2 or more enabled crtcs means no need for w/a */
		13013	if (enabled_pipe != INVALID_PIPE)
		13014	return 0;
3746	Serge	13015
6084	serge	13016	enabled_pipe = intel_crtc->pipe;
3031	serge	13017	}
		13018
6084	serge	13019	if (enabled_pipe != INVALID_PIPE)
		13020	first_crtc_state->hsw_workaround_pipe = enabled_pipe;
		13021	else if (other_crtc_state)
		13022	other_crtc_state->hsw_workaround_pipe = first_pipe;
4560	Serge	13023
6084	serge	13024	return 0;
		13025	}
2327	Serge	13026
6084	serge	13027	static int intel_modeset_all_pipes(struct drm_atomic_state *state)
		13028	{
		13029	struct drm_crtc *crtc;
		13030	struct drm_crtc_state *crtc_state;
		13031	int ret = 0;
3031	serge	13032
6084	serge	13033	/* add all active pipes to the state */
		13034	for_each_crtc(state->dev, crtc) {
		13035	crtc_state = drm_atomic_get_crtc_state(state, crtc);
		13036	if (IS_ERR(crtc_state))
		13037	return PTR_ERR(crtc_state);
3243	Serge	13038
6084	serge	13039	if (!crtc_state->active \|\| needs_modeset(crtc_state))
		13040	continue;
5060	serge	13041
6084	serge	13042	crtc_state->mode_changed = true;
5060	serge	13043
6084	serge	13044	ret = drm_atomic_add_affected_connectors(state, crtc);
		13045	if (ret)
		13046	break;
3031	serge	13047
6084	serge	13048	ret = drm_atomic_add_affected_planes(state, crtc);
		13049	if (ret)
		13050	break;
5060	serge	13051	}
3031	serge	13052
		13053	return ret;
2330	Serge	13054	}
2327	Serge	13055
6084	serge	13056	static int intel_modeset_checks(struct drm_atomic_state *state)
3746	Serge	13057	{
6084	serge	13058	struct drm_device *dev = state->dev;
		13059	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	13060	int ret;
		13061
6084	serge	13062	if (!check_digital_port_conflicts(state)) {
		13063	DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
		13064	return -EINVAL;
		13065	}
3746	Serge	13066
6084	serge	13067	/*
		13068	* See if the config requires any additional preparation, e.g.
		13069	* to adjust global state with pipes off. We need to do this
		13070	* here so we can get the modeset_pipe updated config for the new
		13071	* mode set on this crtc. For other crtcs we need to use the
		13072	* adjusted_mode bits in the crtc directly.
		13073	*/
		13074	if (dev_priv->display.modeset_calc_cdclk) {
		13075	unsigned int cdclk;
3746	Serge	13076
6084	serge	13077	ret = dev_priv->display.modeset_calc_cdclk(state);
3746	Serge	13078
6084	serge	13079	cdclk = to_intel_atomic_state(state)->cdclk;
		13080	if (!ret && cdclk != dev_priv->cdclk_freq)
		13081	ret = intel_modeset_all_pipes(state);
5354	serge	13082
6084	serge	13083	if (ret < 0)
		13084	return ret;
		13085	} else
		13086	to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
5354	serge	13087
6084	serge	13088	intel_modeset_clear_plls(state);
5354	serge	13089
6084	serge	13090	if (IS_HASWELL(dev))
		13091	return haswell_mode_set_planes_workaround(state);
5354	serge	13092
6084	serge	13093	return 0;
3480	Serge	13094	}
		13095
6084	serge	13096	/**
		13097	* intel_atomic_check - validate state object
		13098	* @dev: drm device
		13099	* @state: state to validate
		13100	*/
		13101	static int intel_atomic_check(struct drm_device *dev,
		13102	struct drm_atomic_state *state)
3031	serge	13103	{
6084	serge	13104	struct drm_crtc *crtc;
		13105	struct drm_crtc_state *crtc_state;
		13106	int ret, i;
		13107	bool any_ms = false;
3031	serge	13108
6084	serge	13109	ret = drm_atomic_helper_check_modeset(dev, state);
		13110	if (ret)
		13111	return ret;
3031	serge	13112
6084	serge	13113	for_each_crtc_in_state(state, crtc, crtc_state, i) {
		13114	struct intel_crtc_state *pipe_config =
		13115	to_intel_crtc_state(crtc_state);
3031	serge	13116
6084	serge	13117	memset(&to_intel_crtc(crtc)->atomic, 0,
		13118	sizeof(struct intel_crtc_atomic_commit));
5060	serge	13119
6084	serge	13120	/* Catch I915_MODE_FLAG_INHERITED */
		13121	if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
		13122	crtc_state->mode_changed = true;
3031	serge	13123
6084	serge	13124	if (!crtc_state->enable) {
		13125	if (needs_modeset(crtc_state))
		13126	any_ms = true;
		13127	continue;
		13128	}
3031	serge	13129
6084	serge	13130	if (!needs_modeset(crtc_state))
		13131	continue;
5060	serge	13132
6084	serge	13133	/* FIXME: For only active_changed we shouldn't need to do any
		13134	* state recomputation at all. */
3031	serge	13135
6084	serge	13136	ret = drm_atomic_add_affected_connectors(state, crtc);
		13137	if (ret)
		13138	return ret;
3031	serge	13139
6084	serge	13140	ret = intel_modeset_pipe_config(crtc, pipe_config);
		13141	if (ret)
		13142	return ret;
3031	serge	13143
6084	serge	13144	if (i915.fastboot &&
		13145	intel_pipe_config_compare(state->dev,
		13146	to_intel_crtc_state(crtc->state),
		13147	pipe_config, true)) {
		13148	crtc_state->mode_changed = false;
		13149	to_intel_crtc_state(crtc_state)->update_pipe = true;
		13150	}
3031	serge	13151
6084	serge	13152	if (needs_modeset(crtc_state)) {
		13153	any_ms = true;
5060	serge	13154
6084	serge	13155	ret = drm_atomic_add_affected_planes(state, crtc);
		13156	if (ret)
		13157	return ret;
		13158	}
5060	serge	13159
6084	serge	13160	intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
		13161	needs_modeset(crtc_state) ?
		13162	"[modeset]" : "[fastset]");
3031	serge	13163	}
		13164
6084	serge	13165	if (any_ms) {
		13166	ret = intel_modeset_checks(state);
3031	serge	13167
6084	serge	13168	if (ret)
		13169	return ret;
		13170	} else
		13171	to_intel_atomic_state(state)->cdclk =
		13172	to_i915(state->dev)->cdclk_freq;
3746	Serge	13173
6084	serge	13174	return drm_atomic_helper_check_planes(state->dev, state);
3746	Serge	13175	}
		13176
6084	serge	13177	/**
		13178	* intel_atomic_commit - commit validated state object
		13179	* @dev: DRM device
		13180	* @state: the top-level driver state object
		13181	* @async: asynchronous commit
		13182	*
		13183	* This function commits a top-level state object that has been validated
		13184	* with drm_atomic_helper_check().
		13185	*
		13186	* FIXME: Atomic modeset support for i915 is not yet complete. At the moment
		13187	* we can only handle plane-related operations and do not yet support
		13188	* asynchronous commit.
		13189	*
		13190	* RETURNS
		13191	* Zero for success or -errno.
		13192	*/
		13193	static int intel_atomic_commit(struct drm_device *dev,
		13194	struct drm_atomic_state *state,
		13195	bool async)
3031	serge	13196	{
6084	serge	13197	struct drm_i915_private *dev_priv = dev->dev_private;
		13198	struct drm_crtc *crtc;
		13199	struct drm_crtc_state *crtc_state;
		13200	int ret = 0;
		13201	int i;
		13202	bool any_ms = false;
3031	serge	13203
6084	serge	13204	if (async) {
		13205	DRM_DEBUG_KMS("i915 does not yet support async commit\n");
		13206	return -EINVAL;
3031	serge	13207	}
		13208
6084	serge	13209	ret = drm_atomic_helper_prepare_planes(dev, state);
		13210	if (ret)
		13211	return ret;
3031	serge	13212
6084	serge	13213	drm_atomic_helper_swap_state(dev, state);
4104	Serge	13214
6084	serge	13215	for_each_crtc_in_state(state, crtc, crtc_state, i) {
		13216	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	13217
6084	serge	13218	if (!needs_modeset(crtc->state))
		13219	continue;
3031	serge	13220
6084	serge	13221	any_ms = true;
		13222	intel_pre_plane_update(intel_crtc);
3031	serge	13223
6084	serge	13224	if (crtc_state->active) {
		13225	intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
		13226	dev_priv->display.crtc_disable(crtc);
		13227	intel_crtc->active = false;
		13228	intel_disable_shared_dpll(intel_crtc);
3031	serge	13229	}
6084	serge	13230	}
3031	serge	13231
6084	serge	13232	/* Only after disabling all output pipelines that will be changed can we
		13233	* update the the output configuration. */
		13234	intel_modeset_update_crtc_state(state);
3031	serge	13235
6084	serge	13236	if (any_ms) {
		13237	intel_shared_dpll_commit(state);
3031	serge	13238
6084	serge	13239	drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
		13240	modeset_update_crtc_power_domains(state);
3031	serge	13241	}
		13242
6084	serge	13243	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
		13244	for_each_crtc_in_state(state, crtc, crtc_state, i) {
		13245	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		13246	bool modeset = needs_modeset(crtc->state);
		13247	bool update_pipe = !modeset &&
		13248	to_intel_crtc_state(crtc->state)->update_pipe;
		13249	unsigned long put_domains = 0;
5060	serge	13250
6084	serge	13251	if (modeset && crtc->state->active) {
		13252	update_scanline_offset(to_intel_crtc(crtc));
		13253	dev_priv->display.crtc_enable(crtc);
3031	serge	13254	}
		13255
6084	serge	13256	if (update_pipe) {
		13257	put_domains = modeset_get_crtc_power_domains(crtc);
3031	serge	13258
6084	serge	13259	/* make sure intel_modeset_check_state runs */
		13260	any_ms = true;
3031	serge	13261	}
4560	Serge	13262
6084	serge	13263	if (!modeset)
		13264	intel_pre_plane_update(intel_crtc);
4560	Serge	13265
6084	serge	13266	drm_atomic_helper_commit_planes_on_crtc(crtc_state);
3031	serge	13267
6084	serge	13268	if (put_domains)
		13269	modeset_put_power_domains(dev_priv, put_domains);
5060	serge	13270
6084	serge	13271	intel_post_plane_update(intel_crtc);
5060	serge	13272	}
		13273
6084	serge	13274	/* FIXME: add subpixel order */
3031	serge	13275
6088	serge	13276	drm_atomic_helper_wait_for_vblanks(dev, state);
6084	serge	13277	drm_atomic_helper_cleanup_planes(dev, state);
5060	serge	13278
6084	serge	13279	if (any_ms)
		13280	intel_modeset_check_state(dev, state);
5060	serge	13281
6084	serge	13282	drm_atomic_state_free(state);
5060	serge	13283
6084	serge	13284	return 0;
5060	serge	13285	}
		13286
6084	serge	13287	void intel_crtc_restore_mode(struct drm_crtc *crtc)
3031	serge	13288	{
6084	serge	13289	struct drm_device *dev = crtc->dev;
		13290	struct drm_atomic_state *state;
		13291	struct drm_crtc_state *crtc_state;
3031	serge	13292	int ret;
		13293
6084	serge	13294	state = drm_atomic_state_alloc(dev);
		13295	if (!state) {
		13296	DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
		13297	crtc->base.id);
		13298	return;
3031	serge	13299	}
		13300
6084	serge	13301	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
3031	serge	13302
6084	serge	13303	retry:
		13304	crtc_state = drm_atomic_get_crtc_state(state, crtc);
		13305	ret = PTR_ERR_OR_ZERO(crtc_state);
		13306	if (!ret) {
		13307	if (!crtc_state->active)
		13308	goto out;
3031	serge	13309
6084	serge	13310	crtc_state->mode_changed = true;
		13311	ret = drm_atomic_commit(state);
5354	serge	13312	}
		13313
6084	serge	13314	if (ret == -EDEADLK) {
		13315	drm_atomic_state_clear(state);
		13316	drm_modeset_backoff(state->acquire_ctx);
		13317	goto retry;
3031	serge	13318	}
		13319
6084	serge	13320	if (ret)
		13321	out:
		13322	drm_atomic_state_free(state);
		13323	}
3031	serge	13324
6084	serge	13325	#undef for_each_intel_crtc_masked
5060	serge	13326
2330	Serge	13327	static const struct drm_crtc_funcs intel_crtc_funcs = {
		13328	.gamma_set = intel_crtc_gamma_set,
6084	serge	13329	.set_config = drm_atomic_helper_set_config,
2330	Serge	13330	.destroy = intel_crtc_destroy,
6320	serge	13331	.page_flip = intel_crtc_page_flip,
6084	serge	13332	.atomic_duplicate_state = intel_crtc_duplicate_state,
		13333	.atomic_destroy_state = intel_crtc_destroy_state,
2330	Serge	13334	};
2327	Serge	13335
4104	Serge	13336	static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
		13337	struct intel_shared_dpll *pll,
		13338	struct intel_dpll_hw_state *hw_state)
3031	serge	13339	{
4104	Serge	13340	uint32_t val;
3031	serge	13341
5354	serge	13342	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
5060	serge	13343	return false;
		13344
4104	Serge	13345	val = I915_READ(PCH_DPLL(pll->id));
		13346	hw_state->dpll = val;
		13347	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
		13348	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
		13349
		13350	return val & DPLL_VCO_ENABLE;
		13351	}
		13352
		13353	static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
		13354	struct intel_shared_dpll *pll)
		13355	{
5354	serge	13356	I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
		13357	I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
4104	Serge	13358	}
		13359
		13360	static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
		13361	struct intel_shared_dpll *pll)
		13362	{
		13363	/* PCH refclock must be enabled first */
4560	Serge	13364	ibx_assert_pch_refclk_enabled(dev_priv);
4104	Serge	13365
5354	serge	13366	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
4104	Serge	13367
		13368	/* Wait for the clocks to stabilize. */
		13369	POSTING_READ(PCH_DPLL(pll->id));
		13370	udelay(150);
		13371
		13372	/* The pixel multiplier can only be updated once the
		13373	* DPLL is enabled and the clocks are stable.
		13374	*
		13375	* So write it again.
		13376	*/
5354	serge	13377	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
4104	Serge	13378	POSTING_READ(PCH_DPLL(pll->id));
		13379	udelay(200);
		13380	}
		13381
		13382	static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
		13383	struct intel_shared_dpll *pll)
		13384	{
		13385	struct drm_device *dev = dev_priv->dev;
		13386	struct intel_crtc *crtc;
		13387
		13388	/* Make sure no transcoder isn't still depending on us. */
5060	serge	13389	for_each_intel_crtc(dev, crtc) {
4104	Serge	13390	if (intel_crtc_to_shared_dpll(crtc) == pll)
		13391	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
3031	serge	13392	}
		13393
4104	Serge	13394	I915_WRITE(PCH_DPLL(pll->id), 0);
		13395	POSTING_READ(PCH_DPLL(pll->id));
		13396	udelay(200);
		13397	}
		13398
		13399	static char *ibx_pch_dpll_names[] = {
		13400	"PCH DPLL A",
		13401	"PCH DPLL B",
		13402	};
		13403
		13404	static void ibx_pch_dpll_init(struct drm_device *dev)
		13405	{
		13406	struct drm_i915_private *dev_priv = dev->dev_private;
		13407	int i;
		13408
		13409	dev_priv->num_shared_dpll = 2;
		13410
		13411	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		13412	dev_priv->shared_dplls[i].id = i;
		13413	dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
		13414	dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
		13415	dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
		13416	dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
		13417	dev_priv->shared_dplls[i].get_hw_state =
		13418	ibx_pch_dpll_get_hw_state;
3031	serge	13419	}
		13420	}
		13421
4104	Serge	13422	static void intel_shared_dpll_init(struct drm_device *dev)
		13423	{
		13424	struct drm_i915_private *dev_priv = dev->dev_private;
		13425
5060	serge	13426	if (HAS_DDI(dev))
		13427	intel_ddi_pll_init(dev);
		13428	else if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
4104	Serge	13429	ibx_pch_dpll_init(dev);
		13430	else
		13431	dev_priv->num_shared_dpll = 0;
		13432
		13433	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
		13434	}
		13435
6084	serge	13436	/**
		13437	* intel_prepare_plane_fb - Prepare fb for usage on plane
		13438	* @plane: drm plane to prepare for
		13439	* @fb: framebuffer to prepare for presentation
		13440	*
		13441	* Prepares a framebuffer for usage on a display plane. Generally this
		13442	* involves pinning the underlying object and updating the frontbuffer tracking
		13443	* bits. Some older platforms need special physical address handling for
		13444	* cursor planes.
		13445	*
		13446	* Returns 0 on success, negative error code on failure.
		13447	*/
		13448	int
		13449	intel_prepare_plane_fb(struct drm_plane *plane,
		13450	const struct drm_plane_state *new_state)
5060	serge	13451	{
		13452	struct drm_device *dev = plane->dev;
6084	serge	13453	struct drm_framebuffer *fb = new_state->fb;
		13454	struct intel_plane *intel_plane = to_intel_plane(plane);
		13455	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
		13456	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
		13457	int ret = 0;
5060	serge	13458
6084	serge	13459	if (!obj)
5060	serge	13460	return 0;
		13461
6084	serge	13462	mutex_lock(&dev->struct_mutex);
5060	serge	13463
6084	serge	13464	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
		13465	INTEL_INFO(dev)->cursor_needs_physical) {
		13466	int align = IS_I830(dev) ? 16 * 1024 : 256;
		13467	ret = 1;
		13468	if (ret)
		13469	DRM_DEBUG_KMS("failed to attach phys object\n");
		13470	} else {
		13471	ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
		13472	}
5060	serge	13473
6084	serge	13474	if (ret == 0)
		13475	i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
5060	serge	13476
		13477	mutex_unlock(&dev->struct_mutex);
		13478
6084	serge	13479	return ret;
5060	serge	13480	}
		13481
6084	serge	13482	/**
		13483	* intel_cleanup_plane_fb - Cleans up an fb after plane use
		13484	* @plane: drm plane to clean up for
		13485	* @fb: old framebuffer that was on plane
		13486	*
		13487	* Cleans up a framebuffer that has just been removed from a plane.
		13488	*/
		13489	void
		13490	intel_cleanup_plane_fb(struct drm_plane *plane,
		13491	const struct drm_plane_state *old_state)
5060	serge	13492	{
6084	serge	13493	struct drm_device *dev = plane->dev;
		13494	struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
5354	serge	13495
6084	serge	13496	if (!obj)
		13497	return;
		13498
		13499	if (plane->type != DRM_PLANE_TYPE_CURSOR \|\|
		13500	!INTEL_INFO(dev)->cursor_needs_physical) {
		13501	mutex_lock(&dev->struct_mutex);
		13502	intel_unpin_fb_obj(old_state->fb, old_state);
		13503	mutex_unlock(&dev->struct_mutex);
		13504	}
5354	serge	13505	}
		13506
6084	serge	13507	int
		13508	skl_max_scale(struct intel_crtc intel_crtc, struct intel_crtc_state crtc_state)
5354	serge	13509	{
6084	serge	13510	int max_scale;
		13511	struct drm_device *dev;
		13512	struct drm_i915_private *dev_priv;
		13513	int crtc_clock, cdclk;
5060	serge	13514
6084	serge	13515	if (!intel_crtc \|\| !crtc_state)
		13516	return DRM_PLANE_HELPER_NO_SCALING;
5060	serge	13517
6084	serge	13518	dev = intel_crtc->base.dev;
		13519	dev_priv = dev->dev_private;
		13520	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
		13521	cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
5060	serge	13522
6084	serge	13523	if (!crtc_clock \|\| !cdclk)
		13524	return DRM_PLANE_HELPER_NO_SCALING;
		13525
		13526	/*
		13527	* skl max scale is lower of:
		13528	* close to 3 but not 3, -1 is for that purpose
		13529	* or
		13530	* cdclk/crtc_clock
		13531	*/
		13532	max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
		13533
		13534	return max_scale;
		13535	}
		13536
		13537	static int
		13538	intel_check_primary_plane(struct drm_plane *plane,
		13539	struct intel_crtc_state *crtc_state,
		13540	struct intel_plane_state *state)
		13541	{
		13542	struct drm_crtc *crtc = state->base.crtc;
		13543	struct drm_framebuffer *fb = state->base.fb;
		13544	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
		13545	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
		13546	bool can_position = false;
		13547
6320	serge	13548	if (INTEL_INFO(plane->dev)->gen >= 9) {
6084	serge	13549	/* use scaler when colorkey is not required */
6320	serge	13550	if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
6084	serge	13551	min_scale = 1;
		13552	max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
6320	serge	13553	}
6084	serge	13554	can_position = true;
5354	serge	13555	}
5060	serge	13556
6084	serge	13557	return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
		13558	&state->dst, &state->clip,
		13559	min_scale, max_scale,
		13560	can_position, true,
		13561	&state->visible);
5354	serge	13562	}
		13563
		13564	static void
		13565	intel_commit_primary_plane(struct drm_plane *plane,
		13566	struct intel_plane_state *state)
		13567	{
6084	serge	13568	struct drm_crtc *crtc = state->base.crtc;
		13569	struct drm_framebuffer *fb = state->base.fb;
		13570	struct drm_device *dev = plane->dev;
5354	serge	13571	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	13572	struct intel_crtc *intel_crtc;
5354	serge	13573	struct drm_rect *src = &state->src;
		13574
6084	serge	13575	crtc = crtc ? crtc : plane->crtc;
		13576	intel_crtc = to_intel_crtc(crtc);
		13577
		13578	plane->fb = fb;
5354	serge	13579	crtc->x = src->x1 >> 16;
		13580	crtc->y = src->y1 >> 16;
		13581
6084	serge	13582	if (!crtc->state->active)
		13583	return;
5354	serge	13584
6084	serge	13585	dev_priv->display.update_primary_plane(crtc, fb,
		13586	state->src.x1 >> 16,
		13587	state->src.y1 >> 16);
		13588	}
5060	serge	13589
6084	serge	13590	static void
		13591	intel_disable_primary_plane(struct drm_plane *plane,
		13592	struct drm_crtc *crtc)
		13593	{
		13594	struct drm_device *dev = plane->dev;
		13595	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	13596
6084	serge	13597	dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
		13598	}
5060	serge	13599
6084	serge	13600	static void intel_begin_crtc_commit(struct drm_crtc *crtc,
		13601	struct drm_crtc_state *old_crtc_state)
		13602	{
		13603	struct drm_device *dev = crtc->dev;
		13604	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		13605	struct intel_crtc_state *old_intel_state =
		13606	to_intel_crtc_state(old_crtc_state);
		13607	bool modeset = needs_modeset(crtc->state);
5060	serge	13608
6084	serge	13609	if (intel_crtc->atomic.update_wm_pre)
		13610	intel_update_watermarks(crtc);
5060	serge	13611
6084	serge	13612	/* Perform vblank evasion around commit operation */
		13613	if (crtc->state->active)
		13614	intel_pipe_update_start(intel_crtc);
5354	serge	13615
6084	serge	13616	if (modeset)
		13617	return;
5354	serge	13618
6084	serge	13619	if (to_intel_crtc_state(crtc->state)->update_pipe)
		13620	intel_update_pipe_config(intel_crtc, old_intel_state);
		13621	else if (INTEL_INFO(dev)->gen >= 9)
		13622	skl_detach_scalers(intel_crtc);
5354	serge	13623	}
5060	serge	13624
6084	serge	13625	static void intel_finish_crtc_commit(struct drm_crtc *crtc,
		13626	struct drm_crtc_state *old_crtc_state)
5354	serge	13627	{
		13628	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	13629
6084	serge	13630	if (crtc->state->active)
		13631	intel_pipe_update_end(intel_crtc);
5060	serge	13632	}
		13633
6084	serge	13634	/**
		13635	* intel_plane_destroy - destroy a plane
		13636	* @plane: plane to destroy
		13637	*
		13638	* Common destruction function for all types of planes (primary, cursor,
		13639	* sprite).
		13640	*/
		13641	void intel_plane_destroy(struct drm_plane *plane)
5060	serge	13642	{
		13643	struct intel_plane *intel_plane = to_intel_plane(plane);
		13644	drm_plane_cleanup(plane);
		13645	kfree(intel_plane);
		13646	}
		13647
6084	serge	13648	const struct drm_plane_funcs intel_plane_funcs = {
		13649	.update_plane = drm_atomic_helper_update_plane,
		13650	.disable_plane = drm_atomic_helper_disable_plane,
5060	serge	13651	.destroy = intel_plane_destroy,
6084	serge	13652	.set_property = drm_atomic_helper_plane_set_property,
		13653	.atomic_get_property = intel_plane_atomic_get_property,
		13654	.atomic_set_property = intel_plane_atomic_set_property,
		13655	.atomic_duplicate_state = intel_plane_duplicate_state,
		13656	.atomic_destroy_state = intel_plane_destroy_state,
		13657
5060	serge	13658	};
		13659
		13660	static struct drm_plane intel_primary_plane_create(struct drm_device dev,
		13661	int pipe)
		13662	{
		13663	struct intel_plane *primary;
6084	serge	13664	struct intel_plane_state *state;
5060	serge	13665	const uint32_t *intel_primary_formats;
6084	serge	13666	unsigned int num_formats;
5060	serge	13667
		13668	primary = kzalloc(sizeof(*primary), GFP_KERNEL);
		13669	if (primary == NULL)
		13670	return NULL;
		13671
6084	serge	13672	state = intel_create_plane_state(&primary->base);
		13673	if (!state) {
		13674	kfree(primary);
		13675	return NULL;
		13676	}
		13677	primary->base.state = &state->base;
		13678
5060	serge	13679	primary->can_scale = false;
		13680	primary->max_downscale = 1;
6084	serge	13681	if (INTEL_INFO(dev)->gen >= 9) {
		13682	primary->can_scale = true;
		13683	state->scaler_id = -1;
		13684	}
5060	serge	13685	primary->pipe = pipe;
		13686	primary->plane = pipe;
6084	serge	13687	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
		13688	primary->check_plane = intel_check_primary_plane;
		13689	primary->commit_plane = intel_commit_primary_plane;
		13690	primary->disable_plane = intel_disable_primary_plane;
5060	serge	13691	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
		13692	primary->plane = !pipe;
		13693
6084	serge	13694	if (INTEL_INFO(dev)->gen >= 9) {
		13695	intel_primary_formats = skl_primary_formats;
		13696	num_formats = ARRAY_SIZE(skl_primary_formats);
		13697	} else if (INTEL_INFO(dev)->gen >= 4) {
		13698	intel_primary_formats = i965_primary_formats;
		13699	num_formats = ARRAY_SIZE(i965_primary_formats);
5060	serge	13700	} else {
6084	serge	13701	intel_primary_formats = i8xx_primary_formats;
		13702	num_formats = ARRAY_SIZE(i8xx_primary_formats);
5060	serge	13703	}
		13704
		13705	drm_universal_plane_init(dev, &primary->base, 0,
6084	serge	13706	&intel_plane_funcs,
5060	serge	13707	intel_primary_formats, num_formats,
		13708	DRM_PLANE_TYPE_PRIMARY);
5354	serge	13709
6084	serge	13710	if (INTEL_INFO(dev)->gen >= 4)
		13711	intel_create_rotation_property(dev, primary);
5354	serge	13712
6084	serge	13713	drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
		13714
5060	serge	13715	return &primary->base;
		13716	}
		13717
6084	serge	13718	void intel_create_rotation_property(struct drm_device dev, struct intel_plane plane)
5060	serge	13719	{
6084	serge	13720	if (!dev->mode_config.rotation_property) {
		13721	unsigned long flags = BIT(DRM_ROTATE_0) \|
		13722	BIT(DRM_ROTATE_180);
5060	serge	13723
6084	serge	13724	if (INTEL_INFO(dev)->gen >= 9)
		13725	flags \|= BIT(DRM_ROTATE_90) \| BIT(DRM_ROTATE_270);
5060	serge	13726
6084	serge	13727	dev->mode_config.rotation_property =
		13728	drm_mode_create_rotation_property(dev, flags);
		13729	}
		13730	if (dev->mode_config.rotation_property)
		13731	drm_object_attach_property(&plane->base.base,
		13732	dev->mode_config.rotation_property,
		13733	plane->base.state->rotation);
5060	serge	13734	}
		13735
		13736	static int
5354	serge	13737	intel_check_cursor_plane(struct drm_plane *plane,
6084	serge	13738	struct intel_crtc_state *crtc_state,
5354	serge	13739	struct intel_plane_state *state)
5060	serge	13740	{
6084	serge	13741	struct drm_crtc *crtc = crtc_state->base.crtc;
		13742	struct drm_framebuffer *fb = state->base.fb;
5354	serge	13743	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6084	serge	13744	enum pipe pipe = to_intel_plane(plane)->pipe;
5354	serge	13745	unsigned stride;
5060	serge	13746	int ret;
		13747
6084	serge	13748	ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
		13749	&state->dst, &state->clip,
5060	serge	13750	DRM_PLANE_HELPER_NO_SCALING,
		13751	DRM_PLANE_HELPER_NO_SCALING,
5354	serge	13752	true, true, &state->visible);
5060	serge	13753	if (ret)
		13754	return ret;
		13755
5354	serge	13756	/* if we want to turn off the cursor ignore width and height */
		13757	if (!obj)
		13758	return 0;
		13759
		13760	/* Check for which cursor types we support */
6084	serge	13761	if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
		13762	DRM_DEBUG("Cursor dimension %dx%d not supported\n",
		13763	state->base.crtc_w, state->base.crtc_h);
5354	serge	13764	return -EINVAL;
		13765	}
		13766
6084	serge	13767	stride = roundup_pow_of_two(state->base.crtc_w) * 4;
		13768	if (obj->base.size < stride * state->base.crtc_h) {
5354	serge	13769	DRM_DEBUG_KMS("buffer is too small\n");
		13770	return -ENOMEM;
		13771	}
		13772
6084	serge	13773	if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
5354	serge	13774	DRM_DEBUG_KMS("cursor cannot be tiled\n");
6084	serge	13775	return -EINVAL;
5354	serge	13776	}
		13777
6084	serge	13778	/*
		13779	* There's something wrong with the cursor on CHV pipe C.
		13780	* If it straddles the left edge of the screen then
		13781	* moving it away from the edge or disabling it often
		13782	* results in a pipe underrun, and often that can lead to
		13783	* dead pipe (constant underrun reported, and it scans
		13784	* out just a solid color). To recover from that, the
		13785	* display power well must be turned off and on again.
		13786	* Refuse the put the cursor into that compromised position.
		13787	*/
		13788	if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
		13789	state->visible && state->base.crtc_x < 0) {
		13790	DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
		13791	return -EINVAL;
		13792	}
		13793
		13794	return 0;
5354	serge	13795	}
		13796
6084	serge	13797	static void
		13798	intel_disable_cursor_plane(struct drm_plane *plane,
		13799	struct drm_crtc *crtc)
5354	serge	13800	{
6084	serge	13801	intel_crtc_update_cursor(crtc, false);
5060	serge	13802	}
5354	serge	13803
6084	serge	13804	static void
		13805	intel_commit_cursor_plane(struct drm_plane *plane,
		13806	struct intel_plane_state *state)
5354	serge	13807	{
6084	serge	13808	struct drm_crtc *crtc = state->base.crtc;
		13809	struct drm_device *dev = plane->dev;
		13810	struct intel_crtc *intel_crtc;
		13811	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
		13812	uint32_t addr;
5354	serge	13813
6084	serge	13814	crtc = crtc ? crtc : plane->crtc;
		13815	intel_crtc = to_intel_crtc(crtc);
5354	serge	13816
6084	serge	13817	if (!obj)
		13818	addr = 0;
		13819	else if (!INTEL_INFO(dev)->cursor_needs_physical)
		13820	addr = i915_gem_obj_ggtt_offset(obj);
		13821	else
		13822	addr = obj->phys_handle->busaddr;
5354	serge	13823
6084	serge	13824	intel_crtc->cursor_addr = addr;
5354	serge	13825
6084	serge	13826	if (crtc->state->active)
		13827	intel_crtc_update_cursor(crtc, state->visible);
5354	serge	13828	}
		13829
5060	serge	13830	static struct drm_plane intel_cursor_plane_create(struct drm_device dev,
		13831	int pipe)
		13832	{
		13833	struct intel_plane *cursor;
6084	serge	13834	struct intel_plane_state *state;
5060	serge	13835
		13836	cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
		13837	if (cursor == NULL)
		13838	return NULL;
		13839
6084	serge	13840	state = intel_create_plane_state(&cursor->base);
		13841	if (!state) {
		13842	kfree(cursor);
		13843	return NULL;
		13844	}
		13845	cursor->base.state = &state->base;
		13846
5060	serge	13847	cursor->can_scale = false;
		13848	cursor->max_downscale = 1;
		13849	cursor->pipe = pipe;
		13850	cursor->plane = pipe;
6084	serge	13851	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
		13852	cursor->check_plane = intel_check_cursor_plane;
		13853	cursor->commit_plane = intel_commit_cursor_plane;
		13854	cursor->disable_plane = intel_disable_cursor_plane;
5060	serge	13855
		13856	drm_universal_plane_init(dev, &cursor->base, 0,
6084	serge	13857	&intel_plane_funcs,
5060	serge	13858	intel_cursor_formats,
		13859	ARRAY_SIZE(intel_cursor_formats),
		13860	DRM_PLANE_TYPE_CURSOR);
5354	serge	13861
		13862	if (INTEL_INFO(dev)->gen >= 4) {
		13863	if (!dev->mode_config.rotation_property)
		13864	dev->mode_config.rotation_property =
		13865	drm_mode_create_rotation_property(dev,
		13866	BIT(DRM_ROTATE_0) \|
		13867	BIT(DRM_ROTATE_180));
		13868	if (dev->mode_config.rotation_property)
		13869	drm_object_attach_property(&cursor->base.base,
		13870	dev->mode_config.rotation_property,
6084	serge	13871	state->base.rotation);
5354	serge	13872	}
		13873
6084	serge	13874	if (INTEL_INFO(dev)->gen >=9)
		13875	state->scaler_id = -1;
		13876
		13877	drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
		13878
5060	serge	13879	return &cursor->base;
		13880	}
		13881
6084	serge	13882	static void skl_init_scalers(struct drm_device dev, struct intel_crtc intel_crtc,
		13883	struct intel_crtc_state *crtc_state)
		13884	{
		13885	int i;
		13886	struct intel_scaler *intel_scaler;
		13887	struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
		13888
		13889	for (i = 0; i < intel_crtc->num_scalers; i++) {
		13890	intel_scaler = &scaler_state->scalers[i];
		13891	intel_scaler->in_use = 0;
		13892	intel_scaler->mode = PS_SCALER_MODE_DYN;
		13893	}
		13894
		13895	scaler_state->scaler_id = -1;
		13896	}
		13897
2330	Serge	13898	static void intel_crtc_init(struct drm_device *dev, int pipe)
		13899	{
5060	serge	13900	struct drm_i915_private *dev_priv = dev->dev_private;
2330	Serge	13901	struct intel_crtc *intel_crtc;
6084	serge	13902	struct intel_crtc_state *crtc_state = NULL;
5060	serge	13903	struct drm_plane *primary = NULL;
		13904	struct drm_plane *cursor = NULL;
		13905	int i, ret;
2327	Serge	13906
4560	Serge	13907	intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
2330	Serge	13908	if (intel_crtc == NULL)
		13909	return;
2327	Serge	13910
6084	serge	13911	crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
		13912	if (!crtc_state)
		13913	goto fail;
		13914	intel_crtc->config = crtc_state;
		13915	intel_crtc->base.state = &crtc_state->base;
		13916	crtc_state->base.crtc = &intel_crtc->base;
		13917
		13918	/* initialize shared scalers */
		13919	if (INTEL_INFO(dev)->gen >= 9) {
		13920	if (pipe == PIPE_C)
		13921	intel_crtc->num_scalers = 1;
		13922	else
		13923	intel_crtc->num_scalers = SKL_NUM_SCALERS;
		13924
		13925	skl_init_scalers(dev, intel_crtc, crtc_state);
		13926	}
		13927
5060	serge	13928	primary = intel_primary_plane_create(dev, pipe);
		13929	if (!primary)
		13930	goto fail;
2327	Serge	13931
5060	serge	13932	cursor = intel_cursor_plane_create(dev, pipe);
		13933	if (!cursor)
		13934	goto fail;
		13935
		13936	ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
		13937	cursor, &intel_crtc_funcs);
		13938	if (ret)
		13939	goto fail;
		13940
2330	Serge	13941	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		13942	for (i = 0; i < 256; i++) {
		13943	intel_crtc->lut_r[i] = i;
		13944	intel_crtc->lut_g[i] = i;
		13945	intel_crtc->lut_b[i] = i;
		13946	}
2327	Serge	13947
4560	Serge	13948	/*
		13949	* On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
5060	serge	13950	* is hooked to pipe B. Hence we want plane A feeding pipe B.
4560	Serge	13951	*/
2330	Serge	13952	intel_crtc->pipe = pipe;
		13953	intel_crtc->plane = pipe;
4560	Serge	13954	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
2330	Serge	13955	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		13956	intel_crtc->plane = !pipe;
		13957	}
2327	Serge	13958
5060	serge	13959	intel_crtc->cursor_base = ~0;
		13960	intel_crtc->cursor_cntl = ~0;
5354	serge	13961	intel_crtc->cursor_size = ~0;
5060	serge	13962
6084	serge	13963	intel_crtc->wm.cxsr_allowed = true;
		13964
2330	Serge	13965	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		13966	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		13967	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		13968	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	13969
2330	Serge	13970	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5060	serge	13971
		13972	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
		13973	return;
		13974
		13975	fail:
		13976	if (primary)
		13977	drm_plane_cleanup(primary);
		13978	if (cursor)
		13979	drm_plane_cleanup(cursor);
6084	serge	13980	kfree(crtc_state);
5060	serge	13981	kfree(intel_crtc);
2330	Serge	13982	}
2327	Serge	13983
4560	Serge	13984	enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
		13985	{
		13986	struct drm_encoder *encoder = connector->base.encoder;
5060	serge	13987	struct drm_device *dev = connector->base.dev;
4560	Serge	13988
5060	serge	13989	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4560	Serge	13990
5354	serge	13991	if (!encoder \|\| WARN_ON(!encoder->crtc))
4560	Serge	13992	return INVALID_PIPE;
		13993
		13994	return to_intel_crtc(encoder->crtc)->pipe;
		13995	}
		13996
3031	serge	13997	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		13998	struct drm_file *file)
		13999	{
		14000	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5060	serge	14001	struct drm_crtc *drmmode_crtc;
3031	serge	14002	struct intel_crtc *crtc;
2327	Serge	14003
5060	serge	14004	drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
2327	Serge	14005
5060	serge	14006	if (!drmmode_crtc) {
3031	serge	14007	DRM_ERROR("no such CRTC id\n");
4560	Serge	14008	return -ENOENT;
3031	serge	14009	}
2327	Serge	14010
5060	serge	14011	crtc = to_intel_crtc(drmmode_crtc);
3031	serge	14012	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	14013
3031	serge	14014	return 0;
		14015	}
2327	Serge	14016
3031	serge	14017	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	14018	{
3031	serge	14019	struct drm_device *dev = encoder->base.dev;
		14020	struct intel_encoder *source_encoder;
2330	Serge	14021	int index_mask = 0;
		14022	int entry = 0;
2327	Serge	14023
5354	serge	14024	for_each_intel_encoder(dev, source_encoder) {
5060	serge	14025	if (encoders_cloneable(encoder, source_encoder))
2330	Serge	14026	index_mask \|= (1 << entry);
3031	serge	14027
2330	Serge	14028	entry++;
		14029	}
2327	Serge	14030
2330	Serge	14031	return index_mask;
		14032	}
2327	Serge	14033
2330	Serge	14034	static bool has_edp_a(struct drm_device *dev)
		14035	{
		14036	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	14037
2330	Serge	14038	if (!IS_MOBILE(dev))
		14039	return false;
2327	Serge	14040
2330	Serge	14041	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		14042	return false;
2327	Serge	14043
5060	serge	14044	if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
2330	Serge	14045	return false;
2327	Serge	14046
2330	Serge	14047	return true;
		14048	}
2327	Serge	14049
5060	serge	14050	static bool intel_crt_present(struct drm_device *dev)
		14051	{
		14052	struct drm_i915_private *dev_priv = dev->dev_private;
		14053
5354	serge	14054	if (INTEL_INFO(dev)->gen >= 9)
5060	serge	14055	return false;
		14056
5354	serge	14057	if (IS_HSW_ULT(dev) \|\| IS_BDW_ULT(dev))
		14058	return false;
		14059
5060	serge	14060	if (IS_CHERRYVIEW(dev))
		14061	return false;
		14062
		14063	if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
		14064	return false;
		14065
		14066	return true;
		14067	}
		14068
2330	Serge	14069	static void intel_setup_outputs(struct drm_device *dev)
		14070	{
		14071	struct drm_i915_private *dev_priv = dev->dev_private;
		14072	struct intel_encoder *encoder;
		14073	bool dpd_is_edp = false;
2327	Serge	14074
4104	Serge	14075	intel_lvds_init(dev);
2327	Serge	14076
5060	serge	14077	if (intel_crt_present(dev))
6084	serge	14078	intel_crt_init(dev);
2327	Serge	14079
6084	serge	14080	if (IS_BROXTON(dev)) {
		14081	/*
		14082	* FIXME: Broxton doesn't support port detection via the
		14083	* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
		14084	* detect the ports.
		14085	*/
		14086	intel_ddi_init(dev, PORT_A);
		14087	intel_ddi_init(dev, PORT_B);
		14088	intel_ddi_init(dev, PORT_C);
		14089	} else if (HAS_DDI(dev)) {
2330	Serge	14090	int found;
2327	Serge	14091
6084	serge	14092	/*
		14093	* Haswell uses DDI functions to detect digital outputs.
		14094	* On SKL pre-D0 the strap isn't connected, so we assume
		14095	* it's there.
		14096	*/
		14097	found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
		14098	/* WaIgnoreDDIAStrap: skl */
		14099	if (found \|\| IS_SKYLAKE(dev))
3031	serge	14100	intel_ddi_init(dev, PORT_A);
		14101
		14102	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		14103	* register */
		14104	found = I915_READ(SFUSE_STRAP);
		14105
		14106	if (found & SFUSE_STRAP_DDIB_DETECTED)
		14107	intel_ddi_init(dev, PORT_B);
		14108	if (found & SFUSE_STRAP_DDIC_DETECTED)
		14109	intel_ddi_init(dev, PORT_C);
		14110	if (found & SFUSE_STRAP_DDID_DETECTED)
		14111	intel_ddi_init(dev, PORT_D);
6084	serge	14112	/*
		14113	* On SKL we don't have a way to detect DDI-E so we rely on VBT.
		14114	*/
		14115	if (IS_SKYLAKE(dev) &&
		14116	(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp \|\|
		14117	dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi \|\|
		14118	dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
		14119	intel_ddi_init(dev, PORT_E);
		14120
3031	serge	14121	} else if (HAS_PCH_SPLIT(dev)) {
		14122	int found;
4560	Serge	14123	dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
3031	serge	14124
3243	Serge	14125	if (has_edp_a(dev))
		14126	intel_dp_init(dev, DP_A, PORT_A);
		14127
3746	Serge	14128	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
2330	Serge	14129	/* PCH SDVOB multiplex with HDMIB */
3031	serge	14130	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	14131	if (!found)
3746	Serge	14132	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
2330	Serge	14133	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	14134	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	14135	}
2327	Serge	14136
3746	Serge	14137	if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
		14138	intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
2327	Serge	14139
3746	Serge	14140	if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
		14141	intel_hdmi_init(dev, PCH_HDMID, PORT_D);
2327	Serge	14142
2330	Serge	14143	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	14144	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	14145
3243	Serge	14146	if (I915_READ(PCH_DP_D) & DP_DETECTED)
3031	serge	14147	intel_dp_init(dev, PCH_DP_D, PORT_D);
		14148	} else if (IS_VALLEYVIEW(dev)) {
5354	serge	14149	/*
		14150	* The DP_DETECTED bit is the latched state of the DDC
		14151	* SDA pin at boot. However since eDP doesn't require DDC
		14152	* (no way to plug in a DP->HDMI dongle) the DDC pins for
		14153	* eDP ports may have been muxed to an alternate function.
		14154	* Thus we can't rely on the DP_DETECTED bit alone to detect
		14155	* eDP ports. Consult the VBT as well as DP_DETECTED to
		14156	* detect eDP ports.
		14157	*/
6084	serge	14158	if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
		14159	!intel_dp_is_edp(dev, PORT_B))
		14160	intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
		14161	if (I915_READ(VLV_DP_B) & DP_DETECTED \|\|
5354	serge	14162	intel_dp_is_edp(dev, PORT_B))
6084	serge	14163	intel_dp_init(dev, VLV_DP_B, PORT_B);
4560	Serge	14164
6084	serge	14165	if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
		14166	!intel_dp_is_edp(dev, PORT_C))
		14167	intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
		14168	if (I915_READ(VLV_DP_C) & DP_DETECTED \|\|
5354	serge	14169	intel_dp_is_edp(dev, PORT_C))
6084	serge	14170	intel_dp_init(dev, VLV_DP_C, PORT_C);
3243	Serge	14171
5060	serge	14172	if (IS_CHERRYVIEW(dev)) {
5354	serge	14173	/* eDP not supported on port D, so don't check VBT */
6084	serge	14174	if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
		14175	intel_hdmi_init(dev, CHV_HDMID, PORT_D);
		14176	if (I915_READ(CHV_DP_D) & DP_DETECTED)
		14177	intel_dp_init(dev, CHV_DP_D, PORT_D);
		14178	}
5060	serge	14179
4560	Serge	14180	intel_dsi_init(dev);
6084	serge	14181	} else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
2330	Serge	14182	bool found = false;
2327	Serge	14183
3746	Serge	14184	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	14185	DRM_DEBUG_KMS("probing SDVOB\n");
3746	Serge	14186	found = intel_sdvo_init(dev, GEN3_SDVOB, true);
6084	serge	14187	if (!found && IS_G4X(dev)) {
2330	Serge	14188	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3746	Serge	14189	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
2330	Serge	14190	}
2327	Serge	14191
6084	serge	14192	if (!found && IS_G4X(dev))
3031	serge	14193	intel_dp_init(dev, DP_B, PORT_B);
6084	serge	14194	}
2327	Serge	14195
2330	Serge	14196	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	14197
3746	Serge	14198	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	14199	DRM_DEBUG_KMS("probing SDVOC\n");
3746	Serge	14200	found = intel_sdvo_init(dev, GEN3_SDVOC, false);
2330	Serge	14201	}
2327	Serge	14202
3746	Serge	14203	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
2327	Serge	14204
6084	serge	14205	if (IS_G4X(dev)) {
2330	Serge	14206	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3746	Serge	14207	intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
2330	Serge	14208	}
6084	serge	14209	if (IS_G4X(dev))
3031	serge	14210	intel_dp_init(dev, DP_C, PORT_C);
6084	serge	14211	}
2327	Serge	14212
6084	serge	14213	if (IS_G4X(dev) &&
4104	Serge	14214	(I915_READ(DP_D) & DP_DETECTED))
3031	serge	14215	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	14216	} else if (IS_GEN2(dev))
		14217	intel_dvo_init(dev);
2327	Serge	14218
5354	serge	14219	intel_psr_init(dev);
5060	serge	14220
5354	serge	14221	for_each_intel_encoder(dev, encoder) {
2330	Serge	14222	encoder->base.possible_crtcs = encoder->crtc_mask;
		14223	encoder->base.possible_clones =
3031	serge	14224	intel_encoder_clones(encoder);
2330	Serge	14225	}
2327	Serge	14226
3243	Serge	14227	intel_init_pch_refclk(dev);
		14228
		14229	drm_helper_move_panel_connectors_to_head(dev);
2330	Serge	14230	}
		14231
6084	serge	14232	static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
		14233	{
		14234	struct drm_device *dev = fb->dev;
		14235	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2330	Serge	14236
6084	serge	14237	drm_framebuffer_cleanup(fb);
		14238	mutex_lock(&dev->struct_mutex);
		14239	WARN_ON(!intel_fb->obj->framebuffer_references--);
		14240	drm_gem_object_unreference(&intel_fb->obj->base);
		14241	mutex_unlock(&dev->struct_mutex);
		14242	kfree(intel_fb);
		14243	}
2330	Serge	14244
6084	serge	14245	static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
		14246	struct drm_file *file,
		14247	unsigned int *handle)
		14248	{
		14249	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		14250	struct drm_i915_gem_object *obj = intel_fb->obj;
		14251
		14252	if (obj->userptr.mm) {
		14253	DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
		14254	return -EINVAL;
		14255	}
		14256
		14257	return drm_gem_handle_create(file, &obj->base, handle);
		14258	}
		14259
		14260	static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
		14261	struct drm_file *file,
		14262	unsigned flags, unsigned color,
		14263	struct drm_clip_rect *clips,
		14264	unsigned num_clips)
		14265	{
		14266	struct drm_device *dev = fb->dev;
		14267	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		14268	struct drm_i915_gem_object *obj = intel_fb->obj;
		14269
		14270	mutex_lock(&dev->struct_mutex);
		14271	intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
		14272	mutex_unlock(&dev->struct_mutex);
		14273
		14274	return 0;
		14275	}
		14276
2335	Serge	14277	static const struct drm_framebuffer_funcs intel_fb_funcs = {
6084	serge	14278	.destroy = intel_user_framebuffer_destroy,
		14279	.create_handle = intel_user_framebuffer_create_handle,
		14280	.dirty = intel_user_framebuffer_dirty,
2335	Serge	14281	};
2327	Serge	14282
6084	serge	14283	static
		14284	u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
		14285	uint32_t pixel_format)
		14286	{
		14287	u32 gen = INTEL_INFO(dev)->gen;
		14288
		14289	if (gen >= 9) {
		14290	/* "The stride in bytes must not exceed the of the size of 8K
		14291	* pixels and 32K bytes."
		14292	*/
		14293	return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
		14294	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
		14295	return 32*1024;
		14296	} else if (gen >= 4) {
		14297	if (fb_modifier == I915_FORMAT_MOD_X_TILED)
		14298	return 16*1024;
		14299	else
		14300	return 32*1024;
		14301	} else if (gen >= 3) {
		14302	if (fb_modifier == I915_FORMAT_MOD_X_TILED)
		14303	return 8*1024;
		14304	else
		14305	return 16*1024;
		14306	} else {
		14307	/* XXX DSPC is limited to 4k tiled */
		14308	return 8*1024;
		14309	}
		14310	}
		14311
5060	serge	14312	static int intel_framebuffer_init(struct drm_device *dev,
6084	serge	14313	struct intel_framebuffer *intel_fb,
		14314	struct drm_mode_fb_cmd2 *mode_cmd,
		14315	struct drm_i915_gem_object *obj)
2335	Serge	14316	{
6084	serge	14317	unsigned int aligned_height;
2335	Serge	14318	int ret;
6084	serge	14319	u32 pitch_limit, stride_alignment;
2327	Serge	14320
4560	Serge	14321	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
		14322
6084	serge	14323	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
		14324	/* Enforce that fb modifier and tiling mode match, but only for
		14325	* X-tiled. This is needed for FBC. */
		14326	if (!!(obj->tiling_mode == I915_TILING_X) !=
		14327	!!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
		14328	DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
		14329	return -EINVAL;
		14330	}
		14331	} else {
		14332	if (obj->tiling_mode == I915_TILING_X)
		14333	mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
		14334	else if (obj->tiling_mode == I915_TILING_Y) {
		14335	DRM_DEBUG("No Y tiling for legacy addfb\n");
		14336	return -EINVAL;
		14337	}
		14338	}
		14339
		14340	/* Passed in modifier sanity checking. */
		14341	switch (mode_cmd->modifier[0]) {
		14342	case I915_FORMAT_MOD_Y_TILED:
		14343	case I915_FORMAT_MOD_Yf_TILED:
		14344	if (INTEL_INFO(dev)->gen < 9) {
		14345	DRM_DEBUG("Unsupported tiling 0x%llx!\n",
		14346	mode_cmd->modifier[0]);
		14347	return -EINVAL;
		14348	}
		14349	case DRM_FORMAT_MOD_NONE:
		14350	case I915_FORMAT_MOD_X_TILED:
		14351	break;
		14352	default:
		14353	DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
		14354	mode_cmd->modifier[0]);
2335	Serge	14355	return -EINVAL;
3243	Serge	14356	}
2327	Serge	14357
6084	serge	14358	stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
		14359	mode_cmd->pixel_format);
		14360	if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
		14361	DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
		14362	mode_cmd->pitches[0], stride_alignment);
3243	Serge	14363	return -EINVAL;
		14364	}
		14365
6084	serge	14366	pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
		14367	mode_cmd->pixel_format);
4104	Serge	14368	if (mode_cmd->pitches[0] > pitch_limit) {
6084	serge	14369	DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
		14370	mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
		14371	"tiled" : "linear",
4104	Serge	14372	mode_cmd->pitches[0], pitch_limit);
3243	Serge	14373	return -EINVAL;
		14374	}
		14375
6084	serge	14376	if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
3243	Serge	14377	mode_cmd->pitches[0] != obj->stride) {
		14378	DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
		14379	mode_cmd->pitches[0], obj->stride);
6084	serge	14380	return -EINVAL;
3243	Serge	14381	}
2327	Serge	14382
3243	Serge	14383	/* Reject formats not supported by any plane early. */
2342	Serge	14384	switch (mode_cmd->pixel_format) {
3243	Serge	14385	case DRM_FORMAT_C8:
2342	Serge	14386	case DRM_FORMAT_RGB565:
		14387	case DRM_FORMAT_XRGB8888:
3243	Serge	14388	case DRM_FORMAT_ARGB8888:
		14389	break;
		14390	case DRM_FORMAT_XRGB1555:
		14391	if (INTEL_INFO(dev)->gen > 3) {
4104	Serge	14392	DRM_DEBUG("unsupported pixel format: %s\n",
		14393	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	14394	return -EINVAL;
		14395	}
		14396	break;
6084	serge	14397	case DRM_FORMAT_ABGR8888:
		14398	if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
		14399	DRM_DEBUG("unsupported pixel format: %s\n",
		14400	drm_get_format_name(mode_cmd->pixel_format));
		14401	return -EINVAL;
		14402	}
		14403	break;
3031	serge	14404	case DRM_FORMAT_XBGR8888:
2342	Serge	14405	case DRM_FORMAT_XRGB2101010:
3243	Serge	14406	case DRM_FORMAT_XBGR2101010:
		14407	if (INTEL_INFO(dev)->gen < 4) {
4104	Serge	14408	DRM_DEBUG("unsupported pixel format: %s\n",
		14409	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	14410	return -EINVAL;
		14411	}
2335	Serge	14412	break;
6084	serge	14413	case DRM_FORMAT_ABGR2101010:
		14414	if (!IS_VALLEYVIEW(dev)) {
		14415	DRM_DEBUG("unsupported pixel format: %s\n",
		14416	drm_get_format_name(mode_cmd->pixel_format));
		14417	return -EINVAL;
		14418	}
		14419	break;
2342	Serge	14420	case DRM_FORMAT_YUYV:
		14421	case DRM_FORMAT_UYVY:
		14422	case DRM_FORMAT_YVYU:
		14423	case DRM_FORMAT_VYUY:
3243	Serge	14424	if (INTEL_INFO(dev)->gen < 5) {
4104	Serge	14425	DRM_DEBUG("unsupported pixel format: %s\n",
		14426	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	14427	return -EINVAL;
		14428	}
2342	Serge	14429	break;
2335	Serge	14430	default:
4104	Serge	14431	DRM_DEBUG("unsupported pixel format: %s\n",
		14432	drm_get_format_name(mode_cmd->pixel_format));
2335	Serge	14433	return -EINVAL;
		14434	}
2327	Serge	14435
3243	Serge	14436	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
		14437	if (mode_cmd->offsets[0] != 0)
		14438	return -EINVAL;
		14439
6084	serge	14440	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
		14441	mode_cmd->pixel_format,
		14442	mode_cmd->modifier[0]);
4560	Serge	14443	/* FIXME drm helper for size checks (especially planar formats)? */
		14444	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
		14445	return -EINVAL;
		14446
3480	Serge	14447	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		14448	intel_fb->obj = obj;
4560	Serge	14449	intel_fb->obj->framebuffer_references++;
3480	Serge	14450
2335	Serge	14451	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		14452	if (ret) {
		14453	DRM_ERROR("framebuffer init failed %d\n", ret);
		14454	return ret;
		14455	}
6283	serge	14456	kolibri_framebuffer_init(intel_fb);
2335	Serge	14457	return 0;
		14458	}
2327	Serge	14459
6084	serge	14460	static struct drm_framebuffer *
		14461	intel_user_framebuffer_create(struct drm_device *dev,
		14462	struct drm_file *filp,
		14463	struct drm_mode_fb_cmd2 *user_mode_cmd)
		14464	{
		14465	struct drm_i915_gem_object *obj;
		14466	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
		14467
		14468	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
		14469	mode_cmd.handles[0]));
		14470	if (&obj->base == NULL)
		14471	return ERR_PTR(-ENOENT);
		14472
		14473	return intel_framebuffer_create(dev, &mode_cmd, obj);
		14474	}
		14475
		14476	#ifndef CONFIG_DRM_FBDEV_EMULATION
4560	Serge	14477	static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
		14478	{
		14479	}
		14480	#endif
2327	Serge	14481
2360	Serge	14482	static const struct drm_mode_config_funcs intel_mode_funcs = {
6084	serge	14483	.fb_create = intel_user_framebuffer_create,
4560	Serge	14484	.output_poll_changed = intel_fbdev_output_poll_changed,
6084	serge	14485	.atomic_check = intel_atomic_check,
		14486	.atomic_commit = intel_atomic_commit,
		14487	.atomic_state_alloc = intel_atomic_state_alloc,
		14488	.atomic_state_clear = intel_atomic_state_clear,
2360	Serge	14489	};
2327	Serge	14490
3031	serge	14491	/* Set up chip specific display functions */
		14492	static void intel_init_display(struct drm_device *dev)
		14493	{
		14494	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	14495
4104	Serge	14496	if (HAS_PCH_SPLIT(dev) \|\| IS_G4X(dev))
		14497	dev_priv->display.find_dpll = g4x_find_best_dpll;
5060	serge	14498	else if (IS_CHERRYVIEW(dev))
		14499	dev_priv->display.find_dpll = chv_find_best_dpll;
4104	Serge	14500	else if (IS_VALLEYVIEW(dev))
		14501	dev_priv->display.find_dpll = vlv_find_best_dpll;
		14502	else if (IS_PINEVIEW(dev))
		14503	dev_priv->display.find_dpll = pnv_find_best_dpll;
		14504	else
		14505	dev_priv->display.find_dpll = i9xx_find_best_dpll;
		14506
6084	serge	14507	if (INTEL_INFO(dev)->gen >= 9) {
3746	Serge	14508	dev_priv->display.get_pipe_config = haswell_get_pipe_config;
6084	serge	14509	dev_priv->display.get_initial_plane_config =
		14510	skylake_get_initial_plane_config;
5354	serge	14511	dev_priv->display.crtc_compute_clock =
		14512	haswell_crtc_compute_clock;
3243	Serge	14513	dev_priv->display.crtc_enable = haswell_crtc_enable;
		14514	dev_priv->display.crtc_disable = haswell_crtc_disable;
5060	serge	14515	dev_priv->display.update_primary_plane =
6084	serge	14516	skylake_update_primary_plane;
		14517	} else if (HAS_DDI(dev)) {
		14518	dev_priv->display.get_pipe_config = haswell_get_pipe_config;
		14519	dev_priv->display.get_initial_plane_config =
		14520	ironlake_get_initial_plane_config;
		14521	dev_priv->display.crtc_compute_clock =
		14522	haswell_crtc_compute_clock;
		14523	dev_priv->display.crtc_enable = haswell_crtc_enable;
		14524	dev_priv->display.crtc_disable = haswell_crtc_disable;
		14525	dev_priv->display.update_primary_plane =
5060	serge	14526	ironlake_update_primary_plane;
3243	Serge	14527	} else if (HAS_PCH_SPLIT(dev)) {
3746	Serge	14528	dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
6084	serge	14529	dev_priv->display.get_initial_plane_config =
		14530	ironlake_get_initial_plane_config;
5354	serge	14531	dev_priv->display.crtc_compute_clock =
		14532	ironlake_crtc_compute_clock;
3031	serge	14533	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		14534	dev_priv->display.crtc_disable = ironlake_crtc_disable;
5060	serge	14535	dev_priv->display.update_primary_plane =
		14536	ironlake_update_primary_plane;
4104	Serge	14537	} else if (IS_VALLEYVIEW(dev)) {
		14538	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
6084	serge	14539	dev_priv->display.get_initial_plane_config =
		14540	i9xx_get_initial_plane_config;
5354	serge	14541	dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
4104	Serge	14542	dev_priv->display.crtc_enable = valleyview_crtc_enable;
		14543	dev_priv->display.crtc_disable = i9xx_crtc_disable;
5060	serge	14544	dev_priv->display.update_primary_plane =
		14545	i9xx_update_primary_plane;
3031	serge	14546	} else {
3746	Serge	14547	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
6084	serge	14548	dev_priv->display.get_initial_plane_config =
		14549	i9xx_get_initial_plane_config;
5354	serge	14550	dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
3031	serge	14551	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		14552	dev_priv->display.crtc_disable = i9xx_crtc_disable;
5060	serge	14553	dev_priv->display.update_primary_plane =
		14554	i9xx_update_primary_plane;
3031	serge	14555	}
2327	Serge	14556
3031	serge	14557	/* Returns the core display clock speed */
6084	serge	14558	if (IS_SKYLAKE(dev))
3031	serge	14559	dev_priv->display.get_display_clock_speed =
6084	serge	14560	skylake_get_display_clock_speed;
		14561	else if (IS_BROXTON(dev))
		14562	dev_priv->display.get_display_clock_speed =
		14563	broxton_get_display_clock_speed;
		14564	else if (IS_BROADWELL(dev))
		14565	dev_priv->display.get_display_clock_speed =
		14566	broadwell_get_display_clock_speed;
		14567	else if (IS_HASWELL(dev))
		14568	dev_priv->display.get_display_clock_speed =
		14569	haswell_get_display_clock_speed;
		14570	else if (IS_VALLEYVIEW(dev))
		14571	dev_priv->display.get_display_clock_speed =
3031	serge	14572	valleyview_get_display_clock_speed;
6084	serge	14573	else if (IS_GEN5(dev))
3031	serge	14574	dev_priv->display.get_display_clock_speed =
6084	serge	14575	ilk_get_display_clock_speed;
		14576	else if (IS_I945G(dev) \|\| IS_BROADWATER(dev) \|\|
		14577	IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev))
		14578	dev_priv->display.get_display_clock_speed =
3031	serge	14579	i945_get_display_clock_speed;
6084	serge	14580	else if (IS_GM45(dev))
		14581	dev_priv->display.get_display_clock_speed =
		14582	gm45_get_display_clock_speed;
		14583	else if (IS_CRESTLINE(dev))
		14584	dev_priv->display.get_display_clock_speed =
		14585	i965gm_get_display_clock_speed;
		14586	else if (IS_PINEVIEW(dev))
		14587	dev_priv->display.get_display_clock_speed =
		14588	pnv_get_display_clock_speed;
		14589	else if (IS_G33(dev) \|\| IS_G4X(dev))
		14590	dev_priv->display.get_display_clock_speed =
		14591	g33_get_display_clock_speed;
3031	serge	14592	else if (IS_I915G(dev))
		14593	dev_priv->display.get_display_clock_speed =
		14594	i915_get_display_clock_speed;
4104	Serge	14595	else if (IS_I945GM(dev) \|\| IS_845G(dev))
3031	serge	14596	dev_priv->display.get_display_clock_speed =
		14597	i9xx_misc_get_display_clock_speed;
4104	Serge	14598	else if (IS_PINEVIEW(dev))
		14599	dev_priv->display.get_display_clock_speed =
		14600	pnv_get_display_clock_speed;
3031	serge	14601	else if (IS_I915GM(dev))
		14602	dev_priv->display.get_display_clock_speed =
		14603	i915gm_get_display_clock_speed;
		14604	else if (IS_I865G(dev))
		14605	dev_priv->display.get_display_clock_speed =
		14606	i865_get_display_clock_speed;
		14607	else if (IS_I85X(dev))
		14608	dev_priv->display.get_display_clock_speed =
6084	serge	14609	i85x_get_display_clock_speed;
		14610	else { /* 830 */
		14611	WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
3031	serge	14612	dev_priv->display.get_display_clock_speed =
		14613	i830_get_display_clock_speed;
6084	serge	14614	}
2327	Serge	14615
6084	serge	14616	if (IS_GEN5(dev)) {
		14617	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		14618	} else if (IS_GEN6(dev)) {
		14619	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		14620	} else if (IS_IVYBRIDGE(dev)) {
		14621	/* FIXME: detect B0+ stepping and use auto training */
		14622	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
5354	serge	14623	} else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
6084	serge	14624	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		14625	if (IS_BROADWELL(dev)) {
		14626	dev_priv->display.modeset_commit_cdclk =
		14627	broadwell_modeset_commit_cdclk;
		14628	dev_priv->display.modeset_calc_cdclk =
		14629	broadwell_modeset_calc_cdclk;
		14630	}
4560	Serge	14631	} else if (IS_VALLEYVIEW(dev)) {
6084	serge	14632	dev_priv->display.modeset_commit_cdclk =
		14633	valleyview_modeset_commit_cdclk;
		14634	dev_priv->display.modeset_calc_cdclk =
		14635	valleyview_modeset_calc_cdclk;
		14636	} else if (IS_BROXTON(dev)) {
		14637	dev_priv->display.modeset_commit_cdclk =
		14638	broxton_modeset_commit_cdclk;
		14639	dev_priv->display.modeset_calc_cdclk =
		14640	broxton_modeset_calc_cdclk;
3031	serge	14641	}
2327	Serge	14642
6320	serge	14643	switch (INTEL_INFO(dev)->gen) {
		14644	case 2:
		14645	dev_priv->display.queue_flip = intel_gen2_queue_flip;
		14646	break;
2327	Serge	14647
6320	serge	14648	case 3:
		14649	dev_priv->display.queue_flip = intel_gen3_queue_flip;
		14650	break;
2327	Serge	14651
6320	serge	14652	case 4:
		14653	case 5:
		14654	dev_priv->display.queue_flip = intel_gen4_queue_flip;
		14655	break;
2327	Serge	14656
6320	serge	14657	case 6:
		14658	dev_priv->display.queue_flip = intel_gen6_queue_flip;
		14659	break;
		14660	case 7:
		14661	case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
		14662	dev_priv->display.queue_flip = intel_gen7_queue_flip;
		14663	break;
		14664	case 9:
		14665	/* Drop through - unsupported since execlist only. */
		14666	default:
		14667	/* Default just returns -ENODEV to indicate unsupported */
		14668	dev_priv->display.queue_flip = intel_default_queue_flip;
		14669	}
2327	Serge	14670
5354	serge	14671	mutex_init(&dev_priv->pps_mutex);
3031	serge	14672	}
		14673
		14674	/*
		14675	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		14676	* resume, or other times. This quirk makes sure that's the case for
		14677	* affected systems.
		14678	*/
		14679	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	14680	{
		14681	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	14682
3031	serge	14683	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		14684	DRM_INFO("applying pipe a force quirk\n");
		14685	}
2327	Serge	14686
5354	serge	14687	static void quirk_pipeb_force(struct drm_device *dev)
		14688	{
		14689	struct drm_i915_private *dev_priv = dev->dev_private;
		14690
		14691	dev_priv->quirks \|= QUIRK_PIPEB_FORCE;
		14692	DRM_INFO("applying pipe b force quirk\n");
		14693	}
		14694
3031	serge	14695	/*
		14696	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		14697	*/
		14698	static void quirk_ssc_force_disable(struct drm_device *dev)
		14699	{
		14700	struct drm_i915_private *dev_priv = dev->dev_private;
		14701	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		14702	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	14703	}
2327	Serge	14704
3031	serge	14705	/*
		14706	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		14707	* brightness value
		14708	*/
		14709	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	14710	{
		14711	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	14712	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		14713	DRM_INFO("applying inverted panel brightness quirk\n");
		14714	}
2327	Serge	14715
5060	serge	14716	/* Some VBT's incorrectly indicate no backlight is present */
		14717	static void quirk_backlight_present(struct drm_device *dev)
		14718	{
		14719	struct drm_i915_private *dev_priv = dev->dev_private;
		14720	dev_priv->quirks \|= QUIRK_BACKLIGHT_PRESENT;
		14721	DRM_INFO("applying backlight present quirk\n");
		14722	}
		14723
3031	serge	14724	struct intel_quirk {
		14725	int device;
		14726	int subsystem_vendor;
		14727	int subsystem_device;
		14728	void (hook)(struct drm_device dev);
		14729	};
2327	Serge	14730
3031	serge	14731	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		14732	struct intel_dmi_quirk {
		14733	void (hook)(struct drm_device dev);
		14734	const struct dmi_system_id (*dmi_id_list)[];
		14735	};
2327	Serge	14736
3031	serge	14737	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		14738	{
		14739	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		14740	return 1;
2330	Serge	14741	}
2327	Serge	14742
3031	serge	14743	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		14744	{
		14745	.dmi_id_list = &(const struct dmi_system_id[]) {
		14746	{
		14747	.callback = intel_dmi_reverse_brightness,
		14748	.ident = "NCR Corporation",
		14749	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		14750	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		14751	},
		14752	},
		14753	{ } /* terminating entry */
		14754	},
		14755	.hook = quirk_invert_brightness,
		14756	},
		14757	};
2327	Serge	14758
3031	serge	14759	static struct intel_quirk intel_quirks[] = {
		14760	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		14761	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	14762
3031	serge	14763	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		14764	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	14765
5367	serge	14766	/* 830 needs to leave pipe A & dpll A up */
		14767	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		14768
		14769	/* 830 needs to leave pipe B & dpll B up */
		14770	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
		14771
3031	serge	14772	/* Lenovo U160 cannot use SSC on LVDS */
		14773	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	14774
3031	serge	14775	/* Sony Vaio Y cannot use SSC on LVDS */
		14776	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	14777
3031	serge	14778	/* Acer Aspire 5734Z must invert backlight brightness */
		14779	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
3480	Serge	14780
		14781	/* Acer/eMachines G725 */
		14782	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
		14783
		14784	/* Acer/eMachines e725 */
		14785	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
		14786
		14787	/* Acer/Packard Bell NCL20 */
		14788	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
		14789
		14790	/* Acer Aspire 4736Z */
		14791	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
5060	serge	14792
		14793	/* Acer Aspire 5336 */
		14794	{ 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
		14795
		14796	/* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
		14797	{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
		14798
5097	serge	14799	/* Acer C720 Chromebook (Core i3 4005U) */
		14800	{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
		14801
5354	serge	14802	/* Apple Macbook 2,1 (Core 2 T7400) */
		14803	{ 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
		14804
6084	serge	14805	/* Apple Macbook 4,1 */
		14806	{ 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
		14807
5060	serge	14808	/* Toshiba CB35 Chromebook (Celeron 2955U) */
		14809	{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
		14810
		14811	/* HP Chromebook 14 (Celeron 2955U) */
		14812	{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
6084	serge	14813
		14814	/* Dell Chromebook 11 */
		14815	{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
		14816
		14817	/* Dell Chromebook 11 (2015 version) */
		14818	{ 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
3031	serge	14819	};
2327	Serge	14820
3031	serge	14821	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	14822	{
3031	serge	14823	struct pci_dev *d = dev->pdev;
		14824	int i;
2327	Serge	14825
3031	serge	14826	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		14827	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	14828
3031	serge	14829	if (d->device == q->device &&
		14830	(d->subsystem_vendor == q->subsystem_vendor \|\|
		14831	q->subsystem_vendor == PCI_ANY_ID) &&
		14832	(d->subsystem_device == q->subsystem_device \|\|
		14833	q->subsystem_device == PCI_ANY_ID))
		14834	q->hook(dev);
		14835	}
5097	serge	14836	for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
		14837	if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
		14838	intel_dmi_quirks[i].hook(dev);
		14839	}
2330	Serge	14840	}
2327	Serge	14841
3031	serge	14842	/* Disable the VGA plane that we never use */
		14843	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	14844	{
		14845	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	14846	u8 sr1;
3480	Serge	14847	u32 vga_reg = i915_vgacntrl_reg(dev);
2327	Serge	14848
6084	serge	14849	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
4560	Serge	14850	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		14851	outb(SR01, VGA_SR_INDEX);
		14852	sr1 = inb(VGA_SR_DATA);
		14853	outb(sr1 \| 1<<5, VGA_SR_DATA);
		14854	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
3031	serge	14855	udelay(300);
2327	Serge	14856
6084	serge	14857	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
3031	serge	14858	POSTING_READ(vga_reg);
2330	Serge	14859	}
		14860
3031	serge	14861	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	14862	{
6084	serge	14863	intel_update_cdclk(dev);
3031	serge	14864	intel_prepare_ddi(dev);
		14865	intel_init_clock_gating(dev);
6084	serge	14866	intel_enable_gt_powersave(dev);
2342	Serge	14867	}
		14868
3031	serge	14869	void intel_modeset_init(struct drm_device *dev)
2330	Serge	14870	{
3031	serge	14871	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	14872	int sprite, ret;
		14873	enum pipe pipe;
		14874	struct intel_crtc *crtc;
6088	serge	14875
3031	serge	14876	drm_mode_config_init(dev);
2330	Serge	14877
3031	serge	14878	dev->mode_config.min_width = 0;
		14879	dev->mode_config.min_height = 0;
2330	Serge	14880
3031	serge	14881	dev->mode_config.preferred_depth = 24;
		14882	dev->mode_config.prefer_shadow = 1;
2330	Serge	14883
6084	serge	14884	dev->mode_config.allow_fb_modifiers = true;
		14885
3031	serge	14886	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	14887
3031	serge	14888	intel_init_quirks(dev);
2330	Serge	14889
3031	serge	14890	intel_init_pm(dev);
2330	Serge	14891
3746	Serge	14892	if (INTEL_INFO(dev)->num_pipes == 0)
		14893	return;
		14894
6084	serge	14895	/*
		14896	* There may be no VBT; and if the BIOS enabled SSC we can
		14897	* just keep using it to avoid unnecessary flicker. Whereas if the
		14898	* BIOS isn't using it, don't assume it will work even if the VBT
		14899	* indicates as much.
		14900	*/
		14901	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)) {
		14902	bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
		14903	DREF_SSC1_ENABLE);
		14904
		14905	if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
		14906	DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
		14907	bios_lvds_use_ssc ? "en" : "dis",
		14908	dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
		14909	dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
		14910	}
		14911	}
		14912
3031	serge	14913	intel_init_display(dev);
2330	Serge	14914
3031	serge	14915	if (IS_GEN2(dev)) {
		14916	dev->mode_config.max_width = 2048;
		14917	dev->mode_config.max_height = 2048;
		14918	} else if (IS_GEN3(dev)) {
		14919	dev->mode_config.max_width = 4096;
		14920	dev->mode_config.max_height = 4096;
		14921	} else {
		14922	dev->mode_config.max_width = 8192;
		14923	dev->mode_config.max_height = 8192;
		14924	}
5060	serge	14925
		14926	if (IS_GEN2(dev)) {
		14927	dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
		14928	dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
		14929	} else {
		14930	dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
		14931	dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
		14932	}
		14933
3480	Serge	14934	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
2330	Serge	14935
3031	serge	14936	DRM_DEBUG_KMS("%d display pipe%s available.\n",
3746	Serge	14937	INTEL_INFO(dev)->num_pipes,
		14938	INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
2330	Serge	14939
5354	serge	14940	for_each_pipe(dev_priv, pipe) {
5060	serge	14941	intel_crtc_init(dev, pipe);
6084	serge	14942	for_each_sprite(dev_priv, pipe, sprite) {
5060	serge	14943	ret = intel_plane_init(dev, pipe, sprite);
6084	serge	14944	if (ret)
4104	Serge	14945	DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
5060	serge	14946	pipe_name(pipe), sprite_name(pipe, sprite), ret);
3746	Serge	14947	}
2330	Serge	14948	}
		14949
6084	serge	14950	intel_update_czclk(dev_priv);
		14951	intel_update_cdclk(dev);
4560	Serge	14952
4104	Serge	14953	intel_shared_dpll_init(dev);
2330	Serge	14954
3031	serge	14955	/* Just disable it once at startup */
		14956	i915_disable_vga(dev);
		14957	intel_setup_outputs(dev);
3480	Serge	14958
		14959	/* Just in case the BIOS is doing something questionable. */
6084	serge	14960	intel_fbc_disable(dev_priv);
2330	Serge	14961
5060	serge	14962	drm_modeset_lock_all(dev);
6084	serge	14963	intel_modeset_setup_hw_state(dev);
5060	serge	14964	drm_modeset_unlock_all(dev);
		14965
		14966	for_each_intel_crtc(dev, crtc) {
6084	serge	14967	struct intel_initial_plane_config plane_config = {};
		14968
5060	serge	14969	if (!crtc->active)
		14970	continue;
		14971
		14972	/*
		14973	* Note that reserving the BIOS fb up front prevents us
		14974	* from stuffing other stolen allocations like the ring
		14975	* on top. This prevents some ugliness at boot time, and
		14976	* can even allow for smooth boot transitions if the BIOS
		14977	* fb is large enough for the active pipe configuration.
		14978	*/
6084	serge	14979	dev_priv->display.get_initial_plane_config(crtc,
		14980	&plane_config);
		14981
		14982	/*
		14983	* If the fb is shared between multiple heads, we'll
		14984	* just get the first one.
		14985	*/
		14986	intel_find_initial_plane_obj(crtc, &plane_config);
5060	serge	14987	}
2330	Serge	14988	}
		14989
3031	serge	14990	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	14991	{
3031	serge	14992	struct intel_connector *connector;
		14993	struct drm_connector *crt = NULL;
		14994	struct intel_load_detect_pipe load_detect_temp;
5060	serge	14995	struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
2330	Serge	14996
3031	serge	14997	/* We can't just switch on the pipe A, we need to set things up with a
		14998	* proper mode and output configuration. As a gross hack, enable pipe A
		14999	* by enabling the load detect pipe once. */
6084	serge	15000	for_each_intel_connector(dev, connector) {
3031	serge	15001	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		15002	crt = &connector->base;
		15003	break;
2330	Serge	15004	}
		15005	}
		15006
3031	serge	15007	if (!crt)
		15008	return;
2330	Serge	15009
5060	serge	15010	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
6084	serge	15011	intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
2327	Serge	15012	}
		15013
3031	serge	15014	static bool
		15015	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	15016	{
3746	Serge	15017	struct drm_device *dev = crtc->base.dev;
		15018	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	15019	u32 val;
2327	Serge	15020
3746	Serge	15021	if (INTEL_INFO(dev)->num_pipes == 1)
3031	serge	15022	return true;
2327	Serge	15023
6084	serge	15024	val = I915_READ(DSPCNTR(!crtc->plane));
2327	Serge	15025
3031	serge	15026	if ((val & DISPLAY_PLANE_ENABLE) &&
		15027	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		15028	return false;
2327	Serge	15029
3031	serge	15030	return true;
2327	Serge	15031	}
		15032
6084	serge	15033	static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
		15034	{
		15035	struct drm_device *dev = crtc->base.dev;
		15036	struct intel_encoder *encoder;
		15037
		15038	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
		15039	return true;
		15040
		15041	return false;
		15042	}
		15043
3031	serge	15044	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	15045	{
3031	serge	15046	struct drm_device *dev = crtc->base.dev;
2327	Serge	15047	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	15048	u32 reg;
2327	Serge	15049
3031	serge	15050	/* Clear any frame start delays used for debugging left by the BIOS */
6084	serge	15051	reg = PIPECONF(crtc->config->cpu_transcoder);
3031	serge	15052	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	15053
5060	serge	15054	/* restore vblank interrupts to correct state */
6084	serge	15055	drm_crtc_vblank_reset(&crtc->base);
5354	serge	15056	if (crtc->active) {
6084	serge	15057	struct intel_plane *plane;
5060	serge	15058
6084	serge	15059	drm_crtc_vblank_on(&crtc->base);
		15060
		15061	/* Disable everything but the primary plane */
		15062	for_each_intel_plane_on_crtc(dev, crtc, plane) {
		15063	if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
		15064	continue;
		15065
		15066	plane->disable_plane(&plane->base, &crtc->base);
		15067	}
		15068	}
		15069
3031	serge	15070	/* We need to sanitize the plane -> pipe mapping first because this will
		15071	* disable the crtc (and hence change the state) if it is wrong. Note
		15072	* that gen4+ has a fixed plane -> pipe mapping. */
		15073	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		15074	bool plane;
2327	Serge	15075
3031	serge	15076	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		15077	crtc->base.base.id);
2327	Serge	15078
3031	serge	15079	/* Pipe has the wrong plane attached and the plane is active.
		15080	* Temporarily change the plane mapping and disable everything
		15081	* ... */
		15082	plane = crtc->plane;
6084	serge	15083	to_intel_plane_state(crtc->base.primary->state)->visible = true;
3031	serge	15084	crtc->plane = !plane;
6084	serge	15085	intel_crtc_disable_noatomic(&crtc->base);
3031	serge	15086	crtc->plane = plane;
		15087	}
2327	Serge	15088
3031	serge	15089	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		15090	crtc->pipe == PIPE_A && !crtc->active) {
		15091	/* BIOS forgot to enable pipe A, this mostly happens after
		15092	* resume. Force-enable the pipe to fix this, the update_dpms
		15093	* call below we restore the pipe to the right state, but leave
		15094	* the required bits on. */
		15095	intel_enable_pipe_a(dev);
		15096	}
2327	Serge	15097
3031	serge	15098	/* Adjust the state of the output pipe according to whether we
		15099	* have active connectors/encoders. */
6084	serge	15100	if (!intel_crtc_has_encoders(crtc))
		15101	intel_crtc_disable_noatomic(&crtc->base);
2327	Serge	15102
6084	serge	15103	if (crtc->active != crtc->base.state->active) {
3031	serge	15104	struct intel_encoder *encoder;
2327	Serge	15105
3031	serge	15106	/* This can happen either due to bugs in the get_hw_state
6084	serge	15107	* functions or because of calls to intel_crtc_disable_noatomic,
		15108	* or because the pipe is force-enabled due to the
3031	serge	15109	* pipe A quirk. */
		15110	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		15111	crtc->base.base.id,
6084	serge	15112	crtc->base.state->enable ? "enabled" : "disabled",
3031	serge	15113	crtc->active ? "enabled" : "disabled");
2327	Serge	15114
6084	serge	15115	WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
		15116	crtc->base.state->active = crtc->active;
3031	serge	15117	crtc->base.enabled = crtc->active;
2327	Serge	15118
3031	serge	15119	/* Because we only establish the connector -> encoder ->
		15120	* crtc links if something is active, this means the
		15121	* crtc is now deactivated. Break the links. connector
		15122	* -> encoder links are only establish when things are
		15123	* actually up, hence no need to break them. */
		15124	WARN_ON(crtc->active);
2327	Serge	15125
6084	serge	15126	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
3031	serge	15127	encoder->base.crtc = NULL;
		15128	}
5060	serge	15129
5354	serge	15130	if (crtc->active \|\| HAS_GMCH_DISPLAY(dev)) {
5060	serge	15131	/*
		15132	* We start out with underrun reporting disabled to avoid races.
		15133	* For correct bookkeeping mark this on active crtcs.
		15134	*
		15135	* Also on gmch platforms we dont have any hardware bits to
		15136	* disable the underrun reporting. Which means we need to start
		15137	* out with underrun reporting disabled also on inactive pipes,
		15138	* since otherwise we'll complain about the garbage we read when
		15139	* e.g. coming up after runtime pm.
		15140	*
		15141	* No protection against concurrent access is required - at
		15142	* worst a fifo underrun happens which also sets this to false.
		15143	*/
		15144	crtc->cpu_fifo_underrun_disabled = true;
		15145	crtc->pch_fifo_underrun_disabled = true;
		15146	}
2327	Serge	15147	}
		15148
3031	serge	15149	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	15150	{
3031	serge	15151	struct intel_connector *connector;
		15152	struct drm_device *dev = encoder->base.dev;
6084	serge	15153	bool active = false;
2327	Serge	15154
3031	serge	15155	/* We need to check both for a crtc link (meaning that the
		15156	* encoder is active and trying to read from a pipe) and the
		15157	* pipe itself being active. */
		15158	bool has_active_crtc = encoder->base.crtc &&
		15159	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	15160
6084	serge	15161	for_each_intel_connector(dev, connector) {
		15162	if (connector->base.encoder != &encoder->base)
		15163	continue;
		15164
		15165	active = true;
		15166	break;
		15167	}
		15168
		15169	if (active && !has_active_crtc) {
3031	serge	15170	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		15171	encoder->base.base.id,
5060	serge	15172	encoder->base.name);
2327	Serge	15173
3031	serge	15174	/* Connector is active, but has no active pipe. This is
		15175	* fallout from our resume register restoring. Disable
		15176	* the encoder manually again. */
		15177	if (encoder->base.crtc) {
		15178	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		15179	encoder->base.base.id,
5060	serge	15180	encoder->base.name);
3031	serge	15181	encoder->disable(encoder);
5060	serge	15182	if (encoder->post_disable)
		15183	encoder->post_disable(encoder);
3031	serge	15184	}
5060	serge	15185	encoder->base.crtc = NULL;
2327	Serge	15186
3031	serge	15187	/* Inconsistent output/port/pipe state happens presumably due to
		15188	* a bug in one of the get_hw_state functions. Or someplace else
		15189	* in our code, like the register restore mess on resume. Clamp
		15190	* things to off as a safer default. */
6084	serge	15191	for_each_intel_connector(dev, connector) {
3031	serge	15192	if (connector->encoder != encoder)
		15193	continue;
5060	serge	15194	connector->base.dpms = DRM_MODE_DPMS_OFF;
		15195	connector->base.encoder = NULL;
3031	serge	15196	}
		15197	}
		15198	/* Enabled encoders without active connectors will be fixed in
		15199	* the crtc fixup. */
2327	Serge	15200	}
		15201
5060	serge	15202	void i915_redisable_vga_power_on(struct drm_device *dev)
3746	Serge	15203	{
		15204	struct drm_i915_private *dev_priv = dev->dev_private;
		15205	u32 vga_reg = i915_vgacntrl_reg(dev);
		15206
5060	serge	15207	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
		15208	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
		15209	i915_disable_vga(dev);
		15210	}
		15211	}
		15212
		15213	void i915_redisable_vga(struct drm_device *dev)
		15214	{
		15215	struct drm_i915_private *dev_priv = dev->dev_private;
		15216
4104	Serge	15217	/* This function can be called both from intel_modeset_setup_hw_state or
		15218	* at a very early point in our resume sequence, where the power well
		15219	* structures are not yet restored. Since this function is at a very
		15220	* paranoid "someone might have enabled VGA while we were not looking"
		15221	* level, just check if the power well is enabled instead of trying to
		15222	* follow the "don't touch the power well if we don't need it" policy
		15223	* the rest of the driver uses. */
5354	serge	15224	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
4104	Serge	15225	return;
		15226
5060	serge	15227	i915_redisable_vga_power_on(dev);
3746	Serge	15228	}
		15229
6084	serge	15230	static bool primary_get_hw_state(struct intel_plane *plane)
5060	serge	15231	{
6084	serge	15232	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5060	serge	15233
6084	serge	15234	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
		15235	}
5060	serge	15236
6084	serge	15237	/* FIXME read out full plane state for all planes */
		15238	static void readout_plane_state(struct intel_crtc *crtc)
		15239	{
		15240	struct drm_plane *primary = crtc->base.primary;
		15241	struct intel_plane_state *plane_state =
		15242	to_intel_plane_state(primary->state);
		15243
		15244	plane_state->visible =
		15245	primary_get_hw_state(to_intel_plane(primary));
		15246
		15247	if (plane_state->visible)
		15248	crtc->base.state->plane_mask \|= 1 << drm_plane_index(primary);
5060	serge	15249	}
		15250
4104	Serge	15251	static void intel_modeset_readout_hw_state(struct drm_device *dev)
2332	Serge	15252	{
		15253	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	15254	enum pipe pipe;
		15255	struct intel_crtc *crtc;
		15256	struct intel_encoder *encoder;
		15257	struct intel_connector *connector;
4104	Serge	15258	int i;
2327	Serge	15259
5060	serge	15260	for_each_intel_crtc(dev, crtc) {
6084	serge	15261	__drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
		15262	memset(crtc->config, 0, sizeof(*crtc->config));
		15263	crtc->config->base.crtc = &crtc->base;
2327	Serge	15264
3746	Serge	15265	crtc->active = dev_priv->display.get_pipe_config(crtc,
6084	serge	15266	crtc->config);
2327	Serge	15267
6084	serge	15268	crtc->base.state->active = crtc->active;
3031	serge	15269	crtc->base.enabled = crtc->active;
2330	Serge	15270
6084	serge	15271	readout_plane_state(crtc);
		15272
3031	serge	15273	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		15274	crtc->base.base.id,
		15275	crtc->active ? "enabled" : "disabled");
2339	Serge	15276	}
2332	Serge	15277
4104	Serge	15278	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		15279	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		15280
5354	serge	15281	pll->on = pll->get_hw_state(dev_priv, pll,
		15282	&pll->config.hw_state);
4104	Serge	15283	pll->active = 0;
5354	serge	15284	pll->config.crtc_mask = 0;
5060	serge	15285	for_each_intel_crtc(dev, crtc) {
5354	serge	15286	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
4104	Serge	15287	pll->active++;
5354	serge	15288	pll->config.crtc_mask \|= 1 << crtc->pipe;
		15289	}
4104	Serge	15290	}
		15291
5354	serge	15292	DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
		15293	pll->name, pll->config.crtc_mask, pll->on);
5060	serge	15294
5354	serge	15295	if (pll->config.crtc_mask)
5060	serge	15296	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
4104	Serge	15297	}
		15298
5354	serge	15299	for_each_intel_encoder(dev, encoder) {
3031	serge	15300	pipe = 0;
2332	Serge	15301
3031	serge	15302	if (encoder->get_hw_state(encoder, &pipe)) {
4104	Serge	15303	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		15304	encoder->base.crtc = &crtc->base;
6084	serge	15305	encoder->get_config(encoder, crtc->config);
3031	serge	15306	} else {
		15307	encoder->base.crtc = NULL;
		15308	}
2332	Serge	15309
4560	Serge	15310	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
3031	serge	15311	encoder->base.base.id,
5060	serge	15312	encoder->base.name,
3031	serge	15313	encoder->base.crtc ? "enabled" : "disabled",
4560	Serge	15314	pipe_name(pipe));
3031	serge	15315	}
2332	Serge	15316
6084	serge	15317	for_each_intel_connector(dev, connector) {
3031	serge	15318	if (connector->get_hw_state(connector)) {
		15319	connector->base.dpms = DRM_MODE_DPMS_ON;
		15320	connector->base.encoder = &connector->encoder->base;
		15321	} else {
		15322	connector->base.dpms = DRM_MODE_DPMS_OFF;
		15323	connector->base.encoder = NULL;
		15324	}
		15325	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		15326	connector->base.base.id,
5060	serge	15327	connector->base.name,
3031	serge	15328	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	15329	}
6084	serge	15330
		15331	for_each_intel_crtc(dev, crtc) {
		15332	crtc->base.hwmode = crtc->config->base.adjusted_mode;
		15333
		15334	memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
		15335	if (crtc->base.state->active) {
		15336	intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
		15337	intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
		15338	WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
		15339
		15340	/*
		15341	* The initial mode needs to be set in order to keep
		15342	* the atomic core happy. It wants a valid mode if the
		15343	* crtc's enabled, so we do the above call.
		15344	*
		15345	* At this point some state updated by the connectors
		15346	* in their ->detect() callback has not run yet, so
		15347	* no recalculation can be done yet.
		15348	*
		15349	* Even if we could do a recalculation and modeset
		15350	* right now it would cause a double modeset if
		15351	* fbdev or userspace chooses a different initial mode.
		15352	*
		15353	* If that happens, someone indicated they wanted a
		15354	* mode change, which means it's safe to do a full
		15355	* recalculation.
		15356	*/
		15357	crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
		15358
		15359	drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
		15360	update_scanline_offset(crtc);
		15361	}
		15362	}
4104	Serge	15363	}
2332	Serge	15364
6084	serge	15365	/* Scan out the current hw modeset state,
		15366	* and sanitizes it to the current state
		15367	*/
		15368	static void
		15369	intel_modeset_setup_hw_state(struct drm_device *dev)
4104	Serge	15370	{
		15371	struct drm_i915_private *dev_priv = dev->dev_private;
		15372	enum pipe pipe;
		15373	struct intel_crtc *crtc;
		15374	struct intel_encoder *encoder;
		15375	int i;
		15376
		15377	intel_modeset_readout_hw_state(dev);
		15378
3031	serge	15379	/* HW state is read out, now we need to sanitize this mess. */
5354	serge	15380	for_each_intel_encoder(dev, encoder) {
3031	serge	15381	intel_sanitize_encoder(encoder);
2332	Serge	15382	}
		15383
5354	serge	15384	for_each_pipe(dev_priv, pipe) {
3031	serge	15385	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		15386	intel_sanitize_crtc(crtc);
6084	serge	15387	intel_dump_pipe_config(crtc, crtc->config,
		15388	"[setup_hw_state]");
2332	Serge	15389	}
		15390
6084	serge	15391	intel_modeset_update_connector_atomic_state(dev);
		15392
4104	Serge	15393	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		15394	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		15395
		15396	if (!pll->on \|\| pll->active)
		15397	continue;
		15398
		15399	DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
		15400
		15401	pll->disable(dev_priv, pll);
		15402	pll->on = false;
		15403	}
		15404
6084	serge	15405	if (IS_VALLEYVIEW(dev))
		15406	vlv_wm_get_hw_state(dev);
		15407	else if (IS_GEN9(dev))
5354	serge	15408	skl_wm_get_hw_state(dev);
		15409	else if (HAS_PCH_SPLIT(dev))
4560	Serge	15410	ilk_wm_get_hw_state(dev);
		15411
6084	serge	15412	for_each_intel_crtc(dev, crtc) {
		15413	unsigned long put_domains;
4560	Serge	15414
6084	serge	15415	put_domains = modeset_get_crtc_power_domains(&crtc->base);
		15416	if (WARN_ON(put_domains))
		15417	modeset_put_power_domains(dev_priv, put_domains);
		15418	}
		15419	intel_display_set_init_power(dev_priv, false);
		15420	}
3746	Serge	15421
6084	serge	15422	void intel_display_resume(struct drm_device *dev)
		15423	{
		15424	struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
		15425	struct intel_connector *conn;
		15426	struct intel_plane *plane;
		15427	struct drm_crtc *crtc;
		15428	int ret;
		15429
		15430	if (!state)
		15431	return;
		15432
		15433	state->acquire_ctx = dev->mode_config.acquire_ctx;
		15434
		15435	/* preserve complete old state, including dpll */
		15436	intel_atomic_get_shared_dpll_state(state);
		15437
		15438	for_each_crtc(dev, crtc) {
		15439	struct drm_crtc_state *crtc_state =
		15440	drm_atomic_get_crtc_state(state, crtc);
		15441
		15442	ret = PTR_ERR_OR_ZERO(crtc_state);
		15443	if (ret)
		15444	goto err;
		15445
		15446	/* force a restore */
		15447	crtc_state->mode_changed = true;
3243	Serge	15448	}
2332	Serge	15449
6084	serge	15450	for_each_intel_plane(dev, plane) {
		15451	ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
		15452	if (ret)
		15453	goto err;
		15454	}
		15455
		15456	for_each_intel_connector(dev, conn) {
		15457	ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
		15458	if (ret)
		15459	goto err;
		15460	}
		15461
		15462	intel_modeset_setup_hw_state(dev);
		15463
		15464	i915_redisable_vga(dev);
		15465	ret = drm_atomic_commit(state);
		15466	if (!ret)
		15467	return;
		15468
		15469	err:
		15470	DRM_ERROR("Restoring old state failed with %i\n", ret);
		15471	drm_atomic_state_free(state);
2332	Serge	15472	}
		15473
3031	serge	15474	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	15475	{
5060	serge	15476	struct drm_crtc *c;
		15477	struct drm_i915_gem_object *obj;
6084	serge	15478	int ret;
5060	serge	15479
		15480	mutex_lock(&dev->struct_mutex);
		15481	intel_init_gt_powersave(dev);
		15482	mutex_unlock(&dev->struct_mutex);
		15483
3031	serge	15484	intel_modeset_init_hw(dev);
2330	Serge	15485
3031	serge	15486	// intel_setup_overlay(dev);
2330	Serge	15487
5060	serge	15488	/*
		15489	* Make sure any fbs we allocated at startup are properly
		15490	* pinned & fenced. When we do the allocation it's too early
		15491	* for this.
		15492	*/
		15493	for_each_crtc(dev, c) {
		15494	obj = intel_fb_obj(c->primary->fb);
		15495	if (obj == NULL)
		15496	continue;
		15497
6084	serge	15498	mutex_lock(&dev->struct_mutex);
		15499	ret = intel_pin_and_fence_fb_obj(c->primary,
		15500	c->primary->fb,
		15501	c->primary->state,
		15502	NULL, NULL);
		15503	mutex_unlock(&dev->struct_mutex);
		15504	if (ret) {
5060	serge	15505	DRM_ERROR("failed to pin boot fb on pipe %d\n",
		15506	to_intel_crtc(c)->pipe);
		15507	drm_framebuffer_unreference(c->primary->fb);
		15508	c->primary->fb = NULL;
6084	serge	15509	c->primary->crtc = c->primary->state->crtc = NULL;
		15510	update_state_fb(c->primary);
		15511	c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
5060	serge	15512	}
		15513	}
6084	serge	15514
		15515	intel_backlight_register(dev);
2330	Serge	15516	}
		15517
5060	serge	15518	void intel_connector_unregister(struct intel_connector *intel_connector)
		15519	{
		15520	struct drm_connector *connector = &intel_connector->base;
		15521
		15522	intel_panel_destroy_backlight(connector);
		15523	drm_connector_unregister(connector);
		15524	}
		15525
3031	serge	15526	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	15527	{
3031	serge	15528	#if 0
		15529	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	15530	struct drm_connector *connector;
2327	Serge	15531
5354	serge	15532	intel_disable_gt_powersave(dev);
		15533
		15534	intel_backlight_unregister(dev);
		15535
4104	Serge	15536	/*
		15537	* Interrupts and polling as the first thing to avoid creating havoc.
5354	serge	15538	* Too much stuff here (turning of connectors, ...) would
4104	Serge	15539	* experience fancy races otherwise.
		15540	*/
5354	serge	15541	intel_irq_uninstall(dev_priv);
5060	serge	15542
4104	Serge	15543	/*
		15544	* Due to the hpd irq storm handling the hotplug work can re-arm the
		15545	* poll handlers. Hence disable polling after hpd handling is shut down.
		15546	*/
4560	Serge	15547	drm_kms_helper_poll_fini(dev);
4104	Serge	15548
4560	Serge	15549	intel_unregister_dsm_handler();
2327	Serge	15550
6084	serge	15551	intel_fbc_disable(dev_priv);
2342	Serge	15552
4104	Serge	15553	/* flush any delayed tasks or pending work */
		15554	flush_scheduled_work();
2327	Serge	15555
4560	Serge	15556	/* destroy the backlight and sysfs files before encoders/connectors */
		15557	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5060	serge	15558	struct intel_connector *intel_connector;
		15559
		15560	intel_connector = to_intel_connector(connector);
		15561	intel_connector->unregister(intel_connector);
4560	Serge	15562	}
2327	Serge	15563
3031	serge	15564	drm_mode_config_cleanup(dev);
5060	serge	15565
		15566	intel_cleanup_overlay(dev);
		15567
		15568	mutex_lock(&dev->struct_mutex);
		15569	intel_cleanup_gt_powersave(dev);
		15570	mutex_unlock(&dev->struct_mutex);
2327	Serge	15571	#endif
		15572	}
		15573
		15574	/*
3031	serge	15575	* Return which encoder is currently attached for connector.
2327	Serge	15576	*/
3031	serge	15577	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	15578	{
3031	serge	15579	return &intel_attached_encoder(connector)->base;
		15580	}
2327	Serge	15581
3031	serge	15582	void intel_connector_attach_encoder(struct intel_connector *connector,
		15583	struct intel_encoder *encoder)
		15584	{
		15585	connector->encoder = encoder;
		15586	drm_mode_connector_attach_encoder(&connector->base,
		15587	&encoder->base);
2327	Serge	15588	}
		15589
		15590	/*
3031	serge	15591	* set vga decode state - true == enable VGA decode
2327	Serge	15592	*/
3031	serge	15593	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	15594	{
2330	Serge	15595	struct drm_i915_private *dev_priv = dev->dev_private;
4539	Serge	15596	unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
3031	serge	15597	u16 gmch_ctrl;
2327	Serge	15598
5060	serge	15599	if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
		15600	DRM_ERROR("failed to read control word\n");
		15601	return -EIO;
		15602	}
		15603
		15604	if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
		15605	return 0;
		15606
3031	serge	15607	if (state)
		15608	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	15609	else
3031	serge	15610	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
5060	serge	15611
		15612	if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
		15613	DRM_ERROR("failed to write control word\n");
		15614	return -EIO;
		15615	}
		15616
3031	serge	15617	return 0;
2330	Serge	15618	}
		15619
3031	serge	15620	#ifdef CONFIG_DEBUG_FS
2327	Serge	15621
3031	serge	15622	struct intel_display_error_state {
4104	Serge	15623
		15624	u32 power_well_driver;
		15625
		15626	int num_transcoders;
		15627
3031	serge	15628	struct intel_cursor_error_state {
		15629	u32 control;
		15630	u32 position;
		15631	u32 base;
		15632	u32 size;
		15633	} cursor[I915_MAX_PIPES];
2327	Serge	15634
3031	serge	15635	struct intel_pipe_error_state {
4560	Serge	15636	bool power_domain_on;
3031	serge	15637	u32 source;
5060	serge	15638	u32 stat;
3031	serge	15639	} pipe[I915_MAX_PIPES];
2327	Serge	15640
3031	serge	15641	struct intel_plane_error_state {
		15642	u32 control;
		15643	u32 stride;
		15644	u32 size;
		15645	u32 pos;
		15646	u32 addr;
		15647	u32 surface;
		15648	u32 tile_offset;
		15649	} plane[I915_MAX_PIPES];
4104	Serge	15650
		15651	struct intel_transcoder_error_state {
4560	Serge	15652	bool power_domain_on;
4104	Serge	15653	enum transcoder cpu_transcoder;
		15654
		15655	u32 conf;
		15656
		15657	u32 htotal;
		15658	u32 hblank;
		15659	u32 hsync;
		15660	u32 vtotal;
		15661	u32 vblank;
		15662	u32 vsync;
		15663	} transcoder[4];
3031	serge	15664	};
2327	Serge	15665
3031	serge	15666	struct intel_display_error_state *
		15667	intel_display_capture_error_state(struct drm_device *dev)
		15668	{
5060	serge	15669	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	15670	struct intel_display_error_state *error;
4104	Serge	15671	int transcoders[] = {
		15672	TRANSCODER_A,
		15673	TRANSCODER_B,
		15674	TRANSCODER_C,
		15675	TRANSCODER_EDP,
		15676	};
3031	serge	15677	int i;
2327	Serge	15678
4104	Serge	15679	if (INTEL_INFO(dev)->num_pipes == 0)
		15680	return NULL;
		15681
4560	Serge	15682	error = kzalloc(sizeof(*error), GFP_ATOMIC);
3031	serge	15683	if (error == NULL)
		15684	return NULL;
2327	Serge	15685
4560	Serge	15686	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
4104	Serge	15687	error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
		15688
5354	serge	15689	for_each_pipe(dev_priv, i) {
4560	Serge	15690	error->pipe[i].power_domain_on =
5354	serge	15691	__intel_display_power_is_enabled(dev_priv,
6084	serge	15692	POWER_DOMAIN_PIPE(i));
4560	Serge	15693	if (!error->pipe[i].power_domain_on)
		15694	continue;
		15695
3031	serge	15696	error->cursor[i].control = I915_READ(CURCNTR(i));
		15697	error->cursor[i].position = I915_READ(CURPOS(i));
		15698	error->cursor[i].base = I915_READ(CURBASE(i));
2327	Serge	15699
3031	serge	15700	error->plane[i].control = I915_READ(DSPCNTR(i));
		15701	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
3746	Serge	15702	if (INTEL_INFO(dev)->gen <= 3) {
6084	serge	15703	error->plane[i].size = I915_READ(DSPSIZE(i));
		15704	error->plane[i].pos = I915_READ(DSPPOS(i));
3746	Serge	15705	}
		15706	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
6084	serge	15707	error->plane[i].addr = I915_READ(DSPADDR(i));
3031	serge	15708	if (INTEL_INFO(dev)->gen >= 4) {
		15709	error->plane[i].surface = I915_READ(DSPSURF(i));
		15710	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		15711	}
2327	Serge	15712
3031	serge	15713	error->pipe[i].source = I915_READ(PIPESRC(i));
5060	serge	15714
		15715	if (HAS_GMCH_DISPLAY(dev))
		15716	error->pipe[i].stat = I915_READ(PIPESTAT(i));
3031	serge	15717	}
2327	Serge	15718
4104	Serge	15719	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
		15720	if (HAS_DDI(dev_priv->dev))
		15721	error->num_transcoders++; /* Account for eDP. */
		15722
		15723	for (i = 0; i < error->num_transcoders; i++) {
		15724	enum transcoder cpu_transcoder = transcoders[i];
		15725
4560	Serge	15726	error->transcoder[i].power_domain_on =
5354	serge	15727	__intel_display_power_is_enabled(dev_priv,
4560	Serge	15728	POWER_DOMAIN_TRANSCODER(cpu_transcoder));
		15729	if (!error->transcoder[i].power_domain_on)
		15730	continue;
		15731
4104	Serge	15732	error->transcoder[i].cpu_transcoder = cpu_transcoder;
		15733
		15734	error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
		15735	error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		15736	error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		15737	error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		15738	error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		15739	error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		15740	error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
		15741	}
		15742
3031	serge	15743	return error;
2330	Serge	15744	}
2327	Serge	15745
4104	Serge	15746	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		15747
3031	serge	15748	void
4104	Serge	15749	intel_display_print_error_state(struct drm_i915_error_state_buf *m,
3031	serge	15750	struct drm_device *dev,
		15751	struct intel_display_error_state *error)
2332	Serge	15752	{
5354	serge	15753	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	15754	int i;
2330	Serge	15755
4104	Serge	15756	if (!error)
		15757	return;
		15758
		15759	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
4560	Serge	15760	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
4104	Serge	15761	err_printf(m, "PWR_WELL_CTL2: %08x\n",
		15762	error->power_well_driver);
5354	serge	15763	for_each_pipe(dev_priv, i) {
4104	Serge	15764	err_printf(m, "Pipe [%d]:\n", i);
4560	Serge	15765	err_printf(m, " Power: %s\n",
		15766	error->pipe[i].power_domain_on ? "on" : "off");
4104	Serge	15767	err_printf(m, " SRC: %08x\n", error->pipe[i].source);
5060	serge	15768	err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
2332	Serge	15769
4104	Serge	15770	err_printf(m, "Plane [%d]:\n", i);
		15771	err_printf(m, " CNTR: %08x\n", error->plane[i].control);
		15772	err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
3746	Serge	15773	if (INTEL_INFO(dev)->gen <= 3) {
4104	Serge	15774	err_printf(m, " SIZE: %08x\n", error->plane[i].size);
		15775	err_printf(m, " POS: %08x\n", error->plane[i].pos);
3746	Serge	15776	}
		15777	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
4104	Serge	15778	err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
3031	serge	15779	if (INTEL_INFO(dev)->gen >= 4) {
4104	Serge	15780	err_printf(m, " SURF: %08x\n", error->plane[i].surface);
		15781	err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
3031	serge	15782	}
2332	Serge	15783
4104	Serge	15784	err_printf(m, "Cursor [%d]:\n", i);
		15785	err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		15786	err_printf(m, " POS: %08x\n", error->cursor[i].position);
		15787	err_printf(m, " BASE: %08x\n", error->cursor[i].base);
3031	serge	15788	}
4104	Serge	15789
		15790	for (i = 0; i < error->num_transcoders; i++) {
4560	Serge	15791	err_printf(m, "CPU transcoder: %c\n",
4104	Serge	15792	transcoder_name(error->transcoder[i].cpu_transcoder));
4560	Serge	15793	err_printf(m, " Power: %s\n",
		15794	error->transcoder[i].power_domain_on ? "on" : "off");
4104	Serge	15795	err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
		15796	err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
		15797	err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
		15798	err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
		15799	err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
		15800	err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
		15801	err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
		15802	}
2327	Serge	15803	}
3031	serge	15804	#endif
5354	serge	15805
		15806	void intel_modeset_preclose(struct drm_device dev, struct drm_file file)
		15807	{
		15808	struct intel_crtc *crtc;
		15809
		15810	for_each_intel_crtc(dev, crtc) {
		15811	struct intel_unpin_work *work;
		15812
		15813	spin_lock_irq(&dev->event_lock);
		15814
		15815	work = crtc->unpin_work;
		15816
		15817	if (work && work->event &&
		15818	work->event->base.file_priv == file) {
		15819	kfree(work->event);
		15820	work->event = NULL;
		15821	}
		15822
		15823	spin_unlock_irq(&dev->event_lock);
		15824	}
		15825	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c – Rev 6320