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2327 Serge 1
/*
2
 * Copyright © 2006-2007 Intel Corporation
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the "Software"),
6
 * to deal in the Software without restriction, including without limitation
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
 * and/or sell copies of the Software, and to permit persons to whom the
9
 * Software is furnished to do so, subject to the following conditions:
10
 *
11
 * The above copyright notice and this permission notice (including the next
12
 * paragraph) shall be included in all copies or substantial portions of the
13
 * Software.
14
 *
15
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21
 * DEALINGS IN THE SOFTWARE.
22
 *
23
 * Authors:
6084 serge 24
 *	Eric Anholt 
2327 Serge 25
 */
26
 
5097 serge 27
#include 
2327 Serge 28
#include 
6088 serge 29
#include 
2327 Serge 30
#include 
31
#include 
2330 Serge 32
#include 
5354 serge 33
#include 
2342 Serge 34
#include 
3031 serge 35
#include 
2327 Serge 36
#include "intel_drv.h"
3031 serge 37
#include 
2327 Serge 38
#include "i915_drv.h"
2351 Serge 39
#include "i915_trace.h"
6084 serge 40
#include 
41
#include 
3031 serge 42
#include 
43
#include 
5060 serge 44
#include 
45
#include 
46
#include 
2327 Serge 47
 
5060 serge 48
/* Primary plane formats for gen <= 3 */
6084 serge 49
static const uint32_t i8xx_primary_formats[] = {
50
	DRM_FORMAT_C8,
51
	DRM_FORMAT_RGB565,
5060 serge 52
	DRM_FORMAT_XRGB1555,
6084 serge 53
	DRM_FORMAT_XRGB8888,
5060 serge 54
};
55
 
56
/* Primary plane formats for gen >= 4 */
6084 serge 57
static const uint32_t i965_primary_formats[] = {
58
	DRM_FORMAT_C8,
59
	DRM_FORMAT_RGB565,
60
	DRM_FORMAT_XRGB8888,
5060 serge 61
	DRM_FORMAT_XBGR8888,
6084 serge 62
	DRM_FORMAT_XRGB2101010,
63
	DRM_FORMAT_XBGR2101010,
64
};
65
 
66
static const uint32_t skl_primary_formats[] = {
67
	DRM_FORMAT_C8,
68
	DRM_FORMAT_RGB565,
69
	DRM_FORMAT_XRGB8888,
70
	DRM_FORMAT_XBGR8888,
71
	DRM_FORMAT_ARGB8888,
5060 serge 72
	DRM_FORMAT_ABGR8888,
73
	DRM_FORMAT_XRGB2101010,
74
	DRM_FORMAT_XBGR2101010,
6084 serge 75
	DRM_FORMAT_YUYV,
76
	DRM_FORMAT_YVYU,
77
	DRM_FORMAT_UYVY,
78
	DRM_FORMAT_VYUY,
5060 serge 79
};
80
 
81
/* Cursor formats */
82
static const uint32_t intel_cursor_formats[] = {
83
	DRM_FORMAT_ARGB8888,
84
};
85
 
86
void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327 Serge 87
 
4104 Serge 88
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6084 serge 89
				struct intel_crtc_state *pipe_config);
4560 Serge 90
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
6084 serge 91
				   struct intel_crtc_state *pipe_config);
2327 Serge 92
 
5060 serge 93
static int intel_framebuffer_init(struct drm_device *dev,
94
				  struct intel_framebuffer *ifb,
95
				  struct drm_mode_fb_cmd2 *mode_cmd,
96
				  struct drm_i915_gem_object *obj);
97
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99
static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5354 serge 100
					 struct intel_link_m_n *m_n,
101
					 struct intel_link_m_n *m2_n2);
5060 serge 102
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103
static void haswell_set_pipeconf(struct drm_crtc *crtc);
104
static void intel_set_pipe_csc(struct drm_crtc *crtc);
5354 serge 105
static void vlv_prepare_pll(struct intel_crtc *crtc,
6084 serge 106
			    const struct intel_crtc_state *pipe_config);
5354 serge 107
static void chv_prepare_pll(struct intel_crtc *crtc,
6084 serge 108
			    const struct intel_crtc_state *pipe_config);
109
static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110
static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111
static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112
	struct intel_crtc_state *crtc_state);
113
static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114
			   int num_connectors);
115
static void skylake_pfit_enable(struct intel_crtc *crtc);
116
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117
static void ironlake_pfit_enable(struct intel_crtc *crtc);
118
static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
static void intel_pre_disable_primary(struct drm_crtc *crtc);
4104 Serge 120
 
2327 Serge 121
typedef struct {
6084 serge 122
	int	min, max;
2327 Serge 123
} intel_range_t;
124
 
125
typedef struct {
6084 serge 126
	int	dot_limit;
127
	int	p2_slow, p2_fast;
2327 Serge 128
} intel_p2_t;
129
 
130
typedef struct intel_limit intel_limit_t;
131
struct intel_limit {
6084 serge 132
	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
133
	intel_p2_t	    p2;
2327 Serge 134
};
135
 
6084 serge 136
/* returns HPLL frequency in kHz */
137
static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138
{
139
	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
 
141
	/* Obtain SKU information */
142
	mutex_lock(&dev_priv->sb_lock);
143
	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144
		CCK_FUSE_HPLL_FREQ_MASK;
145
	mutex_unlock(&dev_priv->sb_lock);
146
 
147
	return vco_freq[hpll_freq] * 1000;
148
}
149
 
150
static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
151
				  const char *name, u32 reg)
152
{
153
	u32 val;
154
	int divider;
155
 
156
	if (dev_priv->hpll_freq == 0)
157
		dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158
 
159
	mutex_lock(&dev_priv->sb_lock);
160
	val = vlv_cck_read(dev_priv, reg);
161
	mutex_unlock(&dev_priv->sb_lock);
162
 
163
	divider = val & CCK_FREQUENCY_VALUES;
164
 
165
	WARN((val & CCK_FREQUENCY_STATUS) !=
166
	     (divider << CCK_FREQUENCY_STATUS_SHIFT),
167
	     "%s change in progress\n", name);
168
 
169
	return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
170
}
171
 
3243 Serge 172
int
173
intel_pch_rawclk(struct drm_device *dev)
174
{
175
	struct drm_i915_private *dev_priv = dev->dev_private;
176
 
177
	WARN_ON(!HAS_PCH_SPLIT(dev));
178
 
179
	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
180
}
181
 
6084 serge 182
/* hrawclock is 1/4 the FSB frequency */
183
int intel_hrawclk(struct drm_device *dev)
184
{
185
	struct drm_i915_private *dev_priv = dev->dev_private;
186
	uint32_t clkcfg;
187
 
188
	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
189
	if (IS_VALLEYVIEW(dev))
190
		return 200;
191
 
192
	clkcfg = I915_READ(CLKCFG);
193
	switch (clkcfg & CLKCFG_FSB_MASK) {
194
	case CLKCFG_FSB_400:
195
		return 100;
196
	case CLKCFG_FSB_533:
197
		return 133;
198
	case CLKCFG_FSB_667:
199
		return 166;
200
	case CLKCFG_FSB_800:
201
		return 200;
202
	case CLKCFG_FSB_1067:
203
		return 266;
204
	case CLKCFG_FSB_1333:
205
		return 333;
206
	/* these two are just a guess; one of them might be right */
207
	case CLKCFG_FSB_1600:
208
	case CLKCFG_FSB_1600_ALT:
209
		return 400;
210
	default:
211
		return 133;
212
	}
213
}
214
 
215
static void intel_update_czclk(struct drm_i915_private *dev_priv)
216
{
217
	if (!IS_VALLEYVIEW(dev_priv))
218
		return;
219
 
220
	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
221
						      CCK_CZ_CLOCK_CONTROL);
222
 
223
	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
224
}
225
 
2327 Serge 226
static inline u32 /* units of 100MHz */
227
intel_fdi_link_freq(struct drm_device *dev)
228
{
229
	if (IS_GEN5(dev)) {
230
		struct drm_i915_private *dev_priv = dev->dev_private;
231
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
232
	} else
233
		return 27;
234
}
235
 
4104 Serge 236
static const intel_limit_t intel_limits_i8xx_dac = {
237
	.dot = { .min = 25000, .max = 350000 },
4560 Serge 238
	.vco = { .min = 908000, .max = 1512000 },
239
	.n = { .min = 2, .max = 16 },
4104 Serge 240
	.m = { .min = 96, .max = 140 },
241
	.m1 = { .min = 18, .max = 26 },
242
	.m2 = { .min = 6, .max = 16 },
243
	.p = { .min = 4, .max = 128 },
244
	.p1 = { .min = 2, .max = 33 },
245
	.p2 = { .dot_limit = 165000,
246
		.p2_slow = 4, .p2_fast = 2 },
247
};
248
 
2327 Serge 249
static const intel_limit_t intel_limits_i8xx_dvo = {
6084 serge 250
	.dot = { .min = 25000, .max = 350000 },
4560 Serge 251
	.vco = { .min = 908000, .max = 1512000 },
252
	.n = { .min = 2, .max = 16 },
6084 serge 253
	.m = { .min = 96, .max = 140 },
254
	.m1 = { .min = 18, .max = 26 },
255
	.m2 = { .min = 6, .max = 16 },
256
	.p = { .min = 4, .max = 128 },
257
	.p1 = { .min = 2, .max = 33 },
2327 Serge 258
	.p2 = { .dot_limit = 165000,
4104 Serge 259
		.p2_slow = 4, .p2_fast = 4 },
2327 Serge 260
};
261
 
262
static const intel_limit_t intel_limits_i8xx_lvds = {
6084 serge 263
	.dot = { .min = 25000, .max = 350000 },
4560 Serge 264
	.vco = { .min = 908000, .max = 1512000 },
265
	.n = { .min = 2, .max = 16 },
6084 serge 266
	.m = { .min = 96, .max = 140 },
267
	.m1 = { .min = 18, .max = 26 },
268
	.m2 = { .min = 6, .max = 16 },
269
	.p = { .min = 4, .max = 128 },
270
	.p1 = { .min = 1, .max = 6 },
2327 Serge 271
	.p2 = { .dot_limit = 165000,
272
		.p2_slow = 14, .p2_fast = 7 },
273
};
274
 
275
static const intel_limit_t intel_limits_i9xx_sdvo = {
6084 serge 276
	.dot = { .min = 20000, .max = 400000 },
277
	.vco = { .min = 1400000, .max = 2800000 },
278
	.n = { .min = 1, .max = 6 },
279
	.m = { .min = 70, .max = 120 },
3480 Serge 280
	.m1 = { .min = 8, .max = 18 },
281
	.m2 = { .min = 3, .max = 7 },
6084 serge 282
	.p = { .min = 5, .max = 80 },
283
	.p1 = { .min = 1, .max = 8 },
2327 Serge 284
	.p2 = { .dot_limit = 200000,
285
		.p2_slow = 10, .p2_fast = 5 },
286
};
287
 
288
static const intel_limit_t intel_limits_i9xx_lvds = {
6084 serge 289
	.dot = { .min = 20000, .max = 400000 },
290
	.vco = { .min = 1400000, .max = 2800000 },
291
	.n = { .min = 1, .max = 6 },
292
	.m = { .min = 70, .max = 120 },
3480 Serge 293
	.m1 = { .min = 8, .max = 18 },
294
	.m2 = { .min = 3, .max = 7 },
6084 serge 295
	.p = { .min = 7, .max = 98 },
296
	.p1 = { .min = 1, .max = 8 },
2327 Serge 297
	.p2 = { .dot_limit = 112000,
298
		.p2_slow = 14, .p2_fast = 7 },
299
};
300
 
301
 
302
static const intel_limit_t intel_limits_g4x_sdvo = {
303
	.dot = { .min = 25000, .max = 270000 },
304
	.vco = { .min = 1750000, .max = 3500000},
305
	.n = { .min = 1, .max = 4 },
306
	.m = { .min = 104, .max = 138 },
307
	.m1 = { .min = 17, .max = 23 },
308
	.m2 = { .min = 5, .max = 11 },
309
	.p = { .min = 10, .max = 30 },
310
	.p1 = { .min = 1, .max = 3},
311
	.p2 = { .dot_limit = 270000,
312
		.p2_slow = 10,
313
		.p2_fast = 10
314
	},
315
};
316
 
317
static const intel_limit_t intel_limits_g4x_hdmi = {
318
	.dot = { .min = 22000, .max = 400000 },
319
	.vco = { .min = 1750000, .max = 3500000},
320
	.n = { .min = 1, .max = 4 },
321
	.m = { .min = 104, .max = 138 },
322
	.m1 = { .min = 16, .max = 23 },
323
	.m2 = { .min = 5, .max = 11 },
324
	.p = { .min = 5, .max = 80 },
325
	.p1 = { .min = 1, .max = 8},
326
	.p2 = { .dot_limit = 165000,
327
		.p2_slow = 10, .p2_fast = 5 },
328
};
329
 
330
static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
331
	.dot = { .min = 20000, .max = 115000 },
332
	.vco = { .min = 1750000, .max = 3500000 },
333
	.n = { .min = 1, .max = 3 },
334
	.m = { .min = 104, .max = 138 },
335
	.m1 = { .min = 17, .max = 23 },
336
	.m2 = { .min = 5, .max = 11 },
337
	.p = { .min = 28, .max = 112 },
338
	.p1 = { .min = 2, .max = 8 },
339
	.p2 = { .dot_limit = 0,
340
		.p2_slow = 14, .p2_fast = 14
341
	},
342
};
343
 
344
static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
345
	.dot = { .min = 80000, .max = 224000 },
346
	.vco = { .min = 1750000, .max = 3500000 },
347
	.n = { .min = 1, .max = 3 },
348
	.m = { .min = 104, .max = 138 },
349
	.m1 = { .min = 17, .max = 23 },
350
	.m2 = { .min = 5, .max = 11 },
351
	.p = { .min = 14, .max = 42 },
352
	.p1 = { .min = 2, .max = 6 },
353
	.p2 = { .dot_limit = 0,
354
		.p2_slow = 7, .p2_fast = 7
355
	},
356
};
357
 
358
static const intel_limit_t intel_limits_pineview_sdvo = {
6084 serge 359
	.dot = { .min = 20000, .max = 400000},
360
	.vco = { .min = 1700000, .max = 3500000 },
2327 Serge 361
	/* Pineview's Ncounter is a ring counter */
6084 serge 362
	.n = { .min = 3, .max = 6 },
363
	.m = { .min = 2, .max = 256 },
2327 Serge 364
	/* Pineview only has one combined m divider, which we treat as m2. */
6084 serge 365
	.m1 = { .min = 0, .max = 0 },
366
	.m2 = { .min = 0, .max = 254 },
367
	.p = { .min = 5, .max = 80 },
368
	.p1 = { .min = 1, .max = 8 },
2327 Serge 369
	.p2 = { .dot_limit = 200000,
370
		.p2_slow = 10, .p2_fast = 5 },
371
};
372
 
373
static const intel_limit_t intel_limits_pineview_lvds = {
6084 serge 374
	.dot = { .min = 20000, .max = 400000 },
375
	.vco = { .min = 1700000, .max = 3500000 },
376
	.n = { .min = 3, .max = 6 },
377
	.m = { .min = 2, .max = 256 },
378
	.m1 = { .min = 0, .max = 0 },
379
	.m2 = { .min = 0, .max = 254 },
380
	.p = { .min = 7, .max = 112 },
381
	.p1 = { .min = 1, .max = 8 },
2327 Serge 382
	.p2 = { .dot_limit = 112000,
383
		.p2_slow = 14, .p2_fast = 14 },
384
};
385
 
386
/* Ironlake / Sandybridge
387
 *
388
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
389
 * the range value for them is (actual_value - 2).
390
 */
391
static const intel_limit_t intel_limits_ironlake_dac = {
392
	.dot = { .min = 25000, .max = 350000 },
393
	.vco = { .min = 1760000, .max = 3510000 },
394
	.n = { .min = 1, .max = 5 },
395
	.m = { .min = 79, .max = 127 },
396
	.m1 = { .min = 12, .max = 22 },
397
	.m2 = { .min = 5, .max = 9 },
398
	.p = { .min = 5, .max = 80 },
399
	.p1 = { .min = 1, .max = 8 },
400
	.p2 = { .dot_limit = 225000,
401
		.p2_slow = 10, .p2_fast = 5 },
402
};
403
 
404
static const intel_limit_t intel_limits_ironlake_single_lvds = {
405
	.dot = { .min = 25000, .max = 350000 },
406
	.vco = { .min = 1760000, .max = 3510000 },
407
	.n = { .min = 1, .max = 3 },
408
	.m = { .min = 79, .max = 118 },
409
	.m1 = { .min = 12, .max = 22 },
410
	.m2 = { .min = 5, .max = 9 },
411
	.p = { .min = 28, .max = 112 },
412
	.p1 = { .min = 2, .max = 8 },
413
	.p2 = { .dot_limit = 225000,
414
		.p2_slow = 14, .p2_fast = 14 },
415
};
416
 
417
static const intel_limit_t intel_limits_ironlake_dual_lvds = {
418
	.dot = { .min = 25000, .max = 350000 },
419
	.vco = { .min = 1760000, .max = 3510000 },
420
	.n = { .min = 1, .max = 3 },
421
	.m = { .min = 79, .max = 127 },
422
	.m1 = { .min = 12, .max = 22 },
423
	.m2 = { .min = 5, .max = 9 },
424
	.p = { .min = 14, .max = 56 },
425
	.p1 = { .min = 2, .max = 8 },
426
	.p2 = { .dot_limit = 225000,
427
		.p2_slow = 7, .p2_fast = 7 },
428
};
429
 
430
/* LVDS 100mhz refclk limits. */
431
static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
432
	.dot = { .min = 25000, .max = 350000 },
433
	.vco = { .min = 1760000, .max = 3510000 },
434
	.n = { .min = 1, .max = 2 },
435
	.m = { .min = 79, .max = 126 },
436
	.m1 = { .min = 12, .max = 22 },
437
	.m2 = { .min = 5, .max = 9 },
438
	.p = { .min = 28, .max = 112 },
2342 Serge 439
	.p1 = { .min = 2, .max = 8 },
2327 Serge 440
	.p2 = { .dot_limit = 225000,
441
		.p2_slow = 14, .p2_fast = 14 },
442
};
443
 
444
static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
445
	.dot = { .min = 25000, .max = 350000 },
446
	.vco = { .min = 1760000, .max = 3510000 },
447
	.n = { .min = 1, .max = 3 },
448
	.m = { .min = 79, .max = 126 },
449
	.m1 = { .min = 12, .max = 22 },
450
	.m2 = { .min = 5, .max = 9 },
451
	.p = { .min = 14, .max = 42 },
2342 Serge 452
	.p1 = { .min = 2, .max = 6 },
2327 Serge 453
	.p2 = { .dot_limit = 225000,
454
		.p2_slow = 7, .p2_fast = 7 },
455
};
456
 
4560 Serge 457
static const intel_limit_t intel_limits_vlv = {
458
	 /*
459
	  * These are the data rate limits (measured in fast clocks)
460
	  * since those are the strictest limits we have. The fast
461
	  * clock and actual rate limits are more relaxed, so checking
462
	  * them would make no difference.
463
	  */
464
	.dot = { .min = 25000 * 5, .max = 270000 * 5 },
3031 serge 465
	.vco = { .min = 4000000, .max = 6000000 },
466
	.n = { .min = 1, .max = 7 },
467
	.m1 = { .min = 2, .max = 3 },
468
	.m2 = { .min = 11, .max = 156 },
469
	.p1 = { .min = 2, .max = 3 },
4560 Serge 470
	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
3031 serge 471
};
472
 
5060 serge 473
static const intel_limit_t intel_limits_chv = {
474
	/*
475
	 * These are the data rate limits (measured in fast clocks)
476
	 * since those are the strictest limits we have.  The fast
477
	 * clock and actual rate limits are more relaxed, so checking
478
	 * them would make no difference.
479
	 */
480
	.dot = { .min = 25000 * 5, .max = 540000 * 5},
6084 serge 481
	.vco = { .min = 4800000, .max = 6480000 },
5060 serge 482
	.n = { .min = 1, .max = 1 },
483
	.m1 = { .min = 2, .max = 2 },
484
	.m2 = { .min = 24 << 22, .max = 175 << 22 },
485
	.p1 = { .min = 2, .max = 4 },
486
	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
487
};
488
 
6084 serge 489
static const intel_limit_t intel_limits_bxt = {
490
	/* FIXME: find real dot limits */
491
	.dot = { .min = 0, .max = INT_MAX },
492
	.vco = { .min = 4800000, .max = 6700000 },
493
	.n = { .min = 1, .max = 1 },
494
	.m1 = { .min = 2, .max = 2 },
495
	/* FIXME: find real m2 limits */
496
	.m2 = { .min = 2 << 22, .max = 255 << 22 },
497
	.p1 = { .min = 2, .max = 4 },
498
	.p2 = { .p2_slow = 1, .p2_fast = 20 },
499
};
500
 
501
static bool
502
needs_modeset(struct drm_crtc_state *state)
4560 Serge 503
{
6084 serge 504
	return drm_atomic_crtc_needs_modeset(state);
4560 Serge 505
}
3031 serge 506
 
4560 Serge 507
/**
508
 * Returns whether any output on the specified pipe is of the specified type
509
 */
5354 serge 510
bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
4560 Serge 511
{
5354 serge 512
	struct drm_device *dev = crtc->base.dev;
4560 Serge 513
	struct intel_encoder *encoder;
514
 
5354 serge 515
	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4560 Serge 516
		if (encoder->type == type)
517
			return true;
518
 
519
	return false;
520
}
521
 
5354 serge 522
/**
523
 * Returns whether any output on the specified pipe will have the specified
524
 * type after a staged modeset is complete, i.e., the same as
525
 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
526
 * encoder->crtc.
527
 */
6084 serge 528
static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
529
				      int type)
5354 serge 530
{
6084 serge 531
	struct drm_atomic_state *state = crtc_state->base.state;
532
	struct drm_connector *connector;
533
	struct drm_connector_state *connector_state;
5354 serge 534
	struct intel_encoder *encoder;
6084 serge 535
	int i, num_connectors = 0;
5354 serge 536
 
6084 serge 537
	for_each_connector_in_state(state, connector, connector_state, i) {
538
		if (connector_state->crtc != crtc_state->base.crtc)
539
			continue;
540
 
541
		num_connectors++;
542
 
543
		encoder = to_intel_encoder(connector_state->best_encoder);
544
		if (encoder->type == type)
5354 serge 545
			return true;
6084 serge 546
	}
5354 serge 547
 
6084 serge 548
	WARN_ON(num_connectors == 0);
549
 
5354 serge 550
	return false;
551
}
552
 
6084 serge 553
static const intel_limit_t *
554
intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2327 Serge 555
{
6084 serge 556
	struct drm_device *dev = crtc_state->base.crtc->dev;
2327 Serge 557
	const intel_limit_t *limit;
558
 
6084 serge 559
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
3480 Serge 560
		if (intel_is_dual_link_lvds(dev)) {
2327 Serge 561
			if (refclk == 100000)
562
				limit = &intel_limits_ironlake_dual_lvds_100m;
563
			else
564
				limit = &intel_limits_ironlake_dual_lvds;
565
		} else {
566
			if (refclk == 100000)
567
				limit = &intel_limits_ironlake_single_lvds_100m;
568
			else
569
				limit = &intel_limits_ironlake_single_lvds;
570
		}
4104 Serge 571
	} else
2327 Serge 572
		limit = &intel_limits_ironlake_dac;
573
 
574
	return limit;
575
}
576
 
6084 serge 577
static const intel_limit_t *
578
intel_g4x_limit(struct intel_crtc_state *crtc_state)
2327 Serge 579
{
6084 serge 580
	struct drm_device *dev = crtc_state->base.crtc->dev;
2327 Serge 581
	const intel_limit_t *limit;
582
 
6084 serge 583
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
3480 Serge 584
		if (intel_is_dual_link_lvds(dev))
2327 Serge 585
			limit = &intel_limits_g4x_dual_channel_lvds;
586
		else
587
			limit = &intel_limits_g4x_single_channel_lvds;
6084 serge 588
	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
589
		   intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
2327 Serge 590
		limit = &intel_limits_g4x_hdmi;
6084 serge 591
	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
2327 Serge 592
		limit = &intel_limits_g4x_sdvo;
593
	} else /* The option is for other outputs */
594
		limit = &intel_limits_i9xx_sdvo;
595
 
596
	return limit;
597
}
598
 
6084 serge 599
static const intel_limit_t *
600
intel_limit(struct intel_crtc_state *crtc_state, int refclk)
2327 Serge 601
{
6084 serge 602
	struct drm_device *dev = crtc_state->base.crtc->dev;
2327 Serge 603
	const intel_limit_t *limit;
604
 
6084 serge 605
	if (IS_BROXTON(dev))
606
		limit = &intel_limits_bxt;
607
	else if (HAS_PCH_SPLIT(dev))
608
		limit = intel_ironlake_limit(crtc_state, refclk);
2327 Serge 609
	else if (IS_G4X(dev)) {
6084 serge 610
		limit = intel_g4x_limit(crtc_state);
2327 Serge 611
	} else if (IS_PINEVIEW(dev)) {
6084 serge 612
		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
2327 Serge 613
			limit = &intel_limits_pineview_lvds;
614
		else
615
			limit = &intel_limits_pineview_sdvo;
5060 serge 616
	} else if (IS_CHERRYVIEW(dev)) {
617
		limit = &intel_limits_chv;
3031 serge 618
	} else if (IS_VALLEYVIEW(dev)) {
4560 Serge 619
		limit = &intel_limits_vlv;
2327 Serge 620
	} else if (!IS_GEN2(dev)) {
6084 serge 621
		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
2327 Serge 622
			limit = &intel_limits_i9xx_lvds;
623
		else
624
			limit = &intel_limits_i9xx_sdvo;
625
	} else {
6084 serge 626
		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
2327 Serge 627
			limit = &intel_limits_i8xx_lvds;
6084 serge 628
		else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4104 Serge 629
			limit = &intel_limits_i8xx_dvo;
2327 Serge 630
		else
4104 Serge 631
			limit = &intel_limits_i8xx_dac;
2327 Serge 632
	}
633
	return limit;
634
}
635
 
6084 serge 636
/*
637
 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
638
 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
639
 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
640
 * The helpers' return value is the rate of the clock that is fed to the
641
 * display engine's pipe which can be the above fast dot clock rate or a
642
 * divided-down version of it.
643
 */
2327 Serge 644
/* m1 is reserved as 0 in Pineview, n is a ring counter */
6084 serge 645
static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
2327 Serge 646
{
647
	clock->m = clock->m2 + 2;
648
	clock->p = clock->p1 * clock->p2;
4560 Serge 649
	if (WARN_ON(clock->n == 0 || clock->p == 0))
6084 serge 650
		return 0;
4560 Serge 651
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
652
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6084 serge 653
 
654
	return clock->dot;
2327 Serge 655
}
656
 
4104 Serge 657
static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
2327 Serge 658
{
4104 Serge 659
	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
660
}
661
 
6084 serge 662
static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
4104 Serge 663
{
664
	clock->m = i9xx_dpll_compute_m(clock);
2327 Serge 665
	clock->p = clock->p1 * clock->p2;
4560 Serge 666
	if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
6084 serge 667
		return 0;
4560 Serge 668
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
669
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6084 serge 670
 
671
	return clock->dot;
2327 Serge 672
}
673
 
6084 serge 674
static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
5060 serge 675
{
676
	clock->m = clock->m1 * clock->m2;
677
	clock->p = clock->p1 * clock->p2;
678
	if (WARN_ON(clock->n == 0 || clock->p == 0))
6084 serge 679
		return 0;
680
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
681
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682
 
683
	return clock->dot / 5;
684
}
685
 
686
int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
687
{
688
	clock->m = clock->m1 * clock->m2;
689
	clock->p = clock->p1 * clock->p2;
690
	if (WARN_ON(clock->n == 0 || clock->p == 0))
691
		return 0;
5060 serge 692
	clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
693
			clock->n << 22);
694
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6084 serge 695
 
696
	return clock->dot / 5;
5060 serge 697
}
698
 
2327 Serge 699
#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
700
/**
701
 * Returns whether the given set of divisors are valid for a given refclk with
702
 * the given connectors.
703
 */
704
 
705
static bool intel_PLL_is_valid(struct drm_device *dev,
706
			       const intel_limit_t *limit,
707
			       const intel_clock_t *clock)
708
{
4560 Serge 709
	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
710
		INTELPllInvalid("n out of range\n");
2327 Serge 711
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
2342 Serge 712
		INTELPllInvalid("p1 out of range\n");
2327 Serge 713
	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
2342 Serge 714
		INTELPllInvalid("m2 out of range\n");
2327 Serge 715
	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
2342 Serge 716
		INTELPllInvalid("m1 out of range\n");
4560 Serge 717
 
6084 serge 718
	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
4560 Serge 719
		if (clock->m1 <= clock->m2)
6084 serge 720
			INTELPllInvalid("m1 <= m2\n");
4560 Serge 721
 
6084 serge 722
	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
4560 Serge 723
		if (clock->p < limit->p.min || limit->p.max < clock->p)
724
			INTELPllInvalid("p out of range\n");
6084 serge 725
		if (clock->m < limit->m.min || limit->m.max < clock->m)
726
			INTELPllInvalid("m out of range\n");
4560 Serge 727
	}
728
 
2327 Serge 729
	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
2342 Serge 730
		INTELPllInvalid("vco out of range\n");
2327 Serge 731
	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
732
	 * connector, etc., rather than just a single range.
733
	 */
734
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
2342 Serge 735
		INTELPllInvalid("dot out of range\n");
2327 Serge 736
 
737
	return true;
738
}
739
 
6084 serge 740
static int
741
i9xx_select_p2_div(const intel_limit_t *limit,
742
		   const struct intel_crtc_state *crtc_state,
743
		   int target)
2327 Serge 744
{
6084 serge 745
	struct drm_device *dev = crtc_state->base.crtc->dev;
2327 Serge 746
 
6084 serge 747
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
2327 Serge 748
		/*
3480 Serge 749
		 * For LVDS just rely on its current settings for dual-channel.
750
		 * We haven't figured out how to reliably set up different
751
		 * single/dual channel state, if we even can.
2327 Serge 752
		 */
3480 Serge 753
		if (intel_is_dual_link_lvds(dev))
6084 serge 754
			return limit->p2.p2_fast;
2327 Serge 755
		else
6084 serge 756
			return limit->p2.p2_slow;
2327 Serge 757
	} else {
758
		if (target < limit->p2.dot_limit)
6084 serge 759
			return limit->p2.p2_slow;
2327 Serge 760
		else
6084 serge 761
			return limit->p2.p2_fast;
2327 Serge 762
	}
6084 serge 763
}
2327 Serge 764
 
6084 serge 765
static bool
766
i9xx_find_best_dpll(const intel_limit_t *limit,
767
		    struct intel_crtc_state *crtc_state,
768
		    int target, int refclk, intel_clock_t *match_clock,
769
		    intel_clock_t *best_clock)
770
{
771
	struct drm_device *dev = crtc_state->base.crtc->dev;
772
	intel_clock_t clock;
773
	int err = target;
774
 
2342 Serge 775
	memset(best_clock, 0, sizeof(*best_clock));
2327 Serge 776
 
6084 serge 777
	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
778
 
2327 Serge 779
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
780
	     clock.m1++) {
781
		for (clock.m2 = limit->m2.min;
782
		     clock.m2 <= limit->m2.max; clock.m2++) {
4104 Serge 783
			if (clock.m2 >= clock.m1)
2327 Serge 784
				break;
785
			for (clock.n = limit->n.min;
786
			     clock.n <= limit->n.max; clock.n++) {
787
				for (clock.p1 = limit->p1.min;
788
					clock.p1 <= limit->p1.max; clock.p1++) {
789
					int this_err;
790
 
6084 serge 791
					i9xx_calc_dpll_params(refclk, &clock);
2327 Serge 792
					if (!intel_PLL_is_valid(dev, limit,
793
								&clock))
794
						continue;
3031 serge 795
					if (match_clock &&
796
					    clock.p != match_clock->p)
797
						continue;
2327 Serge 798
 
799
					this_err = abs(clock.dot - target);
800
					if (this_err < err) {
801
						*best_clock = clock;
802
						err = this_err;
803
					}
804
				}
805
			}
806
		}
807
	}
808
 
809
	return (err != target);
810
}
811
 
812
static bool
6084 serge 813
pnv_find_best_dpll(const intel_limit_t *limit,
814
		   struct intel_crtc_state *crtc_state,
4104 Serge 815
		   int target, int refclk, intel_clock_t *match_clock,
816
		   intel_clock_t *best_clock)
817
{
6084 serge 818
	struct drm_device *dev = crtc_state->base.crtc->dev;
4104 Serge 819
	intel_clock_t clock;
820
	int err = target;
821
 
822
	memset(best_clock, 0, sizeof(*best_clock));
823
 
6084 serge 824
	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
825
 
4104 Serge 826
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
827
	     clock.m1++) {
828
		for (clock.m2 = limit->m2.min;
829
		     clock.m2 <= limit->m2.max; clock.m2++) {
830
			for (clock.n = limit->n.min;
831
			     clock.n <= limit->n.max; clock.n++) {
832
				for (clock.p1 = limit->p1.min;
833
					clock.p1 <= limit->p1.max; clock.p1++) {
834
					int this_err;
835
 
6084 serge 836
					pnv_calc_dpll_params(refclk, &clock);
4104 Serge 837
					if (!intel_PLL_is_valid(dev, limit,
838
								&clock))
839
						continue;
840
					if (match_clock &&
841
					    clock.p != match_clock->p)
842
						continue;
843
 
844
					this_err = abs(clock.dot - target);
845
					if (this_err < err) {
846
						*best_clock = clock;
847
						err = this_err;
848
					}
849
				}
850
			}
851
		}
852
	}
853
 
854
	return (err != target);
855
}
856
 
857
static bool
6084 serge 858
g4x_find_best_dpll(const intel_limit_t *limit,
859
		   struct intel_crtc_state *crtc_state,
860
		   int target, int refclk, intel_clock_t *match_clock,
861
		   intel_clock_t *best_clock)
2327 Serge 862
{
6084 serge 863
	struct drm_device *dev = crtc_state->base.crtc->dev;
2327 Serge 864
	intel_clock_t clock;
865
	int max_n;
6084 serge 866
	bool found = false;
2327 Serge 867
	/* approximately equals target * 0.00585 */
868
	int err_most = (target >> 8) + (target >> 9);
869
 
6084 serge 870
	memset(best_clock, 0, sizeof(*best_clock));
2327 Serge 871
 
6084 serge 872
	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
873
 
2327 Serge 874
	max_n = limit->n.max;
875
	/* based on hardware requirement, prefer smaller n to precision */
876
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
877
		/* based on hardware requirement, prefere larger m1,m2 */
878
		for (clock.m1 = limit->m1.max;
879
		     clock.m1 >= limit->m1.min; clock.m1--) {
880
			for (clock.m2 = limit->m2.max;
881
			     clock.m2 >= limit->m2.min; clock.m2--) {
882
				for (clock.p1 = limit->p1.max;
883
				     clock.p1 >= limit->p1.min; clock.p1--) {
884
					int this_err;
885
 
6084 serge 886
					i9xx_calc_dpll_params(refclk, &clock);
2327 Serge 887
					if (!intel_PLL_is_valid(dev, limit,
888
								&clock))
889
						continue;
890
 
891
					this_err = abs(clock.dot - target);
892
					if (this_err < err_most) {
893
						*best_clock = clock;
894
						err_most = this_err;
895
						max_n = clock.n;
896
						found = true;
897
					}
898
				}
899
			}
900
		}
901
	}
902
	return found;
903
}
904
 
6084 serge 905
/*
906
 * Check if the calculated PLL configuration is more optimal compared to the
907
 * best configuration and error found so far. Return the calculated error.
908
 */
909
static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
910
			       const intel_clock_t *calculated_clock,
911
			       const intel_clock_t *best_clock,
912
			       unsigned int best_error_ppm,
913
			       unsigned int *error_ppm)
914
{
915
	/*
916
	 * For CHV ignore the error and consider only the P value.
917
	 * Prefer a bigger P value based on HW requirements.
918
	 */
919
	if (IS_CHERRYVIEW(dev)) {
920
		*error_ppm = 0;
921
 
922
		return calculated_clock->p > best_clock->p;
923
	}
924
 
925
	if (WARN_ON_ONCE(!target_freq))
926
		return false;
927
 
928
	*error_ppm = div_u64(1000000ULL *
929
				abs(target_freq - calculated_clock->dot),
930
			     target_freq);
931
	/*
932
	 * Prefer a better P value over a better (smaller) error if the error
933
	 * is small. Ensure this preference for future configurations too by
934
	 * setting the error to 0.
935
	 */
936
	if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
937
		*error_ppm = 0;
938
 
939
		return true;
940
	}
941
 
942
	return *error_ppm + 10 < best_error_ppm;
943
}
944
 
2327 Serge 945
static bool
6084 serge 946
vlv_find_best_dpll(const intel_limit_t *limit,
947
		   struct intel_crtc_state *crtc_state,
948
		   int target, int refclk, intel_clock_t *match_clock,
949
		   intel_clock_t *best_clock)
3031 serge 950
{
6084 serge 951
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5354 serge 952
	struct drm_device *dev = crtc->base.dev;
4560 Serge 953
	intel_clock_t clock;
954
	unsigned int bestppm = 1000000;
955
	/* min update 19.2 MHz */
956
	int max_n = min(limit->n.max, refclk / 19200);
957
	bool found = false;
2327 Serge 958
 
4560 Serge 959
	target *= 5; /* fast clock */
3031 serge 960
 
4560 Serge 961
	memset(best_clock, 0, sizeof(*best_clock));
962
 
3031 serge 963
	/* based on hardware requirement, prefer smaller n to precision */
4560 Serge 964
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
965
		for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
966
			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
967
			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {
968
				clock.p = clock.p1 * clock.p2;
3031 serge 969
				/* based on hardware requirement, prefer bigger m1,m2 values */
4560 Serge 970
				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
6084 serge 971
					unsigned int ppm;
4560 Serge 972
 
973
					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
974
								     refclk * clock.m1);
975
 
6084 serge 976
					vlv_calc_dpll_params(refclk, &clock);
4560 Serge 977
 
978
					if (!intel_PLL_is_valid(dev, limit,
979
								&clock))
980
						continue;
981
 
6084 serge 982
					if (!vlv_PLL_is_optimal(dev, target,
983
								&clock,
984
								best_clock,
985
								bestppm, &ppm))
986
						continue;
4560 Serge 987
 
6084 serge 988
					*best_clock = clock;
989
					bestppm = ppm;
990
					found = true;
3031 serge 991
				}
992
			}
6084 serge 993
		}
994
	}
3031 serge 995
 
4560 Serge 996
	return found;
3031 serge 997
}
998
 
5060 serge 999
static bool
6084 serge 1000
chv_find_best_dpll(const intel_limit_t *limit,
1001
		   struct intel_crtc_state *crtc_state,
5060 serge 1002
		   int target, int refclk, intel_clock_t *match_clock,
1003
		   intel_clock_t *best_clock)
1004
{
6084 serge 1005
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5354 serge 1006
	struct drm_device *dev = crtc->base.dev;
6084 serge 1007
	unsigned int best_error_ppm;
5060 serge 1008
	intel_clock_t clock;
1009
	uint64_t m2;
1010
	int found = false;
1011
 
1012
	memset(best_clock, 0, sizeof(*best_clock));
6084 serge 1013
	best_error_ppm = 1000000;
5060 serge 1014
 
1015
	/*
1016
	 * Based on hardware doc, the n always set to 1, and m1 always
1017
	 * set to 2.  If requires to support 200Mhz refclk, we need to
1018
	 * revisit this because n may not 1 anymore.
1019
	 */
1020
	clock.n = 1, clock.m1 = 2;
1021
	target *= 5;	/* fast clock */
1022
 
1023
	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1024
		for (clock.p2 = limit->p2.p2_fast;
1025
				clock.p2 >= limit->p2.p2_slow;
1026
				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6084 serge 1027
			unsigned int error_ppm;
5060 serge 1028
 
1029
			clock.p = clock.p1 * clock.p2;
1030
 
1031
			m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1032
					clock.n) << 22, refclk * clock.m1);
1033
 
1034
			if (m2 > INT_MAX/clock.m1)
1035
				continue;
1036
 
1037
			clock.m2 = m2;
1038
 
6084 serge 1039
			chv_calc_dpll_params(refclk, &clock);
5060 serge 1040
 
1041
			if (!intel_PLL_is_valid(dev, limit, &clock))
1042
				continue;
1043
 
6084 serge 1044
			if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1045
						best_error_ppm, &error_ppm))
1046
				continue;
1047
 
1048
			*best_clock = clock;
1049
			best_error_ppm = error_ppm;
1050
			found = true;
5060 serge 1051
		}
1052
	}
1053
 
1054
	return found;
1055
}
1056
 
6084 serge 1057
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1058
			intel_clock_t *best_clock)
1059
{
1060
	int refclk = i9xx_get_refclk(crtc_state, 0);
1061
 
1062
	return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1063
				  target_clock, refclk, NULL, best_clock);
1064
}
1065
 
4560 Serge 1066
bool intel_crtc_active(struct drm_crtc *crtc)
1067
{
1068
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069
 
1070
	/* Be paranoid as we can arrive here with only partial
1071
	 * state retrieved from the hardware during setup.
1072
	 *
1073
	 * We can ditch the adjusted_mode.crtc_clock check as soon
1074
	 * as Haswell has gained clock readout/fastboot support.
1075
	 *
5060 serge 1076
	 * We can ditch the crtc->primary->fb check as soon as we can
4560 Serge 1077
	 * properly reconstruct framebuffers.
6084 serge 1078
	 *
1079
	 * FIXME: The intel_crtc->active here should be switched to
1080
	 * crtc->state->active once we have proper CRTC states wired up
1081
	 * for atomic.
4560 Serge 1082
	 */
6084 serge 1083
	return intel_crtc->active && crtc->primary->state->fb &&
1084
		intel_crtc->config->base.adjusted_mode.crtc_clock;
4560 Serge 1085
}
1086
 
3243 Serge 1087
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1088
					     enum pipe pipe)
1089
{
1090
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1091
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1092
 
6084 serge 1093
	return intel_crtc->config->cpu_transcoder;
3243 Serge 1094
}
1095
 
4560 Serge 1096
static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1097
{
1098
	struct drm_i915_private *dev_priv = dev->dev_private;
1099
	u32 reg = PIPEDSL(pipe);
1100
	u32 line1, line2;
1101
	u32 line_mask;
1102
 
1103
	if (IS_GEN2(dev))
1104
		line_mask = DSL_LINEMASK_GEN2;
1105
	else
1106
		line_mask = DSL_LINEMASK_GEN3;
1107
 
1108
	line1 = I915_READ(reg) & line_mask;
6084 serge 1109
	msleep(5);
4560 Serge 1110
	line2 = I915_READ(reg) & line_mask;
1111
 
1112
	return line1 == line2;
1113
}
1114
 
2327 Serge 1115
/*
1116
 * intel_wait_for_pipe_off - wait for pipe to turn off
5354 serge 1117
 * @crtc: crtc whose pipe to wait for
2327 Serge 1118
 *
1119
 * After disabling a pipe, we can't wait for vblank in the usual way,
1120
 * spinning on the vblank interrupt status bit, since we won't actually
1121
 * see an interrupt when the pipe is disabled.
1122
 *
1123
 * On Gen4 and above:
1124
 *   wait for the pipe register state bit to turn off
1125
 *
1126
 * Otherwise:
1127
 *   wait for the display line value to settle (it usually
1128
 *   ends up stopping at the start of the next frame).
1129
 *
1130
 */
5354 serge 1131
static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
2327 Serge 1132
{
5354 serge 1133
	struct drm_device *dev = crtc->base.dev;
2327 Serge 1134
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 1135
	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
5354 serge 1136
	enum pipe pipe = crtc->pipe;
2327 Serge 1137
 
1138
	if (INTEL_INFO(dev)->gen >= 4) {
3243 Serge 1139
		int reg = PIPECONF(cpu_transcoder);
2327 Serge 1140
 
1141
		/* Wait for the Pipe State to go off */
1142
		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1143
			     100))
3031 serge 1144
			WARN(1, "pipe_off wait timed out\n");
2327 Serge 1145
	} else {
1146
		/* Wait for the display line to settle */
4560 Serge 1147
		if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
3031 serge 1148
			WARN(1, "pipe_off wait timed out\n");
2327 Serge 1149
	}
1150
}
1151
 
1152
static const char *state_string(bool enabled)
1153
{
1154
	return enabled ? "on" : "off";
1155
}
1156
 
1157
/* Only for pre-ILK configs */
4104 Serge 1158
void assert_pll(struct drm_i915_private *dev_priv,
6084 serge 1159
		enum pipe pipe, bool state)
2327 Serge 1160
{
1161
	u32 val;
1162
	bool cur_state;
1163
 
6084 serge 1164
	val = I915_READ(DPLL(pipe));
2327 Serge 1165
	cur_state = !!(val & DPLL_VCO_ENABLE);
6084 serge 1166
	I915_STATE_WARN(cur_state != state,
2327 Serge 1167
	     "PLL state assertion failure (expected %s, current %s)\n",
1168
	     state_string(state), state_string(cur_state));
1169
}
1170
 
4560 Serge 1171
/* XXX: the dsi pll is shared between MIPI DSI ports */
1172
static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1173
{
1174
	u32 val;
1175
	bool cur_state;
1176
 
6084 serge 1177
	mutex_lock(&dev_priv->sb_lock);
4560 Serge 1178
	val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
6084 serge 1179
	mutex_unlock(&dev_priv->sb_lock);
4560 Serge 1180
 
1181
	cur_state = val & DSI_PLL_VCO_EN;
6084 serge 1182
	I915_STATE_WARN(cur_state != state,
4560 Serge 1183
	     "DSI PLL state assertion failure (expected %s, current %s)\n",
1184
	     state_string(state), state_string(cur_state));
1185
}
1186
#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1187
#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1188
 
4104 Serge 1189
struct intel_shared_dpll *
1190
intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1191
{
1192
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1193
 
6084 serge 1194
	if (crtc->config->shared_dpll < 0)
4104 Serge 1195
		return NULL;
1196
 
6084 serge 1197
	return &dev_priv->shared_dplls[crtc->config->shared_dpll];
4104 Serge 1198
}
1199
 
2327 Serge 1200
/* For ILK+ */
4104 Serge 1201
void assert_shared_dpll(struct drm_i915_private *dev_priv,
6084 serge 1202
			struct intel_shared_dpll *pll,
1203
			bool state)
2327 Serge 1204
{
1205
	bool cur_state;
4104 Serge 1206
	struct intel_dpll_hw_state hw_state;
2327 Serge 1207
 
3031 serge 1208
	if (WARN (!pll,
4104 Serge 1209
		  "asserting DPLL %s with no DPLL\n", state_string(state)))
3031 serge 1210
		return;
2342 Serge 1211
 
4104 Serge 1212
	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
6084 serge 1213
	I915_STATE_WARN(cur_state != state,
4104 Serge 1214
	     "%s assertion failure (expected %s, current %s)\n",
1215
	     pll->name, state_string(state), state_string(cur_state));
2327 Serge 1216
}
1217
 
1218
static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1219
			  enum pipe pipe, bool state)
1220
{
1221
	bool cur_state;
3243 Serge 1222
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223
								      pipe);
2327 Serge 1224
 
3480 Serge 1225
	if (HAS_DDI(dev_priv->dev)) {
1226
		/* DDI does not have a specific FDI_TX register */
6084 serge 1227
		u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3243 Serge 1228
		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
3031 serge 1229
	} else {
6084 serge 1230
		u32 val = I915_READ(FDI_TX_CTL(pipe));
1231
		cur_state = !!(val & FDI_TX_ENABLE);
3031 serge 1232
	}
6084 serge 1233
	I915_STATE_WARN(cur_state != state,
2327 Serge 1234
	     "FDI TX state assertion failure (expected %s, current %s)\n",
1235
	     state_string(state), state_string(cur_state));
1236
}
1237
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1238
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1239
 
1240
static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1241
			  enum pipe pipe, bool state)
1242
{
1243
	u32 val;
1244
	bool cur_state;
1245
 
6084 serge 1246
	val = I915_READ(FDI_RX_CTL(pipe));
2327 Serge 1247
	cur_state = !!(val & FDI_RX_ENABLE);
6084 serge 1248
	I915_STATE_WARN(cur_state != state,
2327 Serge 1249
	     "FDI RX state assertion failure (expected %s, current %s)\n",
1250
	     state_string(state), state_string(cur_state));
1251
}
1252
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1253
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1254
 
1255
static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1256
				      enum pipe pipe)
1257
{
1258
	u32 val;
1259
 
1260
	/* ILK FDI PLL is always enabled */
5060 serge 1261
	if (INTEL_INFO(dev_priv->dev)->gen == 5)
2327 Serge 1262
		return;
1263
 
3031 serge 1264
	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
3480 Serge 1265
	if (HAS_DDI(dev_priv->dev))
3031 serge 1266
		return;
1267
 
6084 serge 1268
	val = I915_READ(FDI_TX_CTL(pipe));
1269
	I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
2327 Serge 1270
}
1271
 
4104 Serge 1272
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1273
		       enum pipe pipe, bool state)
2327 Serge 1274
{
1275
	u32 val;
4104 Serge 1276
	bool cur_state;
2327 Serge 1277
 
6084 serge 1278
	val = I915_READ(FDI_RX_CTL(pipe));
4104 Serge 1279
	cur_state = !!(val & FDI_RX_PLL_ENABLE);
6084 serge 1280
	I915_STATE_WARN(cur_state != state,
4104 Serge 1281
	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
1282
	     state_string(state), state_string(cur_state));
2327 Serge 1283
}
1284
 
5354 serge 1285
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
6084 serge 1286
			   enum pipe pipe)
2327 Serge 1287
{
5354 serge 1288
	struct drm_device *dev = dev_priv->dev;
1289
	int pp_reg;
2327 Serge 1290
	u32 val;
1291
	enum pipe panel_pipe = PIPE_A;
1292
	bool locked = true;
1293
 
5354 serge 1294
	if (WARN_ON(HAS_DDI(dev)))
1295
		return;
1296
 
1297
	if (HAS_PCH_SPLIT(dev)) {
1298
		u32 port_sel;
1299
 
2327 Serge 1300
		pp_reg = PCH_PP_CONTROL;
5354 serge 1301
		port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1302
 
1303
		if (port_sel == PANEL_PORT_SELECT_LVDS &&
1304
		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1305
			panel_pipe = PIPE_B;
1306
		/* XXX: else fix for eDP */
1307
	} else if (IS_VALLEYVIEW(dev)) {
1308
		/* presumably write lock depends on pipe, not port select */
1309
		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1310
		panel_pipe = pipe;
2327 Serge 1311
	} else {
1312
		pp_reg = PP_CONTROL;
5354 serge 1313
		if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1314
			panel_pipe = PIPE_B;
2327 Serge 1315
	}
1316
 
1317
	val = I915_READ(pp_reg);
1318
	if (!(val & PANEL_POWER_ON) ||
5354 serge 1319
	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
2327 Serge 1320
		locked = false;
1321
 
6084 serge 1322
	I915_STATE_WARN(panel_pipe == pipe && locked,
2327 Serge 1323
	     "panel assertion failure, pipe %c regs locked\n",
1324
	     pipe_name(pipe));
1325
}
1326
 
4560 Serge 1327
static void assert_cursor(struct drm_i915_private *dev_priv,
1328
			  enum pipe pipe, bool state)
1329
{
1330
	struct drm_device *dev = dev_priv->dev;
1331
	bool cur_state;
1332
 
5060 serge 1333
	if (IS_845G(dev) || IS_I865G(dev))
6084 serge 1334
		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
4560 Serge 1335
	else
1336
		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1337
 
6084 serge 1338
	I915_STATE_WARN(cur_state != state,
4560 Serge 1339
	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1340
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1341
}
1342
#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1343
#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1344
 
2342 Serge 1345
void assert_pipe(struct drm_i915_private *dev_priv,
6084 serge 1346
		 enum pipe pipe, bool state)
2327 Serge 1347
{
1348
	bool cur_state;
3243 Serge 1349
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1350
								      pipe);
2327 Serge 1351
 
5354 serge 1352
	/* if we need the pipe quirk it must be always on */
1353
	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1354
	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
3031 serge 1355
		state = true;
1356
 
5354 serge 1357
	if (!intel_display_power_is_enabled(dev_priv,
4104 Serge 1358
				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
3480 Serge 1359
		cur_state = false;
1360
	} else {
6084 serge 1361
		u32 val = I915_READ(PIPECONF(cpu_transcoder));
1362
		cur_state = !!(val & PIPECONF_ENABLE);
3480 Serge 1363
	}
1364
 
6084 serge 1365
	I915_STATE_WARN(cur_state != state,
2327 Serge 1366
	     "pipe %c assertion failure (expected %s, current %s)\n",
1367
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1368
}
1369
 
3031 serge 1370
static void assert_plane(struct drm_i915_private *dev_priv,
1371
			 enum plane plane, bool state)
2327 Serge 1372
{
1373
	u32 val;
3031 serge 1374
	bool cur_state;
2327 Serge 1375
 
6084 serge 1376
	val = I915_READ(DSPCNTR(plane));
3031 serge 1377
	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
6084 serge 1378
	I915_STATE_WARN(cur_state != state,
3031 serge 1379
	     "plane %c assertion failure (expected %s, current %s)\n",
1380
	     plane_name(plane), state_string(state), state_string(cur_state));
2327 Serge 1381
}
1382
 
3031 serge 1383
#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1384
#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1385
 
2327 Serge 1386
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1387
				   enum pipe pipe)
1388
{
4104 Serge 1389
	struct drm_device *dev = dev_priv->dev;
6084 serge 1390
	int i;
2327 Serge 1391
 
4104 Serge 1392
	/* Primary planes are fixed to pipes on gen4+ */
1393
	if (INTEL_INFO(dev)->gen >= 4) {
6084 serge 1394
		u32 val = I915_READ(DSPCNTR(pipe));
1395
		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
3031 serge 1396
		     "plane %c assertion failure, should be disabled but not\n",
1397
		     plane_name(pipe));
2327 Serge 1398
		return;
3031 serge 1399
	}
2327 Serge 1400
 
1401
	/* Need to check both planes against the pipe */
5354 serge 1402
	for_each_pipe(dev_priv, i) {
6084 serge 1403
		u32 val = I915_READ(DSPCNTR(i));
1404
		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
2327 Serge 1405
			DISPPLANE_SEL_PIPE_SHIFT;
6084 serge 1406
		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
2327 Serge 1407
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
1408
		     plane_name(i), pipe_name(pipe));
1409
	}
1410
}
1411
 
3746 Serge 1412
static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1413
				    enum pipe pipe)
1414
{
4104 Serge 1415
	struct drm_device *dev = dev_priv->dev;
6084 serge 1416
	int sprite;
3746 Serge 1417
 
5354 serge 1418
	if (INTEL_INFO(dev)->gen >= 9) {
6084 serge 1419
		for_each_sprite(dev_priv, pipe, sprite) {
1420
			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1421
			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
5354 serge 1422
			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
1423
			     sprite, pipe_name(pipe));
1424
		}
1425
	} else if (IS_VALLEYVIEW(dev)) {
6084 serge 1426
		for_each_sprite(dev_priv, pipe, sprite) {
1427
			u32 val = I915_READ(SPCNTR(pipe, sprite));
1428
			I915_STATE_WARN(val & SP_ENABLE,
4104 Serge 1429
			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
5060 serge 1430
			     sprite_name(pipe, sprite), pipe_name(pipe));
4104 Serge 1431
		}
1432
	} else if (INTEL_INFO(dev)->gen >= 7) {
6084 serge 1433
		u32 val = I915_READ(SPRCTL(pipe));
1434
		I915_STATE_WARN(val & SPRITE_ENABLE,
4104 Serge 1435
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1436
		     plane_name(pipe), pipe_name(pipe));
1437
	} else if (INTEL_INFO(dev)->gen >= 5) {
6084 serge 1438
		u32 val = I915_READ(DVSCNTR(pipe));
1439
		I915_STATE_WARN(val & DVS_ENABLE,
4104 Serge 1440
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1441
		     plane_name(pipe), pipe_name(pipe));
3746 Serge 1442
	}
1443
}
1444
 
5354 serge 1445
static void assert_vblank_disabled(struct drm_crtc *crtc)
1446
{
6084 serge 1447
	if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
5354 serge 1448
		drm_crtc_vblank_put(crtc);
1449
}
1450
 
4560 Serge 1451
static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
2327 Serge 1452
{
1453
	u32 val;
1454
	bool enabled;
1455
 
6084 serge 1456
	I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
3031 serge 1457
 
2327 Serge 1458
	val = I915_READ(PCH_DREF_CONTROL);
1459
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1460
			    DREF_SUPERSPREAD_SOURCE_MASK));
6084 serge 1461
	I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
2327 Serge 1462
}
1463
 
4104 Serge 1464
static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
6084 serge 1465
					   enum pipe pipe)
2327 Serge 1466
{
1467
	u32 val;
1468
	bool enabled;
1469
 
6084 serge 1470
	val = I915_READ(PCH_TRANSCONF(pipe));
2327 Serge 1471
	enabled = !!(val & TRANS_ENABLE);
6084 serge 1472
	I915_STATE_WARN(enabled,
2327 Serge 1473
	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
1474
	     pipe_name(pipe));
1475
}
1476
 
1477
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1478
			    enum pipe pipe, u32 port_sel, u32 val)
1479
{
1480
	if ((val & DP_PORT_EN) == 0)
1481
		return false;
1482
 
1483
	if (HAS_PCH_CPT(dev_priv->dev)) {
1484
		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1485
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1486
		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487
			return false;
5060 serge 1488
	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
1489
		if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1490
			return false;
2327 Serge 1491
	} else {
1492
		if ((val & DP_PIPE_MASK) != (pipe << 30))
1493
			return false;
1494
	}
1495
	return true;
1496
}
1497
 
1498
static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1499
			      enum pipe pipe, u32 val)
1500
{
3746 Serge 1501
	if ((val & SDVO_ENABLE) == 0)
2327 Serge 1502
		return false;
1503
 
1504
	if (HAS_PCH_CPT(dev_priv->dev)) {
3746 Serge 1505
		if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
2327 Serge 1506
			return false;
5060 serge 1507
	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
1508
		if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1509
			return false;
2327 Serge 1510
	} else {
3746 Serge 1511
		if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
2327 Serge 1512
			return false;
1513
	}
1514
	return true;
1515
}
1516
 
1517
static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1518
			      enum pipe pipe, u32 val)
1519
{
1520
	if ((val & LVDS_PORT_EN) == 0)
1521
		return false;
1522
 
1523
	if (HAS_PCH_CPT(dev_priv->dev)) {
1524
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1525
			return false;
1526
	} else {
1527
		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1528
			return false;
1529
	}
1530
	return true;
1531
}
1532
 
1533
static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1534
			      enum pipe pipe, u32 val)
1535
{
1536
	if ((val & ADPA_DAC_ENABLE) == 0)
1537
		return false;
1538
	if (HAS_PCH_CPT(dev_priv->dev)) {
1539
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1540
			return false;
1541
	} else {
1542
		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1543
			return false;
1544
	}
1545
	return true;
1546
}
1547
 
1548
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1549
				   enum pipe pipe, int reg, u32 port_sel)
1550
{
1551
	u32 val = I915_READ(reg);
6084 serge 1552
	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
2327 Serge 1553
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1554
	     reg, pipe_name(pipe));
3031 serge 1555
 
6084 serge 1556
	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
3031 serge 1557
	     && (val & DP_PIPEB_SELECT),
1558
	     "IBX PCH dp port still using transcoder B\n");
2327 Serge 1559
}
1560
 
1561
static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1562
				     enum pipe pipe, int reg)
1563
{
1564
	u32 val = I915_READ(reg);
6084 serge 1565
	I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
3031 serge 1566
	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327 Serge 1567
	     reg, pipe_name(pipe));
3031 serge 1568
 
6084 serge 1569
	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
3031 serge 1570
	     && (val & SDVO_PIPE_B_SELECT),
1571
	     "IBX PCH hdmi port still using transcoder B\n");
2327 Serge 1572
}
1573
 
1574
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1575
				      enum pipe pipe)
1576
{
1577
	u32 val;
1578
 
1579
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1580
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1581
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1582
 
6084 serge 1583
	val = I915_READ(PCH_ADPA);
1584
	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327 Serge 1585
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1586
	     pipe_name(pipe));
1587
 
6084 serge 1588
	val = I915_READ(PCH_LVDS);
1589
	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327 Serge 1590
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
1591
	     pipe_name(pipe));
1592
 
3746 Serge 1593
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1594
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1595
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
2327 Serge 1596
}
1597
 
5354 serge 1598
static void vlv_enable_pll(struct intel_crtc *crtc,
6084 serge 1599
			   const struct intel_crtc_state *pipe_config)
4560 Serge 1600
{
4104 Serge 1601
	struct drm_device *dev = crtc->base.dev;
1602
	struct drm_i915_private *dev_priv = dev->dev_private;
1603
	int reg = DPLL(crtc->pipe);
5354 serge 1604
	u32 dpll = pipe_config->dpll_hw_state.dpll;
2327 Serge 1605
 
4104 Serge 1606
	assert_pipe_disabled(dev_priv, crtc->pipe);
1607
 
6084 serge 1608
	/* No really, not for ILK+ */
4104 Serge 1609
	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
2327 Serge 1610
 
6084 serge 1611
	/* PLL is protected by panel, make sure we can write it */
5354 serge 1612
	if (IS_MOBILE(dev_priv->dev))
4104 Serge 1613
		assert_panel_unlocked(dev_priv, crtc->pipe);
2327 Serge 1614
 
4104 Serge 1615
	I915_WRITE(reg, dpll);
1616
	POSTING_READ(reg);
1617
	udelay(150);
2327 Serge 1618
 
4104 Serge 1619
	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1620
		DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1621
 
5354 serge 1622
	I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
4104 Serge 1623
	POSTING_READ(DPLL_MD(crtc->pipe));
1624
 
1625
	/* We do this three times for luck */
1626
	I915_WRITE(reg, dpll);
1627
	POSTING_READ(reg);
1628
	udelay(150); /* wait for warmup */
1629
	I915_WRITE(reg, dpll);
1630
	POSTING_READ(reg);
1631
	udelay(150); /* wait for warmup */
1632
	I915_WRITE(reg, dpll);
1633
	POSTING_READ(reg);
1634
	udelay(150); /* wait for warmup */
1635
}
1636
 
5354 serge 1637
static void chv_enable_pll(struct intel_crtc *crtc,
6084 serge 1638
			   const struct intel_crtc_state *pipe_config)
5060 serge 1639
{
1640
	struct drm_device *dev = crtc->base.dev;
1641
	struct drm_i915_private *dev_priv = dev->dev_private;
1642
	int pipe = crtc->pipe;
1643
	enum dpio_channel port = vlv_pipe_to_channel(pipe);
1644
	u32 tmp;
1645
 
1646
	assert_pipe_disabled(dev_priv, crtc->pipe);
1647
 
1648
	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1649
 
6084 serge 1650
	mutex_lock(&dev_priv->sb_lock);
5060 serge 1651
 
1652
	/* Enable back the 10bit clock to display controller */
1653
	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1654
	tmp |= DPIO_DCLKP_EN;
1655
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1656
 
6084 serge 1657
	mutex_unlock(&dev_priv->sb_lock);
1658
 
5060 serge 1659
	/*
1660
	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1661
	 */
1662
	udelay(1);
1663
 
1664
	/* Enable PLL */
5354 serge 1665
	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
5060 serge 1666
 
1667
	/* Check PLL is locked */
1668
	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1669
		DRM_ERROR("PLL %d failed to lock\n", pipe);
1670
 
1671
	/* not sure when this should be written */
5354 serge 1672
	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
5060 serge 1673
	POSTING_READ(DPLL_MD(pipe));
1674
}
1675
 
5354 serge 1676
static int intel_num_dvo_pipes(struct drm_device *dev)
1677
{
1678
	struct intel_crtc *crtc;
1679
	int count = 0;
1680
 
1681
	for_each_intel_crtc(dev, crtc)
6084 serge 1682
		count += crtc->base.state->active &&
5354 serge 1683
			intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1684
 
1685
	return count;
1686
}
1687
 
4104 Serge 1688
static void i9xx_enable_pll(struct intel_crtc *crtc)
1689
{
1690
	struct drm_device *dev = crtc->base.dev;
1691
	struct drm_i915_private *dev_priv = dev->dev_private;
1692
	int reg = DPLL(crtc->pipe);
6084 serge 1693
	u32 dpll = crtc->config->dpll_hw_state.dpll;
4104 Serge 1694
 
1695
	assert_pipe_disabled(dev_priv, crtc->pipe);
1696
 
1697
	/* No really, not for ILK+ */
5060 serge 1698
	BUG_ON(INTEL_INFO(dev)->gen >= 5);
4104 Serge 1699
 
1700
	/* PLL is protected by panel, make sure we can write it */
1701
	if (IS_MOBILE(dev) && !IS_I830(dev))
1702
		assert_panel_unlocked(dev_priv, crtc->pipe);
1703
 
5354 serge 1704
	/* Enable DVO 2x clock on both PLLs if necessary */
1705
	if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1706
		/*
1707
		 * It appears to be important that we don't enable this
1708
		 * for the current pipe before otherwise configuring the
1709
		 * PLL. No idea how this should be handled if multiple
1710
		 * DVO outputs are enabled simultaneosly.
1711
		 */
1712
		dpll |= DPLL_DVO_2X_MODE;
1713
		I915_WRITE(DPLL(!crtc->pipe),
1714
			   I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1715
	}
4104 Serge 1716
 
6084 serge 1717
	/*
1718
	 * Apparently we need to have VGA mode enabled prior to changing
1719
	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1720
	 * dividers, even though the register value does change.
1721
	 */
1722
	I915_WRITE(reg, 0);
1723
 
1724
	I915_WRITE(reg, dpll);
1725
 
4104 Serge 1726
	/* Wait for the clocks to stabilize. */
1727
	POSTING_READ(reg);
1728
	udelay(150);
1729
 
1730
	if (INTEL_INFO(dev)->gen >= 4) {
1731
		I915_WRITE(DPLL_MD(crtc->pipe),
6084 serge 1732
			   crtc->config->dpll_hw_state.dpll_md);
4104 Serge 1733
	} else {
1734
		/* The pixel multiplier can only be updated once the
1735
		 * DPLL is enabled and the clocks are stable.
1736
		 *
1737
		 * So write it again.
1738
		 */
1739
		I915_WRITE(reg, dpll);
1740
	}
1741
 
6084 serge 1742
	/* We do this three times for luck */
4104 Serge 1743
	I915_WRITE(reg, dpll);
6084 serge 1744
	POSTING_READ(reg);
1745
	udelay(150); /* wait for warmup */
4104 Serge 1746
	I915_WRITE(reg, dpll);
6084 serge 1747
	POSTING_READ(reg);
1748
	udelay(150); /* wait for warmup */
4104 Serge 1749
	I915_WRITE(reg, dpll);
6084 serge 1750
	POSTING_READ(reg);
1751
	udelay(150); /* wait for warmup */
2327 Serge 1752
}
1753
 
1754
/**
4104 Serge 1755
 * i9xx_disable_pll - disable a PLL
2327 Serge 1756
 * @dev_priv: i915 private structure
1757
 * @pipe: pipe PLL to disable
1758
 *
1759
 * Disable the PLL for @pipe, making sure the pipe is off first.
1760
 *
1761
 * Note!  This is for pre-ILK only.
1762
 */
5354 serge 1763
static void i9xx_disable_pll(struct intel_crtc *crtc)
2327 Serge 1764
{
5354 serge 1765
	struct drm_device *dev = crtc->base.dev;
1766
	struct drm_i915_private *dev_priv = dev->dev_private;
1767
	enum pipe pipe = crtc->pipe;
1768
 
1769
	/* Disable DVO 2x clock on both PLLs if necessary */
1770
	if (IS_I830(dev) &&
1771
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
6084 serge 1772
	    !intel_num_dvo_pipes(dev)) {
5354 serge 1773
		I915_WRITE(DPLL(PIPE_B),
1774
			   I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1775
		I915_WRITE(DPLL(PIPE_A),
1776
			   I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1777
	}
1778
 
1779
	/* Don't disable pipe or pipe PLLs if needed */
1780
	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1781
	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2327 Serge 1782
		return;
1783
 
1784
	/* Make sure the pipe isn't still relying on us */
1785
	assert_pipe_disabled(dev_priv, pipe);
1786
 
6084 serge 1787
	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
4104 Serge 1788
	POSTING_READ(DPLL(pipe));
2327 Serge 1789
}
1790
 
4539 Serge 1791
static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1792
{
6084 serge 1793
	u32 val;
4539 Serge 1794
 
1795
	/* Make sure the pipe isn't still relying on us */
1796
	assert_pipe_disabled(dev_priv, pipe);
1797
 
4560 Serge 1798
	/*
1799
	 * Leave integrated clock source and reference clock enabled for pipe B.
1800
	 * The latter is needed for VGA hotplug / manual detection.
1801
	 */
6084 serge 1802
	val = DPLL_VGA_MODE_DIS;
4539 Serge 1803
	if (pipe == PIPE_B)
6084 serge 1804
		val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
4539 Serge 1805
	I915_WRITE(DPLL(pipe), val);
1806
	POSTING_READ(DPLL(pipe));
5060 serge 1807
 
4539 Serge 1808
}
1809
 
5060 serge 1810
static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811
{
1812
	enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813
	u32 val;
1814
 
1815
	/* Make sure the pipe isn't still relying on us */
1816
	assert_pipe_disabled(dev_priv, pipe);
1817
 
1818
	/* Set PLL en = 0 */
6084 serge 1819
	val = DPLL_SSC_REF_CLK_CHV |
1820
		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
5060 serge 1821
	if (pipe != PIPE_A)
1822
		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1823
	I915_WRITE(DPLL(pipe), val);
1824
	POSTING_READ(DPLL(pipe));
1825
 
6084 serge 1826
	mutex_lock(&dev_priv->sb_lock);
5060 serge 1827
 
1828
	/* Disable 10bit clock to display controller */
1829
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1830
	val &= ~DPIO_DCLKP_EN;
1831
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1832
 
6084 serge 1833
	mutex_unlock(&dev_priv->sb_lock);
5060 serge 1834
}
1835
 
4560 Serge 1836
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
6084 serge 1837
			 struct intel_digital_port *dport,
1838
			 unsigned int expected_mask)
3031 serge 1839
{
4104 Serge 1840
	u32 port_mask;
5060 serge 1841
	int dpll_reg;
3031 serge 1842
 
4560 Serge 1843
	switch (dport->port) {
1844
	case PORT_B:
4104 Serge 1845
		port_mask = DPLL_PORTB_READY_MASK;
5060 serge 1846
		dpll_reg = DPLL(0);
4560 Serge 1847
		break;
1848
	case PORT_C:
4104 Serge 1849
		port_mask = DPLL_PORTC_READY_MASK;
5060 serge 1850
		dpll_reg = DPLL(0);
6084 serge 1851
		expected_mask <<= 4;
4560 Serge 1852
		break;
5060 serge 1853
	case PORT_D:
1854
		port_mask = DPLL_PORTD_READY_MASK;
1855
		dpll_reg = DPIO_PHY_STATUS;
1856
		break;
4560 Serge 1857
	default:
1858
		BUG();
1859
	}
3243 Serge 1860
 
6084 serge 1861
	if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1862
		WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1863
		     port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
3031 serge 1864
}
1865
 
5060 serge 1866
static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1867
{
1868
	struct drm_device *dev = crtc->base.dev;
1869
	struct drm_i915_private *dev_priv = dev->dev_private;
1870
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1871
 
1872
	if (WARN_ON(pll == NULL))
1873
		return;
1874
 
5354 serge 1875
	WARN_ON(!pll->config.crtc_mask);
5060 serge 1876
	if (pll->active == 0) {
1877
		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1878
		WARN_ON(pll->on);
1879
		assert_shared_dpll_disabled(dev_priv, pll);
1880
 
1881
		pll->mode_set(dev_priv, pll);
1882
	}
1883
}
1884
 
2327 Serge 1885
/**
5060 serge 1886
 * intel_enable_shared_dpll - enable PCH PLL
2327 Serge 1887
 * @dev_priv: i915 private structure
1888
 * @pipe: pipe PLL to enable
1889
 *
1890
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1891
 * drives the transcoder clock.
1892
 */
5060 serge 1893
static void intel_enable_shared_dpll(struct intel_crtc *crtc)
2327 Serge 1894
{
5060 serge 1895
	struct drm_device *dev = crtc->base.dev;
1896
	struct drm_i915_private *dev_priv = dev->dev_private;
4104 Serge 1897
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327 Serge 1898
 
4104 Serge 1899
	if (WARN_ON(pll == NULL))
2342 Serge 1900
		return;
1901
 
5354 serge 1902
	if (WARN_ON(pll->config.crtc_mask == 0))
3031 serge 1903
		return;
2327 Serge 1904
 
5354 serge 1905
	DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
4104 Serge 1906
		      pll->name, pll->active, pll->on,
1907
		      crtc->base.base.id);
3031 serge 1908
 
4104 Serge 1909
	if (pll->active++) {
1910
		WARN_ON(!pll->on);
1911
		assert_shared_dpll_enabled(dev_priv, pll);
3031 serge 1912
		return;
1913
	}
4104 Serge 1914
	WARN_ON(pll->on);
3031 serge 1915
 
5060 serge 1916
	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1917
 
4104 Serge 1918
	DRM_DEBUG_KMS("enabling %s\n", pll->name);
1919
	pll->enable(dev_priv, pll);
3031 serge 1920
	pll->on = true;
2327 Serge 1921
}
1922
 
5354 serge 1923
static void intel_disable_shared_dpll(struct intel_crtc *crtc)
2327 Serge 1924
{
5060 serge 1925
	struct drm_device *dev = crtc->base.dev;
1926
	struct drm_i915_private *dev_priv = dev->dev_private;
4104 Serge 1927
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327 Serge 1928
 
1929
	/* PCH only available on ILK+ */
6084 serge 1930
	if (INTEL_INFO(dev)->gen < 5)
1931
		return;
2327 Serge 1932
 
6084 serge 1933
	if (pll == NULL)
3031 serge 1934
		return;
2327 Serge 1935
 
6084 serge 1936
	if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1937
		return;
1938
 
4104 Serge 1939
	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1940
		      pll->name, pll->active, pll->on,
1941
		      crtc->base.base.id);
2342 Serge 1942
 
3031 serge 1943
	if (WARN_ON(pll->active == 0)) {
4104 Serge 1944
		assert_shared_dpll_disabled(dev_priv, pll);
3031 serge 1945
		return;
1946
	}
2342 Serge 1947
 
4104 Serge 1948
	assert_shared_dpll_enabled(dev_priv, pll);
1949
	WARN_ON(!pll->on);
1950
	if (--pll->active)
2342 Serge 1951
		return;
1952
 
4104 Serge 1953
	DRM_DEBUG_KMS("disabling %s\n", pll->name);
1954
	pll->disable(dev_priv, pll);
3031 serge 1955
	pll->on = false;
5060 serge 1956
 
1957
	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2327 Serge 1958
}
1959
 
3243 Serge 1960
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
6084 serge 1961
					   enum pipe pipe)
2327 Serge 1962
{
3243 Serge 1963
	struct drm_device *dev = dev_priv->dev;
3031 serge 1964
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4104 Serge 1965
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243 Serge 1966
	uint32_t reg, val, pipeconf_val;
2327 Serge 1967
 
1968
	/* PCH only available on ILK+ */
5354 serge 1969
	BUG_ON(!HAS_PCH_SPLIT(dev));
2327 Serge 1970
 
1971
	/* Make sure PCH DPLL is enabled */
4104 Serge 1972
	assert_shared_dpll_enabled(dev_priv,
1973
				   intel_crtc_to_shared_dpll(intel_crtc));
2327 Serge 1974
 
1975
	/* FDI must be feeding us bits for PCH ports */
1976
	assert_fdi_tx_enabled(dev_priv, pipe);
1977
	assert_fdi_rx_enabled(dev_priv, pipe);
1978
 
3243 Serge 1979
	if (HAS_PCH_CPT(dev)) {
1980
		/* Workaround: Set the timing override bit before enabling the
1981
		 * pch transcoder. */
1982
		reg = TRANS_CHICKEN2(pipe);
1983
		val = I915_READ(reg);
1984
		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1985
		I915_WRITE(reg, val);
3031 serge 1986
	}
3243 Serge 1987
 
4104 Serge 1988
	reg = PCH_TRANSCONF(pipe);
2327 Serge 1989
	val = I915_READ(reg);
3031 serge 1990
	pipeconf_val = I915_READ(PIPECONF(pipe));
2327 Serge 1991
 
1992
	if (HAS_PCH_IBX(dev_priv->dev)) {
1993
		/*
6084 serge 1994
		 * Make the BPC in transcoder be consistent with
1995
		 * that in pipeconf reg. For HDMI we must use 8bpc
1996
		 * here for both 8bpc and 12bpc.
2327 Serge 1997
		 */
3480 Serge 1998
		val &= ~PIPECONF_BPC_MASK;
6084 serge 1999
		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2000
			val |= PIPECONF_8BPC;
2001
		else
2002
			val |= pipeconf_val & PIPECONF_BPC_MASK;
2327 Serge 2003
	}
3031 serge 2004
 
2005
	val &= ~TRANS_INTERLACE_MASK;
2006
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2007
		if (HAS_PCH_IBX(dev_priv->dev) &&
5354 serge 2008
		    intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
3031 serge 2009
			val |= TRANS_LEGACY_INTERLACED_ILK;
2010
		else
2011
			val |= TRANS_INTERLACED;
2012
	else
2013
		val |= TRANS_PROGRESSIVE;
2014
 
2327 Serge 2015
	I915_WRITE(reg, val | TRANS_ENABLE);
2016
	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4104 Serge 2017
		DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2327 Serge 2018
}
2019
 
3243 Serge 2020
static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2021
				      enum transcoder cpu_transcoder)
2022
{
2023
	u32 val, pipeconf_val;
2024
 
2025
	/* PCH only available on ILK+ */
5354 serge 2026
	BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
3243 Serge 2027
 
2028
	/* FDI must be feeding us bits for PCH ports */
3480 Serge 2029
	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
3243 Serge 2030
	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2031
 
2032
	/* Workaround: set timing override bit. */
6084 serge 2033
	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
3243 Serge 2034
	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6084 serge 2035
	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
3243 Serge 2036
 
2037
	val = TRANS_ENABLE;
2038
	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2039
 
2040
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2041
	    PIPECONF_INTERLACED_ILK)
2042
		val |= TRANS_INTERLACED;
2043
	else
2044
		val |= TRANS_PROGRESSIVE;
2045
 
4104 Serge 2046
	I915_WRITE(LPT_TRANSCONF, val);
2047
	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
3243 Serge 2048
		DRM_ERROR("Failed to enable PCH transcoder\n");
2049
}
2050
 
2051
static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
6084 serge 2052
					    enum pipe pipe)
2327 Serge 2053
{
3243 Serge 2054
	struct drm_device *dev = dev_priv->dev;
2055
	uint32_t reg, val;
2327 Serge 2056
 
2057
	/* FDI relies on the transcoder */
2058
	assert_fdi_tx_disabled(dev_priv, pipe);
2059
	assert_fdi_rx_disabled(dev_priv, pipe);
2060
 
2061
	/* Ports must be off as well */
2062
	assert_pch_ports_disabled(dev_priv, pipe);
2063
 
4104 Serge 2064
	reg = PCH_TRANSCONF(pipe);
2327 Serge 2065
	val = I915_READ(reg);
2066
	val &= ~TRANS_ENABLE;
2067
	I915_WRITE(reg, val);
2068
	/* wait for PCH transcoder off, transcoder state */
2069
	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4104 Serge 2070
		DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
3243 Serge 2071
 
2072
	if (!HAS_PCH_IBX(dev)) {
2073
		/* Workaround: Clear the timing override chicken bit again. */
2074
		reg = TRANS_CHICKEN2(pipe);
2075
		val = I915_READ(reg);
2076
		val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2077
		I915_WRITE(reg, val);
2078
	}
2327 Serge 2079
}
2080
 
3243 Serge 2081
static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2082
{
2083
	u32 val;
2084
 
4104 Serge 2085
	val = I915_READ(LPT_TRANSCONF);
3243 Serge 2086
	val &= ~TRANS_ENABLE;
4104 Serge 2087
	I915_WRITE(LPT_TRANSCONF, val);
3243 Serge 2088
	/* wait for PCH transcoder off, transcoder state */
4104 Serge 2089
	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
3243 Serge 2090
		DRM_ERROR("Failed to disable PCH transcoder\n");
2091
 
2092
	/* Workaround: clear timing override bit. */
6084 serge 2093
	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
3243 Serge 2094
	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
6084 serge 2095
	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
3243 Serge 2096
}
2097
 
2327 Serge 2098
/**
2099
 * intel_enable_pipe - enable a pipe, asserting requirements
5060 serge 2100
 * @crtc: crtc responsible for the pipe
2327 Serge 2101
 *
5060 serge 2102
 * Enable @crtc's pipe, making sure that various hardware specific requirements
2327 Serge 2103
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2104
 */
5060 serge 2105
static void intel_enable_pipe(struct intel_crtc *crtc)
2327 Serge 2106
{
5060 serge 2107
	struct drm_device *dev = crtc->base.dev;
2108
	struct drm_i915_private *dev_priv = dev->dev_private;
2109
	enum pipe pipe = crtc->pipe;
3243 Serge 2110
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2111
								      pipe);
3480 Serge 2112
	enum pipe pch_transcoder;
2327 Serge 2113
	int reg;
2114
	u32 val;
2115
 
6084 serge 2116
	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2117
 
4104 Serge 2118
	assert_planes_disabled(dev_priv, pipe);
4560 Serge 2119
	assert_cursor_disabled(dev_priv, pipe);
4104 Serge 2120
	assert_sprites_disabled(dev_priv, pipe);
2121
 
3480 Serge 2122
	if (HAS_PCH_LPT(dev_priv->dev))
3243 Serge 2123
		pch_transcoder = TRANSCODER_A;
2124
	else
2125
		pch_transcoder = pipe;
2126
 
2327 Serge 2127
	/*
2128
	 * A pipe without a PLL won't actually be able to drive bits from
2129
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2130
	 * need the check.
2131
	 */
6084 serge 2132
	if (HAS_GMCH_DISPLAY(dev_priv->dev))
5354 serge 2133
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4560 Serge 2134
			assert_dsi_pll_enabled(dev_priv);
2135
		else
6084 serge 2136
			assert_pll_enabled(dev_priv, pipe);
2327 Serge 2137
	else {
6084 serge 2138
		if (crtc->config->has_pch_encoder) {
2327 Serge 2139
			/* if driving the PCH, we need FDI enabled */
3243 Serge 2140
			assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
3480 Serge 2141
			assert_fdi_tx_pll_enabled(dev_priv,
2142
						  (enum pipe) cpu_transcoder);
2327 Serge 2143
		}
2144
		/* FIXME: assert CPU port conditions for SNB+ */
2145
	}
2146
 
3243 Serge 2147
	reg = PIPECONF(cpu_transcoder);
2327 Serge 2148
	val = I915_READ(reg);
5060 serge 2149
	if (val & PIPECONF_ENABLE) {
5354 serge 2150
		WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2151
			  (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2327 Serge 2152
		return;
5060 serge 2153
	}
2327 Serge 2154
 
2155
	I915_WRITE(reg, val | PIPECONF_ENABLE);
5060 serge 2156
	POSTING_READ(reg);
2327 Serge 2157
}
2158
 
2159
/**
2160
 * intel_disable_pipe - disable a pipe, asserting requirements
5354 serge 2161
 * @crtc: crtc whose pipes is to be disabled
2327 Serge 2162
 *
5354 serge 2163
 * Disable the pipe of @crtc, making sure that various hardware
2164
 * specific requirements are met, if applicable, e.g. plane
2165
 * disabled, panel fitter off, etc.
2327 Serge 2166
 *
2167
 * Will wait until the pipe has shut down before returning.
2168
 */
5354 serge 2169
static void intel_disable_pipe(struct intel_crtc *crtc)
2327 Serge 2170
{
5354 serge 2171
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6084 serge 2172
	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
5354 serge 2173
	enum pipe pipe = crtc->pipe;
2327 Serge 2174
	int reg;
2175
	u32 val;
2176
 
6084 serge 2177
	DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2178
 
2179
	/*
2327 Serge 2180
	 * Make sure planes won't keep trying to pump pixels to us,
2181
	 * or we might hang the display.
2182
	 */
2183
	assert_planes_disabled(dev_priv, pipe);
4560 Serge 2184
	assert_cursor_disabled(dev_priv, pipe);
3746 Serge 2185
	assert_sprites_disabled(dev_priv, pipe);
2327 Serge 2186
 
3243 Serge 2187
	reg = PIPECONF(cpu_transcoder);
2327 Serge 2188
	val = I915_READ(reg);
2189
	if ((val & PIPECONF_ENABLE) == 0)
2190
		return;
2191
 
5354 serge 2192
	/*
2193
	 * Double wide has implications for planes
2194
	 * so best keep it disabled when not needed.
2195
	 */
6084 serge 2196
	if (crtc->config->double_wide)
5354 serge 2197
		val &= ~PIPECONF_DOUBLE_WIDE;
2198
 
2199
	/* Don't disable pipe or pipe PLLs if needed */
2200
	if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201
	    !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202
		val &= ~PIPECONF_ENABLE;
2203
 
2204
	I915_WRITE(reg, val);
2205
	if ((val & PIPECONF_ENABLE) == 0)
2206
		intel_wait_for_pipe_off(crtc);
2327 Serge 2207
}
2208
 
6084 serge 2209
static bool need_vtd_wa(struct drm_device *dev)
2327 Serge 2210
{
6084 serge 2211
#ifdef CONFIG_INTEL_IOMMU
2212
	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2213
		return true;
2214
#endif
2215
	return false;
2327 Serge 2216
}
2217
 
6084 serge 2218
unsigned int
2219
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2220
		  uint64_t fb_format_modifier, unsigned int plane)
2327 Serge 2221
{
6084 serge 2222
	unsigned int tile_height;
2223
	uint32_t pixel_bytes;
2327 Serge 2224
 
6084 serge 2225
	switch (fb_format_modifier) {
2226
	case DRM_FORMAT_MOD_NONE:
2227
		tile_height = 1;
2228
		break;
2229
	case I915_FORMAT_MOD_X_TILED:
2230
		tile_height = IS_GEN2(dev) ? 16 : 8;
2231
		break;
2232
	case I915_FORMAT_MOD_Y_TILED:
2233
		tile_height = 32;
2234
		break;
2235
	case I915_FORMAT_MOD_Yf_TILED:
2236
		pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2237
		switch (pixel_bytes) {
2238
		default:
2239
		case 1:
2240
			tile_height = 64;
2241
			break;
2242
		case 2:
2243
		case 4:
2244
			tile_height = 32;
2245
			break;
2246
		case 8:
2247
			tile_height = 16;
2248
			break;
2249
		case 16:
2250
			WARN_ONCE(1,
2251
				  "128-bit pixels are not supported for display!");
2252
			tile_height = 16;
2253
			break;
2254
		}
2255
		break;
2256
	default:
2257
		MISSING_CASE(fb_format_modifier);
2258
		tile_height = 1;
2259
		break;
2260
	}
2327 Serge 2261
 
6084 serge 2262
	return tile_height;
2263
}
4560 Serge 2264
 
6084 serge 2265
unsigned int
2266
intel_fb_align_height(struct drm_device *dev, unsigned int height,
2267
		      uint32_t pixel_format, uint64_t fb_format_modifier)
2268
{
2269
	return ALIGN(height, intel_tile_height(dev, pixel_format,
2270
					       fb_format_modifier, 0));
2327 Serge 2271
}
2272
 
6084 serge 2273
static int
2274
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2275
			const struct drm_plane_state *plane_state)
2327 Serge 2276
{
6084 serge 2277
	struct intel_rotation_info *info = &view->rotation_info;
2278
	unsigned int tile_height, tile_pitch;
2327 Serge 2279
 
6084 serge 2280
	*view = i915_ggtt_view_normal;
5354 serge 2281
 
6084 serge 2282
	if (!plane_state)
2283
		return 0;
4560 Serge 2284
 
6084 serge 2285
	if (!intel_rotation_90_or_270(plane_state->rotation))
2286
		return 0;
4560 Serge 2287
 
6084 serge 2288
	*view = i915_ggtt_view_rotated;
2327 Serge 2289
 
6084 serge 2290
	info->height = fb->height;
2291
	info->pixel_format = fb->pixel_format;
2292
	info->pitch = fb->pitches[0];
2293
	info->uv_offset = fb->offsets[1];
2294
	info->fb_modifier = fb->modifier[0];
2295
 
2296
	tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2297
					fb->modifier[0], 0);
2298
	tile_pitch = PAGE_SIZE / tile_height;
2299
	info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2300
	info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2301
	info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2302
 
2303
	if (info->pixel_format == DRM_FORMAT_NV12) {
2304
		tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305
						fb->modifier[0], 1);
2306
		tile_pitch = PAGE_SIZE / tile_height;
2307
		info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308
		info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2309
						     tile_height);
2310
		info->size_uv = info->width_pages_uv * info->height_pages_uv *
2311
				PAGE_SIZE;
2312
	}
2313
 
2314
	return 0;
3746 Serge 2315
}
2316
 
6084 serge 2317
static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
5060 serge 2318
{
6084 serge 2319
	if (INTEL_INFO(dev_priv)->gen >= 9)
2320
		return 256 * 1024;
2321
	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2322
		 IS_VALLEYVIEW(dev_priv))
2323
		return 128 * 1024;
2324
	else if (INTEL_INFO(dev_priv)->gen >= 4)
2325
		return 4 * 1024;
2326
	else
2327
		return 0;
5060 serge 2328
}
2329
 
2335 Serge 2330
int
5354 serge 2331
intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332
			   struct drm_framebuffer *fb,
6084 serge 2333
			   const struct drm_plane_state *plane_state,
2334
			   struct intel_engine_cs *pipelined,
2335
			   struct drm_i915_gem_request **pipelined_request)
2335 Serge 2336
{
5354 serge 2337
	struct drm_device *dev = fb->dev;
2335 Serge 2338
	struct drm_i915_private *dev_priv = dev->dev_private;
5354 serge 2339
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6084 serge 2340
	struct i915_ggtt_view view;
2335 Serge 2341
	u32 alignment;
2342
	int ret;
2327 Serge 2343
 
5060 serge 2344
	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2345
 
6084 serge 2346
	switch (fb->modifier[0]) {
2347
	case DRM_FORMAT_MOD_NONE:
2348
		alignment = intel_linear_alignment(dev_priv);
2335 Serge 2349
		break;
6084 serge 2350
	case I915_FORMAT_MOD_X_TILED:
5354 serge 2351
		if (INTEL_INFO(dev)->gen >= 9)
2352
			alignment = 256 * 1024;
2353
		else {
6084 serge 2354
			/* pin() will align the object as required by fence */
2355
			alignment = 0;
5354 serge 2356
		}
2335 Serge 2357
		break;
6084 serge 2358
	case I915_FORMAT_MOD_Y_TILED:
2359
	case I915_FORMAT_MOD_Yf_TILED:
2360
		if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361
			  "Y tiling bo slipped through, driver bug!\n"))
2362
			return -EINVAL;
2363
		alignment = 1 * 1024 * 1024;
2364
		break;
2365
	default:
2366
		MISSING_CASE(fb->modifier[0]);
2335 Serge 2367
		return -EINVAL;
2368
	}
2327 Serge 2369
 
6084 serge 2370
	ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371
	if (ret)
2372
		return ret;
2373
 
3746 Serge 2374
	/* Note that the w/a also requires 64 PTE of padding following the
2375
	 * bo. We currently fill all unused PTE with the shadow page and so
2376
	 * we should always have valid PTE following the scanout preventing
2377
	 * the VT-d warning.
2378
	 */
2379
	if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380
		alignment = 256 * 1024;
2381
 
5097 serge 2382
	/*
2383
	 * Global gtt pte registers are special registers which actually forward
2384
	 * writes to a chunk of system memory. Which means that there is no risk
2385
	 * that the register values disappear as soon as we call
2386
	 * intel_runtime_pm_put(), so it is correct to wrap only the
2387
	 * pin/unpin/fence and not more.
2388
	 */
2389
	intel_runtime_pm_get(dev_priv);
2390
 
2335 Serge 2391
	dev_priv->mm.interruptible = false;
6084 serge 2392
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2393
						   pipelined_request, &view);
2335 Serge 2394
	if (ret)
2395
		goto err_interruptible;
2327 Serge 2396
 
2335 Serge 2397
	/* Install a fence for tiled scan-out. Pre-i965 always needs a
2398
	 * fence, whereas 965+ only requires a fence if using
2399
	 * framebuffer compression.  For simplicity, we always install
2400
	 * a fence as the cost is not that onerous.
2401
	 */
6084 serge 2402
	if (view.type == I915_GGTT_VIEW_NORMAL) {
2403
		ret = i915_gem_object_get_fence(obj);
2404
		if (ret == -EDEADLK) {
2405
			/*
2406
			 * -EDEADLK means there are no free fences
2407
			 * no pending flips.
2408
			 *
2409
			 * This is propagated to atomic, but it uses
2410
			 * -EDEADLK to force a locking recovery, so
2411
			 * change the returned error to -EBUSY.
2412
			 */
2413
			ret = -EBUSY;
2414
			goto err_unpin;
2415
		} else if (ret)
2416
			goto err_unpin;
2327 Serge 2417
 
6084 serge 2418
		i915_gem_object_pin_fence(obj);
2419
	}
3480 Serge 2420
 
2335 Serge 2421
	dev_priv->mm.interruptible = true;
5097 serge 2422
	intel_runtime_pm_put(dev_priv);
2335 Serge 2423
	return 0;
2327 Serge 2424
 
2335 Serge 2425
err_unpin:
6084 serge 2426
	i915_gem_object_unpin_from_display_plane(obj, &view);
2335 Serge 2427
err_interruptible:
2428
	dev_priv->mm.interruptible = true;
5097 serge 2429
	intel_runtime_pm_put(dev_priv);
2335 Serge 2430
	return ret;
2431
}
2327 Serge 2432
 
6084 serge 2433
static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434
			       const struct drm_plane_state *plane_state)
3031 serge 2435
{
6084 serge 2436
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437
	struct i915_ggtt_view view;
2438
	int ret;
2439
 
5060 serge 2440
	WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441
 
6084 serge 2442
	ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443
	WARN_ONCE(ret, "Couldn't get view from plane state!");
2444
 
2445
	if (view.type == I915_GGTT_VIEW_NORMAL)
2446
		i915_gem_object_unpin_fence(obj);
2447
 
2448
	i915_gem_object_unpin_from_display_plane(obj, &view);
3031 serge 2449
}
2450
 
2451
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2452
 * is assumed to be a power-of-two. */
6084 serge 2453
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2454
					     int *x, int *y,
3480 Serge 2455
					     unsigned int tiling_mode,
2456
					     unsigned int cpp,
6084 serge 2457
					     unsigned int pitch)
3031 serge 2458
{
3480 Serge 2459
	if (tiling_mode != I915_TILING_NONE) {
2460
		unsigned int tile_rows, tiles;
3031 serge 2461
 
6084 serge 2462
		tile_rows = *y / 8;
2463
		*y %= 8;
3031 serge 2464
 
3480 Serge 2465
		tiles = *x / (512/cpp);
2466
		*x %= 512/cpp;
2467
 
6084 serge 2468
		return tile_rows * pitch * 8 + tiles * 4096;
3480 Serge 2469
	} else {
6084 serge 2470
		unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
3480 Serge 2471
		unsigned int offset;
2472
 
2473
		offset = *y * pitch + *x * cpp;
6084 serge 2474
		*y = (offset & alignment) / pitch;
2475
		*x = ((offset & alignment) - *y * pitch) / cpp;
2476
		return offset & ~alignment;
3480 Serge 2477
	}
3031 serge 2478
}
2479
 
6084 serge 2480
static int i9xx_format_to_fourcc(int format)
2327 Serge 2481
{
5060 serge 2482
	switch (format) {
2483
	case DISPPLANE_8BPP:
2484
		return DRM_FORMAT_C8;
2485
	case DISPPLANE_BGRX555:
2486
		return DRM_FORMAT_XRGB1555;
2487
	case DISPPLANE_BGRX565:
2488
		return DRM_FORMAT_RGB565;
2489
	default:
2490
	case DISPPLANE_BGRX888:
2491
		return DRM_FORMAT_XRGB8888;
2492
	case DISPPLANE_RGBX888:
2493
		return DRM_FORMAT_XBGR8888;
2494
	case DISPPLANE_BGRX101010:
2495
		return DRM_FORMAT_XRGB2101010;
2496
	case DISPPLANE_RGBX101010:
2497
		return DRM_FORMAT_XBGR2101010;
2498
	}
2499
}
2500
 
6084 serge 2501
static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
5060 serge 2502
{
6084 serge 2503
	switch (format) {
2504
	case PLANE_CTL_FORMAT_RGB_565:
2505
		return DRM_FORMAT_RGB565;
2506
	default:
2507
	case PLANE_CTL_FORMAT_XRGB_8888:
2508
		if (rgb_order) {
2509
			if (alpha)
2510
				return DRM_FORMAT_ABGR8888;
2511
			else
2512
				return DRM_FORMAT_XBGR8888;
2513
		} else {
2514
			if (alpha)
2515
				return DRM_FORMAT_ARGB8888;
2516
			else
2517
				return DRM_FORMAT_XRGB8888;
2518
		}
2519
	case PLANE_CTL_FORMAT_XRGB_2101010:
2520
		if (rgb_order)
2521
			return DRM_FORMAT_XBGR2101010;
2522
		else
2523
			return DRM_FORMAT_XRGB2101010;
2524
	}
2525
}
2526
 
2527
static bool
2528
intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2529
			      struct intel_initial_plane_config *plane_config)
2530
{
5060 serge 2531
	struct drm_device *dev = crtc->base.dev;
6084 serge 2532
	struct drm_i915_private *dev_priv = to_i915(dev);
5060 serge 2533
	struct drm_i915_gem_object *obj = NULL;
2534
	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6084 serge 2535
	struct drm_framebuffer *fb = &plane_config->fb->base;
2536
	u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2537
	u32 size_aligned = round_up(plane_config->base + plane_config->size,
2538
				    PAGE_SIZE);
5060 serge 2539
 
6084 serge 2540
	size_aligned -= base_aligned;
2541
 
5060 serge 2542
	if (plane_config->size == 0)
2543
		return false;
2544
 
6084 serge 2545
	/* If the FB is too big, just don't use it since fbdev is not very
2546
	 * important and we should probably use that space with FBC or other
2547
	 * features. */
2548
	if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2549
		return false;
2550
 
2551
	obj = i915_gem_object_create_stolen_for_preallocated(dev,
2552
							     base_aligned,
2553
							     base_aligned,
2554
							     size_aligned);
5060 serge 2555
	if (!obj)
2556
		return false;
2557
 
6084 serge 2558
	obj->tiling_mode = plane_config->tiling;
2559
	if (obj->tiling_mode == I915_TILING_X)
2560
		obj->stride = fb->pitches[0];
5060 serge 2561
 
6084 serge 2562
	mode_cmd.pixel_format = fb->pixel_format;
2563
	mode_cmd.width = fb->width;
2564
	mode_cmd.height = fb->height;
2565
	mode_cmd.pitches[0] = fb->pitches[0];
2566
	mode_cmd.modifier[0] = fb->modifier[0];
2567
	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
5060 serge 2568
 
2569
	mutex_lock(&dev->struct_mutex);
6084 serge 2570
	if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
5060 serge 2571
				   &mode_cmd, obj)) {
2572
		DRM_DEBUG_KMS("intel fb init failed\n");
2573
		goto out_unref_obj;
2574
	}
2575
	mutex_unlock(&dev->struct_mutex);
2576
 
6084 serge 2577
	DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
5060 serge 2578
	return true;
2579
 
2580
out_unref_obj:
2581
	drm_gem_object_unreference(&obj->base);
2582
	mutex_unlock(&dev->struct_mutex);
2583
	return false;
2584
}
2585
 
6084 serge 2586
/* Update plane->state->fb to match plane->fb after driver-internal updates */
2587
static void
2588
update_state_fb(struct drm_plane *plane)
5060 serge 2589
{
6084 serge 2590
	if (plane->fb == plane->state->fb)
2591
		return;
2592
 
2593
	if (plane->state->fb)
2594
		drm_framebuffer_unreference(plane->state->fb);
2595
	plane->state->fb = plane->fb;
2596
	if (plane->state->fb)
2597
		drm_framebuffer_reference(plane->state->fb);
2598
}
2599
 
2600
static void
2601
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2602
			     struct intel_initial_plane_config *plane_config)
2603
{
5060 serge 2604
	struct drm_device *dev = intel_crtc->base.dev;
5354 serge 2605
	struct drm_i915_private *dev_priv = dev->dev_private;
5060 serge 2606
	struct drm_crtc *c;
2607
	struct intel_crtc *i;
2608
	struct drm_i915_gem_object *obj;
6084 serge 2609
	struct drm_plane *primary = intel_crtc->base.primary;
2610
	struct drm_plane_state *plane_state = primary->state;
2611
	struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2612
	struct intel_plane *intel_plane = to_intel_plane(primary);
2613
	struct drm_framebuffer *fb;
5060 serge 2614
 
6084 serge 2615
	if (!plane_config->fb)
5060 serge 2616
		return;
2617
 
6084 serge 2618
	if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2619
		fb = &plane_config->fb->base;
2620
		goto valid_fb;
2621
	}
5060 serge 2622
 
6084 serge 2623
	kfree(plane_config->fb);
5060 serge 2624
 
2625
	/*
2626
	 * Failed to alloc the obj, check to see if we should share
2627
	 * an fb with another CRTC instead
2628
	 */
2629
	for_each_crtc(dev, c) {
2630
		i = to_intel_crtc(c);
2631
 
2632
		if (c == &intel_crtc->base)
2633
			continue;
2634
 
2635
		if (!i->active)
2636
			continue;
2637
 
6084 serge 2638
		fb = c->primary->fb;
2639
		if (!fb)
5060 serge 2640
			continue;
2641
 
6084 serge 2642
		obj = intel_fb_obj(fb);
5060 serge 2643
		if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
6084 serge 2644
			drm_framebuffer_reference(fb);
2645
			goto valid_fb;
5060 serge 2646
		}
2647
	}
6084 serge 2648
 
2649
	/*
2650
	 * We've failed to reconstruct the BIOS FB.  Current display state
2651
	 * indicates that the primary plane is visible, but has a NULL FB,
2652
	 * which will lead to problems later if we don't fix it up.  The
2653
	 * simplest solution is to just disable the primary plane now and
2654
	 * pretend the BIOS never had it enabled.
2655
	 */
2656
	to_intel_plane_state(plane_state)->visible = false;
2657
	crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2658
	intel_pre_disable_primary(&intel_crtc->base);
2659
	intel_plane->disable_plane(primary, &intel_crtc->base);
2660
 
2661
	return;
2662
 
2663
valid_fb:
2664
	plane_state->src_x = 0;
2665
	plane_state->src_y = 0;
2666
	plane_state->src_w = fb->width << 16;
2667
	plane_state->src_h = fb->height << 16;
2668
 
2669
	plane_state->crtc_x = 0;
2670
	plane_state->crtc_y = 0;
2671
	plane_state->crtc_w = fb->width;
2672
	plane_state->crtc_h = fb->height;
2673
 
2674
	obj = intel_fb_obj(fb);
2675
	if (obj->tiling_mode != I915_TILING_NONE)
2676
		dev_priv->preserve_bios_swizzle = true;
2677
 
2678
	drm_framebuffer_reference(fb);
2679
	primary->fb = primary->state->fb = fb;
2680
	primary->crtc = primary->state->crtc = &intel_crtc->base;
2681
	intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2682
	obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
5060 serge 2683
}
2684
 
2685
static void i9xx_update_primary_plane(struct drm_crtc *crtc,
6084 serge 2686
				      struct drm_framebuffer *fb,
2687
				      int x, int y)
5060 serge 2688
{
6084 serge 2689
	struct drm_device *dev = crtc->dev;
2690
	struct drm_i915_private *dev_priv = dev->dev_private;
2691
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692
	struct drm_plane *primary = crtc->primary;
2693
	bool visible = to_intel_plane_state(primary->state)->visible;
5354 serge 2694
	struct drm_i915_gem_object *obj;
6084 serge 2695
	int plane = intel_crtc->plane;
3031 serge 2696
	unsigned long linear_offset;
6084 serge 2697
	u32 dspcntr;
5354 serge 2698
	u32 reg = DSPCNTR(plane);
2699
	int pixel_size;
2327 Serge 2700
 
6084 serge 2701
	if (!visible || !fb) {
5354 serge 2702
		I915_WRITE(reg, 0);
2703
		if (INTEL_INFO(dev)->gen >= 4)
2704
			I915_WRITE(DSPSURF(plane), 0);
2705
		else
2706
			I915_WRITE(DSPADDR(plane), 0);
2707
		POSTING_READ(reg);
2708
		return;
2709
	}
2710
 
2711
	obj = intel_fb_obj(fb);
2712
	if (WARN_ON(obj == NULL))
2713
		return;
2714
 
2715
	pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2716
 
2717
	dspcntr = DISPPLANE_GAMMA_ENABLE;
2718
 
2719
	dspcntr |= DISPLAY_PLANE_ENABLE;
2720
 
2721
	if (INTEL_INFO(dev)->gen < 4) {
2722
		if (intel_crtc->pipe == PIPE_B)
2723
			dspcntr |= DISPPLANE_SEL_PIPE_B;
2724
 
2725
		/* pipesrc and dspsize control the size that is scaled from,
2726
		 * which should always be the user's requested size.
2727
		 */
2728
		I915_WRITE(DSPSIZE(plane),
6084 serge 2729
			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
2730
			   (intel_crtc->config->pipe_src_w - 1));
5354 serge 2731
		I915_WRITE(DSPPOS(plane), 0);
2732
	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2733
		I915_WRITE(PRIMSIZE(plane),
6084 serge 2734
			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
2735
			   (intel_crtc->config->pipe_src_w - 1));
5354 serge 2736
		I915_WRITE(PRIMPOS(plane), 0);
2737
		I915_WRITE(PRIMCNSTALPHA(plane), 0);
2738
	}
2739
 
3243 Serge 2740
	switch (fb->pixel_format) {
2741
	case DRM_FORMAT_C8:
6084 serge 2742
		dspcntr |= DISPPLANE_8BPP;
2743
		break;
3243 Serge 2744
	case DRM_FORMAT_XRGB1555:
2745
		dspcntr |= DISPPLANE_BGRX555;
2746
		break;
2747
	case DRM_FORMAT_RGB565:
2748
		dspcntr |= DISPPLANE_BGRX565;
2749
		break;
2750
	case DRM_FORMAT_XRGB8888:
2751
		dspcntr |= DISPPLANE_BGRX888;
2752
		break;
2753
	case DRM_FORMAT_XBGR8888:
2754
		dspcntr |= DISPPLANE_RGBX888;
2755
		break;
2756
	case DRM_FORMAT_XRGB2101010:
2757
		dspcntr |= DISPPLANE_BGRX101010;
6084 serge 2758
		break;
3243 Serge 2759
	case DRM_FORMAT_XBGR2101010:
2760
		dspcntr |= DISPPLANE_RGBX101010;
6084 serge 2761
		break;
2762
	default:
3746 Serge 2763
		BUG();
6084 serge 2764
	}
3243 Serge 2765
 
5354 serge 2766
	if (INTEL_INFO(dev)->gen >= 4 &&
2767
	    obj->tiling_mode != I915_TILING_NONE)
6084 serge 2768
		dspcntr |= DISPPLANE_TILED;
2327 Serge 2769
 
4104 Serge 2770
	if (IS_G4X(dev))
2771
		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2772
 
5354 serge 2773
	linear_offset = y * fb->pitches[0] + x * pixel_size;
2327 Serge 2774
 
3031 serge 2775
	if (INTEL_INFO(dev)->gen >= 4) {
2776
		intel_crtc->dspaddr_offset =
6084 serge 2777
			intel_gen4_compute_page_offset(dev_priv,
2778
						       &x, &y, obj->tiling_mode,
5354 serge 2779
						       pixel_size,
6084 serge 2780
						       fb->pitches[0]);
3031 serge 2781
		linear_offset -= intel_crtc->dspaddr_offset;
2782
	} else {
2783
		intel_crtc->dspaddr_offset = linear_offset;
2784
	}
2785
 
6084 serge 2786
	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
5354 serge 2787
		dspcntr |= DISPPLANE_ROTATE_180;
2788
 
6084 serge 2789
		x += (intel_crtc->config->pipe_src_w - 1);
2790
		y += (intel_crtc->config->pipe_src_h - 1);
5354 serge 2791
 
2792
		/* Finding the last pixel of the last line of the display
2793
		data and adding to linear_offset*/
2794
		linear_offset +=
6084 serge 2795
			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2796
			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
5354 serge 2797
	}
2798
 
6084 serge 2799
	intel_crtc->adjusted_x = x;
2800
	intel_crtc->adjusted_y = y;
2801
 
5354 serge 2802
	I915_WRITE(reg, dspcntr);
2803
 
2342 Serge 2804
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
6084 serge 2805
	if (INTEL_INFO(dev)->gen >= 4) {
4560 Serge 2806
		I915_WRITE(DSPSURF(plane),
6084 serge 2807
			   i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2808
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3031 serge 2809
		I915_WRITE(DSPLINOFF(plane), linear_offset);
6084 serge 2810
	} else
4104 Serge 2811
		I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
6084 serge 2812
	POSTING_READ(reg);
2327 Serge 2813
}
2814
 
5060 serge 2815
static void ironlake_update_primary_plane(struct drm_crtc *crtc,
6084 serge 2816
					  struct drm_framebuffer *fb,
2817
					  int x, int y)
2327 Serge 2818
{
6084 serge 2819
	struct drm_device *dev = crtc->dev;
2820
	struct drm_i915_private *dev_priv = dev->dev_private;
2821
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2822
	struct drm_plane *primary = crtc->primary;
2823
	bool visible = to_intel_plane_state(primary->state)->visible;
5354 serge 2824
	struct drm_i915_gem_object *obj;
6084 serge 2825
	int plane = intel_crtc->plane;
3031 serge 2826
	unsigned long linear_offset;
6084 serge 2827
	u32 dspcntr;
5354 serge 2828
	u32 reg = DSPCNTR(plane);
2829
	int pixel_size;
2327 Serge 2830
 
6084 serge 2831
	if (!visible || !fb) {
5354 serge 2832
		I915_WRITE(reg, 0);
2833
		I915_WRITE(DSPSURF(plane), 0);
2834
		POSTING_READ(reg);
2835
		return;
2836
	}
2837
 
2838
	obj = intel_fb_obj(fb);
2839
	if (WARN_ON(obj == NULL))
2840
		return;
2841
 
2842
	pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2843
 
2844
	dspcntr = DISPPLANE_GAMMA_ENABLE;
2845
 
2846
	dspcntr |= DISPLAY_PLANE_ENABLE;
2847
 
2848
	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2849
		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2850
 
3243 Serge 2851
	switch (fb->pixel_format) {
2852
	case DRM_FORMAT_C8:
6084 serge 2853
		dspcntr |= DISPPLANE_8BPP;
2854
		break;
3243 Serge 2855
	case DRM_FORMAT_RGB565:
2856
		dspcntr |= DISPPLANE_BGRX565;
6084 serge 2857
		break;
3243 Serge 2858
	case DRM_FORMAT_XRGB8888:
2859
		dspcntr |= DISPPLANE_BGRX888;
2860
		break;
2861
	case DRM_FORMAT_XBGR8888:
2862
		dspcntr |= DISPPLANE_RGBX888;
2863
		break;
2864
	case DRM_FORMAT_XRGB2101010:
2865
		dspcntr |= DISPPLANE_BGRX101010;
2866
		break;
2867
	case DRM_FORMAT_XBGR2101010:
2868
		dspcntr |= DISPPLANE_RGBX101010;
6084 serge 2869
		break;
2870
	default:
3746 Serge 2871
		BUG();
6084 serge 2872
	}
2327 Serge 2873
 
3480 Serge 2874
	if (obj->tiling_mode != I915_TILING_NONE)
2875
		dspcntr |= DISPPLANE_TILED;
2327 Serge 2876
 
5354 serge 2877
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
6084 serge 2878
		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2327 Serge 2879
 
5354 serge 2880
	linear_offset = y * fb->pitches[0] + x * pixel_size;
3031 serge 2881
	intel_crtc->dspaddr_offset =
6084 serge 2882
		intel_gen4_compute_page_offset(dev_priv,
2883
					       &x, &y, obj->tiling_mode,
5354 serge 2884
					       pixel_size,
6084 serge 2885
					       fb->pitches[0]);
3031 serge 2886
	linear_offset -= intel_crtc->dspaddr_offset;
6084 serge 2887
	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
5354 serge 2888
		dspcntr |= DISPPLANE_ROTATE_180;
2327 Serge 2889
 
5354 serge 2890
		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6084 serge 2891
			x += (intel_crtc->config->pipe_src_w - 1);
2892
			y += (intel_crtc->config->pipe_src_h - 1);
5354 serge 2893
 
2894
			/* Finding the last pixel of the last line of the display
2895
			data and adding to linear_offset*/
2896
			linear_offset +=
6084 serge 2897
				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2898
				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
5354 serge 2899
		}
2900
	}
2901
 
6084 serge 2902
	intel_crtc->adjusted_x = x;
2903
	intel_crtc->adjusted_y = y;
2904
 
5354 serge 2905
	I915_WRITE(reg, dspcntr);
2906
 
2342 Serge 2907
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
4560 Serge 2908
	I915_WRITE(DSPSURF(plane),
6084 serge 2909
		   i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
4560 Serge 2910
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3243 Serge 2911
		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2912
	} else {
6084 serge 2913
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2914
		I915_WRITE(DSPLINOFF(plane), linear_offset);
3243 Serge 2915
	}
2330 Serge 2916
	POSTING_READ(reg);
2327 Serge 2917
}
2918
 
6084 serge 2919
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2920
			      uint32_t pixel_format)
2921
{
2922
	u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2923
 
2924
	/*
2925
	 * The stride is either expressed as a multiple of 64 bytes
2926
	 * chunks for linear buffers or in number of tiles for tiled
2927
	 * buffers.
2928
	 */
2929
	switch (fb_modifier) {
2930
	case DRM_FORMAT_MOD_NONE:
2931
		return 64;
2932
	case I915_FORMAT_MOD_X_TILED:
2933
		if (INTEL_INFO(dev)->gen == 2)
2934
			return 128;
2935
		return 512;
2936
	case I915_FORMAT_MOD_Y_TILED:
2937
		/* No need to check for old gens and Y tiling since this is
2938
		 * about the display engine and those will be blocked before
2939
		 * we get here.
2940
		 */
2941
		return 128;
2942
	case I915_FORMAT_MOD_Yf_TILED:
2943
		if (bits_per_pixel == 8)
2944
			return 64;
2945
		else
2946
			return 128;
2947
	default:
2948
		MISSING_CASE(fb_modifier);
2949
		return 64;
2950
	}
2951
}
2952
 
2953
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2954
				     struct drm_i915_gem_object *obj,
2955
				     unsigned int plane)
2956
{
2957
	const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2958
	struct i915_vma *vma;
2959
	unsigned char *offset;
2960
 
2961
	if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2962
		view = &i915_ggtt_view_rotated;
2963
 
2964
	vma = i915_gem_obj_to_ggtt_view(obj, view);
2965
	if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2966
		view->type))
2967
		return -1;
2968
 
2969
	offset = (unsigned char *)vma->node.start;
2970
 
2971
	if (plane == 1) {
2972
		offset += vma->ggtt_view.rotation_info.uv_start_page *
2973
			  PAGE_SIZE;
2974
	}
2975
 
2976
	return (unsigned long)offset;
2977
}
2978
 
2979
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2980
{
2981
	struct drm_device *dev = intel_crtc->base.dev;
2982
	struct drm_i915_private *dev_priv = dev->dev_private;
2983
 
2984
	I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2985
	I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2986
	I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2987
}
2988
 
2989
/*
2990
 * This function detaches (aka. unbinds) unused scalers in hardware
2991
 */
2992
static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2993
{
2994
	struct intel_crtc_scaler_state *scaler_state;
2995
	int i;
2996
 
2997
	scaler_state = &intel_crtc->config->scaler_state;
2998
 
2999
	/* loop through and disable scalers that aren't in use */
3000
	for (i = 0; i < intel_crtc->num_scalers; i++) {
3001
		if (!scaler_state->scalers[i].in_use)
3002
			skl_detach_scaler(intel_crtc, i);
3003
	}
3004
}
3005
 
3006
u32 skl_plane_ctl_format(uint32_t pixel_format)
3007
{
3008
	switch (pixel_format) {
3009
	case DRM_FORMAT_C8:
3010
		return PLANE_CTL_FORMAT_INDEXED;
3011
	case DRM_FORMAT_RGB565:
3012
		return PLANE_CTL_FORMAT_RGB_565;
3013
	case DRM_FORMAT_XBGR8888:
3014
		return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3015
	case DRM_FORMAT_XRGB8888:
3016
		return PLANE_CTL_FORMAT_XRGB_8888;
3017
	/*
3018
	 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3019
	 * to be already pre-multiplied. We need to add a knob (or a different
3020
	 * DRM_FORMAT) for user-space to configure that.
3021
	 */
3022
	case DRM_FORMAT_ABGR8888:
3023
		return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3024
			PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3025
	case DRM_FORMAT_ARGB8888:
3026
		return PLANE_CTL_FORMAT_XRGB_8888 |
3027
			PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3028
	case DRM_FORMAT_XRGB2101010:
3029
		return PLANE_CTL_FORMAT_XRGB_2101010;
3030
	case DRM_FORMAT_XBGR2101010:
3031
		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3032
	case DRM_FORMAT_YUYV:
3033
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3034
	case DRM_FORMAT_YVYU:
3035
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3036
	case DRM_FORMAT_UYVY:
3037
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3038
	case DRM_FORMAT_VYUY:
3039
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3040
	default:
3041
		MISSING_CASE(pixel_format);
3042
	}
3043
 
3044
	return 0;
3045
}
3046
 
3047
u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3048
{
3049
	switch (fb_modifier) {
3050
	case DRM_FORMAT_MOD_NONE:
3051
		break;
3052
	case I915_FORMAT_MOD_X_TILED:
3053
		return PLANE_CTL_TILED_X;
3054
	case I915_FORMAT_MOD_Y_TILED:
3055
		return PLANE_CTL_TILED_Y;
3056
	case I915_FORMAT_MOD_Yf_TILED:
3057
		return PLANE_CTL_TILED_YF;
3058
	default:
3059
		MISSING_CASE(fb_modifier);
3060
	}
3061
 
3062
	return 0;
3063
}
3064
 
3065
u32 skl_plane_ctl_rotation(unsigned int rotation)
3066
{
3067
	switch (rotation) {
3068
	case BIT(DRM_ROTATE_0):
3069
		break;
3070
	/*
3071
	 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3072
	 * while i915 HW rotation is clockwise, thats why this swapping.
3073
	 */
3074
	case BIT(DRM_ROTATE_90):
3075
		return PLANE_CTL_ROTATE_270;
3076
	case BIT(DRM_ROTATE_180):
3077
		return PLANE_CTL_ROTATE_180;
3078
	case BIT(DRM_ROTATE_270):
3079
		return PLANE_CTL_ROTATE_90;
3080
	default:
3081
		MISSING_CASE(rotation);
3082
	}
3083
 
3084
	return 0;
3085
}
3086
 
5354 serge 3087
static void skylake_update_primary_plane(struct drm_crtc *crtc,
3088
					 struct drm_framebuffer *fb,
3089
					 int x, int y)
3090
{
3091
	struct drm_device *dev = crtc->dev;
3092
	struct drm_i915_private *dev_priv = dev->dev_private;
3093
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084 serge 3094
	struct drm_plane *plane = crtc->primary;
3095
	bool visible = to_intel_plane_state(plane->state)->visible;
5354 serge 3096
	struct drm_i915_gem_object *obj;
3097
	int pipe = intel_crtc->pipe;
6084 serge 3098
	u32 plane_ctl, stride_div, stride;
3099
	u32 tile_height, plane_offset, plane_size;
3100
	unsigned int rotation;
3101
	int x_offset, y_offset;
3102
	unsigned long surf_addr;
3103
	struct intel_crtc_state *crtc_state = intel_crtc->config;
3104
	struct intel_plane_state *plane_state;
3105
	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3106
	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3107
	int scaler_id = -1;
5354 serge 3108
 
6084 serge 3109
	plane_state = to_intel_plane_state(plane->state);
3110
 
3111
	if (!visible || !fb) {
5354 serge 3112
		I915_WRITE(PLANE_CTL(pipe, 0), 0);
3113
		I915_WRITE(PLANE_SURF(pipe, 0), 0);
3114
		POSTING_READ(PLANE_CTL(pipe, 0));
3115
		return;
3116
	}
3117
 
3118
	plane_ctl = PLANE_CTL_ENABLE |
3119
		    PLANE_CTL_PIPE_GAMMA_ENABLE |
3120
		    PLANE_CTL_PIPE_CSC_ENABLE;
3121
 
6084 serge 3122
	plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3123
	plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3124
	plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
5354 serge 3125
 
6084 serge 3126
	rotation = plane->state->rotation;
3127
	plane_ctl |= skl_plane_ctl_rotation(rotation);
5354 serge 3128
 
6084 serge 3129
	obj = intel_fb_obj(fb);
3130
	stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3131
					       fb->pixel_format);
3132
	surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3133
 
3134
	WARN_ON(drm_rect_width(&plane_state->src) == 0);
3135
 
3136
	scaler_id = plane_state->scaler_id;
3137
	src_x = plane_state->src.x1 >> 16;
3138
	src_y = plane_state->src.y1 >> 16;
3139
	src_w = drm_rect_width(&plane_state->src) >> 16;
3140
	src_h = drm_rect_height(&plane_state->src) >> 16;
3141
	dst_x = plane_state->dst.x1;
3142
	dst_y = plane_state->dst.y1;
3143
	dst_w = drm_rect_width(&plane_state->dst);
3144
	dst_h = drm_rect_height(&plane_state->dst);
3145
 
3146
	WARN_ON(x != src_x || y != src_y);
3147
 
3148
	if (intel_rotation_90_or_270(rotation)) {
3149
		/* stride = Surface height in tiles */
3150
		tile_height = intel_tile_height(dev, fb->pixel_format,
3151
						fb->modifier[0], 0);
3152
		stride = DIV_ROUND_UP(fb->height, tile_height);
3153
		x_offset = stride * tile_height - y - src_h;
3154
		y_offset = x;
3155
		plane_size = (src_w - 1) << 16 | (src_h - 1);
3156
	} else {
3157
		stride = fb->pitches[0] / stride_div;
3158
		x_offset = x;
3159
		y_offset = y;
3160
		plane_size = (src_h - 1) << 16 | (src_w - 1);
5354 serge 3161
	}
6084 serge 3162
	plane_offset = y_offset << 16 | x_offset;
5354 serge 3163
 
6084 serge 3164
	intel_crtc->adjusted_x = x_offset;
3165
	intel_crtc->adjusted_y = y_offset;
5354 serge 3166
 
3167
	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
6084 serge 3168
	I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3169
	I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3170
	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
5354 serge 3171
 
6084 serge 3172
	if (scaler_id >= 0) {
3173
		uint32_t ps_ctrl = 0;
5354 serge 3174
 
6084 serge 3175
		WARN_ON(!dst_w || !dst_h);
3176
		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3177
			crtc_state->scaler_state.scalers[scaler_id].mode;
3178
		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3179
		I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3180
		I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3181
		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3182
		I915_WRITE(PLANE_POS(pipe, 0), 0);
3183
	} else {
3184
		I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3185
	}
5354 serge 3186
 
6084 serge 3187
	I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3188
 
5354 serge 3189
	POSTING_READ(PLANE_SURF(pipe, 0));
3190
}
3191
 
2327 Serge 3192
/* Assume fb object is pinned & idle & fenced and just update base pointers */
3193
static int
3194
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3195
			   int x, int y, enum mode_set_atomic state)
3196
{
3197
	struct drm_device *dev = crtc->dev;
3198
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 3199
 
6084 serge 3200
	if (dev_priv->fbc.disable_fbc)
3201
		dev_priv->fbc.disable_fbc(dev_priv);
3031 serge 3202
 
5060 serge 3203
	dev_priv->display.update_primary_plane(crtc, fb, x, y);
3204
 
3205
	return 0;
3031 serge 3206
}
3207
 
5354 serge 3208
static void intel_complete_page_flips(struct drm_device *dev)
4104 Serge 3209
{
3210
	struct drm_crtc *crtc;
3211
 
5060 serge 3212
	for_each_crtc(dev, crtc) {
4104 Serge 3213
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214
		enum plane plane = intel_crtc->plane;
3215
 
3216
		intel_prepare_page_flip(dev, plane);
3217
		intel_finish_page_flip_plane(dev, plane);
3218
	}
5354 serge 3219
}
4104 Serge 3220
 
5354 serge 3221
static void intel_update_primary_planes(struct drm_device *dev)
3222
{
3223
	struct drm_crtc *crtc;
3224
 
5060 serge 3225
	for_each_crtc(dev, crtc) {
6084 serge 3226
		struct intel_plane *plane = to_intel_plane(crtc->primary);
3227
		struct intel_plane_state *plane_state;
4104 Serge 3228
 
6084 serge 3229
		drm_modeset_lock_crtc(crtc, &plane->base);
3230
 
3231
		plane_state = to_intel_plane_state(plane->base.state);
3232
 
3233
		if (plane_state->base.fb)
3234
			plane->commit_plane(&plane->base, plane_state);
3235
 
3236
		drm_modeset_unlock_crtc(crtc);
4104 Serge 3237
	}
3238
}
3239
 
5354 serge 3240
void intel_prepare_reset(struct drm_device *dev)
3241
{
3242
	/* no reset support for gen2 */
3243
	if (IS_GEN2(dev))
3244
		return;
3245
 
3246
	/* reset doesn't touch the display */
3247
	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3248
		return;
3249
 
3250
	drm_modeset_lock_all(dev);
3251
	/*
3252
	 * Disabling the crtcs gracefully seems nicer. Also the
3253
	 * g33 docs say we should at least disable all the planes.
3254
	 */
6084 serge 3255
	intel_display_suspend(dev);
5354 serge 3256
}
3257
 
3258
void intel_finish_reset(struct drm_device *dev)
3259
{
3260
	struct drm_i915_private *dev_priv = to_i915(dev);
3261
 
3262
	/*
3263
	 * Flips in the rings will be nuked by the reset,
3264
	 * so complete all pending flips so that user space
3265
	 * will get its events and not get stuck.
3266
	 */
3267
	intel_complete_page_flips(dev);
3268
 
3269
	/* no reset support for gen2 */
3270
	if (IS_GEN2(dev))
3271
		return;
3272
 
3273
	/* reset doesn't touch the display */
3274
	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3275
		/*
3276
		 * Flips in the rings have been nuked by the reset,
3277
		 * so update the base address of all primary
3278
		 * planes to the the last fb to make sure we're
3279
		 * showing the correct fb after a reset.
6084 serge 3280
		 *
3281
		 * FIXME: Atomic will make this obsolete since we won't schedule
3282
		 * CS-based flips (which might get lost in gpu resets) any more.
5354 serge 3283
		 */
3284
		intel_update_primary_planes(dev);
3285
		return;
3286
	}
3287
 
3288
	/*
3289
	 * The display has been reset as well,
3290
	 * so need a full re-initialization.
3291
	 */
3292
	intel_runtime_pm_disable_interrupts(dev_priv);
3293
	intel_runtime_pm_enable_interrupts(dev_priv);
3294
 
3295
	intel_modeset_init_hw(dev);
3296
 
3297
	spin_lock_irq(&dev_priv->irq_lock);
3298
	if (dev_priv->display.hpd_irq_setup)
3299
		dev_priv->display.hpd_irq_setup(dev);
3300
	spin_unlock_irq(&dev_priv->irq_lock);
3301
 
6084 serge 3302
	intel_display_resume(dev);
5354 serge 3303
 
6283 serge 3304
//	intel_hpd_init(dev_priv);
5354 serge 3305
 
3306
	drm_modeset_unlock_all(dev);
3307
}
3308
 
6084 serge 3309
static void
3031 serge 3310
intel_finish_fb(struct drm_framebuffer *old_fb)
3311
{
5060 serge 3312
	struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
6084 serge 3313
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3031 serge 3314
	bool was_interruptible = dev_priv->mm.interruptible;
2327 Serge 3315
	int ret;
3316
 
3031 serge 3317
	/* Big Hammer, we also need to ensure that any pending
3318
	 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3319
	 * current scanout is retired before unpinning the old
6084 serge 3320
	 * framebuffer. Note that we rely on userspace rendering
3321
	 * into the buffer attached to the pipe they are waiting
3322
	 * on. If not, userspace generates a GPU hang with IPEHR
3323
	 * point to the MI_WAIT_FOR_EVENT.
3031 serge 3324
	 *
3325
	 * This should only fail upon a hung GPU, in which case we
3326
	 * can safely continue.
3327
	 */
3328
	dev_priv->mm.interruptible = false;
6084 serge 3329
	ret = i915_gem_object_wait_rendering(obj, true);
3031 serge 3330
	dev_priv->mm.interruptible = was_interruptible;
2327 Serge 3331
 
6084 serge 3332
	WARN_ON(ret);
2327 Serge 3333
}
4104 Serge 3334
 
5060 serge 3335
static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
4104 Serge 3336
{
3337
	struct drm_device *dev = crtc->dev;
5060 serge 3338
	struct drm_i915_private *dev_priv = dev->dev_private;
4104 Serge 3339
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060 serge 3340
	bool pending;
4104 Serge 3341
 
5060 serge 3342
	if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3343
	    intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3344
		return false;
4104 Serge 3345
 
5354 serge 3346
	spin_lock_irq(&dev->event_lock);
5060 serge 3347
	pending = to_intel_crtc(crtc)->unpin_work != NULL;
5354 serge 3348
	spin_unlock_irq(&dev->event_lock);
4104 Serge 3349
 
5060 serge 3350
	return pending;
4104 Serge 3351
}
2327 Serge 3352
 
6084 serge 3353
static void intel_update_pipe_config(struct intel_crtc *crtc,
3354
				     struct intel_crtc_state *old_crtc_state)
5354 serge 3355
{
3356
	struct drm_device *dev = crtc->base.dev;
3357
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 3358
	struct intel_crtc_state *pipe_config =
3359
		to_intel_crtc_state(crtc->base.state);
5354 serge 3360
 
6084 serge 3361
	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3362
	crtc->base.mode = crtc->base.state->mode;
5354 serge 3363
 
6084 serge 3364
	DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3365
		      old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3366
		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3367
 
3368
	if (HAS_DDI(dev))
3369
		intel_set_pipe_csc(&crtc->base);
3370
 
5354 serge 3371
	/*
3372
	 * Update pipe size and adjust fitter if needed: the reason for this is
3373
	 * that in compute_mode_changes we check the native mode (not the pfit
3374
	 * mode) to see if we can flip rather than do a full mode set. In the
3375
	 * fastboot case, we'll flip, but if we don't update the pipesrc and
3376
	 * pfit state, we'll end up with a big fb scanned out into the wrong
3377
	 * sized surface.
3378
	 */
3379
 
3380
	I915_WRITE(PIPESRC(crtc->pipe),
6084 serge 3381
		   ((pipe_config->pipe_src_w - 1) << 16) |
3382
		   (pipe_config->pipe_src_h - 1));
5354 serge 3383
 
6084 serge 3384
	/* on skylake this is done by detaching scalers */
3385
	if (INTEL_INFO(dev)->gen >= 9) {
3386
		skl_detach_scalers(crtc);
2327 Serge 3387
 
6084 serge 3388
		if (pipe_config->pch_pfit.enabled)
3389
			skylake_pfit_enable(crtc);
3390
	} else if (HAS_PCH_SPLIT(dev)) {
3391
		if (pipe_config->pch_pfit.enabled)
3392
			ironlake_pfit_enable(crtc);
3393
		else if (old_crtc_state->pch_pfit.enabled)
3394
			ironlake_pfit_disable(crtc, true);
2327 Serge 3395
	}
3396
}
3397
 
3398
static void intel_fdi_normal_train(struct drm_crtc *crtc)
3399
{
3400
	struct drm_device *dev = crtc->dev;
3401
	struct drm_i915_private *dev_priv = dev->dev_private;
3402
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3403
	int pipe = intel_crtc->pipe;
3404
	u32 reg, temp;
3405
 
3406
	/* enable normal train */
3407
	reg = FDI_TX_CTL(pipe);
3408
	temp = I915_READ(reg);
3409
	if (IS_IVYBRIDGE(dev)) {
3410
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3411
		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3412
	} else {
3413
		temp &= ~FDI_LINK_TRAIN_NONE;
3414
		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3415
	}
3416
	I915_WRITE(reg, temp);
3417
 
3418
	reg = FDI_RX_CTL(pipe);
3419
	temp = I915_READ(reg);
3420
	if (HAS_PCH_CPT(dev)) {
3421
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3422
		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3423
	} else {
3424
		temp &= ~FDI_LINK_TRAIN_NONE;
3425
		temp |= FDI_LINK_TRAIN_NONE;
3426
	}
3427
	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3428
 
3429
	/* wait one idle pattern time */
3430
	POSTING_READ(reg);
3431
	udelay(1000);
3432
 
3433
	/* IVB wants error correction enabled */
3434
	if (IS_IVYBRIDGE(dev))
3435
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3436
			   FDI_FE_ERRC_ENABLE);
3437
}
3438
 
3439
/* The FDI link training functions for ILK/Ibexpeak. */
3440
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3441
{
6084 serge 3442
	struct drm_device *dev = crtc->dev;
3443
	struct drm_i915_private *dev_priv = dev->dev_private;
3444
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3445
	int pipe = intel_crtc->pipe;
3446
	u32 reg, temp, tries;
2327 Serge 3447
 
5060 serge 3448
	/* FDI needs bits from pipe first */
6084 serge 3449
	assert_pipe_enabled(dev_priv, pipe);
2327 Serge 3450
 
6084 serge 3451
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3452
	   for train result */
3453
	reg = FDI_RX_IMR(pipe);
3454
	temp = I915_READ(reg);
3455
	temp &= ~FDI_RX_SYMBOL_LOCK;
3456
	temp &= ~FDI_RX_BIT_LOCK;
3457
	I915_WRITE(reg, temp);
3458
	I915_READ(reg);
3459
	udelay(150);
2327 Serge 3460
 
6084 serge 3461
	/* enable CPU FDI TX and PCH FDI RX */
3462
	reg = FDI_TX_CTL(pipe);
3463
	temp = I915_READ(reg);
4104 Serge 3464
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
6084 serge 3465
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3466
	temp &= ~FDI_LINK_TRAIN_NONE;
3467
	temp |= FDI_LINK_TRAIN_PATTERN_1;
3468
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2327 Serge 3469
 
6084 serge 3470
	reg = FDI_RX_CTL(pipe);
3471
	temp = I915_READ(reg);
3472
	temp &= ~FDI_LINK_TRAIN_NONE;
3473
	temp |= FDI_LINK_TRAIN_PATTERN_1;
3474
	I915_WRITE(reg, temp | FDI_RX_ENABLE);
2327 Serge 3475
 
6084 serge 3476
	POSTING_READ(reg);
3477
	udelay(150);
2327 Serge 3478
 
6084 serge 3479
	/* Ironlake workaround, enable clock pointer after FDI enable*/
3480
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3481
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3482
		   FDI_RX_PHASE_SYNC_POINTER_EN);
2327 Serge 3483
 
6084 serge 3484
	reg = FDI_RX_IIR(pipe);
3485
	for (tries = 0; tries < 5; tries++) {
3486
		temp = I915_READ(reg);
3487
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2327 Serge 3488
 
6084 serge 3489
		if ((temp & FDI_RX_BIT_LOCK)) {
3490
			DRM_DEBUG_KMS("FDI train 1 done.\n");
3491
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3492
			break;
3493
		}
3494
	}
3495
	if (tries == 5)
3496
		DRM_ERROR("FDI train 1 fail!\n");
2327 Serge 3497
 
6084 serge 3498
	/* Train 2 */
3499
	reg = FDI_TX_CTL(pipe);
3500
	temp = I915_READ(reg);
3501
	temp &= ~FDI_LINK_TRAIN_NONE;
3502
	temp |= FDI_LINK_TRAIN_PATTERN_2;
3503
	I915_WRITE(reg, temp);
2327 Serge 3504
 
6084 serge 3505
	reg = FDI_RX_CTL(pipe);
3506
	temp = I915_READ(reg);
3507
	temp &= ~FDI_LINK_TRAIN_NONE;
3508
	temp |= FDI_LINK_TRAIN_PATTERN_2;
3509
	I915_WRITE(reg, temp);
2327 Serge 3510
 
6084 serge 3511
	POSTING_READ(reg);
3512
	udelay(150);
2327 Serge 3513
 
6084 serge 3514
	reg = FDI_RX_IIR(pipe);
3515
	for (tries = 0; tries < 5; tries++) {
3516
		temp = I915_READ(reg);
3517
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2327 Serge 3518
 
6084 serge 3519
		if (temp & FDI_RX_SYMBOL_LOCK) {
3520
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3521
			DRM_DEBUG_KMS("FDI train 2 done.\n");
3522
			break;
3523
		}
3524
	}
3525
	if (tries == 5)
3526
		DRM_ERROR("FDI train 2 fail!\n");
2327 Serge 3527
 
6084 serge 3528
	DRM_DEBUG_KMS("FDI train done\n");
2327 Serge 3529
 
3530
}
3531
 
2342 Serge 3532
static const int snb_b_fdi_train_param[] = {
6084 serge 3533
	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3534
	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3535
	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3536
	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2327 Serge 3537
};
3538
 
3539
/* The FDI link training functions for SNB/Cougarpoint. */
3540
static void gen6_fdi_link_train(struct drm_crtc *crtc)
3541
{
6084 serge 3542
	struct drm_device *dev = crtc->dev;
3543
	struct drm_i915_private *dev_priv = dev->dev_private;
3544
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3545
	int pipe = intel_crtc->pipe;
3031 serge 3546
	u32 reg, temp, i, retry;
2327 Serge 3547
 
6084 serge 3548
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3549
	   for train result */
3550
	reg = FDI_RX_IMR(pipe);
3551
	temp = I915_READ(reg);
3552
	temp &= ~FDI_RX_SYMBOL_LOCK;
3553
	temp &= ~FDI_RX_BIT_LOCK;
3554
	I915_WRITE(reg, temp);
2327 Serge 3555
 
6084 serge 3556
	POSTING_READ(reg);
3557
	udelay(150);
2327 Serge 3558
 
6084 serge 3559
	/* enable CPU FDI TX and PCH FDI RX */
3560
	reg = FDI_TX_CTL(pipe);
3561
	temp = I915_READ(reg);
4104 Serge 3562
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
6084 serge 3563
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3564
	temp &= ~FDI_LINK_TRAIN_NONE;
3565
	temp |= FDI_LINK_TRAIN_PATTERN_1;
3566
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3567
	/* SNB-B */
3568
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3569
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2327 Serge 3570
 
3243 Serge 3571
	I915_WRITE(FDI_RX_MISC(pipe),
3572
		   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3573
 
6084 serge 3574
	reg = FDI_RX_CTL(pipe);
3575
	temp = I915_READ(reg);
3576
	if (HAS_PCH_CPT(dev)) {
3577
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3578
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3579
	} else {
3580
		temp &= ~FDI_LINK_TRAIN_NONE;
3581
		temp |= FDI_LINK_TRAIN_PATTERN_1;
3582
	}
3583
	I915_WRITE(reg, temp | FDI_RX_ENABLE);
2327 Serge 3584
 
6084 serge 3585
	POSTING_READ(reg);
3586
	udelay(150);
2327 Serge 3587
 
2342 Serge 3588
	for (i = 0; i < 4; i++) {
6084 serge 3589
		reg = FDI_TX_CTL(pipe);
3590
		temp = I915_READ(reg);
3591
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3592
		temp |= snb_b_fdi_train_param[i];
3593
		I915_WRITE(reg, temp);
2327 Serge 3594
 
6084 serge 3595
		POSTING_READ(reg);
3596
		udelay(500);
2327 Serge 3597
 
3031 serge 3598
		for (retry = 0; retry < 5; retry++) {
6084 serge 3599
			reg = FDI_RX_IIR(pipe);
3600
			temp = I915_READ(reg);
3601
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3602
			if (temp & FDI_RX_BIT_LOCK) {
3603
				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3604
				DRM_DEBUG_KMS("FDI train 1 done.\n");
3605
				break;
3606
			}
3031 serge 3607
			udelay(50);
3608
		}
3609
		if (retry < 5)
3610
			break;
6084 serge 3611
	}
3612
	if (i == 4)
3613
		DRM_ERROR("FDI train 1 fail!\n");
2327 Serge 3614
 
6084 serge 3615
	/* Train 2 */
3616
	reg = FDI_TX_CTL(pipe);
3617
	temp = I915_READ(reg);
3618
	temp &= ~FDI_LINK_TRAIN_NONE;
3619
	temp |= FDI_LINK_TRAIN_PATTERN_2;
3620
	if (IS_GEN6(dev)) {
3621
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3622
		/* SNB-B */
3623
		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3624
	}
3625
	I915_WRITE(reg, temp);
2327 Serge 3626
 
6084 serge 3627
	reg = FDI_RX_CTL(pipe);
3628
	temp = I915_READ(reg);
3629
	if (HAS_PCH_CPT(dev)) {
3630
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3631
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3632
	} else {
3633
		temp &= ~FDI_LINK_TRAIN_NONE;
3634
		temp |= FDI_LINK_TRAIN_PATTERN_2;
3635
	}
3636
	I915_WRITE(reg, temp);
2327 Serge 3637
 
6084 serge 3638
	POSTING_READ(reg);
3639
	udelay(150);
2327 Serge 3640
 
2342 Serge 3641
	for (i = 0; i < 4; i++) {
6084 serge 3642
		reg = FDI_TX_CTL(pipe);
3643
		temp = I915_READ(reg);
3644
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3645
		temp |= snb_b_fdi_train_param[i];
3646
		I915_WRITE(reg, temp);
2327 Serge 3647
 
6084 serge 3648
		POSTING_READ(reg);
3649
		udelay(500);
2327 Serge 3650
 
3031 serge 3651
		for (retry = 0; retry < 5; retry++) {
6084 serge 3652
			reg = FDI_RX_IIR(pipe);
3653
			temp = I915_READ(reg);
3654
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3655
			if (temp & FDI_RX_SYMBOL_LOCK) {
3656
				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3657
				DRM_DEBUG_KMS("FDI train 2 done.\n");
3658
				break;
3659
			}
3031 serge 3660
			udelay(50);
3661
		}
3662
		if (retry < 5)
3663
			break;
6084 serge 3664
	}
3665
	if (i == 4)
3666
		DRM_ERROR("FDI train 2 fail!\n");
2327 Serge 3667
 
6084 serge 3668
	DRM_DEBUG_KMS("FDI train done.\n");
2327 Serge 3669
}
3670
 
3671
/* Manual link training for Ivy Bridge A0 parts */
3672
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3673
{
6084 serge 3674
	struct drm_device *dev = crtc->dev;
3675
	struct drm_i915_private *dev_priv = dev->dev_private;
3676
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677
	int pipe = intel_crtc->pipe;
4104 Serge 3678
	u32 reg, temp, i, j;
2327 Serge 3679
 
6084 serge 3680
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3681
	   for train result */
3682
	reg = FDI_RX_IMR(pipe);
3683
	temp = I915_READ(reg);
3684
	temp &= ~FDI_RX_SYMBOL_LOCK;
3685
	temp &= ~FDI_RX_BIT_LOCK;
3686
	I915_WRITE(reg, temp);
2327 Serge 3687
 
6084 serge 3688
	POSTING_READ(reg);
3689
	udelay(150);
2327 Serge 3690
 
3243 Serge 3691
	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3692
		      I915_READ(FDI_RX_IIR(pipe)));
3693
 
4104 Serge 3694
	/* Try each vswing and preemphasis setting twice before moving on */
3695
	for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3696
		/* disable first in case we need to retry */
3697
		reg = FDI_TX_CTL(pipe);
3698
		temp = I915_READ(reg);
3699
		temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3700
		temp &= ~FDI_TX_ENABLE;
3701
		I915_WRITE(reg, temp);
3702
 
3703
		reg = FDI_RX_CTL(pipe);
3704
		temp = I915_READ(reg);
3705
		temp &= ~FDI_LINK_TRAIN_AUTO;
3706
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3707
		temp &= ~FDI_RX_ENABLE;
3708
		I915_WRITE(reg, temp);
3709
 
6084 serge 3710
		/* enable CPU FDI TX and PCH FDI RX */
3711
		reg = FDI_TX_CTL(pipe);
3712
		temp = I915_READ(reg);
3713
		temp &= ~FDI_DP_PORT_WIDTH_MASK;
3714
		temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3715
		temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3716
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4104 Serge 3717
		temp |= snb_b_fdi_train_param[j/2];
6084 serge 3718
		temp |= FDI_COMPOSITE_SYNC;
3719
		I915_WRITE(reg, temp | FDI_TX_ENABLE);
2327 Serge 3720
 
6084 serge 3721
		I915_WRITE(FDI_RX_MISC(pipe),
3722
			   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3243 Serge 3723
 
6084 serge 3724
		reg = FDI_RX_CTL(pipe);
3725
		temp = I915_READ(reg);
3726
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3727
		temp |= FDI_COMPOSITE_SYNC;
3728
		I915_WRITE(reg, temp | FDI_RX_ENABLE);
2327 Serge 3729
 
6084 serge 3730
		POSTING_READ(reg);
4104 Serge 3731
		udelay(1); /* should be 0.5us */
2327 Serge 3732
 
6084 serge 3733
		for (i = 0; i < 4; i++) {
3734
			reg = FDI_RX_IIR(pipe);
3735
			temp = I915_READ(reg);
3736
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2327 Serge 3737
 
6084 serge 3738
			if (temp & FDI_RX_BIT_LOCK ||
3739
			    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3740
				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4104 Serge 3741
				DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3742
					      i);
6084 serge 3743
				break;
3744
			}
4104 Serge 3745
			udelay(1); /* should be 0.5us */
3746
		}
3747
		if (i == 4) {
3748
			DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3749
			continue;
6084 serge 3750
		}
2327 Serge 3751
 
6084 serge 3752
		/* Train 2 */
3753
		reg = FDI_TX_CTL(pipe);
3754
		temp = I915_READ(reg);
3755
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3756
		temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3757
		I915_WRITE(reg, temp);
2327 Serge 3758
 
6084 serge 3759
		reg = FDI_RX_CTL(pipe);
3760
		temp = I915_READ(reg);
3761
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3762
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3763
		I915_WRITE(reg, temp);
2327 Serge 3764
 
6084 serge 3765
		POSTING_READ(reg);
4104 Serge 3766
		udelay(2); /* should be 1.5us */
2327 Serge 3767
 
6084 serge 3768
		for (i = 0; i < 4; i++) {
3769
			reg = FDI_RX_IIR(pipe);
3770
			temp = I915_READ(reg);
3771
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2327 Serge 3772
 
4104 Serge 3773
			if (temp & FDI_RX_SYMBOL_LOCK ||
3774
			    (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
6084 serge 3775
				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4104 Serge 3776
				DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3777
					      i);
3778
				goto train_done;
6084 serge 3779
			}
4104 Serge 3780
			udelay(2); /* should be 1.5us */
6084 serge 3781
		}
3782
		if (i == 4)
4104 Serge 3783
			DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3784
	}
2327 Serge 3785
 
4104 Serge 3786
train_done:
6084 serge 3787
	DRM_DEBUG_KMS("FDI train done.\n");
2327 Serge 3788
}
3789
 
3031 serge 3790
static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327 Serge 3791
{
3031 serge 3792
	struct drm_device *dev = intel_crtc->base.dev;
2327 Serge 3793
	struct drm_i915_private *dev_priv = dev->dev_private;
3794
	int pipe = intel_crtc->pipe;
3795
	u32 reg, temp;
3796
 
3797
 
3798
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3799
	reg = FDI_RX_CTL(pipe);
3800
	temp = I915_READ(reg);
4104 Serge 3801
	temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6084 serge 3802
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3480 Serge 3803
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327 Serge 3804
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3805
 
3806
	POSTING_READ(reg);
3807
	udelay(200);
3808
 
3809
	/* Switch from Rawclk to PCDclk */
3810
	temp = I915_READ(reg);
3811
	I915_WRITE(reg, temp | FDI_PCDCLK);
3812
 
3813
	POSTING_READ(reg);
3814
	udelay(200);
3815
 
3816
	/* Enable CPU FDI TX PLL, always on for Ironlake */
3817
	reg = FDI_TX_CTL(pipe);
3818
	temp = I915_READ(reg);
3819
	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3820
		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3821
 
3822
		POSTING_READ(reg);
3823
		udelay(100);
3824
	}
3825
}
3826
 
3031 serge 3827
static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3828
{
3829
	struct drm_device *dev = intel_crtc->base.dev;
3830
	struct drm_i915_private *dev_priv = dev->dev_private;
3831
	int pipe = intel_crtc->pipe;
3832
	u32 reg, temp;
3833
 
3834
	/* Switch from PCDclk to Rawclk */
3835
	reg = FDI_RX_CTL(pipe);
3836
	temp = I915_READ(reg);
3837
	I915_WRITE(reg, temp & ~FDI_PCDCLK);
3838
 
3839
	/* Disable CPU FDI TX PLL */
3840
	reg = FDI_TX_CTL(pipe);
3841
	temp = I915_READ(reg);
3842
	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3843
 
3844
	POSTING_READ(reg);
3845
	udelay(100);
3846
 
3847
	reg = FDI_RX_CTL(pipe);
3848
	temp = I915_READ(reg);
3849
	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3850
 
3851
	/* Wait for the clocks to turn off. */
3852
	POSTING_READ(reg);
3853
	udelay(100);
3854
}
3855
 
2327 Serge 3856
static void ironlake_fdi_disable(struct drm_crtc *crtc)
3857
{
3858
	struct drm_device *dev = crtc->dev;
3859
	struct drm_i915_private *dev_priv = dev->dev_private;
3860
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3861
	int pipe = intel_crtc->pipe;
3862
	u32 reg, temp;
3863
 
3864
	/* disable CPU FDI tx and PCH FDI rx */
3865
	reg = FDI_TX_CTL(pipe);
3866
	temp = I915_READ(reg);
3867
	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3868
	POSTING_READ(reg);
3869
 
3870
	reg = FDI_RX_CTL(pipe);
3871
	temp = I915_READ(reg);
3872
	temp &= ~(0x7 << 16);
3480 Serge 3873
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327 Serge 3874
	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3875
 
3876
	POSTING_READ(reg);
3877
	udelay(100);
3878
 
3879
	/* Ironlake workaround, disable clock pointer after downing FDI */
5060 serge 3880
	if (HAS_PCH_IBX(dev))
2327 Serge 3881
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3882
 
3883
	/* still set train pattern 1 */
3884
	reg = FDI_TX_CTL(pipe);
3885
	temp = I915_READ(reg);
3886
	temp &= ~FDI_LINK_TRAIN_NONE;
3887
	temp |= FDI_LINK_TRAIN_PATTERN_1;
3888
	I915_WRITE(reg, temp);
3889
 
3890
	reg = FDI_RX_CTL(pipe);
3891
	temp = I915_READ(reg);
3892
	if (HAS_PCH_CPT(dev)) {
3893
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3894
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3895
	} else {
3896
		temp &= ~FDI_LINK_TRAIN_NONE;
3897
		temp |= FDI_LINK_TRAIN_PATTERN_1;
3898
	}
3899
	/* BPC in FDI rx is consistent with that in PIPECONF */
3900
	temp &= ~(0x07 << 16);
3480 Serge 3901
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327 Serge 3902
	I915_WRITE(reg, temp);
3903
 
3904
	POSTING_READ(reg);
3905
	udelay(100);
3906
}
3907
 
5060 serge 3908
bool intel_has_pending_fb_unpin(struct drm_device *dev)
2327 Serge 3909
{
5060 serge 3910
	struct intel_crtc *crtc;
2327 Serge 3911
 
5060 serge 3912
	/* Note that we don't need to be called with mode_config.lock here
3913
	 * as our list of CRTC objects is static for the lifetime of the
3914
	 * device and so cannot disappear as we iterate. Similarly, we can
3915
	 * happily treat the predicates as racy, atomic checks as userspace
3916
	 * cannot claim and pin a new fb without at least acquring the
3917
	 * struct_mutex and so serialising with us.
3918
	 */
3919
	for_each_intel_crtc(dev, crtc) {
3920
		if (atomic_read(&crtc->unpin_work_count) == 0)
3921
			continue;
2327 Serge 3922
 
5060 serge 3923
		if (crtc->unpin_work)
3924
			intel_wait_for_vblank(dev, crtc->pipe);
3031 serge 3925
 
5060 serge 3926
		return true;
3927
	}
3928
 
3929
	return false;
2327 Serge 3930
}
3931
 
6283 serge 3932
static void page_flip_completed(struct intel_crtc *intel_crtc)
3933
{
3934
	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3935
	struct intel_unpin_work *work = intel_crtc->unpin_work;
3936
 
3937
	/* ensure that the unpin work is consistent wrt ->pending. */
3938
	smp_rmb();
3939
	intel_crtc->unpin_work = NULL;
3940
 
3941
	if (work->event)
3942
		drm_send_vblank_event(intel_crtc->base.dev,
3943
				      intel_crtc->pipe,
3944
				      work->event);
3945
 
3946
	drm_crtc_vblank_put(&intel_crtc->base);
3947
 
3948
//	wake_up_all(&dev_priv->pending_flip_queue);
3949
//	queue_work(dev_priv->wq, &work->work);
3950
 
3951
//	trace_i915_flip_complete(intel_crtc->plane,
3952
//				 work->pending_flip_obj);
3953
}
3031 serge 3954
#if 0
5060 serge 3955
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2327 Serge 3956
{
3031 serge 3957
	struct drm_device *dev = crtc->dev;
3958
	struct drm_i915_private *dev_priv = dev->dev_private;
2327 Serge 3959
 
3480 Serge 3960
	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5354 serge 3961
	if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3962
				       !intel_crtc_has_pending_flip(crtc),
3963
				       60*HZ) == 0)) {
3964
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480 Serge 3965
 
5354 serge 3966
		spin_lock_irq(&dev->event_lock);
3967
		if (intel_crtc->unpin_work) {
3968
			WARN_ONCE(1, "Removing stuck page flip\n");
3969
			page_flip_completed(intel_crtc);
3970
		}
3971
		spin_unlock_irq(&dev->event_lock);
3972
	}
3031 serge 3973
 
5354 serge 3974
	if (crtc->primary->fb) {
6084 serge 3975
		mutex_lock(&dev->struct_mutex);
3976
		intel_finish_fb(crtc->primary->fb);
3977
		mutex_unlock(&dev->struct_mutex);
5354 serge 3978
	}
2327 Serge 3979
}
3031 serge 3980
#endif
2327 Serge 3981
 
3031 serge 3982
/* Program iCLKIP clock to the desired frequency */
3983
static void lpt_program_iclkip(struct drm_crtc *crtc)
3984
{
3985
	struct drm_device *dev = crtc->dev;
3986
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 3987
	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3031 serge 3988
	u32 divsel, phaseinc, auxdiv, phasedir = 0;
3989
	u32 temp;
3990
 
6084 serge 3991
	mutex_lock(&dev_priv->sb_lock);
3480 Serge 3992
 
3031 serge 3993
	/* It is necessary to ungate the pixclk gate prior to programming
3994
	 * the divisors, and gate it back when it is done.
3995
	 */
3996
	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3997
 
3998
	/* Disable SSCCTL */
3999
	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3243 Serge 4000
			intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
4001
				SBI_SSCCTL_DISABLE,
4002
			SBI_ICLK);
3031 serge 4003
 
4004
	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
4560 Serge 4005
	if (clock == 20000) {
3031 serge 4006
		auxdiv = 1;
4007
		divsel = 0x41;
4008
		phaseinc = 0x20;
4009
	} else {
4010
		/* The iCLK virtual clock root frequency is in MHz,
4560 Serge 4011
		 * but the adjusted_mode->crtc_clock in in KHz. To get the
4012
		 * divisors, it is necessary to divide one by another, so we
3031 serge 4013
		 * convert the virtual clock precision to KHz here for higher
4014
		 * precision.
4015
		 */
4016
		u32 iclk_virtual_root_freq = 172800 * 1000;
4017
		u32 iclk_pi_range = 64;
4018
		u32 desired_divisor, msb_divisor_value, pi_value;
4019
 
4560 Serge 4020
		desired_divisor = (iclk_virtual_root_freq / clock);
3031 serge 4021
		msb_divisor_value = desired_divisor / iclk_pi_range;
4022
		pi_value = desired_divisor % iclk_pi_range;
4023
 
4024
		auxdiv = 0;
4025
		divsel = msb_divisor_value - 2;
4026
		phaseinc = pi_value;
4027
	}
4028
 
4029
	/* This should not happen with any sane values */
4030
	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4031
		~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4032
	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4033
		~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4034
 
4035
	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4560 Serge 4036
			clock,
3031 serge 4037
			auxdiv,
4038
			divsel,
4039
			phasedir,
4040
			phaseinc);
4041
 
4042
	/* Program SSCDIVINTPHASE6 */
3243 Serge 4043
	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3031 serge 4044
	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4045
	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4046
	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4047
	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4048
	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4049
	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3243 Serge 4050
	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031 serge 4051
 
4052
	/* Program SSCAUXDIV */
3243 Serge 4053
	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3031 serge 4054
	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4055
	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3243 Serge 4056
	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3031 serge 4057
 
4058
	/* Enable modulator and associated divider */
3243 Serge 4059
	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3031 serge 4060
	temp &= ~SBI_SSCCTL_DISABLE;
3243 Serge 4061
	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3031 serge 4062
 
4063
	/* Wait for initialization time */
4064
	udelay(24);
4065
 
4066
	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3480 Serge 4067
 
6084 serge 4068
	mutex_unlock(&dev_priv->sb_lock);
3031 serge 4069
}
4070
 
4104 Serge 4071
static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4072
						enum pipe pch_transcoder)
4073
{
4074
	struct drm_device *dev = crtc->base.dev;
4075
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 4076
	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4104 Serge 4077
 
4078
	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4079
		   I915_READ(HTOTAL(cpu_transcoder)));
4080
	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4081
		   I915_READ(HBLANK(cpu_transcoder)));
4082
	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4083
		   I915_READ(HSYNC(cpu_transcoder)));
4084
 
4085
	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4086
		   I915_READ(VTOTAL(cpu_transcoder)));
4087
	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4088
		   I915_READ(VBLANK(cpu_transcoder)));
4089
	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4090
		   I915_READ(VSYNC(cpu_transcoder)));
4091
	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4092
		   I915_READ(VSYNCSHIFT(cpu_transcoder)));
4093
}
4094
 
6084 serge 4095
static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4280 Serge 4096
{
4097
	struct drm_i915_private *dev_priv = dev->dev_private;
4098
	uint32_t temp;
4099
 
4100
	temp = I915_READ(SOUTH_CHICKEN1);
6084 serge 4101
	if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4280 Serge 4102
		return;
4103
 
4104
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4105
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4106
 
6084 serge 4107
	temp &= ~FDI_BC_BIFURCATION_SELECT;
4108
	if (enable)
4109
		temp |= FDI_BC_BIFURCATION_SELECT;
4110
 
4111
	DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4280 Serge 4112
	I915_WRITE(SOUTH_CHICKEN1, temp);
4113
	POSTING_READ(SOUTH_CHICKEN1);
4114
}
4115
 
4116
static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4117
{
4118
	struct drm_device *dev = intel_crtc->base.dev;
4119
 
4120
	switch (intel_crtc->pipe) {
4121
	case PIPE_A:
4122
		break;
4123
	case PIPE_B:
6084 serge 4124
		if (intel_crtc->config->fdi_lanes > 2)
4125
			cpt_set_fdi_bc_bifurcation(dev, false);
4280 Serge 4126
		else
6084 serge 4127
			cpt_set_fdi_bc_bifurcation(dev, true);
4280 Serge 4128
 
4129
		break;
4130
	case PIPE_C:
6084 serge 4131
		cpt_set_fdi_bc_bifurcation(dev, true);
4280 Serge 4132
 
4133
		break;
4134
	default:
4135
		BUG();
4136
	}
4137
}
4138
 
2327 Serge 4139
/*
4140
 * Enable PCH resources required for PCH ports:
4141
 *   - PCH PLLs
4142
 *   - FDI training & RX/TX
4143
 *   - update transcoder timings
4144
 *   - DP transcoding bits
4145
 *   - transcoder
4146
 */
4147
static void ironlake_pch_enable(struct drm_crtc *crtc)
4148
{
4149
	struct drm_device *dev = crtc->dev;
4150
	struct drm_i915_private *dev_priv = dev->dev_private;
4151
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4152
	int pipe = intel_crtc->pipe;
3031 serge 4153
	u32 reg, temp;
2327 Serge 4154
 
4104 Serge 4155
	assert_pch_transcoder_disabled(dev_priv, pipe);
3031 serge 4156
 
4280 Serge 4157
	if (IS_IVYBRIDGE(dev))
4158
		ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4159
 
3243 Serge 4160
	/* Write the TU size bits before fdi link training, so that error
4161
	 * detection works. */
4162
	I915_WRITE(FDI_RX_TUSIZE1(pipe),
4163
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4164
 
2327 Serge 4165
	/* For PCH output, training FDI link */
4166
	dev_priv->display.fdi_link_train(crtc);
4167
 
4104 Serge 4168
	/* We need to program the right clock selection before writing the pixel
4169
	 * mutliplier into the DPLL. */
3243 Serge 4170
	if (HAS_PCH_CPT(dev)) {
3031 serge 4171
		u32 sel;
2342 Serge 4172
 
2327 Serge 4173
		temp = I915_READ(PCH_DPLL_SEL);
4104 Serge 4174
		temp |= TRANS_DPLL_ENABLE(pipe);
4175
		sel = TRANS_DPLLB_SEL(pipe);
6084 serge 4176
		if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3031 serge 4177
			temp |= sel;
4178
		else
4179
			temp &= ~sel;
2327 Serge 4180
		I915_WRITE(PCH_DPLL_SEL, temp);
4181
	}
4182
 
4104 Serge 4183
	/* XXX: pch pll's can be enabled any time before we enable the PCH
4184
	 * transcoder, and we actually should do this to not upset any PCH
4185
	 * transcoder that already use the clock when we share it.
4186
	 *
4187
	 * Note that enable_shared_dpll tries to do the right thing, but
4188
	 * get_shared_dpll unconditionally resets the pll - we need that to have
4189
	 * the right LVDS enable sequence. */
5060 serge 4190
	intel_enable_shared_dpll(intel_crtc);
4104 Serge 4191
 
2327 Serge 4192
	/* set transcoder timing, panel must allow it */
4193
	assert_panel_unlocked(dev_priv, pipe);
4104 Serge 4194
	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2327 Serge 4195
 
4196
	intel_fdi_normal_train(crtc);
4197
 
4198
	/* For PCH DP, enable TRANS_DP_CTL */
6084 serge 4199
	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3480 Serge 4200
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2327 Serge 4201
		reg = TRANS_DP_CTL(pipe);
4202
		temp = I915_READ(reg);
4203
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
4204
			  TRANS_DP_SYNC_MASK |
4205
			  TRANS_DP_BPC_MASK);
6084 serge 4206
		temp |= TRANS_DP_OUTPUT_ENABLE;
2327 Serge 4207
		temp |= bpc << 9; /* same format but at 11:9 */
4208
 
4209
		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4210
			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4211
		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4212
			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4213
 
4214
		switch (intel_trans_dp_port_sel(crtc)) {
4215
		case PCH_DP_B:
4216
			temp |= TRANS_DP_PORT_SEL_B;
4217
			break;
4218
		case PCH_DP_C:
4219
			temp |= TRANS_DP_PORT_SEL_C;
4220
			break;
4221
		case PCH_DP_D:
4222
			temp |= TRANS_DP_PORT_SEL_D;
4223
			break;
4224
		default:
3243 Serge 4225
			BUG();
2327 Serge 4226
		}
4227
 
4228
		I915_WRITE(reg, temp);
4229
	}
4230
 
3243 Serge 4231
	ironlake_enable_pch_transcoder(dev_priv, pipe);
2327 Serge 4232
}
4233
 
3243 Serge 4234
static void lpt_pch_enable(struct drm_crtc *crtc)
4235
{
4236
	struct drm_device *dev = crtc->dev;
4237
	struct drm_i915_private *dev_priv = dev->dev_private;
4238
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084 serge 4239
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243 Serge 4240
 
4104 Serge 4241
	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3243 Serge 4242
 
4243
	lpt_program_iclkip(crtc);
4244
 
4245
	/* Set transcoder timing. */
4104 Serge 4246
	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3243 Serge 4247
 
4248
	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4249
}
4250
 
6084 serge 4251
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4252
						struct intel_crtc_state *crtc_state)
3031 serge 4253
{
4104 Serge 4254
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
5354 serge 4255
	struct intel_shared_dpll *pll;
6084 serge 4256
	struct intel_shared_dpll_config *shared_dpll;
4104 Serge 4257
	enum intel_dpll_id i;
6084 serge 4258
	int max = dev_priv->num_shared_dpll;
3031 serge 4259
 
6084 serge 4260
	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4261
 
3031 serge 4262
	if (HAS_PCH_IBX(dev_priv->dev)) {
4263
		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4104 Serge 4264
		i = (enum intel_dpll_id) crtc->pipe;
4265
		pll = &dev_priv->shared_dplls[i];
3031 serge 4266
 
4104 Serge 4267
		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4268
			      crtc->base.base.id, pll->name);
3031 serge 4269
 
6084 serge 4270
		WARN_ON(shared_dpll[i].crtc_mask);
5060 serge 4271
 
3031 serge 4272
		goto found;
4273
	}
4274
 
6084 serge 4275
	if (IS_BROXTON(dev_priv->dev)) {
4276
		/* PLL is attached to port in bxt */
4277
		struct intel_encoder *encoder;
4278
		struct intel_digital_port *intel_dig_port;
4279
 
4280
		encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4281
		if (WARN_ON(!encoder))
4282
			return NULL;
4283
 
4284
		intel_dig_port = enc_to_dig_port(&encoder->base);
4285
		/* 1:1 mapping between ports and PLLs */
4286
		i = (enum intel_dpll_id)intel_dig_port->port;
4104 Serge 4287
		pll = &dev_priv->shared_dplls[i];
6084 serge 4288
		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4289
			crtc->base.base.id, pll->name);
4290
		WARN_ON(shared_dpll[i].crtc_mask);
3031 serge 4291
 
6084 serge 4292
		goto found;
4293
	} else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4294
		/* Do not consider SPLL */
4295
		max = 2;
4296
 
4297
	for (i = 0; i < max; i++) {
4298
		pll = &dev_priv->shared_dplls[i];
4299
 
3031 serge 4300
		/* Only want to check enabled timings first */
6084 serge 4301
		if (shared_dpll[i].crtc_mask == 0)
3031 serge 4302
			continue;
4303
 
6084 serge 4304
		if (memcmp(&crtc_state->dpll_hw_state,
4305
			   &shared_dpll[i].hw_state,
4306
			   sizeof(crtc_state->dpll_hw_state)) == 0) {
5354 serge 4307
			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4308
				      crtc->base.base.id, pll->name,
6084 serge 4309
				      shared_dpll[i].crtc_mask,
5354 serge 4310
				      pll->active);
3031 serge 4311
			goto found;
4312
		}
4313
	}
4314
 
4315
	/* Ok no matching timings, maybe there's a free one? */
4104 Serge 4316
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4317
		pll = &dev_priv->shared_dplls[i];
6084 serge 4318
		if (shared_dpll[i].crtc_mask == 0) {
4104 Serge 4319
			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4320
				      crtc->base.base.id, pll->name);
3031 serge 4321
			goto found;
4322
		}
4323
	}
4324
 
4325
	return NULL;
4326
 
4327
found:
6084 serge 4328
	if (shared_dpll[i].crtc_mask == 0)
4329
		shared_dpll[i].hw_state =
4330
			crtc_state->dpll_hw_state;
5060 serge 4331
 
6084 serge 4332
	crtc_state->shared_dpll = i;
4104 Serge 4333
	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4334
			 pipe_name(crtc->pipe));
4335
 
6084 serge 4336
	shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
3031 serge 4337
 
4338
	return pll;
4339
}
4340
 
6084 serge 4341
static void intel_shared_dpll_commit(struct drm_atomic_state *state)
5354 serge 4342
{
6084 serge 4343
	struct drm_i915_private *dev_priv = to_i915(state->dev);
4344
	struct intel_shared_dpll_config *shared_dpll;
5354 serge 4345
	struct intel_shared_dpll *pll;
4346
	enum intel_dpll_id i;
4347
 
6084 serge 4348
	if (!to_intel_atomic_state(state)->dpll_set)
4349
		return;
4350
 
4351
	shared_dpll = to_intel_atomic_state(state)->shared_dpll;
5354 serge 4352
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4353
		pll = &dev_priv->shared_dplls[i];
6084 serge 4354
		pll->config = shared_dpll[i];
4355
	}
4356
}
5354 serge 4357
 
6084 serge 4358
static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4359
{
4360
	struct drm_i915_private *dev_priv = dev->dev_private;
4361
	int dslreg = PIPEDSL(pipe);
4362
	u32 temp;
5354 serge 4363
 
6084 serge 4364
	temp = I915_READ(dslreg);
4365
	udelay(500);
4366
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
4367
		if (wait_for(I915_READ(dslreg) != temp, 5))
4368
			DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5354 serge 4369
	}
6084 serge 4370
}
5354 serge 4371
 
6084 serge 4372
static int
4373
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4374
		  unsigned scaler_user, int *scaler_id, unsigned int rotation,
4375
		  int src_w, int src_h, int dst_w, int dst_h)
4376
{
4377
	struct intel_crtc_scaler_state *scaler_state =
4378
		&crtc_state->scaler_state;
4379
	struct intel_crtc *intel_crtc =
4380
		to_intel_crtc(crtc_state->base.crtc);
4381
	int need_scaling;
5354 serge 4382
 
6084 serge 4383
	need_scaling = intel_rotation_90_or_270(rotation) ?
4384
		(src_h != dst_w || src_w != dst_h):
4385
		(src_w != dst_w || src_h != dst_h);
4386
 
4387
	/*
4388
	 * if plane is being disabled or scaler is no more required or force detach
4389
	 *  - free scaler binded to this plane/crtc
4390
	 *  - in order to do this, update crtc->scaler_usage
4391
	 *
4392
	 * Here scaler state in crtc_state is set free so that
4393
	 * scaler can be assigned to other user. Actual register
4394
	 * update to free the scaler is done in plane/panel-fit programming.
4395
	 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4396
	 */
4397
	if (force_detach || !need_scaling) {
4398
		if (*scaler_id >= 0) {
4399
			scaler_state->scaler_users &= ~(1 << scaler_user);
4400
			scaler_state->scalers[*scaler_id].in_use = 0;
4401
 
4402
			DRM_DEBUG_KMS("scaler_user index %u.%u: "
4403
				"Staged freeing scaler id %d scaler_users = 0x%x\n",
4404
				intel_crtc->pipe, scaler_user, *scaler_id,
4405
				scaler_state->scaler_users);
4406
			*scaler_id = -1;
4407
		}
4408
		return 0;
5354 serge 4409
	}
4410
 
6084 serge 4411
	/* range checks */
4412
	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4413
		dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4414
 
4415
		src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4416
		dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4417
		DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4418
			"size is out of scaler range\n",
4419
			intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4420
		return -EINVAL;
4421
	}
4422
 
4423
	/* mark this plane as a scaler user in crtc_state */
4424
	scaler_state->scaler_users |= (1 << scaler_user);
4425
	DRM_DEBUG_KMS("scaler_user index %u.%u: "
4426
		"staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4427
		intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4428
		scaler_state->scaler_users);
4429
 
4430
	return 0;
5354 serge 4431
}
4432
 
6084 serge 4433
/**
4434
 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4435
 *
4436
 * @state: crtc's scaler state
4437
 *
4438
 * Return
4439
 *     0 - scaler_usage updated successfully
4440
 *    error - requested scaling cannot be supported or other error condition
4441
 */
4442
int skl_update_scaler_crtc(struct intel_crtc_state *state)
5354 serge 4443
{
6084 serge 4444
	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4445
	const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5354 serge 4446
 
6084 serge 4447
	DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4448
		      intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
5354 serge 4449
 
6084 serge 4450
	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4451
		&state->scaler_state.scaler_id, DRM_ROTATE_0,
4452
		state->pipe_src_w, state->pipe_src_h,
4453
		adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
5354 serge 4454
}
4455
 
6084 serge 4456
/**
4457
 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4458
 *
4459
 * @state: crtc's scaler state
4460
 * @plane_state: atomic plane state to update
4461
 *
4462
 * Return
4463
 *     0 - scaler_usage updated successfully
4464
 *    error - requested scaling cannot be supported or other error condition
4465
 */
4466
static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4467
				   struct intel_plane_state *plane_state)
5354 serge 4468
{
4469
 
6084 serge 4470
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4471
	struct intel_plane *intel_plane =
4472
		to_intel_plane(plane_state->base.plane);
4473
	struct drm_framebuffer *fb = plane_state->base.fb;
4474
	int ret;
5354 serge 4475
 
6084 serge 4476
	bool force_detach = !fb || !plane_state->visible;
5354 serge 4477
 
6084 serge 4478
	DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4479
		      intel_plane->base.base.id, intel_crtc->pipe,
4480
		      drm_plane_index(&intel_plane->base));
4481
 
4482
	ret = skl_update_scaler(crtc_state, force_detach,
4483
				drm_plane_index(&intel_plane->base),
4484
				&plane_state->scaler_id,
4485
				plane_state->base.rotation,
4486
				drm_rect_width(&plane_state->src) >> 16,
4487
				drm_rect_height(&plane_state->src) >> 16,
4488
				drm_rect_width(&plane_state->dst),
4489
				drm_rect_height(&plane_state->dst));
4490
 
4491
	if (ret || plane_state->scaler_id < 0)
4492
		return ret;
4493
 
4494
	/* check colorkey */
4495
	if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4496
		DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4497
			      intel_plane->base.base.id);
4498
		return -EINVAL;
5354 serge 4499
	}
6084 serge 4500
 
4501
	/* Check src format */
4502
	switch (fb->pixel_format) {
4503
	case DRM_FORMAT_RGB565:
4504
	case DRM_FORMAT_XBGR8888:
4505
	case DRM_FORMAT_XRGB8888:
4506
	case DRM_FORMAT_ABGR8888:
4507
	case DRM_FORMAT_ARGB8888:
4508
	case DRM_FORMAT_XRGB2101010:
4509
	case DRM_FORMAT_XBGR2101010:
4510
	case DRM_FORMAT_YUYV:
4511
	case DRM_FORMAT_YVYU:
4512
	case DRM_FORMAT_UYVY:
4513
	case DRM_FORMAT_VYUY:
4514
		break;
4515
	default:
4516
		DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4517
			intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4518
		return -EINVAL;
4519
	}
4520
 
4521
	return 0;
5354 serge 4522
}
4523
 
6084 serge 4524
static void skylake_scaler_disable(struct intel_crtc *crtc)
2342 Serge 4525
{
6084 serge 4526
	int i;
2342 Serge 4527
 
6084 serge 4528
	for (i = 0; i < crtc->num_scalers; i++)
4529
		skl_detach_scaler(crtc, i);
2342 Serge 4530
}
4531
 
5354 serge 4532
static void skylake_pfit_enable(struct intel_crtc *crtc)
4533
{
4534
	struct drm_device *dev = crtc->base.dev;
4535
	struct drm_i915_private *dev_priv = dev->dev_private;
4536
	int pipe = crtc->pipe;
6084 serge 4537
	struct intel_crtc_scaler_state *scaler_state =
4538
		&crtc->config->scaler_state;
5354 serge 4539
 
6084 serge 4540
	DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4541
 
4542
	if (crtc->config->pch_pfit.enabled) {
4543
		int id;
4544
 
4545
		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4546
			DRM_ERROR("Requesting pfit without getting a scaler first\n");
4547
			return;
4548
		}
4549
 
4550
		id = scaler_state->scaler_id;
4551
		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4552
			PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4553
		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4554
		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4555
 
4556
		DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
5354 serge 4557
	}
4558
}
4559
 
4104 Serge 4560
static void ironlake_pfit_enable(struct intel_crtc *crtc)
4561
{
4562
	struct drm_device *dev = crtc->base.dev;
4563
	struct drm_i915_private *dev_priv = dev->dev_private;
4564
	int pipe = crtc->pipe;
4565
 
6084 serge 4566
	if (crtc->config->pch_pfit.enabled) {
4104 Serge 4567
		/* Force use of hard-coded filter coefficients
4568
		 * as some pre-programmed values are broken,
4569
		 * e.g. x201.
4570
		 */
4571
		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4572
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4573
						 PF_PIPE_SEL_IVB(pipe));
4574
		else
4575
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6084 serge 4576
		I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4577
		I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4104 Serge 4578
	}
4579
}
4580
 
4560 Serge 4581
void hsw_enable_ips(struct intel_crtc *crtc)
4582
{
5060 serge 4583
	struct drm_device *dev = crtc->base.dev;
4584
	struct drm_i915_private *dev_priv = dev->dev_private;
4560 Serge 4585
 
6084 serge 4586
	if (!crtc->config->ips_enabled)
4560 Serge 4587
		return;
4588
 
5060 serge 4589
	/* We can only enable IPS after we enable a plane and wait for a vblank */
4590
	intel_wait_for_vblank(dev, crtc->pipe);
4591
 
4560 Serge 4592
	assert_plane_enabled(dev_priv, crtc->plane);
5060 serge 4593
	if (IS_BROADWELL(dev)) {
4560 Serge 4594
		mutex_lock(&dev_priv->rps.hw_lock);
4595
		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4596
		mutex_unlock(&dev_priv->rps.hw_lock);
4597
		/* Quoting Art Runyan: "its not safe to expect any particular
4598
		 * value in IPS_CTL bit 31 after enabling IPS through the
4599
		 * mailbox." Moreover, the mailbox may return a bogus state,
4600
		 * so we need to just enable it and continue on.
4601
		 */
4602
	} else {
4603
		I915_WRITE(IPS_CTL, IPS_ENABLE);
4604
		/* The bit only becomes 1 in the next vblank, so this wait here
4605
		 * is essentially intel_wait_for_vblank. If we don't have this
4606
		 * and don't wait for vblanks until the end of crtc_enable, then
4607
		 * the HW state readout code will complain that the expected
4608
		 * IPS_CTL value is not the one we read. */
4609
		if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4610
			DRM_ERROR("Timed out waiting for IPS enable\n");
4611
	}
4612
}
4613
 
4614
void hsw_disable_ips(struct intel_crtc *crtc)
4615
{
4616
	struct drm_device *dev = crtc->base.dev;
4617
	struct drm_i915_private *dev_priv = dev->dev_private;
4618
 
6084 serge 4619
	if (!crtc->config->ips_enabled)
4560 Serge 4620
		return;
4621
 
4622
	assert_plane_enabled(dev_priv, crtc->plane);
5060 serge 4623
	if (IS_BROADWELL(dev)) {
4560 Serge 4624
		mutex_lock(&dev_priv->rps.hw_lock);
4625
		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4626
		mutex_unlock(&dev_priv->rps.hw_lock);
5060 serge 4627
		/* wait for pcode to finish disabling IPS, which may take up to 42ms */
4628
		if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4629
			DRM_ERROR("Timed out waiting for IPS disable\n");
4560 Serge 4630
	} else {
4631
		I915_WRITE(IPS_CTL, 0);
4632
		POSTING_READ(IPS_CTL);
4633
	}
4634
 
4635
	/* We need to wait for a vblank before we can disable the plane. */
4636
	intel_wait_for_vblank(dev, crtc->pipe);
4637
}
4638
 
4639
/** Loads the palette/gamma unit for the CRTC with the prepared values */
4640
static void intel_crtc_load_lut(struct drm_crtc *crtc)
4641
{
4642
	struct drm_device *dev = crtc->dev;
4643
	struct drm_i915_private *dev_priv = dev->dev_private;
4644
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645
	enum pipe pipe = intel_crtc->pipe;
4646
	int i;
4647
	bool reenable_ips = false;
4648
 
4649
	/* The clocks have to be on to load the palette. */
6084 serge 4650
	if (!crtc->state->active)
4560 Serge 4651
		return;
4652
 
6084 serge 4653
	if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
5354 serge 4654
		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4560 Serge 4655
			assert_dsi_pll_enabled(dev_priv);
4656
		else
4657
			assert_pll_enabled(dev_priv, pipe);
4658
	}
4659
 
4660
	/* Workaround : Do not read or write the pipe palette/gamma data while
4661
	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4662
	 */
6084 serge 4663
	if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4560 Serge 4664
	    ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4665
	     GAMMA_MODE_MODE_SPLIT)) {
4666
		hsw_disable_ips(intel_crtc);
4667
		reenable_ips = true;
4668
	}
4669
 
4670
	for (i = 0; i < 256; i++) {
6084 serge 4671
		u32 palreg;
4672
 
4673
		if (HAS_GMCH_DISPLAY(dev))
4674
			palreg = PALETTE(pipe, i);
4675
		else
4676
			palreg = LGC_PALETTE(pipe, i);
4677
 
4678
		I915_WRITE(palreg,
4560 Serge 4679
			   (intel_crtc->lut_r[i] << 16) |
4680
			   (intel_crtc->lut_g[i] << 8) |
4681
			   intel_crtc->lut_b[i]);
4682
	}
4683
 
4684
	if (reenable_ips)
4685
		hsw_enable_ips(intel_crtc);
4686
}
4687
 
6084 serge 4688
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5060 serge 4689
{
6084 serge 4690
	if (intel_crtc->overlay) {
5060 serge 4691
		struct drm_device *dev = intel_crtc->base.dev;
4692
		struct drm_i915_private *dev_priv = dev->dev_private;
4693
 
4694
		mutex_lock(&dev->struct_mutex);
4695
		dev_priv->mm.interruptible = false;
5354 serge 4696
//       (void) intel_overlay_switch_off(intel_crtc->overlay);
6084 serge 4697
		dev_priv->mm.interruptible = true;
5060 serge 4698
		mutex_unlock(&dev->struct_mutex);
4699
	}
4700
 
4701
	/* Let userspace switch the overlay on again. In most cases userspace
4702
	 * has to recompute where to put it anyway.
4703
	 */
4704
}
4705
 
6084 serge 4706
/**
4707
 * intel_post_enable_primary - Perform operations after enabling primary plane
4708
 * @crtc: the CRTC whose primary plane was just enabled
4709
 *
4710
 * Performs potentially sleeping operations that must be done after the primary
4711
 * plane is enabled, such as updating FBC and IPS.  Note that this may be
4712
 * called due to an explicit primary plane update, or due to an implicit
4713
 * re-enable that is caused when a sprite plane is updated to no longer
4714
 * completely hide the primary plane.
4715
 */
4716
static void
4717
intel_post_enable_primary(struct drm_crtc *crtc)
5060 serge 4718
{
4719
	struct drm_device *dev = crtc->dev;
6084 serge 4720
	struct drm_i915_private *dev_priv = dev->dev_private;
5060 serge 4721
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4722
	int pipe = intel_crtc->pipe;
4723
 
6084 serge 4724
	/*
4725
	 * BDW signals flip done immediately if the plane
4726
	 * is disabled, even if the plane enable is already
4727
	 * armed to occur at the next vblank :(
4728
	 */
4729
	if (IS_BROADWELL(dev))
4730
		intel_wait_for_vblank(dev, pipe);
5060 serge 4731
 
6084 serge 4732
	/*
4733
	 * FIXME IPS should be fine as long as one plane is
4734
	 * enabled, but in practice it seems to have problems
4735
	 * when going from primary only to sprite only and vice
4736
	 * versa.
4737
	 */
5060 serge 4738
	hsw_enable_ips(intel_crtc);
4739
 
5354 serge 4740
	/*
6084 serge 4741
	 * Gen2 reports pipe underruns whenever all planes are disabled.
4742
	 * So don't enable underrun reporting before at least some planes
4743
	 * are enabled.
4744
	 * FIXME: Need to fix the logic to work when we turn off all planes
4745
	 * but leave the pipe running.
5354 serge 4746
	 */
6084 serge 4747
	if (IS_GEN2(dev))
4748
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4749
 
4750
	/* Underruns don't raise interrupts, so check manually. */
4751
	if (HAS_GMCH_DISPLAY(dev))
4752
		i9xx_check_fifo_underruns(dev_priv);
5060 serge 4753
}
4754
 
6084 serge 4755
/**
4756
 * intel_pre_disable_primary - Perform operations before disabling primary plane
4757
 * @crtc: the CRTC whose primary plane is to be disabled
4758
 *
4759
 * Performs potentially sleeping operations that must be done before the
4760
 * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4761
 * be called due to an explicit primary plane update, or due to an implicit
4762
 * disable that is caused when a sprite plane completely hides the primary
4763
 * plane.
4764
 */
4765
static void
4766
intel_pre_disable_primary(struct drm_crtc *crtc)
5060 serge 4767
{
4768
	struct drm_device *dev = crtc->dev;
4769
	struct drm_i915_private *dev_priv = dev->dev_private;
4770
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4771
	int pipe = intel_crtc->pipe;
4772
 
6084 serge 4773
	/*
4774
	 * Gen2 reports pipe underruns whenever all planes are disabled.
4775
	 * So diasble underrun reporting before all the planes get disabled.
4776
	 * FIXME: Need to fix the logic to work when we turn off all planes
4777
	 * but leave the pipe running.
4778
	 */
4779
	if (IS_GEN2(dev))
4780
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5060 serge 4781
 
6084 serge 4782
	/*
4783
	 * Vblank time updates from the shadow to live plane control register
4784
	 * are blocked if the memory self-refresh mode is active at that
4785
	 * moment. So to make sure the plane gets truly disabled, disable
4786
	 * first the self-refresh mode. The self-refresh enable bit in turn
4787
	 * will be checked/applied by the HW only at the next frame start
4788
	 * event which is after the vblank start event, so we need to have a
4789
	 * wait-for-vblank between disabling the plane and the pipe.
4790
	 */
4791
	if (HAS_GMCH_DISPLAY(dev)) {
4792
		intel_set_memory_cxsr(dev_priv, false);
4793
		dev_priv->wm.vlv.cxsr = false;
4794
		intel_wait_for_vblank(dev, pipe);
4795
	}
5060 serge 4796
 
6084 serge 4797
	/*
4798
	 * FIXME IPS should be fine as long as one plane is
4799
	 * enabled, but in practice it seems to have problems
4800
	 * when going from primary only to sprite only and vice
4801
	 * versa.
4802
	 */
5060 serge 4803
	hsw_disable_ips(intel_crtc);
6084 serge 4804
}
5060 serge 4805
 
6084 serge 4806
static void intel_post_plane_update(struct intel_crtc *crtc)
4807
{
4808
	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4809
	struct drm_device *dev = crtc->base.dev;
4810
	struct drm_i915_private *dev_priv = dev->dev_private;
4811
	struct drm_plane *plane;
5354 serge 4812
 
6084 serge 4813
	if (atomic->wait_vblank)
4814
		intel_wait_for_vblank(dev, crtc->pipe);
4815
 
4816
	intel_frontbuffer_flip(dev, atomic->fb_bits);
4817
 
4818
	if (atomic->disable_cxsr)
4819
		crtc->wm.cxsr_allowed = true;
4820
 
4821
	if (crtc->atomic.update_wm_post)
4822
		intel_update_watermarks(&crtc->base);
4823
 
4824
	if (atomic->update_fbc)
4825
		intel_fbc_update(dev_priv);
4826
 
4827
	if (atomic->post_enable_primary)
4828
		intel_post_enable_primary(&crtc->base);
4829
 
4830
	drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4831
		intel_update_sprite_watermarks(plane, &crtc->base,
4832
					       0, 0, 0, false, false);
4833
 
4834
	memset(atomic, 0, sizeof(*atomic));
4835
}
4836
 
4837
static void intel_pre_plane_update(struct intel_crtc *crtc)
4838
{
4839
	struct drm_device *dev = crtc->base.dev;
4840
	struct drm_i915_private *dev_priv = dev->dev_private;
4841
	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4842
	struct drm_plane *p;
4843
 
4844
	/* Track fb's for any planes being disabled */
4845
	drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4846
		struct intel_plane *plane = to_intel_plane(p);
4847
 
4848
		mutex_lock(&dev->struct_mutex);
4849
		i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4850
				  plane->frontbuffer_bit);
4851
		mutex_unlock(&dev->struct_mutex);
4852
	}
4853
 
4854
	if (atomic->disable_fbc)
4855
		intel_fbc_disable_crtc(crtc);
4856
 
4857
	if (crtc->atomic.disable_ips)
4858
		hsw_disable_ips(crtc);
4859
 
4860
	if (atomic->pre_disable_primary)
4861
		intel_pre_disable_primary(&crtc->base);
4862
 
4863
	if (atomic->disable_cxsr) {
4864
		crtc->wm.cxsr_allowed = false;
4865
		intel_set_memory_cxsr(dev_priv, false);
4866
	}
4867
}
4868
 
4869
static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4870
{
4871
	struct drm_device *dev = crtc->dev;
4872
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873
	struct drm_plane *p;
4874
	int pipe = intel_crtc->pipe;
4875
 
4876
	intel_crtc_dpms_overlay_disable(intel_crtc);
4877
 
4878
	drm_for_each_plane_mask(p, dev, plane_mask)
4879
		to_intel_plane(p)->disable_plane(p, crtc);
4880
 
5354 serge 4881
	/*
4882
	 * FIXME: Once we grow proper nuclear flip support out of this we need
4883
	 * to compute the mask of flip planes precisely. For the time being
4884
	 * consider this a flip to a NULL plane.
4885
	 */
4886
//	intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
5060 serge 4887
}
4888
 
2327 Serge 4889
static void ironlake_crtc_enable(struct drm_crtc *crtc)
4890
{
6084 serge 4891
	struct drm_device *dev = crtc->dev;
4892
	struct drm_i915_private *dev_priv = dev->dev_private;
4893
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 serge 4894
	struct intel_encoder *encoder;
6084 serge 4895
	int pipe = intel_crtc->pipe;
2327 Serge 4896
 
6084 serge 4897
	if (WARN_ON(intel_crtc->active))
4898
		return;
3031 serge 4899
 
6084 serge 4900
	if (intel_crtc->config->has_pch_encoder)
5060 serge 4901
		intel_prepare_shared_dpll(intel_crtc);
4902
 
6084 serge 4903
	if (intel_crtc->config->has_dp_encoder)
4904
		intel_dp_set_m_n(intel_crtc, M1_N1);
5060 serge 4905
 
4906
	intel_set_pipe_timings(intel_crtc);
4907
 
6084 serge 4908
	if (intel_crtc->config->has_pch_encoder) {
5060 serge 4909
		intel_cpu_transcoder_set_m_n(intel_crtc,
6084 serge 4910
				     &intel_crtc->config->fdi_m_n, NULL);
5060 serge 4911
	}
4912
 
4913
	ironlake_set_pipeconf(crtc);
4914
 
6084 serge 4915
	intel_crtc->active = true;
4104 Serge 4916
 
5354 serge 4917
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4918
	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4104 Serge 4919
 
4920
	for_each_encoder_on_crtc(dev, crtc, encoder)
4921
		if (encoder->pre_enable)
4922
			encoder->pre_enable(encoder);
2327 Serge 4923
 
6084 serge 4924
	if (intel_crtc->config->has_pch_encoder) {
3243 Serge 4925
		/* Note: FDI PLL enabling _must_ be done before we enable the
4926
		 * cpu pipes, hence this is separate from all the other fdi/pch
4927
		 * enabling. */
3031 serge 4928
		ironlake_fdi_pll_enable(intel_crtc);
4929
	} else {
4930
		assert_fdi_tx_disabled(dev_priv, pipe);
4931
		assert_fdi_rx_disabled(dev_priv, pipe);
4932
	}
2327 Serge 4933
 
4104 Serge 4934
	ironlake_pfit_enable(intel_crtc);
3031 serge 4935
 
6084 serge 4936
	/*
4937
	 * On ILK+ LUT must be loaded before the pipe is running but with
4938
	 * clocks enabled
4939
	 */
4940
	intel_crtc_load_lut(crtc);
2327 Serge 4941
 
4560 Serge 4942
	intel_update_watermarks(crtc);
5060 serge 4943
	intel_enable_pipe(intel_crtc);
2327 Serge 4944
 
6084 serge 4945
	if (intel_crtc->config->has_pch_encoder)
4946
		ironlake_pch_enable(crtc);
2327 Serge 4947
 
6084 serge 4948
	assert_vblank_disabled(crtc);
4949
	drm_crtc_vblank_on(crtc);
4950
 
3031 serge 4951
	for_each_encoder_on_crtc(dev, crtc, encoder)
4952
		encoder->enable(encoder);
4953
 
4954
	if (HAS_PCH_CPT(dev))
4104 Serge 4955
		cpt_verify_modeset(dev, intel_crtc->pipe);
2327 Serge 4956
}
4957
 
4104 Serge 4958
/* IPS only exists on ULT machines and is tied to pipe A. */
4959
static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4960
{
4961
	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4962
}
4963
 
3243 Serge 4964
static void haswell_crtc_enable(struct drm_crtc *crtc)
4965
{
4966
	struct drm_device *dev = crtc->dev;
4967
	struct drm_i915_private *dev_priv = dev->dev_private;
4968
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969
	struct intel_encoder *encoder;
6084 serge 4970
	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4971
	struct intel_crtc_state *pipe_config =
4972
		to_intel_crtc_state(crtc->state);
4973
	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
3243 Serge 4974
 
6084 serge 4975
	if (WARN_ON(intel_crtc->active))
3243 Serge 4976
		return;
4977
 
5060 serge 4978
	if (intel_crtc_to_shared_dpll(intel_crtc))
4979
		intel_enable_shared_dpll(intel_crtc);
4980
 
6084 serge 4981
	if (intel_crtc->config->has_dp_encoder)
4982
		intel_dp_set_m_n(intel_crtc, M1_N1);
5060 serge 4983
 
4984
	intel_set_pipe_timings(intel_crtc);
4985
 
6084 serge 4986
	if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4987
		I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4988
			   intel_crtc->config->pixel_multiplier - 1);
5354 serge 4989
	}
4990
 
6084 serge 4991
	if (intel_crtc->config->has_pch_encoder) {
5060 serge 4992
		intel_cpu_transcoder_set_m_n(intel_crtc,
6084 serge 4993
				     &intel_crtc->config->fdi_m_n, NULL);
5060 serge 4994
	}
4995
 
4996
	haswell_set_pipeconf(crtc);
4997
 
4998
	intel_set_pipe_csc(crtc);
4999
 
3243 Serge 5000
	intel_crtc->active = true;
4104 Serge 5001
 
5354 serge 5002
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6084 serge 5003
	for_each_encoder_on_crtc(dev, crtc, encoder) {
5004
		if (encoder->pre_pll_enable)
5005
			encoder->pre_pll_enable(encoder);
3243 Serge 5006
		if (encoder->pre_enable)
5007
			encoder->pre_enable(encoder);
6084 serge 5008
	}
3243 Serge 5009
 
6084 serge 5010
	if (intel_crtc->config->has_pch_encoder) {
5354 serge 5011
		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5012
						      true);
5060 serge 5013
		dev_priv->display.fdi_link_train(crtc);
5014
	}
5015
 
6084 serge 5016
	if (!is_dsi)
5017
		intel_ddi_enable_pipe_clock(intel_crtc);
3243 Serge 5018
 
6084 serge 5019
	if (INTEL_INFO(dev)->gen >= 9)
5354 serge 5020
		skylake_pfit_enable(intel_crtc);
5021
	else
6084 serge 5022
		ironlake_pfit_enable(intel_crtc);
3243 Serge 5023
 
5024
	/*
5025
	 * On ILK+ LUT must be loaded before the pipe is running but with
5026
	 * clocks enabled
5027
	 */
5028
	intel_crtc_load_lut(crtc);
5029
 
5030
	intel_ddi_set_pipe_settings(crtc);
6084 serge 5031
	if (!is_dsi)
5032
		intel_ddi_enable_transcoder_func(crtc);
3243 Serge 5033
 
4560 Serge 5034
	intel_update_watermarks(crtc);
5060 serge 5035
	intel_enable_pipe(intel_crtc);
3243 Serge 5036
 
6084 serge 5037
	if (intel_crtc->config->has_pch_encoder)
3243 Serge 5038
		lpt_pch_enable(crtc);
5039
 
6084 serge 5040
	if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5060 serge 5041
		intel_ddi_set_vc_payload_alloc(crtc, true);
5042
 
6084 serge 5043
	assert_vblank_disabled(crtc);
5044
	drm_crtc_vblank_on(crtc);
5045
 
4560 Serge 5046
	for_each_encoder_on_crtc(dev, crtc, encoder) {
3243 Serge 5047
		encoder->enable(encoder);
4560 Serge 5048
		intel_opregion_notify_encoder(encoder, true);
5049
	}
3243 Serge 5050
 
4560 Serge 5051
	/* If we change the relative order between pipe/planes enabling, we need
5052
	 * to change the workaround. */
6084 serge 5053
	hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5054
	if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5055
		intel_wait_for_vblank(dev, hsw_workaround_pipe);
5056
		intel_wait_for_vblank(dev, hsw_workaround_pipe);
5354 serge 5057
	}
5058
}
5059
 
6084 serge 5060
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4104 Serge 5061
{
5062
	struct drm_device *dev = crtc->base.dev;
5063
	struct drm_i915_private *dev_priv = dev->dev_private;
5064
	int pipe = crtc->pipe;
5065
 
5066
	/* To avoid upsetting the power well on haswell only disable the pfit if
5067
	 * it's in use. The hw state code will make sure we get this right. */
6084 serge 5068
	if (force || crtc->config->pch_pfit.enabled) {
4104 Serge 5069
		I915_WRITE(PF_CTL(pipe), 0);
5070
		I915_WRITE(PF_WIN_POS(pipe), 0);
5071
		I915_WRITE(PF_WIN_SZ(pipe), 0);
5072
	}
5073
}
5074
 
2327 Serge 5075
static void ironlake_crtc_disable(struct drm_crtc *crtc)
5076
{
6084 serge 5077
	struct drm_device *dev = crtc->dev;
5078
	struct drm_i915_private *dev_priv = dev->dev_private;
5079
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 serge 5080
	struct intel_encoder *encoder;
6084 serge 5081
	int pipe = intel_crtc->pipe;
5082
	u32 reg, temp;
2327 Serge 5083
 
6084 serge 5084
	for_each_encoder_on_crtc(dev, crtc, encoder)
5085
		encoder->disable(encoder);
2327 Serge 5086
 
5354 serge 5087
	drm_crtc_vblank_off(crtc);
5088
	assert_vblank_disabled(crtc);
5089
 
6084 serge 5090
	if (intel_crtc->config->has_pch_encoder)
5354 serge 5091
		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
2327 Serge 5092
 
5354 serge 5093
	intel_disable_pipe(intel_crtc);
5094
 
6084 serge 5095
	ironlake_pfit_disable(intel_crtc, false);
2327 Serge 5096
 
6084 serge 5097
	if (intel_crtc->config->has_pch_encoder)
5098
		ironlake_fdi_disable(crtc);
5099
 
3031 serge 5100
	for_each_encoder_on_crtc(dev, crtc, encoder)
5101
		if (encoder->post_disable)
5102
			encoder->post_disable(encoder);
5103
 
6084 serge 5104
	if (intel_crtc->config->has_pch_encoder) {
5105
		ironlake_disable_pch_transcoder(dev_priv, pipe);
2327 Serge 5106
 
6084 serge 5107
		if (HAS_PCH_CPT(dev)) {
5108
			/* disable TRANS_DP_CTL */
5109
			reg = TRANS_DP_CTL(pipe);
5110
			temp = I915_READ(reg);
4104 Serge 5111
			temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5112
				  TRANS_DP_PORT_SEL_MASK);
6084 serge 5113
			temp |= TRANS_DP_PORT_SEL_NONE;
5114
			I915_WRITE(reg, temp);
2327 Serge 5115
 
6084 serge 5116
			/* disable DPLL_SEL */
5117
			temp = I915_READ(PCH_DPLL_SEL);
4104 Serge 5118
			temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6084 serge 5119
			I915_WRITE(PCH_DPLL_SEL, temp);
5120
		}
2327 Serge 5121
 
6084 serge 5122
		ironlake_fdi_pll_disable(intel_crtc);
4104 Serge 5123
	}
2327 Serge 5124
}
5125
 
3243 Serge 5126
static void haswell_crtc_disable(struct drm_crtc *crtc)
5127
{
5128
	struct drm_device *dev = crtc->dev;
5129
	struct drm_i915_private *dev_priv = dev->dev_private;
5130
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5131
	struct intel_encoder *encoder;
6084 serge 5132
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5133
	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
3243 Serge 5134
 
4560 Serge 5135
	for_each_encoder_on_crtc(dev, crtc, encoder) {
5136
		intel_opregion_notify_encoder(encoder, false);
3243 Serge 5137
		encoder->disable(encoder);
4560 Serge 5138
	}
3243 Serge 5139
 
6084 serge 5140
	drm_crtc_vblank_off(crtc);
5141
	assert_vblank_disabled(crtc);
5142
 
5143
	if (intel_crtc->config->has_pch_encoder)
5354 serge 5144
		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5145
						      false);
5146
	intel_disable_pipe(intel_crtc);
3243 Serge 5147
 
6084 serge 5148
	if (intel_crtc->config->dp_encoder_is_mst)
5097 serge 5149
		intel_ddi_set_vc_payload_alloc(crtc, false);
5150
 
6084 serge 5151
	if (!is_dsi)
5152
		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3243 Serge 5153
 
6084 serge 5154
	if (INTEL_INFO(dev)->gen >= 9)
5155
		skylake_scaler_disable(intel_crtc);
5354 serge 5156
	else
6084 serge 5157
		ironlake_pfit_disable(intel_crtc, false);
3243 Serge 5158
 
6084 serge 5159
	if (!is_dsi)
5160
		intel_ddi_disable_pipe_clock(intel_crtc);
3243 Serge 5161
 
6084 serge 5162
	if (intel_crtc->config->has_pch_encoder) {
3243 Serge 5163
		lpt_disable_pch_transcoder(dev_priv);
5164
		intel_ddi_fdi_disable(crtc);
5165
	}
5166
 
5060 serge 5167
	for_each_encoder_on_crtc(dev, crtc, encoder)
5168
		if (encoder->post_disable)
5169
			encoder->post_disable(encoder);
3243 Serge 5170
}
5171
 
4104 Serge 5172
static void i9xx_pfit_enable(struct intel_crtc *crtc)
5173
{
5174
	struct drm_device *dev = crtc->base.dev;
5175
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 5176
	struct intel_crtc_state *pipe_config = crtc->config;
4104 Serge 5177
 
6084 serge 5178
	if (!pipe_config->gmch_pfit.control)
4104 Serge 5179
		return;
5180
 
5181
	/*
5182
	 * The panel fitter should only be adjusted whilst the pipe is disabled,
5183
	 * according to register description and PRM.
5184
	 */
5185
	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5186
	assert_pipe_disabled(dev_priv, crtc->pipe);
5187
 
5188
	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5189
	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5190
 
5191
	/* Border color in case we don't scale up to the full screen. Black by
5192
	 * default, change to something else for debugging. */
5193
	I915_WRITE(BCLRPAT(crtc->pipe), 0);
5194
}
5195
 
5060 serge 5196
static enum intel_display_power_domain port_to_power_domain(enum port port)
4560 Serge 5197
{
5060 serge 5198
	switch (port) {
5199
	case PORT_A:
5200
		return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5201
	case PORT_B:
5202
		return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5203
	case PORT_C:
5204
		return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5205
	case PORT_D:
5206
		return POWER_DOMAIN_PORT_DDI_D_4_LANES;
6084 serge 5207
	case PORT_E:
5208
		return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5060 serge 5209
	default:
6084 serge 5210
		MISSING_CASE(port);
5060 serge 5211
		return POWER_DOMAIN_PORT_OTHER;
5212
	}
5213
}
5214
 
6084 serge 5215
static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5216
{
5217
	switch (port) {
5218
	case PORT_A:
5219
		return POWER_DOMAIN_AUX_A;
5220
	case PORT_B:
5221
		return POWER_DOMAIN_AUX_B;
5222
	case PORT_C:
5223
		return POWER_DOMAIN_AUX_C;
5224
	case PORT_D:
5225
		return POWER_DOMAIN_AUX_D;
5226
	case PORT_E:
5227
		/* FIXME: Check VBT for actual wiring of PORT E */
5228
		return POWER_DOMAIN_AUX_D;
5229
	default:
5230
		MISSING_CASE(port);
5231
		return POWER_DOMAIN_AUX_A;
5232
	}
5233
}
5234
 
5060 serge 5235
#define for_each_power_domain(domain, mask)				\
5236
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
5237
		if ((1 << (domain)) & (mask))
5238
 
5239
enum intel_display_power_domain
5240
intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5241
{
5242
	struct drm_device *dev = intel_encoder->base.dev;
5243
	struct intel_digital_port *intel_dig_port;
5244
 
5245
	switch (intel_encoder->type) {
5246
	case INTEL_OUTPUT_UNKNOWN:
5247
		/* Only DDI platforms should ever use this output type */
5248
		WARN_ON_ONCE(!HAS_DDI(dev));
5249
	case INTEL_OUTPUT_DISPLAYPORT:
5250
	case INTEL_OUTPUT_HDMI:
5251
	case INTEL_OUTPUT_EDP:
5252
		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5253
		return port_to_power_domain(intel_dig_port->port);
5254
	case INTEL_OUTPUT_DP_MST:
5255
		intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5256
		return port_to_power_domain(intel_dig_port->port);
5257
	case INTEL_OUTPUT_ANALOG:
5258
		return POWER_DOMAIN_PORT_CRT;
5259
	case INTEL_OUTPUT_DSI:
5260
		return POWER_DOMAIN_PORT_DSI;
5261
	default:
5262
		return POWER_DOMAIN_PORT_OTHER;
5263
	}
5264
}
5265
 
6084 serge 5266
enum intel_display_power_domain
5267
intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5268
{
5269
	struct drm_device *dev = intel_encoder->base.dev;
5270
	struct intel_digital_port *intel_dig_port;
5271
 
5272
	switch (intel_encoder->type) {
5273
	case INTEL_OUTPUT_UNKNOWN:
5274
	case INTEL_OUTPUT_HDMI:
5275
		/*
5276
		 * Only DDI platforms should ever use these output types.
5277
		 * We can get here after the HDMI detect code has already set
5278
		 * the type of the shared encoder. Since we can't be sure
5279
		 * what's the status of the given connectors, play safe and
5280
		 * run the DP detection too.
5281
		 */
5282
		WARN_ON_ONCE(!HAS_DDI(dev));
5283
	case INTEL_OUTPUT_DISPLAYPORT:
5284
	case INTEL_OUTPUT_EDP:
5285
		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5286
		return port_to_aux_power_domain(intel_dig_port->port);
5287
	case INTEL_OUTPUT_DP_MST:
5288
		intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5289
		return port_to_aux_power_domain(intel_dig_port->port);
5290
	default:
5291
		MISSING_CASE(intel_encoder->type);
5292
		return POWER_DOMAIN_AUX_A;
5293
	}
5294
}
5295
 
5060 serge 5296
static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5297
{
5298
	struct drm_device *dev = crtc->dev;
5299
	struct intel_encoder *intel_encoder;
5300
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5301
	enum pipe pipe = intel_crtc->pipe;
5302
	unsigned long mask;
5303
	enum transcoder transcoder;
5304
 
6084 serge 5305
	if (!crtc->state->active)
5306
		return 0;
5307
 
5060 serge 5308
	transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5309
 
5310
	mask = BIT(POWER_DOMAIN_PIPE(pipe));
5311
	mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6084 serge 5312
	if (intel_crtc->config->pch_pfit.enabled ||
5313
	    intel_crtc->config->pch_pfit.force_thru)
5060 serge 5314
		mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5315
 
5316
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5317
		mask |= BIT(intel_display_port_power_domain(intel_encoder));
5318
 
5319
	return mask;
5320
}
5321
 
6084 serge 5322
static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5060 serge 5323
{
6084 serge 5324
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5325
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5326
	enum intel_display_power_domain domain;
5327
	unsigned long domains, new_domains, old_domains;
5060 serge 5328
 
6084 serge 5329
	old_domains = intel_crtc->enabled_power_domains;
5330
	intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5060 serge 5331
 
6084 serge 5332
	domains = new_domains & ~old_domains;
5060 serge 5333
 
6084 serge 5334
	for_each_power_domain(domain, domains)
5335
		intel_display_power_get(dev_priv, domain);
5060 serge 5336
 
6084 serge 5337
	return old_domains & ~new_domains;
5338
}
5060 serge 5339
 
6084 serge 5340
static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5341
				      unsigned long domains)
5342
{
5343
	enum intel_display_power_domain domain;
5354 serge 5344
 
6084 serge 5345
	for_each_power_domain(domain, domains)
5346
		intel_display_power_put(dev_priv, domain);
5347
}
5060 serge 5348
 
6084 serge 5349
static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5350
{
5351
	struct drm_device *dev = state->dev;
5352
	struct drm_i915_private *dev_priv = dev->dev_private;
5353
	unsigned long put_domains[I915_MAX_PIPES] = {};
5354
	struct drm_crtc_state *crtc_state;
5355
	struct drm_crtc *crtc;
5356
	int i;
5060 serge 5357
 
6084 serge 5358
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
5359
		if (needs_modeset(crtc->state))
5360
			put_domains[to_intel_crtc(crtc)->pipe] =
5361
				modeset_get_crtc_power_domains(crtc);
5060 serge 5362
	}
5363
 
6084 serge 5364
	if (dev_priv->display.modeset_commit_cdclk) {
5365
		unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5366
 
5367
		if (cdclk != dev_priv->cdclk_freq &&
5368
		    !WARN_ON(!state->allow_modeset))
5369
			dev_priv->display.modeset_commit_cdclk(state);
5370
	}
5371
 
5372
	for (i = 0; i < I915_MAX_PIPES; i++)
5373
		if (put_domains[i])
5374
			modeset_put_power_domains(dev_priv, put_domains[i]);
5060 serge 5375
}
5376
 
6084 serge 5377
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5060 serge 5378
{
6084 serge 5379
	int max_cdclk_freq = dev_priv->max_cdclk_freq;
4560 Serge 5380
 
6084 serge 5381
	if (INTEL_INFO(dev_priv)->gen >= 9 ||
5382
	    IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5383
		return max_cdclk_freq;
5384
	else if (IS_CHERRYVIEW(dev_priv))
5385
		return max_cdclk_freq*95/100;
5386
	else if (INTEL_INFO(dev_priv)->gen < 4)
5387
		return 2*max_cdclk_freq*90/100;
5388
	else
5389
		return max_cdclk_freq*90/100;
5390
}
4560 Serge 5391
 
6084 serge 5392
static void intel_update_max_cdclk(struct drm_device *dev)
5393
{
5394
	struct drm_i915_private *dev_priv = dev->dev_private;
5395
 
5396
	if (IS_SKYLAKE(dev)) {
5397
		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5398
 
5399
		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5400
			dev_priv->max_cdclk_freq = 675000;
5401
		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5402
			dev_priv->max_cdclk_freq = 540000;
5403
		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5404
			dev_priv->max_cdclk_freq = 450000;
5405
		else
5406
			dev_priv->max_cdclk_freq = 337500;
5407
	} else if (IS_BROADWELL(dev))  {
5408
		/*
5409
		 * FIXME with extra cooling we can allow
5410
		 * 540 MHz for ULX and 675 Mhz for ULT.
5411
		 * How can we know if extra cooling is
5412
		 * available? PCI ID, VTB, something else?
5413
		 */
5414
		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5415
			dev_priv->max_cdclk_freq = 450000;
5416
		else if (IS_BDW_ULX(dev))
5417
			dev_priv->max_cdclk_freq = 450000;
5418
		else if (IS_BDW_ULT(dev))
5419
			dev_priv->max_cdclk_freq = 540000;
5420
		else
5421
			dev_priv->max_cdclk_freq = 675000;
5422
	} else if (IS_CHERRYVIEW(dev)) {
5423
		dev_priv->max_cdclk_freq = 320000;
5424
	} else if (IS_VALLEYVIEW(dev)) {
5425
		dev_priv->max_cdclk_freq = 400000;
5426
	} else {
5427
		/* otherwise assume cdclk is fixed */
5428
		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5429
	}
5430
 
5431
	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5432
 
5433
	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5434
			 dev_priv->max_cdclk_freq);
5435
 
5436
	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5437
			 dev_priv->max_dotclk_freq);
4560 Serge 5438
}
5439
 
6084 serge 5440
static void intel_update_cdclk(struct drm_device *dev)
5060 serge 5441
{
5442
	struct drm_i915_private *dev_priv = dev->dev_private;
5443
 
6084 serge 5444
	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5354 serge 5445
	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
6084 serge 5446
			 dev_priv->cdclk_freq);
5060 serge 5447
 
5448
	/*
5449
	 * Program the gmbus_freq based on the cdclk frequency.
5450
	 * BSpec erroneously claims we should aim for 4MHz, but
5451
	 * in fact 1MHz is the correct frequency.
5452
	 */
6084 serge 5453
	if (IS_VALLEYVIEW(dev)) {
5454
		/*
5455
		 * Program the gmbus_freq based on the cdclk frequency.
5456
		 * BSpec erroneously claims we should aim for 4MHz, but
5457
		 * in fact 1MHz is the correct frequency.
5458
		 */
5459
		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5460
	}
5461
 
5462
	if (dev_priv->max_cdclk_freq == 0)
5463
		intel_update_max_cdclk(dev);
5060 serge 5464
}
5465
 
6084 serge 5466
static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5467
{
5468
	struct drm_i915_private *dev_priv = dev->dev_private;
5469
	uint32_t divider;
5470
	uint32_t ratio;
5471
	uint32_t current_freq;
5472
	int ret;
5473
 
5474
	/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5475
	switch (frequency) {
5476
	case 144000:
5477
		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5478
		ratio = BXT_DE_PLL_RATIO(60);
5479
		break;
5480
	case 288000:
5481
		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5482
		ratio = BXT_DE_PLL_RATIO(60);
5483
		break;
5484
	case 384000:
5485
		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5486
		ratio = BXT_DE_PLL_RATIO(60);
5487
		break;
5488
	case 576000:
5489
		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5490
		ratio = BXT_DE_PLL_RATIO(60);
5491
		break;
5492
	case 624000:
5493
		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5494
		ratio = BXT_DE_PLL_RATIO(65);
5495
		break;
5496
	case 19200:
5497
		/*
5498
		 * Bypass frequency with DE PLL disabled. Init ratio, divider
5499
		 * to suppress GCC warning.
5500
		 */
5501
		ratio = 0;
5502
		divider = 0;
5503
		break;
5504
	default:
5505
		DRM_ERROR("unsupported CDCLK freq %d", frequency);
5506
 
5507
		return;
5508
	}
5509
 
5510
	mutex_lock(&dev_priv->rps.hw_lock);
5511
	/* Inform power controller of upcoming frequency change */
5512
	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5513
				      0x80000000);
5514
	mutex_unlock(&dev_priv->rps.hw_lock);
5515
 
5516
	if (ret) {
5517
		DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5518
			  ret, frequency);
5519
		return;
5520
	}
5521
 
5522
	current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5523
	/* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5524
	current_freq = current_freq * 500 + 1000;
5525
 
5526
	/*
5527
	 * DE PLL has to be disabled when
5528
	 * - setting to 19.2MHz (bypass, PLL isn't used)
5529
	 * - before setting to 624MHz (PLL needs toggling)
5530
	 * - before setting to any frequency from 624MHz (PLL needs toggling)
5531
	 */
5532
	if (frequency == 19200 || frequency == 624000 ||
5533
	    current_freq == 624000) {
5534
		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5535
		/* Timeout 200us */
5536
		if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5537
			     1))
5538
			DRM_ERROR("timout waiting for DE PLL unlock\n");
5539
	}
5540
 
5541
	if (frequency != 19200) {
5542
		uint32_t val;
5543
 
5544
		val = I915_READ(BXT_DE_PLL_CTL);
5545
		val &= ~BXT_DE_PLL_RATIO_MASK;
5546
		val |= ratio;
5547
		I915_WRITE(BXT_DE_PLL_CTL, val);
5548
 
5549
		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5550
		/* Timeout 200us */
5551
		if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5552
			DRM_ERROR("timeout waiting for DE PLL lock\n");
5553
 
5554
		val = I915_READ(CDCLK_CTL);
5555
		val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5556
		val |= divider;
5557
		/*
5558
		 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5559
		 * enable otherwise.
5560
		 */
5561
		val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5562
		if (frequency >= 500000)
5563
			val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5564
 
5565
		val &= ~CDCLK_FREQ_DECIMAL_MASK;
5566
		/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5567
		val |= (frequency - 1000) / 500;
5568
		I915_WRITE(CDCLK_CTL, val);
5569
	}
5570
 
5571
	mutex_lock(&dev_priv->rps.hw_lock);
5572
	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5573
				      DIV_ROUND_UP(frequency, 25000));
5574
	mutex_unlock(&dev_priv->rps.hw_lock);
5575
 
5576
	if (ret) {
5577
		DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5578
			  ret, frequency);
5579
		return;
5580
	}
5581
 
5582
	intel_update_cdclk(dev);
5583
}
5584
 
5585
void broxton_init_cdclk(struct drm_device *dev)
5586
{
5587
	struct drm_i915_private *dev_priv = dev->dev_private;
5588
	uint32_t val;
5589
 
5590
	/*
5591
	 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5592
	 * or else the reset will hang because there is no PCH to respond.
5593
	 * Move the handshake programming to initialization sequence.
5594
	 * Previously was left up to BIOS.
5595
	 */
5596
	val = I915_READ(HSW_NDE_RSTWRN_OPT);
5597
	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5598
	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5599
 
5600
	/* Enable PG1 for cdclk */
5601
	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5602
 
5603
	/* check if cd clock is enabled */
5604
	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5605
		DRM_DEBUG_KMS("Display already initialized\n");
5606
		return;
5607
	}
5608
 
5609
	/*
5610
	 * FIXME:
5611
	 * - The initial CDCLK needs to be read from VBT.
5612
	 *   Need to make this change after VBT has changes for BXT.
5613
	 * - check if setting the max (or any) cdclk freq is really necessary
5614
	 *   here, it belongs to modeset time
5615
	 */
5616
	broxton_set_cdclk(dev, 624000);
5617
 
5618
	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5619
	POSTING_READ(DBUF_CTL);
5620
 
5621
	udelay(10);
5622
 
5623
	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5624
		DRM_ERROR("DBuf power enable timeout!\n");
5625
}
5626
 
5627
void broxton_uninit_cdclk(struct drm_device *dev)
5628
{
5629
	struct drm_i915_private *dev_priv = dev->dev_private;
5630
 
5631
	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5632
	POSTING_READ(DBUF_CTL);
5633
 
5634
	udelay(10);
5635
 
5636
	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5637
		DRM_ERROR("DBuf power disable timeout!\n");
5638
 
5639
	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5640
	broxton_set_cdclk(dev, 19200);
5641
 
5642
	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5643
}
5644
 
5645
static const struct skl_cdclk_entry {
5646
	unsigned int freq;
5647
	unsigned int vco;
5648
} skl_cdclk_frequencies[] = {
5649
	{ .freq = 308570, .vco = 8640 },
5650
	{ .freq = 337500, .vco = 8100 },
5651
	{ .freq = 432000, .vco = 8640 },
5652
	{ .freq = 450000, .vco = 8100 },
5653
	{ .freq = 540000, .vco = 8100 },
5654
	{ .freq = 617140, .vco = 8640 },
5655
	{ .freq = 675000, .vco = 8100 },
5656
};
5657
 
5658
static unsigned int skl_cdclk_decimal(unsigned int freq)
5659
{
5660
	return (freq - 1000) / 500;
5661
}
5662
 
5663
static unsigned int skl_cdclk_get_vco(unsigned int freq)
5664
{
5665
	unsigned int i;
5666
 
5667
	for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5668
		const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5669
 
5670
		if (e->freq == freq)
5671
			return e->vco;
5672
	}
5673
 
5674
	return 8100;
5675
}
5676
 
5677
static void
5678
skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5679
{
5680
	unsigned int min_freq;
5681
	u32 val;
5682
 
5683
	/* select the minimum CDCLK before enabling DPLL 0 */
5684
	val = I915_READ(CDCLK_CTL);
5685
	val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5686
	val |= CDCLK_FREQ_337_308;
5687
 
5688
	if (required_vco == 8640)
5689
		min_freq = 308570;
5690
	else
5691
		min_freq = 337500;
5692
 
5693
	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5694
 
5695
	I915_WRITE(CDCLK_CTL, val);
5696
	POSTING_READ(CDCLK_CTL);
5697
 
5698
	/*
5699
	 * We always enable DPLL0 with the lowest link rate possible, but still
5700
	 * taking into account the VCO required to operate the eDP panel at the
5701
	 * desired frequency. The usual DP link rates operate with a VCO of
5702
	 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5703
	 * The modeset code is responsible for the selection of the exact link
5704
	 * rate later on, with the constraint of choosing a frequency that
5705
	 * works with required_vco.
5706
	 */
5707
	val = I915_READ(DPLL_CTRL1);
5708
 
5709
	val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5710
		 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5711
	val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5712
	if (required_vco == 8640)
5713
		val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5714
					    SKL_DPLL0);
5715
	else
5716
		val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5717
					    SKL_DPLL0);
5718
 
5719
	I915_WRITE(DPLL_CTRL1, val);
5720
	POSTING_READ(DPLL_CTRL1);
5721
 
5722
	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5723
 
5724
	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5725
		DRM_ERROR("DPLL0 not locked\n");
5726
}
5727
 
5728
static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5729
{
5730
	int ret;
5731
	u32 val;
5732
 
5733
	/* inform PCU we want to change CDCLK */
5734
	val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5735
	mutex_lock(&dev_priv->rps.hw_lock);
5736
	ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5737
	mutex_unlock(&dev_priv->rps.hw_lock);
5738
 
5739
	return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5740
}
5741
 
5742
static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5743
{
5744
	unsigned int i;
5745
 
5746
	for (i = 0; i < 15; i++) {
5747
		if (skl_cdclk_pcu_ready(dev_priv))
5748
			return true;
5749
		udelay(10);
5750
	}
5751
 
5752
	return false;
5753
}
5754
 
5755
static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5756
{
5757
	struct drm_device *dev = dev_priv->dev;
5758
	u32 freq_select, pcu_ack;
5759
 
5760
	DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5761
 
5762
	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5763
		DRM_ERROR("failed to inform PCU about cdclk change\n");
5764
		return;
5765
	}
5766
 
5767
	/* set CDCLK_CTL */
5768
	switch(freq) {
5769
	case 450000:
5770
	case 432000:
5771
		freq_select = CDCLK_FREQ_450_432;
5772
		pcu_ack = 1;
5773
		break;
5774
	case 540000:
5775
		freq_select = CDCLK_FREQ_540;
5776
		pcu_ack = 2;
5777
		break;
5778
	case 308570:
5779
	case 337500:
5780
	default:
5781
		freq_select = CDCLK_FREQ_337_308;
5782
		pcu_ack = 0;
5783
		break;
5784
	case 617140:
5785
	case 675000:
5786
		freq_select = CDCLK_FREQ_675_617;
5787
		pcu_ack = 3;
5788
		break;
5789
	}
5790
 
5791
	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5792
	POSTING_READ(CDCLK_CTL);
5793
 
5794
	/* inform PCU of the change */
5795
	mutex_lock(&dev_priv->rps.hw_lock);
5796
	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5797
	mutex_unlock(&dev_priv->rps.hw_lock);
5798
 
5799
	intel_update_cdclk(dev);
5800
}
5801
 
5802
void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5803
{
5804
	/* disable DBUF power */
5805
	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5806
	POSTING_READ(DBUF_CTL);
5807
 
5808
	udelay(10);
5809
 
5810
	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5811
		DRM_ERROR("DBuf power disable timeout\n");
5812
 
5813
	/*
5814
	 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5815
	 */
5816
	if (dev_priv->csr.dmc_payload) {
5817
		/* disable DPLL0 */
5818
		I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5819
					~LCPLL_PLL_ENABLE);
5820
		if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5821
			DRM_ERROR("Couldn't disable DPLL0\n");
5822
	}
5823
 
5824
	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5825
}
5826
 
5827
void skl_init_cdclk(struct drm_i915_private *dev_priv)
5828
{
5829
	u32 val;
5830
	unsigned int required_vco;
5831
 
5832
	/* enable PCH reset handshake */
5833
	val = I915_READ(HSW_NDE_RSTWRN_OPT);
5834
	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5835
 
5836
	/* enable PG1 and Misc I/O */
5837
	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5838
 
5839
	/* DPLL0 not enabled (happens on early BIOS versions) */
5840
	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5841
		/* enable DPLL0 */
5842
		required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5843
		skl_dpll0_enable(dev_priv, required_vco);
5844
	}
5845
 
5846
	/* set CDCLK to the frequency the BIOS chose */
5847
	skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5848
 
5849
	/* enable DBUF power */
5850
	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5851
	POSTING_READ(DBUF_CTL);
5852
 
5853
	udelay(10);
5854
 
5855
	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5856
		DRM_ERROR("DBuf power enable timeout\n");
5857
}
5858
 
4560 Serge 5859
/* Adjust CDclk dividers to allow high res or save power if possible */
5860
static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5861
{
5862
	struct drm_i915_private *dev_priv = dev->dev_private;
5863
	u32 val, cmd;
5864
 
6084 serge 5865
	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5866
					!= dev_priv->cdclk_freq);
5060 serge 5867
 
5868
	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4560 Serge 5869
		cmd = 2;
5060 serge 5870
	else if (cdclk == 266667)
4560 Serge 5871
		cmd = 1;
5872
	else
5873
		cmd = 0;
5874
 
5875
	mutex_lock(&dev_priv->rps.hw_lock);
5876
	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5877
	val &= ~DSPFREQGUAR_MASK;
5878
	val |= (cmd << DSPFREQGUAR_SHIFT);
5879
	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5880
	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5881
		      DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5882
		     50)) {
5883
		DRM_ERROR("timed out waiting for CDclk change\n");
5884
	}
5885
	mutex_unlock(&dev_priv->rps.hw_lock);
5886
 
6084 serge 5887
	mutex_lock(&dev_priv->sb_lock);
5888
 
5060 serge 5889
	if (cdclk == 400000) {
5354 serge 5890
		u32 divider;
4560 Serge 5891
 
5354 serge 5892
		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4560 Serge 5893
 
5894
		/* adjust cdclk divider */
5895
		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6084 serge 5896
		val &= ~CCK_FREQUENCY_VALUES;
4560 Serge 5897
		val |= divider;
5898
		vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5060 serge 5899
 
5900
		if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6084 serge 5901
			      CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5060 serge 5902
			     50))
5903
			DRM_ERROR("timed out waiting for CDclk change\n");
4560 Serge 5904
	}
5905
 
5906
	/* adjust self-refresh exit latency value */
5907
	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5908
	val &= ~0x7f;
5909
 
5910
	/*
5911
	 * For high bandwidth configs, we set a higher latency in the bunit
5912
	 * so that the core display fetch happens in time to avoid underruns.
5913
	 */
5060 serge 5914
	if (cdclk == 400000)
4560 Serge 5915
		val |= 4500 / 250; /* 4.5 usec */
5916
	else
5917
		val |= 3000 / 250; /* 3.0 usec */
5918
	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5919
 
6084 serge 5920
	mutex_unlock(&dev_priv->sb_lock);
5921
 
5922
	intel_update_cdclk(dev);
4560 Serge 5923
}
5924
 
5354 serge 5925
static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5926
{
5927
	struct drm_i915_private *dev_priv = dev->dev_private;
5928
	u32 val, cmd;
5929
 
6084 serge 5930
	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5931
						!= dev_priv->cdclk_freq);
5354 serge 5932
 
5933
	switch (cdclk) {
5934
	case 333333:
5935
	case 320000:
5936
	case 266667:
5937
	case 200000:
5938
		break;
5939
	default:
6084 serge 5940
		MISSING_CASE(cdclk);
5354 serge 5941
		return;
5942
	}
5943
 
6084 serge 5944
	/*
5945
	 * Specs are full of misinformation, but testing on actual
5946
	 * hardware has shown that we just need to write the desired
5947
	 * CCK divider into the Punit register.
5948
	 */
5949
	cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5950
 
5354 serge 5951
	mutex_lock(&dev_priv->rps.hw_lock);
5952
	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5953
	val &= ~DSPFREQGUAR_MASK_CHV;
5954
	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5955
	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5956
	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5957
		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5958
		     50)) {
5959
		DRM_ERROR("timed out waiting for CDclk change\n");
5960
	}
5961
	mutex_unlock(&dev_priv->rps.hw_lock);
5962
 
6084 serge 5963
	intel_update_cdclk(dev);
5354 serge 5964
}
5965
 
4560 Serge 5966
static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5967
				 int max_pixclk)
5968
{
5354 serge 5969
	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6084 serge 5970
	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
4560 Serge 5971
 
5972
	/*
5973
	 * Really only a few cases to deal with, as only 4 CDclks are supported:
5974
	 *   200MHz
5975
	 *   267MHz
5060 serge 5976
	 *   320/333MHz (depends on HPLL freq)
6084 serge 5977
	 *   400MHz (VLV only)
5978
	 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5979
	 * of the lower bin and adjust if needed.
5060 serge 5980
	 *
5981
	 * We seem to get an unstable or solid color picture at 200MHz.
5982
	 * Not sure what's wrong. For now use 200MHz only when all pipes
5983
	 * are off.
4560 Serge 5984
	 */
6084 serge 5985
	if (!IS_CHERRYVIEW(dev_priv) &&
5986
	    max_pixclk > freq_320*limit/100)
5060 serge 5987
		return 400000;
6084 serge 5988
	else if (max_pixclk > 266667*limit/100)
5060 serge 5989
		return freq_320;
5990
	else if (max_pixclk > 0)
5991
		return 266667;
5992
	else
5993
		return 200000;
4560 Serge 5994
}
5995
 
6084 serge 5996
static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5997
			      int max_pixclk)
4560 Serge 5998
{
6084 serge 5999
	/*
6000
	 * FIXME:
6001
	 * - remove the guardband, it's not needed on BXT
6002
	 * - set 19.2MHz bypass frequency if there are no active pipes
6003
	 */
6004
	if (max_pixclk > 576000*9/10)
6005
		return 624000;
6006
	else if (max_pixclk > 384000*9/10)
6007
		return 576000;
6008
	else if (max_pixclk > 288000*9/10)
6009
		return 384000;
6010
	else if (max_pixclk > 144000*9/10)
6011
		return 288000;
6012
	else
6013
		return 144000;
6014
}
6015
 
6016
/* Compute the max pixel clock for new configuration. Uses atomic state if
6017
 * that's non-NULL, look at current state otherwise. */
6018
static int intel_mode_max_pixclk(struct drm_device *dev,
6019
				 struct drm_atomic_state *state)
6020
{
4560 Serge 6021
	struct intel_crtc *intel_crtc;
6084 serge 6022
	struct intel_crtc_state *crtc_state;
4560 Serge 6023
	int max_pixclk = 0;
6024
 
5060 serge 6025
	for_each_intel_crtc(dev, intel_crtc) {
6084 serge 6026
		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6027
		if (IS_ERR(crtc_state))
6028
			return PTR_ERR(crtc_state);
6029
 
6030
		if (!crtc_state->base.enable)
6031
			continue;
6032
 
6033
		max_pixclk = max(max_pixclk,
6034
				 crtc_state->base.adjusted_mode.crtc_clock);
4560 Serge 6035
	}
6036
 
6037
	return max_pixclk;
6038
}
6039
 
6084 serge 6040
static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
4560 Serge 6041
{
6084 serge 6042
	struct drm_device *dev = state->dev;
4560 Serge 6043
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 6044
	int max_pixclk = intel_mode_max_pixclk(dev, state);
4560 Serge 6045
 
6084 serge 6046
	if (max_pixclk < 0)
6047
		return max_pixclk;
4560 Serge 6048
 
6084 serge 6049
	to_intel_atomic_state(state)->cdclk =
6050
		valleyview_calc_cdclk(dev_priv, max_pixclk);
6051
 
6052
	return 0;
4560 Serge 6053
}
6054
 
6084 serge 6055
static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
4560 Serge 6056
{
6084 serge 6057
	struct drm_device *dev = state->dev;
4560 Serge 6058
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 6059
	int max_pixclk = intel_mode_max_pixclk(dev, state);
4560 Serge 6060
 
6084 serge 6061
	if (max_pixclk < 0)
6062
		return max_pixclk;
5354 serge 6063
 
6084 serge 6064
	to_intel_atomic_state(state)->cdclk =
6065
		broxton_calc_cdclk(dev_priv, max_pixclk);
6066
 
6067
	return 0;
6068
}
6069
 
6070
static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6071
{
6072
	unsigned int credits, default_credits;
6073
 
6074
	if (IS_CHERRYVIEW(dev_priv))
6075
		default_credits = PFI_CREDIT(12);
6076
	else
6077
		default_credits = PFI_CREDIT(8);
6078
 
6079
	if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6080
		/* CHV suggested value is 31 or 63 */
6081
		if (IS_CHERRYVIEW(dev_priv))
6082
			credits = PFI_CREDIT_63;
5354 serge 6083
		else
6084 serge 6084
			credits = PFI_CREDIT(15);
6085
	} else {
6086
		credits = default_credits;
6087
	}
6088
 
6089
	/*
6090
	 * WA - write default credits before re-programming
6091
	 * FIXME: should we also set the resend bit here?
6092
	 */
6093
	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6094
		   default_credits);
6095
 
6096
	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6097
		   credits | PFI_CREDIT_RESEND);
6098
 
6099
	/*
6100
	 * FIXME is this guaranteed to clear
6101
	 * immediately or should we poll for it?
6102
	 */
6103
	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6104
}
6105
 
6106
static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6107
{
6108
	struct drm_device *dev = old_state->dev;
6109
	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6110
	struct drm_i915_private *dev_priv = dev->dev_private;
6111
 
6112
	/*
6113
	 * FIXME: We can end up here with all power domains off, yet
6114
	 * with a CDCLK frequency other than the minimum. To account
6115
	 * for this take the PIPE-A power domain, which covers the HW
6116
	 * blocks needed for the following programming. This can be
6117
	 * removed once it's guaranteed that we get here either with
6118
	 * the minimum CDCLK set, or the required power domains
6119
	 * enabled.
6120
	 */
6121
	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6122
 
6123
	if (IS_CHERRYVIEW(dev))
6124
		cherryview_set_cdclk(dev, req_cdclk);
6125
	else
4560 Serge 6126
		valleyview_set_cdclk(dev, req_cdclk);
5354 serge 6127
 
6084 serge 6128
	vlv_program_pfi_credits(dev_priv);
6129
 
6130
	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4560 Serge 6131
}
6132
 
4104 Serge 6133
static void valleyview_crtc_enable(struct drm_crtc *crtc)
6134
{
6135
	struct drm_device *dev = crtc->dev;
5354 serge 6136
	struct drm_i915_private *dev_priv = to_i915(dev);
4104 Serge 6137
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6138
	struct intel_encoder *encoder;
6139
	int pipe = intel_crtc->pipe;
4560 Serge 6140
	bool is_dsi;
4104 Serge 6141
 
6084 serge 6142
	if (WARN_ON(intel_crtc->active))
4104 Serge 6143
		return;
6144
 
5354 serge 6145
	is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5060 serge 6146
 
6084 serge 6147
	if (intel_crtc->config->has_dp_encoder)
6148
		intel_dp_set_m_n(intel_crtc, M1_N1);
5060 serge 6149
 
6150
	intel_set_pipe_timings(intel_crtc);
6151
 
5354 serge 6152
	if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6153
		struct drm_i915_private *dev_priv = dev->dev_private;
5060 serge 6154
 
5354 serge 6155
		I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6156
		I915_WRITE(CHV_CANVAS(pipe), 0);
6157
	}
6158
 
5060 serge 6159
	i9xx_set_pipeconf(intel_crtc);
6160
 
4104 Serge 6161
	intel_crtc->active = true;
6162
 
5354 serge 6163
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5060 serge 6164
 
4104 Serge 6165
	for_each_encoder_on_crtc(dev, crtc, encoder)
6166
		if (encoder->pre_pll_enable)
6167
			encoder->pre_pll_enable(encoder);
6168
 
5060 serge 6169
	if (!is_dsi) {
6084 serge 6170
		if (IS_CHERRYVIEW(dev)) {
6171
			chv_prepare_pll(intel_crtc, intel_crtc->config);
6172
			chv_enable_pll(intel_crtc, intel_crtc->config);
6173
		} else {
6174
			vlv_prepare_pll(intel_crtc, intel_crtc->config);
6175
			vlv_enable_pll(intel_crtc, intel_crtc->config);
6176
		}
5060 serge 6177
	}
4104 Serge 6178
 
6179
	for_each_encoder_on_crtc(dev, crtc, encoder)
6180
		if (encoder->pre_enable)
6181
			encoder->pre_enable(encoder);
6182
 
6183
	i9xx_pfit_enable(intel_crtc);
6184
 
6185
	intel_crtc_load_lut(crtc);
6186
 
5060 serge 6187
	intel_enable_pipe(intel_crtc);
4104 Serge 6188
 
5354 serge 6189
	assert_vblank_disabled(crtc);
6190
	drm_crtc_vblank_on(crtc);
6191
 
6084 serge 6192
	for_each_encoder_on_crtc(dev, crtc, encoder)
6193
		encoder->enable(encoder);
4104 Serge 6194
}
6195
 
5060 serge 6196
static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6197
{
6198
	struct drm_device *dev = crtc->base.dev;
6199
	struct drm_i915_private *dev_priv = dev->dev_private;
6200
 
6084 serge 6201
	I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6202
	I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5060 serge 6203
}
6204
 
2327 Serge 6205
static void i9xx_crtc_enable(struct drm_crtc *crtc)
6206
{
6084 serge 6207
	struct drm_device *dev = crtc->dev;
5354 serge 6208
	struct drm_i915_private *dev_priv = to_i915(dev);
6084 serge 6209
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 serge 6210
	struct intel_encoder *encoder;
6084 serge 6211
	int pipe = intel_crtc->pipe;
2327 Serge 6212
 
6084 serge 6213
	if (WARN_ON(intel_crtc->active))
6214
		return;
3031 serge 6215
 
5060 serge 6216
	i9xx_set_pll_dividers(intel_crtc);
6217
 
6084 serge 6218
	if (intel_crtc->config->has_dp_encoder)
6219
		intel_dp_set_m_n(intel_crtc, M1_N1);
5060 serge 6220
 
6221
	intel_set_pipe_timings(intel_crtc);
6222
 
6223
	i9xx_set_pipeconf(intel_crtc);
6224
 
6084 serge 6225
	intel_crtc->active = true;
2327 Serge 6226
 
5060 serge 6227
	if (!IS_GEN2(dev))
5354 serge 6228
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5060 serge 6229
 
3480 Serge 6230
	for_each_encoder_on_crtc(dev, crtc, encoder)
6231
		if (encoder->pre_enable)
6232
			encoder->pre_enable(encoder);
6233
 
4104 Serge 6234
	i9xx_enable_pll(intel_crtc);
6235
 
6236
	i9xx_pfit_enable(intel_crtc);
6237
 
6238
	intel_crtc_load_lut(crtc);
6239
 
4560 Serge 6240
	intel_update_watermarks(crtc);
5060 serge 6241
	intel_enable_pipe(intel_crtc);
2327 Serge 6242
 
5354 serge 6243
	assert_vblank_disabled(crtc);
6244
	drm_crtc_vblank_on(crtc);
6245
 
6084 serge 6246
	for_each_encoder_on_crtc(dev, crtc, encoder)
6247
		encoder->enable(encoder);
2327 Serge 6248
}
6249
 
3746 Serge 6250
static void i9xx_pfit_disable(struct intel_crtc *crtc)
6251
{
6252
	struct drm_device *dev = crtc->base.dev;
6253
	struct drm_i915_private *dev_priv = dev->dev_private;
6254
 
6084 serge 6255
	if (!crtc->config->gmch_pfit.control)
4104 Serge 6256
		return;
6257
 
3746 Serge 6258
	assert_pipe_disabled(dev_priv, crtc->pipe);
6259
 
4104 Serge 6260
	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6261
			 I915_READ(PFIT_CONTROL));
6084 serge 6262
	I915_WRITE(PFIT_CONTROL, 0);
3746 Serge 6263
}
6264
 
2327 Serge 6265
static void i9xx_crtc_disable(struct drm_crtc *crtc)
6266
{
6084 serge 6267
	struct drm_device *dev = crtc->dev;
6268
	struct drm_i915_private *dev_priv = dev->dev_private;
6269
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 serge 6270
	struct intel_encoder *encoder;
6084 serge 6271
	int pipe = intel_crtc->pipe;
2327 Serge 6272
 
5060 serge 6273
	/*
6274
	 * On gen2 planes are double buffered but the pipe isn't, so we must
6275
	 * wait for planes to fully turn off before disabling the pipe.
6276
	 * We also need to wait on all gmch platforms because of the
6277
	 * self-refresh mode constraint explained above.
6278
	 */
6084 serge 6279
	intel_wait_for_vblank(dev, pipe);
2327 Serge 6280
 
6084 serge 6281
	for_each_encoder_on_crtc(dev, crtc, encoder)
6282
		encoder->disable(encoder);
6283
 
5354 serge 6284
	drm_crtc_vblank_off(crtc);
6285
	assert_vblank_disabled(crtc);
3480 Serge 6286
 
5354 serge 6287
	intel_disable_pipe(intel_crtc);
6288
 
3746 Serge 6289
	i9xx_pfit_disable(intel_crtc);
3480 Serge 6290
 
4104 Serge 6291
	for_each_encoder_on_crtc(dev, crtc, encoder)
6292
		if (encoder->post_disable)
6293
			encoder->post_disable(encoder);
2327 Serge 6294
 
5354 serge 6295
	if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5060 serge 6296
		if (IS_CHERRYVIEW(dev))
6297
			chv_disable_pll(dev_priv, pipe);
6298
		else if (IS_VALLEYVIEW(dev))
6084 serge 6299
			vlv_disable_pll(dev_priv, pipe);
5060 serge 6300
		else
5354 serge 6301
			i9xx_disable_pll(intel_crtc);
5060 serge 6302
	}
4104 Serge 6303
 
6084 serge 6304
	for_each_encoder_on_crtc(dev, crtc, encoder)
6305
		if (encoder->post_pll_disable)
6306
			encoder->post_pll_disable(encoder);
6307
 
5060 serge 6308
	if (!IS_GEN2(dev))
5354 serge 6309
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2327 Serge 6310
}
6311
 
6084 serge 6312
static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
2327 Serge 6313
{
5060 serge 6314
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084 serge 6315
	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5060 serge 6316
	enum intel_display_power_domain domain;
6317
	unsigned long domains;
6318
 
6084 serge 6319
	if (!intel_crtc->active)
6320
		return;
5060 serge 6321
 
6084 serge 6322
	if (to_intel_plane_state(crtc->primary->state)->visible) {
6323
		intel_pre_disable_primary(crtc);
5060 serge 6324
 
6084 serge 6325
		intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6326
		to_intel_plane_state(crtc->primary->state)->visible = false;
5060 serge 6327
	}
6084 serge 6328
 
6329
	dev_priv->display.crtc_disable(crtc);
6330
	intel_crtc->active = false;
6331
	intel_update_watermarks(crtc);
6332
	intel_disable_shared_dpll(intel_crtc);
6333
 
6334
	domains = intel_crtc->enabled_power_domains;
6335
	for_each_power_domain(domain, domains)
6336
		intel_display_power_put(dev_priv, domain);
6337
	intel_crtc->enabled_power_domains = 0;
2330 Serge 6338
}
2327 Serge 6339
 
6084 serge 6340
/*
6341
 * turn all crtc's off, but do not adjust state
6342
 * This has to be paired with a call to intel_modeset_setup_hw_state.
3031 serge 6343
 */
6084 serge 6344
int intel_display_suspend(struct drm_device *dev)
3031 serge 6345
{
6084 serge 6346
	struct drm_mode_config *config = &dev->mode_config;
6347
	struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6348
	struct drm_atomic_state *state;
6349
	struct drm_crtc *crtc;
6350
	unsigned crtc_mask = 0;
6351
	int ret = 0;
3031 serge 6352
 
6084 serge 6353
	if (WARN_ON(!ctx))
6354
		return 0;
3031 serge 6355
 
6084 serge 6356
	lockdep_assert_held(&ctx->ww_ctx);
6357
	state = drm_atomic_state_alloc(dev);
6358
	if (WARN_ON(!state))
6359
		return -ENOMEM;
3031 serge 6360
 
6084 serge 6361
	state->acquire_ctx = ctx;
6362
	state->allow_modeset = true;
2327 Serge 6363
 
6084 serge 6364
	for_each_crtc(dev, crtc) {
6365
		struct drm_crtc_state *crtc_state =
6366
			drm_atomic_get_crtc_state(state, crtc);
2327 Serge 6367
 
6084 serge 6368
		ret = PTR_ERR_OR_ZERO(crtc_state);
6369
		if (ret)
6370
			goto free;
3031 serge 6371
 
6084 serge 6372
		if (!crtc_state->active)
6373
			continue;
6374
 
6375
		crtc_state->active = false;
6376
		crtc_mask |= 1 << drm_crtc_index(crtc);
4280 Serge 6377
	}
3031 serge 6378
 
6084 serge 6379
	if (crtc_mask) {
6380
		ret = drm_atomic_commit(state);
3031 serge 6381
 
6084 serge 6382
		if (!ret) {
6383
			for_each_crtc(dev, crtc)
6384
				if (crtc_mask & (1 << drm_crtc_index(crtc)))
6385
					crtc->state->active = true;
3031 serge 6386
 
6084 serge 6387
			return ret;
6388
		}
2330 Serge 6389
	}
6084 serge 6390
 
6391
free:
6392
	if (ret)
6393
		DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6394
	drm_atomic_state_free(state);
6395
	return ret;
2330 Serge 6396
}
2327 Serge 6397
 
3031 serge 6398
void intel_encoder_destroy(struct drm_encoder *encoder)
2330 Serge 6399
{
3031 serge 6400
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6401
 
6402
	drm_encoder_cleanup(encoder);
6403
	kfree(intel_encoder);
2330 Serge 6404
}
2327 Serge 6405
 
3031 serge 6406
/* Cross check the actual hw state with our own modeset state tracking (and it's
6407
 * internal consistency). */
6408
static void intel_connector_check_state(struct intel_connector *connector)
2330 Serge 6409
{
6084 serge 6410
	struct drm_crtc *crtc = connector->base.state->crtc;
6411
 
6412
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6413
		      connector->base.base.id,
6414
		      connector->base.name);
6415
 
3031 serge 6416
	if (connector->get_hw_state(connector)) {
6417
		struct intel_encoder *encoder = connector->encoder;
6084 serge 6418
		struct drm_connector_state *conn_state = connector->base.state;
3031 serge 6419
 
6084 serge 6420
		I915_STATE_WARN(!crtc,
6421
			 "connector enabled without attached crtc\n");
3031 serge 6422
 
6084 serge 6423
		if (!crtc)
5060 serge 6424
			return;
6425
 
6084 serge 6426
		I915_STATE_WARN(!crtc->state->active,
6427
		      "connector is active, but attached crtc isn't\n");
5060 serge 6428
 
6084 serge 6429
		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
3031 serge 6430
			return;
6431
 
6084 serge 6432
		I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6433
			"atomic encoder doesn't match attached encoder\n");
3031 serge 6434
 
6084 serge 6435
		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6436
			"attached encoder crtc differs from connector crtc\n");
6437
	} else {
6438
		I915_STATE_WARN(crtc && crtc->state->active,
6439
			"attached crtc is active, but connector isn't\n");
6440
		I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6441
			"best encoder set without crtc!\n");
3031 serge 6442
	}
2330 Serge 6443
}
2327 Serge 6444
 
6084 serge 6445
int intel_connector_init(struct intel_connector *connector)
2330 Serge 6446
{
6084 serge 6447
	struct drm_connector_state *connector_state;
2342 Serge 6448
 
6084 serge 6449
	connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6450
	if (!connector_state)
6451
		return -ENOMEM;
3031 serge 6452
 
6084 serge 6453
	connector->base.state = connector_state;
6454
	return 0;
6455
}
3031 serge 6456
 
6084 serge 6457
struct intel_connector *intel_connector_alloc(void)
6458
{
6459
	struct intel_connector *connector;
3031 serge 6460
 
6084 serge 6461
	connector = kzalloc(sizeof *connector, GFP_KERNEL);
6462
	if (!connector)
6463
		return NULL;
6464
 
6465
	if (intel_connector_init(connector) < 0) {
6466
		kfree(connector);
6467
		return NULL;
6468
	}
6469
 
6470
	return connector;
2330 Serge 6471
}
2327 Serge 6472
 
3031 serge 6473
/* Simple connector->get_hw_state implementation for encoders that support only
6474
 * one connector and no cloning and hence the encoder state determines the state
6475
 * of the connector. */
6476
bool intel_connector_get_hw_state(struct intel_connector *connector)
2330 Serge 6477
{
3031 serge 6478
	enum pipe pipe = 0;
6479
	struct intel_encoder *encoder = connector->encoder;
2330 Serge 6480
 
3031 serge 6481
	return encoder->get_hw_state(encoder, &pipe);
2330 Serge 6482
}
6483
 
6084 serge 6484
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
4104 Serge 6485
{
6084 serge 6486
	if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6487
		return crtc_state->fdi_lanes;
4104 Serge 6488
 
6084 serge 6489
	return 0;
6490
}
6491
 
6492
static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6493
				     struct intel_crtc_state *pipe_config)
6494
{
6495
	struct drm_atomic_state *state = pipe_config->base.state;
6496
	struct intel_crtc *other_crtc;
6497
	struct intel_crtc_state *other_crtc_state;
6498
 
4104 Serge 6499
	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6500
		      pipe_name(pipe), pipe_config->fdi_lanes);
6501
	if (pipe_config->fdi_lanes > 4) {
6502
		DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6503
			      pipe_name(pipe), pipe_config->fdi_lanes);
6084 serge 6504
		return -EINVAL;
4104 Serge 6505
	}
6506
 
4560 Serge 6507
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4104 Serge 6508
		if (pipe_config->fdi_lanes > 2) {
6509
			DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6510
				      pipe_config->fdi_lanes);
6084 serge 6511
			return -EINVAL;
4104 Serge 6512
		} else {
6084 serge 6513
			return 0;
4104 Serge 6514
		}
6515
	}
6516
 
6517
	if (INTEL_INFO(dev)->num_pipes == 2)
6084 serge 6518
		return 0;
4104 Serge 6519
 
6520
	/* Ivybridge 3 pipe is really complicated */
6521
	switch (pipe) {
6522
	case PIPE_A:
6084 serge 6523
		return 0;
4104 Serge 6524
	case PIPE_B:
6084 serge 6525
		if (pipe_config->fdi_lanes <= 2)
6526
			return 0;
6527
 
6528
		other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6529
		other_crtc_state =
6530
			intel_atomic_get_crtc_state(state, other_crtc);
6531
		if (IS_ERR(other_crtc_state))
6532
			return PTR_ERR(other_crtc_state);
6533
 
6534
		if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
4104 Serge 6535
			DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6536
				      pipe_name(pipe), pipe_config->fdi_lanes);
6084 serge 6537
			return -EINVAL;
4104 Serge 6538
		}
6084 serge 6539
		return 0;
4104 Serge 6540
	case PIPE_C:
6084 serge 6541
		if (pipe_config->fdi_lanes > 2) {
6542
			DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6543
				      pipe_name(pipe), pipe_config->fdi_lanes);
6544
			return -EINVAL;
6545
		}
6546
 
6547
		other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6548
		other_crtc_state =
6549
			intel_atomic_get_crtc_state(state, other_crtc);
6550
		if (IS_ERR(other_crtc_state))
6551
			return PTR_ERR(other_crtc_state);
6552
 
6553
		if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
4104 Serge 6554
			DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6084 serge 6555
			return -EINVAL;
4104 Serge 6556
		}
6084 serge 6557
		return 0;
4104 Serge 6558
	default:
6559
		BUG();
6560
	}
6561
}
6562
 
6563
#define RETRY 1
6564
static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6084 serge 6565
				       struct intel_crtc_state *pipe_config)
2330 Serge 6566
{
4104 Serge 6567
	struct drm_device *dev = intel_crtc->base.dev;
6084 serge 6568
	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6569
	int lane, link_bw, fdi_dotclock, ret;
6570
	bool needs_recompute = false;
2330 Serge 6571
 
4104 Serge 6572
retry:
6573
	/* FDI is a binary signal running at ~2.7GHz, encoding
6574
	 * each output octet as 10 bits. The actual frequency
6575
	 * is stored as a divider into a 100MHz clock, and the
6576
	 * mode pixel clock is stored in units of 1KHz.
6577
	 * Hence the bw of each lane in terms of the mode signal
6578
	 * is:
6579
	 */
6580
	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6581
 
4560 Serge 6582
	fdi_dotclock = adjusted_mode->crtc_clock;
4104 Serge 6583
 
6584
	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6585
					   pipe_config->pipe_bpp);
6586
 
6587
	pipe_config->fdi_lanes = lane;
6588
 
6589
	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6590
			       link_bw, &pipe_config->fdi_m_n);
6591
 
6084 serge 6592
	ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6593
				       intel_crtc->pipe, pipe_config);
6594
	if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
4104 Serge 6595
		pipe_config->pipe_bpp -= 2*3;
6596
		DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6597
			      pipe_config->pipe_bpp);
6598
		needs_recompute = true;
6599
		pipe_config->bw_constrained = true;
6600
 
6601
		goto retry;
6602
	}
6603
 
6604
	if (needs_recompute)
6605
		return RETRY;
6606
 
6084 serge 6607
	return ret;
4104 Serge 6608
}
6609
 
6084 serge 6610
static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6611
				     struct intel_crtc_state *pipe_config)
6612
{
6613
	if (pipe_config->pipe_bpp > 24)
6614
		return false;
6615
 
6616
	/* HSW can handle pixel rate up to cdclk? */
6617
	if (IS_HASWELL(dev_priv->dev))
6618
		return true;
6619
 
6620
	/*
6621
	 * We compare against max which means we must take
6622
	 * the increased cdclk requirement into account when
6623
	 * calculating the new cdclk.
6624
	 *
6625
	 * Should measure whether using a lower cdclk w/o IPS
6626
	 */
6627
	return ilk_pipe_pixel_rate(pipe_config) <=
6628
		dev_priv->max_cdclk_freq * 95 / 100;
6629
}
6630
 
4104 Serge 6631
static void hsw_compute_ips_config(struct intel_crtc *crtc,
6084 serge 6632
				   struct intel_crtc_state *pipe_config)
4104 Serge 6633
{
6084 serge 6634
	struct drm_device *dev = crtc->base.dev;
6635
	struct drm_i915_private *dev_priv = dev->dev_private;
6636
 
5060 serge 6637
	pipe_config->ips_enabled = i915.enable_ips &&
6084 serge 6638
		hsw_crtc_supports_ips(crtc) &&
6639
		pipe_config_supports_ips(dev_priv, pipe_config);
4104 Serge 6640
}
6641
 
6642
static int intel_crtc_compute_config(struct intel_crtc *crtc,
6084 serge 6643
				     struct intel_crtc_state *pipe_config)
4104 Serge 6644
{
6645
	struct drm_device *dev = crtc->base.dev;
5354 serge 6646
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 6647
	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
4104 Serge 6648
 
4560 Serge 6649
	/* FIXME should check pixel clock limits on all platforms */
6650
	if (INTEL_INFO(dev)->gen < 4) {
6084 serge 6651
		int clock_limit = dev_priv->max_cdclk_freq;
4560 Serge 6652
 
6653
		/*
6654
		 * Enable pixel doubling when the dot clock
6655
		 * is > 90% of the (display) core speed.
6656
		 *
6657
		 * GDG double wide on either pipe,
6658
		 * otherwise pipe A only.
6659
		 */
6660
		if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6661
		    adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6662
			clock_limit *= 2;
6663
			pipe_config->double_wide = true;
6664
		}
6665
 
6666
		if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4104 Serge 6667
			return -EINVAL;
2330 Serge 6668
	}
6669
 
4560 Serge 6670
	/*
6671
	 * Pipe horizontal size must be even in:
6672
	 * - DVO ganged mode
6673
	 * - LVDS dual channel mode
6674
	 * - Double wide pipe
6675
	 */
6084 serge 6676
	if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
4560 Serge 6677
	     intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6678
		pipe_config->pipe_src_w &= ~1;
6679
 
4104 Serge 6680
	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
6681
	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
3031 serge 6682
	 */
6683
	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6084 serge 6684
		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
4104 Serge 6685
		return -EINVAL;
3031 serge 6686
 
4104 Serge 6687
	if (HAS_IPS(dev))
6688
		hsw_compute_ips_config(crtc, pipe_config);
6689
 
6690
	if (pipe_config->has_pch_encoder)
6691
		return ironlake_fdi_compute_config(crtc, pipe_config);
6692
 
6693
	return 0;
2330 Serge 6694
}
6695
 
6084 serge 6696
static int skylake_get_display_clock_speed(struct drm_device *dev)
3031 serge 6697
{
6084 serge 6698
	struct drm_i915_private *dev_priv = to_i915(dev);
6699
	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6700
	uint32_t cdctl = I915_READ(CDCLK_CTL);
6701
	uint32_t linkrate;
5060 serge 6702
 
6084 serge 6703
	if (!(lcpll1 & LCPLL_PLL_ENABLE))
6704
		return 24000; /* 24MHz is the cd freq with NSSC ref */
5354 serge 6705
 
6084 serge 6706
	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6707
		return 540000;
5354 serge 6708
 
6084 serge 6709
	linkrate = (I915_READ(DPLL_CTRL1) &
6710
		    DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
5060 serge 6711
 
6084 serge 6712
	if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6713
	    linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6714
		/* vco 8640 */
6715
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6716
		case CDCLK_FREQ_450_432:
6717
			return 432000;
6718
		case CDCLK_FREQ_337_308:
6719
			return 308570;
6720
		case CDCLK_FREQ_675_617:
6721
			return 617140;
6722
		default:
6723
			WARN(1, "Unknown cd freq selection\n");
6724
		}
6725
	} else {
6726
		/* vco 8100 */
6727
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6728
		case CDCLK_FREQ_450_432:
6729
			return 450000;
6730
		case CDCLK_FREQ_337_308:
6731
			return 337500;
6732
		case CDCLK_FREQ_675_617:
6733
			return 675000;
6734
		default:
6735
			WARN(1, "Unknown cd freq selection\n");
6736
		}
6737
	}
5060 serge 6738
 
6084 serge 6739
	/* error case, do as if DPLL0 isn't enabled */
6740
	return 24000;
6741
}
5060 serge 6742
 
6084 serge 6743
static int broxton_get_display_clock_speed(struct drm_device *dev)
6744
{
6745
	struct drm_i915_private *dev_priv = to_i915(dev);
6746
	uint32_t cdctl = I915_READ(CDCLK_CTL);
6747
	uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6748
	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6749
	int cdclk;
6750
 
6751
	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6752
		return 19200;
6753
 
6754
	cdclk = 19200 * pll_ratio / 2;
6755
 
6756
	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6757
	case BXT_CDCLK_CD2X_DIV_SEL_1:
6758
		return cdclk;  /* 576MHz or 624MHz */
6759
	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6760
		return cdclk * 2 / 3; /* 384MHz */
6761
	case BXT_CDCLK_CD2X_DIV_SEL_2:
6762
		return cdclk / 2; /* 288MHz */
6763
	case BXT_CDCLK_CD2X_DIV_SEL_4:
6764
		return cdclk / 4; /* 144MHz */
6765
	}
6766
 
6767
	/* error case, do as if DE PLL isn't enabled */
6768
	return 19200;
3031 serge 6769
}
6770
 
6084 serge 6771
static int broadwell_get_display_clock_speed(struct drm_device *dev)
6772
{
6773
	struct drm_i915_private *dev_priv = dev->dev_private;
6774
	uint32_t lcpll = I915_READ(LCPLL_CTL);
6775
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6776
 
6777
	if (lcpll & LCPLL_CD_SOURCE_FCLK)
6778
		return 800000;
6779
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6780
		return 450000;
6781
	else if (freq == LCPLL_CLK_FREQ_450)
6782
		return 450000;
6783
	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6784
		return 540000;
6785
	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6786
		return 337500;
6787
	else
6788
		return 675000;
6789
}
6790
 
6791
static int haswell_get_display_clock_speed(struct drm_device *dev)
6792
{
6793
	struct drm_i915_private *dev_priv = dev->dev_private;
6794
	uint32_t lcpll = I915_READ(LCPLL_CTL);
6795
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6796
 
6797
	if (lcpll & LCPLL_CD_SOURCE_FCLK)
6798
		return 800000;
6799
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6800
		return 450000;
6801
	else if (freq == LCPLL_CLK_FREQ_450)
6802
		return 450000;
6803
	else if (IS_HSW_ULT(dev))
6804
		return 337500;
6805
	else
6806
		return 540000;
6807
}
6808
 
6809
static int valleyview_get_display_clock_speed(struct drm_device *dev)
6810
{
6811
	return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6812
				      CCK_DISPLAY_CLOCK_CONTROL);
6813
}
6814
 
6815
static int ilk_get_display_clock_speed(struct drm_device *dev)
6816
{
6817
	return 450000;
6818
}
6819
 
2327 Serge 6820
static int i945_get_display_clock_speed(struct drm_device *dev)
6821
{
6822
	return 400000;
6823
}
6824
 
6825
static int i915_get_display_clock_speed(struct drm_device *dev)
6826
{
6084 serge 6827
	return 333333;
2327 Serge 6828
}
6829
 
6830
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6831
{
6832
	return 200000;
6833
}
6834
 
4104 Serge 6835
static int pnv_get_display_clock_speed(struct drm_device *dev)
6836
{
6837
	u16 gcfgc = 0;
6838
 
6839
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6840
 
6841
	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6842
	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6084 serge 6843
		return 266667;
4104 Serge 6844
	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6084 serge 6845
		return 333333;
4104 Serge 6846
	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6084 serge 6847
		return 444444;
4104 Serge 6848
	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6849
		return 200000;
6850
	default:
6851
		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6852
	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6084 serge 6853
		return 133333;
4104 Serge 6854
	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6084 serge 6855
		return 166667;
4104 Serge 6856
	}
6857
}
6858
 
2327 Serge 6859
static int i915gm_get_display_clock_speed(struct drm_device *dev)
6860
{
6861
	u16 gcfgc = 0;
6862
 
6863
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6864
 
6865
	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6084 serge 6866
		return 133333;
2327 Serge 6867
	else {
6868
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6869
		case GC_DISPLAY_CLOCK_333_MHZ:
6084 serge 6870
			return 333333;
2327 Serge 6871
		default:
6872
		case GC_DISPLAY_CLOCK_190_200_MHZ:
6873
			return 190000;
6874
		}
6875
	}
6876
}
6877
 
6878
static int i865_get_display_clock_speed(struct drm_device *dev)
6879
{
6084 serge 6880
	return 266667;
2327 Serge 6881
}
6882
 
6084 serge 6883
static int i85x_get_display_clock_speed(struct drm_device *dev)
2327 Serge 6884
{
6885
	u16 hpllcc = 0;
6084 serge 6886
 
6887
	/*
6888
	 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6889
	 * encoding is different :(
6890
	 * FIXME is this the right way to detect 852GM/852GMV?
6891
	 */
6892
	if (dev->pdev->revision == 0x1)
6893
		return 133333;
6894
 
6895
//   pci_bus_read_config_word(dev->pdev->bus,
6896
//                PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6897
 
2327 Serge 6898
	/* Assume that the hardware is in the high speed state.  This
6899
	 * should be the default.
6900
	 */
6901
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6902
	case GC_CLOCK_133_200:
6084 serge 6903
	case GC_CLOCK_133_200_2:
2327 Serge 6904
	case GC_CLOCK_100_200:
6905
		return 200000;
6906
	case GC_CLOCK_166_250:
6907
		return 250000;
6908
	case GC_CLOCK_100_133:
6084 serge 6909
		return 133333;
6910
	case GC_CLOCK_133_266:
6911
	case GC_CLOCK_133_266_2:
6912
	case GC_CLOCK_166_266:
6913
		return 266667;
2327 Serge 6914
	}
6915
 
6916
	/* Shouldn't happen */
6917
	return 0;
6918
}
6919
 
6920
static int i830_get_display_clock_speed(struct drm_device *dev)
6921
{
6084 serge 6922
	return 133333;
2327 Serge 6923
}
6924
 
6084 serge 6925
static unsigned int intel_hpll_vco(struct drm_device *dev)
6926
{
6927
	struct drm_i915_private *dev_priv = dev->dev_private;
6928
	static const unsigned int blb_vco[8] = {
6929
		[0] = 3200000,
6930
		[1] = 4000000,
6931
		[2] = 5333333,
6932
		[3] = 4800000,
6933
		[4] = 6400000,
6934
	};
6935
	static const unsigned int pnv_vco[8] = {
6936
		[0] = 3200000,
6937
		[1] = 4000000,
6938
		[2] = 5333333,
6939
		[3] = 4800000,
6940
		[4] = 2666667,
6941
	};
6942
	static const unsigned int cl_vco[8] = {
6943
		[0] = 3200000,
6944
		[1] = 4000000,
6945
		[2] = 5333333,
6946
		[3] = 6400000,
6947
		[4] = 3333333,
6948
		[5] = 3566667,
6949
		[6] = 4266667,
6950
	};
6951
	static const unsigned int elk_vco[8] = {
6952
		[0] = 3200000,
6953
		[1] = 4000000,
6954
		[2] = 5333333,
6955
		[3] = 4800000,
6956
	};
6957
	static const unsigned int ctg_vco[8] = {
6958
		[0] = 3200000,
6959
		[1] = 4000000,
6960
		[2] = 5333333,
6961
		[3] = 6400000,
6962
		[4] = 2666667,
6963
		[5] = 4266667,
6964
	};
6965
	const unsigned int *vco_table;
6966
	unsigned int vco;
6967
	uint8_t tmp = 0;
6968
 
6969
	/* FIXME other chipsets? */
6970
	if (IS_GM45(dev))
6971
		vco_table = ctg_vco;
6972
	else if (IS_G4X(dev))
6973
		vco_table = elk_vco;
6974
	else if (IS_CRESTLINE(dev))
6975
		vco_table = cl_vco;
6976
	else if (IS_PINEVIEW(dev))
6977
		vco_table = pnv_vco;
6978
	else if (IS_G33(dev))
6979
		vco_table = blb_vco;
6980
	else
6981
		return 0;
6982
 
6983
	tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6984
 
6985
	vco = vco_table[tmp & 0x7];
6986
	if (vco == 0)
6987
		DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6988
	else
6989
		DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6990
 
6991
	return vco;
6992
}
6993
 
6994
static int gm45_get_display_clock_speed(struct drm_device *dev)
6995
{
6996
	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6997
	uint16_t tmp = 0;
6998
 
6999
	pci_read_config_word(dev->pdev, GCFGC, &tmp);
7000
 
7001
	cdclk_sel = (tmp >> 12) & 0x1;
7002
 
7003
	switch (vco) {
7004
	case 2666667:
7005
	case 4000000:
7006
	case 5333333:
7007
		return cdclk_sel ? 333333 : 222222;
7008
	case 3200000:
7009
		return cdclk_sel ? 320000 : 228571;
7010
	default:
7011
		DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7012
		return 222222;
7013
	}
7014
}
7015
 
7016
static int i965gm_get_display_clock_speed(struct drm_device *dev)
7017
{
7018
	static const uint8_t div_3200[] = { 16, 10,  8 };
7019
	static const uint8_t div_4000[] = { 20, 12, 10 };
7020
	static const uint8_t div_5333[] = { 24, 16, 14 };
7021
	const uint8_t *div_table;
7022
	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7023
	uint16_t tmp = 0;
7024
 
7025
	pci_read_config_word(dev->pdev, GCFGC, &tmp);
7026
 
7027
	cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7028
 
7029
	if (cdclk_sel >= ARRAY_SIZE(div_3200))
7030
		goto fail;
7031
 
7032
	switch (vco) {
7033
	case 3200000:
7034
		div_table = div_3200;
7035
		break;
7036
	case 4000000:
7037
		div_table = div_4000;
7038
		break;
7039
	case 5333333:
7040
		div_table = div_5333;
7041
		break;
7042
	default:
7043
		goto fail;
7044
	}
7045
 
7046
	return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7047
 
7048
fail:
7049
	DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7050
	return 200000;
7051
}
7052
 
7053
static int g33_get_display_clock_speed(struct drm_device *dev)
7054
{
7055
	static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7056
	static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7057
	static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7058
	static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7059
	const uint8_t *div_table;
7060
	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7061
	uint16_t tmp = 0;
7062
 
7063
	pci_read_config_word(dev->pdev, GCFGC, &tmp);
7064
 
7065
	cdclk_sel = (tmp >> 4) & 0x7;
7066
 
7067
	if (cdclk_sel >= ARRAY_SIZE(div_3200))
7068
		goto fail;
7069
 
7070
	switch (vco) {
7071
	case 3200000:
7072
		div_table = div_3200;
7073
		break;
7074
	case 4000000:
7075
		div_table = div_4000;
7076
		break;
7077
	case 4800000:
7078
		div_table = div_4800;
7079
		break;
7080
	case 5333333:
7081
		div_table = div_5333;
7082
		break;
7083
	default:
7084
		goto fail;
7085
	}
7086
 
7087
	return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7088
 
7089
fail:
7090
	DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7091
	return 190476;
7092
}
7093
 
2327 Serge 7094
static void
3746 Serge 7095
intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2327 Serge 7096
{
3746 Serge 7097
	while (*num > DATA_LINK_M_N_MASK ||
7098
	       *den > DATA_LINK_M_N_MASK) {
2327 Serge 7099
		*num >>= 1;
7100
		*den >>= 1;
7101
	}
7102
}
7103
 
3746 Serge 7104
static void compute_m_n(unsigned int m, unsigned int n,
7105
			uint32_t *ret_m, uint32_t *ret_n)
7106
{
7107
	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7108
	*ret_m = div_u64((uint64_t) m * *ret_n, n);
7109
	intel_reduce_m_n_ratio(ret_m, ret_n);
7110
}
7111
 
3480 Serge 7112
void
7113
intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7114
		       int pixel_clock, int link_clock,
7115
		       struct intel_link_m_n *m_n)
2327 Serge 7116
{
3480 Serge 7117
	m_n->tu = 64;
3746 Serge 7118
 
7119
	compute_m_n(bits_per_pixel * pixel_clock,
7120
		    link_clock * nlanes * 8,
7121
		    &m_n->gmch_m, &m_n->gmch_n);
7122
 
7123
	compute_m_n(pixel_clock, link_clock,
7124
		    &m_n->link_m, &m_n->link_n);
2327 Serge 7125
}
7126
 
7127
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7128
{
5060 serge 7129
	if (i915.panel_use_ssc >= 0)
7130
		return i915.panel_use_ssc != 0;
4104 Serge 7131
	return dev_priv->vbt.lvds_use_ssc
2327 Serge 7132
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7133
}
7134
 
6084 serge 7135
static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7136
			   int num_connectors)
3031 serge 7137
{
6084 serge 7138
	struct drm_device *dev = crtc_state->base.crtc->dev;
3031 serge 7139
	struct drm_i915_private *dev_priv = dev->dev_private;
7140
	int refclk;
2327 Serge 7141
 
6084 serge 7142
	WARN_ON(!crtc_state->base.state);
7143
 
7144
	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
4560 Serge 7145
		refclk = 100000;
6084 serge 7146
	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
3031 serge 7147
	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4560 Serge 7148
		refclk = dev_priv->vbt.lvds_ssc_freq;
7149
		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
3031 serge 7150
	} else if (!IS_GEN2(dev)) {
7151
		refclk = 96000;
7152
	} else {
7153
		refclk = 48000;
7154
	}
2327 Serge 7155
 
3031 serge 7156
	return refclk;
7157
}
2327 Serge 7158
 
4104 Serge 7159
static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
3031 serge 7160
{
4104 Serge 7161
	return (1 << dpll->n) << 16 | dpll->m2;
7162
}
3746 Serge 7163
 
4104 Serge 7164
static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7165
{
7166
	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
3031 serge 7167
}
2327 Serge 7168
 
3746 Serge 7169
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6084 serge 7170
				     struct intel_crtc_state *crtc_state,
3031 serge 7171
				     intel_clock_t *reduced_clock)
7172
{
3746 Serge 7173
	struct drm_device *dev = crtc->base.dev;
3031 serge 7174
	u32 fp, fp2 = 0;
2327 Serge 7175
 
3031 serge 7176
	if (IS_PINEVIEW(dev)) {
6084 serge 7177
		fp = pnv_dpll_compute_fp(&crtc_state->dpll);
3031 serge 7178
		if (reduced_clock)
4104 Serge 7179
			fp2 = pnv_dpll_compute_fp(reduced_clock);
3031 serge 7180
	} else {
6084 serge 7181
		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
3031 serge 7182
		if (reduced_clock)
4104 Serge 7183
			fp2 = i9xx_dpll_compute_fp(reduced_clock);
3031 serge 7184
	}
2327 Serge 7185
 
6084 serge 7186
	crtc_state->dpll_hw_state.fp0 = fp;
2327 Serge 7187
 
3746 Serge 7188
	crtc->lowfreq_avail = false;
6084 serge 7189
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7190
	    reduced_clock) {
7191
		crtc_state->dpll_hw_state.fp1 = fp2;
3746 Serge 7192
		crtc->lowfreq_avail = true;
3031 serge 7193
	} else {
6084 serge 7194
		crtc_state->dpll_hw_state.fp1 = fp;
3031 serge 7195
	}
7196
}
2327 Serge 7197
 
4560 Serge 7198
static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7199
		pipe)
4104 Serge 7200
{
7201
	u32 reg_val;
7202
 
7203
	/*
7204
	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7205
	 * and set it to a reasonable value instead.
7206
	 */
4560 Serge 7207
	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4104 Serge 7208
	reg_val &= 0xffffff00;
7209
	reg_val |= 0x00000030;
4560 Serge 7210
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4104 Serge 7211
 
4560 Serge 7212
	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4104 Serge 7213
	reg_val &= 0x8cffffff;
7214
	reg_val = 0x8c000000;
4560 Serge 7215
	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4104 Serge 7216
 
4560 Serge 7217
	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4104 Serge 7218
	reg_val &= 0xffffff00;
4560 Serge 7219
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4104 Serge 7220
 
4560 Serge 7221
	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4104 Serge 7222
	reg_val &= 0x00ffffff;
7223
	reg_val |= 0xb0000000;
4560 Serge 7224
	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4104 Serge 7225
}
7226
 
7227
static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7228
					 struct intel_link_m_n *m_n)
7229
{
7230
	struct drm_device *dev = crtc->base.dev;
7231
	struct drm_i915_private *dev_priv = dev->dev_private;
7232
	int pipe = crtc->pipe;
7233
 
7234
	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7235
	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7236
	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7237
	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7238
}
7239
 
7240
static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5354 serge 7241
					 struct intel_link_m_n *m_n,
7242
					 struct intel_link_m_n *m2_n2)
4104 Serge 7243
{
7244
	struct drm_device *dev = crtc->base.dev;
7245
	struct drm_i915_private *dev_priv = dev->dev_private;
7246
	int pipe = crtc->pipe;
6084 serge 7247
	enum transcoder transcoder = crtc->config->cpu_transcoder;
4104 Serge 7248
 
7249
	if (INTEL_INFO(dev)->gen >= 5) {
7250
		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7251
		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7252
		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7253
		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5354 serge 7254
		/* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7255
		 * for gen < 8) and if DRRS is supported (to make sure the
7256
		 * registers are not unnecessarily accessed).
7257
		 */
6084 serge 7258
		if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7259
			crtc->config->has_drrs) {
5354 serge 7260
			I915_WRITE(PIPE_DATA_M2(transcoder),
7261
					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7262
			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7263
			I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7264
			I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7265
		}
4104 Serge 7266
	} else {
7267
		I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7268
		I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7269
		I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7270
		I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7271
	}
7272
}
7273
 
6084 serge 7274
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
3031 serge 7275
{
6084 serge 7276
	struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7277
 
7278
	if (m_n == M1_N1) {
7279
		dp_m_n = &crtc->config->dp_m_n;
7280
		dp_m2_n2 = &crtc->config->dp_m2_n2;
7281
	} else if (m_n == M2_N2) {
7282
 
7283
		/*
7284
		 * M2_N2 registers are not supported. Hence m2_n2 divider value
7285
		 * needs to be programmed into M1_N1.
7286
		 */
7287
		dp_m_n = &crtc->config->dp_m2_n2;
7288
	} else {
7289
		DRM_ERROR("Unsupported divider value\n");
7290
		return;
7291
	}
7292
 
7293
	if (crtc->config->has_pch_encoder)
7294
		intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
3746 Serge 7295
	else
6084 serge 7296
		intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
3746 Serge 7297
}
7298
 
6084 serge 7299
static void vlv_compute_dpll(struct intel_crtc *crtc,
7300
			     struct intel_crtc_state *pipe_config)
3746 Serge 7301
{
5060 serge 7302
	u32 dpll, dpll_md;
7303
 
7304
	/*
7305
	 * Enable DPIO clock input. We should never disable the reference
7306
	 * clock for pipe B, since VGA hotplug / manual detection depends
7307
	 * on it.
7308
	 */
6084 serge 7309
	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7310
		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
5060 serge 7311
	/* We should never disable this, set it here for state tracking */
7312
	if (crtc->pipe == PIPE_B)
7313
		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7314
	dpll |= DPLL_VCO_ENABLE;
5354 serge 7315
	pipe_config->dpll_hw_state.dpll = dpll;
5060 serge 7316
 
5354 serge 7317
	dpll_md = (pipe_config->pixel_multiplier - 1)
5060 serge 7318
		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
5354 serge 7319
	pipe_config->dpll_hw_state.dpll_md = dpll_md;
5060 serge 7320
}
7321
 
5354 serge 7322
static void vlv_prepare_pll(struct intel_crtc *crtc,
6084 serge 7323
			    const struct intel_crtc_state *pipe_config)
5060 serge 7324
{
3746 Serge 7325
	struct drm_device *dev = crtc->base.dev;
3031 serge 7326
	struct drm_i915_private *dev_priv = dev->dev_private;
3746 Serge 7327
	int pipe = crtc->pipe;
5060 serge 7328
	u32 mdiv;
3031 serge 7329
	u32 bestn, bestm1, bestm2, bestp1, bestp2;
5060 serge 7330
	u32 coreclk, reg_val;
2327 Serge 7331
 
6084 serge 7332
	mutex_lock(&dev_priv->sb_lock);
3480 Serge 7333
 
5354 serge 7334
	bestn = pipe_config->dpll.n;
7335
	bestm1 = pipe_config->dpll.m1;
7336
	bestm2 = pipe_config->dpll.m2;
7337
	bestp1 = pipe_config->dpll.p1;
7338
	bestp2 = pipe_config->dpll.p2;
3031 serge 7339
 
4104 Serge 7340
	/* See eDP HDMI DPIO driver vbios notes doc */
7341
 
7342
	/* PLL B needs special handling */
5060 serge 7343
	if (pipe == PIPE_B)
4560 Serge 7344
		vlv_pllb_recal_opamp(dev_priv, pipe);
4104 Serge 7345
 
7346
	/* Set up Tx target for periodic Rcomp update */
4560 Serge 7347
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4104 Serge 7348
 
7349
	/* Disable target IRef on PLL */
4560 Serge 7350
	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4104 Serge 7351
	reg_val &= 0x00ffffff;
4560 Serge 7352
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4104 Serge 7353
 
7354
	/* Disable fast lock */
4560 Serge 7355
	vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4104 Serge 7356
 
7357
	/* Set idtafcrecal before PLL is enabled */
3031 serge 7358
	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7359
	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7360
	mdiv |= ((bestn << DPIO_N_SHIFT));
7361
	mdiv |= (1 << DPIO_K_SHIFT);
4104 Serge 7362
 
7363
	/*
7364
	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7365
	 * but we don't support that).
7366
	 * Note: don't use the DAC post divider as it seems unstable.
7367
	 */
7368
	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4560 Serge 7369
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4104 Serge 7370
 
3031 serge 7371
	mdiv |= DPIO_ENABLE_CALIBRATION;
4560 Serge 7372
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
3031 serge 7373
 
4104 Serge 7374
	/* Set HBR and RBR LPF coefficients */
5354 serge 7375
	if (pipe_config->port_clock == 162000 ||
7376
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7377
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4560 Serge 7378
		vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4104 Serge 7379
				 0x009f0003);
7380
	else
4560 Serge 7381
		vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4104 Serge 7382
				 0x00d0000f);
3031 serge 7383
 
6084 serge 7384
	if (pipe_config->has_dp_encoder) {
4104 Serge 7385
		/* Use SSC source */
5060 serge 7386
		if (pipe == PIPE_A)
4560 Serge 7387
			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104 Serge 7388
					 0x0df40000);
7389
		else
4560 Serge 7390
			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104 Serge 7391
					 0x0df70000);
7392
	} else { /* HDMI or VGA */
7393
		/* Use bend source */
5060 serge 7394
		if (pipe == PIPE_A)
4560 Serge 7395
			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104 Serge 7396
					 0x0df70000);
7397
		else
4560 Serge 7398
			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104 Serge 7399
					 0x0df40000);
7400
	}
3031 serge 7401
 
4560 Serge 7402
	coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4104 Serge 7403
	coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5354 serge 7404
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7405
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4104 Serge 7406
		coreclk |= 0x01000000;
4560 Serge 7407
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
3031 serge 7408
 
4560 Serge 7409
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6084 serge 7410
	mutex_unlock(&dev_priv->sb_lock);
5060 serge 7411
}
4104 Serge 7412
 
6084 serge 7413
static void chv_compute_dpll(struct intel_crtc *crtc,
7414
			     struct intel_crtc_state *pipe_config)
5060 serge 7415
{
6084 serge 7416
	pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7417
		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5354 serge 7418
		DPLL_VCO_ENABLE;
7419
	if (crtc->pipe != PIPE_A)
7420
		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7421
 
7422
	pipe_config->dpll_hw_state.dpll_md =
7423
		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7424
}
7425
 
7426
static void chv_prepare_pll(struct intel_crtc *crtc,
6084 serge 7427
			    const struct intel_crtc_state *pipe_config)
5354 serge 7428
{
5060 serge 7429
	struct drm_device *dev = crtc->base.dev;
7430
	struct drm_i915_private *dev_priv = dev->dev_private;
7431
	int pipe = crtc->pipe;
7432
	int dpll_reg = DPLL(crtc->pipe);
7433
	enum dpio_channel port = vlv_pipe_to_channel(pipe);
6084 serge 7434
	u32 loopfilter, tribuf_calcntr;
5060 serge 7435
	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6084 serge 7436
	u32 dpio_val;
7437
	int vco;
5060 serge 7438
 
5354 serge 7439
	bestn = pipe_config->dpll.n;
7440
	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7441
	bestm1 = pipe_config->dpll.m1;
7442
	bestm2 = pipe_config->dpll.m2 >> 22;
7443
	bestp1 = pipe_config->dpll.p1;
7444
	bestp2 = pipe_config->dpll.p2;
6084 serge 7445
	vco = pipe_config->dpll.vco;
7446
	dpio_val = 0;
7447
	loopfilter = 0;
5060 serge 7448
 
4560 Serge 7449
	/*
5060 serge 7450
	 * Enable Refclk and SSC
4560 Serge 7451
	 */
5060 serge 7452
	I915_WRITE(dpll_reg,
5354 serge 7453
		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
3031 serge 7454
 
6084 serge 7455
	mutex_lock(&dev_priv->sb_lock);
3031 serge 7456
 
5060 serge 7457
	/* p1 and p2 divider */
7458
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7459
			5 << DPIO_CHV_S1_DIV_SHIFT |
7460
			bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7461
			bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7462
			1 << DPIO_CHV_K_DIV_SHIFT);
3243 Serge 7463
 
5060 serge 7464
	/* Feedback post-divider - m2 */
7465
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7466
 
7467
	/* Feedback refclk divider - n and m1 */
7468
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7469
			DPIO_CHV_M1_DIV_BY_2 |
7470
			1 << DPIO_CHV_N_DIV_SHIFT);
7471
 
7472
	/* M2 fraction division */
7473
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7474
 
7475
	/* M2 fraction division enable */
6084 serge 7476
	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7477
	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7478
	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7479
	if (bestm2_frac)
7480
		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7481
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
5060 serge 7482
 
6084 serge 7483
	/* Program digital lock detect threshold */
7484
	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7485
	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7486
					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7487
	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7488
	if (!bestm2_frac)
7489
		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7490
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7491
 
5060 serge 7492
	/* Loop filter */
6084 serge 7493
	if (vco == 5400000) {
7494
		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7495
		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7496
		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7497
		tribuf_calcntr = 0x9;
7498
	} else if (vco <= 6200000) {
7499
		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7500
		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7501
		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7502
		tribuf_calcntr = 0x9;
7503
	} else if (vco <= 6480000) {
7504
		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7505
		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7506
		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7507
		tribuf_calcntr = 0x8;
7508
	} else {
7509
		/* Not supported. Apply the same limits as in the max case */
7510
		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7511
		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7512
		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7513
		tribuf_calcntr = 0;
7514
	}
5060 serge 7515
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7516
 
6084 serge 7517
	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7518
	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7519
	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7520
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7521
 
5060 serge 7522
	/* AFC Recal */
7523
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7524
			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7525
			DPIO_AFC_RECAL);
7526
 
6084 serge 7527
	mutex_unlock(&dev_priv->sb_lock);
3031 serge 7528
}
7529
 
5354 serge 7530
/**
7531
 * vlv_force_pll_on - forcibly enable just the PLL
7532
 * @dev_priv: i915 private structure
7533
 * @pipe: pipe PLL to enable
7534
 * @dpll: PLL configuration
7535
 *
7536
 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7537
 * in cases where we need the PLL enabled even when @pipe is not going to
7538
 * be enabled.
7539
 */
7540
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7541
		      const struct dpll *dpll)
7542
{
7543
	struct intel_crtc *crtc =
7544
		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6084 serge 7545
	struct intel_crtc_state pipe_config = {
7546
		.base.crtc = &crtc->base,
5354 serge 7547
		.pixel_multiplier = 1,
7548
		.dpll = *dpll,
7549
	};
7550
 
7551
	if (IS_CHERRYVIEW(dev)) {
6084 serge 7552
		chv_compute_dpll(crtc, &pipe_config);
5354 serge 7553
		chv_prepare_pll(crtc, &pipe_config);
7554
		chv_enable_pll(crtc, &pipe_config);
7555
	} else {
6084 serge 7556
		vlv_compute_dpll(crtc, &pipe_config);
5354 serge 7557
		vlv_prepare_pll(crtc, &pipe_config);
7558
		vlv_enable_pll(crtc, &pipe_config);
7559
	}
7560
}
7561
 
7562
/**
7563
 * vlv_force_pll_off - forcibly disable just the PLL
7564
 * @dev_priv: i915 private structure
7565
 * @pipe: pipe PLL to disable
7566
 *
7567
 * Disable the PLL for @pipe. To be used in cases where we need
7568
 * the PLL enabled even when @pipe is not going to be enabled.
7569
 */
7570
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7571
{
7572
	if (IS_CHERRYVIEW(dev))
7573
		chv_disable_pll(to_i915(dev), pipe);
7574
	else
7575
		vlv_disable_pll(to_i915(dev), pipe);
7576
}
7577
 
6084 serge 7578
static void i9xx_compute_dpll(struct intel_crtc *crtc,
7579
			      struct intel_crtc_state *crtc_state,
7580
			      intel_clock_t *reduced_clock,
7581
			      int num_connectors)
3031 serge 7582
{
3746 Serge 7583
	struct drm_device *dev = crtc->base.dev;
3031 serge 7584
	struct drm_i915_private *dev_priv = dev->dev_private;
7585
	u32 dpll;
7586
	bool is_sdvo;
6084 serge 7587
	struct dpll *clock = &crtc_state->dpll;
3031 serge 7588
 
6084 serge 7589
	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
3243 Serge 7590
 
6084 serge 7591
	is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7592
		intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
3031 serge 7593
 
7594
	dpll = DPLL_VGA_MODE_DIS;
7595
 
6084 serge 7596
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
3031 serge 7597
		dpll |= DPLLB_MODE_LVDS;
7598
	else
7599
		dpll |= DPLLB_MODE_DAC_SERIAL;
3746 Serge 7600
 
4104 Serge 7601
	if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6084 serge 7602
		dpll |= (crtc_state->pixel_multiplier - 1)
7603
			<< SDVO_MULTIPLIER_SHIFT_HIRES;
7604
	}
4104 Serge 7605
 
7606
	if (is_sdvo)
7607
		dpll |= DPLL_SDVO_HIGH_SPEED;
7608
 
6084 serge 7609
	if (crtc_state->has_dp_encoder)
4104 Serge 7610
		dpll |= DPLL_SDVO_HIGH_SPEED;
2342 Serge 7611
 
3031 serge 7612
	/* compute bitmask from p1 value */
7613
	if (IS_PINEVIEW(dev))
7614
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7615
	else {
7616
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7617
		if (IS_G4X(dev) && reduced_clock)
7618
			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7619
	}
7620
	switch (clock->p2) {
7621
	case 5:
7622
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7623
		break;
7624
	case 7:
7625
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7626
		break;
7627
	case 10:
7628
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7629
		break;
7630
	case 14:
7631
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7632
		break;
7633
	}
7634
	if (INTEL_INFO(dev)->gen >= 4)
7635
		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327 Serge 7636
 
6084 serge 7637
	if (crtc_state->sdvo_tv_clock)
3031 serge 7638
		dpll |= PLL_REF_INPUT_TVCLKINBC;
6084 serge 7639
	else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
3031 serge 7640
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7641
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7642
	else
7643
		dpll |= PLL_REF_INPUT_DREFCLK;
2327 Serge 7644
 
3031 serge 7645
	dpll |= DPLL_VCO_ENABLE;
6084 serge 7646
	crtc_state->dpll_hw_state.dpll = dpll;
2327 Serge 7647
 
4104 Serge 7648
	if (INTEL_INFO(dev)->gen >= 4) {
6084 serge 7649
		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7650
			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
7651
		crtc_state->dpll_hw_state.dpll_md = dpll_md;
4104 Serge 7652
	}
3031 serge 7653
}
2327 Serge 7654
 
6084 serge 7655
static void i8xx_compute_dpll(struct intel_crtc *crtc,
7656
			      struct intel_crtc_state *crtc_state,
7657
			      intel_clock_t *reduced_clock,
7658
			      int num_connectors)
3031 serge 7659
{
3746 Serge 7660
	struct drm_device *dev = crtc->base.dev;
3031 serge 7661
	struct drm_i915_private *dev_priv = dev->dev_private;
7662
	u32 dpll;
6084 serge 7663
	struct dpll *clock = &crtc_state->dpll;
2327 Serge 7664
 
6084 serge 7665
	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
3243 Serge 7666
 
3031 serge 7667
	dpll = DPLL_VGA_MODE_DIS;
2327 Serge 7668
 
6084 serge 7669
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
3031 serge 7670
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7671
	} else {
7672
		if (clock->p1 == 2)
7673
			dpll |= PLL_P1_DIVIDE_BY_TWO;
7674
		else
7675
			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7676
		if (clock->p2 == 4)
7677
			dpll |= PLL_P2_DIVIDE_BY_4;
7678
	}
2327 Serge 7679
 
6084 serge 7680
	if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4104 Serge 7681
		dpll |= DPLL_DVO_2X_MODE;
7682
 
6084 serge 7683
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
3031 serge 7684
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7685
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7686
	else
7687
		dpll |= PLL_REF_INPUT_DREFCLK;
7688
 
7689
	dpll |= DPLL_VCO_ENABLE;
6084 serge 7690
	crtc_state->dpll_hw_state.dpll = dpll;
3031 serge 7691
}
7692
 
4104 Serge 7693
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
3243 Serge 7694
{
7695
	struct drm_device *dev = intel_crtc->base.dev;
7696
	struct drm_i915_private *dev_priv = dev->dev_private;
7697
	enum pipe pipe = intel_crtc->pipe;
6084 serge 7698
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7699
	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
5060 serge 7700
	uint32_t crtc_vtotal, crtc_vblank_end;
7701
	int vsyncshift = 0;
3243 Serge 7702
 
4104 Serge 7703
	/* We need to be careful not to changed the adjusted mode, for otherwise
7704
	 * the hw state checker will get angry at the mismatch. */
7705
	crtc_vtotal = adjusted_mode->crtc_vtotal;
7706
	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7707
 
5060 serge 7708
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3243 Serge 7709
		/* the chip adds 2 halflines automatically */
4104 Serge 7710
		crtc_vtotal -= 1;
7711
		crtc_vblank_end -= 1;
5060 serge 7712
 
5354 serge 7713
		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
5060 serge 7714
			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7715
		else
7716
			vsyncshift = adjusted_mode->crtc_hsync_start -
7717
				adjusted_mode->crtc_htotal / 2;
7718
		if (vsyncshift < 0)
7719
			vsyncshift += adjusted_mode->crtc_htotal;
3243 Serge 7720
	}
7721
 
7722
	if (INTEL_INFO(dev)->gen > 3)
7723
		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7724
 
7725
	I915_WRITE(HTOTAL(cpu_transcoder),
7726
		   (adjusted_mode->crtc_hdisplay - 1) |
7727
		   ((adjusted_mode->crtc_htotal - 1) << 16));
7728
	I915_WRITE(HBLANK(cpu_transcoder),
7729
		   (adjusted_mode->crtc_hblank_start - 1) |
7730
		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
7731
	I915_WRITE(HSYNC(cpu_transcoder),
7732
		   (adjusted_mode->crtc_hsync_start - 1) |
7733
		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
7734
 
7735
	I915_WRITE(VTOTAL(cpu_transcoder),
7736
		   (adjusted_mode->crtc_vdisplay - 1) |
4104 Serge 7737
		   ((crtc_vtotal - 1) << 16));
3243 Serge 7738
	I915_WRITE(VBLANK(cpu_transcoder),
7739
		   (adjusted_mode->crtc_vblank_start - 1) |
4104 Serge 7740
		   ((crtc_vblank_end - 1) << 16));
3243 Serge 7741
	I915_WRITE(VSYNC(cpu_transcoder),
7742
		   (adjusted_mode->crtc_vsync_start - 1) |
7743
		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
7744
 
7745
	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7746
	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7747
	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7748
	 * bits. */
7749
	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7750
	    (pipe == PIPE_B || pipe == PIPE_C))
7751
		I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7752
 
7753
	/* pipesrc controls the size that is scaled from, which should
7754
	 * always be the user's requested size.
7755
	 */
7756
	I915_WRITE(PIPESRC(pipe),
6084 serge 7757
		   ((intel_crtc->config->pipe_src_w - 1) << 16) |
7758
		   (intel_crtc->config->pipe_src_h - 1));
3243 Serge 7759
}
7760
 
4104 Serge 7761
static void intel_get_pipe_timings(struct intel_crtc *crtc,
6084 serge 7762
				   struct intel_crtc_state *pipe_config)
4104 Serge 7763
{
7764
	struct drm_device *dev = crtc->base.dev;
7765
	struct drm_i915_private *dev_priv = dev->dev_private;
7766
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7767
	uint32_t tmp;
7768
 
7769
	tmp = I915_READ(HTOTAL(cpu_transcoder));
6084 serge 7770
	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7771
	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4104 Serge 7772
	tmp = I915_READ(HBLANK(cpu_transcoder));
6084 serge 7773
	pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7774
	pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4104 Serge 7775
	tmp = I915_READ(HSYNC(cpu_transcoder));
6084 serge 7776
	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7777
	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4104 Serge 7778
 
7779
	tmp = I915_READ(VTOTAL(cpu_transcoder));
6084 serge 7780
	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7781
	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4104 Serge 7782
	tmp = I915_READ(VBLANK(cpu_transcoder));
6084 serge 7783
	pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7784
	pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4104 Serge 7785
	tmp = I915_READ(VSYNC(cpu_transcoder));
6084 serge 7786
	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7787
	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4104 Serge 7788
 
7789
	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6084 serge 7790
		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7791
		pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7792
		pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
4104 Serge 7793
	}
7794
 
7795
	tmp = I915_READ(PIPESRC(crtc->pipe));
4560 Serge 7796
	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7797
	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7798
 
6084 serge 7799
	pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7800
	pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
4104 Serge 7801
}
7802
 
5060 serge 7803
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6084 serge 7804
				 struct intel_crtc_state *pipe_config)
4104 Serge 7805
{
6084 serge 7806
	mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7807
	mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7808
	mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7809
	mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
4104 Serge 7810
 
6084 serge 7811
	mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7812
	mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7813
	mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7814
	mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
4104 Serge 7815
 
6084 serge 7816
	mode->flags = pipe_config->base.adjusted_mode.flags;
7817
	mode->type = DRM_MODE_TYPE_DRIVER;
4104 Serge 7818
 
6084 serge 7819
	mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7820
	mode->flags |= pipe_config->base.adjusted_mode.flags;
7821
 
7822
	mode->hsync = drm_mode_hsync(mode);
7823
	mode->vrefresh = drm_mode_vrefresh(mode);
7824
	drm_mode_set_name(mode);
4104 Serge 7825
}
7826
 
3746 Serge 7827
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7828
{
7829
	struct drm_device *dev = intel_crtc->base.dev;
7830
	struct drm_i915_private *dev_priv = dev->dev_private;
7831
	uint32_t pipeconf;
7832
 
4104 Serge 7833
	pipeconf = 0;
3746 Serge 7834
 
5354 serge 7835
	if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7836
	    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7837
		pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
4104 Serge 7838
 
6084 serge 7839
	if (intel_crtc->config->double_wide)
7840
		pipeconf |= PIPECONF_DOUBLE_WIDE;
3746 Serge 7841
 
4104 Serge 7842
	/* only g4x and later have fancy bpc/dither controls */
7843
	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7844
		/* Bspec claims that we can't use dithering for 30bpp pipes. */
6084 serge 7845
		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
4104 Serge 7846
			pipeconf |= PIPECONF_DITHER_EN |
3746 Serge 7847
				    PIPECONF_DITHER_TYPE_SP;
7848
 
6084 serge 7849
		switch (intel_crtc->config->pipe_bpp) {
4104 Serge 7850
		case 18:
7851
			pipeconf |= PIPECONF_6BPC;
7852
			break;
7853
		case 24:
7854
			pipeconf |= PIPECONF_8BPC;
7855
			break;
7856
		case 30:
7857
			pipeconf |= PIPECONF_10BPC;
7858
			break;
7859
		default:
7860
			/* Case prevented by intel_choose_pipe_bpp_dither. */
7861
			BUG();
3746 Serge 7862
		}
7863
	}
7864
 
7865
	if (HAS_PIPE_CXSR(dev)) {
7866
		if (intel_crtc->lowfreq_avail) {
7867
			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7868
			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7869
		} else {
7870
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7871
		}
7872
	}
7873
 
6084 serge 7874
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5060 serge 7875
		if (INTEL_INFO(dev)->gen < 4 ||
5354 serge 7876
		    intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6084 serge 7877
			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7878
		else
5060 serge 7879
			pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7880
	} else
3746 Serge 7881
		pipeconf |= PIPECONF_PROGRESSIVE;
7882
 
6084 serge 7883
	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7884
		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
3746 Serge 7885
 
7886
	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7887
	POSTING_READ(PIPECONF(intel_crtc->pipe));
7888
}
7889
 
6084 serge 7890
static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7891
				   struct intel_crtc_state *crtc_state)
3031 serge 7892
{
5354 serge 7893
	struct drm_device *dev = crtc->base.dev;
3031 serge 7894
	struct drm_i915_private *dev_priv = dev->dev_private;
7895
	int refclk, num_connectors = 0;
6084 serge 7896
	intel_clock_t clock;
7897
	bool ok;
7898
	bool is_dsi = false;
3031 serge 7899
	struct intel_encoder *encoder;
7900
	const intel_limit_t *limit;
6084 serge 7901
	struct drm_atomic_state *state = crtc_state->base.state;
7902
	struct drm_connector *connector;
7903
	struct drm_connector_state *connector_state;
7904
	int i;
3031 serge 7905
 
6084 serge 7906
	memset(&crtc_state->dpll_hw_state, 0,
7907
	       sizeof(crtc_state->dpll_hw_state));
7908
 
7909
	for_each_connector_in_state(state, connector, connector_state, i) {
7910
		if (connector_state->crtc != &crtc->base)
5354 serge 7911
			continue;
7912
 
6084 serge 7913
		encoder = to_intel_encoder(connector_state->best_encoder);
7914
 
3031 serge 7915
		switch (encoder->type) {
4560 Serge 7916
		case INTEL_OUTPUT_DSI:
7917
			is_dsi = true;
7918
			break;
5354 serge 7919
		default:
7920
			break;
3031 serge 7921
		}
7922
 
7923
		num_connectors++;
7924
	}
7925
 
4560 Serge 7926
	if (is_dsi)
5060 serge 7927
		return 0;
4560 Serge 7928
 
6084 serge 7929
	if (!crtc_state->clock_set) {
7930
		refclk = i9xx_get_refclk(crtc_state, num_connectors);
3031 serge 7931
 
6084 serge 7932
		/*
4560 Serge 7933
		 * Returns a set of divisors for the desired target clock with
7934
		 * the given refclk, or FALSE.  The returned values represent
7935
		 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7936
		 * 2) / p1 / p2.
6084 serge 7937
		 */
7938
		limit = intel_limit(crtc_state, refclk);
7939
		ok = dev_priv->display.find_dpll(limit, crtc_state,
7940
						 crtc_state->port_clock,
7941
						 refclk, NULL, &clock);
4560 Serge 7942
		if (!ok) {
6084 serge 7943
			DRM_ERROR("Couldn't find PLL settings for mode!\n");
7944
			return -EINVAL;
7945
		}
3031 serge 7946
 
6084 serge 7947
		/* Compat-code for transition, will disappear. */
7948
		crtc_state->dpll.n = clock.n;
7949
		crtc_state->dpll.m1 = clock.m1;
7950
		crtc_state->dpll.m2 = clock.m2;
7951
		crtc_state->dpll.p1 = clock.p1;
7952
		crtc_state->dpll.p2 = clock.p2;
3031 serge 7953
	}
7954
 
4560 Serge 7955
	if (IS_GEN2(dev)) {
6084 serge 7956
		i8xx_compute_dpll(crtc, crtc_state, NULL,
7957
				  num_connectors);
5060 serge 7958
	} else if (IS_CHERRYVIEW(dev)) {
6084 serge 7959
		chv_compute_dpll(crtc, crtc_state);
4560 Serge 7960
	} else if (IS_VALLEYVIEW(dev)) {
6084 serge 7961
		vlv_compute_dpll(crtc, crtc_state);
4560 Serge 7962
	} else {
6084 serge 7963
		i9xx_compute_dpll(crtc, crtc_state, NULL,
7964
				  num_connectors);
4560 Serge 7965
	}
3031 serge 7966
 
5060 serge 7967
	return 0;
2327 Serge 7968
}
7969
 
4104 Serge 7970
static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6084 serge 7971
				 struct intel_crtc_state *pipe_config)
4104 Serge 7972
{
7973
	struct drm_device *dev = crtc->base.dev;
7974
	struct drm_i915_private *dev_priv = dev->dev_private;
7975
	uint32_t tmp;
7976
 
4560 Serge 7977
	if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7978
		return;
7979
 
4104 Serge 7980
	tmp = I915_READ(PFIT_CONTROL);
7981
	if (!(tmp & PFIT_ENABLE))
7982
		return;
7983
 
7984
	/* Check whether the pfit is attached to our pipe. */
7985
	if (INTEL_INFO(dev)->gen < 4) {
7986
		if (crtc->pipe != PIPE_B)
7987
			return;
7988
	} else {
7989
		if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7990
			return;
7991
	}
7992
 
7993
	pipe_config->gmch_pfit.control = tmp;
7994
	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7995
	if (INTEL_INFO(dev)->gen < 5)
7996
		pipe_config->gmch_pfit.lvds_border_bits =
7997
			I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7998
}
7999
 
4398 Serge 8000
static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6084 serge 8001
			       struct intel_crtc_state *pipe_config)
4398 Serge 8002
{
8003
	struct drm_device *dev = crtc->base.dev;
8004
	struct drm_i915_private *dev_priv = dev->dev_private;
8005
	int pipe = pipe_config->cpu_transcoder;
8006
	intel_clock_t clock;
8007
	u32 mdiv;
8008
	int refclk = 100000;
8009
 
5060 serge 8010
	/* In case of MIPI DPLL will not even be used */
8011
	if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8012
		return;
8013
 
6084 serge 8014
	mutex_lock(&dev_priv->sb_lock);
4560 Serge 8015
	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6084 serge 8016
	mutex_unlock(&dev_priv->sb_lock);
4398 Serge 8017
 
8018
	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8019
	clock.m2 = mdiv & DPIO_M2DIV_MASK;
8020
	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8021
	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8022
	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8023
 
6084 serge 8024
	pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
4398 Serge 8025
}
8026
 
6084 serge 8027
static void
8028
i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8029
			      struct intel_initial_plane_config *plane_config)
5060 serge 8030
{
8031
	struct drm_device *dev = crtc->base.dev;
8032
	struct drm_i915_private *dev_priv = dev->dev_private;
8033
	u32 val, base, offset;
8034
	int pipe = crtc->pipe, plane = crtc->plane;
8035
	int fourcc, pixel_format;
6084 serge 8036
	unsigned int aligned_height;
8037
	struct drm_framebuffer *fb;
8038
	struct intel_framebuffer *intel_fb;
5060 serge 8039
 
6084 serge 8040
	val = I915_READ(DSPCNTR(plane));
8041
	if (!(val & DISPLAY_PLANE_ENABLE))
8042
		return;
8043
 
8044
	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8045
	if (!intel_fb) {
5060 serge 8046
		DRM_DEBUG_KMS("failed to alloc fb\n");
8047
		return;
8048
	}
8049
 
6084 serge 8050
	fb = &intel_fb->base;
5060 serge 8051
 
6084 serge 8052
	if (INTEL_INFO(dev)->gen >= 4) {
8053
		if (val & DISPPLANE_TILED) {
8054
			plane_config->tiling = I915_TILING_X;
8055
			fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8056
		}
8057
	}
5060 serge 8058
 
8059
	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6084 serge 8060
	fourcc = i9xx_format_to_fourcc(pixel_format);
8061
	fb->pixel_format = fourcc;
8062
	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
5060 serge 8063
 
8064
	if (INTEL_INFO(dev)->gen >= 4) {
6084 serge 8065
		if (plane_config->tiling)
5060 serge 8066
			offset = I915_READ(DSPTILEOFF(plane));
8067
		else
8068
			offset = I915_READ(DSPLINOFF(plane));
8069
		base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8070
	} else {
8071
		base = I915_READ(DSPADDR(plane));
8072
	}
8073
	plane_config->base = base;
8074
 
8075
	val = I915_READ(PIPESRC(pipe));
6084 serge 8076
	fb->width = ((val >> 16) & 0xfff) + 1;
8077
	fb->height = ((val >> 0) & 0xfff) + 1;
5060 serge 8078
 
8079
	val = I915_READ(DSPSTRIDE(pipe));
6283 serge 8080
	fb->pitches[0] = val & 0xffffffc0;
5060 serge 8081
 
6084 serge 8082
	aligned_height = intel_fb_align_height(dev, fb->height,
8083
					       fb->pixel_format,
8084
					       fb->modifier[0]);
5060 serge 8085
 
6283 serge 8086
	plane_config->size = fb->pitches[0] * aligned_height;
5060 serge 8087
 
6084 serge 8088
	DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8089
		      pipe_name(pipe), plane, fb->width, fb->height,
8090
		      fb->bits_per_pixel, base, fb->pitches[0],
5060 serge 8091
		      plane_config->size);
8092
 
6084 serge 8093
	plane_config->fb = intel_fb;
5060 serge 8094
}
8095
 
8096
static void chv_crtc_clock_get(struct intel_crtc *crtc,
6084 serge 8097
			       struct intel_crtc_state *pipe_config)
5060 serge 8098
{
8099
	struct drm_device *dev = crtc->base.dev;
8100
	struct drm_i915_private *dev_priv = dev->dev_private;
8101
	int pipe = pipe_config->cpu_transcoder;
8102
	enum dpio_channel port = vlv_pipe_to_channel(pipe);
8103
	intel_clock_t clock;
6084 serge 8104
	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
5060 serge 8105
	int refclk = 100000;
8106
 
6084 serge 8107
	mutex_lock(&dev_priv->sb_lock);
5060 serge 8108
	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8109
	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8110
	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8111
	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6084 serge 8112
	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8113
	mutex_unlock(&dev_priv->sb_lock);
5060 serge 8114
 
8115
	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6084 serge 8116
	clock.m2 = (pll_dw0 & 0xff) << 22;
8117
	if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8118
		clock.m2 |= pll_dw2 & 0x3fffff;
5060 serge 8119
	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8120
	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8121
	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8122
 
6084 serge 8123
	pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
5060 serge 8124
}
8125
 
3746 Serge 8126
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6084 serge 8127
				 struct intel_crtc_state *pipe_config)
3746 Serge 8128
{
8129
	struct drm_device *dev = crtc->base.dev;
8130
	struct drm_i915_private *dev_priv = dev->dev_private;
8131
	uint32_t tmp;
8132
 
5354 serge 8133
	if (!intel_display_power_is_enabled(dev_priv,
6084 serge 8134
					    POWER_DOMAIN_PIPE(crtc->pipe)))
5060 serge 8135
		return false;
8136
 
4104 Serge 8137
	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8138
	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8139
 
3746 Serge 8140
	tmp = I915_READ(PIPECONF(crtc->pipe));
8141
	if (!(tmp & PIPECONF_ENABLE))
8142
		return false;
8143
 
4280 Serge 8144
	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8145
		switch (tmp & PIPECONF_BPC_MASK) {
8146
		case PIPECONF_6BPC:
8147
			pipe_config->pipe_bpp = 18;
8148
			break;
8149
		case PIPECONF_8BPC:
8150
			pipe_config->pipe_bpp = 24;
8151
			break;
8152
		case PIPECONF_10BPC:
8153
			pipe_config->pipe_bpp = 30;
8154
			break;
8155
		default:
8156
			break;
8157
		}
8158
	}
8159
 
5060 serge 8160
	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8161
		pipe_config->limited_color_range = true;
8162
 
4560 Serge 8163
	if (INTEL_INFO(dev)->gen < 4)
8164
		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8165
 
4104 Serge 8166
	intel_get_pipe_timings(crtc, pipe_config);
8167
 
8168
	i9xx_get_pfit_config(crtc, pipe_config);
8169
 
8170
	if (INTEL_INFO(dev)->gen >= 4) {
8171
		tmp = I915_READ(DPLL_MD(crtc->pipe));
8172
		pipe_config->pixel_multiplier =
8173
			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8174
			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8175
		pipe_config->dpll_hw_state.dpll_md = tmp;
8176
	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8177
		tmp = I915_READ(DPLL(crtc->pipe));
8178
		pipe_config->pixel_multiplier =
8179
			((tmp & SDVO_MULTIPLIER_MASK)
8180
			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8181
	} else {
8182
		/* Note that on i915G/GM the pixel multiplier is in the sdvo
8183
		 * port and will be fixed up in the encoder->get_config
8184
		 * function. */
8185
		pipe_config->pixel_multiplier = 1;
8186
	}
8187
	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8188
	if (!IS_VALLEYVIEW(dev)) {
5354 serge 8189
		/*
8190
		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8191
		 * on 830. Filter it out here so that we don't
8192
		 * report errors due to that.
8193
		 */
8194
		if (IS_I830(dev))
8195
			pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8196
 
4104 Serge 8197
		pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8198
		pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8199
	} else {
8200
		/* Mask out read-only status bits. */
8201
		pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8202
						     DPLL_PORTC_READY_MASK |
8203
						     DPLL_PORTB_READY_MASK);
8204
	}
8205
 
5060 serge 8206
	if (IS_CHERRYVIEW(dev))
8207
		chv_crtc_clock_get(crtc, pipe_config);
8208
	else if (IS_VALLEYVIEW(dev))
4560 Serge 8209
		vlv_crtc_clock_get(crtc, pipe_config);
8210
	else
8211
		i9xx_crtc_clock_get(crtc, pipe_config);
8212
 
6084 serge 8213
	/*
8214
	 * Normally the dotclock is filled in by the encoder .get_config()
8215
	 * but in case the pipe is enabled w/o any ports we need a sane
8216
	 * default.
8217
	 */
8218
	pipe_config->base.adjusted_mode.crtc_clock =
8219
		pipe_config->port_clock / pipe_config->pixel_multiplier;
8220
 
3746 Serge 8221
	return true;
8222
}
8223
 
3243 Serge 8224
static void ironlake_init_pch_refclk(struct drm_device *dev)
2327 Serge 8225
{
8226
	struct drm_i915_private *dev_priv = dev->dev_private;
8227
	struct intel_encoder *encoder;
3746 Serge 8228
	u32 val, final;
2327 Serge 8229
	bool has_lvds = false;
2342 Serge 8230
	bool has_cpu_edp = false;
8231
	bool has_panel = false;
8232
	bool has_ck505 = false;
8233
	bool can_ssc = false;
2327 Serge 8234
 
8235
	/* We need to take the global config into account */
5354 serge 8236
	for_each_intel_encoder(dev, encoder) {
6084 serge 8237
		switch (encoder->type) {
8238
		case INTEL_OUTPUT_LVDS:
2342 Serge 8239
			has_panel = true;
6084 serge 8240
			has_lvds = true;
2342 Serge 8241
			break;
6084 serge 8242
		case INTEL_OUTPUT_EDP:
2342 Serge 8243
			has_panel = true;
4104 Serge 8244
			if (enc_to_dig_port(&encoder->base)->port == PORT_A)
2342 Serge 8245
				has_cpu_edp = true;
6084 serge 8246
			break;
5354 serge 8247
		default:
8248
			break;
2327 Serge 8249
		}
6084 serge 8250
	}
2342 Serge 8251
 
8252
	if (HAS_PCH_IBX(dev)) {
4104 Serge 8253
		has_ck505 = dev_priv->vbt.display_clock_mode;
2342 Serge 8254
		can_ssc = has_ck505;
8255
	} else {
8256
		has_ck505 = false;
8257
		can_ssc = true;
2327 Serge 8258
	}
8259
 
4104 Serge 8260
	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8261
		      has_panel, has_lvds, has_ck505);
2342 Serge 8262
 
2327 Serge 8263
	/* Ironlake: try to setup display ref clock before DPLL
8264
	 * enabling. This is only under driver's control after
8265
	 * PCH B stepping, previous chipset stepping should be
8266
	 * ignoring this setting.
8267
	 */
3746 Serge 8268
	val = I915_READ(PCH_DREF_CONTROL);
8269
 
8270
	/* As we must carefully and slowly disable/enable each source in turn,
8271
	 * compute the final state we want first and check if we need to
8272
	 * make any changes at all.
8273
	 */
8274
	final = val;
8275
	final &= ~DREF_NONSPREAD_SOURCE_MASK;
8276
	if (has_ck505)
8277
		final |= DREF_NONSPREAD_CK505_ENABLE;
8278
	else
8279
		final |= DREF_NONSPREAD_SOURCE_ENABLE;
8280
 
8281
	final &= ~DREF_SSC_SOURCE_MASK;
8282
	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8283
	final &= ~DREF_SSC1_ENABLE;
8284
 
8285
	if (has_panel) {
8286
		final |= DREF_SSC_SOURCE_ENABLE;
8287
 
8288
		if (intel_panel_use_ssc(dev_priv) && can_ssc)
8289
			final |= DREF_SSC1_ENABLE;
8290
 
8291
		if (has_cpu_edp) {
8292
			if (intel_panel_use_ssc(dev_priv) && can_ssc)
8293
				final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8294
			else
8295
				final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8296
		} else
8297
			final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8298
	} else {
8299
		final |= DREF_SSC_SOURCE_DISABLE;
8300
		final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8301
	}
8302
 
8303
	if (final == val)
8304
		return;
8305
 
2327 Serge 8306
	/* Always enable nonspread source */
3746 Serge 8307
	val &= ~DREF_NONSPREAD_SOURCE_MASK;
2342 Serge 8308
 
8309
	if (has_ck505)
3746 Serge 8310
		val |= DREF_NONSPREAD_CK505_ENABLE;
2342 Serge 8311
	else
3746 Serge 8312
		val |= DREF_NONSPREAD_SOURCE_ENABLE;
2342 Serge 8313
 
8314
	if (has_panel) {
3746 Serge 8315
		val &= ~DREF_SSC_SOURCE_MASK;
8316
		val |= DREF_SSC_SOURCE_ENABLE;
2327 Serge 8317
 
2342 Serge 8318
		/* SSC must be turned on before enabling the CPU output  */
8319
		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8320
			DRM_DEBUG_KMS("Using SSC on panel\n");
3746 Serge 8321
			val |= DREF_SSC1_ENABLE;
3031 serge 8322
		} else
3746 Serge 8323
			val &= ~DREF_SSC1_ENABLE;
2327 Serge 8324
 
2342 Serge 8325
		/* Get SSC going before enabling the outputs */
3746 Serge 8326
		I915_WRITE(PCH_DREF_CONTROL, val);
6084 serge 8327
		POSTING_READ(PCH_DREF_CONTROL);
8328
		udelay(200);
2342 Serge 8329
 
3746 Serge 8330
		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2327 Serge 8331
 
8332
		/* Enable CPU source on CPU attached eDP */
2342 Serge 8333
		if (has_cpu_edp) {
8334
			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8335
				DRM_DEBUG_KMS("Using SSC on eDP\n");
3746 Serge 8336
				val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5060 serge 8337
			} else
3746 Serge 8338
				val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342 Serge 8339
		} else
3746 Serge 8340
			val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342 Serge 8341
 
3746 Serge 8342
		I915_WRITE(PCH_DREF_CONTROL, val);
2342 Serge 8343
		POSTING_READ(PCH_DREF_CONTROL);
8344
		udelay(200);
6084 serge 8345
	} else {
2342 Serge 8346
		DRM_DEBUG_KMS("Disabling SSC entirely\n");
8347
 
3746 Serge 8348
		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2342 Serge 8349
 
8350
		/* Turn off CPU output */
3746 Serge 8351
		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342 Serge 8352
 
3746 Serge 8353
		I915_WRITE(PCH_DREF_CONTROL, val);
2327 Serge 8354
		POSTING_READ(PCH_DREF_CONTROL);
8355
		udelay(200);
2342 Serge 8356
 
8357
		/* Turn off the SSC source */
3746 Serge 8358
		val &= ~DREF_SSC_SOURCE_MASK;
8359
		val |= DREF_SSC_SOURCE_DISABLE;
2342 Serge 8360
 
8361
		/* Turn off SSC1 */
3746 Serge 8362
		val &= ~DREF_SSC1_ENABLE;
2342 Serge 8363
 
3746 Serge 8364
		I915_WRITE(PCH_DREF_CONTROL, val);
2342 Serge 8365
		POSTING_READ(PCH_DREF_CONTROL);
8366
		udelay(200);
2327 Serge 8367
	}
3746 Serge 8368
 
8369
	BUG_ON(val != final);
2327 Serge 8370
}
8371
 
4104 Serge 8372
static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
3243 Serge 8373
{
4104 Serge 8374
	uint32_t tmp;
3243 Serge 8375
 
6084 serge 8376
	tmp = I915_READ(SOUTH_CHICKEN2);
8377
	tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8378
	I915_WRITE(SOUTH_CHICKEN2, tmp);
3243 Serge 8379
 
6084 serge 8380
	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8381
			       FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8382
		DRM_ERROR("FDI mPHY reset assert timeout\n");
3243 Serge 8383
 
6084 serge 8384
	tmp = I915_READ(SOUTH_CHICKEN2);
8385
	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8386
	I915_WRITE(SOUTH_CHICKEN2, tmp);
3243 Serge 8387
 
6084 serge 8388
	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4104 Serge 8389
				FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6084 serge 8390
		DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4539 Serge 8391
}
3243 Serge 8392
 
4104 Serge 8393
/* WaMPhyProgramming:hsw */
8394
static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8395
{
8396
	uint32_t tmp;
8397
 
3243 Serge 8398
	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8399
	tmp &= ~(0xFF << 24);
8400
	tmp |= (0x12 << 24);
8401
	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8402
 
8403
	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8404
	tmp |= (1 << 11);
8405
	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8406
 
8407
	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8408
	tmp |= (1 << 11);
8409
	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8410
 
8411
	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8412
	tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8413
	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8414
 
8415
	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8416
	tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8417
	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8418
 
6084 serge 8419
	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8420
	tmp &= ~(7 << 13);
8421
	tmp |= (5 << 13);
8422
	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
3243 Serge 8423
 
6084 serge 8424
	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8425
	tmp &= ~(7 << 13);
8426
	tmp |= (5 << 13);
8427
	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
3243 Serge 8428
 
8429
	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8430
	tmp &= ~0xFF;
8431
	tmp |= 0x1C;
8432
	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8433
 
8434
	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8435
	tmp &= ~0xFF;
8436
	tmp |= 0x1C;
8437
	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8438
 
8439
	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8440
	tmp &= ~(0xFF << 16);
8441
	tmp |= (0x1C << 16);
8442
	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8443
 
8444
	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8445
	tmp &= ~(0xFF << 16);
8446
	tmp |= (0x1C << 16);
8447
	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8448
 
6084 serge 8449
	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8450
	tmp |= (1 << 27);
8451
	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
3243 Serge 8452
 
6084 serge 8453
	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8454
	tmp |= (1 << 27);
8455
	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
3243 Serge 8456
 
6084 serge 8457
	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8458
	tmp &= ~(0xF << 28);
8459
	tmp |= (4 << 28);
8460
	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
3243 Serge 8461
 
6084 serge 8462
	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8463
	tmp &= ~(0xF << 28);
8464
	tmp |= (4 << 28);
8465
	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
4539 Serge 8466
}
3243 Serge 8467
 
4104 Serge 8468
/* Implements 3 different sequences from BSpec chapter "Display iCLK
8469
 * Programming" based on the parameters passed:
8470
 * - Sequence to enable CLKOUT_DP
8471
 * - Sequence to enable CLKOUT_DP without spread
8472
 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8473
 */
8474
static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8475
				 bool with_fdi)
8476
{
8477
	struct drm_i915_private *dev_priv = dev->dev_private;
8478
	uint32_t reg, tmp;
3480 Serge 8479
 
4104 Serge 8480
	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8481
		with_spread = true;
6084 serge 8482
	if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
4104 Serge 8483
		with_fdi = false;
8484
 
6084 serge 8485
	mutex_lock(&dev_priv->sb_lock);
4104 Serge 8486
 
8487
	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8488
	tmp &= ~SBI_SSCCTL_DISABLE;
8489
	tmp |= SBI_SSCCTL_PATHALT;
8490
	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8491
 
8492
	udelay(24);
8493
 
8494
	if (with_spread) {
8495
		tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8496
		tmp &= ~SBI_SSCCTL_PATHALT;
8497
		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8498
 
8499
		if (with_fdi) {
8500
			lpt_reset_fdi_mphy(dev_priv);
8501
			lpt_program_fdi_mphy(dev_priv);
8502
		}
8503
	}
8504
 
6084 serge 8505
	reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
4104 Serge 8506
	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8507
	tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8508
	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8509
 
6084 serge 8510
	mutex_unlock(&dev_priv->sb_lock);
3243 Serge 8511
}
8512
 
4104 Serge 8513
/* Sequence to disable CLKOUT_DP */
8514
static void lpt_disable_clkout_dp(struct drm_device *dev)
8515
{
8516
	struct drm_i915_private *dev_priv = dev->dev_private;
8517
	uint32_t reg, tmp;
8518
 
6084 serge 8519
	mutex_lock(&dev_priv->sb_lock);
4104 Serge 8520
 
6084 serge 8521
	reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
4104 Serge 8522
	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8523
	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8524
	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8525
 
8526
	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8527
	if (!(tmp & SBI_SSCCTL_DISABLE)) {
8528
		if (!(tmp & SBI_SSCCTL_PATHALT)) {
8529
			tmp |= SBI_SSCCTL_PATHALT;
8530
			intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8531
			udelay(32);
8532
		}
8533
		tmp |= SBI_SSCCTL_DISABLE;
8534
		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8535
	}
8536
 
6084 serge 8537
	mutex_unlock(&dev_priv->sb_lock);
4104 Serge 8538
}
8539
 
8540
static void lpt_init_pch_refclk(struct drm_device *dev)
8541
{
8542
	struct intel_encoder *encoder;
8543
	bool has_vga = false;
8544
 
5354 serge 8545
	for_each_intel_encoder(dev, encoder) {
4104 Serge 8546
		switch (encoder->type) {
8547
		case INTEL_OUTPUT_ANALOG:
8548
			has_vga = true;
8549
			break;
5354 serge 8550
		default:
8551
			break;
4104 Serge 8552
		}
8553
	}
8554
 
8555
	if (has_vga)
8556
		lpt_enable_clkout_dp(dev, true, true);
8557
	else
8558
		lpt_disable_clkout_dp(dev);
8559
}
8560
 
3243 Serge 8561
/*
8562
 * Initialize reference clocks when the driver loads
8563
 */
8564
void intel_init_pch_refclk(struct drm_device *dev)
8565
{
8566
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8567
		ironlake_init_pch_refclk(dev);
8568
	else if (HAS_PCH_LPT(dev))
8569
		lpt_init_pch_refclk(dev);
8570
}
8571
 
6084 serge 8572
static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
2342 Serge 8573
{
6084 serge 8574
	struct drm_device *dev = crtc_state->base.crtc->dev;
2342 Serge 8575
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 8576
	struct drm_atomic_state *state = crtc_state->base.state;
8577
	struct drm_connector *connector;
8578
	struct drm_connector_state *connector_state;
2342 Serge 8579
	struct intel_encoder *encoder;
6084 serge 8580
	int num_connectors = 0, i;
2342 Serge 8581
	bool is_lvds = false;
8582
 
6084 serge 8583
	for_each_connector_in_state(state, connector, connector_state, i) {
8584
		if (connector_state->crtc != crtc_state->base.crtc)
5354 serge 8585
			continue;
8586
 
6084 serge 8587
		encoder = to_intel_encoder(connector_state->best_encoder);
8588
 
2342 Serge 8589
		switch (encoder->type) {
8590
		case INTEL_OUTPUT_LVDS:
8591
			is_lvds = true;
8592
			break;
5354 serge 8593
		default:
8594
			break;
2342 Serge 8595
		}
8596
		num_connectors++;
8597
	}
8598
 
8599
	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4560 Serge 8600
		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
4104 Serge 8601
			      dev_priv->vbt.lvds_ssc_freq);
4560 Serge 8602
		return dev_priv->vbt.lvds_ssc_freq;
2342 Serge 8603
	}
8604
 
8605
	return 120000;
8606
}
8607
 
4104 Serge 8608
static void ironlake_set_pipeconf(struct drm_crtc *crtc)
3031 serge 8609
{
8610
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8611
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8612
	int pipe = intel_crtc->pipe;
8613
	uint32_t val;
8614
 
4104 Serge 8615
	val = 0;
3031 serge 8616
 
6084 serge 8617
	switch (intel_crtc->config->pipe_bpp) {
3031 serge 8618
	case 18:
3480 Serge 8619
		val |= PIPECONF_6BPC;
3031 serge 8620
		break;
8621
	case 24:
3480 Serge 8622
		val |= PIPECONF_8BPC;
3031 serge 8623
		break;
8624
	case 30:
3480 Serge 8625
		val |= PIPECONF_10BPC;
3031 serge 8626
		break;
8627
	case 36:
3480 Serge 8628
		val |= PIPECONF_12BPC;
3031 serge 8629
		break;
8630
	default:
3243 Serge 8631
		/* Case prevented by intel_choose_pipe_bpp_dither. */
8632
		BUG();
3031 serge 8633
	}
8634
 
6084 serge 8635
	if (intel_crtc->config->dither)
3031 serge 8636
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8637
 
6084 serge 8638
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3031 serge 8639
		val |= PIPECONF_INTERLACED_ILK;
8640
	else
8641
		val |= PIPECONF_PROGRESSIVE;
8642
 
6084 serge 8643
	if (intel_crtc->config->limited_color_range)
3480 Serge 8644
		val |= PIPECONF_COLOR_RANGE_SELECT;
8645
 
3031 serge 8646
	I915_WRITE(PIPECONF(pipe), val);
8647
	POSTING_READ(PIPECONF(pipe));
8648
}
8649
 
3480 Serge 8650
/*
8651
 * Set up the pipe CSC unit.
8652
 *
8653
 * Currently only full range RGB to limited range RGB conversion
8654
 * is supported, but eventually this should handle various
8655
 * RGB<->YCbCr scenarios as well.
8656
 */
3746 Serge 8657
static void intel_set_pipe_csc(struct drm_crtc *crtc)
3480 Serge 8658
{
8659
	struct drm_device *dev = crtc->dev;
8660
	struct drm_i915_private *dev_priv = dev->dev_private;
8661
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8662
	int pipe = intel_crtc->pipe;
8663
	uint16_t coeff = 0x7800; /* 1.0 */
8664
 
8665
	/*
8666
	 * TODO: Check what kind of values actually come out of the pipe
8667
	 * with these coeff/postoff values and adjust to get the best
8668
	 * accuracy. Perhaps we even need to take the bpc value into
8669
	 * consideration.
8670
	 */
8671
 
6084 serge 8672
	if (intel_crtc->config->limited_color_range)
3480 Serge 8673
		coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8674
 
8675
	/*
8676
	 * GY/GU and RY/RU should be the other way around according
8677
	 * to BSpec, but reality doesn't agree. Just set them up in
8678
	 * a way that results in the correct picture.
8679
	 */
8680
	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8681
	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8682
 
8683
	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8684
	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8685
 
8686
	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8687
	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8688
 
8689
	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8690
	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8691
	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8692
 
8693
	if (INTEL_INFO(dev)->gen > 6) {
8694
		uint16_t postoff = 0;
8695
 
6084 serge 8696
		if (intel_crtc->config->limited_color_range)
4398 Serge 8697
			postoff = (16 * (1 << 12) / 255) & 0x1fff;
3480 Serge 8698
 
8699
		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8700
		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8701
		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8702
 
8703
		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8704
	} else {
8705
		uint32_t mode = CSC_MODE_YUV_TO_RGB;
8706
 
6084 serge 8707
		if (intel_crtc->config->limited_color_range)
3480 Serge 8708
			mode |= CSC_BLACK_SCREEN_OFFSET;
8709
 
8710
		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8711
	}
8712
}
8713
 
4104 Serge 8714
static void haswell_set_pipeconf(struct drm_crtc *crtc)
3243 Serge 8715
{
4560 Serge 8716
	struct drm_device *dev = crtc->dev;
8717
	struct drm_i915_private *dev_priv = dev->dev_private;
3243 Serge 8718
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4560 Serge 8719
	enum pipe pipe = intel_crtc->pipe;
6084 serge 8720
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243 Serge 8721
	uint32_t val;
8722
 
4104 Serge 8723
	val = 0;
3243 Serge 8724
 
6084 serge 8725
	if (IS_HASWELL(dev) && intel_crtc->config->dither)
3243 Serge 8726
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8727
 
6084 serge 8728
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3243 Serge 8729
		val |= PIPECONF_INTERLACED_ILK;
8730
	else
8731
		val |= PIPECONF_PROGRESSIVE;
8732
 
8733
	I915_WRITE(PIPECONF(cpu_transcoder), val);
8734
	POSTING_READ(PIPECONF(cpu_transcoder));
4104 Serge 8735
 
8736
	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8737
	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
4560 Serge 8738
 
5354 serge 8739
	if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
4560 Serge 8740
		val = 0;
8741
 
6084 serge 8742
		switch (intel_crtc->config->pipe_bpp) {
4560 Serge 8743
		case 18:
8744
			val |= PIPEMISC_DITHER_6_BPC;
8745
			break;
8746
		case 24:
8747
			val |= PIPEMISC_DITHER_8_BPC;
8748
			break;
8749
		case 30:
8750
			val |= PIPEMISC_DITHER_10_BPC;
8751
			break;
8752
		case 36:
8753
			val |= PIPEMISC_DITHER_12_BPC;
8754
			break;
8755
		default:
8756
			/* Case prevented by pipe_config_set_bpp. */
8757
			BUG();
8758
		}
8759
 
6084 serge 8760
		if (intel_crtc->config->dither)
4560 Serge 8761
			val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8762
 
8763
		I915_WRITE(PIPEMISC(pipe), val);
8764
	}
3243 Serge 8765
}
8766
 
3031 serge 8767
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6084 serge 8768
				    struct intel_crtc_state *crtc_state,
3031 serge 8769
				    intel_clock_t *clock,
8770
				    bool *has_reduced_clock,
8771
				    intel_clock_t *reduced_clock)
8772
{
8773
	struct drm_device *dev = crtc->dev;
8774
	struct drm_i915_private *dev_priv = dev->dev_private;
8775
	int refclk;
8776
	const intel_limit_t *limit;
6084 serge 8777
	bool ret;
3031 serge 8778
 
6084 serge 8779
	refclk = ironlake_get_refclk(crtc_state);
3031 serge 8780
 
8781
	/*
8782
	 * Returns a set of divisors for the desired target clock with the given
8783
	 * refclk, or FALSE.  The returned values represent the clock equation:
8784
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8785
	 */
6084 serge 8786
	limit = intel_limit(crtc_state, refclk);
8787
	ret = dev_priv->display.find_dpll(limit, crtc_state,
8788
					  crtc_state->port_clock,
4104 Serge 8789
					  refclk, NULL, clock);
3031 serge 8790
	if (!ret)
8791
		return false;
8792
 
8793
	return true;
8794
}
8795
 
3243 Serge 8796
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8797
{
8798
	/*
8799
	 * Account for spread spectrum to avoid
8800
	 * oversubscribing the link. Max center spread
8801
	 * is 2.5%; use 5% for safety's sake.
8802
	 */
8803
	u32 bps = target_clock * bpp * 21 / 20;
5060 serge 8804
	return DIV_ROUND_UP(bps, link_bw * 8);
3243 Serge 8805
}
8806
 
4104 Serge 8807
static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
2327 Serge 8808
{
4104 Serge 8809
	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
3746 Serge 8810
}
8811
 
3243 Serge 8812
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6084 serge 8813
				      struct intel_crtc_state *crtc_state,
4104 Serge 8814
				      u32 *fp,
3746 Serge 8815
				      intel_clock_t *reduced_clock, u32 *fp2)
3243 Serge 8816
{
8817
	struct drm_crtc *crtc = &intel_crtc->base;
8818
	struct drm_device *dev = crtc->dev;
8819
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 8820
	struct drm_atomic_state *state = crtc_state->base.state;
8821
	struct drm_connector *connector;
8822
	struct drm_connector_state *connector_state;
8823
	struct intel_encoder *encoder;
3243 Serge 8824
	uint32_t dpll;
6084 serge 8825
	int factor, num_connectors = 0, i;
4104 Serge 8826
	bool is_lvds = false, is_sdvo = false;
3243 Serge 8827
 
6084 serge 8828
	for_each_connector_in_state(state, connector, connector_state, i) {
8829
		if (connector_state->crtc != crtc_state->base.crtc)
5354 serge 8830
			continue;
8831
 
6084 serge 8832
		encoder = to_intel_encoder(connector_state->best_encoder);
8833
 
8834
		switch (encoder->type) {
3243 Serge 8835
		case INTEL_OUTPUT_LVDS:
8836
			is_lvds = true;
8837
			break;
8838
		case INTEL_OUTPUT_SDVO:
8839
		case INTEL_OUTPUT_HDMI:
8840
			is_sdvo = true;
8841
			break;
5354 serge 8842
		default:
8843
			break;
3243 Serge 8844
		}
8845
 
8846
		num_connectors++;
8847
	}
8848
 
6084 serge 8849
	/* Enable autotuning of the PLL clock (if permissible) */
8850
	factor = 21;
8851
	if (is_lvds) {
8852
		if ((intel_panel_use_ssc(dev_priv) &&
4560 Serge 8853
		     dev_priv->vbt.lvds_ssc_freq == 100000) ||
3746 Serge 8854
		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6084 serge 8855
			factor = 25;
8856
	} else if (crtc_state->sdvo_tv_clock)
8857
		factor = 20;
2327 Serge 8858
 
6084 serge 8859
	if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
3746 Serge 8860
		*fp |= FP_CB_TUNE;
2327 Serge 8861
 
3746 Serge 8862
	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8863
		*fp2 |= FP_CB_TUNE;
8864
 
6084 serge 8865
	dpll = 0;
2327 Serge 8866
 
6084 serge 8867
	if (is_lvds)
8868
		dpll |= DPLLB_MODE_LVDS;
8869
	else
8870
		dpll |= DPLLB_MODE_DAC_SERIAL;
4104 Serge 8871
 
6084 serge 8872
	dpll |= (crtc_state->pixel_multiplier - 1)
8873
		<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2327 Serge 8874
 
4104 Serge 8875
	if (is_sdvo)
8876
		dpll |= DPLL_SDVO_HIGH_SPEED;
6084 serge 8877
	if (crtc_state->has_dp_encoder)
4104 Serge 8878
		dpll |= DPLL_SDVO_HIGH_SPEED;
8879
 
6084 serge 8880
	/* compute bitmask from p1 value */
8881
	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8882
	/* also FPA1 */
8883
	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2327 Serge 8884
 
6084 serge 8885
	switch (crtc_state->dpll.p2) {
8886
	case 5:
8887
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8888
		break;
8889
	case 7:
8890
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8891
		break;
8892
	case 10:
8893
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8894
		break;
8895
	case 14:
8896
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8897
		break;
8898
	}
2327 Serge 8899
 
4104 Serge 8900
	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6084 serge 8901
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8902
	else
8903
		dpll |= PLL_REF_INPUT_DREFCLK;
2327 Serge 8904
 
4104 Serge 8905
	return dpll | DPLL_VCO_ENABLE;
3243 Serge 8906
}
8907
 
6084 serge 8908
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8909
				       struct intel_crtc_state *crtc_state)
3243 Serge 8910
{
5354 serge 8911
	struct drm_device *dev = crtc->base.dev;
3243 Serge 8912
	intel_clock_t clock, reduced_clock;
4104 Serge 8913
	u32 dpll = 0, fp = 0, fp2 = 0;
3243 Serge 8914
	bool ok, has_reduced_clock = false;
3746 Serge 8915
	bool is_lvds = false;
4104 Serge 8916
	struct intel_shared_dpll *pll;
3243 Serge 8917
 
6084 serge 8918
	memset(&crtc_state->dpll_hw_state, 0,
8919
	       sizeof(crtc_state->dpll_hw_state));
8920
 
5354 serge 8921
	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
3243 Serge 8922
 
8923
	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8924
	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8925
 
6084 serge 8926
	ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
3243 Serge 8927
				     &has_reduced_clock, &reduced_clock);
6084 serge 8928
	if (!ok && !crtc_state->clock_set) {
3243 Serge 8929
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
8930
		return -EINVAL;
8931
	}
3746 Serge 8932
	/* Compat-code for transition, will disappear. */
6084 serge 8933
	if (!crtc_state->clock_set) {
8934
		crtc_state->dpll.n = clock.n;
8935
		crtc_state->dpll.m1 = clock.m1;
8936
		crtc_state->dpll.m2 = clock.m2;
8937
		crtc_state->dpll.p1 = clock.p1;
8938
		crtc_state->dpll.p2 = clock.p2;
3746 Serge 8939
	}
3243 Serge 8940
 
4104 Serge 8941
	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6084 serge 8942
	if (crtc_state->has_pch_encoder) {
8943
		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8944
		if (has_reduced_clock)
4104 Serge 8945
			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
3243 Serge 8946
 
6084 serge 8947
		dpll = ironlake_compute_dpll(crtc, crtc_state,
4104 Serge 8948
					     &fp, &reduced_clock,
5060 serge 8949
					     has_reduced_clock ? &fp2 : NULL);
3243 Serge 8950
 
6084 serge 8951
		crtc_state->dpll_hw_state.dpll = dpll;
8952
		crtc_state->dpll_hw_state.fp0 = fp;
4104 Serge 8953
		if (has_reduced_clock)
6084 serge 8954
			crtc_state->dpll_hw_state.fp1 = fp2;
4104 Serge 8955
		else
6084 serge 8956
			crtc_state->dpll_hw_state.fp1 = fp;
2327 Serge 8957
 
6084 serge 8958
		pll = intel_get_shared_dpll(crtc, crtc_state);
3031 serge 8959
		if (pll == NULL) {
4104 Serge 8960
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5354 serge 8961
					 pipe_name(crtc->pipe));
2342 Serge 8962
			return -EINVAL;
6084 serge 8963
		}
5354 serge 8964
	}
2327 Serge 8965
 
6084 serge 8966
	if (is_lvds && has_reduced_clock)
5354 serge 8967
		crtc->lowfreq_avail = true;
4104 Serge 8968
	else
5354 serge 8969
		crtc->lowfreq_avail = false;
2327 Serge 8970
 
5060 serge 8971
	return 0;
4104 Serge 8972
}
3243 Serge 8973
 
4560 Serge 8974
static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8975
					 struct intel_link_m_n *m_n)
4104 Serge 8976
{
8977
	struct drm_device *dev = crtc->base.dev;
8978
	struct drm_i915_private *dev_priv = dev->dev_private;
4560 Serge 8979
	enum pipe pipe = crtc->pipe;
4104 Serge 8980
 
4560 Serge 8981
	m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8982
	m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8983
	m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8984
		& ~TU_SIZE_MASK;
8985
	m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8986
	m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8987
		    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8988
}
8989
 
8990
static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8991
					 enum transcoder transcoder,
5354 serge 8992
					 struct intel_link_m_n *m_n,
8993
					 struct intel_link_m_n *m2_n2)
4560 Serge 8994
{
8995
	struct drm_device *dev = crtc->base.dev;
8996
	struct drm_i915_private *dev_priv = dev->dev_private;
8997
	enum pipe pipe = crtc->pipe;
8998
 
8999
	if (INTEL_INFO(dev)->gen >= 5) {
9000
		m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9001
		m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9002
		m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6084 serge 9003
			& ~TU_SIZE_MASK;
4560 Serge 9004
		m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9005
		m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6084 serge 9006
			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5354 serge 9007
		/* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9008
		 * gen < 8) and if DRRS is supported (to make sure the
9009
		 * registers are not unnecessarily read).
9010
		 */
9011
		if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6084 serge 9012
			crtc->config->has_drrs) {
5354 serge 9013
			m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9014
			m2_n2->link_n =	I915_READ(PIPE_LINK_N2(transcoder));
9015
			m2_n2->gmch_m =	I915_READ(PIPE_DATA_M2(transcoder))
9016
					& ~TU_SIZE_MASK;
9017
			m2_n2->gmch_n =	I915_READ(PIPE_DATA_N2(transcoder));
9018
			m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9019
					& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9020
		}
4560 Serge 9021
	} else {
9022
		m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9023
		m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9024
		m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9025
			& ~TU_SIZE_MASK;
9026
		m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9027
		m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9028
			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9029
	}
3243 Serge 9030
}
9031
 
4560 Serge 9032
void intel_dp_get_m_n(struct intel_crtc *crtc,
6084 serge 9033
		      struct intel_crtc_state *pipe_config)
4560 Serge 9034
{
6084 serge 9035
	if (pipe_config->has_pch_encoder)
4560 Serge 9036
		intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9037
	else
9038
		intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5354 serge 9039
					     &pipe_config->dp_m_n,
9040
					     &pipe_config->dp_m2_n2);
4560 Serge 9041
}
9042
 
9043
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6084 serge 9044
					struct intel_crtc_state *pipe_config)
4560 Serge 9045
{
9046
	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5354 serge 9047
				     &pipe_config->fdi_m_n, NULL);
4560 Serge 9048
}
9049
 
5354 serge 9050
static void skylake_get_pfit_config(struct intel_crtc *crtc,
6084 serge 9051
				    struct intel_crtc_state *pipe_config)
5354 serge 9052
{
9053
	struct drm_device *dev = crtc->base.dev;
9054
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 9055
	struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9056
	uint32_t ps_ctrl = 0;
9057
	int id = -1;
9058
	int i;
5354 serge 9059
 
6084 serge 9060
	/* find scaler attached to this pipe */
9061
	for (i = 0; i < crtc->num_scalers; i++) {
9062
		ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9063
		if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9064
			id = i;
9065
			pipe_config->pch_pfit.enabled = true;
9066
			pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9067
			pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9068
			break;
9069
		}
9070
	}
5354 serge 9071
 
6084 serge 9072
	scaler_state->scaler_id = id;
9073
	if (id >= 0) {
9074
		scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9075
	} else {
9076
		scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
5354 serge 9077
	}
9078
}
9079
 
6084 serge 9080
static void
9081
skylake_get_initial_plane_config(struct intel_crtc *crtc,
9082
				 struct intel_initial_plane_config *plane_config)
9083
{
9084
	struct drm_device *dev = crtc->base.dev;
9085
	struct drm_i915_private *dev_priv = dev->dev_private;
9086
	u32 val, base, offset, stride_mult, tiling;
9087
	int pipe = crtc->pipe;
9088
	int fourcc, pixel_format;
9089
	unsigned int aligned_height;
9090
	struct drm_framebuffer *fb;
9091
	struct intel_framebuffer *intel_fb;
9092
 
9093
	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9094
	if (!intel_fb) {
9095
		DRM_DEBUG_KMS("failed to alloc fb\n");
9096
		return;
9097
	}
9098
 
9099
	fb = &intel_fb->base;
9100
 
9101
	val = I915_READ(PLANE_CTL(pipe, 0));
9102
	if (!(val & PLANE_CTL_ENABLE))
9103
		goto error;
9104
 
9105
	pixel_format = val & PLANE_CTL_FORMAT_MASK;
9106
	fourcc = skl_format_to_fourcc(pixel_format,
9107
				      val & PLANE_CTL_ORDER_RGBX,
9108
				      val & PLANE_CTL_ALPHA_MASK);
9109
	fb->pixel_format = fourcc;
9110
	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9111
 
9112
	tiling = val & PLANE_CTL_TILED_MASK;
9113
	switch (tiling) {
9114
	case PLANE_CTL_TILED_LINEAR:
9115
		fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9116
		break;
9117
	case PLANE_CTL_TILED_X:
9118
		plane_config->tiling = I915_TILING_X;
9119
		fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9120
		break;
9121
	case PLANE_CTL_TILED_Y:
9122
		fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9123
		break;
9124
	case PLANE_CTL_TILED_YF:
9125
		fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9126
		break;
9127
	default:
9128
		MISSING_CASE(tiling);
9129
		goto error;
9130
	}
9131
 
9132
	base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9133
	plane_config->base = base;
9134
 
9135
	offset = I915_READ(PLANE_OFFSET(pipe, 0));
9136
 
9137
	val = I915_READ(PLANE_SIZE(pipe, 0));
9138
	fb->height = ((val >> 16) & 0xfff) + 1;
9139
	fb->width = ((val >> 0) & 0x1fff) + 1;
9140
 
9141
	val = I915_READ(PLANE_STRIDE(pipe, 0));
9142
	stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9143
						fb->pixel_format);
6283 serge 9144
	fb->pitches[0] = (val & 0x3ff) * stride_mult;
6084 serge 9145
 
9146
	aligned_height = intel_fb_align_height(dev, fb->height,
9147
					       fb->pixel_format,
9148
					       fb->modifier[0]);
9149
 
6283 serge 9150
	plane_config->size = fb->pitches[0] * aligned_height;
6084 serge 9151
 
9152
	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9153
		      pipe_name(pipe), fb->width, fb->height,
9154
		      fb->bits_per_pixel, base, fb->pitches[0],
9155
		      plane_config->size);
9156
 
9157
	plane_config->fb = intel_fb;
9158
	return;
9159
 
9160
error:
9161
	kfree(fb);
9162
}
9163
 
4104 Serge 9164
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6084 serge 9165
				     struct intel_crtc_state *pipe_config)
4104 Serge 9166
{
9167
	struct drm_device *dev = crtc->base.dev;
9168
	struct drm_i915_private *dev_priv = dev->dev_private;
9169
	uint32_t tmp;
9170
 
9171
	tmp = I915_READ(PF_CTL(crtc->pipe));
9172
 
9173
	if (tmp & PF_ENABLE) {
9174
		pipe_config->pch_pfit.enabled = true;
9175
		pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9176
		pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9177
 
9178
		/* We currently do not free assignements of panel fitters on
9179
		 * ivb/hsw (since we don't use the higher upscaling modes which
9180
		 * differentiates them) so just WARN about this case for now. */
9181
		if (IS_GEN7(dev)) {
9182
			WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9183
				PF_PIPE_SEL_IVB(crtc->pipe));
9184
		}
9185
	}
9186
}
9187
 
6084 serge 9188
static void
9189
ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9190
				  struct intel_initial_plane_config *plane_config)
5060 serge 9191
{
9192
	struct drm_device *dev = crtc->base.dev;
9193
	struct drm_i915_private *dev_priv = dev->dev_private;
9194
	u32 val, base, offset;
6084 serge 9195
	int pipe = crtc->pipe;
5060 serge 9196
	int fourcc, pixel_format;
6084 serge 9197
	unsigned int aligned_height;
9198
	struct drm_framebuffer *fb;
9199
	struct intel_framebuffer *intel_fb;
5060 serge 9200
 
6084 serge 9201
	val = I915_READ(DSPCNTR(pipe));
9202
	if (!(val & DISPLAY_PLANE_ENABLE))
9203
		return;
9204
 
9205
	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9206
	if (!intel_fb) {
5060 serge 9207
		DRM_DEBUG_KMS("failed to alloc fb\n");
9208
		return;
9209
	}
9210
 
6084 serge 9211
	fb = &intel_fb->base;
5060 serge 9212
 
6084 serge 9213
	if (INTEL_INFO(dev)->gen >= 4) {
9214
		if (val & DISPPLANE_TILED) {
9215
			plane_config->tiling = I915_TILING_X;
9216
			fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9217
		}
9218
	}
5060 serge 9219
 
9220
	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6084 serge 9221
	fourcc = i9xx_format_to_fourcc(pixel_format);
9222
	fb->pixel_format = fourcc;
9223
	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
5060 serge 9224
 
6084 serge 9225
	base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
5060 serge 9226
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6084 serge 9227
		offset = I915_READ(DSPOFFSET(pipe));
5060 serge 9228
	} else {
6084 serge 9229
		if (plane_config->tiling)
9230
			offset = I915_READ(DSPTILEOFF(pipe));
5060 serge 9231
		else
6084 serge 9232
			offset = I915_READ(DSPLINOFF(pipe));
5060 serge 9233
	}
9234
	plane_config->base = base;
9235
 
9236
	val = I915_READ(PIPESRC(pipe));
6084 serge 9237
	fb->width = ((val >> 16) & 0xfff) + 1;
9238
	fb->height = ((val >> 0) & 0xfff) + 1;
5060 serge 9239
 
9240
	val = I915_READ(DSPSTRIDE(pipe));
6283 serge 9241
	fb->pitches[0] = val & 0xffffffc0;
5060 serge 9242
 
6084 serge 9243
	aligned_height = intel_fb_align_height(dev, fb->height,
9244
					       fb->pixel_format,
9245
					       fb->modifier[0]);
5060 serge 9246
 
6283 serge 9247
	plane_config->size = fb->pitches[0] * aligned_height;
5060 serge 9248
 
6084 serge 9249
	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9250
		      pipe_name(pipe), fb->width, fb->height,
9251
		      fb->bits_per_pixel, base, fb->pitches[0],
5060 serge 9252
		      plane_config->size);
6084 serge 9253
 
9254
	plane_config->fb = intel_fb;
5060 serge 9255
}
9256
 
3746 Serge 9257
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6084 serge 9258
				     struct intel_crtc_state *pipe_config)
3746 Serge 9259
{
9260
	struct drm_device *dev = crtc->base.dev;
9261
	struct drm_i915_private *dev_priv = dev->dev_private;
9262
	uint32_t tmp;
9263
 
5354 serge 9264
	if (!intel_display_power_is_enabled(dev_priv,
6084 serge 9265
					    POWER_DOMAIN_PIPE(crtc->pipe)))
5060 serge 9266
		return false;
9267
 
4104 Serge 9268
	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9269
	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9270
 
3746 Serge 9271
	tmp = I915_READ(PIPECONF(crtc->pipe));
9272
	if (!(tmp & PIPECONF_ENABLE))
9273
		return false;
9274
 
4280 Serge 9275
	switch (tmp & PIPECONF_BPC_MASK) {
9276
	case PIPECONF_6BPC:
9277
		pipe_config->pipe_bpp = 18;
9278
		break;
9279
	case PIPECONF_8BPC:
9280
		pipe_config->pipe_bpp = 24;
9281
		break;
9282
	case PIPECONF_10BPC:
9283
		pipe_config->pipe_bpp = 30;
9284
		break;
9285
	case PIPECONF_12BPC:
9286
		pipe_config->pipe_bpp = 36;
9287
		break;
9288
	default:
9289
		break;
9290
	}
9291
 
5060 serge 9292
	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9293
		pipe_config->limited_color_range = true;
9294
 
4104 Serge 9295
	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9296
		struct intel_shared_dpll *pll;
9297
 
3746 Serge 9298
		pipe_config->has_pch_encoder = true;
9299
 
4104 Serge 9300
		tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9301
		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9302
					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
9303
 
9304
		ironlake_get_fdi_m_n_config(crtc, pipe_config);
9305
 
9306
		if (HAS_PCH_IBX(dev_priv->dev)) {
9307
			pipe_config->shared_dpll =
9308
				(enum intel_dpll_id) crtc->pipe;
9309
		} else {
9310
			tmp = I915_READ(PCH_DPLL_SEL);
9311
			if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9312
				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9313
			else
9314
				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9315
		}
9316
 
9317
		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9318
 
9319
		WARN_ON(!pll->get_hw_state(dev_priv, pll,
9320
					   &pipe_config->dpll_hw_state));
9321
 
9322
		tmp = pipe_config->dpll_hw_state.dpll;
9323
		pipe_config->pixel_multiplier =
9324
			((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9325
			 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
4560 Serge 9326
 
9327
		ironlake_pch_clock_get(crtc, pipe_config);
4104 Serge 9328
	} else {
9329
		pipe_config->pixel_multiplier = 1;
9330
	}
9331
 
9332
	intel_get_pipe_timings(crtc, pipe_config);
9333
 
9334
	ironlake_get_pfit_config(crtc, pipe_config);
9335
 
3746 Serge 9336
	return true;
9337
}
9338
 
4104 Serge 9339
static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9340
{
9341
	struct drm_device *dev = dev_priv->dev;
9342
	struct intel_crtc *crtc;
9343
 
5060 serge 9344
	for_each_intel_crtc(dev, crtc)
6084 serge 9345
		I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
4104 Serge 9346
		     pipe_name(crtc->pipe));
9347
 
6084 serge 9348
	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9349
	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9350
	I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9351
	I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9352
	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9353
	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
4104 Serge 9354
	     "CPU PWM1 enabled\n");
5060 serge 9355
	if (IS_HASWELL(dev))
6084 serge 9356
		I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9357
		     "CPU PWM2 enabled\n");
9358
	I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
4104 Serge 9359
	     "PCH PWM1 enabled\n");
6084 serge 9360
	I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
4104 Serge 9361
	     "Utility pin enabled\n");
6084 serge 9362
	I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
4104 Serge 9363
 
5060 serge 9364
	/*
9365
	 * In theory we can still leave IRQs enabled, as long as only the HPD
9366
	 * interrupts remain enabled. We used to check for that, but since it's
9367
	 * gen-specific and since we only disable LCPLL after we fully disable
9368
	 * the interrupts, the check below should be enough.
9369
	 */
6084 serge 9370
	I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
4104 Serge 9371
}
9372
 
5060 serge 9373
static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9374
{
9375
	struct drm_device *dev = dev_priv->dev;
9376
 
9377
	if (IS_HASWELL(dev))
9378
		return I915_READ(D_COMP_HSW);
9379
	else
9380
		return I915_READ(D_COMP_BDW);
9381
}
9382
 
9383
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9384
{
9385
	struct drm_device *dev = dev_priv->dev;
9386
 
9387
	if (IS_HASWELL(dev)) {
9388
		mutex_lock(&dev_priv->rps.hw_lock);
9389
		if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9390
					    val))
9391
			DRM_ERROR("Failed to write to D_COMP\n");
9392
		mutex_unlock(&dev_priv->rps.hw_lock);
9393
	} else {
9394
		I915_WRITE(D_COMP_BDW, val);
9395
		POSTING_READ(D_COMP_BDW);
9396
	}
9397
}
9398
 
4104 Serge 9399
/*
9400
 * This function implements pieces of two sequences from BSpec:
9401
 * - Sequence for display software to disable LCPLL
9402
 * - Sequence for display software to allow package C8+
9403
 * The steps implemented here are just the steps that actually touch the LCPLL
9404
 * register. Callers should take care of disabling all the display engine
9405
 * functions, doing the mode unset, fixing interrupts, etc.
9406
 */
4560 Serge 9407
static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6084 serge 9408
			      bool switch_to_fclk, bool allow_power_down)
4104 Serge 9409
{
9410
	uint32_t val;
9411
 
9412
	assert_can_disable_lcpll(dev_priv);
9413
 
9414
	val = I915_READ(LCPLL_CTL);
9415
 
9416
	if (switch_to_fclk) {
9417
		val |= LCPLL_CD_SOURCE_FCLK;
9418
		I915_WRITE(LCPLL_CTL, val);
9419
 
9420
		if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9421
				       LCPLL_CD_SOURCE_FCLK_DONE, 1))
9422
			DRM_ERROR("Switching to FCLK failed\n");
9423
 
9424
		val = I915_READ(LCPLL_CTL);
9425
	}
9426
 
9427
	val |= LCPLL_PLL_DISABLE;
9428
	I915_WRITE(LCPLL_CTL, val);
9429
	POSTING_READ(LCPLL_CTL);
9430
 
9431
	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9432
		DRM_ERROR("LCPLL still locked\n");
9433
 
5060 serge 9434
	val = hsw_read_dcomp(dev_priv);
4104 Serge 9435
	val |= D_COMP_COMP_DISABLE;
5060 serge 9436
	hsw_write_dcomp(dev_priv, val);
9437
	ndelay(100);
4104 Serge 9438
 
5060 serge 9439
	if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9440
		     1))
4104 Serge 9441
		DRM_ERROR("D_COMP RCOMP still in progress\n");
9442
 
9443
	if (allow_power_down) {
9444
		val = I915_READ(LCPLL_CTL);
9445
		val |= LCPLL_POWER_DOWN_ALLOW;
9446
		I915_WRITE(LCPLL_CTL, val);
9447
		POSTING_READ(LCPLL_CTL);
9448
	}
9449
}
9450
 
9451
/*
9452
 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9453
 * source.
9454
 */
4560 Serge 9455
static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
4104 Serge 9456
{
9457
	uint32_t val;
9458
 
9459
	val = I915_READ(LCPLL_CTL);
9460
 
9461
	if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9462
		    LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9463
		return;
9464
 
5060 serge 9465
	/*
9466
	 * Make sure we're not on PC8 state before disabling PC8, otherwise
9467
	 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9468
	 */
6084 serge 9469
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4104 Serge 9470
 
9471
	if (val & LCPLL_POWER_DOWN_ALLOW) {
9472
		val &= ~LCPLL_POWER_DOWN_ALLOW;
9473
		I915_WRITE(LCPLL_CTL, val);
9474
		POSTING_READ(LCPLL_CTL);
9475
	}
9476
 
5060 serge 9477
	val = hsw_read_dcomp(dev_priv);
4104 Serge 9478
	val |= D_COMP_COMP_FORCE;
9479
	val &= ~D_COMP_COMP_DISABLE;
5060 serge 9480
	hsw_write_dcomp(dev_priv, val);
4104 Serge 9481
 
9482
	val = I915_READ(LCPLL_CTL);
9483
	val &= ~LCPLL_PLL_DISABLE;
9484
	I915_WRITE(LCPLL_CTL, val);
9485
 
9486
	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9487
		DRM_ERROR("LCPLL not locked yet\n");
9488
 
9489
	if (val & LCPLL_CD_SOURCE_FCLK) {
9490
		val = I915_READ(LCPLL_CTL);
9491
		val &= ~LCPLL_CD_SOURCE_FCLK;
9492
		I915_WRITE(LCPLL_CTL, val);
9493
 
9494
		if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9495
					LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9496
			DRM_ERROR("Switching back to LCPLL failed\n");
9497
	}
9498
 
6084 serge 9499
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9500
	intel_update_cdclk(dev_priv->dev);
4104 Serge 9501
}
9502
 
5060 serge 9503
/*
9504
 * Package states C8 and deeper are really deep PC states that can only be
9505
 * reached when all the devices on the system allow it, so even if the graphics
9506
 * device allows PC8+, it doesn't mean the system will actually get to these
9507
 * states. Our driver only allows PC8+ when going into runtime PM.
9508
 *
9509
 * The requirements for PC8+ are that all the outputs are disabled, the power
9510
 * well is disabled and most interrupts are disabled, and these are also
9511
 * requirements for runtime PM. When these conditions are met, we manually do
9512
 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9513
 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9514
 * hang the machine.
9515
 *
9516
 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9517
 * the state of some registers, so when we come back from PC8+ we need to
9518
 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9519
 * need to take care of the registers kept by RC6. Notice that this happens even
9520
 * if we don't put the device in PCI D3 state (which is what currently happens
9521
 * because of the runtime PM support).
9522
 *
9523
 * For more, read "Display Sequences for Package C8" on the hardware
9524
 * documentation.
9525
 */
9526
void hsw_enable_pc8(struct drm_i915_private *dev_priv)
4104 Serge 9527
{
9528
	struct drm_device *dev = dev_priv->dev;
9529
	uint32_t val;
9530
 
9531
	DRM_DEBUG_KMS("Enabling package C8+\n");
9532
 
6084 serge 9533
	if (HAS_PCH_LPT_LP(dev)) {
4104 Serge 9534
		val = I915_READ(SOUTH_DSPCLK_GATE_D);
9535
		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9536
		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9537
	}
9538
 
9539
	lpt_disable_clkout_dp(dev);
9540
	hsw_disable_lcpll(dev_priv, true, true);
9541
}
9542
 
5060 serge 9543
void hsw_disable_pc8(struct drm_i915_private *dev_priv)
4104 Serge 9544
{
9545
	struct drm_device *dev = dev_priv->dev;
9546
	uint32_t val;
9547
 
9548
	DRM_DEBUG_KMS("Disabling package C8+\n");
9549
 
9550
	hsw_restore_lcpll(dev_priv);
9551
	lpt_init_pch_refclk(dev);
9552
 
6084 serge 9553
	if (HAS_PCH_LPT_LP(dev)) {
4104 Serge 9554
		val = I915_READ(SOUTH_DSPCLK_GATE_D);
9555
		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9556
		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9557
	}
9558
 
9559
	intel_prepare_ddi(dev);
9560
}
9561
 
6084 serge 9562
static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
4104 Serge 9563
{
6084 serge 9564
	struct drm_device *dev = old_state->dev;
9565
	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9566
 
9567
	broxton_set_cdclk(dev, req_cdclk);
9568
}
9569
 
9570
/* compute the max rate for new configuration */
9571
static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9572
{
9573
	struct intel_crtc *intel_crtc;
9574
	struct intel_crtc_state *crtc_state;
9575
	int max_pixel_rate = 0;
9576
 
9577
	for_each_intel_crtc(state->dev, intel_crtc) {
9578
		int pixel_rate;
9579
 
9580
		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9581
		if (IS_ERR(crtc_state))
9582
			return PTR_ERR(crtc_state);
9583
 
9584
		if (!crtc_state->base.enable)
9585
			continue;
9586
 
9587
		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9588
 
9589
		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9590
		if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9591
			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9592
 
9593
		max_pixel_rate = max(max_pixel_rate, pixel_rate);
9594
	}
9595
 
9596
	return max_pixel_rate;
9597
}
9598
 
9599
static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9600
{
9601
	struct drm_i915_private *dev_priv = dev->dev_private;
9602
	uint32_t val, data;
9603
	int ret;
9604
 
9605
	if (WARN((I915_READ(LCPLL_CTL) &
9606
		  (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9607
		   LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9608
		   LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9609
		   LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9610
		 "trying to change cdclk frequency with cdclk not enabled\n"))
9611
		return;
9612
 
9613
	mutex_lock(&dev_priv->rps.hw_lock);
9614
	ret = sandybridge_pcode_write(dev_priv,
9615
				      BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9616
	mutex_unlock(&dev_priv->rps.hw_lock);
9617
	if (ret) {
9618
		DRM_ERROR("failed to inform pcode about cdclk change\n");
9619
		return;
9620
	}
9621
 
9622
	val = I915_READ(LCPLL_CTL);
9623
	val |= LCPLL_CD_SOURCE_FCLK;
9624
	I915_WRITE(LCPLL_CTL, val);
9625
 
9626
	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9627
			       LCPLL_CD_SOURCE_FCLK_DONE, 1))
9628
		DRM_ERROR("Switching to FCLK failed\n");
9629
 
9630
	val = I915_READ(LCPLL_CTL);
9631
	val &= ~LCPLL_CLK_FREQ_MASK;
9632
 
9633
	switch (cdclk) {
9634
	case 450000:
9635
		val |= LCPLL_CLK_FREQ_450;
9636
		data = 0;
9637
		break;
9638
	case 540000:
9639
		val |= LCPLL_CLK_FREQ_54O_BDW;
9640
		data = 1;
9641
		break;
9642
	case 337500:
9643
		val |= LCPLL_CLK_FREQ_337_5_BDW;
9644
		data = 2;
9645
		break;
9646
	case 675000:
9647
		val |= LCPLL_CLK_FREQ_675_BDW;
9648
		data = 3;
9649
		break;
9650
	default:
9651
		WARN(1, "invalid cdclk frequency\n");
9652
		return;
9653
	}
9654
 
9655
	I915_WRITE(LCPLL_CTL, val);
9656
 
9657
	val = I915_READ(LCPLL_CTL);
9658
	val &= ~LCPLL_CD_SOURCE_FCLK;
9659
	I915_WRITE(LCPLL_CTL, val);
9660
 
9661
	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9662
				LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9663
		DRM_ERROR("Switching back to LCPLL failed\n");
9664
 
9665
	mutex_lock(&dev_priv->rps.hw_lock);
9666
	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9667
	mutex_unlock(&dev_priv->rps.hw_lock);
9668
 
9669
	intel_update_cdclk(dev);
9670
 
9671
	WARN(cdclk != dev_priv->cdclk_freq,
9672
	     "cdclk requested %d kHz but got %d kHz\n",
9673
	     cdclk, dev_priv->cdclk_freq);
9674
}
9675
 
9676
static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9677
{
9678
	struct drm_i915_private *dev_priv = to_i915(state->dev);
9679
	int max_pixclk = ilk_max_pixel_rate(state);
9680
	int cdclk;
9681
 
9682
	/*
9683
	 * FIXME should also account for plane ratio
9684
	 * once 64bpp pixel formats are supported.
9685
	 */
9686
	if (max_pixclk > 540000)
9687
		cdclk = 675000;
9688
	else if (max_pixclk > 450000)
9689
		cdclk = 540000;
9690
	else if (max_pixclk > 337500)
9691
		cdclk = 450000;
9692
	else
9693
		cdclk = 337500;
9694
 
9695
	/*
9696
	 * FIXME move the cdclk caclulation to
9697
	 * compute_config() so we can fail gracegully.
9698
	 */
9699
	if (cdclk > dev_priv->max_cdclk_freq) {
9700
		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9701
			  cdclk, dev_priv->max_cdclk_freq);
9702
		cdclk = dev_priv->max_cdclk_freq;
9703
	}
9704
 
9705
	to_intel_atomic_state(state)->cdclk = cdclk;
9706
 
9707
	return 0;
9708
}
9709
 
9710
static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9711
{
9712
	struct drm_device *dev = old_state->dev;
9713
	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9714
 
9715
	broadwell_set_cdclk(dev, req_cdclk);
9716
}
9717
 
9718
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9719
				      struct intel_crtc_state *crtc_state)
9720
{
9721
	if (!intel_ddi_pll_select(crtc, crtc_state))
5354 serge 9722
		return -EINVAL;
9723
 
9724
	crtc->lowfreq_avail = false;
9725
 
9726
	return 0;
4104 Serge 9727
}
9728
 
6084 serge 9729
static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9730
				enum port port,
9731
				struct intel_crtc_state *pipe_config)
9732
{
9733
	switch (port) {
9734
	case PORT_A:
9735
		pipe_config->ddi_pll_sel = SKL_DPLL0;
9736
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9737
		break;
9738
	case PORT_B:
9739
		pipe_config->ddi_pll_sel = SKL_DPLL1;
9740
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9741
		break;
9742
	case PORT_C:
9743
		pipe_config->ddi_pll_sel = SKL_DPLL2;
9744
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9745
		break;
9746
	default:
9747
		DRM_ERROR("Incorrect port type\n");
9748
	}
9749
}
9750
 
5354 serge 9751
static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9752
				enum port port,
6084 serge 9753
				struct intel_crtc_state *pipe_config)
4104 Serge 9754
{
6084 serge 9755
	u32 temp, dpll_ctl1;
5354 serge 9756
 
9757
	temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9758
	pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9759
 
9760
	switch (pipe_config->ddi_pll_sel) {
6084 serge 9761
	case SKL_DPLL0:
9762
		/*
9763
		 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9764
		 * of the shared DPLL framework and thus needs to be read out
9765
		 * separately
9766
		 */
9767
		dpll_ctl1 = I915_READ(DPLL_CTRL1);
9768
		pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9769
		break;
5354 serge 9770
	case SKL_DPLL1:
9771
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9772
		break;
9773
	case SKL_DPLL2:
9774
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9775
		break;
9776
	case SKL_DPLL3:
9777
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9778
		break;
9779
	}
4104 Serge 9780
}
9781
 
5354 serge 9782
static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9783
				enum port port,
6084 serge 9784
				struct intel_crtc_state *pipe_config)
4104 Serge 9785
{
5354 serge 9786
	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
4104 Serge 9787
 
5354 serge 9788
	switch (pipe_config->ddi_pll_sel) {
9789
	case PORT_CLK_SEL_WRPLL1:
9790
		pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9791
		break;
9792
	case PORT_CLK_SEL_WRPLL2:
9793
		pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9794
		break;
6084 serge 9795
	case PORT_CLK_SEL_SPLL:
9796
		pipe_config->shared_dpll = DPLL_ID_SPLL;
5354 serge 9797
	}
4104 Serge 9798
}
9799
 
5060 serge 9800
static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
6084 serge 9801
				       struct intel_crtc_state *pipe_config)
4104 Serge 9802
{
5060 serge 9803
	struct drm_device *dev = crtc->base.dev;
4104 Serge 9804
	struct drm_i915_private *dev_priv = dev->dev_private;
5060 serge 9805
	struct intel_shared_dpll *pll;
9806
	enum port port;
9807
	uint32_t tmp;
4104 Serge 9808
 
5060 serge 9809
	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
4560 Serge 9810
 
5060 serge 9811
	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
4104 Serge 9812
 
5354 serge 9813
	if (IS_SKYLAKE(dev))
9814
		skylake_get_ddi_pll(dev_priv, port, pipe_config);
6084 serge 9815
	else if (IS_BROXTON(dev))
9816
		bxt_get_ddi_pll(dev_priv, port, pipe_config);
5354 serge 9817
	else
9818
		haswell_get_ddi_pll(dev_priv, port, pipe_config);
4104 Serge 9819
 
5060 serge 9820
	if (pipe_config->shared_dpll >= 0) {
9821
		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
4560 Serge 9822
 
5060 serge 9823
		WARN_ON(!pll->get_hw_state(dev_priv, pll,
9824
					   &pipe_config->dpll_hw_state));
4104 Serge 9825
	}
9826
 
4560 Serge 9827
	/*
5060 serge 9828
	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9829
	 * DDI E. So just check whether this pipe is wired to DDI E and whether
9830
	 * the PCH transcoder is on.
4560 Serge 9831
	 */
5354 serge 9832
	if (INTEL_INFO(dev)->gen < 9 &&
9833
	    (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5060 serge 9834
		pipe_config->has_pch_encoder = true;
4560 Serge 9835
 
5060 serge 9836
		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9837
		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9838
					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
3480 Serge 9839
 
5060 serge 9840
		ironlake_get_fdi_m_n_config(crtc, pipe_config);
3480 Serge 9841
	}
4560 Serge 9842
}
9843
 
3746 Serge 9844
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6084 serge 9845
				    struct intel_crtc_state *pipe_config)
3746 Serge 9846
{
9847
	struct drm_device *dev = crtc->base.dev;
9848
	struct drm_i915_private *dev_priv = dev->dev_private;
4104 Serge 9849
	enum intel_display_power_domain pfit_domain;
3746 Serge 9850
	uint32_t tmp;
9851
 
5354 serge 9852
	if (!intel_display_power_is_enabled(dev_priv,
5060 serge 9853
					 POWER_DOMAIN_PIPE(crtc->pipe)))
9854
		return false;
9855
 
4104 Serge 9856
	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9857
	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9858
 
9859
	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9860
	if (tmp & TRANS_DDI_FUNC_ENABLE) {
9861
		enum pipe trans_edp_pipe;
9862
		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9863
		default:
9864
			WARN(1, "unknown pipe linked to edp transcoder\n");
9865
		case TRANS_DDI_EDP_INPUT_A_ONOFF:
9866
		case TRANS_DDI_EDP_INPUT_A_ON:
9867
			trans_edp_pipe = PIPE_A;
9868
			break;
9869
		case TRANS_DDI_EDP_INPUT_B_ONOFF:
9870
			trans_edp_pipe = PIPE_B;
9871
			break;
9872
		case TRANS_DDI_EDP_INPUT_C_ONOFF:
9873
			trans_edp_pipe = PIPE_C;
9874
			break;
9875
		}
9876
 
9877
		if (trans_edp_pipe == crtc->pipe)
9878
			pipe_config->cpu_transcoder = TRANSCODER_EDP;
9879
	}
9880
 
5354 serge 9881
	if (!intel_display_power_is_enabled(dev_priv,
4104 Serge 9882
			POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9883
		return false;
9884
 
9885
	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
3746 Serge 9886
	if (!(tmp & PIPECONF_ENABLE))
9887
		return false;
9888
 
5060 serge 9889
	haswell_get_ddi_port_state(crtc, pipe_config);
3746 Serge 9890
 
4104 Serge 9891
	intel_get_pipe_timings(crtc, pipe_config);
9892
 
6084 serge 9893
	if (INTEL_INFO(dev)->gen >= 9) {
9894
		skl_init_scalers(dev, crtc, pipe_config);
9895
	}
9896
 
4104 Serge 9897
	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6084 serge 9898
 
9899
	if (INTEL_INFO(dev)->gen >= 9) {
9900
		pipe_config->scaler_state.scaler_id = -1;
9901
		pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9902
	}
9903
 
5354 serge 9904
	if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
6084 serge 9905
		if (INTEL_INFO(dev)->gen >= 9)
5354 serge 9906
			skylake_get_pfit_config(crtc, pipe_config);
9907
		else
6084 serge 9908
			ironlake_get_pfit_config(crtc, pipe_config);
5354 serge 9909
	}
4104 Serge 9910
 
4560 Serge 9911
	if (IS_HASWELL(dev))
6084 serge 9912
		pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9913
			(I915_READ(IPS_CTL) & IPS_ENABLE);
4104 Serge 9914
 
5354 serge 9915
	if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9916
		pipe_config->pixel_multiplier =
9917
			I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9918
	} else {
6084 serge 9919
		pipe_config->pixel_multiplier = 1;
4560 Serge 9920
	}
9921
 
2342 Serge 9922
	return true;
9923
}
9924
 
6084 serge 9925
static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
2342 Serge 9926
{
5354 serge 9927
	struct drm_device *dev = crtc->dev;
9928
	struct drm_i915_private *dev_priv = dev->dev_private;
9929
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9930
	uint32_t cntl = 0, size = 0;
2342 Serge 9931
 
6084 serge 9932
	if (on) {
9933
		unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9934
		unsigned int height = intel_crtc->base.cursor->state->crtc_h;
5354 serge 9935
		unsigned int stride = roundup_pow_of_two(width) * 4;
2342 Serge 9936
 
5354 serge 9937
		switch (stride) {
9938
		default:
9939
			WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9940
				  width, stride);
9941
			stride = 256;
9942
			/* fallthrough */
9943
		case 256:
9944
		case 512:
9945
		case 1024:
9946
		case 2048:
9947
			break;
6084 serge 9948
		}
3031 serge 9949
 
5354 serge 9950
		cntl |= CURSOR_ENABLE |
9951
			CURSOR_GAMMA_ENABLE |
9952
			CURSOR_FORMAT_ARGB |
9953
			CURSOR_STRIDE(stride);
3031 serge 9954
 
5354 serge 9955
		size = (height << 12) | width;
2342 Serge 9956
	}
9957
 
5354 serge 9958
	if (intel_crtc->cursor_cntl != 0 &&
9959
	    (intel_crtc->cursor_base != base ||
9960
	     intel_crtc->cursor_size != size ||
9961
	     intel_crtc->cursor_cntl != cntl)) {
9962
		/* On these chipsets we can only modify the base/size/stride
9963
		 * whilst the cursor is disabled.
3031 serge 9964
		 */
6084 serge 9965
		I915_WRITE(CURCNTR(PIPE_A), 0);
9966
		POSTING_READ(CURCNTR(PIPE_A));
9967
		intel_crtc->cursor_cntl = 0;
9968
	}
5060 serge 9969
 
5354 serge 9970
	if (intel_crtc->cursor_base != base) {
6084 serge 9971
		I915_WRITE(CURBASE(PIPE_A), base);
5354 serge 9972
		intel_crtc->cursor_base = base;
5060 serge 9973
	}
2327 Serge 9974
 
5354 serge 9975
	if (intel_crtc->cursor_size != size) {
9976
		I915_WRITE(CURSIZE, size);
9977
		intel_crtc->cursor_size = size;
9978
	}
9979
 
5060 serge 9980
	if (intel_crtc->cursor_cntl != cntl) {
6084 serge 9981
		I915_WRITE(CURCNTR(PIPE_A), cntl);
9982
		POSTING_READ(CURCNTR(PIPE_A));
5060 serge 9983
		intel_crtc->cursor_cntl = cntl;
9984
	}
3031 serge 9985
}
2327 Serge 9986
 
6084 serge 9987
static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
3031 serge 9988
{
9989
	struct drm_device *dev = crtc->dev;
9990
	struct drm_i915_private *dev_priv = dev->dev_private;
9991
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9992
	int pipe = intel_crtc->pipe;
6084 serge 9993
	uint32_t cntl = 0;
2327 Serge 9994
 
6084 serge 9995
	if (on) {
5060 serge 9996
		cntl = MCURSOR_GAMMA_ENABLE;
6084 serge 9997
		switch (intel_crtc->base.cursor->state->crtc_w) {
5060 serge 9998
			case 64:
9999
				cntl |= CURSOR_MODE_64_ARGB_AX;
10000
				break;
10001
			case 128:
10002
				cntl |= CURSOR_MODE_128_ARGB_AX;
10003
				break;
10004
			case 256:
10005
				cntl |= CURSOR_MODE_256_ARGB_AX;
10006
				break;
10007
			default:
6084 serge 10008
				MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
5060 serge 10009
				return;
6084 serge 10010
		}
10011
		cntl |= pipe << 28; /* Connect to correct pipe */
2327 Serge 10012
 
6084 serge 10013
		if (HAS_DDI(dev))
3480 Serge 10014
			cntl |= CURSOR_PIPE_CSC_ENABLE;
5354 serge 10015
	}
5060 serge 10016
 
6084 serge 10017
	if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
5354 serge 10018
		cntl |= CURSOR_ROTATE_180;
10019
 
5060 serge 10020
	if (intel_crtc->cursor_cntl != cntl) {
10021
		I915_WRITE(CURCNTR(pipe), cntl);
10022
		POSTING_READ(CURCNTR(pipe));
10023
		intel_crtc->cursor_cntl = cntl;
6084 serge 10024
	}
2327 Serge 10025
 
3031 serge 10026
	/* and commit changes on next vblank */
5060 serge 10027
	I915_WRITE(CURBASE(pipe), base);
10028
	POSTING_READ(CURBASE(pipe));
5354 serge 10029
 
10030
	intel_crtc->cursor_base = base;
3031 serge 10031
}
2327 Serge 10032
 
3031 serge 10033
/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5060 serge 10034
void intel_crtc_update_cursor(struct drm_crtc *crtc,
3031 serge 10035
				     bool on)
10036
{
10037
	struct drm_device *dev = crtc->dev;
10038
	struct drm_i915_private *dev_priv = dev->dev_private;
10039
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10040
	int pipe = intel_crtc->pipe;
6084 serge 10041
	struct drm_plane_state *cursor_state = crtc->cursor->state;
10042
	int x = cursor_state->crtc_x;
10043
	int y = cursor_state->crtc_y;
4560 Serge 10044
	u32 base = 0, pos = 0;
2327 Serge 10045
 
6084 serge 10046
	base = intel_crtc->cursor_addr;
2327 Serge 10047
 
6084 serge 10048
	if (x >= intel_crtc->config->pipe_src_w)
10049
		on = false;
2327 Serge 10050
 
6084 serge 10051
	if (y >= intel_crtc->config->pipe_src_h)
10052
		on = false;
2327 Serge 10053
 
3031 serge 10054
	if (x < 0) {
6084 serge 10055
		if (x + cursor_state->crtc_w <= 0)
10056
			on = false;
2327 Serge 10057
 
3031 serge 10058
		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10059
		x = -x;
10060
	}
10061
	pos |= x << CURSOR_X_SHIFT;
2327 Serge 10062
 
3031 serge 10063
	if (y < 0) {
6084 serge 10064
		if (y + cursor_state->crtc_h <= 0)
10065
			on = false;
2327 Serge 10066
 
3031 serge 10067
		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10068
		y = -y;
10069
	}
10070
	pos |= y << CURSOR_Y_SHIFT;
2327 Serge 10071
 
5060 serge 10072
	I915_WRITE(CURPOS(pipe), pos);
10073
 
5354 serge 10074
	/* ILK+ do this automagically */
10075
	if (HAS_GMCH_DISPLAY(dev) &&
6084 serge 10076
	    crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10077
		base += (cursor_state->crtc_h *
10078
			 cursor_state->crtc_w - 1) * 4;
5354 serge 10079
	}
10080
 
10081
	if (IS_845G(dev) || IS_I865G(dev))
6084 serge 10082
		i845_update_cursor(crtc, base, on);
5060 serge 10083
	else
6084 serge 10084
		i9xx_update_cursor(crtc, base, on);
3031 serge 10085
}
2327 Serge 10086
 
5354 serge 10087
static bool cursor_size_ok(struct drm_device *dev,
10088
			   uint32_t width, uint32_t height)
10089
{
10090
	if (width == 0 || height == 0)
10091
		return false;
10092
 
10093
	/*
10094
	 * 845g/865g are special in that they are only limited by
10095
	 * the width of their cursors, the height is arbitrary up to
10096
	 * the precision of the register. Everything else requires
10097
	 * square cursors, limited to a few power-of-two sizes.
6084 serge 10098
	 */
5354 serge 10099
	if (IS_845G(dev) || IS_I865G(dev)) {
10100
		if ((width & 63) != 0)
10101
			return false;
10102
 
10103
		if (width > (IS_845G(dev) ? 64 : 512))
10104
			return false;
10105
 
10106
		if (height > 1023)
10107
			return false;
10108
	} else {
10109
		switch (width | height) {
10110
		case 256:
10111
		case 128:
10112
			if (IS_GEN2(dev))
10113
				return false;
10114
		case 64:
10115
			break;
10116
		default:
10117
			return false;
10118
		}
10119
	}
10120
 
10121
	return true;
10122
}
10123
 
2330 Serge 10124
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10125
				 u16 *blue, uint32_t start, uint32_t size)
10126
{
10127
	int end = (start + size > 256) ? 256 : start + size, i;
10128
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327 Serge 10129
 
2330 Serge 10130
	for (i = start; i < end; i++) {
10131
		intel_crtc->lut_r[i] = red[i] >> 8;
10132
		intel_crtc->lut_g[i] = green[i] >> 8;
10133
		intel_crtc->lut_b[i] = blue[i] >> 8;
10134
	}
2327 Serge 10135
 
2330 Serge 10136
	intel_crtc_load_lut(crtc);
10137
}
2327 Serge 10138
 
2330 Serge 10139
/* VESA 640x480x72Hz mode to set on the pipe */
10140
static struct drm_display_mode load_detect_mode = {
10141
	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10142
		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10143
};
2327 Serge 10144
 
4560 Serge 10145
struct drm_framebuffer *
5060 serge 10146
__intel_framebuffer_create(struct drm_device *dev,
6084 serge 10147
			   struct drm_mode_fb_cmd2 *mode_cmd,
10148
			   struct drm_i915_gem_object *obj)
3031 serge 10149
{
10150
	struct intel_framebuffer *intel_fb;
10151
	int ret;
2327 Serge 10152
 
3031 serge 10153
	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10154
	if (!intel_fb) {
5354 serge 10155
		drm_gem_object_unreference(&obj->base);
3031 serge 10156
		return ERR_PTR(-ENOMEM);
10157
	}
2327 Serge 10158
 
3031 serge 10159
	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
4560 Serge 10160
	if (ret)
10161
		goto err;
10162
 
10163
	return &intel_fb->base;
10164
err:
5354 serge 10165
	drm_gem_object_unreference(&obj->base);
6084 serge 10166
	kfree(intel_fb);
4560 Serge 10167
 
6084 serge 10168
	return ERR_PTR(ret);
3031 serge 10169
}
2327 Serge 10170
 
5060 serge 10171
static struct drm_framebuffer *
10172
intel_framebuffer_create(struct drm_device *dev,
10173
			 struct drm_mode_fb_cmd2 *mode_cmd,
10174
			 struct drm_i915_gem_object *obj)
10175
{
10176
	struct drm_framebuffer *fb;
10177
	int ret;
10178
 
10179
	ret = i915_mutex_lock_interruptible(dev);
10180
	if (ret)
10181
		return ERR_PTR(ret);
10182
	fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10183
	mutex_unlock(&dev->struct_mutex);
10184
 
10185
	return fb;
10186
}
10187
 
2330 Serge 10188
static u32
10189
intel_framebuffer_pitch_for_width(int width, int bpp)
10190
{
10191
	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10192
	return ALIGN(pitch, 64);
10193
}
2327 Serge 10194
 
2330 Serge 10195
static u32
10196
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10197
{
10198
	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5060 serge 10199
	return PAGE_ALIGN(pitch * mode->vdisplay);
2330 Serge 10200
}
2327 Serge 10201
 
2330 Serge 10202
static struct drm_framebuffer *
10203
intel_framebuffer_create_for_mode(struct drm_device *dev,
10204
				  struct drm_display_mode *mode,
10205
				  int depth, int bpp)
10206
{
10207
	struct drm_i915_gem_object *obj;
3243 Serge 10208
	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327 Serge 10209
 
5060 serge 10210
	obj = i915_gem_alloc_object(dev,
10211
				    intel_framebuffer_size_for_mode(mode, bpp));
10212
	if (obj == NULL)
10213
		return ERR_PTR(-ENOMEM);
10214
 
10215
	mode_cmd.width = mode->hdisplay;
10216
	mode_cmd.height = mode->vdisplay;
10217
	mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10218
								bpp);
10219
	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10220
 
10221
	return intel_framebuffer_create(dev, &mode_cmd, obj);
2330 Serge 10222
}
2327 Serge 10223
 
2330 Serge 10224
static struct drm_framebuffer *
10225
mode_fits_in_fbdev(struct drm_device *dev,
10226
		   struct drm_display_mode *mode)
10227
{
6084 serge 10228
#ifdef CONFIG_DRM_FBDEV_EMULATION
2330 Serge 10229
	struct drm_i915_private *dev_priv = dev->dev_private;
10230
	struct drm_i915_gem_object *obj;
10231
	struct drm_framebuffer *fb;
2327 Serge 10232
 
5060 serge 10233
	if (!dev_priv->fbdev)
4280 Serge 10234
		return NULL;
2327 Serge 10235
 
5060 serge 10236
	if (!dev_priv->fbdev->fb)
2330 Serge 10237
		return NULL;
2327 Serge 10238
 
5060 serge 10239
	obj = dev_priv->fbdev->fb->obj;
10240
	BUG_ON(!obj);
10241
 
10242
	fb = &dev_priv->fbdev->fb->base;
3031 serge 10243
	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10244
							       fb->bits_per_pixel))
4280 Serge 10245
		return NULL;
2327 Serge 10246
 
3031 serge 10247
	if (obj->base.size < mode->vdisplay * fb->pitches[0])
10248
		return NULL;
10249
 
4280 Serge 10250
	return fb;
4560 Serge 10251
#else
10252
	return NULL;
10253
#endif
2330 Serge 10254
}
2327 Serge 10255
 
6084 serge 10256
static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10257
					   struct drm_crtc *crtc,
10258
					   struct drm_display_mode *mode,
10259
					   struct drm_framebuffer *fb,
10260
					   int x, int y)
10261
{
10262
	struct drm_plane_state *plane_state;
10263
	int hdisplay, vdisplay;
10264
	int ret;
10265
 
10266
	plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10267
	if (IS_ERR(plane_state))
10268
		return PTR_ERR(plane_state);
10269
 
10270
	if (mode)
10271
		drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10272
	else
10273
		hdisplay = vdisplay = 0;
10274
 
10275
	ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10276
	if (ret)
10277
		return ret;
10278
	drm_atomic_set_fb_for_plane(plane_state, fb);
10279
	plane_state->crtc_x = 0;
10280
	plane_state->crtc_y = 0;
10281
	plane_state->crtc_w = hdisplay;
10282
	plane_state->crtc_h = vdisplay;
10283
	plane_state->src_x = x << 16;
10284
	plane_state->src_y = y << 16;
10285
	plane_state->src_w = hdisplay << 16;
10286
	plane_state->src_h = vdisplay << 16;
10287
 
10288
	return 0;
10289
}
10290
 
3031 serge 10291
bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330 Serge 10292
				struct drm_display_mode *mode,
5060 serge 10293
				struct intel_load_detect_pipe *old,
10294
				struct drm_modeset_acquire_ctx *ctx)
2330 Serge 10295
{
10296
	struct intel_crtc *intel_crtc;
3031 serge 10297
	struct intel_encoder *intel_encoder =
10298
		intel_attached_encoder(connector);
2330 Serge 10299
	struct drm_crtc *possible_crtc;
10300
	struct drm_encoder *encoder = &intel_encoder->base;
10301
	struct drm_crtc *crtc = NULL;
10302
	struct drm_device *dev = encoder->dev;
3031 serge 10303
	struct drm_framebuffer *fb;
5060 serge 10304
	struct drm_mode_config *config = &dev->mode_config;
6084 serge 10305
	struct drm_atomic_state *state = NULL;
10306
	struct drm_connector_state *connector_state;
10307
	struct intel_crtc_state *crtc_state;
5060 serge 10308
	int ret, i = -1;
2327 Serge 10309
 
2330 Serge 10310
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5060 serge 10311
		      connector->base.id, connector->name,
10312
		      encoder->base.id, encoder->name);
2327 Serge 10313
 
5060 serge 10314
retry:
10315
	ret = drm_modeset_lock(&config->connection_mutex, ctx);
10316
	if (ret)
6084 serge 10317
		goto fail;
5060 serge 10318
 
2330 Serge 10319
	/*
10320
	 * Algorithm gets a little messy:
10321
	 *
10322
	 *   - if the connector already has an assigned crtc, use it (but make
10323
	 *     sure it's on first)
10324
	 *
10325
	 *   - try to find the first unused crtc that can drive this connector,
10326
	 *     and use that if we find one
10327
	 */
2327 Serge 10328
 
2330 Serge 10329
	/* See if we already have a CRTC for this connector */
10330
	if (encoder->crtc) {
10331
		crtc = encoder->crtc;
2327 Serge 10332
 
5060 serge 10333
		ret = drm_modeset_lock(&crtc->mutex, ctx);
10334
		if (ret)
6084 serge 10335
			goto fail;
5354 serge 10336
		ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10337
		if (ret)
6084 serge 10338
			goto fail;
3480 Serge 10339
 
3031 serge 10340
		old->dpms_mode = connector->dpms;
2330 Serge 10341
		old->load_detect_temp = false;
2327 Serge 10342
 
2330 Serge 10343
		/* Make sure the crtc and connector are running */
3031 serge 10344
		if (connector->dpms != DRM_MODE_DPMS_ON)
10345
			connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327 Serge 10346
 
2330 Serge 10347
		return true;
10348
	}
2327 Serge 10349
 
2330 Serge 10350
	/* Find an unused one (if possible) */
5060 serge 10351
	for_each_crtc(dev, possible_crtc) {
2330 Serge 10352
		i++;
10353
		if (!(encoder->possible_crtcs & (1 << i)))
10354
			continue;
6084 serge 10355
		if (possible_crtc->state->enable)
5060 serge 10356
			continue;
10357
 
6084 serge 10358
		crtc = possible_crtc;
10359
		break;
10360
	}
2327 Serge 10361
 
2330 Serge 10362
	/*
10363
	 * If we didn't find an unused CRTC, don't use any.
10364
	 */
10365
	if (!crtc) {
10366
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
6084 serge 10367
		goto fail;
2330 Serge 10368
	}
2327 Serge 10369
 
5060 serge 10370
	ret = drm_modeset_lock(&crtc->mutex, ctx);
10371
	if (ret)
6084 serge 10372
		goto fail;
5354 serge 10373
	ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10374
	if (ret)
6084 serge 10375
		goto fail;
2327 Serge 10376
 
2330 Serge 10377
	intel_crtc = to_intel_crtc(crtc);
3031 serge 10378
	old->dpms_mode = connector->dpms;
2330 Serge 10379
	old->load_detect_temp = true;
10380
	old->release_fb = NULL;
2327 Serge 10381
 
6084 serge 10382
	state = drm_atomic_state_alloc(dev);
10383
	if (!state)
10384
		return false;
10385
 
10386
	state->acquire_ctx = ctx;
10387
 
10388
	connector_state = drm_atomic_get_connector_state(state, connector);
10389
	if (IS_ERR(connector_state)) {
10390
		ret = PTR_ERR(connector_state);
10391
		goto fail;
10392
	}
10393
 
10394
	connector_state->crtc = crtc;
10395
	connector_state->best_encoder = &intel_encoder->base;
10396
 
10397
	crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10398
	if (IS_ERR(crtc_state)) {
10399
		ret = PTR_ERR(crtc_state);
10400
		goto fail;
10401
	}
10402
 
10403
	crtc_state->base.active = crtc_state->base.enable = true;
10404
 
2330 Serge 10405
	if (!mode)
10406
		mode = &load_detect_mode;
2327 Serge 10407
 
2330 Serge 10408
	/* We need a framebuffer large enough to accommodate all accesses
10409
	 * that the plane may generate whilst we perform load detection.
10410
	 * We can not rely on the fbcon either being present (we get called
10411
	 * during its initialisation to detect all boot displays, or it may
10412
	 * not even exist) or that it is large enough to satisfy the
10413
	 * requested mode.
10414
	 */
3031 serge 10415
	fb = mode_fits_in_fbdev(dev, mode);
10416
	if (fb == NULL) {
2330 Serge 10417
		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031 serge 10418
		fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10419
		old->release_fb = fb;
2330 Serge 10420
	} else
10421
		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031 serge 10422
	if (IS_ERR(fb)) {
2330 Serge 10423
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5060 serge 10424
		goto fail;
2330 Serge 10425
	}
2327 Serge 10426
 
6084 serge 10427
	ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10428
	if (ret)
10429
		goto fail;
10430
 
10431
	drm_mode_copy(&crtc_state->base.mode, mode);
10432
 
10433
	if (drm_atomic_commit(state)) {
2330 Serge 10434
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10435
		if (old->release_fb)
10436
			old->release_fb->funcs->destroy(old->release_fb);
5060 serge 10437
		goto fail;
2330 Serge 10438
	}
6084 serge 10439
	crtc->primary->crtc = crtc;
2327 Serge 10440
 
2330 Serge 10441
	/* let the connector get through one full cycle before testing */
10442
	intel_wait_for_vblank(dev, intel_crtc->pipe);
10443
	return true;
5060 serge 10444
 
6084 serge 10445
fail:
10446
	drm_atomic_state_free(state);
10447
	state = NULL;
10448
 
5060 serge 10449
	if (ret == -EDEADLK) {
10450
		drm_modeset_backoff(ctx);
10451
		goto retry;
10452
	}
10453
 
10454
	return false;
2330 Serge 10455
}
2327 Serge 10456
 
3031 serge 10457
void intel_release_load_detect_pipe(struct drm_connector *connector,
6084 serge 10458
				    struct intel_load_detect_pipe *old,
10459
				    struct drm_modeset_acquire_ctx *ctx)
2330 Serge 10460
{
6084 serge 10461
	struct drm_device *dev = connector->dev;
3031 serge 10462
	struct intel_encoder *intel_encoder =
10463
		intel_attached_encoder(connector);
2330 Serge 10464
	struct drm_encoder *encoder = &intel_encoder->base;
3480 Serge 10465
	struct drm_crtc *crtc = encoder->crtc;
5060 serge 10466
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084 serge 10467
	struct drm_atomic_state *state;
10468
	struct drm_connector_state *connector_state;
10469
	struct intel_crtc_state *crtc_state;
10470
	int ret;
2327 Serge 10471
 
2330 Serge 10472
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5060 serge 10473
		      connector->base.id, connector->name,
10474
		      encoder->base.id, encoder->name);
2327 Serge 10475
 
2330 Serge 10476
	if (old->load_detect_temp) {
6084 serge 10477
		state = drm_atomic_state_alloc(dev);
10478
		if (!state)
10479
			goto fail;
3031 serge 10480
 
6084 serge 10481
		state->acquire_ctx = ctx;
10482
 
10483
		connector_state = drm_atomic_get_connector_state(state, connector);
10484
		if (IS_ERR(connector_state))
10485
			goto fail;
10486
 
10487
		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10488
		if (IS_ERR(crtc_state))
10489
			goto fail;
10490
 
10491
		connector_state->best_encoder = NULL;
10492
		connector_state->crtc = NULL;
10493
 
10494
		crtc_state->base.enable = crtc_state->base.active = false;
10495
 
10496
		ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10497
						      0, 0);
10498
		if (ret)
10499
			goto fail;
10500
 
10501
		ret = drm_atomic_commit(state);
10502
		if (ret)
10503
			goto fail;
10504
 
3480 Serge 10505
		if (old->release_fb) {
10506
			drm_framebuffer_unregister_private(old->release_fb);
10507
			drm_framebuffer_unreference(old->release_fb);
10508
		}
2327 Serge 10509
 
2330 Serge 10510
		return;
10511
	}
2327 Serge 10512
 
2330 Serge 10513
	/* Switch crtc and encoder back off if necessary */
3031 serge 10514
	if (old->dpms_mode != DRM_MODE_DPMS_ON)
10515
		connector->funcs->dpms(connector, old->dpms_mode);
6084 serge 10516
 
10517
	return;
10518
fail:
10519
	DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10520
	drm_atomic_state_free(state);
2330 Serge 10521
}
2327 Serge 10522
 
4560 Serge 10523
static int i9xx_pll_refclk(struct drm_device *dev,
6084 serge 10524
			   const struct intel_crtc_state *pipe_config)
4560 Serge 10525
{
10526
	struct drm_i915_private *dev_priv = dev->dev_private;
10527
	u32 dpll = pipe_config->dpll_hw_state.dpll;
10528
 
10529
	if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10530
		return dev_priv->vbt.lvds_ssc_freq;
10531
	else if (HAS_PCH_SPLIT(dev))
10532
		return 120000;
10533
	else if (!IS_GEN2(dev))
10534
		return 96000;
10535
	else
10536
		return 48000;
10537
}
10538
 
2330 Serge 10539
/* Returns the clock of the currently programmed mode of the given pipe. */
4104 Serge 10540
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6084 serge 10541
				struct intel_crtc_state *pipe_config)
2330 Serge 10542
{
4104 Serge 10543
	struct drm_device *dev = crtc->base.dev;
2330 Serge 10544
	struct drm_i915_private *dev_priv = dev->dev_private;
4104 Serge 10545
	int pipe = pipe_config->cpu_transcoder;
4560 Serge 10546
	u32 dpll = pipe_config->dpll_hw_state.dpll;
2330 Serge 10547
	u32 fp;
10548
	intel_clock_t clock;
6084 serge 10549
	int port_clock;
4560 Serge 10550
	int refclk = i9xx_pll_refclk(dev, pipe_config);
2327 Serge 10551
 
2330 Serge 10552
	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4560 Serge 10553
		fp = pipe_config->dpll_hw_state.fp0;
2330 Serge 10554
	else
4560 Serge 10555
		fp = pipe_config->dpll_hw_state.fp1;
2327 Serge 10556
 
2330 Serge 10557
	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10558
	if (IS_PINEVIEW(dev)) {
10559
		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10560
		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10561
	} else {
10562
		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10563
		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10564
	}
2327 Serge 10565
 
2330 Serge 10566
	if (!IS_GEN2(dev)) {
10567
		if (IS_PINEVIEW(dev))
10568
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10569
				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10570
		else
10571
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10572
			       DPLL_FPA01_P1_POST_DIV_SHIFT);
2327 Serge 10573
 
2330 Serge 10574
		switch (dpll & DPLL_MODE_MASK) {
10575
		case DPLLB_MODE_DAC_SERIAL:
10576
			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10577
				5 : 10;
10578
			break;
10579
		case DPLLB_MODE_LVDS:
10580
			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10581
				7 : 14;
10582
			break;
10583
		default:
10584
			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10585
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
4104 Serge 10586
			return;
2330 Serge 10587
		}
2327 Serge 10588
 
4104 Serge 10589
		if (IS_PINEVIEW(dev))
6084 serge 10590
			port_clock = pnv_calc_dpll_params(refclk, &clock);
4104 Serge 10591
		else
6084 serge 10592
			port_clock = i9xx_calc_dpll_params(refclk, &clock);
2330 Serge 10593
	} else {
4560 Serge 10594
		u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10595
		bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
2327 Serge 10596
 
2330 Serge 10597
		if (is_lvds) {
10598
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10599
				       DPLL_FPA01_P1_POST_DIV_SHIFT);
4560 Serge 10600
 
10601
			if (lvds & LVDS_CLKB_POWER_UP)
10602
				clock.p2 = 7;
10603
			else
6084 serge 10604
				clock.p2 = 14;
2330 Serge 10605
		} else {
10606
			if (dpll & PLL_P1_DIVIDE_BY_TWO)
10607
				clock.p1 = 2;
10608
			else {
10609
				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10610
					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10611
			}
10612
			if (dpll & PLL_P2_DIVIDE_BY_4)
10613
				clock.p2 = 4;
10614
			else
10615
				clock.p2 = 2;
4560 Serge 10616
		}
2327 Serge 10617
 
6084 serge 10618
		port_clock = i9xx_calc_dpll_params(refclk, &clock);
2330 Serge 10619
	}
2327 Serge 10620
 
4560 Serge 10621
	/*
10622
	 * This value includes pixel_multiplier. We will use
10623
	 * port_clock to compute adjusted_mode.crtc_clock in the
10624
	 * encoder's get_config() function.
10625
	 */
6084 serge 10626
	pipe_config->port_clock = port_clock;
4104 Serge 10627
}
10628
 
4560 Serge 10629
int intel_dotclock_calculate(int link_freq,
10630
			     const struct intel_link_m_n *m_n)
4104 Serge 10631
{
10632
	/*
10633
	 * The calculation for the data clock is:
4560 Serge 10634
	 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4104 Serge 10635
	 * But we want to avoid losing precison if possible, so:
4560 Serge 10636
	 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4104 Serge 10637
	 *
10638
	 * and the link clock is simpler:
4560 Serge 10639
	 * link_clock = (m * link_clock) / n
2330 Serge 10640
	 */
2327 Serge 10641
 
4560 Serge 10642
	if (!m_n->link_n)
10643
		return 0;
4104 Serge 10644
 
4560 Serge 10645
	return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10646
}
4104 Serge 10647
 
4560 Serge 10648
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
6084 serge 10649
				   struct intel_crtc_state *pipe_config)
4560 Serge 10650
{
10651
	struct drm_device *dev = crtc->base.dev;
4104 Serge 10652
 
4560 Serge 10653
	/* read out port_clock from the DPLL */
10654
	i9xx_crtc_clock_get(crtc, pipe_config);
4104 Serge 10655
 
4560 Serge 10656
	/*
10657
	 * This value does not include pixel_multiplier.
10658
	 * We will check that port_clock and adjusted_mode.crtc_clock
10659
	 * agree once we know their relationship in the encoder's
10660
	 * get_config() function.
10661
	 */
6084 serge 10662
	pipe_config->base.adjusted_mode.crtc_clock =
4560 Serge 10663
		intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10664
					 &pipe_config->fdi_m_n);
2330 Serge 10665
}
2327 Serge 10666
 
2330 Serge 10667
/** Returns the currently programmed mode of the given pipe. */
10668
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10669
					     struct drm_crtc *crtc)
10670
{
10671
	struct drm_i915_private *dev_priv = dev->dev_private;
10672
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084 serge 10673
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2330 Serge 10674
	struct drm_display_mode *mode;
6084 serge 10675
	struct intel_crtc_state pipe_config;
3243 Serge 10676
	int htot = I915_READ(HTOTAL(cpu_transcoder));
10677
	int hsync = I915_READ(HSYNC(cpu_transcoder));
10678
	int vtot = I915_READ(VTOTAL(cpu_transcoder));
10679
	int vsync = I915_READ(VSYNC(cpu_transcoder));
4560 Serge 10680
	enum pipe pipe = intel_crtc->pipe;
2327 Serge 10681
 
2330 Serge 10682
	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10683
	if (!mode)
10684
		return NULL;
10685
 
4104 Serge 10686
	/*
10687
	 * Construct a pipe_config sufficient for getting the clock info
10688
	 * back out of crtc_clock_get.
10689
	 *
10690
	 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10691
	 * to use a real value here instead.
10692
	 */
4560 Serge 10693
	pipe_config.cpu_transcoder = (enum transcoder) pipe;
4104 Serge 10694
	pipe_config.pixel_multiplier = 1;
4560 Serge 10695
	pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10696
	pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10697
	pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
4104 Serge 10698
	i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10699
 
4560 Serge 10700
	mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
2330 Serge 10701
	mode->hdisplay = (htot & 0xffff) + 1;
10702
	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10703
	mode->hsync_start = (hsync & 0xffff) + 1;
10704
	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10705
	mode->vdisplay = (vtot & 0xffff) + 1;
10706
	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10707
	mode->vsync_start = (vsync & 0xffff) + 1;
10708
	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10709
 
10710
	drm_mode_set_name(mode);
10711
 
10712
	return mode;
10713
}
10714
 
3031 serge 10715
void intel_mark_busy(struct drm_device *dev)
10716
{
4104 Serge 10717
	struct drm_i915_private *dev_priv = dev->dev_private;
10718
 
5060 serge 10719
	if (dev_priv->mm.busy)
10720
		return;
10721
 
10722
	intel_runtime_pm_get(dev_priv);
4104 Serge 10723
	i915_update_gfx_val(dev_priv);
6084 serge 10724
	if (INTEL_INFO(dev)->gen >= 6)
10725
		gen6_rps_busy(dev_priv);
5060 serge 10726
	dev_priv->mm.busy = true;
3031 serge 10727
}
2327 Serge 10728
 
3031 serge 10729
void intel_mark_idle(struct drm_device *dev)
10730
{
4104 Serge 10731
	struct drm_i915_private *dev_priv = dev->dev_private;
2327 Serge 10732
 
5060 serge 10733
	if (!dev_priv->mm.busy)
3031 serge 10734
		return;
2327 Serge 10735
 
5060 serge 10736
	dev_priv->mm.busy = false;
10737
 
10738
	if (INTEL_INFO(dev)->gen >= 6)
4560 Serge 10739
		gen6_rps_idle(dev->dev_private);
5060 serge 10740
 
10741
	intel_runtime_pm_put(dev_priv);
3031 serge 10742
}
2327 Serge 10743
 
2330 Serge 10744
static void intel_crtc_destroy(struct drm_crtc *crtc)
10745
{
10746
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10747
	struct drm_device *dev = crtc->dev;
10748
	struct intel_unpin_work *work;
2327 Serge 10749
 
5354 serge 10750
	spin_lock_irq(&dev->event_lock);
2330 Serge 10751
	work = intel_crtc->unpin_work;
10752
	intel_crtc->unpin_work = NULL;
5354 serge 10753
	spin_unlock_irq(&dev->event_lock);
2327 Serge 10754
 
2330 Serge 10755
	if (work) {
4293 Serge 10756
		cancel_work_sync(&work->work);
2330 Serge 10757
		kfree(work);
10758
	}
2327 Serge 10759
 
2330 Serge 10760
	drm_crtc_cleanup(crtc);
2327 Serge 10761
 
2330 Serge 10762
	kfree(intel_crtc);
10763
}
2327 Serge 10764
 
3031 serge 10765
static void intel_unpin_work_fn(struct work_struct *__work)
10766
{
10767
	struct intel_unpin_work *work =
10768
		container_of(__work, struct intel_unpin_work, work);
6084 serge 10769
	struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10770
	struct drm_device *dev = crtc->base.dev;
10771
	struct drm_plane *primary = crtc->base.primary;
2327 Serge 10772
 
3243 Serge 10773
	mutex_lock(&dev->struct_mutex);
6084 serge 10774
	intel_unpin_fb_obj(work->old_fb, primary->state);
3031 serge 10775
	drm_gem_object_unreference(&work->pending_flip_obj->base);
2327 Serge 10776
 
6084 serge 10777
	if (work->flip_queued_req)
10778
		i915_gem_request_assign(&work->flip_queued_req, NULL);
3243 Serge 10779
	mutex_unlock(&dev->struct_mutex);
10780
 
6084 serge 10781
	intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10782
	drm_framebuffer_unreference(work->old_fb);
5354 serge 10783
 
6084 serge 10784
	BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10785
	atomic_dec(&crtc->unpin_work_count);
3243 Serge 10786
 
3031 serge 10787
	kfree(work);
10788
}
2327 Serge 10789
 
3031 serge 10790
static void do_intel_finish_page_flip(struct drm_device *dev,
10791
				      struct drm_crtc *crtc)
10792
{
10793
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10794
	struct intel_unpin_work *work;
10795
	unsigned long flags;
2327 Serge 10796
 
3031 serge 10797
	/* Ignore early vblank irqs */
10798
	if (intel_crtc == NULL)
10799
		return;
2327 Serge 10800
 
5354 serge 10801
	/*
10802
	 * This is called both by irq handlers and the reset code (to complete
10803
	 * lost pageflips) so needs the full irqsave spinlocks.
10804
	 */
3031 serge 10805
	spin_lock_irqsave(&dev->event_lock, flags);
10806
	work = intel_crtc->unpin_work;
3243 Serge 10807
 
10808
	/* Ensure we don't miss a work->pending update ... */
10809
	smp_rmb();
10810
 
10811
	if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
3031 serge 10812
		spin_unlock_irqrestore(&dev->event_lock, flags);
10813
		return;
10814
	}
2327 Serge 10815
 
5354 serge 10816
	page_flip_completed(intel_crtc);
3243 Serge 10817
 
3031 serge 10818
	spin_unlock_irqrestore(&dev->event_lock, flags);
10819
}
2327 Serge 10820
 
3031 serge 10821
void intel_finish_page_flip(struct drm_device *dev, int pipe)
10822
{
5060 serge 10823
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 10824
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327 Serge 10825
 
3031 serge 10826
	do_intel_finish_page_flip(dev, crtc);
10827
}
2327 Serge 10828
 
3031 serge 10829
void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10830
{
5060 serge 10831
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 10832
	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327 Serge 10833
 
3031 serge 10834
	do_intel_finish_page_flip(dev, crtc);
10835
}
2327 Serge 10836
 
5060 serge 10837
/* Is 'a' after or equal to 'b'? */
10838
static bool g4x_flip_count_after_eq(u32 a, u32 b)
10839
{
10840
	return !((a - b) & 0x80000000);
10841
}
10842
 
10843
static bool page_flip_finished(struct intel_crtc *crtc)
10844
{
10845
	struct drm_device *dev = crtc->base.dev;
10846
	struct drm_i915_private *dev_priv = dev->dev_private;
10847
 
5354 serge 10848
	if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10849
	    crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10850
		return true;
10851
 
5060 serge 10852
	/*
10853
	 * The relevant registers doen't exist on pre-ctg.
10854
	 * As the flip done interrupt doesn't trigger for mmio
10855
	 * flips on gmch platforms, a flip count check isn't
10856
	 * really needed there. But since ctg has the registers,
10857
	 * include it in the check anyway.
10858
	 */
10859
	if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10860
		return true;
10861
 
10862
	/*
10863
	 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10864
	 * used the same base address. In that case the mmio flip might
10865
	 * have completed, but the CS hasn't even executed the flip yet.
10866
	 *
10867
	 * A flip count check isn't enough as the CS might have updated
10868
	 * the base address just after start of vblank, but before we
10869
	 * managed to process the interrupt. This means we'd complete the
10870
	 * CS flip too soon.
10871
	 *
10872
	 * Combining both checks should get us a good enough result. It may
10873
	 * still happen that the CS flip has been executed, but has not
10874
	 * yet actually completed. But in case the base address is the same
10875
	 * anyway, we don't really care.
10876
	 */
10877
	return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10878
		crtc->unpin_work->gtt_offset &&
6084 serge 10879
		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
5060 serge 10880
				    crtc->unpin_work->flip_count);
10881
}
10882
 
3031 serge 10883
void intel_prepare_page_flip(struct drm_device *dev, int plane)
10884
{
5060 serge 10885
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 10886
	struct intel_crtc *intel_crtc =
10887
		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10888
	unsigned long flags;
2327 Serge 10889
 
5354 serge 10890
 
10891
	/*
10892
	 * This is called both by irq handlers and the reset code (to complete
10893
	 * lost pageflips) so needs the full irqsave spinlocks.
10894
	 *
10895
	 * NB: An MMIO update of the plane base pointer will also
3243 Serge 10896
	 * generate a page-flip completion irq, i.e. every modeset
10897
	 * is also accompanied by a spurious intel_prepare_page_flip().
10898
	 */
3031 serge 10899
	spin_lock_irqsave(&dev->event_lock, flags);
5060 serge 10900
	if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
3243 Serge 10901
		atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
3031 serge 10902
	spin_unlock_irqrestore(&dev->event_lock, flags);
10903
}
2327 Serge 10904
 
6084 serge 10905
static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
3243 Serge 10906
{
10907
	/* Ensure that the work item is consistent when activating it ... */
10908
	smp_wmb();
6084 serge 10909
	atomic_set(&work->pending, INTEL_FLIP_PENDING);
3243 Serge 10910
	/* and that it is marked active as soon as the irq could fire. */
10911
	smp_wmb();
10912
}
6283 serge 10913
#if 0
3031 serge 10914
static int intel_gen2_queue_flip(struct drm_device *dev,
10915
				 struct drm_crtc *crtc,
10916
				 struct drm_framebuffer *fb,
4104 Serge 10917
				 struct drm_i915_gem_object *obj,
6084 serge 10918
				 struct drm_i915_gem_request *req,
4104 Serge 10919
				 uint32_t flags)
3031 serge 10920
{
6084 serge 10921
	struct intel_engine_cs *ring = req->ring;
3031 serge 10922
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10923
	u32 flip_mask;
10924
	int ret;
2327 Serge 10925
 
6084 serge 10926
	ret = intel_ring_begin(req, 6);
3031 serge 10927
	if (ret)
5060 serge 10928
		return ret;
2327 Serge 10929
 
3031 serge 10930
	/* Can't queue multiple flips, so wait for the previous
10931
	 * one to finish before executing the next.
10932
	 */
10933
	if (intel_crtc->plane)
10934
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10935
	else
10936
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10937
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10938
	intel_ring_emit(ring, MI_NOOP);
10939
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
10940
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10941
	intel_ring_emit(ring, fb->pitches[0]);
5060 serge 10942
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031 serge 10943
	intel_ring_emit(ring, 0); /* aux display base address, unused */
3243 Serge 10944
 
6084 serge 10945
	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031 serge 10946
	return 0;
10947
}
2327 Serge 10948
 
3031 serge 10949
static int intel_gen3_queue_flip(struct drm_device *dev,
10950
				 struct drm_crtc *crtc,
10951
				 struct drm_framebuffer *fb,
4104 Serge 10952
				 struct drm_i915_gem_object *obj,
6084 serge 10953
				 struct drm_i915_gem_request *req,
4104 Serge 10954
				 uint32_t flags)
3031 serge 10955
{
6084 serge 10956
	struct intel_engine_cs *ring = req->ring;
3031 serge 10957
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10958
	u32 flip_mask;
10959
	int ret;
2327 Serge 10960
 
6084 serge 10961
	ret = intel_ring_begin(req, 6);
3031 serge 10962
	if (ret)
5060 serge 10963
		return ret;
2327 Serge 10964
 
3031 serge 10965
	if (intel_crtc->plane)
10966
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10967
	else
10968
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10969
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10970
	intel_ring_emit(ring, MI_NOOP);
10971
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10972
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10973
	intel_ring_emit(ring, fb->pitches[0]);
5060 serge 10974
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031 serge 10975
	intel_ring_emit(ring, MI_NOOP);
2327 Serge 10976
 
6084 serge 10977
	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031 serge 10978
	return 0;
10979
}
2327 Serge 10980
 
3031 serge 10981
static int intel_gen4_queue_flip(struct drm_device *dev,
10982
				 struct drm_crtc *crtc,
10983
				 struct drm_framebuffer *fb,
4104 Serge 10984
				 struct drm_i915_gem_object *obj,
6084 serge 10985
				 struct drm_i915_gem_request *req,
4104 Serge 10986
				 uint32_t flags)
3031 serge 10987
{
6084 serge 10988
	struct intel_engine_cs *ring = req->ring;
3031 serge 10989
	struct drm_i915_private *dev_priv = dev->dev_private;
10990
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10991
	uint32_t pf, pipesrc;
10992
	int ret;
2327 Serge 10993
 
6084 serge 10994
	ret = intel_ring_begin(req, 4);
3031 serge 10995
	if (ret)
5060 serge 10996
		return ret;
2327 Serge 10997
 
3031 serge 10998
	/* i965+ uses the linear or tiled offsets from the
10999
	 * Display Registers (which do not change across a page-flip)
11000
	 * so we need only reprogram the base address.
11001
	 */
11002
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
11003
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11004
	intel_ring_emit(ring, fb->pitches[0]);
5060 serge 11005
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
3031 serge 11006
			obj->tiling_mode);
2327 Serge 11007
 
3031 serge 11008
	/* XXX Enabling the panel-fitter across page-flip is so far
11009
	 * untested on non-native modes, so ignore it for now.
11010
	 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11011
	 */
11012
	pf = 0;
11013
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11014
	intel_ring_emit(ring, pf | pipesrc);
3243 Serge 11015
 
6084 serge 11016
	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031 serge 11017
	return 0;
11018
}
2327 Serge 11019
 
3031 serge 11020
static int intel_gen6_queue_flip(struct drm_device *dev,
11021
				 struct drm_crtc *crtc,
11022
				 struct drm_framebuffer *fb,
4104 Serge 11023
				 struct drm_i915_gem_object *obj,
6084 serge 11024
				 struct drm_i915_gem_request *req,
4104 Serge 11025
				 uint32_t flags)
3031 serge 11026
{
6084 serge 11027
	struct intel_engine_cs *ring = req->ring;
3031 serge 11028
	struct drm_i915_private *dev_priv = dev->dev_private;
11029
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11030
	uint32_t pf, pipesrc;
11031
	int ret;
2327 Serge 11032
 
6084 serge 11033
	ret = intel_ring_begin(req, 4);
3031 serge 11034
	if (ret)
5060 serge 11035
		return ret;
2327 Serge 11036
 
3031 serge 11037
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
11038
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11039
	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5060 serge 11040
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
2327 Serge 11041
 
3031 serge 11042
	/* Contrary to the suggestions in the documentation,
11043
	 * "Enable Panel Fitter" does not seem to be required when page
11044
	 * flipping with a non-native mode, and worse causes a normal
11045
	 * modeset to fail.
11046
	 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11047
	 */
11048
	pf = 0;
11049
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11050
	intel_ring_emit(ring, pf | pipesrc);
3243 Serge 11051
 
6084 serge 11052
	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031 serge 11053
	return 0;
11054
}
2327 Serge 11055
 
3031 serge 11056
static int intel_gen7_queue_flip(struct drm_device *dev,
11057
				 struct drm_crtc *crtc,
11058
				 struct drm_framebuffer *fb,
4104 Serge 11059
				 struct drm_i915_gem_object *obj,
6084 serge 11060
				 struct drm_i915_gem_request *req,
4104 Serge 11061
				 uint32_t flags)
3031 serge 11062
{
6084 serge 11063
	struct intel_engine_cs *ring = req->ring;
3031 serge 11064
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11065
	uint32_t plane_bit = 0;
4104 Serge 11066
	int len, ret;
2327 Serge 11067
 
5060 serge 11068
	switch (intel_crtc->plane) {
3031 serge 11069
	case PLANE_A:
11070
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11071
		break;
11072
	case PLANE_B:
11073
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11074
		break;
11075
	case PLANE_C:
11076
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11077
		break;
11078
	default:
11079
		WARN_ONCE(1, "unknown plane in flip command\n");
5060 serge 11080
		return -ENODEV;
3031 serge 11081
	}
2327 Serge 11082
 
4104 Serge 11083
	len = 4;
5060 serge 11084
	if (ring->id == RCS) {
4104 Serge 11085
		len += 6;
5060 serge 11086
		/*
11087
		 * On Gen 8, SRM is now taking an extra dword to accommodate
11088
		 * 48bits addresses, and we need a NOOP for the batch size to
11089
		 * stay even.
11090
		 */
11091
		if (IS_GEN8(dev))
11092
			len += 2;
11093
	}
4104 Serge 11094
 
5060 serge 11095
	/*
11096
	 * BSpec MI_DISPLAY_FLIP for IVB:
11097
	 * "The full packet must be contained within the same cache line."
11098
	 *
11099
	 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11100
	 * cacheline, if we ever start emitting more commands before
11101
	 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11102
	 * then do the cacheline alignment, and finally emit the
11103
	 * MI_DISPLAY_FLIP.
11104
	 */
6084 serge 11105
	ret = intel_ring_cacheline_align(req);
5060 serge 11106
	if (ret)
11107
		return ret;
11108
 
6084 serge 11109
	ret = intel_ring_begin(req, len);
3031 serge 11110
	if (ret)
5060 serge 11111
		return ret;
2327 Serge 11112
 
4104 Serge 11113
	/* Unmask the flip-done completion message. Note that the bspec says that
11114
	 * we should do this for both the BCS and RCS, and that we must not unmask
11115
	 * more than one flip event at any time (or ensure that one flip message
11116
	 * can be sent by waiting for flip-done prior to queueing new flips).
11117
	 * Experimentation says that BCS works despite DERRMR masking all
11118
	 * flip-done completion events and that unmasking all planes at once
11119
	 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11120
	 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11121
	 */
11122
	if (ring->id == RCS) {
11123
		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11124
		intel_ring_emit(ring, DERRMR);
11125
		intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11126
					DERRMR_PIPEB_PRI_FLIP_DONE |
11127
					DERRMR_PIPEC_PRI_FLIP_DONE));
5060 serge 11128
		if (IS_GEN8(dev))
6084 serge 11129
			intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
5060 serge 11130
					      MI_SRM_LRM_GLOBAL_GTT);
11131
		else
6084 serge 11132
			intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11133
					      MI_SRM_LRM_GLOBAL_GTT);
4104 Serge 11134
		intel_ring_emit(ring, DERRMR);
11135
		intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
5060 serge 11136
		if (IS_GEN8(dev)) {
11137
			intel_ring_emit(ring, 0);
11138
			intel_ring_emit(ring, MI_NOOP);
11139
		}
4104 Serge 11140
	}
11141
 
3031 serge 11142
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11143
	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5060 serge 11144
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031 serge 11145
	intel_ring_emit(ring, (MI_NOOP));
3243 Serge 11146
 
6084 serge 11147
	intel_mark_page_flip_active(intel_crtc->unpin_work);
3031 serge 11148
	return 0;
11149
}
2327 Serge 11150
 
6084 serge 11151
static bool use_mmio_flip(struct intel_engine_cs *ring,
11152
			  struct drm_i915_gem_object *obj)
11153
{
11154
	/*
11155
	 * This is not being used for older platforms, because
11156
	 * non-availability of flip done interrupt forces us to use
11157
	 * CS flips. Older platforms derive flip done using some clever
11158
	 * tricks involving the flip_pending status bits and vblank irqs.
11159
	 * So using MMIO flips there would disrupt this mechanism.
11160
	 */
11161
 
11162
	if (ring == NULL)
11163
		return true;
11164
 
11165
	if (INTEL_INFO(ring->dev)->gen < 5)
11166
		return false;
11167
 
11168
	if (i915.use_mmio_flip < 0)
11169
		return false;
11170
	else if (i915.use_mmio_flip > 0)
11171
		return true;
11172
	else if (i915.enable_execlists)
11173
		return true;
11174
	else
11175
		return ring != i915_gem_request_get_ring(obj->last_write_req);
11176
}
11177
 
11178
static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11179
			     struct intel_unpin_work *work)
11180
{
11181
	struct drm_device *dev = intel_crtc->base.dev;
11182
	struct drm_i915_private *dev_priv = dev->dev_private;
11183
	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11184
	const enum pipe pipe = intel_crtc->pipe;
11185
	u32 ctl, stride;
11186
 
11187
	ctl = I915_READ(PLANE_CTL(pipe, 0));
11188
	ctl &= ~PLANE_CTL_TILED_MASK;
11189
	switch (fb->modifier[0]) {
11190
	case DRM_FORMAT_MOD_NONE:
11191
		break;
11192
	case I915_FORMAT_MOD_X_TILED:
11193
		ctl |= PLANE_CTL_TILED_X;
11194
		break;
11195
	case I915_FORMAT_MOD_Y_TILED:
11196
		ctl |= PLANE_CTL_TILED_Y;
11197
		break;
11198
	case I915_FORMAT_MOD_Yf_TILED:
11199
		ctl |= PLANE_CTL_TILED_YF;
11200
		break;
11201
	default:
11202
		MISSING_CASE(fb->modifier[0]);
11203
	}
11204
 
11205
	/*
11206
	 * The stride is either expressed as a multiple of 64 bytes chunks for
11207
	 * linear buffers or in number of tiles for tiled buffers.
11208
	 */
11209
	stride = fb->pitches[0] /
11210
		 intel_fb_stride_alignment(dev, fb->modifier[0],
11211
					   fb->pixel_format);
11212
 
11213
	/*
11214
	 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11215
	 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11216
	 */
11217
	I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11218
	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11219
 
11220
	I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11221
	POSTING_READ(PLANE_SURF(pipe, 0));
11222
}
11223
 
11224
static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11225
			     struct intel_unpin_work *work)
11226
{
11227
	struct drm_device *dev = intel_crtc->base.dev;
11228
	struct drm_i915_private *dev_priv = dev->dev_private;
11229
	struct intel_framebuffer *intel_fb =
11230
		to_intel_framebuffer(intel_crtc->base.primary->fb);
11231
	struct drm_i915_gem_object *obj = intel_fb->obj;
11232
	u32 dspcntr;
11233
	u32 reg;
11234
 
11235
	reg = DSPCNTR(intel_crtc->plane);
11236
	dspcntr = I915_READ(reg);
11237
 
11238
	if (obj->tiling_mode != I915_TILING_NONE)
11239
		dspcntr |= DISPPLANE_TILED;
11240
	else
11241
		dspcntr &= ~DISPPLANE_TILED;
11242
 
11243
	I915_WRITE(reg, dspcntr);
11244
 
11245
	I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11246
	POSTING_READ(DSPSURF(intel_crtc->plane));
11247
}
11248
 
11249
/*
11250
 * XXX: This is the temporary way to update the plane registers until we get
11251
 * around to using the usual plane update functions for MMIO flips
11252
 */
11253
static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11254
{
11255
	struct intel_crtc *crtc = mmio_flip->crtc;
11256
	struct intel_unpin_work *work;
11257
 
11258
	spin_lock_irq(&crtc->base.dev->event_lock);
11259
	work = crtc->unpin_work;
11260
	spin_unlock_irq(&crtc->base.dev->event_lock);
11261
	if (work == NULL)
11262
		return;
11263
 
11264
	intel_mark_page_flip_active(work);
11265
 
11266
	intel_pipe_update_start(crtc);
11267
 
11268
	if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11269
		skl_do_mmio_flip(crtc, work);
11270
	else
11271
		/* use_mmio_flip() retricts MMIO flips to ilk+ */
11272
		ilk_do_mmio_flip(crtc, work);
11273
 
11274
	intel_pipe_update_end(crtc);
11275
}
11276
 
11277
static void intel_mmio_flip_work_func(struct work_struct *work)
11278
{
11279
	struct intel_mmio_flip *mmio_flip =
11280
		container_of(work, struct intel_mmio_flip, work);
11281
 
11282
	if (mmio_flip->req) {
11283
		WARN_ON(__i915_wait_request(mmio_flip->req,
11284
					    mmio_flip->crtc->reset_counter,
11285
					    false, NULL,
11286
					    &mmio_flip->i915->rps.mmioflips));
11287
		i915_gem_request_unreference__unlocked(mmio_flip->req);
11288
	}
11289
 
11290
	intel_do_mmio_flip(mmio_flip);
11291
	kfree(mmio_flip);
11292
}
11293
 
11294
static int intel_queue_mmio_flip(struct drm_device *dev,
11295
				 struct drm_crtc *crtc,
11296
				 struct drm_framebuffer *fb,
11297
				 struct drm_i915_gem_object *obj,
11298
				 struct intel_engine_cs *ring,
11299
				 uint32_t flags)
11300
{
11301
	struct intel_mmio_flip *mmio_flip;
11302
 
11303
	mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11304
	if (mmio_flip == NULL)
11305
		return -ENOMEM;
11306
 
11307
	mmio_flip->i915 = to_i915(dev);
11308
	mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11309
	mmio_flip->crtc = to_intel_crtc(crtc);
11310
 
11311
	INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11312
	schedule_work(&mmio_flip->work);
11313
 
11314
	return 0;
11315
}
11316
 
3031 serge 11317
static int intel_default_queue_flip(struct drm_device *dev,
11318
				    struct drm_crtc *crtc,
11319
				    struct drm_framebuffer *fb,
4104 Serge 11320
				    struct drm_i915_gem_object *obj,
6084 serge 11321
				    struct drm_i915_gem_request *req,
4104 Serge 11322
				    uint32_t flags)
3031 serge 11323
{
11324
	return -ENODEV;
11325
}
2327 Serge 11326
 
6084 serge 11327
static bool __intel_pageflip_stall_check(struct drm_device *dev,
11328
					 struct drm_crtc *crtc)
11329
{
11330
	struct drm_i915_private *dev_priv = dev->dev_private;
11331
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11332
	struct intel_unpin_work *work = intel_crtc->unpin_work;
11333
	u32 addr;
11334
 
11335
	if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11336
		return true;
11337
 
11338
	if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11339
		return false;
11340
 
11341
	if (!work->enable_stall_check)
11342
		return false;
11343
 
11344
	if (work->flip_ready_vblank == 0) {
11345
		if (work->flip_queued_req &&
11346
		    !i915_gem_request_completed(work->flip_queued_req, true))
11347
			return false;
11348
 
11349
		work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11350
	}
11351
 
11352
	if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11353
		return false;
11354
 
11355
	/* Potential stall - if we see that the flip has happened,
11356
	 * assume a missed interrupt. */
11357
	if (INTEL_INFO(dev)->gen >= 4)
11358
		addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11359
	else
11360
		addr = I915_READ(DSPADDR(intel_crtc->plane));
11361
 
11362
	/* There is a potential issue here with a false positive after a flip
11363
	 * to the same address. We could address this by checking for a
11364
	 * non-incrementing frame counter.
11365
	 */
11366
	return addr == work->gtt_offset;
11367
}
11368
 
11369
void intel_check_page_flip(struct drm_device *dev, int pipe)
11370
{
11371
	struct drm_i915_private *dev_priv = dev->dev_private;
11372
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11373
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11374
	struct intel_unpin_work *work;
11375
 
11376
	WARN_ON(!in_interrupt());
11377
 
11378
	if (crtc == NULL)
11379
		return;
11380
 
11381
	spin_lock(&dev->event_lock);
11382
	work = intel_crtc->unpin_work;
11383
	if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11384
		WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11385
			 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11386
		page_flip_completed(intel_crtc);
11387
		work = NULL;
11388
	}
11389
	if (work != NULL &&
11390
	    drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11391
		intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11392
	spin_unlock(&dev->event_lock);
11393
}
6283 serge 11394
#endif
3031 serge 11395
static int intel_crtc_page_flip(struct drm_crtc *crtc,
11396
				struct drm_framebuffer *fb,
4104 Serge 11397
				struct drm_pending_vblank_event *event,
11398
				uint32_t page_flip_flags)
3031 serge 11399
{
11400
	struct drm_device *dev = crtc->dev;
11401
	struct drm_i915_private *dev_priv = dev->dev_private;
5060 serge 11402
	struct drm_framebuffer *old_fb = crtc->primary->fb;
11403
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3031 serge 11404
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084 serge 11405
	struct drm_plane *primary = crtc->primary;
5060 serge 11406
	enum pipe pipe = intel_crtc->pipe;
3031 serge 11407
	struct intel_unpin_work *work;
5060 serge 11408
	struct intel_engine_cs *ring;
6084 serge 11409
	bool mmio_flip;
11410
	struct drm_i915_gem_request *request = NULL;
3031 serge 11411
	int ret;
2327 Serge 11412
 
5060 serge 11413
	/*
11414
	 * drm_mode_page_flip_ioctl() should already catch this, but double
11415
	 * check to be safe.  In the future we may enable pageflipping from
11416
	 * a disabled primary plane.
11417
	 */
11418
	if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11419
		return -EBUSY;
11420
 
3031 serge 11421
	/* Can't change pixel format via MI display flips. */
5060 serge 11422
	if (fb->pixel_format != crtc->primary->fb->pixel_format)
3031 serge 11423
		return -EINVAL;
2327 Serge 11424
 
3031 serge 11425
	/*
11426
	 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11427
	 * Note that pitch changes could also affect these register.
11428
	 */
11429
	if (INTEL_INFO(dev)->gen > 3 &&
5060 serge 11430
	    (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11431
	     fb->pitches[0] != crtc->primary->fb->pitches[0]))
3031 serge 11432
		return -EINVAL;
2327 Serge 11433
 
5354 serge 11434
	if (i915_terminally_wedged(&dev_priv->gpu_error))
11435
		goto out_hang;
11436
 
4560 Serge 11437
	work = kzalloc(sizeof(*work), GFP_KERNEL);
3031 serge 11438
	if (work == NULL)
11439
		return -ENOMEM;
2327 Serge 11440
 
3031 serge 11441
	work->event = event;
3243 Serge 11442
	work->crtc = crtc;
6084 serge 11443
	work->old_fb = old_fb;
6283 serge 11444
//	INIT_WORK(&work->work, intel_unpin_work_fn);
2327 Serge 11445
 
5060 serge 11446
	ret = drm_crtc_vblank_get(crtc);
3031 serge 11447
	if (ret)
11448
		goto free_work;
2327 Serge 11449
 
3031 serge 11450
	/* We borrow the event spin lock for protecting unpin_work */
5354 serge 11451
	spin_lock_irq(&dev->event_lock);
3031 serge 11452
	if (intel_crtc->unpin_work) {
5354 serge 11453
		/* Before declaring the flip queue wedged, check if
11454
		 * the hardware completed the operation behind our backs.
11455
		 */
11456
		if (__intel_pageflip_stall_check(dev, crtc)) {
11457
			DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11458
			page_flip_completed(intel_crtc);
11459
		} else {
11460
			DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11461
			spin_unlock_irq(&dev->event_lock);
11462
 
11463
			drm_crtc_vblank_put(crtc);
6084 serge 11464
			kfree(work);
11465
			return -EBUSY;
11466
		}
3031 serge 11467
	}
11468
	intel_crtc->unpin_work = work;
5354 serge 11469
	spin_unlock_irq(&dev->event_lock);
2327 Serge 11470
 
3243 Serge 11471
	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11472
		flush_workqueue(dev_priv->wq);
11473
 
3031 serge 11474
	/* Reference the objects for the scheduled work. */
6084 serge 11475
	drm_framebuffer_reference(work->old_fb);
3031 serge 11476
	drm_gem_object_reference(&obj->base);
2327 Serge 11477
 
5060 serge 11478
	crtc->primary->fb = fb;
6084 serge 11479
	update_state_fb(crtc->primary);
2327 Serge 11480
 
3031 serge 11481
	work->pending_flip_obj = obj;
2327 Serge 11482
 
6084 serge 11483
	ret = i915_mutex_lock_interruptible(dev);
11484
	if (ret)
11485
		goto cleanup;
11486
 
3243 Serge 11487
	atomic_inc(&intel_crtc->unpin_work_count);
3480 Serge 11488
	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3031 serge 11489
 
5060 serge 11490
	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
6084 serge 11491
		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
5060 serge 11492
 
11493
	if (IS_VALLEYVIEW(dev)) {
11494
		ring = &dev_priv->ring[BCS];
6084 serge 11495
		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
5060 serge 11496
			/* vlv: DISPLAY_FLIP fails to change tiling */
11497
			ring = NULL;
6084 serge 11498
	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5060 serge 11499
		ring = &dev_priv->ring[BCS];
11500
	} else if (INTEL_INFO(dev)->gen >= 7) {
6084 serge 11501
		ring = i915_gem_request_get_ring(obj->last_write_req);
5060 serge 11502
		if (ring == NULL || ring->id != RCS)
11503
			ring = &dev_priv->ring[BCS];
11504
	} else {
11505
		ring = &dev_priv->ring[RCS];
11506
	}
11507
 
6084 serge 11508
	mmio_flip = use_mmio_flip(ring, obj);
11509
 
11510
	/* When using CS flips, we want to emit semaphores between rings.
11511
	 * However, when using mmio flips we will create a task to do the
11512
	 * synchronisation, so all we want here is to pin the framebuffer
11513
	 * into the display plane and skip any waits.
11514
	 */
11515
	ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11516
					 crtc->primary->state,
11517
					 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
3031 serge 11518
	if (ret)
11519
		goto cleanup_pending;
11520
 
6084 serge 11521
	work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11522
						  obj, 0);
11523
	work->gtt_offset += intel_crtc->dspaddr_offset;
5060 serge 11524
 
6084 serge 11525
	if (mmio_flip) {
5060 serge 11526
		ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11527
					    page_flip_flags);
5354 serge 11528
		if (ret)
11529
			goto cleanup_unpin;
11530
 
6084 serge 11531
		i915_gem_request_assign(&work->flip_queued_req,
11532
					obj->last_write_req);
5354 serge 11533
	} else {
6084 serge 11534
		if (!request) {
11535
			ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11536
			if (ret)
11537
				goto cleanup_unpin;
11538
		}
5060 serge 11539
 
6084 serge 11540
		ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11541
						   page_flip_flags);
11542
		if (ret)
11543
			goto cleanup_unpin;
11544
 
11545
		i915_gem_request_assign(&work->flip_queued_req, request);
5354 serge 11546
	}
11547
 
6084 serge 11548
	if (request)
11549
		i915_add_request_no_flush(request);
11550
 
11551
	work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
5354 serge 11552
	work->enable_stall_check = true;
11553
 
6084 serge 11554
	i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11555
			  to_intel_plane(primary)->frontbuffer_bit);
3031 serge 11556
	mutex_unlock(&dev->struct_mutex);
11557
 
6084 serge 11558
	intel_fbc_disable_crtc(intel_crtc);
11559
	intel_frontbuffer_flip_prepare(dev,
11560
				       to_intel_plane(primary)->frontbuffer_bit);
11561
 
3031 serge 11562
	trace_i915_flip_request(intel_crtc->plane, obj);
11563
 
11564
	return 0;
11565
 
5060 serge 11566
cleanup_unpin:
6084 serge 11567
	intel_unpin_fb_obj(fb, crtc->primary->state);
3031 serge 11568
cleanup_pending:
6084 serge 11569
	if (request)
11570
		i915_gem_request_cancel(request);
3243 Serge 11571
	atomic_dec(&intel_crtc->unpin_work_count);
6084 serge 11572
	mutex_unlock(&dev->struct_mutex);
11573
cleanup:
5060 serge 11574
	crtc->primary->fb = old_fb;
6084 serge 11575
	update_state_fb(crtc->primary);
3031 serge 11576
 
6084 serge 11577
	drm_gem_object_unreference_unlocked(&obj->base);
11578
	drm_framebuffer_unreference(work->old_fb);
11579
 
5354 serge 11580
	spin_lock_irq(&dev->event_lock);
3031 serge 11581
	intel_crtc->unpin_work = NULL;
5354 serge 11582
	spin_unlock_irq(&dev->event_lock);
3031 serge 11583
 
5060 serge 11584
	drm_crtc_vblank_put(crtc);
3031 serge 11585
free_work:
11586
	kfree(work);
11587
 
5060 serge 11588
	if (ret == -EIO) {
6084 serge 11589
		struct drm_atomic_state *state;
11590
		struct drm_plane_state *plane_state;
11591
 
5060 serge 11592
out_hang:
6084 serge 11593
		state = drm_atomic_state_alloc(dev);
11594
		if (!state)
11595
			return -ENOMEM;
11596
		state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11597
 
11598
retry:
11599
		plane_state = drm_atomic_get_plane_state(state, primary);
11600
		ret = PTR_ERR_OR_ZERO(plane_state);
11601
		if (!ret) {
11602
			drm_atomic_set_fb_for_plane(plane_state, fb);
11603
 
11604
			ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11605
			if (!ret)
11606
				ret = drm_atomic_commit(state);
11607
		}
11608
 
11609
		if (ret == -EDEADLK) {
11610
			drm_modeset_backoff(state->acquire_ctx);
11611
			drm_atomic_state_clear(state);
11612
			goto retry;
11613
		}
11614
 
11615
		if (ret)
11616
			drm_atomic_state_free(state);
11617
 
5354 serge 11618
		if (ret == 0 && event) {
11619
			spin_lock_irq(&dev->event_lock);
5060 serge 11620
			drm_send_vblank_event(dev, pipe, event);
5354 serge 11621
			spin_unlock_irq(&dev->event_lock);
11622
		}
5060 serge 11623
	}
3031 serge 11624
	return ret;
11625
}
11626
 
11627
 
11628
/**
6084 serge 11629
 * intel_wm_need_update - Check whether watermarks need updating
11630
 * @plane: drm plane
11631
 * @state: new plane state
3031 serge 11632
 *
6084 serge 11633
 * Check current plane state versus the new one to determine whether
11634
 * watermarks need to be recalculated.
11635
 *
11636
 * Returns true or false.
3031 serge 11637
 */
6084 serge 11638
static bool intel_wm_need_update(struct drm_plane *plane,
11639
				 struct drm_plane_state *state)
3031 serge 11640
{
6084 serge 11641
	/* Update watermarks on tiling changes. */
11642
	if (!plane->state->fb || !state->fb ||
11643
	    plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11644
	    plane->state->rotation != state->rotation)
11645
		return true;
3031 serge 11646
 
6084 serge 11647
	if (plane->state->crtc_w != state->crtc_w)
11648
		return true;
11649
 
11650
	return false;
11651
}
11652
 
11653
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11654
				    struct drm_plane_state *plane_state)
11655
{
11656
	struct drm_crtc *crtc = crtc_state->crtc;
11657
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11658
	struct drm_plane *plane = plane_state->plane;
11659
	struct drm_device *dev = crtc->dev;
11660
	struct drm_i915_private *dev_priv = dev->dev_private;
11661
	struct intel_plane_state *old_plane_state =
11662
		to_intel_plane_state(plane->state);
11663
	int idx = intel_crtc->base.base.id, ret;
11664
	int i = drm_plane_index(plane);
11665
	bool mode_changed = needs_modeset(crtc_state);
11666
	bool was_crtc_enabled = crtc->state->active;
11667
	bool is_crtc_enabled = crtc_state->active;
11668
 
11669
	bool turn_off, turn_on, visible, was_visible;
11670
	struct drm_framebuffer *fb = plane_state->fb;
11671
 
11672
	if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11673
	    plane->type != DRM_PLANE_TYPE_CURSOR) {
11674
		ret = skl_update_scaler_plane(
11675
			to_intel_crtc_state(crtc_state),
11676
			to_intel_plane_state(plane_state));
11677
		if (ret)
11678
			return ret;
3031 serge 11679
	}
11680
 
6084 serge 11681
	/*
11682
	 * Disabling a plane is always okay; we just need to update
11683
	 * fb tracking in a special way since cleanup_fb() won't
11684
	 * get called by the plane helpers.
11685
	 */
11686
	if (old_plane_state->base.fb && !fb)
11687
		intel_crtc->atomic.disabled_planes |= 1 << i;
11688
 
11689
	was_visible = old_plane_state->visible;
11690
	visible = to_intel_plane_state(plane_state)->visible;
11691
 
11692
	if (!was_crtc_enabled && WARN_ON(was_visible))
11693
		was_visible = false;
11694
 
11695
	if (!is_crtc_enabled && WARN_ON(visible))
11696
		visible = false;
11697
 
11698
	if (!was_visible && !visible)
11699
		return 0;
11700
 
11701
	turn_off = was_visible && (!visible || mode_changed);
11702
	turn_on = visible && (!was_visible || mode_changed);
11703
 
11704
	DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11705
			 plane->base.id, fb ? fb->base.id : -1);
11706
 
11707
	DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11708
			 plane->base.id, was_visible, visible,
11709
			 turn_off, turn_on, mode_changed);
11710
 
11711
	if (turn_on) {
11712
		intel_crtc->atomic.update_wm_pre = true;
11713
		/* must disable cxsr around plane enable/disable */
11714
		if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11715
			intel_crtc->atomic.disable_cxsr = true;
11716
			/* to potentially re-enable cxsr */
11717
			intel_crtc->atomic.wait_vblank = true;
11718
			intel_crtc->atomic.update_wm_post = true;
11719
		}
11720
	} else if (turn_off) {
11721
		intel_crtc->atomic.update_wm_post = true;
11722
		/* must disable cxsr around plane enable/disable */
11723
		if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11724
			if (is_crtc_enabled)
11725
				intel_crtc->atomic.wait_vblank = true;
11726
			intel_crtc->atomic.disable_cxsr = true;
11727
		}
11728
	} else if (intel_wm_need_update(plane, plane_state)) {
11729
		intel_crtc->atomic.update_wm_pre = true;
3031 serge 11730
	}
5060 serge 11731
 
6084 serge 11732
	if (visible || was_visible)
11733
		intel_crtc->atomic.fb_bits |=
11734
			to_intel_plane(plane)->frontbuffer_bit;
5060 serge 11735
 
6084 serge 11736
	switch (plane->type) {
11737
	case DRM_PLANE_TYPE_PRIMARY:
11738
		intel_crtc->atomic.wait_for_flips = true;
11739
		intel_crtc->atomic.pre_disable_primary = turn_off;
11740
		intel_crtc->atomic.post_enable_primary = turn_on;
11741
 
11742
		if (turn_off) {
11743
			/*
11744
			 * FIXME: Actually if we will still have any other
11745
			 * plane enabled on the pipe we could let IPS enabled
11746
			 * still, but for now lets consider that when we make
11747
			 * primary invisible by setting DSPCNTR to 0 on
11748
			 * update_primary_plane function IPS needs to be
11749
			 * disable.
11750
			 */
11751
			intel_crtc->atomic.disable_ips = true;
11752
 
11753
			intel_crtc->atomic.disable_fbc = true;
11754
		}
11755
 
11756
		/*
11757
		 * FBC does not work on some platforms for rotated
11758
		 * planes, so disable it when rotation is not 0 and
11759
		 * update it when rotation is set back to 0.
11760
		 *
11761
		 * FIXME: This is redundant with the fbc update done in
11762
		 * the primary plane enable function except that that
11763
		 * one is done too late. We eventually need to unify
11764
		 * this.
11765
		 */
11766
 
11767
		if (visible &&
11768
		    INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11769
		    dev_priv->fbc.crtc == intel_crtc &&
11770
		    plane_state->rotation != BIT(DRM_ROTATE_0))
11771
			intel_crtc->atomic.disable_fbc = true;
11772
 
11773
		/*
11774
		 * BDW signals flip done immediately if the plane
11775
		 * is disabled, even if the plane enable is already
11776
		 * armed to occur at the next vblank :(
11777
		 */
11778
		if (turn_on && IS_BROADWELL(dev))
11779
			intel_crtc->atomic.wait_vblank = true;
11780
 
11781
		intel_crtc->atomic.update_fbc |= visible || mode_changed;
11782
		break;
11783
	case DRM_PLANE_TYPE_CURSOR:
11784
		break;
11785
	case DRM_PLANE_TYPE_OVERLAY:
11786
		if (turn_off && !mode_changed) {
11787
			intel_crtc->atomic.wait_vblank = true;
11788
			intel_crtc->atomic.update_sprite_watermarks |=
11789
				1 << i;
11790
		}
5060 serge 11791
	}
6084 serge 11792
	return 0;
3031 serge 11793
}
11794
 
6084 serge 11795
static bool encoders_cloneable(const struct intel_encoder *a,
11796
			       const struct intel_encoder *b)
3031 serge 11797
{
6084 serge 11798
	/* masks could be asymmetric, so check both ways */
11799
	return a == b || (a->cloneable & (1 << b->type) &&
11800
			  b->cloneable & (1 << a->type));
11801
}
11802
 
11803
static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11804
					 struct intel_crtc *crtc,
11805
					 struct intel_encoder *encoder)
11806
{
11807
	struct intel_encoder *source_encoder;
11808
	struct drm_connector *connector;
11809
	struct drm_connector_state *connector_state;
11810
	int i;
11811
 
11812
	for_each_connector_in_state(state, connector, connector_state, i) {
11813
		if (connector_state->crtc != &crtc->base)
11814
			continue;
11815
 
11816
		source_encoder =
11817
			to_intel_encoder(connector_state->best_encoder);
11818
		if (!encoders_cloneable(encoder, source_encoder))
11819
			return false;
11820
	}
11821
 
11822
	return true;
11823
}
11824
 
11825
static bool check_encoder_cloning(struct drm_atomic_state *state,
11826
				  struct intel_crtc *crtc)
11827
{
3031 serge 11828
	struct intel_encoder *encoder;
6084 serge 11829
	struct drm_connector *connector;
11830
	struct drm_connector_state *connector_state;
11831
	int i;
3031 serge 11832
 
6084 serge 11833
	for_each_connector_in_state(state, connector, connector_state, i) {
11834
		if (connector_state->crtc != &crtc->base)
11835
			continue;
11836
 
11837
		encoder = to_intel_encoder(connector_state->best_encoder);
11838
		if (!check_single_encoder_cloning(state, crtc, encoder))
11839
			return false;
3031 serge 11840
	}
11841
 
6084 serge 11842
	return true;
11843
}
11844
 
11845
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11846
				   struct drm_crtc_state *crtc_state)
11847
{
11848
	struct drm_device *dev = crtc->dev;
11849
	struct drm_i915_private *dev_priv = dev->dev_private;
11850
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11851
	struct intel_crtc_state *pipe_config =
11852
		to_intel_crtc_state(crtc_state);
11853
	struct drm_atomic_state *state = crtc_state->state;
11854
	int ret;
11855
	bool mode_changed = needs_modeset(crtc_state);
11856
 
11857
	if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11858
		DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11859
		return -EINVAL;
3031 serge 11860
	}
5060 serge 11861
 
6084 serge 11862
	if (mode_changed && !crtc_state->active)
11863
		intel_crtc->atomic.update_wm_post = true;
11864
 
11865
	if (mode_changed && crtc_state->enable &&
11866
	    dev_priv->display.crtc_compute_clock &&
11867
	    !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11868
		ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11869
							   pipe_config);
11870
		if (ret)
11871
			return ret;
5060 serge 11872
	}
6084 serge 11873
 
11874
	ret = 0;
11875
	if (INTEL_INFO(dev)->gen >= 9) {
11876
		if (mode_changed)
11877
			ret = skl_update_scaler_crtc(pipe_config);
11878
 
11879
		if (!ret)
11880
			ret = intel_atomic_setup_scalers(dev, intel_crtc,
11881
							 pipe_config);
11882
	}
11883
 
11884
	return ret;
3031 serge 11885
}
11886
 
6084 serge 11887
static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11888
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
11889
	.load_lut = intel_crtc_load_lut,
11890
	.atomic_begin = intel_begin_crtc_commit,
11891
	.atomic_flush = intel_finish_crtc_commit,
11892
	.atomic_check = intel_crtc_atomic_check,
11893
};
11894
 
11895
static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11896
{
11897
	struct intel_connector *connector;
11898
 
11899
	for_each_intel_connector(dev, connector) {
11900
		if (connector->base.encoder) {
11901
			connector->base.state->best_encoder =
11902
				connector->base.encoder;
11903
			connector->base.state->crtc =
11904
				connector->base.encoder->crtc;
11905
		} else {
11906
			connector->base.state->best_encoder = NULL;
11907
			connector->base.state->crtc = NULL;
11908
		}
11909
	}
11910
}
11911
 
4104 Serge 11912
static void
5060 serge 11913
connected_sink_compute_bpp(struct intel_connector *connector,
6084 serge 11914
			   struct intel_crtc_state *pipe_config)
4104 Serge 11915
{
11916
	int bpp = pipe_config->pipe_bpp;
11917
 
11918
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11919
		connector->base.base.id,
5060 serge 11920
		connector->base.name);
4104 Serge 11921
 
11922
	/* Don't use an invalid EDID bpc value */
11923
	if (connector->base.display_info.bpc &&
11924
	    connector->base.display_info.bpc * 3 < bpp) {
11925
		DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11926
			      bpp, connector->base.display_info.bpc*3);
11927
		pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11928
	}
11929
 
11930
	/* Clamp bpp to 8 on screens without EDID 1.4 */
11931
	if (connector->base.display_info.bpc == 0 && bpp > 24) {
11932
		DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11933
			      bpp);
11934
		pipe_config->pipe_bpp = 24;
11935
	}
11936
}
11937
 
3746 Serge 11938
static int
4104 Serge 11939
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
6084 serge 11940
			  struct intel_crtc_state *pipe_config)
3746 Serge 11941
{
4104 Serge 11942
	struct drm_device *dev = crtc->base.dev;
6084 serge 11943
	struct drm_atomic_state *state;
11944
	struct drm_connector *connector;
11945
	struct drm_connector_state *connector_state;
11946
	int bpp, i;
3746 Serge 11947
 
6084 serge 11948
	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11949
		bpp = 10*3;
11950
	else if (INTEL_INFO(dev)->gen >= 5)
11951
		bpp = 12*3;
11952
	else
3746 Serge 11953
		bpp = 8*3;
11954
 
6084 serge 11955
 
3746 Serge 11956
	pipe_config->pipe_bpp = bpp;
11957
 
6084 serge 11958
	state = pipe_config->base.state;
11959
 
3746 Serge 11960
	/* Clamp display bpp to EDID value */
6084 serge 11961
	for_each_connector_in_state(state, connector, connector_state, i) {
11962
		if (connector_state->crtc != &crtc->base)
3746 Serge 11963
			continue;
11964
 
6084 serge 11965
		connected_sink_compute_bpp(to_intel_connector(connector),
11966
					   pipe_config);
3746 Serge 11967
	}
11968
 
11969
	return bpp;
11970
}
11971
 
4560 Serge 11972
static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11973
{
11974
	DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11975
			"type: 0x%x flags: 0x%x\n",
11976
		mode->crtc_clock,
11977
		mode->crtc_hdisplay, mode->crtc_hsync_start,
11978
		mode->crtc_hsync_end, mode->crtc_htotal,
11979
		mode->crtc_vdisplay, mode->crtc_vsync_start,
11980
		mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11981
}
11982
 
4104 Serge 11983
static void intel_dump_pipe_config(struct intel_crtc *crtc,
6084 serge 11984
				   struct intel_crtc_state *pipe_config,
4104 Serge 11985
				   const char *context)
11986
{
6084 serge 11987
	struct drm_device *dev = crtc->base.dev;
11988
	struct drm_plane *plane;
11989
	struct intel_plane *intel_plane;
11990
	struct intel_plane_state *state;
11991
	struct drm_framebuffer *fb;
4104 Serge 11992
 
6084 serge 11993
	DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11994
		      context, pipe_config, pipe_name(crtc->pipe));
11995
 
4104 Serge 11996
	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11997
	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11998
		      pipe_config->pipe_bpp, pipe_config->dither);
11999
	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12000
		      pipe_config->has_pch_encoder,
12001
		      pipe_config->fdi_lanes,
12002
		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12003
		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12004
		      pipe_config->fdi_m_n.tu);
6084 serge 12005
	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
4560 Serge 12006
		      pipe_config->has_dp_encoder,
6084 serge 12007
		      pipe_config->lane_count,
4560 Serge 12008
		      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12009
		      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12010
		      pipe_config->dp_m_n.tu);
5354 serge 12011
 
6084 serge 12012
	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
5354 serge 12013
		      pipe_config->has_dp_encoder,
6084 serge 12014
		      pipe_config->lane_count,
5354 serge 12015
		      pipe_config->dp_m2_n2.gmch_m,
12016
		      pipe_config->dp_m2_n2.gmch_n,
12017
		      pipe_config->dp_m2_n2.link_m,
12018
		      pipe_config->dp_m2_n2.link_n,
12019
		      pipe_config->dp_m2_n2.tu);
12020
 
12021
	DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12022
		      pipe_config->has_audio,
12023
		      pipe_config->has_infoframe);
12024
 
4104 Serge 12025
	DRM_DEBUG_KMS("requested mode:\n");
6084 serge 12026
	drm_mode_debug_printmodeline(&pipe_config->base.mode);
4104 Serge 12027
	DRM_DEBUG_KMS("adjusted mode:\n");
6084 serge 12028
	drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12029
	intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
4560 Serge 12030
	DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12031
	DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12032
		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6084 serge 12033
	DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12034
		      crtc->num_scalers,
12035
		      pipe_config->scaler_state.scaler_users,
12036
		      pipe_config->scaler_state.scaler_id);
4104 Serge 12037
	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12038
		      pipe_config->gmch_pfit.control,
12039
		      pipe_config->gmch_pfit.pgm_ratios,
12040
		      pipe_config->gmch_pfit.lvds_border_bits);
12041
	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12042
		      pipe_config->pch_pfit.pos,
12043
		      pipe_config->pch_pfit.size,
12044
		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12045
	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
4560 Serge 12046
	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
4104 Serge 12047
 
6084 serge 12048
	if (IS_BROXTON(dev)) {
12049
		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12050
			      "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12051
			      "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12052
			      pipe_config->ddi_pll_sel,
12053
			      pipe_config->dpll_hw_state.ebb0,
12054
			      pipe_config->dpll_hw_state.ebb4,
12055
			      pipe_config->dpll_hw_state.pll0,
12056
			      pipe_config->dpll_hw_state.pll1,
12057
			      pipe_config->dpll_hw_state.pll2,
12058
			      pipe_config->dpll_hw_state.pll3,
12059
			      pipe_config->dpll_hw_state.pll6,
12060
			      pipe_config->dpll_hw_state.pll8,
12061
			      pipe_config->dpll_hw_state.pll9,
12062
			      pipe_config->dpll_hw_state.pll10,
12063
			      pipe_config->dpll_hw_state.pcsdw12);
12064
	} else if (IS_SKYLAKE(dev)) {
12065
		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12066
			      "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12067
			      pipe_config->ddi_pll_sel,
12068
			      pipe_config->dpll_hw_state.ctrl1,
12069
			      pipe_config->dpll_hw_state.cfgcr1,
12070
			      pipe_config->dpll_hw_state.cfgcr2);
12071
	} else if (HAS_DDI(dev)) {
12072
		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12073
			      pipe_config->ddi_pll_sel,
12074
			      pipe_config->dpll_hw_state.wrpll,
12075
			      pipe_config->dpll_hw_state.spll);
12076
	} else {
12077
		DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12078
			      "fp0: 0x%x, fp1: 0x%x\n",
12079
			      pipe_config->dpll_hw_state.dpll,
12080
			      pipe_config->dpll_hw_state.dpll_md,
12081
			      pipe_config->dpll_hw_state.fp0,
12082
			      pipe_config->dpll_hw_state.fp1);
12083
	}
5060 serge 12084
 
6084 serge 12085
	DRM_DEBUG_KMS("planes on this crtc\n");
12086
	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12087
		intel_plane = to_intel_plane(plane);
12088
		if (intel_plane->pipe != crtc->pipe)
5060 serge 12089
			continue;
12090
 
6084 serge 12091
		state = to_intel_plane_state(plane->state);
12092
		fb = state->base.fb;
12093
		if (!fb) {
12094
			DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12095
				"disabled, scaler_id = %d\n",
12096
				plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12097
				plane->base.id, intel_plane->pipe,
12098
				(crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12099
				drm_plane_index(plane), state->scaler_id);
4104 Serge 12100
			continue;
6084 serge 12101
		}
4104 Serge 12102
 
6084 serge 12103
		DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12104
			plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12105
			plane->base.id, intel_plane->pipe,
12106
			crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12107
			drm_plane_index(plane));
12108
		DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12109
			fb->base.id, fb->width, fb->height, fb->pixel_format);
12110
		DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12111
			state->scaler_id,
12112
			state->src.x1 >> 16, state->src.y1 >> 16,
12113
			drm_rect_width(&state->src) >> 16,
12114
			drm_rect_height(&state->src) >> 16,
12115
			state->dst.x1, state->dst.y1,
12116
			drm_rect_width(&state->dst), drm_rect_height(&state->dst));
4104 Serge 12117
	}
12118
}
12119
 
6084 serge 12120
static bool check_digital_port_conflicts(struct drm_atomic_state *state)
5354 serge 12121
{
6084 serge 12122
	struct drm_device *dev = state->dev;
12123
	struct drm_connector *connector;
5354 serge 12124
	unsigned int used_ports = 0;
12125
 
12126
	/*
12127
	 * Walk the connector list instead of the encoder
12128
	 * list to detect the problem on ddi platforms
12129
	 * where there's just one encoder per digital port.
12130
	 */
6084 serge 12131
	drm_for_each_connector(connector, dev) {
12132
		struct drm_connector_state *connector_state;
12133
		struct intel_encoder *encoder;
5354 serge 12134
 
6084 serge 12135
		connector_state = drm_atomic_get_existing_connector_state(state, connector);
12136
		if (!connector_state)
12137
			connector_state = connector->state;
12138
 
12139
		if (!connector_state->best_encoder)
5354 serge 12140
			continue;
12141
 
6084 serge 12142
		encoder = to_intel_encoder(connector_state->best_encoder);
5354 serge 12143
 
6084 serge 12144
		WARN_ON(!connector_state->crtc);
12145
 
5354 serge 12146
		switch (encoder->type) {
12147
			unsigned int port_mask;
12148
		case INTEL_OUTPUT_UNKNOWN:
12149
			if (WARN_ON(!HAS_DDI(dev)))
12150
				break;
12151
		case INTEL_OUTPUT_DISPLAYPORT:
12152
		case INTEL_OUTPUT_HDMI:
12153
		case INTEL_OUTPUT_EDP:
12154
			port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12155
 
12156
			/* the same port mustn't appear more than once */
12157
			if (used_ports & port_mask)
12158
				return false;
12159
 
12160
			used_ports |= port_mask;
12161
		default:
12162
			break;
12163
		}
12164
	}
12165
 
12166
	return true;
12167
}
12168
 
6084 serge 12169
static void
12170
clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12171
{
12172
	struct drm_crtc_state tmp_state;
12173
	struct intel_crtc_scaler_state scaler_state;
12174
	struct intel_dpll_hw_state dpll_hw_state;
12175
	enum intel_dpll_id shared_dpll;
12176
	uint32_t ddi_pll_sel;
12177
	bool force_thru;
12178
 
12179
	/* FIXME: before the switch to atomic started, a new pipe_config was
12180
	 * kzalloc'd. Code that depends on any field being zero should be
12181
	 * fixed, so that the crtc_state can be safely duplicated. For now,
12182
	 * only fields that are know to not cause problems are preserved. */
12183
 
12184
	tmp_state = crtc_state->base;
12185
	scaler_state = crtc_state->scaler_state;
12186
	shared_dpll = crtc_state->shared_dpll;
12187
	dpll_hw_state = crtc_state->dpll_hw_state;
12188
	ddi_pll_sel = crtc_state->ddi_pll_sel;
12189
	force_thru = crtc_state->pch_pfit.force_thru;
12190
 
12191
	memset(crtc_state, 0, sizeof *crtc_state);
12192
 
12193
	crtc_state->base = tmp_state;
12194
	crtc_state->scaler_state = scaler_state;
12195
	crtc_state->shared_dpll = shared_dpll;
12196
	crtc_state->dpll_hw_state = dpll_hw_state;
12197
	crtc_state->ddi_pll_sel = ddi_pll_sel;
12198
	crtc_state->pch_pfit.force_thru = force_thru;
12199
}
12200
 
12201
static int
3746 Serge 12202
intel_modeset_pipe_config(struct drm_crtc *crtc,
6084 serge 12203
			  struct intel_crtc_state *pipe_config)
3031 serge 12204
{
6084 serge 12205
	struct drm_atomic_state *state = pipe_config->base.state;
3031 serge 12206
	struct intel_encoder *encoder;
6084 serge 12207
	struct drm_connector *connector;
12208
	struct drm_connector_state *connector_state;
12209
	int base_bpp, ret = -EINVAL;
12210
	int i;
4104 Serge 12211
	bool retry = true;
3031 serge 12212
 
6084 serge 12213
	clear_intel_crtc_state(pipe_config);
4104 Serge 12214
 
12215
	pipe_config->cpu_transcoder =
12216
		(enum transcoder) to_intel_crtc(crtc)->pipe;
3746 Serge 12217
 
4104 Serge 12218
	/*
12219
	 * Sanitize sync polarity flags based on requested ones. If neither
12220
	 * positive or negative polarity is requested, treat this as meaning
12221
	 * negative polarity.
12222
	 */
6084 serge 12223
	if (!(pipe_config->base.adjusted_mode.flags &
4104 Serge 12224
	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
6084 serge 12225
		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4104 Serge 12226
 
6084 serge 12227
	if (!(pipe_config->base.adjusted_mode.flags &
4104 Serge 12228
	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
6084 serge 12229
		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4104 Serge 12230
 
6084 serge 12231
	base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12232
					     pipe_config);
12233
	if (base_bpp < 0)
3746 Serge 12234
		goto fail;
12235
 
4560 Serge 12236
	/*
12237
	 * Determine the real pipe dimensions. Note that stereo modes can
12238
	 * increase the actual pipe size due to the frame doubling and
12239
	 * insertion of additional space for blanks between the frame. This
12240
	 * is stored in the crtc timings. We use the requested mode to do this
12241
	 * computation to clearly distinguish it from the adjusted mode, which
12242
	 * can be changed by the connectors in the below retry loop.
12243
	 */
6084 serge 12244
	drm_crtc_get_hv_timing(&pipe_config->base.mode,
12245
			       &pipe_config->pipe_src_w,
12246
			       &pipe_config->pipe_src_h);
4560 Serge 12247
 
4104 Serge 12248
encoder_retry:
12249
	/* Ensure the port clock defaults are reset when retrying. */
12250
	pipe_config->port_clock = 0;
12251
	pipe_config->pixel_multiplier = 1;
12252
 
12253
	/* Fill in default crtc timings, allow encoders to overwrite them. */
6084 serge 12254
	drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12255
			      CRTC_STEREO_DOUBLE);
4104 Serge 12256
 
3031 serge 12257
	/* Pass our mode to the connectors and the CRTC to give them a chance to
12258
	 * adjust it according to limitations or connector properties, and also
12259
	 * a chance to reject the mode entirely.
2330 Serge 12260
	 */
6084 serge 12261
	for_each_connector_in_state(state, connector, connector_state, i) {
12262
		if (connector_state->crtc != crtc)
3031 serge 12263
			continue;
3746 Serge 12264
 
6084 serge 12265
		encoder = to_intel_encoder(connector_state->best_encoder);
12266
 
12267
		if (!(encoder->compute_config(encoder, pipe_config))) {
12268
			DRM_DEBUG_KMS("Encoder config failure\n");
12269
			goto fail;
3746 Serge 12270
		}
6084 serge 12271
	}
3746 Serge 12272
 
4104 Serge 12273
	/* Set default port clock if not overwritten by the encoder. Needs to be
12274
	 * done afterwards in case the encoder adjusts the mode. */
12275
	if (!pipe_config->port_clock)
6084 serge 12276
		pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
4560 Serge 12277
			* pipe_config->pixel_multiplier;
2327 Serge 12278
 
4104 Serge 12279
	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12280
	if (ret < 0) {
3031 serge 12281
		DRM_DEBUG_KMS("CRTC fixup failed\n");
12282
		goto fail;
12283
	}
2327 Serge 12284
 
4104 Serge 12285
	if (ret == RETRY) {
12286
		if (WARN(!retry, "loop in pipe configuration computation\n")) {
12287
			ret = -EINVAL;
12288
			goto fail;
12289
		}
12290
 
12291
		DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12292
		retry = false;
12293
		goto encoder_retry;
12294
	}
12295
 
6084 serge 12296
	/* Dithering seems to not pass-through bits correctly when it should, so
12297
	 * only enable it on 6bpc panels. */
12298
	pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12299
	DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12300
		      base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
3746 Serge 12301
 
3031 serge 12302
fail:
6084 serge 12303
	return ret;
3031 serge 12304
}
2327 Serge 12305
 
3031 serge 12306
static void
6084 serge 12307
intel_modeset_update_crtc_state(struct drm_atomic_state *state)
3031 serge 12308
{
6084 serge 12309
	struct drm_crtc *crtc;
12310
	struct drm_crtc_state *crtc_state;
12311
	int i;
3031 serge 12312
 
6084 serge 12313
	/* Double check state. */
12314
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
12315
		to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
3031 serge 12316
 
6084 serge 12317
		/* Update hwmode for vblank functions */
12318
		if (crtc->state->active)
12319
			crtc->hwmode = crtc->state->adjusted_mode;
5060 serge 12320
		else
6084 serge 12321
			crtc->hwmode.crtc_clock = 0;
3031 serge 12322
	}
2330 Serge 12323
}
2327 Serge 12324
 
4560 Serge 12325
static bool intel_fuzzy_clock_check(int clock1, int clock2)
4104 Serge 12326
{
4560 Serge 12327
	int diff;
4104 Serge 12328
 
12329
	if (clock1 == clock2)
12330
		return true;
12331
 
12332
	if (!clock1 || !clock2)
12333
		return false;
12334
 
12335
	diff = abs(clock1 - clock2);
12336
 
12337
	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12338
		return true;
12339
 
12340
	return false;
12341
}
12342
 
3031 serge 12343
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12344
	list_for_each_entry((intel_crtc), \
12345
			    &(dev)->mode_config.crtc_list, \
12346
			    base.head) \
4104 Serge 12347
		if (mask & (1 <<(intel_crtc)->pipe))
3031 serge 12348
 
3746 Serge 12349
static bool
6084 serge 12350
intel_compare_m_n(unsigned int m, unsigned int n,
12351
		  unsigned int m2, unsigned int n2,
12352
		  bool exact)
12353
{
12354
	if (m == m2 && n == n2)
12355
		return true;
12356
 
12357
	if (exact || !m || !n || !m2 || !n2)
12358
		return false;
12359
 
12360
	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12361
 
12362
	if (m > m2) {
12363
		while (m > m2) {
12364
			m2 <<= 1;
12365
			n2 <<= 1;
12366
		}
12367
	} else if (m < m2) {
12368
		while (m < m2) {
12369
			m <<= 1;
12370
			n <<= 1;
12371
		}
12372
	}
12373
 
12374
	return m == m2 && n == n2;
12375
}
12376
 
12377
static bool
12378
intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12379
		       struct intel_link_m_n *m2_n2,
12380
		       bool adjust)
12381
{
12382
	if (m_n->tu == m2_n2->tu &&
12383
	    intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12384
			      m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12385
	    intel_compare_m_n(m_n->link_m, m_n->link_n,
12386
			      m2_n2->link_m, m2_n2->link_n, !adjust)) {
12387
		if (adjust)
12388
			*m2_n2 = *m_n;
12389
 
12390
		return true;
12391
	}
12392
 
12393
	return false;
12394
}
12395
 
12396
static bool
4104 Serge 12397
intel_pipe_config_compare(struct drm_device *dev,
6084 serge 12398
			  struct intel_crtc_state *current_config,
12399
			  struct intel_crtc_state *pipe_config,
12400
			  bool adjust)
3746 Serge 12401
{
6084 serge 12402
	bool ret = true;
12403
 
12404
#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12405
	do { \
12406
		if (!adjust) \
12407
			DRM_ERROR(fmt, ##__VA_ARGS__); \
12408
		else \
12409
			DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12410
	} while (0)
12411
 
4104 Serge 12412
#define PIPE_CONF_CHECK_X(name)	\
12413
	if (current_config->name != pipe_config->name) { \
6084 serge 12414
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
4104 Serge 12415
			  "(expected 0x%08x, found 0x%08x)\n", \
12416
			  current_config->name, \
12417
			  pipe_config->name); \
6084 serge 12418
		ret = false; \
3746 Serge 12419
	}
12420
 
4104 Serge 12421
#define PIPE_CONF_CHECK_I(name)	\
12422
	if (current_config->name != pipe_config->name) { \
6084 serge 12423
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
4104 Serge 12424
			  "(expected %i, found %i)\n", \
12425
			  current_config->name, \
12426
			  pipe_config->name); \
6084 serge 12427
		ret = false; \
4104 Serge 12428
	}
12429
 
6084 serge 12430
#define PIPE_CONF_CHECK_M_N(name) \
12431
	if (!intel_compare_link_m_n(¤t_config->name, \
12432
				    &pipe_config->name,\
12433
				    adjust)) { \
12434
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12435
			  "(expected tu %i gmch %i/%i link %i/%i, " \
12436
			  "found tu %i, gmch %i/%i link %i/%i)\n", \
12437
			  current_config->name.tu, \
12438
			  current_config->name.gmch_m, \
12439
			  current_config->name.gmch_n, \
12440
			  current_config->name.link_m, \
12441
			  current_config->name.link_n, \
12442
			  pipe_config->name.tu, \
12443
			  pipe_config->name.gmch_m, \
12444
			  pipe_config->name.gmch_n, \
12445
			  pipe_config->name.link_m, \
12446
			  pipe_config->name.link_n); \
12447
		ret = false; \
12448
	}
12449
 
12450
#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12451
	if (!intel_compare_link_m_n(¤t_config->name, \
12452
				    &pipe_config->name, adjust) && \
12453
	    !intel_compare_link_m_n(¤t_config->alt_name, \
12454
				    &pipe_config->name, adjust)) { \
12455
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12456
			  "(expected tu %i gmch %i/%i link %i/%i, " \
12457
			  "or tu %i gmch %i/%i link %i/%i, " \
12458
			  "found tu %i, gmch %i/%i link %i/%i)\n", \
12459
			  current_config->name.tu, \
12460
			  current_config->name.gmch_m, \
12461
			  current_config->name.gmch_n, \
12462
			  current_config->name.link_m, \
12463
			  current_config->name.link_n, \
12464
			  current_config->alt_name.tu, \
12465
			  current_config->alt_name.gmch_m, \
12466
			  current_config->alt_name.gmch_n, \
12467
			  current_config->alt_name.link_m, \
12468
			  current_config->alt_name.link_n, \
12469
			  pipe_config->name.tu, \
12470
			  pipe_config->name.gmch_m, \
12471
			  pipe_config->name.gmch_n, \
12472
			  pipe_config->name.link_m, \
12473
			  pipe_config->name.link_n); \
12474
		ret = false; \
12475
	}
12476
 
5354 serge 12477
/* This is required for BDW+ where there is only one set of registers for
12478
 * switching between high and low RR.
12479
 * This macro can be used whenever a comparison has to be made between one
12480
 * hw state and multiple sw state variables.
12481
 */
12482
#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12483
	if ((current_config->name != pipe_config->name) && \
12484
		(current_config->alt_name != pipe_config->name)) { \
6084 serge 12485
			INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5354 serge 12486
				  "(expected %i or %i, found %i)\n", \
12487
				  current_config->name, \
12488
				  current_config->alt_name, \
12489
				  pipe_config->name); \
6084 serge 12490
			ret = false; \
5354 serge 12491
	}
12492
 
4104 Serge 12493
#define PIPE_CONF_CHECK_FLAGS(name, mask)	\
12494
	if ((current_config->name ^ pipe_config->name) & (mask)) { \
6084 serge 12495
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
4104 Serge 12496
			  "(expected %i, found %i)\n", \
12497
			  current_config->name & (mask), \
12498
			  pipe_config->name & (mask)); \
6084 serge 12499
		ret = false; \
4104 Serge 12500
	}
12501
 
4560 Serge 12502
#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12503
	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
6084 serge 12504
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
4560 Serge 12505
			  "(expected %i, found %i)\n", \
12506
			  current_config->name, \
12507
			  pipe_config->name); \
6084 serge 12508
		ret = false; \
4560 Serge 12509
	}
12510
 
4104 Serge 12511
#define PIPE_CONF_QUIRK(quirk)	\
12512
	((current_config->quirks | pipe_config->quirks) & (quirk))
12513
 
12514
	PIPE_CONF_CHECK_I(cpu_transcoder);
12515
 
12516
	PIPE_CONF_CHECK_I(has_pch_encoder);
12517
	PIPE_CONF_CHECK_I(fdi_lanes);
6084 serge 12518
	PIPE_CONF_CHECK_M_N(fdi_m_n);
4104 Serge 12519
 
4560 Serge 12520
	PIPE_CONF_CHECK_I(has_dp_encoder);
6084 serge 12521
	PIPE_CONF_CHECK_I(lane_count);
5354 serge 12522
 
12523
	if (INTEL_INFO(dev)->gen < 8) {
6084 serge 12524
		PIPE_CONF_CHECK_M_N(dp_m_n);
4560 Serge 12525
 
6084 serge 12526
		if (current_config->has_drrs)
12527
			PIPE_CONF_CHECK_M_N(dp_m2_n2);
12528
	} else
12529
		PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
5354 serge 12530
 
6084 serge 12531
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12532
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12533
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12534
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12535
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12536
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
4104 Serge 12537
 
6084 serge 12538
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12539
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12540
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12541
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12542
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12543
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
4104 Serge 12544
 
6084 serge 12545
	PIPE_CONF_CHECK_I(pixel_multiplier);
5060 serge 12546
	PIPE_CONF_CHECK_I(has_hdmi_sink);
12547
	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12548
	    IS_VALLEYVIEW(dev))
12549
		PIPE_CONF_CHECK_I(limited_color_range);
5354 serge 12550
	PIPE_CONF_CHECK_I(has_infoframe);
4104 Serge 12551
 
5060 serge 12552
	PIPE_CONF_CHECK_I(has_audio);
12553
 
6084 serge 12554
	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104 Serge 12555
			      DRM_MODE_FLAG_INTERLACE);
12556
 
12557
	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
6084 serge 12558
		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104 Serge 12559
				      DRM_MODE_FLAG_PHSYNC);
6084 serge 12560
		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104 Serge 12561
				      DRM_MODE_FLAG_NHSYNC);
6084 serge 12562
		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104 Serge 12563
				      DRM_MODE_FLAG_PVSYNC);
6084 serge 12564
		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
4104 Serge 12565
				      DRM_MODE_FLAG_NVSYNC);
12566
	}
12567
 
6084 serge 12568
	PIPE_CONF_CHECK_X(gmch_pfit.control);
4104 Serge 12569
	/* pfit ratios are autocomputed by the hw on gen4+ */
12570
	if (INTEL_INFO(dev)->gen < 4)
12571
		PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
6084 serge 12572
	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5060 serge 12573
 
6084 serge 12574
	if (!adjust) {
12575
		PIPE_CONF_CHECK_I(pipe_src_w);
12576
		PIPE_CONF_CHECK_I(pipe_src_h);
12577
 
12578
		PIPE_CONF_CHECK_I(pch_pfit.enabled);
12579
		if (current_config->pch_pfit.enabled) {
12580
			PIPE_CONF_CHECK_X(pch_pfit.pos);
12581
			PIPE_CONF_CHECK_X(pch_pfit.size);
12582
		}
12583
 
12584
		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
4104 Serge 12585
	}
12586
 
4560 Serge 12587
	/* BDW+ don't expose a synchronous way to read the state */
12588
	if (IS_HASWELL(dev))
6084 serge 12589
		PIPE_CONF_CHECK_I(ips_enabled);
4104 Serge 12590
 
4560 Serge 12591
	PIPE_CONF_CHECK_I(double_wide);
12592
 
5060 serge 12593
	PIPE_CONF_CHECK_X(ddi_pll_sel);
12594
 
4104 Serge 12595
	PIPE_CONF_CHECK_I(shared_dpll);
12596
	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12597
	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12598
	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12599
	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5060 serge 12600
	PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
6084 serge 12601
	PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5354 serge 12602
	PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12603
	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12604
	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
4104 Serge 12605
 
4280 Serge 12606
	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12607
		PIPE_CONF_CHECK_I(pipe_bpp);
12608
 
6084 serge 12609
	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12610
	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
4560 Serge 12611
 
4104 Serge 12612
#undef PIPE_CONF_CHECK_X
12613
#undef PIPE_CONF_CHECK_I
5354 serge 12614
#undef PIPE_CONF_CHECK_I_ALT
4104 Serge 12615
#undef PIPE_CONF_CHECK_FLAGS
4560 Serge 12616
#undef PIPE_CONF_CHECK_CLOCK_FUZZY
4104 Serge 12617
#undef PIPE_CONF_QUIRK
6084 serge 12618
#undef INTEL_ERR_OR_DBG_KMS
4104 Serge 12619
 
6084 serge 12620
	return ret;
3746 Serge 12621
}
12622
 
5354 serge 12623
static void check_wm_state(struct drm_device *dev)
12624
{
12625
	struct drm_i915_private *dev_priv = dev->dev_private;
12626
	struct skl_ddb_allocation hw_ddb, *sw_ddb;
12627
	struct intel_crtc *intel_crtc;
12628
	int plane;
12629
 
12630
	if (INTEL_INFO(dev)->gen < 9)
12631
		return;
12632
 
12633
	skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12634
	sw_ddb = &dev_priv->wm.skl_hw.ddb;
12635
 
12636
	for_each_intel_crtc(dev, intel_crtc) {
12637
		struct skl_ddb_entry *hw_entry, *sw_entry;
12638
		const enum pipe pipe = intel_crtc->pipe;
12639
 
12640
		if (!intel_crtc->active)
12641
			continue;
12642
 
12643
		/* planes */
6084 serge 12644
		for_each_plane(dev_priv, pipe, plane) {
5354 serge 12645
			hw_entry = &hw_ddb.plane[pipe][plane];
12646
			sw_entry = &sw_ddb->plane[pipe][plane];
12647
 
12648
			if (skl_ddb_entry_equal(hw_entry, sw_entry))
12649
				continue;
12650
 
12651
			DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12652
				  "(expected (%u,%u), found (%u,%u))\n",
12653
				  pipe_name(pipe), plane + 1,
12654
				  sw_entry->start, sw_entry->end,
12655
				  hw_entry->start, hw_entry->end);
12656
		}
12657
 
12658
		/* cursor */
6084 serge 12659
		hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12660
		sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
5354 serge 12661
 
12662
		if (skl_ddb_entry_equal(hw_entry, sw_entry))
12663
			continue;
12664
 
12665
		DRM_ERROR("mismatch in DDB state pipe %c cursor "
12666
			  "(expected (%u,%u), found (%u,%u))\n",
12667
			  pipe_name(pipe),
12668
			  sw_entry->start, sw_entry->end,
12669
			  hw_entry->start, hw_entry->end);
12670
	}
12671
}
12672
 
4104 Serge 12673
static void
6084 serge 12674
check_connector_state(struct drm_device *dev,
12675
		      struct drm_atomic_state *old_state)
3031 serge 12676
{
6084 serge 12677
	struct drm_connector_state *old_conn_state;
12678
	struct drm_connector *connector;
12679
	int i;
3031 serge 12680
 
6084 serge 12681
	for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12682
		struct drm_encoder *encoder = connector->encoder;
12683
		struct drm_connector_state *state = connector->state;
12684
 
3031 serge 12685
		/* This also checks the encoder/connector hw state with the
12686
		 * ->get_hw_state callbacks. */
6084 serge 12687
		intel_connector_check_state(to_intel_connector(connector));
3031 serge 12688
 
6084 serge 12689
		I915_STATE_WARN(state->best_encoder != encoder,
12690
		     "connector's atomic encoder doesn't match legacy encoder\n");
3031 serge 12691
	}
4104 Serge 12692
}
3031 serge 12693
 
4104 Serge 12694
static void
12695
check_encoder_state(struct drm_device *dev)
12696
{
12697
	struct intel_encoder *encoder;
12698
	struct intel_connector *connector;
12699
 
5354 serge 12700
	for_each_intel_encoder(dev, encoder) {
3031 serge 12701
		bool enabled = false;
6084 serge 12702
		enum pipe pipe;
3031 serge 12703
 
12704
		DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12705
			      encoder->base.base.id,
5060 serge 12706
			      encoder->base.name);
3031 serge 12707
 
6084 serge 12708
		for_each_intel_connector(dev, connector) {
12709
			if (connector->base.state->best_encoder != &encoder->base)
3031 serge 12710
				continue;
12711
			enabled = true;
6084 serge 12712
 
12713
			I915_STATE_WARN(connector->base.state->crtc !=
12714
					encoder->base.crtc,
12715
			     "connector's crtc doesn't match encoder crtc\n");
3031 serge 12716
		}
5060 serge 12717
 
6084 serge 12718
		I915_STATE_WARN(!!encoder->base.crtc != enabled,
3031 serge 12719
		     "encoder's enabled state mismatch "
12720
		     "(expected %i, found %i)\n",
12721
		     !!encoder->base.crtc, enabled);
12722
 
6084 serge 12723
		if (!encoder->base.crtc) {
12724
			bool active;
3031 serge 12725
 
6084 serge 12726
			active = encoder->get_hw_state(encoder, &pipe);
12727
			I915_STATE_WARN(active,
12728
			     "encoder detached but still enabled on pipe %c.\n",
12729
			     pipe_name(pipe));
12730
		}
3031 serge 12731
	}
4104 Serge 12732
}
3031 serge 12733
 
4104 Serge 12734
static void
6084 serge 12735
check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
4104 Serge 12736
{
5060 serge 12737
	struct drm_i915_private *dev_priv = dev->dev_private;
4104 Serge 12738
	struct intel_encoder *encoder;
6084 serge 12739
	struct drm_crtc_state *old_crtc_state;
12740
	struct drm_crtc *crtc;
12741
	int i;
4104 Serge 12742
 
6084 serge 12743
	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12744
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12745
		struct intel_crtc_state *pipe_config, *sw_config;
12746
		bool active;
3031 serge 12747
 
6084 serge 12748
		if (!needs_modeset(crtc->state) &&
12749
		    !to_intel_crtc_state(crtc->state)->update_pipe)
12750
			continue;
4104 Serge 12751
 
6084 serge 12752
		__drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12753
		pipe_config = to_intel_crtc_state(old_crtc_state);
12754
		memset(pipe_config, 0, sizeof(*pipe_config));
12755
		pipe_config->base.crtc = crtc;
12756
		pipe_config->base.state = old_state;
12757
 
3031 serge 12758
		DRM_DEBUG_KMS("[CRTC:%d]\n",
6084 serge 12759
			      crtc->base.id);
3031 serge 12760
 
6084 serge 12761
		active = dev_priv->display.get_pipe_config(intel_crtc,
12762
							   pipe_config);
3031 serge 12763
 
6084 serge 12764
		/* hw state is inconsistent with the pipe quirk */
12765
		if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12766
		    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12767
			active = crtc->state->active;
4104 Serge 12768
 
6084 serge 12769
		I915_STATE_WARN(crtc->state->active != active,
12770
		     "crtc active state doesn't match with hw state "
12771
		     "(expected %i, found %i)\n", crtc->state->active, active);
3031 serge 12772
 
6084 serge 12773
		I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12774
		     "transitional active state does not match atomic hw state "
12775
		     "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
3746 Serge 12776
 
6084 serge 12777
		for_each_encoder_on_crtc(dev, crtc, encoder) {
12778
			enum pipe pipe;
3746 Serge 12779
 
6084 serge 12780
			active = encoder->get_hw_state(encoder, &pipe);
12781
			I915_STATE_WARN(active != crtc->state->active,
12782
				"[ENCODER:%i] active %i with crtc active %i\n",
12783
				encoder->base.base.id, active, crtc->state->active);
12784
 
12785
			I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12786
					"Encoder connected to wrong pipe %c\n",
12787
					pipe_name(pipe));
12788
 
12789
			if (active)
12790
				encoder->get_config(encoder, pipe_config);
4104 Serge 12791
		}
12792
 
6084 serge 12793
		if (!crtc->state->active)
12794
			continue;
3746 Serge 12795
 
6084 serge 12796
		sw_config = to_intel_crtc_state(crtc->state);
12797
		if (!intel_pipe_config_compare(dev, sw_config,
12798
					       pipe_config, false)) {
12799
			I915_STATE_WARN(1, "pipe state doesn't match!\n");
12800
			intel_dump_pipe_config(intel_crtc, pipe_config,
4104 Serge 12801
					       "[hw state]");
6084 serge 12802
			intel_dump_pipe_config(intel_crtc, sw_config,
4104 Serge 12803
					       "[sw state]");
12804
		}
3031 serge 12805
	}
12806
}
12807
 
4104 Serge 12808
static void
12809
check_shared_dpll_state(struct drm_device *dev)
12810
{
5060 serge 12811
	struct drm_i915_private *dev_priv = dev->dev_private;
4104 Serge 12812
	struct intel_crtc *crtc;
12813
	struct intel_dpll_hw_state dpll_hw_state;
12814
	int i;
12815
 
12816
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12817
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12818
		int enabled_crtcs = 0, active_crtcs = 0;
12819
		bool active;
12820
 
12821
		memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12822
 
12823
		DRM_DEBUG_KMS("%s\n", pll->name);
12824
 
12825
		active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12826
 
6084 serge 12827
		I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
4104 Serge 12828
		     "more active pll users than references: %i vs %i\n",
5354 serge 12829
		     pll->active, hweight32(pll->config.crtc_mask));
6084 serge 12830
		I915_STATE_WARN(pll->active && !pll->on,
4104 Serge 12831
		     "pll in active use but not on in sw tracking\n");
6084 serge 12832
		I915_STATE_WARN(pll->on && !pll->active,
4104 Serge 12833
		     "pll in on but not on in use in sw tracking\n");
6084 serge 12834
		I915_STATE_WARN(pll->on != active,
4104 Serge 12835
		     "pll on state mismatch (expected %i, found %i)\n",
12836
		     pll->on, active);
12837
 
5060 serge 12838
		for_each_intel_crtc(dev, crtc) {
6084 serge 12839
			if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
4104 Serge 12840
				enabled_crtcs++;
12841
			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12842
				active_crtcs++;
12843
		}
6084 serge 12844
		I915_STATE_WARN(pll->active != active_crtcs,
4104 Serge 12845
		     "pll active crtcs mismatch (expected %i, found %i)\n",
12846
		     pll->active, active_crtcs);
6084 serge 12847
		I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
4104 Serge 12848
		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
5354 serge 12849
		     hweight32(pll->config.crtc_mask), enabled_crtcs);
4104 Serge 12850
 
6084 serge 12851
		I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
4104 Serge 12852
				       sizeof(dpll_hw_state)),
12853
		     "pll hw state mismatch\n");
12854
	}
12855
}
12856
 
6084 serge 12857
static void
12858
intel_modeset_check_state(struct drm_device *dev,
12859
			  struct drm_atomic_state *old_state)
4104 Serge 12860
{
5354 serge 12861
	check_wm_state(dev);
6084 serge 12862
	check_connector_state(dev, old_state);
4104 Serge 12863
	check_encoder_state(dev);
6084 serge 12864
	check_crtc_state(dev, old_state);
4104 Serge 12865
	check_shared_dpll_state(dev);
12866
}
12867
 
6084 serge 12868
void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
4560 Serge 12869
				     int dotclock)
12870
{
12871
	/*
12872
	 * FDI already provided one idea for the dotclock.
12873
	 * Yell if the encoder disagrees.
12874
	 */
6084 serge 12875
	WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
4560 Serge 12876
	     "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
6084 serge 12877
	     pipe_config->base.adjusted_mode.crtc_clock, dotclock);
4560 Serge 12878
}
12879
 
5060 serge 12880
static void update_scanline_offset(struct intel_crtc *crtc)
12881
{
12882
	struct drm_device *dev = crtc->base.dev;
12883
 
12884
	/*
12885
	 * The scanline counter increments at the leading edge of hsync.
12886
	 *
12887
	 * On most platforms it starts counting from vtotal-1 on the
12888
	 * first active line. That means the scanline counter value is
12889
	 * always one less than what we would expect. Ie. just after
12890
	 * start of vblank, which also occurs at start of hsync (on the
12891
	 * last active line), the scanline counter will read vblank_start-1.
12892
	 *
12893
	 * On gen2 the scanline counter starts counting from 1 instead
12894
	 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12895
	 * to keep the value positive), instead of adding one.
12896
	 *
12897
	 * On HSW+ the behaviour of the scanline counter depends on the output
12898
	 * type. For DP ports it behaves like most other platforms, but on HDMI
12899
	 * there's an extra 1 line difference. So we need to add two instead of
12900
	 * one to the value.
12901
	 */
12902
	if (IS_GEN2(dev)) {
6084 serge 12903
		const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
5060 serge 12904
		int vtotal;
12905
 
6084 serge 12906
		vtotal = adjusted_mode->crtc_vtotal;
12907
		if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5060 serge 12908
			vtotal /= 2;
12909
 
12910
		crtc->scanline_offset = vtotal - 1;
12911
	} else if (HAS_DDI(dev) &&
5354 serge 12912
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
5060 serge 12913
		crtc->scanline_offset = 2;
12914
	} else
12915
		crtc->scanline_offset = 1;
12916
}
12917
 
6084 serge 12918
static void intel_modeset_clear_plls(struct drm_atomic_state *state)
5354 serge 12919
{
6084 serge 12920
	struct drm_device *dev = state->dev;
12921
	struct drm_i915_private *dev_priv = to_i915(dev);
12922
	struct intel_shared_dpll_config *shared_dpll = NULL;
12923
	struct intel_crtc *intel_crtc;
12924
	struct intel_crtc_state *intel_crtc_state;
12925
	struct drm_crtc *crtc;
12926
	struct drm_crtc_state *crtc_state;
12927
	int i;
5354 serge 12928
 
6084 serge 12929
	if (!dev_priv->display.crtc_compute_clock)
12930
		return;
5354 serge 12931
 
6084 serge 12932
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
12933
		int dpll;
5354 serge 12934
 
6084 serge 12935
		intel_crtc = to_intel_crtc(crtc);
12936
		intel_crtc_state = to_intel_crtc_state(crtc_state);
12937
		dpll = intel_crtc_state->shared_dpll;
12938
 
12939
		if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12940
			continue;
12941
 
12942
		intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12943
 
12944
		if (!shared_dpll)
12945
			shared_dpll = intel_atomic_get_shared_dpll_state(state);
12946
 
12947
		shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
5354 serge 12948
	}
12949
}
12950
 
6084 serge 12951
/*
12952
 * This implements the workaround described in the "notes" section of the mode
12953
 * set sequence documentation. When going from no pipes or single pipe to
12954
 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12955
 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12956
 */
12957
static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
3031 serge 12958
{
6084 serge 12959
	struct drm_crtc_state *crtc_state;
3031 serge 12960
	struct intel_crtc *intel_crtc;
6084 serge 12961
	struct drm_crtc *crtc;
12962
	struct intel_crtc_state *first_crtc_state = NULL;
12963
	struct intel_crtc_state *other_crtc_state = NULL;
12964
	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12965
	int i;
3031 serge 12966
 
6084 serge 12967
	/* look at all crtc's that are going to be enabled in during modeset */
12968
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
12969
		intel_crtc = to_intel_crtc(crtc);
3480 Serge 12970
 
6084 serge 12971
		if (!crtc_state->active || !needs_modeset(crtc_state))
12972
			continue;
3031 serge 12973
 
6084 serge 12974
		if (first_crtc_state) {
12975
			other_crtc_state = to_intel_crtc_state(crtc_state);
12976
			break;
12977
		} else {
12978
			first_crtc_state = to_intel_crtc_state(crtc_state);
12979
			first_pipe = intel_crtc->pipe;
12980
		}
12981
	}
3031 serge 12982
 
6084 serge 12983
	/* No workaround needed? */
12984
	if (!first_crtc_state)
12985
		return 0;
4560 Serge 12986
 
6084 serge 12987
	/* w/a possibly needed, check how many crtc's are already enabled. */
12988
	for_each_intel_crtc(state->dev, intel_crtc) {
12989
		struct intel_crtc_state *pipe_config;
4560 Serge 12990
 
6084 serge 12991
		pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12992
		if (IS_ERR(pipe_config))
12993
			return PTR_ERR(pipe_config);
5354 serge 12994
 
6084 serge 12995
		pipe_config->hsw_workaround_pipe = INVALID_PIPE;
5354 serge 12996
 
6084 serge 12997
		if (!pipe_config->base.active ||
12998
		    needs_modeset(&pipe_config->base))
12999
			continue;
5354 serge 13000
 
6084 serge 13001
		/* 2 or more enabled crtcs means no need for w/a */
13002
		if (enabled_pipe != INVALID_PIPE)
13003
			return 0;
3746 Serge 13004
 
6084 serge 13005
		enabled_pipe = intel_crtc->pipe;
3031 serge 13006
	}
13007
 
6084 serge 13008
	if (enabled_pipe != INVALID_PIPE)
13009
		first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13010
	else if (other_crtc_state)
13011
		other_crtc_state->hsw_workaround_pipe = first_pipe;
4560 Serge 13012
 
6084 serge 13013
	return 0;
13014
}
2327 Serge 13015
 
6084 serge 13016
static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13017
{
13018
	struct drm_crtc *crtc;
13019
	struct drm_crtc_state *crtc_state;
13020
	int ret = 0;
3031 serge 13021
 
6084 serge 13022
	/* add all active pipes to the state */
13023
	for_each_crtc(state->dev, crtc) {
13024
		crtc_state = drm_atomic_get_crtc_state(state, crtc);
13025
		if (IS_ERR(crtc_state))
13026
			return PTR_ERR(crtc_state);
3243 Serge 13027
 
6084 serge 13028
		if (!crtc_state->active || needs_modeset(crtc_state))
13029
			continue;
5060 serge 13030
 
6084 serge 13031
		crtc_state->mode_changed = true;
5060 serge 13032
 
6084 serge 13033
		ret = drm_atomic_add_affected_connectors(state, crtc);
13034
		if (ret)
13035
			break;
3031 serge 13036
 
6084 serge 13037
		ret = drm_atomic_add_affected_planes(state, crtc);
13038
		if (ret)
13039
			break;
5060 serge 13040
	}
3031 serge 13041
 
13042
	return ret;
2330 Serge 13043
}
2327 Serge 13044
 
6084 serge 13045
static int intel_modeset_checks(struct drm_atomic_state *state)
3746 Serge 13046
{
6084 serge 13047
	struct drm_device *dev = state->dev;
13048
	struct drm_i915_private *dev_priv = dev->dev_private;
3746 Serge 13049
	int ret;
13050
 
6084 serge 13051
	if (!check_digital_port_conflicts(state)) {
13052
		DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13053
		return -EINVAL;
13054
	}
3746 Serge 13055
 
6084 serge 13056
	/*
13057
	 * See if the config requires any additional preparation, e.g.
13058
	 * to adjust global state with pipes off.  We need to do this
13059
	 * here so we can get the modeset_pipe updated config for the new
13060
	 * mode set on this crtc.  For other crtcs we need to use the
13061
	 * adjusted_mode bits in the crtc directly.
13062
	 */
13063
	if (dev_priv->display.modeset_calc_cdclk) {
13064
		unsigned int cdclk;
3746 Serge 13065
 
6084 serge 13066
		ret = dev_priv->display.modeset_calc_cdclk(state);
3746 Serge 13067
 
6084 serge 13068
		cdclk = to_intel_atomic_state(state)->cdclk;
13069
		if (!ret && cdclk != dev_priv->cdclk_freq)
13070
			ret = intel_modeset_all_pipes(state);
5354 serge 13071
 
6084 serge 13072
		if (ret < 0)
13073
			return ret;
13074
	} else
13075
		to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
5354 serge 13076
 
6084 serge 13077
	intel_modeset_clear_plls(state);
5354 serge 13078
 
6084 serge 13079
	if (IS_HASWELL(dev))
13080
		return haswell_mode_set_planes_workaround(state);
5354 serge 13081
 
6084 serge 13082
	return 0;
3480 Serge 13083
}
13084
 
6084 serge 13085
/**
13086
 * intel_atomic_check - validate state object
13087
 * @dev: drm device
13088
 * @state: state to validate
13089
 */
13090
static int intel_atomic_check(struct drm_device *dev,
13091
			      struct drm_atomic_state *state)
3031 serge 13092
{
6084 serge 13093
	struct drm_crtc *crtc;
13094
	struct drm_crtc_state *crtc_state;
13095
	int ret, i;
13096
	bool any_ms = false;
3031 serge 13097
 
6084 serge 13098
	ret = drm_atomic_helper_check_modeset(dev, state);
13099
	if (ret)
13100
		return ret;
3031 serge 13101
 
6084 serge 13102
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
13103
		struct intel_crtc_state *pipe_config =
13104
			to_intel_crtc_state(crtc_state);
3031 serge 13105
 
6084 serge 13106
		memset(&to_intel_crtc(crtc)->atomic, 0,
13107
		       sizeof(struct intel_crtc_atomic_commit));
5060 serge 13108
 
6084 serge 13109
		/* Catch I915_MODE_FLAG_INHERITED */
13110
		if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13111
			crtc_state->mode_changed = true;
3031 serge 13112
 
6084 serge 13113
		if (!crtc_state->enable) {
13114
			if (needs_modeset(crtc_state))
13115
				any_ms = true;
13116
			continue;
13117
		}
3031 serge 13118
 
6084 serge 13119
		if (!needs_modeset(crtc_state))
13120
			continue;
5060 serge 13121
 
6084 serge 13122
		/* FIXME: For only active_changed we shouldn't need to do any
13123
		 * state recomputation at all. */
3031 serge 13124
 
6084 serge 13125
		ret = drm_atomic_add_affected_connectors(state, crtc);
13126
		if (ret)
13127
			return ret;
3031 serge 13128
 
6084 serge 13129
		ret = intel_modeset_pipe_config(crtc, pipe_config);
13130
		if (ret)
13131
			return ret;
3031 serge 13132
 
6084 serge 13133
		if (i915.fastboot &&
13134
		    intel_pipe_config_compare(state->dev,
13135
					to_intel_crtc_state(crtc->state),
13136
					pipe_config, true)) {
13137
			crtc_state->mode_changed = false;
13138
			to_intel_crtc_state(crtc_state)->update_pipe = true;
13139
		}
3031 serge 13140
 
6084 serge 13141
		if (needs_modeset(crtc_state)) {
13142
			any_ms = true;
5060 serge 13143
 
6084 serge 13144
			ret = drm_atomic_add_affected_planes(state, crtc);
13145
			if (ret)
13146
				return ret;
13147
		}
5060 serge 13148
 
6084 serge 13149
		intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13150
				       needs_modeset(crtc_state) ?
13151
				       "[modeset]" : "[fastset]");
3031 serge 13152
	}
13153
 
6084 serge 13154
	if (any_ms) {
13155
		ret = intel_modeset_checks(state);
3031 serge 13156
 
6084 serge 13157
		if (ret)
13158
			return ret;
13159
	} else
13160
		to_intel_atomic_state(state)->cdclk =
13161
			to_i915(state->dev)->cdclk_freq;
3746 Serge 13162
 
6084 serge 13163
	return drm_atomic_helper_check_planes(state->dev, state);
3746 Serge 13164
}
13165
 
6084 serge 13166
/**
13167
 * intel_atomic_commit - commit validated state object
13168
 * @dev: DRM device
13169
 * @state: the top-level driver state object
13170
 * @async: asynchronous commit
13171
 *
13172
 * This function commits a top-level state object that has been validated
13173
 * with drm_atomic_helper_check().
13174
 *
13175
 * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13176
 * we can only handle plane-related operations and do not yet support
13177
 * asynchronous commit.
13178
 *
13179
 * RETURNS
13180
 * Zero for success or -errno.
13181
 */
13182
static int intel_atomic_commit(struct drm_device *dev,
13183
			       struct drm_atomic_state *state,
13184
			       bool async)
3031 serge 13185
{
6084 serge 13186
	struct drm_i915_private *dev_priv = dev->dev_private;
13187
	struct drm_crtc *crtc;
13188
	struct drm_crtc_state *crtc_state;
13189
	int ret = 0;
13190
	int i;
13191
	bool any_ms = false;
3031 serge 13192
 
6084 serge 13193
	if (async) {
13194
		DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13195
		return -EINVAL;
3031 serge 13196
	}
13197
 
6084 serge 13198
	ret = drm_atomic_helper_prepare_planes(dev, state);
13199
	if (ret)
13200
		return ret;
3031 serge 13201
 
6084 serge 13202
	drm_atomic_helper_swap_state(dev, state);
4104 Serge 13203
 
6084 serge 13204
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
13205
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 serge 13206
 
6084 serge 13207
		if (!needs_modeset(crtc->state))
13208
			continue;
3031 serge 13209
 
6084 serge 13210
		any_ms = true;
13211
		intel_pre_plane_update(intel_crtc);
3031 serge 13212
 
6084 serge 13213
		if (crtc_state->active) {
13214
			intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13215
			dev_priv->display.crtc_disable(crtc);
13216
			intel_crtc->active = false;
13217
			intel_disable_shared_dpll(intel_crtc);
3031 serge 13218
		}
6084 serge 13219
	}
3031 serge 13220
 
6084 serge 13221
	/* Only after disabling all output pipelines that will be changed can we
13222
	 * update the the output configuration. */
13223
	intel_modeset_update_crtc_state(state);
3031 serge 13224
 
6084 serge 13225
	if (any_ms) {
13226
		intel_shared_dpll_commit(state);
3031 serge 13227
 
6084 serge 13228
		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13229
		modeset_update_crtc_power_domains(state);
3031 serge 13230
	}
13231
 
6084 serge 13232
	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
13233
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
13234
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13235
		bool modeset = needs_modeset(crtc->state);
13236
		bool update_pipe = !modeset &&
13237
			to_intel_crtc_state(crtc->state)->update_pipe;
13238
		unsigned long put_domains = 0;
5060 serge 13239
 
6084 serge 13240
		if (modeset && crtc->state->active) {
13241
			update_scanline_offset(to_intel_crtc(crtc));
13242
			dev_priv->display.crtc_enable(crtc);
3031 serge 13243
		}
13244
 
6084 serge 13245
		if (update_pipe) {
13246
			put_domains = modeset_get_crtc_power_domains(crtc);
3031 serge 13247
 
6084 serge 13248
			/* make sure intel_modeset_check_state runs */
13249
			any_ms = true;
3031 serge 13250
		}
4560 Serge 13251
 
6084 serge 13252
		if (!modeset)
13253
			intel_pre_plane_update(intel_crtc);
4560 Serge 13254
 
6084 serge 13255
		drm_atomic_helper_commit_planes_on_crtc(crtc_state);
3031 serge 13256
 
6084 serge 13257
		if (put_domains)
13258
			modeset_put_power_domains(dev_priv, put_domains);
5060 serge 13259
 
6084 serge 13260
		intel_post_plane_update(intel_crtc);
5060 serge 13261
	}
13262
 
6084 serge 13263
	/* FIXME: add subpixel order */
3031 serge 13264
 
6088 serge 13265
	drm_atomic_helper_wait_for_vblanks(dev, state);
6084 serge 13266
	drm_atomic_helper_cleanup_planes(dev, state);
5060 serge 13267
 
6084 serge 13268
	if (any_ms)
13269
		intel_modeset_check_state(dev, state);
5060 serge 13270
 
6084 serge 13271
	drm_atomic_state_free(state);
5060 serge 13272
 
6084 serge 13273
	return 0;
5060 serge 13274
}
13275
 
6084 serge 13276
void intel_crtc_restore_mode(struct drm_crtc *crtc)
3031 serge 13277
{
6084 serge 13278
	struct drm_device *dev = crtc->dev;
13279
	struct drm_atomic_state *state;
13280
	struct drm_crtc_state *crtc_state;
3031 serge 13281
	int ret;
13282
 
6084 serge 13283
	state = drm_atomic_state_alloc(dev);
13284
	if (!state) {
13285
		DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13286
			      crtc->base.id);
13287
		return;
3031 serge 13288
	}
13289
 
6084 serge 13290
	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
3031 serge 13291
 
6084 serge 13292
retry:
13293
	crtc_state = drm_atomic_get_crtc_state(state, crtc);
13294
	ret = PTR_ERR_OR_ZERO(crtc_state);
13295
	if (!ret) {
13296
		if (!crtc_state->active)
13297
			goto out;
3031 serge 13298
 
6084 serge 13299
		crtc_state->mode_changed = true;
13300
		ret = drm_atomic_commit(state);
5354 serge 13301
	}
13302
 
6084 serge 13303
	if (ret == -EDEADLK) {
13304
		drm_atomic_state_clear(state);
13305
		drm_modeset_backoff(state->acquire_ctx);
13306
		goto retry;
3031 serge 13307
	}
13308
 
6084 serge 13309
	if (ret)
13310
out:
13311
		drm_atomic_state_free(state);
13312
}
3031 serge 13313
 
6084 serge 13314
#undef for_each_intel_crtc_masked
5060 serge 13315
 
2330 Serge 13316
static const struct drm_crtc_funcs intel_crtc_funcs = {
13317
	.gamma_set = intel_crtc_gamma_set,
6084 serge 13318
	.set_config = drm_atomic_helper_set_config,
2330 Serge 13319
	.destroy = intel_crtc_destroy,
13320
//	.page_flip = intel_crtc_page_flip,
6084 serge 13321
	.atomic_duplicate_state = intel_crtc_duplicate_state,
13322
	.atomic_destroy_state = intel_crtc_destroy_state,
2330 Serge 13323
};
2327 Serge 13324
 
4104 Serge 13325
static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13326
				      struct intel_shared_dpll *pll,
13327
				      struct intel_dpll_hw_state *hw_state)
3031 serge 13328
{
4104 Serge 13329
	uint32_t val;
3031 serge 13330
 
5354 serge 13331
	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
5060 serge 13332
		return false;
13333
 
4104 Serge 13334
	val = I915_READ(PCH_DPLL(pll->id));
13335
	hw_state->dpll = val;
13336
	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13337
	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13338
 
13339
	return val & DPLL_VCO_ENABLE;
13340
}
13341
 
13342
static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13343
				  struct intel_shared_dpll *pll)
13344
{
5354 serge 13345
	I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13346
	I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
4104 Serge 13347
}
13348
 
13349
static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13350
				struct intel_shared_dpll *pll)
13351
{
13352
	/* PCH refclock must be enabled first */
4560 Serge 13353
	ibx_assert_pch_refclk_enabled(dev_priv);
4104 Serge 13354
 
5354 serge 13355
	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
4104 Serge 13356
 
13357
	/* Wait for the clocks to stabilize. */
13358
	POSTING_READ(PCH_DPLL(pll->id));
13359
	udelay(150);
13360
 
13361
	/* The pixel multiplier can only be updated once the
13362
	 * DPLL is enabled and the clocks are stable.
13363
	 *
13364
	 * So write it again.
13365
	 */
5354 serge 13366
	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
4104 Serge 13367
	POSTING_READ(PCH_DPLL(pll->id));
13368
	udelay(200);
13369
}
13370
 
13371
static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13372
				 struct intel_shared_dpll *pll)
13373
{
13374
	struct drm_device *dev = dev_priv->dev;
13375
	struct intel_crtc *crtc;
13376
 
13377
	/* Make sure no transcoder isn't still depending on us. */
5060 serge 13378
	for_each_intel_crtc(dev, crtc) {
4104 Serge 13379
		if (intel_crtc_to_shared_dpll(crtc) == pll)
13380
			assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
3031 serge 13381
	}
13382
 
4104 Serge 13383
	I915_WRITE(PCH_DPLL(pll->id), 0);
13384
	POSTING_READ(PCH_DPLL(pll->id));
13385
	udelay(200);
13386
}
13387
 
13388
static char *ibx_pch_dpll_names[] = {
13389
	"PCH DPLL A",
13390
	"PCH DPLL B",
13391
};
13392
 
13393
static void ibx_pch_dpll_init(struct drm_device *dev)
13394
{
13395
	struct drm_i915_private *dev_priv = dev->dev_private;
13396
	int i;
13397
 
13398
	dev_priv->num_shared_dpll = 2;
13399
 
13400
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13401
		dev_priv->shared_dplls[i].id = i;
13402
		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13403
		dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13404
		dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13405
		dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13406
		dev_priv->shared_dplls[i].get_hw_state =
13407
			ibx_pch_dpll_get_hw_state;
3031 serge 13408
	}
13409
}
13410
 
4104 Serge 13411
static void intel_shared_dpll_init(struct drm_device *dev)
13412
{
13413
	struct drm_i915_private *dev_priv = dev->dev_private;
13414
 
5060 serge 13415
	if (HAS_DDI(dev))
13416
		intel_ddi_pll_init(dev);
13417
	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4104 Serge 13418
		ibx_pch_dpll_init(dev);
13419
	else
13420
		dev_priv->num_shared_dpll = 0;
13421
 
13422
	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13423
}
13424
 
6084 serge 13425
/**
13426
 * intel_prepare_plane_fb - Prepare fb for usage on plane
13427
 * @plane: drm plane to prepare for
13428
 * @fb: framebuffer to prepare for presentation
13429
 *
13430
 * Prepares a framebuffer for usage on a display plane.  Generally this
13431
 * involves pinning the underlying object and updating the frontbuffer tracking
13432
 * bits.  Some older platforms need special physical address handling for
13433
 * cursor planes.
13434
 *
13435
 * Returns 0 on success, negative error code on failure.
13436
 */
13437
int
13438
intel_prepare_plane_fb(struct drm_plane *plane,
13439
		       const struct drm_plane_state *new_state)
5060 serge 13440
{
13441
	struct drm_device *dev = plane->dev;
6084 serge 13442
	struct drm_framebuffer *fb = new_state->fb;
13443
	struct intel_plane *intel_plane = to_intel_plane(plane);
13444
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13445
	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13446
	int ret = 0;
5060 serge 13447
 
6084 serge 13448
	if (!obj)
5060 serge 13449
		return 0;
13450
 
6084 serge 13451
	mutex_lock(&dev->struct_mutex);
5060 serge 13452
 
6084 serge 13453
	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13454
	    INTEL_INFO(dev)->cursor_needs_physical) {
13455
		int align = IS_I830(dev) ? 16 * 1024 : 256;
13456
        ret = 1;
13457
		if (ret)
13458
			DRM_DEBUG_KMS("failed to attach phys object\n");
13459
	} else {
13460
		ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13461
	}
5060 serge 13462
 
6084 serge 13463
	if (ret == 0)
13464
		i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
5060 serge 13465
 
13466
	mutex_unlock(&dev->struct_mutex);
13467
 
6084 serge 13468
	return ret;
5060 serge 13469
}
13470
 
6084 serge 13471
/**
13472
 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13473
 * @plane: drm plane to clean up for
13474
 * @fb: old framebuffer that was on plane
13475
 *
13476
 * Cleans up a framebuffer that has just been removed from a plane.
13477
 */
13478
void
13479
intel_cleanup_plane_fb(struct drm_plane *plane,
13480
		       const struct drm_plane_state *old_state)
5060 serge 13481
{
6084 serge 13482
	struct drm_device *dev = plane->dev;
13483
	struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
5354 serge 13484
 
6084 serge 13485
	if (!obj)
13486
		return;
13487
 
13488
	if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13489
	    !INTEL_INFO(dev)->cursor_needs_physical) {
13490
		mutex_lock(&dev->struct_mutex);
13491
		intel_unpin_fb_obj(old_state->fb, old_state);
13492
		mutex_unlock(&dev->struct_mutex);
13493
	}
5354 serge 13494
}
13495
 
6084 serge 13496
int
13497
skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
5354 serge 13498
{
6084 serge 13499
	int max_scale;
13500
	struct drm_device *dev;
13501
	struct drm_i915_private *dev_priv;
13502
	int crtc_clock, cdclk;
5060 serge 13503
 
6084 serge 13504
	if (!intel_crtc || !crtc_state)
13505
		return DRM_PLANE_HELPER_NO_SCALING;
5060 serge 13506
 
6084 serge 13507
	dev = intel_crtc->base.dev;
13508
	dev_priv = dev->dev_private;
13509
	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13510
	cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
5060 serge 13511
 
6084 serge 13512
	if (!crtc_clock || !cdclk)
13513
		return DRM_PLANE_HELPER_NO_SCALING;
13514
 
13515
	/*
13516
	 * skl max scale is lower of:
13517
	 *    close to 3 but not 3, -1 is for that purpose
13518
	 *            or
13519
	 *    cdclk/crtc_clock
13520
	 */
13521
	max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13522
 
13523
	return max_scale;
13524
}
13525
 
13526
static int
13527
intel_check_primary_plane(struct drm_plane *plane,
13528
			  struct intel_crtc_state *crtc_state,
13529
			  struct intel_plane_state *state)
13530
{
13531
	struct drm_crtc *crtc = state->base.crtc;
13532
	struct drm_framebuffer *fb = state->base.fb;
13533
	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13534
	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13535
	bool can_position = false;
13536
 
13537
	/* use scaler when colorkey is not required */
13538
	if (INTEL_INFO(plane->dev)->gen >= 9 &&
13539
	    state->ckey.flags == I915_SET_COLORKEY_NONE) {
13540
		min_scale = 1;
13541
		max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13542
		can_position = true;
5354 serge 13543
	}
5060 serge 13544
 
6084 serge 13545
	return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13546
					     &state->dst, &state->clip,
13547
					     min_scale, max_scale,
13548
					     can_position, true,
13549
					     &state->visible);
5354 serge 13550
}
13551
 
13552
static void
13553
intel_commit_primary_plane(struct drm_plane *plane,
13554
			   struct intel_plane_state *state)
13555
{
6084 serge 13556
	struct drm_crtc *crtc = state->base.crtc;
13557
	struct drm_framebuffer *fb = state->base.fb;
13558
	struct drm_device *dev = plane->dev;
5354 serge 13559
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 13560
	struct intel_crtc *intel_crtc;
5354 serge 13561
	struct drm_rect *src = &state->src;
13562
 
6084 serge 13563
	crtc = crtc ? crtc : plane->crtc;
13564
	intel_crtc = to_intel_crtc(crtc);
13565
 
13566
	plane->fb = fb;
5354 serge 13567
	crtc->x = src->x1 >> 16;
13568
	crtc->y = src->y1 >> 16;
13569
 
6084 serge 13570
	if (!crtc->state->active)
13571
		return;
5354 serge 13572
 
6084 serge 13573
	dev_priv->display.update_primary_plane(crtc, fb,
13574
					       state->src.x1 >> 16,
13575
					       state->src.y1 >> 16);
13576
}
5060 serge 13577
 
6084 serge 13578
static void
13579
intel_disable_primary_plane(struct drm_plane *plane,
13580
			    struct drm_crtc *crtc)
13581
{
13582
	struct drm_device *dev = plane->dev;
13583
	struct drm_i915_private *dev_priv = dev->dev_private;
5060 serge 13584
 
6084 serge 13585
	dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13586
}
5060 serge 13587
 
6084 serge 13588
static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13589
				    struct drm_crtc_state *old_crtc_state)
13590
{
13591
	struct drm_device *dev = crtc->dev;
13592
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13593
	struct intel_crtc_state *old_intel_state =
13594
		to_intel_crtc_state(old_crtc_state);
13595
	bool modeset = needs_modeset(crtc->state);
5060 serge 13596
 
6084 serge 13597
	if (intel_crtc->atomic.update_wm_pre)
13598
		intel_update_watermarks(crtc);
5060 serge 13599
 
6084 serge 13600
	/* Perform vblank evasion around commit operation */
13601
	if (crtc->state->active)
13602
		intel_pipe_update_start(intel_crtc);
5354 serge 13603
 
6084 serge 13604
	if (modeset)
13605
		return;
5354 serge 13606
 
6084 serge 13607
	if (to_intel_crtc_state(crtc->state)->update_pipe)
13608
		intel_update_pipe_config(intel_crtc, old_intel_state);
13609
	else if (INTEL_INFO(dev)->gen >= 9)
13610
		skl_detach_scalers(intel_crtc);
5354 serge 13611
}
5060 serge 13612
 
6084 serge 13613
static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13614
				     struct drm_crtc_state *old_crtc_state)
5354 serge 13615
{
13616
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060 serge 13617
 
6084 serge 13618
	if (crtc->state->active)
13619
		intel_pipe_update_end(intel_crtc);
5060 serge 13620
}
13621
 
6084 serge 13622
/**
13623
 * intel_plane_destroy - destroy a plane
13624
 * @plane: plane to destroy
13625
 *
13626
 * Common destruction function for all types of planes (primary, cursor,
13627
 * sprite).
13628
 */
13629
void intel_plane_destroy(struct drm_plane *plane)
5060 serge 13630
{
13631
	struct intel_plane *intel_plane = to_intel_plane(plane);
13632
	drm_plane_cleanup(plane);
13633
	kfree(intel_plane);
13634
}
13635
 
6084 serge 13636
const struct drm_plane_funcs intel_plane_funcs = {
13637
	.update_plane = drm_atomic_helper_update_plane,
13638
	.disable_plane = drm_atomic_helper_disable_plane,
5060 serge 13639
	.destroy = intel_plane_destroy,
6084 serge 13640
	.set_property = drm_atomic_helper_plane_set_property,
13641
	.atomic_get_property = intel_plane_atomic_get_property,
13642
	.atomic_set_property = intel_plane_atomic_set_property,
13643
	.atomic_duplicate_state = intel_plane_duplicate_state,
13644
	.atomic_destroy_state = intel_plane_destroy_state,
13645
 
5060 serge 13646
};
13647
 
13648
static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13649
						    int pipe)
13650
{
13651
	struct intel_plane *primary;
6084 serge 13652
	struct intel_plane_state *state;
5060 serge 13653
	const uint32_t *intel_primary_formats;
6084 serge 13654
	unsigned int num_formats;
5060 serge 13655
 
13656
	primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13657
	if (primary == NULL)
13658
		return NULL;
13659
 
6084 serge 13660
	state = intel_create_plane_state(&primary->base);
13661
	if (!state) {
13662
		kfree(primary);
13663
		return NULL;
13664
	}
13665
	primary->base.state = &state->base;
13666
 
5060 serge 13667
	primary->can_scale = false;
13668
	primary->max_downscale = 1;
6084 serge 13669
	if (INTEL_INFO(dev)->gen >= 9) {
13670
		primary->can_scale = true;
13671
		state->scaler_id = -1;
13672
	}
5060 serge 13673
	primary->pipe = pipe;
13674
	primary->plane = pipe;
6084 serge 13675
	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13676
	primary->check_plane = intel_check_primary_plane;
13677
	primary->commit_plane = intel_commit_primary_plane;
13678
	primary->disable_plane = intel_disable_primary_plane;
5060 serge 13679
	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13680
		primary->plane = !pipe;
13681
 
6084 serge 13682
	if (INTEL_INFO(dev)->gen >= 9) {
13683
		intel_primary_formats = skl_primary_formats;
13684
		num_formats = ARRAY_SIZE(skl_primary_formats);
13685
	} else if (INTEL_INFO(dev)->gen >= 4) {
13686
		intel_primary_formats = i965_primary_formats;
13687
		num_formats = ARRAY_SIZE(i965_primary_formats);
5060 serge 13688
	} else {
6084 serge 13689
		intel_primary_formats = i8xx_primary_formats;
13690
		num_formats = ARRAY_SIZE(i8xx_primary_formats);
5060 serge 13691
	}
13692
 
13693
	drm_universal_plane_init(dev, &primary->base, 0,
6084 serge 13694
				 &intel_plane_funcs,
5060 serge 13695
				 intel_primary_formats, num_formats,
13696
				 DRM_PLANE_TYPE_PRIMARY);
5354 serge 13697
 
6084 serge 13698
	if (INTEL_INFO(dev)->gen >= 4)
13699
		intel_create_rotation_property(dev, primary);
5354 serge 13700
 
6084 serge 13701
	drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13702
 
5060 serge 13703
	return &primary->base;
13704
}
13705
 
6084 serge 13706
void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
5060 serge 13707
{
6084 serge 13708
	if (!dev->mode_config.rotation_property) {
13709
		unsigned long flags = BIT(DRM_ROTATE_0) |
13710
			BIT(DRM_ROTATE_180);
5060 serge 13711
 
6084 serge 13712
		if (INTEL_INFO(dev)->gen >= 9)
13713
			flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
5060 serge 13714
 
6084 serge 13715
		dev->mode_config.rotation_property =
13716
			drm_mode_create_rotation_property(dev, flags);
13717
	}
13718
	if (dev->mode_config.rotation_property)
13719
		drm_object_attach_property(&plane->base.base,
13720
				dev->mode_config.rotation_property,
13721
				plane->base.state->rotation);
5060 serge 13722
}
13723
 
13724
static int
5354 serge 13725
intel_check_cursor_plane(struct drm_plane *plane,
6084 serge 13726
			 struct intel_crtc_state *crtc_state,
5354 serge 13727
			 struct intel_plane_state *state)
5060 serge 13728
{
6084 serge 13729
	struct drm_crtc *crtc = crtc_state->base.crtc;
13730
	struct drm_framebuffer *fb = state->base.fb;
5354 serge 13731
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6084 serge 13732
	enum pipe pipe = to_intel_plane(plane)->pipe;
5354 serge 13733
	unsigned stride;
5060 serge 13734
	int ret;
13735
 
6084 serge 13736
	ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13737
					    &state->dst, &state->clip,
5060 serge 13738
					    DRM_PLANE_HELPER_NO_SCALING,
13739
					    DRM_PLANE_HELPER_NO_SCALING,
5354 serge 13740
					    true, true, &state->visible);
5060 serge 13741
	if (ret)
13742
		return ret;
13743
 
5354 serge 13744
	/* if we want to turn off the cursor ignore width and height */
13745
	if (!obj)
13746
		return 0;
13747
 
13748
	/* Check for which cursor types we support */
6084 serge 13749
	if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13750
		DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13751
			  state->base.crtc_w, state->base.crtc_h);
5354 serge 13752
		return -EINVAL;
13753
	}
13754
 
6084 serge 13755
	stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13756
	if (obj->base.size < stride * state->base.crtc_h) {
5354 serge 13757
		DRM_DEBUG_KMS("buffer is too small\n");
13758
		return -ENOMEM;
13759
	}
13760
 
6084 serge 13761
	if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
5354 serge 13762
		DRM_DEBUG_KMS("cursor cannot be tiled\n");
6084 serge 13763
		return -EINVAL;
5354 serge 13764
	}
13765
 
6084 serge 13766
	/*
13767
	 * There's something wrong with the cursor on CHV pipe C.
13768
	 * If it straddles the left edge of the screen then
13769
	 * moving it away from the edge or disabling it often
13770
	 * results in a pipe underrun, and often that can lead to
13771
	 * dead pipe (constant underrun reported, and it scans
13772
	 * out just a solid color). To recover from that, the
13773
	 * display power well must be turned off and on again.
13774
	 * Refuse the put the cursor into that compromised position.
13775
	 */
13776
	if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
13777
	    state->visible && state->base.crtc_x < 0) {
13778
		DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13779
		return -EINVAL;
13780
	}
13781
 
13782
	return 0;
5354 serge 13783
}
13784
 
6084 serge 13785
static void
13786
intel_disable_cursor_plane(struct drm_plane *plane,
13787
			   struct drm_crtc *crtc)
5354 serge 13788
{
6084 serge 13789
	intel_crtc_update_cursor(crtc, false);
5060 serge 13790
}
5354 serge 13791
 
6084 serge 13792
static void
13793
intel_commit_cursor_plane(struct drm_plane *plane,
13794
			  struct intel_plane_state *state)
5354 serge 13795
{
6084 serge 13796
	struct drm_crtc *crtc = state->base.crtc;
13797
	struct drm_device *dev = plane->dev;
13798
	struct intel_crtc *intel_crtc;
13799
	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13800
	uint32_t addr;
5354 serge 13801
 
6084 serge 13802
	crtc = crtc ? crtc : plane->crtc;
13803
	intel_crtc = to_intel_crtc(crtc);
5354 serge 13804
 
6084 serge 13805
	if (!obj)
13806
		addr = 0;
13807
	else if (!INTEL_INFO(dev)->cursor_needs_physical)
13808
		addr = i915_gem_obj_ggtt_offset(obj);
13809
	else
13810
		addr = obj->phys_handle->busaddr;
5354 serge 13811
 
6084 serge 13812
	intel_crtc->cursor_addr = addr;
5354 serge 13813
 
6084 serge 13814
	if (crtc->state->active)
13815
		intel_crtc_update_cursor(crtc, state->visible);
5354 serge 13816
}
13817
 
5060 serge 13818
static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13819
						   int pipe)
13820
{
13821
	struct intel_plane *cursor;
6084 serge 13822
	struct intel_plane_state *state;
5060 serge 13823
 
13824
	cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13825
	if (cursor == NULL)
13826
		return NULL;
13827
 
6084 serge 13828
	state = intel_create_plane_state(&cursor->base);
13829
	if (!state) {
13830
		kfree(cursor);
13831
		return NULL;
13832
	}
13833
	cursor->base.state = &state->base;
13834
 
5060 serge 13835
	cursor->can_scale = false;
13836
	cursor->max_downscale = 1;
13837
	cursor->pipe = pipe;
13838
	cursor->plane = pipe;
6084 serge 13839
	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13840
	cursor->check_plane = intel_check_cursor_plane;
13841
	cursor->commit_plane = intel_commit_cursor_plane;
13842
	cursor->disable_plane = intel_disable_cursor_plane;
5060 serge 13843
 
13844
	drm_universal_plane_init(dev, &cursor->base, 0,
6084 serge 13845
				 &intel_plane_funcs,
5060 serge 13846
				 intel_cursor_formats,
13847
				 ARRAY_SIZE(intel_cursor_formats),
13848
				 DRM_PLANE_TYPE_CURSOR);
5354 serge 13849
 
13850
	if (INTEL_INFO(dev)->gen >= 4) {
13851
		if (!dev->mode_config.rotation_property)
13852
			dev->mode_config.rotation_property =
13853
				drm_mode_create_rotation_property(dev,
13854
							BIT(DRM_ROTATE_0) |
13855
							BIT(DRM_ROTATE_180));
13856
		if (dev->mode_config.rotation_property)
13857
			drm_object_attach_property(&cursor->base.base,
13858
				dev->mode_config.rotation_property,
6084 serge 13859
				state->base.rotation);
5354 serge 13860
	}
13861
 
6084 serge 13862
	if (INTEL_INFO(dev)->gen >=9)
13863
		state->scaler_id = -1;
13864
 
13865
	drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13866
 
5060 serge 13867
	return &cursor->base;
13868
}
13869
 
6084 serge 13870
static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13871
	struct intel_crtc_state *crtc_state)
13872
{
13873
	int i;
13874
	struct intel_scaler *intel_scaler;
13875
	struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13876
 
13877
	for (i = 0; i < intel_crtc->num_scalers; i++) {
13878
		intel_scaler = &scaler_state->scalers[i];
13879
		intel_scaler->in_use = 0;
13880
		intel_scaler->mode = PS_SCALER_MODE_DYN;
13881
	}
13882
 
13883
	scaler_state->scaler_id = -1;
13884
}
13885
 
2330 Serge 13886
static void intel_crtc_init(struct drm_device *dev, int pipe)
13887
{
5060 serge 13888
	struct drm_i915_private *dev_priv = dev->dev_private;
2330 Serge 13889
	struct intel_crtc *intel_crtc;
6084 serge 13890
	struct intel_crtc_state *crtc_state = NULL;
5060 serge 13891
	struct drm_plane *primary = NULL;
13892
	struct drm_plane *cursor = NULL;
13893
	int i, ret;
2327 Serge 13894
 
4560 Serge 13895
	intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
2330 Serge 13896
	if (intel_crtc == NULL)
13897
		return;
2327 Serge 13898
 
6084 serge 13899
	crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13900
	if (!crtc_state)
13901
		goto fail;
13902
	intel_crtc->config = crtc_state;
13903
	intel_crtc->base.state = &crtc_state->base;
13904
	crtc_state->base.crtc = &intel_crtc->base;
13905
 
13906
	/* initialize shared scalers */
13907
	if (INTEL_INFO(dev)->gen >= 9) {
13908
		if (pipe == PIPE_C)
13909
			intel_crtc->num_scalers = 1;
13910
		else
13911
			intel_crtc->num_scalers = SKL_NUM_SCALERS;
13912
 
13913
		skl_init_scalers(dev, intel_crtc, crtc_state);
13914
	}
13915
 
5060 serge 13916
	primary = intel_primary_plane_create(dev, pipe);
13917
	if (!primary)
13918
		goto fail;
2327 Serge 13919
 
5060 serge 13920
	cursor = intel_cursor_plane_create(dev, pipe);
13921
	if (!cursor)
13922
		goto fail;
13923
 
13924
	ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13925
					cursor, &intel_crtc_funcs);
13926
	if (ret)
13927
		goto fail;
13928
 
2330 Serge 13929
	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13930
	for (i = 0; i < 256; i++) {
13931
		intel_crtc->lut_r[i] = i;
13932
		intel_crtc->lut_g[i] = i;
13933
		intel_crtc->lut_b[i] = i;
13934
	}
2327 Serge 13935
 
4560 Serge 13936
	/*
13937
	 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
5060 serge 13938
	 * is hooked to pipe B. Hence we want plane A feeding pipe B.
4560 Serge 13939
	 */
2330 Serge 13940
	intel_crtc->pipe = pipe;
13941
	intel_crtc->plane = pipe;
4560 Serge 13942
	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
2330 Serge 13943
		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13944
		intel_crtc->plane = !pipe;
13945
	}
2327 Serge 13946
 
5060 serge 13947
	intel_crtc->cursor_base = ~0;
13948
	intel_crtc->cursor_cntl = ~0;
5354 serge 13949
	intel_crtc->cursor_size = ~0;
5060 serge 13950
 
6084 serge 13951
	intel_crtc->wm.cxsr_allowed = true;
13952
 
2330 Serge 13953
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13954
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13955
	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13956
	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327 Serge 13957
 
2330 Serge 13958
	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5060 serge 13959
 
13960
	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13961
	return;
13962
 
13963
fail:
13964
	if (primary)
13965
		drm_plane_cleanup(primary);
13966
	if (cursor)
13967
		drm_plane_cleanup(cursor);
6084 serge 13968
	kfree(crtc_state);
5060 serge 13969
	kfree(intel_crtc);
2330 Serge 13970
}
2327 Serge 13971
 
4560 Serge 13972
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13973
{
13974
	struct drm_encoder *encoder = connector->base.encoder;
5060 serge 13975
	struct drm_device *dev = connector->base.dev;
4560 Serge 13976
 
5060 serge 13977
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4560 Serge 13978
 
5354 serge 13979
	if (!encoder || WARN_ON(!encoder->crtc))
4560 Serge 13980
		return INVALID_PIPE;
13981
 
13982
	return to_intel_crtc(encoder->crtc)->pipe;
13983
}
13984
 
3031 serge 13985
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13986
				struct drm_file *file)
13987
{
13988
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5060 serge 13989
	struct drm_crtc *drmmode_crtc;
3031 serge 13990
	struct intel_crtc *crtc;
2327 Serge 13991
 
5060 serge 13992
	drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
2327 Serge 13993
 
5060 serge 13994
	if (!drmmode_crtc) {
3031 serge 13995
		DRM_ERROR("no such CRTC id\n");
4560 Serge 13996
		return -ENOENT;
3031 serge 13997
	}
2327 Serge 13998
 
5060 serge 13999
	crtc = to_intel_crtc(drmmode_crtc);
3031 serge 14000
	pipe_from_crtc_id->pipe = crtc->pipe;
2327 Serge 14001
 
3031 serge 14002
	return 0;
14003
}
2327 Serge 14004
 
3031 serge 14005
static int intel_encoder_clones(struct intel_encoder *encoder)
2330 Serge 14006
{
3031 serge 14007
	struct drm_device *dev = encoder->base.dev;
14008
	struct intel_encoder *source_encoder;
2330 Serge 14009
	int index_mask = 0;
14010
	int entry = 0;
2327 Serge 14011
 
5354 serge 14012
	for_each_intel_encoder(dev, source_encoder) {
5060 serge 14013
		if (encoders_cloneable(encoder, source_encoder))
2330 Serge 14014
			index_mask |= (1 << entry);
3031 serge 14015
 
2330 Serge 14016
		entry++;
14017
	}
2327 Serge 14018
 
2330 Serge 14019
	return index_mask;
14020
}
2327 Serge 14021
 
2330 Serge 14022
static bool has_edp_a(struct drm_device *dev)
14023
{
14024
	struct drm_i915_private *dev_priv = dev->dev_private;
2327 Serge 14025
 
2330 Serge 14026
	if (!IS_MOBILE(dev))
14027
		return false;
2327 Serge 14028
 
2330 Serge 14029
	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14030
		return false;
2327 Serge 14031
 
5060 serge 14032
	if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
2330 Serge 14033
		return false;
2327 Serge 14034
 
2330 Serge 14035
	return true;
14036
}
2327 Serge 14037
 
5060 serge 14038
static bool intel_crt_present(struct drm_device *dev)
14039
{
14040
	struct drm_i915_private *dev_priv = dev->dev_private;
14041
 
5354 serge 14042
	if (INTEL_INFO(dev)->gen >= 9)
5060 serge 14043
		return false;
14044
 
5354 serge 14045
	if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14046
		return false;
14047
 
5060 serge 14048
	if (IS_CHERRYVIEW(dev))
14049
		return false;
14050
 
14051
	if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14052
		return false;
14053
 
14054
	return true;
14055
}
14056
 
2330 Serge 14057
static void intel_setup_outputs(struct drm_device *dev)
14058
{
14059
	struct drm_i915_private *dev_priv = dev->dev_private;
14060
	struct intel_encoder *encoder;
14061
	bool dpd_is_edp = false;
2327 Serge 14062
 
4104 Serge 14063
	intel_lvds_init(dev);
2327 Serge 14064
 
5060 serge 14065
	if (intel_crt_present(dev))
6084 serge 14066
		intel_crt_init(dev);
2327 Serge 14067
 
6084 serge 14068
	if (IS_BROXTON(dev)) {
14069
		/*
14070
		 * FIXME: Broxton doesn't support port detection via the
14071
		 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14072
		 * detect the ports.
14073
		 */
14074
		intel_ddi_init(dev, PORT_A);
14075
		intel_ddi_init(dev, PORT_B);
14076
		intel_ddi_init(dev, PORT_C);
14077
	} else if (HAS_DDI(dev)) {
2330 Serge 14078
		int found;
2327 Serge 14079
 
6084 serge 14080
		/*
14081
		 * Haswell uses DDI functions to detect digital outputs.
14082
		 * On SKL pre-D0 the strap isn't connected, so we assume
14083
		 * it's there.
14084
		 */
14085
		found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14086
		/* WaIgnoreDDIAStrap: skl */
14087
		if (found || IS_SKYLAKE(dev))
3031 serge 14088
			intel_ddi_init(dev, PORT_A);
14089
 
14090
		/* DDI B, C and D detection is indicated by the SFUSE_STRAP
14091
		 * register */
14092
		found = I915_READ(SFUSE_STRAP);
14093
 
14094
		if (found & SFUSE_STRAP_DDIB_DETECTED)
14095
			intel_ddi_init(dev, PORT_B);
14096
		if (found & SFUSE_STRAP_DDIC_DETECTED)
14097
			intel_ddi_init(dev, PORT_C);
14098
		if (found & SFUSE_STRAP_DDID_DETECTED)
14099
			intel_ddi_init(dev, PORT_D);
6084 serge 14100
		/*
14101
		 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14102
		 */
14103
		if (IS_SKYLAKE(dev) &&
14104
		    (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14105
		     dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14106
		     dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14107
			intel_ddi_init(dev, PORT_E);
14108
 
3031 serge 14109
	} else if (HAS_PCH_SPLIT(dev)) {
14110
		int found;
4560 Serge 14111
		dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
3031 serge 14112
 
3243 Serge 14113
		if (has_edp_a(dev))
14114
			intel_dp_init(dev, DP_A, PORT_A);
14115
 
3746 Serge 14116
		if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
2330 Serge 14117
			/* PCH SDVOB multiplex with HDMIB */
3031 serge 14118
			found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330 Serge 14119
			if (!found)
3746 Serge 14120
				intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
2330 Serge 14121
			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031 serge 14122
				intel_dp_init(dev, PCH_DP_B, PORT_B);
2330 Serge 14123
		}
2327 Serge 14124
 
3746 Serge 14125
		if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14126
			intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
2327 Serge 14127
 
3746 Serge 14128
		if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14129
			intel_hdmi_init(dev, PCH_HDMID, PORT_D);
2327 Serge 14130
 
2330 Serge 14131
		if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031 serge 14132
			intel_dp_init(dev, PCH_DP_C, PORT_C);
2327 Serge 14133
 
3243 Serge 14134
		if (I915_READ(PCH_DP_D) & DP_DETECTED)
3031 serge 14135
			intel_dp_init(dev, PCH_DP_D, PORT_D);
14136
	} else if (IS_VALLEYVIEW(dev)) {
5354 serge 14137
		/*
14138
		 * The DP_DETECTED bit is the latched state of the DDC
14139
		 * SDA pin at boot. However since eDP doesn't require DDC
14140
		 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14141
		 * eDP ports may have been muxed to an alternate function.
14142
		 * Thus we can't rely on the DP_DETECTED bit alone to detect
14143
		 * eDP ports. Consult the VBT as well as DP_DETECTED to
14144
		 * detect eDP ports.
14145
		 */
6084 serge 14146
		if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14147
		    !intel_dp_is_edp(dev, PORT_B))
14148
			intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14149
		if (I915_READ(VLV_DP_B) & DP_DETECTED ||
5354 serge 14150
		    intel_dp_is_edp(dev, PORT_B))
6084 serge 14151
			intel_dp_init(dev, VLV_DP_B, PORT_B);
4560 Serge 14152
 
6084 serge 14153
		if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14154
		    !intel_dp_is_edp(dev, PORT_C))
14155
			intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14156
		if (I915_READ(VLV_DP_C) & DP_DETECTED ||
5354 serge 14157
		    intel_dp_is_edp(dev, PORT_C))
6084 serge 14158
			intel_dp_init(dev, VLV_DP_C, PORT_C);
3243 Serge 14159
 
5060 serge 14160
		if (IS_CHERRYVIEW(dev)) {
5354 serge 14161
			/* eDP not supported on port D, so don't check VBT */
6084 serge 14162
			if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14163
				intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14164
			if (I915_READ(CHV_DP_D) & DP_DETECTED)
14165
				intel_dp_init(dev, CHV_DP_D, PORT_D);
14166
		}
5060 serge 14167
 
4560 Serge 14168
		intel_dsi_init(dev);
6084 serge 14169
	} else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
2330 Serge 14170
		bool found = false;
2327 Serge 14171
 
3746 Serge 14172
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330 Serge 14173
			DRM_DEBUG_KMS("probing SDVOB\n");
3746 Serge 14174
			found = intel_sdvo_init(dev, GEN3_SDVOB, true);
6084 serge 14175
			if (!found && IS_G4X(dev)) {
2330 Serge 14176
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3746 Serge 14177
				intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
2330 Serge 14178
			}
2327 Serge 14179
 
6084 serge 14180
			if (!found && IS_G4X(dev))
3031 serge 14181
				intel_dp_init(dev, DP_B, PORT_B);
6084 serge 14182
		}
2327 Serge 14183
 
2330 Serge 14184
		/* Before G4X SDVOC doesn't have its own detect register */
2327 Serge 14185
 
3746 Serge 14186
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330 Serge 14187
			DRM_DEBUG_KMS("probing SDVOC\n");
3746 Serge 14188
			found = intel_sdvo_init(dev, GEN3_SDVOC, false);
2330 Serge 14189
		}
2327 Serge 14190
 
3746 Serge 14191
		if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
2327 Serge 14192
 
6084 serge 14193
			if (IS_G4X(dev)) {
2330 Serge 14194
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3746 Serge 14195
				intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
2330 Serge 14196
			}
6084 serge 14197
			if (IS_G4X(dev))
3031 serge 14198
				intel_dp_init(dev, DP_C, PORT_C);
6084 serge 14199
		}
2327 Serge 14200
 
6084 serge 14201
		if (IS_G4X(dev) &&
4104 Serge 14202
		    (I915_READ(DP_D) & DP_DETECTED))
3031 serge 14203
			intel_dp_init(dev, DP_D, PORT_D);
2330 Serge 14204
	} else if (IS_GEN2(dev))
14205
		intel_dvo_init(dev);
2327 Serge 14206
 
5354 serge 14207
	intel_psr_init(dev);
5060 serge 14208
 
5354 serge 14209
	for_each_intel_encoder(dev, encoder) {
2330 Serge 14210
		encoder->base.possible_crtcs = encoder->crtc_mask;
14211
		encoder->base.possible_clones =
3031 serge 14212
			intel_encoder_clones(encoder);
2330 Serge 14213
	}
2327 Serge 14214
 
3243 Serge 14215
	intel_init_pch_refclk(dev);
14216
 
14217
	drm_helper_move_panel_connectors_to_head(dev);
2330 Serge 14218
}
14219
 
6084 serge 14220
static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14221
{
14222
	struct drm_device *dev = fb->dev;
14223
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2330 Serge 14224
 
6084 serge 14225
	drm_framebuffer_cleanup(fb);
14226
	mutex_lock(&dev->struct_mutex);
14227
	WARN_ON(!intel_fb->obj->framebuffer_references--);
14228
	drm_gem_object_unreference(&intel_fb->obj->base);
14229
	mutex_unlock(&dev->struct_mutex);
14230
	kfree(intel_fb);
14231
}
2330 Serge 14232
 
6084 serge 14233
static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14234
						struct drm_file *file,
14235
						unsigned int *handle)
14236
{
14237
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14238
	struct drm_i915_gem_object *obj = intel_fb->obj;
14239
 
14240
	if (obj->userptr.mm) {
14241
		DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14242
		return -EINVAL;
14243
	}
14244
 
14245
	return drm_gem_handle_create(file, &obj->base, handle);
14246
}
14247
 
14248
static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14249
					struct drm_file *file,
14250
					unsigned flags, unsigned color,
14251
					struct drm_clip_rect *clips,
14252
					unsigned num_clips)
14253
{
14254
	struct drm_device *dev = fb->dev;
14255
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14256
	struct drm_i915_gem_object *obj = intel_fb->obj;
14257
 
14258
	mutex_lock(&dev->struct_mutex);
14259
	intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14260
	mutex_unlock(&dev->struct_mutex);
14261
 
14262
	return 0;
14263
}
14264
 
2335 Serge 14265
static const struct drm_framebuffer_funcs intel_fb_funcs = {
6084 serge 14266
	.destroy = intel_user_framebuffer_destroy,
14267
	.create_handle = intel_user_framebuffer_create_handle,
14268
	.dirty = intel_user_framebuffer_dirty,
2335 Serge 14269
};
2327 Serge 14270
 
6084 serge 14271
static
14272
u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14273
			 uint32_t pixel_format)
14274
{
14275
	u32 gen = INTEL_INFO(dev)->gen;
14276
 
14277
	if (gen >= 9) {
14278
		/* "The stride in bytes must not exceed the of the size of 8K
14279
		 *  pixels and 32K bytes."
14280
		 */
14281
		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14282
	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14283
		return 32*1024;
14284
	} else if (gen >= 4) {
14285
		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14286
			return 16*1024;
14287
		else
14288
			return 32*1024;
14289
	} else if (gen >= 3) {
14290
		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14291
			return 8*1024;
14292
		else
14293
			return 16*1024;
14294
	} else {
14295
		/* XXX DSPC is limited to 4k tiled */
14296
		return 8*1024;
14297
	}
14298
}
14299
 
5060 serge 14300
static int intel_framebuffer_init(struct drm_device *dev,
6084 serge 14301
				  struct intel_framebuffer *intel_fb,
14302
				  struct drm_mode_fb_cmd2 *mode_cmd,
14303
				  struct drm_i915_gem_object *obj)
2335 Serge 14304
{
6084 serge 14305
	unsigned int aligned_height;
2335 Serge 14306
	int ret;
6084 serge 14307
	u32 pitch_limit, stride_alignment;
2327 Serge 14308
 
4560 Serge 14309
	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14310
 
6084 serge 14311
	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14312
		/* Enforce that fb modifier and tiling mode match, but only for
14313
		 * X-tiled. This is needed for FBC. */
14314
		if (!!(obj->tiling_mode == I915_TILING_X) !=
14315
		    !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14316
			DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14317
			return -EINVAL;
14318
		}
14319
	} else {
14320
		if (obj->tiling_mode == I915_TILING_X)
14321
			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14322
		else if (obj->tiling_mode == I915_TILING_Y) {
14323
			DRM_DEBUG("No Y tiling for legacy addfb\n");
14324
			return -EINVAL;
14325
		}
14326
	}
14327
 
14328
	/* Passed in modifier sanity checking. */
14329
	switch (mode_cmd->modifier[0]) {
14330
	case I915_FORMAT_MOD_Y_TILED:
14331
	case I915_FORMAT_MOD_Yf_TILED:
14332
		if (INTEL_INFO(dev)->gen < 9) {
14333
			DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14334
				  mode_cmd->modifier[0]);
14335
			return -EINVAL;
14336
		}
14337
	case DRM_FORMAT_MOD_NONE:
14338
	case I915_FORMAT_MOD_X_TILED:
14339
		break;
14340
	default:
14341
		DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14342
			  mode_cmd->modifier[0]);
2335 Serge 14343
		return -EINVAL;
3243 Serge 14344
	}
2327 Serge 14345
 
6084 serge 14346
	stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14347
						     mode_cmd->pixel_format);
14348
	if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14349
		DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14350
			  mode_cmd->pitches[0], stride_alignment);
3243 Serge 14351
		return -EINVAL;
14352
	}
14353
 
6084 serge 14354
	pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14355
					   mode_cmd->pixel_format);
4104 Serge 14356
	if (mode_cmd->pitches[0] > pitch_limit) {
6084 serge 14357
		DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14358
			  mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14359
			  "tiled" : "linear",
4104 Serge 14360
			  mode_cmd->pitches[0], pitch_limit);
3243 Serge 14361
		return -EINVAL;
14362
	}
14363
 
6084 serge 14364
	if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
3243 Serge 14365
	    mode_cmd->pitches[0] != obj->stride) {
14366
		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14367
			  mode_cmd->pitches[0], obj->stride);
6084 serge 14368
		return -EINVAL;
3243 Serge 14369
	}
2327 Serge 14370
 
3243 Serge 14371
	/* Reject formats not supported by any plane early. */
2342 Serge 14372
	switch (mode_cmd->pixel_format) {
3243 Serge 14373
	case DRM_FORMAT_C8:
2342 Serge 14374
	case DRM_FORMAT_RGB565:
14375
	case DRM_FORMAT_XRGB8888:
3243 Serge 14376
	case DRM_FORMAT_ARGB8888:
14377
		break;
14378
	case DRM_FORMAT_XRGB1555:
14379
		if (INTEL_INFO(dev)->gen > 3) {
4104 Serge 14380
			DRM_DEBUG("unsupported pixel format: %s\n",
14381
				  drm_get_format_name(mode_cmd->pixel_format));
3243 Serge 14382
			return -EINVAL;
14383
		}
14384
		break;
6084 serge 14385
	case DRM_FORMAT_ABGR8888:
14386
		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14387
			DRM_DEBUG("unsupported pixel format: %s\n",
14388
				  drm_get_format_name(mode_cmd->pixel_format));
14389
			return -EINVAL;
14390
		}
14391
		break;
3031 serge 14392
	case DRM_FORMAT_XBGR8888:
2342 Serge 14393
	case DRM_FORMAT_XRGB2101010:
3243 Serge 14394
	case DRM_FORMAT_XBGR2101010:
14395
		if (INTEL_INFO(dev)->gen < 4) {
4104 Serge 14396
			DRM_DEBUG("unsupported pixel format: %s\n",
14397
				  drm_get_format_name(mode_cmd->pixel_format));
3243 Serge 14398
			return -EINVAL;
14399
		}
2335 Serge 14400
		break;
6084 serge 14401
	case DRM_FORMAT_ABGR2101010:
14402
		if (!IS_VALLEYVIEW(dev)) {
14403
			DRM_DEBUG("unsupported pixel format: %s\n",
14404
				  drm_get_format_name(mode_cmd->pixel_format));
14405
			return -EINVAL;
14406
		}
14407
		break;
2342 Serge 14408
	case DRM_FORMAT_YUYV:
14409
	case DRM_FORMAT_UYVY:
14410
	case DRM_FORMAT_YVYU:
14411
	case DRM_FORMAT_VYUY:
3243 Serge 14412
		if (INTEL_INFO(dev)->gen < 5) {
4104 Serge 14413
			DRM_DEBUG("unsupported pixel format: %s\n",
14414
				  drm_get_format_name(mode_cmd->pixel_format));
3243 Serge 14415
			return -EINVAL;
14416
		}
2342 Serge 14417
		break;
2335 Serge 14418
	default:
4104 Serge 14419
		DRM_DEBUG("unsupported pixel format: %s\n",
14420
			  drm_get_format_name(mode_cmd->pixel_format));
2335 Serge 14421
		return -EINVAL;
14422
	}
2327 Serge 14423
 
3243 Serge 14424
	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14425
	if (mode_cmd->offsets[0] != 0)
14426
		return -EINVAL;
14427
 
6084 serge 14428
	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14429
					       mode_cmd->pixel_format,
14430
					       mode_cmd->modifier[0]);
4560 Serge 14431
	/* FIXME drm helper for size checks (especially planar formats)? */
14432
	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14433
		return -EINVAL;
14434
 
3480 Serge 14435
	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14436
	intel_fb->obj = obj;
4560 Serge 14437
	intel_fb->obj->framebuffer_references++;
3480 Serge 14438
 
2335 Serge 14439
	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14440
	if (ret) {
14441
		DRM_ERROR("framebuffer init failed %d\n", ret);
14442
		return ret;
14443
	}
6283 serge 14444
	kolibri_framebuffer_init(intel_fb);
2327 Serge 14445
 
2335 Serge 14446
	return 0;
14447
}
2327 Serge 14448
 
6084 serge 14449
static struct drm_framebuffer *
14450
intel_user_framebuffer_create(struct drm_device *dev,
14451
			      struct drm_file *filp,
14452
			      struct drm_mode_fb_cmd2 *user_mode_cmd)
14453
{
14454
	struct drm_i915_gem_object *obj;
14455
	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14456
 
14457
	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14458
						mode_cmd.handles[0]));
14459
	if (&obj->base == NULL)
14460
		return ERR_PTR(-ENOENT);
14461
 
14462
	return intel_framebuffer_create(dev, &mode_cmd, obj);
14463
}
14464
 
14465
#ifndef CONFIG_DRM_FBDEV_EMULATION
4560 Serge 14466
static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14467
{
14468
}
14469
#endif
2327 Serge 14470
 
2360 Serge 14471
static const struct drm_mode_config_funcs intel_mode_funcs = {
6084 serge 14472
	.fb_create = intel_user_framebuffer_create,
4560 Serge 14473
	.output_poll_changed = intel_fbdev_output_poll_changed,
6084 serge 14474
	.atomic_check = intel_atomic_check,
14475
	.atomic_commit = intel_atomic_commit,
14476
	.atomic_state_alloc = intel_atomic_state_alloc,
14477
	.atomic_state_clear = intel_atomic_state_clear,
2360 Serge 14478
};
2327 Serge 14479
 
3031 serge 14480
/* Set up chip specific display functions */
14481
static void intel_init_display(struct drm_device *dev)
14482
{
14483
	struct drm_i915_private *dev_priv = dev->dev_private;
2327 Serge 14484
 
4104 Serge 14485
	if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14486
		dev_priv->display.find_dpll = g4x_find_best_dpll;
5060 serge 14487
	else if (IS_CHERRYVIEW(dev))
14488
		dev_priv->display.find_dpll = chv_find_best_dpll;
4104 Serge 14489
	else if (IS_VALLEYVIEW(dev))
14490
		dev_priv->display.find_dpll = vlv_find_best_dpll;
14491
	else if (IS_PINEVIEW(dev))
14492
		dev_priv->display.find_dpll = pnv_find_best_dpll;
14493
	else
14494
		dev_priv->display.find_dpll = i9xx_find_best_dpll;
14495
 
6084 serge 14496
	if (INTEL_INFO(dev)->gen >= 9) {
3746 Serge 14497
		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
6084 serge 14498
		dev_priv->display.get_initial_plane_config =
14499
			skylake_get_initial_plane_config;
5354 serge 14500
		dev_priv->display.crtc_compute_clock =
14501
			haswell_crtc_compute_clock;
3243 Serge 14502
		dev_priv->display.crtc_enable = haswell_crtc_enable;
14503
		dev_priv->display.crtc_disable = haswell_crtc_disable;
5060 serge 14504
		dev_priv->display.update_primary_plane =
6084 serge 14505
			skylake_update_primary_plane;
14506
	} else if (HAS_DDI(dev)) {
14507
		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14508
		dev_priv->display.get_initial_plane_config =
14509
			ironlake_get_initial_plane_config;
14510
		dev_priv->display.crtc_compute_clock =
14511
			haswell_crtc_compute_clock;
14512
		dev_priv->display.crtc_enable = haswell_crtc_enable;
14513
		dev_priv->display.crtc_disable = haswell_crtc_disable;
14514
		dev_priv->display.update_primary_plane =
5060 serge 14515
			ironlake_update_primary_plane;
3243 Serge 14516
	} else if (HAS_PCH_SPLIT(dev)) {
3746 Serge 14517
		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
6084 serge 14518
		dev_priv->display.get_initial_plane_config =
14519
			ironlake_get_initial_plane_config;
5354 serge 14520
		dev_priv->display.crtc_compute_clock =
14521
			ironlake_crtc_compute_clock;
3031 serge 14522
		dev_priv->display.crtc_enable = ironlake_crtc_enable;
14523
		dev_priv->display.crtc_disable = ironlake_crtc_disable;
5060 serge 14524
		dev_priv->display.update_primary_plane =
14525
			ironlake_update_primary_plane;
4104 Serge 14526
	} else if (IS_VALLEYVIEW(dev)) {
14527
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
6084 serge 14528
		dev_priv->display.get_initial_plane_config =
14529
			i9xx_get_initial_plane_config;
5354 serge 14530
		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
4104 Serge 14531
		dev_priv->display.crtc_enable = valleyview_crtc_enable;
14532
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
5060 serge 14533
		dev_priv->display.update_primary_plane =
14534
			i9xx_update_primary_plane;
3031 serge 14535
	} else {
3746 Serge 14536
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
6084 serge 14537
		dev_priv->display.get_initial_plane_config =
14538
			i9xx_get_initial_plane_config;
5354 serge 14539
		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
3031 serge 14540
		dev_priv->display.crtc_enable = i9xx_crtc_enable;
14541
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
5060 serge 14542
		dev_priv->display.update_primary_plane =
14543
			i9xx_update_primary_plane;
3031 serge 14544
	}
2327 Serge 14545
 
3031 serge 14546
	/* Returns the core display clock speed */
6084 serge 14547
	if (IS_SKYLAKE(dev))
3031 serge 14548
		dev_priv->display.get_display_clock_speed =
6084 serge 14549
			skylake_get_display_clock_speed;
14550
	else if (IS_BROXTON(dev))
14551
		dev_priv->display.get_display_clock_speed =
14552
			broxton_get_display_clock_speed;
14553
	else if (IS_BROADWELL(dev))
14554
		dev_priv->display.get_display_clock_speed =
14555
			broadwell_get_display_clock_speed;
14556
	else if (IS_HASWELL(dev))
14557
		dev_priv->display.get_display_clock_speed =
14558
			haswell_get_display_clock_speed;
14559
	else if (IS_VALLEYVIEW(dev))
14560
		dev_priv->display.get_display_clock_speed =
3031 serge 14561
			valleyview_get_display_clock_speed;
6084 serge 14562
	else if (IS_GEN5(dev))
3031 serge 14563
		dev_priv->display.get_display_clock_speed =
6084 serge 14564
			ilk_get_display_clock_speed;
14565
	else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14566
		 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14567
		dev_priv->display.get_display_clock_speed =
3031 serge 14568
			i945_get_display_clock_speed;
6084 serge 14569
	else if (IS_GM45(dev))
14570
		dev_priv->display.get_display_clock_speed =
14571
			gm45_get_display_clock_speed;
14572
	else if (IS_CRESTLINE(dev))
14573
		dev_priv->display.get_display_clock_speed =
14574
			i965gm_get_display_clock_speed;
14575
	else if (IS_PINEVIEW(dev))
14576
		dev_priv->display.get_display_clock_speed =
14577
			pnv_get_display_clock_speed;
14578
	else if (IS_G33(dev) || IS_G4X(dev))
14579
		dev_priv->display.get_display_clock_speed =
14580
			g33_get_display_clock_speed;
3031 serge 14581
	else if (IS_I915G(dev))
14582
		dev_priv->display.get_display_clock_speed =
14583
			i915_get_display_clock_speed;
4104 Serge 14584
	else if (IS_I945GM(dev) || IS_845G(dev))
3031 serge 14585
		dev_priv->display.get_display_clock_speed =
14586
			i9xx_misc_get_display_clock_speed;
4104 Serge 14587
	else if (IS_PINEVIEW(dev))
14588
		dev_priv->display.get_display_clock_speed =
14589
			pnv_get_display_clock_speed;
3031 serge 14590
	else if (IS_I915GM(dev))
14591
		dev_priv->display.get_display_clock_speed =
14592
			i915gm_get_display_clock_speed;
14593
	else if (IS_I865G(dev))
14594
		dev_priv->display.get_display_clock_speed =
14595
			i865_get_display_clock_speed;
14596
	else if (IS_I85X(dev))
14597
		dev_priv->display.get_display_clock_speed =
6084 serge 14598
			i85x_get_display_clock_speed;
14599
	else { /* 830 */
14600
		WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
3031 serge 14601
		dev_priv->display.get_display_clock_speed =
14602
			i830_get_display_clock_speed;
6084 serge 14603
	}
2327 Serge 14604
 
6084 serge 14605
	if (IS_GEN5(dev)) {
14606
		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14607
	} else if (IS_GEN6(dev)) {
14608
		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14609
	} else if (IS_IVYBRIDGE(dev)) {
14610
		/* FIXME: detect B0+ stepping and use auto training */
14611
		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
5354 serge 14612
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6084 serge 14613
		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14614
		if (IS_BROADWELL(dev)) {
14615
			dev_priv->display.modeset_commit_cdclk =
14616
				broadwell_modeset_commit_cdclk;
14617
			dev_priv->display.modeset_calc_cdclk =
14618
				broadwell_modeset_calc_cdclk;
14619
		}
4560 Serge 14620
	} else if (IS_VALLEYVIEW(dev)) {
6084 serge 14621
		dev_priv->display.modeset_commit_cdclk =
14622
			valleyview_modeset_commit_cdclk;
14623
		dev_priv->display.modeset_calc_cdclk =
14624
			valleyview_modeset_calc_cdclk;
14625
	} else if (IS_BROXTON(dev)) {
14626
		dev_priv->display.modeset_commit_cdclk =
14627
			broxton_modeset_commit_cdclk;
14628
		dev_priv->display.modeset_calc_cdclk =
14629
			broxton_modeset_calc_cdclk;
3031 serge 14630
	}
2327 Serge 14631
 
14632
 
14633
 
14634
 
14635
 
5354 serge 14636
 
14637
	mutex_init(&dev_priv->pps_mutex);
3031 serge 14638
}
14639
 
14640
/*
14641
 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14642
 * resume, or other times.  This quirk makes sure that's the case for
14643
 * affected systems.
14644
 */
14645
static void quirk_pipea_force(struct drm_device *dev)
2330 Serge 14646
{
14647
	struct drm_i915_private *dev_priv = dev->dev_private;
2327 Serge 14648
 
3031 serge 14649
	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14650
	DRM_INFO("applying pipe a force quirk\n");
14651
}
2327 Serge 14652
 
5354 serge 14653
static void quirk_pipeb_force(struct drm_device *dev)
14654
{
14655
	struct drm_i915_private *dev_priv = dev->dev_private;
14656
 
14657
	dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14658
	DRM_INFO("applying pipe b force quirk\n");
14659
}
14660
 
3031 serge 14661
/*
14662
 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14663
 */
14664
static void quirk_ssc_force_disable(struct drm_device *dev)
14665
{
14666
	struct drm_i915_private *dev_priv = dev->dev_private;
14667
	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14668
	DRM_INFO("applying lvds SSC disable quirk\n");
2330 Serge 14669
}
2327 Serge 14670
 
3031 serge 14671
/*
14672
 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14673
 * brightness value
14674
 */
14675
static void quirk_invert_brightness(struct drm_device *dev)
2330 Serge 14676
{
14677
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 14678
	dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14679
	DRM_INFO("applying inverted panel brightness quirk\n");
14680
}
2327 Serge 14681
 
5060 serge 14682
/* Some VBT's incorrectly indicate no backlight is present */
14683
static void quirk_backlight_present(struct drm_device *dev)
14684
{
14685
	struct drm_i915_private *dev_priv = dev->dev_private;
14686
	dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14687
	DRM_INFO("applying backlight present quirk\n");
14688
}
14689
 
3031 serge 14690
struct intel_quirk {
14691
	int device;
14692
	int subsystem_vendor;
14693
	int subsystem_device;
14694
	void (*hook)(struct drm_device *dev);
14695
};
2327 Serge 14696
 
3031 serge 14697
/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14698
struct intel_dmi_quirk {
14699
	void (*hook)(struct drm_device *dev);
14700
	const struct dmi_system_id (*dmi_id_list)[];
14701
};
2327 Serge 14702
 
3031 serge 14703
static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14704
{
14705
	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14706
	return 1;
2330 Serge 14707
}
2327 Serge 14708
 
3031 serge 14709
static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14710
	{
14711
		.dmi_id_list = &(const struct dmi_system_id[]) {
14712
			{
14713
				.callback = intel_dmi_reverse_brightness,
14714
				.ident = "NCR Corporation",
14715
				.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14716
					    DMI_MATCH(DMI_PRODUCT_NAME, ""),
14717
				},
14718
			},
14719
			{ }  /* terminating entry */
14720
		},
14721
		.hook = quirk_invert_brightness,
14722
	},
14723
};
2327 Serge 14724
 
3031 serge 14725
static struct intel_quirk intel_quirks[] = {
14726
	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14727
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327 Serge 14728
 
3031 serge 14729
	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14730
	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327 Serge 14731
 
5367 serge 14732
	/* 830 needs to leave pipe A & dpll A up */
14733
	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14734
 
14735
	/* 830 needs to leave pipe B & dpll B up */
14736
	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14737
 
3031 serge 14738
	/* Lenovo U160 cannot use SSC on LVDS */
14739
	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327 Serge 14740
 
3031 serge 14741
	/* Sony Vaio Y cannot use SSC on LVDS */
14742
	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327 Serge 14743
 
3031 serge 14744
	/* Acer Aspire 5734Z must invert backlight brightness */
14745
	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
3480 Serge 14746
 
14747
	/* Acer/eMachines G725 */
14748
	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14749
 
14750
	/* Acer/eMachines e725 */
14751
	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14752
 
14753
	/* Acer/Packard Bell NCL20 */
14754
	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14755
 
14756
	/* Acer Aspire 4736Z */
14757
	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
5060 serge 14758
 
14759
	/* Acer Aspire 5336 */
14760
	{ 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14761
 
14762
	/* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14763
	{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14764
 
5097 serge 14765
	/* Acer C720 Chromebook (Core i3 4005U) */
14766
	{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14767
 
5354 serge 14768
	/* Apple Macbook 2,1 (Core 2 T7400) */
14769
	{ 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14770
 
6084 serge 14771
	/* Apple Macbook 4,1 */
14772
	{ 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14773
 
5060 serge 14774
	/* Toshiba CB35 Chromebook (Celeron 2955U) */
14775
	{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14776
 
14777
	/* HP Chromebook 14 (Celeron 2955U) */
14778
	{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
6084 serge 14779
 
14780
	/* Dell Chromebook 11 */
14781
	{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14782
 
14783
	/* Dell Chromebook 11 (2015 version) */
14784
	{ 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
3031 serge 14785
};
2327 Serge 14786
 
3031 serge 14787
static void intel_init_quirks(struct drm_device *dev)
2330 Serge 14788
{
3031 serge 14789
	struct pci_dev *d = dev->pdev;
14790
	int i;
2327 Serge 14791
 
3031 serge 14792
	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14793
		struct intel_quirk *q = &intel_quirks[i];
2327 Serge 14794
 
3031 serge 14795
		if (d->device == q->device &&
14796
		    (d->subsystem_vendor == q->subsystem_vendor ||
14797
		     q->subsystem_vendor == PCI_ANY_ID) &&
14798
		    (d->subsystem_device == q->subsystem_device ||
14799
		     q->subsystem_device == PCI_ANY_ID))
14800
			q->hook(dev);
14801
	}
5097 serge 14802
	for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14803
		if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14804
			intel_dmi_quirks[i].hook(dev);
14805
	}
2330 Serge 14806
}
2327 Serge 14807
 
3031 serge 14808
/* Disable the VGA plane that we never use */
14809
static void i915_disable_vga(struct drm_device *dev)
2330 Serge 14810
{
14811
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 14812
	u8 sr1;
3480 Serge 14813
	u32 vga_reg = i915_vgacntrl_reg(dev);
2327 Serge 14814
 
6084 serge 14815
	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
4560 Serge 14816
//	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14817
	outb(SR01, VGA_SR_INDEX);
14818
	sr1 = inb(VGA_SR_DATA);
14819
	outb(sr1 | 1<<5, VGA_SR_DATA);
14820
//	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
3031 serge 14821
	udelay(300);
2327 Serge 14822
 
6084 serge 14823
	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
3031 serge 14824
	POSTING_READ(vga_reg);
2330 Serge 14825
}
14826
 
3031 serge 14827
void intel_modeset_init_hw(struct drm_device *dev)
2342 Serge 14828
{
6084 serge 14829
	intel_update_cdclk(dev);
3031 serge 14830
	intel_prepare_ddi(dev);
14831
	intel_init_clock_gating(dev);
6084 serge 14832
	intel_enable_gt_powersave(dev);
2342 Serge 14833
}
14834
 
3031 serge 14835
void intel_modeset_init(struct drm_device *dev)
2330 Serge 14836
{
3031 serge 14837
	struct drm_i915_private *dev_priv = dev->dev_private;
5060 serge 14838
	int sprite, ret;
14839
	enum pipe pipe;
14840
	struct intel_crtc *crtc;
6088 serge 14841
 
3031 serge 14842
	drm_mode_config_init(dev);
2330 Serge 14843
 
3031 serge 14844
	dev->mode_config.min_width = 0;
14845
	dev->mode_config.min_height = 0;
2330 Serge 14846
 
3031 serge 14847
	dev->mode_config.preferred_depth = 24;
14848
	dev->mode_config.prefer_shadow = 1;
2330 Serge 14849
 
6084 serge 14850
	dev->mode_config.allow_fb_modifiers = true;
14851
 
3031 serge 14852
	dev->mode_config.funcs = &intel_mode_funcs;
2330 Serge 14853
 
3031 serge 14854
	intel_init_quirks(dev);
2330 Serge 14855
 
3031 serge 14856
	intel_init_pm(dev);
2330 Serge 14857
 
3746 Serge 14858
	if (INTEL_INFO(dev)->num_pipes == 0)
14859
		return;
14860
 
6084 serge 14861
	/*
14862
	 * There may be no VBT; and if the BIOS enabled SSC we can
14863
	 * just keep using it to avoid unnecessary flicker.  Whereas if the
14864
	 * BIOS isn't using it, don't assume it will work even if the VBT
14865
	 * indicates as much.
14866
	 */
14867
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14868
		bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14869
					    DREF_SSC1_ENABLE);
14870
 
14871
		if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14872
			DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14873
				     bios_lvds_use_ssc ? "en" : "dis",
14874
				     dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14875
			dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14876
		}
14877
	}
14878
 
3031 serge 14879
	intel_init_display(dev);
2330 Serge 14880
 
3031 serge 14881
	if (IS_GEN2(dev)) {
14882
		dev->mode_config.max_width = 2048;
14883
		dev->mode_config.max_height = 2048;
14884
	} else if (IS_GEN3(dev)) {
14885
		dev->mode_config.max_width = 4096;
14886
		dev->mode_config.max_height = 4096;
14887
	} else {
14888
		dev->mode_config.max_width = 8192;
14889
		dev->mode_config.max_height = 8192;
14890
	}
5060 serge 14891
 
14892
	if (IS_GEN2(dev)) {
14893
		dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14894
		dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14895
	} else {
14896
		dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14897
		dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14898
	}
14899
 
3480 Serge 14900
	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
2330 Serge 14901
 
3031 serge 14902
	DRM_DEBUG_KMS("%d display pipe%s available.\n",
3746 Serge 14903
		      INTEL_INFO(dev)->num_pipes,
14904
		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
2330 Serge 14905
 
5354 serge 14906
	for_each_pipe(dev_priv, pipe) {
5060 serge 14907
		intel_crtc_init(dev, pipe);
6084 serge 14908
		for_each_sprite(dev_priv, pipe, sprite) {
5060 serge 14909
			ret = intel_plane_init(dev, pipe, sprite);
6084 serge 14910
			if (ret)
4104 Serge 14911
				DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
5060 serge 14912
					      pipe_name(pipe), sprite_name(pipe, sprite), ret);
3746 Serge 14913
		}
2330 Serge 14914
	}
14915
 
6084 serge 14916
	intel_update_czclk(dev_priv);
14917
	intel_update_cdclk(dev);
4560 Serge 14918
 
4104 Serge 14919
	intel_shared_dpll_init(dev);
2330 Serge 14920
 
3031 serge 14921
	/* Just disable it once at startup */
14922
	i915_disable_vga(dev);
14923
	intel_setup_outputs(dev);
3480 Serge 14924
 
14925
	/* Just in case the BIOS is doing something questionable. */
6084 serge 14926
	intel_fbc_disable(dev_priv);
2330 Serge 14927
 
5060 serge 14928
	drm_modeset_lock_all(dev);
6084 serge 14929
	intel_modeset_setup_hw_state(dev);
5060 serge 14930
	drm_modeset_unlock_all(dev);
14931
 
14932
	for_each_intel_crtc(dev, crtc) {
6084 serge 14933
		struct intel_initial_plane_config plane_config = {};
14934
 
5060 serge 14935
		if (!crtc->active)
14936
			continue;
14937
 
14938
		/*
14939
		 * Note that reserving the BIOS fb up front prevents us
14940
		 * from stuffing other stolen allocations like the ring
14941
		 * on top.  This prevents some ugliness at boot time, and
14942
		 * can even allow for smooth boot transitions if the BIOS
14943
		 * fb is large enough for the active pipe configuration.
14944
		 */
6084 serge 14945
		dev_priv->display.get_initial_plane_config(crtc,
14946
							   &plane_config);
14947
 
14948
		/*
14949
		 * If the fb is shared between multiple heads, we'll
14950
		 * just get the first one.
14951
		 */
14952
		intel_find_initial_plane_obj(crtc, &plane_config);
5060 serge 14953
	}
2330 Serge 14954
}
14955
 
3031 serge 14956
static void intel_enable_pipe_a(struct drm_device *dev)
2330 Serge 14957
{
3031 serge 14958
	struct intel_connector *connector;
14959
	struct drm_connector *crt = NULL;
14960
	struct intel_load_detect_pipe load_detect_temp;
5060 serge 14961
	struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
2330 Serge 14962
 
3031 serge 14963
	/* We can't just switch on the pipe A, we need to set things up with a
14964
	 * proper mode and output configuration. As a gross hack, enable pipe A
14965
	 * by enabling the load detect pipe once. */
6084 serge 14966
	for_each_intel_connector(dev, connector) {
3031 serge 14967
		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14968
			crt = &connector->base;
14969
			break;
2330 Serge 14970
		}
14971
	}
14972
 
3031 serge 14973
	if (!crt)
14974
		return;
2330 Serge 14975
 
5060 serge 14976
	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
6084 serge 14977
		intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
2327 Serge 14978
}
14979
 
3031 serge 14980
static bool
14981
intel_check_plane_mapping(struct intel_crtc *crtc)
2327 Serge 14982
{
3746 Serge 14983
	struct drm_device *dev = crtc->base.dev;
14984
	struct drm_i915_private *dev_priv = dev->dev_private;
6084 serge 14985
	u32 val;
2327 Serge 14986
 
3746 Serge 14987
	if (INTEL_INFO(dev)->num_pipes == 1)
3031 serge 14988
		return true;
2327 Serge 14989
 
6084 serge 14990
	val = I915_READ(DSPCNTR(!crtc->plane));
2327 Serge 14991
 
3031 serge 14992
	if ((val & DISPLAY_PLANE_ENABLE) &&
14993
	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14994
		return false;
2327 Serge 14995
 
3031 serge 14996
	return true;
2327 Serge 14997
}
14998
 
6084 serge 14999
static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15000
{
15001
	struct drm_device *dev = crtc->base.dev;
15002
	struct intel_encoder *encoder;
15003
 
15004
	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15005
		return true;
15006
 
15007
	return false;
15008
}
15009
 
3031 serge 15010
static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327 Serge 15011
{
3031 serge 15012
	struct drm_device *dev = crtc->base.dev;
2327 Serge 15013
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 15014
	u32 reg;
2327 Serge 15015
 
3031 serge 15016
	/* Clear any frame start delays used for debugging left by the BIOS */
6084 serge 15017
	reg = PIPECONF(crtc->config->cpu_transcoder);
3031 serge 15018
	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327 Serge 15019
 
5060 serge 15020
	/* restore vblank interrupts to correct state */
6084 serge 15021
	drm_crtc_vblank_reset(&crtc->base);
5354 serge 15022
	if (crtc->active) {
6084 serge 15023
		struct intel_plane *plane;
5060 serge 15024
 
6084 serge 15025
		drm_crtc_vblank_on(&crtc->base);
15026
 
15027
		/* Disable everything but the primary plane */
15028
		for_each_intel_plane_on_crtc(dev, crtc, plane) {
15029
			if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15030
				continue;
15031
 
15032
			plane->disable_plane(&plane->base, &crtc->base);
15033
		}
15034
	}
15035
 
3031 serge 15036
	/* We need to sanitize the plane -> pipe mapping first because this will
15037
	 * disable the crtc (and hence change the state) if it is wrong. Note
15038
	 * that gen4+ has a fixed plane -> pipe mapping.  */
15039
	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15040
		bool plane;
2327 Serge 15041
 
3031 serge 15042
		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15043
			      crtc->base.base.id);
2327 Serge 15044
 
3031 serge 15045
		/* Pipe has the wrong plane attached and the plane is active.
15046
		 * Temporarily change the plane mapping and disable everything
15047
		 * ...  */
15048
		plane = crtc->plane;
6084 serge 15049
		to_intel_plane_state(crtc->base.primary->state)->visible = true;
3031 serge 15050
		crtc->plane = !plane;
6084 serge 15051
		intel_crtc_disable_noatomic(&crtc->base);
3031 serge 15052
		crtc->plane = plane;
15053
	}
2327 Serge 15054
 
3031 serge 15055
	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15056
	    crtc->pipe == PIPE_A && !crtc->active) {
15057
		/* BIOS forgot to enable pipe A, this mostly happens after
15058
		 * resume. Force-enable the pipe to fix this, the update_dpms
15059
		 * call below we restore the pipe to the right state, but leave
15060
		 * the required bits on. */
15061
		intel_enable_pipe_a(dev);
15062
	}
2327 Serge 15063
 
3031 serge 15064
	/* Adjust the state of the output pipe according to whether we
15065
	 * have active connectors/encoders. */
6084 serge 15066
	if (!intel_crtc_has_encoders(crtc))
15067
		intel_crtc_disable_noatomic(&crtc->base);
2327 Serge 15068
 
6084 serge 15069
	if (crtc->active != crtc->base.state->active) {
3031 serge 15070
		struct intel_encoder *encoder;
2327 Serge 15071
 
3031 serge 15072
		/* This can happen either due to bugs in the get_hw_state
6084 serge 15073
		 * functions or because of calls to intel_crtc_disable_noatomic,
15074
		 * or because the pipe is force-enabled due to the
3031 serge 15075
		 * pipe A quirk. */
15076
		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15077
			      crtc->base.base.id,
6084 serge 15078
			      crtc->base.state->enable ? "enabled" : "disabled",
3031 serge 15079
			      crtc->active ? "enabled" : "disabled");
2327 Serge 15080
 
6084 serge 15081
		WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15082
		crtc->base.state->active = crtc->active;
3031 serge 15083
		crtc->base.enabled = crtc->active;
2327 Serge 15084
 
3031 serge 15085
		/* Because we only establish the connector -> encoder ->
15086
		 * crtc links if something is active, this means the
15087
		 * crtc is now deactivated. Break the links. connector
15088
		 * -> encoder links are only establish when things are
15089
		 *  actually up, hence no need to break them. */
15090
		WARN_ON(crtc->active);
2327 Serge 15091
 
6084 serge 15092
		for_each_encoder_on_crtc(dev, &crtc->base, encoder)
3031 serge 15093
			encoder->base.crtc = NULL;
15094
	}
5060 serge 15095
 
5354 serge 15096
	if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
5060 serge 15097
		/*
15098
		 * We start out with underrun reporting disabled to avoid races.
15099
		 * For correct bookkeeping mark this on active crtcs.
15100
		 *
15101
		 * Also on gmch platforms we dont have any hardware bits to
15102
		 * disable the underrun reporting. Which means we need to start
15103
		 * out with underrun reporting disabled also on inactive pipes,
15104
		 * since otherwise we'll complain about the garbage we read when
15105
		 * e.g. coming up after runtime pm.
15106
		 *
15107
		 * No protection against concurrent access is required - at
15108
		 * worst a fifo underrun happens which also sets this to false.
15109
		 */
15110
		crtc->cpu_fifo_underrun_disabled = true;
15111
		crtc->pch_fifo_underrun_disabled = true;
15112
	}
2327 Serge 15113
}
15114
 
3031 serge 15115
static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327 Serge 15116
{
3031 serge 15117
	struct intel_connector *connector;
15118
	struct drm_device *dev = encoder->base.dev;
6084 serge 15119
	bool active = false;
2327 Serge 15120
 
3031 serge 15121
	/* We need to check both for a crtc link (meaning that the
15122
	 * encoder is active and trying to read from a pipe) and the
15123
	 * pipe itself being active. */
15124
	bool has_active_crtc = encoder->base.crtc &&
15125
		to_intel_crtc(encoder->base.crtc)->active;
2327 Serge 15126
 
6084 serge 15127
	for_each_intel_connector(dev, connector) {
15128
		if (connector->base.encoder != &encoder->base)
15129
			continue;
15130
 
15131
		active = true;
15132
		break;
15133
	}
15134
 
15135
	if (active && !has_active_crtc) {
3031 serge 15136
		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15137
			      encoder->base.base.id,
5060 serge 15138
			      encoder->base.name);
2327 Serge 15139
 
3031 serge 15140
		/* Connector is active, but has no active pipe. This is
15141
		 * fallout from our resume register restoring. Disable
15142
		 * the encoder manually again. */
15143
		if (encoder->base.crtc) {
15144
			DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15145
				      encoder->base.base.id,
5060 serge 15146
				      encoder->base.name);
3031 serge 15147
			encoder->disable(encoder);
5060 serge 15148
			if (encoder->post_disable)
15149
				encoder->post_disable(encoder);
3031 serge 15150
		}
5060 serge 15151
		encoder->base.crtc = NULL;
2327 Serge 15152
 
3031 serge 15153
		/* Inconsistent output/port/pipe state happens presumably due to
15154
		 * a bug in one of the get_hw_state functions. Or someplace else
15155
		 * in our code, like the register restore mess on resume. Clamp
15156
		 * things to off as a safer default. */
6084 serge 15157
		for_each_intel_connector(dev, connector) {
3031 serge 15158
			if (connector->encoder != encoder)
15159
				continue;
5060 serge 15160
			connector->base.dpms = DRM_MODE_DPMS_OFF;
15161
			connector->base.encoder = NULL;
3031 serge 15162
		}
15163
	}
15164
	/* Enabled encoders without active connectors will be fixed in
15165
	 * the crtc fixup. */
2327 Serge 15166
}
15167
 
5060 serge 15168
void i915_redisable_vga_power_on(struct drm_device *dev)
3746 Serge 15169
{
15170
	struct drm_i915_private *dev_priv = dev->dev_private;
15171
	u32 vga_reg = i915_vgacntrl_reg(dev);
15172
 
5060 serge 15173
	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15174
		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15175
		i915_disable_vga(dev);
15176
	}
15177
}
15178
 
15179
void i915_redisable_vga(struct drm_device *dev)
15180
{
15181
	struct drm_i915_private *dev_priv = dev->dev_private;
15182
 
4104 Serge 15183
	/* This function can be called both from intel_modeset_setup_hw_state or
15184
	 * at a very early point in our resume sequence, where the power well
15185
	 * structures are not yet restored. Since this function is at a very
15186
	 * paranoid "someone might have enabled VGA while we were not looking"
15187
	 * level, just check if the power well is enabled instead of trying to
15188
	 * follow the "don't touch the power well if we don't need it" policy
15189
	 * the rest of the driver uses. */
5354 serge 15190
	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
4104 Serge 15191
		return;
15192
 
5060 serge 15193
	i915_redisable_vga_power_on(dev);
3746 Serge 15194
}
15195
 
6084 serge 15196
static bool primary_get_hw_state(struct intel_plane *plane)
5060 serge 15197
{
6084 serge 15198
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5060 serge 15199
 
6084 serge 15200
	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15201
}
5060 serge 15202
 
6084 serge 15203
/* FIXME read out full plane state for all planes */
15204
static void readout_plane_state(struct intel_crtc *crtc)
15205
{
15206
	struct drm_plane *primary = crtc->base.primary;
15207
	struct intel_plane_state *plane_state =
15208
		to_intel_plane_state(primary->state);
15209
 
15210
	plane_state->visible =
15211
		primary_get_hw_state(to_intel_plane(primary));
15212
 
15213
	if (plane_state->visible)
15214
		crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
5060 serge 15215
}
15216
 
4104 Serge 15217
static void intel_modeset_readout_hw_state(struct drm_device *dev)
2332 Serge 15218
{
15219
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 15220
	enum pipe pipe;
15221
	struct intel_crtc *crtc;
15222
	struct intel_encoder *encoder;
15223
	struct intel_connector *connector;
4104 Serge 15224
	int i;
2327 Serge 15225
 
5060 serge 15226
	for_each_intel_crtc(dev, crtc) {
6084 serge 15227
		__drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15228
		memset(crtc->config, 0, sizeof(*crtc->config));
15229
		crtc->config->base.crtc = &crtc->base;
2327 Serge 15230
 
3746 Serge 15231
		crtc->active = dev_priv->display.get_pipe_config(crtc,
6084 serge 15232
								 crtc->config);
2327 Serge 15233
 
6084 serge 15234
		crtc->base.state->active = crtc->active;
3031 serge 15235
		crtc->base.enabled = crtc->active;
2330 Serge 15236
 
6084 serge 15237
		readout_plane_state(crtc);
15238
 
3031 serge 15239
		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15240
			      crtc->base.base.id,
15241
			      crtc->active ? "enabled" : "disabled");
2339 Serge 15242
	}
2332 Serge 15243
 
4104 Serge 15244
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15245
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15246
 
5354 serge 15247
		pll->on = pll->get_hw_state(dev_priv, pll,
15248
					    &pll->config.hw_state);
4104 Serge 15249
		pll->active = 0;
5354 serge 15250
		pll->config.crtc_mask = 0;
5060 serge 15251
		for_each_intel_crtc(dev, crtc) {
5354 serge 15252
			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
4104 Serge 15253
				pll->active++;
5354 serge 15254
				pll->config.crtc_mask |= 1 << crtc->pipe;
15255
			}
4104 Serge 15256
		}
15257
 
5354 serge 15258
		DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15259
			      pll->name, pll->config.crtc_mask, pll->on);
5060 serge 15260
 
5354 serge 15261
		if (pll->config.crtc_mask)
5060 serge 15262
			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
4104 Serge 15263
	}
15264
 
5354 serge 15265
	for_each_intel_encoder(dev, encoder) {
3031 serge 15266
		pipe = 0;
2332 Serge 15267
 
3031 serge 15268
		if (encoder->get_hw_state(encoder, &pipe)) {
4104 Serge 15269
			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15270
			encoder->base.crtc = &crtc->base;
6084 serge 15271
			encoder->get_config(encoder, crtc->config);
3031 serge 15272
		} else {
15273
			encoder->base.crtc = NULL;
15274
		}
2332 Serge 15275
 
4560 Serge 15276
		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
3031 serge 15277
			      encoder->base.base.id,
5060 serge 15278
			      encoder->base.name,
3031 serge 15279
			      encoder->base.crtc ? "enabled" : "disabled",
4560 Serge 15280
			      pipe_name(pipe));
3031 serge 15281
	}
2332 Serge 15282
 
6084 serge 15283
	for_each_intel_connector(dev, connector) {
3031 serge 15284
		if (connector->get_hw_state(connector)) {
15285
			connector->base.dpms = DRM_MODE_DPMS_ON;
15286
			connector->base.encoder = &connector->encoder->base;
15287
		} else {
15288
			connector->base.dpms = DRM_MODE_DPMS_OFF;
15289
			connector->base.encoder = NULL;
15290
		}
15291
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15292
			      connector->base.base.id,
5060 serge 15293
			      connector->base.name,
3031 serge 15294
			      connector->base.encoder ? "enabled" : "disabled");
2332 Serge 15295
	}
6084 serge 15296
 
15297
	for_each_intel_crtc(dev, crtc) {
15298
		crtc->base.hwmode = crtc->config->base.adjusted_mode;
15299
 
15300
		memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15301
		if (crtc->base.state->active) {
15302
			intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15303
			intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15304
			WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15305
 
15306
			/*
15307
			 * The initial mode needs to be set in order to keep
15308
			 * the atomic core happy. It wants a valid mode if the
15309
			 * crtc's enabled, so we do the above call.
15310
			 *
15311
			 * At this point some state updated by the connectors
15312
			 * in their ->detect() callback has not run yet, so
15313
			 * no recalculation can be done yet.
15314
			 *
15315
			 * Even if we could do a recalculation and modeset
15316
			 * right now it would cause a double modeset if
15317
			 * fbdev or userspace chooses a different initial mode.
15318
			 *
15319
			 * If that happens, someone indicated they wanted a
15320
			 * mode change, which means it's safe to do a full
15321
			 * recalculation.
15322
			 */
15323
			crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15324
 
15325
			drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15326
			update_scanline_offset(crtc);
15327
		}
15328
	}
4104 Serge 15329
}
2332 Serge 15330
 
6084 serge 15331
/* Scan out the current hw modeset state,
15332
 * and sanitizes it to the current state
15333
 */
15334
static void
15335
intel_modeset_setup_hw_state(struct drm_device *dev)
4104 Serge 15336
{
15337
	struct drm_i915_private *dev_priv = dev->dev_private;
15338
	enum pipe pipe;
15339
	struct intel_crtc *crtc;
15340
	struct intel_encoder *encoder;
15341
	int i;
15342
 
15343
	intel_modeset_readout_hw_state(dev);
15344
 
3031 serge 15345
	/* HW state is read out, now we need to sanitize this mess. */
5354 serge 15346
	for_each_intel_encoder(dev, encoder) {
3031 serge 15347
		intel_sanitize_encoder(encoder);
2332 Serge 15348
	}
15349
 
5354 serge 15350
	for_each_pipe(dev_priv, pipe) {
3031 serge 15351
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15352
		intel_sanitize_crtc(crtc);
6084 serge 15353
		intel_dump_pipe_config(crtc, crtc->config,
15354
				       "[setup_hw_state]");
2332 Serge 15355
	}
15356
 
6084 serge 15357
	intel_modeset_update_connector_atomic_state(dev);
15358
 
4104 Serge 15359
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15360
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15361
 
15362
		if (!pll->on || pll->active)
15363
			continue;
15364
 
15365
		DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15366
 
15367
		pll->disable(dev_priv, pll);
15368
		pll->on = false;
15369
	}
15370
 
6084 serge 15371
	if (IS_VALLEYVIEW(dev))
15372
		vlv_wm_get_hw_state(dev);
15373
	else if (IS_GEN9(dev))
5354 serge 15374
		skl_wm_get_hw_state(dev);
15375
	else if (HAS_PCH_SPLIT(dev))
4560 Serge 15376
		ilk_wm_get_hw_state(dev);
15377
 
6084 serge 15378
	for_each_intel_crtc(dev, crtc) {
15379
		unsigned long put_domains;
4560 Serge 15380
 
6084 serge 15381
		put_domains = modeset_get_crtc_power_domains(&crtc->base);
15382
		if (WARN_ON(put_domains))
15383
			modeset_put_power_domains(dev_priv, put_domains);
15384
	}
15385
	intel_display_set_init_power(dev_priv, false);
15386
}
3746 Serge 15387
 
6084 serge 15388
void intel_display_resume(struct drm_device *dev)
15389
{
15390
	struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15391
	struct intel_connector *conn;
15392
	struct intel_plane *plane;
15393
	struct drm_crtc *crtc;
15394
	int ret;
15395
 
15396
	if (!state)
15397
		return;
15398
 
15399
	state->acquire_ctx = dev->mode_config.acquire_ctx;
15400
 
15401
	/* preserve complete old state, including dpll */
15402
	intel_atomic_get_shared_dpll_state(state);
15403
 
15404
	for_each_crtc(dev, crtc) {
15405
		struct drm_crtc_state *crtc_state =
15406
			drm_atomic_get_crtc_state(state, crtc);
15407
 
15408
		ret = PTR_ERR_OR_ZERO(crtc_state);
15409
		if (ret)
15410
			goto err;
15411
 
15412
		/* force a restore */
15413
		crtc_state->mode_changed = true;
3243 Serge 15414
	}
2332 Serge 15415
 
6084 serge 15416
	for_each_intel_plane(dev, plane) {
15417
		ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15418
		if (ret)
15419
			goto err;
15420
	}
15421
 
15422
	for_each_intel_connector(dev, conn) {
15423
		ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15424
		if (ret)
15425
			goto err;
15426
	}
15427
 
15428
	intel_modeset_setup_hw_state(dev);
15429
 
15430
	i915_redisable_vga(dev);
15431
	ret = drm_atomic_commit(state);
15432
	if (!ret)
15433
		return;
15434
 
15435
err:
15436
	DRM_ERROR("Restoring old state failed with %i\n", ret);
15437
	drm_atomic_state_free(state);
2332 Serge 15438
}
15439
 
3031 serge 15440
void intel_modeset_gem_init(struct drm_device *dev)
2330 Serge 15441
{
5060 serge 15442
	struct drm_crtc *c;
15443
	struct drm_i915_gem_object *obj;
6084 serge 15444
	int ret;
5060 serge 15445
 
15446
	mutex_lock(&dev->struct_mutex);
15447
	intel_init_gt_powersave(dev);
15448
	mutex_unlock(&dev->struct_mutex);
15449
 
3031 serge 15450
	intel_modeset_init_hw(dev);
2330 Serge 15451
 
3031 serge 15452
//   intel_setup_overlay(dev);
2330 Serge 15453
 
5060 serge 15454
	/*
15455
	 * Make sure any fbs we allocated at startup are properly
15456
	 * pinned & fenced.  When we do the allocation it's too early
15457
	 * for this.
15458
	 */
15459
	for_each_crtc(dev, c) {
15460
		obj = intel_fb_obj(c->primary->fb);
15461
		if (obj == NULL)
15462
			continue;
15463
 
6084 serge 15464
		mutex_lock(&dev->struct_mutex);
15465
		ret = intel_pin_and_fence_fb_obj(c->primary,
15466
						 c->primary->fb,
15467
						 c->primary->state,
15468
						 NULL, NULL);
15469
		mutex_unlock(&dev->struct_mutex);
15470
		if (ret) {
5060 serge 15471
			DRM_ERROR("failed to pin boot fb on pipe %d\n",
15472
				  to_intel_crtc(c)->pipe);
15473
			drm_framebuffer_unreference(c->primary->fb);
15474
			c->primary->fb = NULL;
6084 serge 15475
			c->primary->crtc = c->primary->state->crtc = NULL;
15476
			update_state_fb(c->primary);
15477
			c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
5060 serge 15478
		}
15479
	}
6084 serge 15480
 
15481
	intel_backlight_register(dev);
2330 Serge 15482
}
15483
 
5060 serge 15484
void intel_connector_unregister(struct intel_connector *intel_connector)
15485
{
15486
	struct drm_connector *connector = &intel_connector->base;
15487
 
15488
	intel_panel_destroy_backlight(connector);
15489
	drm_connector_unregister(connector);
15490
}
15491
 
3031 serge 15492
void intel_modeset_cleanup(struct drm_device *dev)
2327 Serge 15493
{
3031 serge 15494
#if 0
15495
	struct drm_i915_private *dev_priv = dev->dev_private;
4560 Serge 15496
	struct drm_connector *connector;
2327 Serge 15497
 
5354 serge 15498
	intel_disable_gt_powersave(dev);
15499
 
15500
	intel_backlight_unregister(dev);
15501
 
4104 Serge 15502
	/*
15503
	 * Interrupts and polling as the first thing to avoid creating havoc.
5354 serge 15504
	 * Too much stuff here (turning of connectors, ...) would
4104 Serge 15505
	 * experience fancy races otherwise.
15506
	 */
5354 serge 15507
	intel_irq_uninstall(dev_priv);
5060 serge 15508
 
4104 Serge 15509
	/*
15510
	 * Due to the hpd irq storm handling the hotplug work can re-arm the
15511
	 * poll handlers. Hence disable polling after hpd handling is shut down.
15512
	 */
4560 Serge 15513
	drm_kms_helper_poll_fini(dev);
4104 Serge 15514
 
4560 Serge 15515
	intel_unregister_dsm_handler();
2327 Serge 15516
 
6084 serge 15517
	intel_fbc_disable(dev_priv);
2342 Serge 15518
 
4104 Serge 15519
	/* flush any delayed tasks or pending work */
15520
	flush_scheduled_work();
2327 Serge 15521
 
4560 Serge 15522
	/* destroy the backlight and sysfs files before encoders/connectors */
15523
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5060 serge 15524
		struct intel_connector *intel_connector;
15525
 
15526
		intel_connector = to_intel_connector(connector);
15527
		intel_connector->unregister(intel_connector);
4560 Serge 15528
	}
2327 Serge 15529
 
3031 serge 15530
	drm_mode_config_cleanup(dev);
5060 serge 15531
 
15532
	intel_cleanup_overlay(dev);
15533
 
15534
	mutex_lock(&dev->struct_mutex);
15535
	intel_cleanup_gt_powersave(dev);
15536
	mutex_unlock(&dev->struct_mutex);
2327 Serge 15537
#endif
15538
}
15539
 
15540
/*
3031 serge 15541
 * Return which encoder is currently attached for connector.
2327 Serge 15542
 */
3031 serge 15543
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
2327 Serge 15544
{
3031 serge 15545
	return &intel_attached_encoder(connector)->base;
15546
}
2327 Serge 15547
 
3031 serge 15548
void intel_connector_attach_encoder(struct intel_connector *connector,
15549
				    struct intel_encoder *encoder)
15550
{
15551
	connector->encoder = encoder;
15552
	drm_mode_connector_attach_encoder(&connector->base,
15553
					  &encoder->base);
2327 Serge 15554
}
15555
 
15556
/*
3031 serge 15557
 * set vga decode state - true == enable VGA decode
2327 Serge 15558
 */
3031 serge 15559
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327 Serge 15560
{
2330 Serge 15561
	struct drm_i915_private *dev_priv = dev->dev_private;
4539 Serge 15562
	unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
3031 serge 15563
	u16 gmch_ctrl;
2327 Serge 15564
 
5060 serge 15565
	if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15566
		DRM_ERROR("failed to read control word\n");
15567
		return -EIO;
15568
	}
15569
 
15570
	if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15571
		return 0;
15572
 
3031 serge 15573
	if (state)
15574
		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330 Serge 15575
	else
3031 serge 15576
		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5060 serge 15577
 
15578
	if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15579
		DRM_ERROR("failed to write control word\n");
15580
		return -EIO;
15581
	}
15582
 
3031 serge 15583
	return 0;
2330 Serge 15584
}
15585
 
3031 serge 15586
#ifdef CONFIG_DEBUG_FS
2327 Serge 15587
 
3031 serge 15588
struct intel_display_error_state {
4104 Serge 15589
 
15590
	u32 power_well_driver;
15591
 
15592
	int num_transcoders;
15593
 
3031 serge 15594
	struct intel_cursor_error_state {
15595
		u32 control;
15596
		u32 position;
15597
		u32 base;
15598
		u32 size;
15599
	} cursor[I915_MAX_PIPES];
2327 Serge 15600
 
3031 serge 15601
	struct intel_pipe_error_state {
4560 Serge 15602
		bool power_domain_on;
3031 serge 15603
		u32 source;
5060 serge 15604
		u32 stat;
3031 serge 15605
	} pipe[I915_MAX_PIPES];
2327 Serge 15606
 
3031 serge 15607
	struct intel_plane_error_state {
15608
		u32 control;
15609
		u32 stride;
15610
		u32 size;
15611
		u32 pos;
15612
		u32 addr;
15613
		u32 surface;
15614
		u32 tile_offset;
15615
	} plane[I915_MAX_PIPES];
4104 Serge 15616
 
15617
	struct intel_transcoder_error_state {
4560 Serge 15618
		bool power_domain_on;
4104 Serge 15619
		enum transcoder cpu_transcoder;
15620
 
15621
		u32 conf;
15622
 
15623
		u32 htotal;
15624
		u32 hblank;
15625
		u32 hsync;
15626
		u32 vtotal;
15627
		u32 vblank;
15628
		u32 vsync;
15629
	} transcoder[4];
3031 serge 15630
};
2327 Serge 15631
 
3031 serge 15632
struct intel_display_error_state *
15633
intel_display_capture_error_state(struct drm_device *dev)
15634
{
5060 serge 15635
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 15636
	struct intel_display_error_state *error;
4104 Serge 15637
	int transcoders[] = {
15638
		TRANSCODER_A,
15639
		TRANSCODER_B,
15640
		TRANSCODER_C,
15641
		TRANSCODER_EDP,
15642
	};
3031 serge 15643
	int i;
2327 Serge 15644
 
4104 Serge 15645
	if (INTEL_INFO(dev)->num_pipes == 0)
15646
		return NULL;
15647
 
4560 Serge 15648
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
3031 serge 15649
	if (error == NULL)
15650
		return NULL;
2327 Serge 15651
 
4560 Serge 15652
	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4104 Serge 15653
		error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15654
 
5354 serge 15655
	for_each_pipe(dev_priv, i) {
4560 Serge 15656
		error->pipe[i].power_domain_on =
5354 serge 15657
			__intel_display_power_is_enabled(dev_priv,
6084 serge 15658
							 POWER_DOMAIN_PIPE(i));
4560 Serge 15659
		if (!error->pipe[i].power_domain_on)
15660
			continue;
15661
 
3031 serge 15662
		error->cursor[i].control = I915_READ(CURCNTR(i));
15663
		error->cursor[i].position = I915_READ(CURPOS(i));
15664
		error->cursor[i].base = I915_READ(CURBASE(i));
2327 Serge 15665
 
3031 serge 15666
		error->plane[i].control = I915_READ(DSPCNTR(i));
15667
		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
3746 Serge 15668
		if (INTEL_INFO(dev)->gen <= 3) {
6084 serge 15669
			error->plane[i].size = I915_READ(DSPSIZE(i));
15670
			error->plane[i].pos = I915_READ(DSPPOS(i));
3746 Serge 15671
		}
15672
		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
6084 serge 15673
			error->plane[i].addr = I915_READ(DSPADDR(i));
3031 serge 15674
		if (INTEL_INFO(dev)->gen >= 4) {
15675
			error->plane[i].surface = I915_READ(DSPSURF(i));
15676
			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15677
		}
2327 Serge 15678
 
3031 serge 15679
		error->pipe[i].source = I915_READ(PIPESRC(i));
5060 serge 15680
 
15681
		if (HAS_GMCH_DISPLAY(dev))
15682
			error->pipe[i].stat = I915_READ(PIPESTAT(i));
3031 serge 15683
	}
2327 Serge 15684
 
4104 Serge 15685
	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15686
	if (HAS_DDI(dev_priv->dev))
15687
		error->num_transcoders++; /* Account for eDP. */
15688
 
15689
	for (i = 0; i < error->num_transcoders; i++) {
15690
		enum transcoder cpu_transcoder = transcoders[i];
15691
 
4560 Serge 15692
		error->transcoder[i].power_domain_on =
5354 serge 15693
			__intel_display_power_is_enabled(dev_priv,
4560 Serge 15694
				POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15695
		if (!error->transcoder[i].power_domain_on)
15696
			continue;
15697
 
4104 Serge 15698
		error->transcoder[i].cpu_transcoder = cpu_transcoder;
15699
 
15700
		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15701
		error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15702
		error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15703
		error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15704
		error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15705
		error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15706
		error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15707
	}
15708
 
3031 serge 15709
	return error;
2330 Serge 15710
}
2327 Serge 15711
 
4104 Serge 15712
#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15713
 
3031 serge 15714
void
4104 Serge 15715
intel_display_print_error_state(struct drm_i915_error_state_buf *m,
3031 serge 15716
				struct drm_device *dev,
15717
				struct intel_display_error_state *error)
2332 Serge 15718
{
5354 serge 15719
	struct drm_i915_private *dev_priv = dev->dev_private;
3031 serge 15720
	int i;
2330 Serge 15721
 
4104 Serge 15722
	if (!error)
15723
		return;
15724
 
15725
	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
4560 Serge 15726
	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4104 Serge 15727
		err_printf(m, "PWR_WELL_CTL2: %08x\n",
15728
			   error->power_well_driver);
5354 serge 15729
	for_each_pipe(dev_priv, i) {
4104 Serge 15730
		err_printf(m, "Pipe [%d]:\n", i);
4560 Serge 15731
		err_printf(m, "  Power: %s\n",
15732
			   error->pipe[i].power_domain_on ? "on" : "off");
4104 Serge 15733
		err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
5060 serge 15734
		err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
2332 Serge 15735
 
4104 Serge 15736
		err_printf(m, "Plane [%d]:\n", i);
15737
		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15738
		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
3746 Serge 15739
		if (INTEL_INFO(dev)->gen <= 3) {
4104 Serge 15740
			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15741
			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
3746 Serge 15742
		}
15743
		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
4104 Serge 15744
			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
3031 serge 15745
		if (INTEL_INFO(dev)->gen >= 4) {
4104 Serge 15746
			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15747
			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
3031 serge 15748
		}
2332 Serge 15749
 
4104 Serge 15750
		err_printf(m, "Cursor [%d]:\n", i);
15751
		err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15752
		err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15753
		err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
3031 serge 15754
	}
4104 Serge 15755
 
15756
	for (i = 0; i < error->num_transcoders; i++) {
4560 Serge 15757
		err_printf(m, "CPU transcoder: %c\n",
4104 Serge 15758
			   transcoder_name(error->transcoder[i].cpu_transcoder));
4560 Serge 15759
		err_printf(m, "  Power: %s\n",
15760
			   error->transcoder[i].power_domain_on ? "on" : "off");
4104 Serge 15761
		err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15762
		err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15763
		err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15764
		err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15765
		err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15766
		err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15767
		err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15768
	}
2327 Serge 15769
}
3031 serge 15770
#endif
5354 serge 15771
 
15772
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15773
{
15774
	struct intel_crtc *crtc;
15775
 
15776
	for_each_intel_crtc(dev, crtc) {
15777
		struct intel_unpin_work *work;
15778
 
15779
		spin_lock_irq(&dev->event_lock);
15780
 
15781
		work = crtc->unpin_work;
15782
 
15783
		if (work && work->event &&
15784
		    work->event->base.file_priv == file) {
15785
			kfree(work->event);
15786
			work->event = NULL;
15787
		}
15788
 
15789
		spin_unlock_irq(&dev->event_lock);
15790
	}
15791
}