WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
3746	Serge	27	//#include
2327	Serge	28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
3746	Serge	33	#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
3031	serge	40	#include
		41	#include
5060	serge	42	#include
		43	#include
		44	#include
2327	Serge	45
5060	serge	46	static inline void ndelay(unsigned long x)
		47	{
		48	udelay(DIV_ROUND_UP(x, 1000));
		49	}
		50
		51	/* Primary plane formats supported by all gen */
		52	#define COMMON_PRIMARY_FORMATS \
		53	DRM_FORMAT_C8, \
		54	DRM_FORMAT_RGB565, \
		55	DRM_FORMAT_XRGB8888, \
		56	DRM_FORMAT_ARGB8888
		57
		58	/* Primary plane formats for gen <= 3 */
		59	static const uint32_t intel_primary_formats_gen2[] = {
		60	COMMON_PRIMARY_FORMATS,
		61	DRM_FORMAT_XRGB1555,
		62	DRM_FORMAT_ARGB1555,
		63	};
		64
		65	/* Primary plane formats for gen >= 4 */
		66	static const uint32_t intel_primary_formats_gen4[] = {
		67	COMMON_PRIMARY_FORMATS, \
		68	DRM_FORMAT_XBGR8888,
		69	DRM_FORMAT_ABGR8888,
		70	DRM_FORMAT_XRGB2101010,
		71	DRM_FORMAT_ARGB2101010,
		72	DRM_FORMAT_XBGR2101010,
		73	DRM_FORMAT_ABGR2101010,
		74	};
		75
		76	/* Cursor formats */
		77	static const uint32_t intel_cursor_formats[] = {
		78	DRM_FORMAT_ARGB8888,
		79	};
		80
		81	#define DIV_ROUND_CLOSEST_ULL(ll, d) \
		82	({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
		83
4104	Serge	84	#define MAX_ERRNO 4095
2327	Serge	85	phys_addr_t get_bus_addr(void);
		86
4560	Serge	87	static inline void outb(u8 v, u16 port)
		88	{
		89	asm volatile("outb %0,%1" : : "a" (v), "dN" (port));
		90	}
		91	static inline u8 inb(u16 port)
		92	{
		93	u8 v;
		94	asm volatile("inb %1,%0" : "=a" (v) : "dN" (port));
		95	return v;
		96	}
		97
5060	serge	98	static void intel_increase_pllclock(struct drm_device *dev,
		99	enum pipe pipe);
		100	void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	101
4104	Serge	102	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		103	struct intel_crtc_config *pipe_config);
4560	Serge	104	static void ironlake_pch_clock_get(struct intel_crtc *crtc,
4104	Serge	105	struct intel_crtc_config *pipe_config);
2327	Serge	106
4104	Serge	107	static int intel_set_mode(struct drm_crtc crtc, struct drm_display_mode mode,
		108	int x, int y, struct drm_framebuffer *old_fb);
5060	serge	109	static int intel_framebuffer_init(struct drm_device *dev,
		110	struct intel_framebuffer *ifb,
		111	struct drm_mode_fb_cmd2 *mode_cmd,
		112	struct drm_i915_gem_object *obj);
		113	static void intel_dp_set_m_n(struct intel_crtc *crtc);
		114	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
		115	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
		116	static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
		117	struct intel_link_m_n *m_n);
		118	static void ironlake_set_pipeconf(struct drm_crtc *crtc);
		119	static void haswell_set_pipeconf(struct drm_crtc *crtc);
		120	static void intel_set_pipe_csc(struct drm_crtc *crtc);
		121	static void vlv_prepare_pll(struct intel_crtc *crtc);
4104	Serge	122
5060	serge	123	static struct intel_encoder intel_find_encoder(struct intel_connector connector, int pipe)
		124	{
		125	if (!connector->mst_port)
		126	return connector->encoder;
		127	else
		128	return &connector->mst_port->mst_encoders[pipe]->base;
		129	}
4104	Serge	130
2327	Serge	131	typedef struct {
		132	int min, max;
		133	} intel_range_t;
		134
		135	typedef struct {
		136	int dot_limit;
		137	int p2_slow, p2_fast;
		138	} intel_p2_t;
		139
		140	typedef struct intel_limit intel_limit_t;
		141	struct intel_limit {
		142	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		143	intel_p2_t p2;
		144	};
		145
3243	Serge	146	int
		147	intel_pch_rawclk(struct drm_device *dev)
		148	{
		149	struct drm_i915_private *dev_priv = dev->dev_private;
		150
		151	WARN_ON(!HAS_PCH_SPLIT(dev));
		152
		153	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
		154	}
		155
2327	Serge	156	static inline u32 /* units of 100MHz */
		157	intel_fdi_link_freq(struct drm_device *dev)
		158	{
		159	if (IS_GEN5(dev)) {
		160	struct drm_i915_private *dev_priv = dev->dev_private;
		161	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		162	} else
		163	return 27;
		164	}
		165
4104	Serge	166	static const intel_limit_t intel_limits_i8xx_dac = {
		167	.dot = { .min = 25000, .max = 350000 },
4560	Serge	168	.vco = { .min = 908000, .max = 1512000 },
		169	.n = { .min = 2, .max = 16 },
4104	Serge	170	.m = { .min = 96, .max = 140 },
		171	.m1 = { .min = 18, .max = 26 },
		172	.m2 = { .min = 6, .max = 16 },
		173	.p = { .min = 4, .max = 128 },
		174	.p1 = { .min = 2, .max = 33 },
		175	.p2 = { .dot_limit = 165000,
		176	.p2_slow = 4, .p2_fast = 2 },
		177	};
		178
2327	Serge	179	static const intel_limit_t intel_limits_i8xx_dvo = {
		180	.dot = { .min = 25000, .max = 350000 },
4560	Serge	181	.vco = { .min = 908000, .max = 1512000 },
		182	.n = { .min = 2, .max = 16 },
2327	Serge	183	.m = { .min = 96, .max = 140 },
		184	.m1 = { .min = 18, .max = 26 },
		185	.m2 = { .min = 6, .max = 16 },
		186	.p = { .min = 4, .max = 128 },
		187	.p1 = { .min = 2, .max = 33 },
		188	.p2 = { .dot_limit = 165000,
4104	Serge	189	.p2_slow = 4, .p2_fast = 4 },
2327	Serge	190	};
		191
		192	static const intel_limit_t intel_limits_i8xx_lvds = {
		193	.dot = { .min = 25000, .max = 350000 },
4560	Serge	194	.vco = { .min = 908000, .max = 1512000 },
		195	.n = { .min = 2, .max = 16 },
2327	Serge	196	.m = { .min = 96, .max = 140 },
		197	.m1 = { .min = 18, .max = 26 },
		198	.m2 = { .min = 6, .max = 16 },
		199	.p = { .min = 4, .max = 128 },
		200	.p1 = { .min = 1, .max = 6 },
		201	.p2 = { .dot_limit = 165000,
		202	.p2_slow = 14, .p2_fast = 7 },
		203	};
		204
		205	static const intel_limit_t intel_limits_i9xx_sdvo = {
		206	.dot = { .min = 20000, .max = 400000 },
		207	.vco = { .min = 1400000, .max = 2800000 },
		208	.n = { .min = 1, .max = 6 },
		209	.m = { .min = 70, .max = 120 },
3480	Serge	210	.m1 = { .min = 8, .max = 18 },
		211	.m2 = { .min = 3, .max = 7 },
2327	Serge	212	.p = { .min = 5, .max = 80 },
		213	.p1 = { .min = 1, .max = 8 },
		214	.p2 = { .dot_limit = 200000,
		215	.p2_slow = 10, .p2_fast = 5 },
		216	};
		217
		218	static const intel_limit_t intel_limits_i9xx_lvds = {
		219	.dot = { .min = 20000, .max = 400000 },
		220	.vco = { .min = 1400000, .max = 2800000 },
		221	.n = { .min = 1, .max = 6 },
		222	.m = { .min = 70, .max = 120 },
3480	Serge	223	.m1 = { .min = 8, .max = 18 },
		224	.m2 = { .min = 3, .max = 7 },
2327	Serge	225	.p = { .min = 7, .max = 98 },
		226	.p1 = { .min = 1, .max = 8 },
		227	.p2 = { .dot_limit = 112000,
		228	.p2_slow = 14, .p2_fast = 7 },
		229	};
		230
		231
		232	static const intel_limit_t intel_limits_g4x_sdvo = {
		233	.dot = { .min = 25000, .max = 270000 },
		234	.vco = { .min = 1750000, .max = 3500000},
		235	.n = { .min = 1, .max = 4 },
		236	.m = { .min = 104, .max = 138 },
		237	.m1 = { .min = 17, .max = 23 },
		238	.m2 = { .min = 5, .max = 11 },
		239	.p = { .min = 10, .max = 30 },
		240	.p1 = { .min = 1, .max = 3},
		241	.p2 = { .dot_limit = 270000,
		242	.p2_slow = 10,
		243	.p2_fast = 10
		244	},
		245	};
		246
		247	static const intel_limit_t intel_limits_g4x_hdmi = {
		248	.dot = { .min = 22000, .max = 400000 },
		249	.vco = { .min = 1750000, .max = 3500000},
		250	.n = { .min = 1, .max = 4 },
		251	.m = { .min = 104, .max = 138 },
		252	.m1 = { .min = 16, .max = 23 },
		253	.m2 = { .min = 5, .max = 11 },
		254	.p = { .min = 5, .max = 80 },
		255	.p1 = { .min = 1, .max = 8},
		256	.p2 = { .dot_limit = 165000,
		257	.p2_slow = 10, .p2_fast = 5 },
		258	};
		259
		260	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		261	.dot = { .min = 20000, .max = 115000 },
		262	.vco = { .min = 1750000, .max = 3500000 },
		263	.n = { .min = 1, .max = 3 },
		264	.m = { .min = 104, .max = 138 },
		265	.m1 = { .min = 17, .max = 23 },
		266	.m2 = { .min = 5, .max = 11 },
		267	.p = { .min = 28, .max = 112 },
		268	.p1 = { .min = 2, .max = 8 },
		269	.p2 = { .dot_limit = 0,
		270	.p2_slow = 14, .p2_fast = 14
		271	},
		272	};
		273
		274	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		275	.dot = { .min = 80000, .max = 224000 },
		276	.vco = { .min = 1750000, .max = 3500000 },
		277	.n = { .min = 1, .max = 3 },
		278	.m = { .min = 104, .max = 138 },
		279	.m1 = { .min = 17, .max = 23 },
		280	.m2 = { .min = 5, .max = 11 },
		281	.p = { .min = 14, .max = 42 },
		282	.p1 = { .min = 2, .max = 6 },
		283	.p2 = { .dot_limit = 0,
		284	.p2_slow = 7, .p2_fast = 7
		285	},
		286	};
		287
		288	static const intel_limit_t intel_limits_pineview_sdvo = {
		289	.dot = { .min = 20000, .max = 400000},
		290	.vco = { .min = 1700000, .max = 3500000 },
		291	/* Pineview's Ncounter is a ring counter */
		292	.n = { .min = 3, .max = 6 },
		293	.m = { .min = 2, .max = 256 },
		294	/* Pineview only has one combined m divider, which we treat as m2. */
		295	.m1 = { .min = 0, .max = 0 },
		296	.m2 = { .min = 0, .max = 254 },
		297	.p = { .min = 5, .max = 80 },
		298	.p1 = { .min = 1, .max = 8 },
		299	.p2 = { .dot_limit = 200000,
		300	.p2_slow = 10, .p2_fast = 5 },
		301	};
		302
		303	static const intel_limit_t intel_limits_pineview_lvds = {
		304	.dot = { .min = 20000, .max = 400000 },
		305	.vco = { .min = 1700000, .max = 3500000 },
		306	.n = { .min = 3, .max = 6 },
		307	.m = { .min = 2, .max = 256 },
		308	.m1 = { .min = 0, .max = 0 },
		309	.m2 = { .min = 0, .max = 254 },
		310	.p = { .min = 7, .max = 112 },
		311	.p1 = { .min = 1, .max = 8 },
		312	.p2 = { .dot_limit = 112000,
		313	.p2_slow = 14, .p2_fast = 14 },
		314	};
		315
		316	/* Ironlake / Sandybridge
		317	*
		318	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		319	* the range value for them is (actual_value - 2).
		320	*/
		321	static const intel_limit_t intel_limits_ironlake_dac = {
		322	.dot = { .min = 25000, .max = 350000 },
		323	.vco = { .min = 1760000, .max = 3510000 },
		324	.n = { .min = 1, .max = 5 },
		325	.m = { .min = 79, .max = 127 },
		326	.m1 = { .min = 12, .max = 22 },
		327	.m2 = { .min = 5, .max = 9 },
		328	.p = { .min = 5, .max = 80 },
		329	.p1 = { .min = 1, .max = 8 },
		330	.p2 = { .dot_limit = 225000,
		331	.p2_slow = 10, .p2_fast = 5 },
		332	};
		333
		334	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		335	.dot = { .min = 25000, .max = 350000 },
		336	.vco = { .min = 1760000, .max = 3510000 },
		337	.n = { .min = 1, .max = 3 },
		338	.m = { .min = 79, .max = 118 },
		339	.m1 = { .min = 12, .max = 22 },
		340	.m2 = { .min = 5, .max = 9 },
		341	.p = { .min = 28, .max = 112 },
		342	.p1 = { .min = 2, .max = 8 },
		343	.p2 = { .dot_limit = 225000,
		344	.p2_slow = 14, .p2_fast = 14 },
		345	};
		346
		347	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		348	.dot = { .min = 25000, .max = 350000 },
		349	.vco = { .min = 1760000, .max = 3510000 },
		350	.n = { .min = 1, .max = 3 },
		351	.m = { .min = 79, .max = 127 },
		352	.m1 = { .min = 12, .max = 22 },
		353	.m2 = { .min = 5, .max = 9 },
		354	.p = { .min = 14, .max = 56 },
		355	.p1 = { .min = 2, .max = 8 },
		356	.p2 = { .dot_limit = 225000,
		357	.p2_slow = 7, .p2_fast = 7 },
		358	};
		359
		360	/* LVDS 100mhz refclk limits. */
		361	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		362	.dot = { .min = 25000, .max = 350000 },
		363	.vco = { .min = 1760000, .max = 3510000 },
		364	.n = { .min = 1, .max = 2 },
		365	.m = { .min = 79, .max = 126 },
		366	.m1 = { .min = 12, .max = 22 },
		367	.m2 = { .min = 5, .max = 9 },
		368	.p = { .min = 28, .max = 112 },
2342	Serge	369	.p1 = { .min = 2, .max = 8 },
2327	Serge	370	.p2 = { .dot_limit = 225000,
		371	.p2_slow = 14, .p2_fast = 14 },
		372	};
		373
		374	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		375	.dot = { .min = 25000, .max = 350000 },
		376	.vco = { .min = 1760000, .max = 3510000 },
		377	.n = { .min = 1, .max = 3 },
		378	.m = { .min = 79, .max = 126 },
		379	.m1 = { .min = 12, .max = 22 },
		380	.m2 = { .min = 5, .max = 9 },
		381	.p = { .min = 14, .max = 42 },
2342	Serge	382	.p1 = { .min = 2, .max = 6 },
2327	Serge	383	.p2 = { .dot_limit = 225000,
		384	.p2_slow = 7, .p2_fast = 7 },
		385	};
		386
4560	Serge	387	static const intel_limit_t intel_limits_vlv = {
		388	/*
		389	* These are the data rate limits (measured in fast clocks)
		390	* since those are the strictest limits we have. The fast
		391	* clock and actual rate limits are more relaxed, so checking
		392	* them would make no difference.
		393	*/
		394	.dot = { .min = 25000 * 5, .max = 270000 * 5 },
3031	serge	395	.vco = { .min = 4000000, .max = 6000000 },
		396	.n = { .min = 1, .max = 7 },
		397	.m1 = { .min = 2, .max = 3 },
		398	.m2 = { .min = 11, .max = 156 },
		399	.p1 = { .min = 2, .max = 3 },
4560	Serge	400	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
3031	serge	401	};
		402
5060	serge	403	static const intel_limit_t intel_limits_chv = {
		404	/*
		405	* These are the data rate limits (measured in fast clocks)
		406	* since those are the strictest limits we have. The fast
		407	* clock and actual rate limits are more relaxed, so checking
		408	* them would make no difference.
		409	*/
		410	.dot = { .min = 25000 * 5, .max = 540000 * 5},
		411	.vco = { .min = 4860000, .max = 6700000 },
		412	.n = { .min = 1, .max = 1 },
		413	.m1 = { .min = 2, .max = 2 },
		414	.m2 = { .min = 24 << 22, .max = 175 << 22 },
		415	.p1 = { .min = 2, .max = 4 },
		416	.p2 = { .p2_slow = 1, .p2_fast = 14 },
		417	};
		418
4560	Serge	419	static void vlv_clock(int refclk, intel_clock_t *clock)
		420	{
		421	clock->m = clock->m1 * clock->m2;
		422	clock->p = clock->p1 * clock->p2;
		423	if (WARN_ON(clock->n == 0 \|\| clock->p == 0))
		424	return;
		425	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
		426	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
		427	}
3031	serge	428
4560	Serge	429	/**
		430	* Returns whether any output on the specified pipe is of the specified type
		431	*/
		432	static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		433	{
		434	struct drm_device *dev = crtc->dev;
		435	struct intel_encoder *encoder;
		436
		437	for_each_encoder_on_crtc(dev, crtc, encoder)
		438	if (encoder->type == type)
		439	return true;
		440
		441	return false;
		442	}
		443
2327	Serge	444	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		445	int refclk)
		446	{
		447	struct drm_device *dev = crtc->dev;
		448	const intel_limit_t *limit;
		449
		450	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	451	if (intel_is_dual_link_lvds(dev)) {
2327	Serge	452	if (refclk == 100000)
		453	limit = &intel_limits_ironlake_dual_lvds_100m;
		454	else
		455	limit = &intel_limits_ironlake_dual_lvds;
		456	} else {
		457	if (refclk == 100000)
		458	limit = &intel_limits_ironlake_single_lvds_100m;
		459	else
		460	limit = &intel_limits_ironlake_single_lvds;
		461	}
4104	Serge	462	} else
2327	Serge	463	limit = &intel_limits_ironlake_dac;
		464
		465	return limit;
		466	}
		467
		468	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		469	{
		470	struct drm_device *dev = crtc->dev;
		471	const intel_limit_t *limit;
		472
		473	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	474	if (intel_is_dual_link_lvds(dev))
2327	Serge	475	limit = &intel_limits_g4x_dual_channel_lvds;
		476	else
		477	limit = &intel_limits_g4x_single_channel_lvds;
		478	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		479	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		480	limit = &intel_limits_g4x_hdmi;
		481	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		482	limit = &intel_limits_g4x_sdvo;
		483	} else /* The option is for other outputs */
		484	limit = &intel_limits_i9xx_sdvo;
		485
		486	return limit;
		487	}
		488
		489	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		490	{
		491	struct drm_device *dev = crtc->dev;
		492	const intel_limit_t *limit;
		493
		494	if (HAS_PCH_SPLIT(dev))
		495	limit = intel_ironlake_limit(crtc, refclk);
		496	else if (IS_G4X(dev)) {
		497	limit = intel_g4x_limit(crtc);
		498	} else if (IS_PINEVIEW(dev)) {
		499	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		500	limit = &intel_limits_pineview_lvds;
		501	else
		502	limit = &intel_limits_pineview_sdvo;
5060	serge	503	} else if (IS_CHERRYVIEW(dev)) {
		504	limit = &intel_limits_chv;
3031	serge	505	} else if (IS_VALLEYVIEW(dev)) {
4560	Serge	506	limit = &intel_limits_vlv;
2327	Serge	507	} else if (!IS_GEN2(dev)) {
		508	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		509	limit = &intel_limits_i9xx_lvds;
		510	else
		511	limit = &intel_limits_i9xx_sdvo;
		512	} else {
		513	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		514	limit = &intel_limits_i8xx_lvds;
4104	Serge	515	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
		516	limit = &intel_limits_i8xx_dvo;
2327	Serge	517	else
4104	Serge	518	limit = &intel_limits_i8xx_dac;
2327	Serge	519	}
		520	return limit;
		521	}
		522
		523	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		524	static void pineview_clock(int refclk, intel_clock_t *clock)
		525	{
		526	clock->m = clock->m2 + 2;
		527	clock->p = clock->p1 * clock->p2;
4560	Serge	528	if (WARN_ON(clock->n == 0 \|\| clock->p == 0))
		529	return;
		530	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
		531	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2327	Serge	532	}
		533
4104	Serge	534	static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
2327	Serge	535	{
4104	Serge	536	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
		537	}
		538
		539	static void i9xx_clock(int refclk, intel_clock_t *clock)
		540	{
		541	clock->m = i9xx_dpll_compute_m(clock);
2327	Serge	542	clock->p = clock->p1 * clock->p2;
4560	Serge	543	if (WARN_ON(clock->n + 2 == 0 \|\| clock->p == 0))
		544	return;
		545	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
		546	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2327	Serge	547	}
		548
5060	serge	549	static void chv_clock(int refclk, intel_clock_t *clock)
		550	{
		551	clock->m = clock->m1 * clock->m2;
		552	clock->p = clock->p1 * clock->p2;
		553	if (WARN_ON(clock->n == 0 \|\| clock->p == 0))
		554	return;
		555	clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
		556	clock->n << 22);
		557	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
		558	}
		559
2327	Serge	560	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		561	/**
		562	* Returns whether the given set of divisors are valid for a given refclk with
		563	* the given connectors.
		564	*/
		565
		566	static bool intel_PLL_is_valid(struct drm_device *dev,
		567	const intel_limit_t *limit,
		568	const intel_clock_t *clock)
		569	{
4560	Serge	570	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
		571	INTELPllInvalid("n out of range\n");
2327	Serge	572	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	573	INTELPllInvalid("p1 out of range\n");
2327	Serge	574	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	575	INTELPllInvalid("m2 out of range\n");
2327	Serge	576	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	577	INTELPllInvalid("m1 out of range\n");
4560	Serge	578
		579	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
		580	if (clock->m1 <= clock->m2)
2342	Serge	581	INTELPllInvalid("m1 <= m2\n");
4560	Serge	582
		583	if (!IS_VALLEYVIEW(dev)) {
		584	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
		585	INTELPllInvalid("p out of range\n");
2327	Serge	586	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
2342	Serge	587	INTELPllInvalid("m out of range\n");
4560	Serge	588	}
		589
2327	Serge	590	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	591	INTELPllInvalid("vco out of range\n");
2327	Serge	592	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		593	* connector, etc., rather than just a single range.
		594	*/
		595	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	596	INTELPllInvalid("dot out of range\n");
2327	Serge	597
		598	return true;
		599	}
		600
		601	static bool
4104	Serge	602	i9xx_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	603	int target, int refclk, intel_clock_t *match_clock,
		604	intel_clock_t *best_clock)
2327	Serge	605	{
		606	struct drm_device *dev = crtc->dev;
		607	intel_clock_t clock;
		608	int err = target;
		609
3480	Serge	610	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2327	Serge	611	/*
3480	Serge	612	* For LVDS just rely on its current settings for dual-channel.
		613	* We haven't figured out how to reliably set up different
		614	* single/dual channel state, if we even can.
2327	Serge	615	*/
3480	Serge	616	if (intel_is_dual_link_lvds(dev))
2327	Serge	617	clock.p2 = limit->p2.p2_fast;
		618	else
		619	clock.p2 = limit->p2.p2_slow;
		620	} else {
		621	if (target < limit->p2.dot_limit)
		622	clock.p2 = limit->p2.p2_slow;
		623	else
		624	clock.p2 = limit->p2.p2_fast;
		625	}
		626
2342	Serge	627	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	628
		629	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		630	clock.m1++) {
		631	for (clock.m2 = limit->m2.min;
		632	clock.m2 <= limit->m2.max; clock.m2++) {
4104	Serge	633	if (clock.m2 >= clock.m1)
2327	Serge	634	break;
		635	for (clock.n = limit->n.min;
		636	clock.n <= limit->n.max; clock.n++) {
		637	for (clock.p1 = limit->p1.min;
		638	clock.p1 <= limit->p1.max; clock.p1++) {
		639	int this_err;
		640
4104	Serge	641	i9xx_clock(refclk, &clock);
2327	Serge	642	if (!intel_PLL_is_valid(dev, limit,
		643	&clock))
		644	continue;
3031	serge	645	if (match_clock &&
		646	clock.p != match_clock->p)
		647	continue;
2327	Serge	648
		649	this_err = abs(clock.dot - target);
		650	if (this_err < err) {
		651	*best_clock = clock;
		652	err = this_err;
		653	}
		654	}
		655	}
		656	}
		657	}
		658
		659	return (err != target);
		660	}
		661
		662	static bool
4104	Serge	663	pnv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
		664	int target, int refclk, intel_clock_t *match_clock,
		665	intel_clock_t *best_clock)
		666	{
		667	struct drm_device *dev = crtc->dev;
		668	intel_clock_t clock;
		669	int err = target;
		670
		671	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		672	/*
		673	* For LVDS just rely on its current settings for dual-channel.
		674	* We haven't figured out how to reliably set up different
		675	* single/dual channel state, if we even can.
		676	*/
		677	if (intel_is_dual_link_lvds(dev))
		678	clock.p2 = limit->p2.p2_fast;
		679	else
		680	clock.p2 = limit->p2.p2_slow;
		681	} else {
		682	if (target < limit->p2.dot_limit)
		683	clock.p2 = limit->p2.p2_slow;
		684	else
		685	clock.p2 = limit->p2.p2_fast;
		686	}
		687
		688	memset(best_clock, 0, sizeof(*best_clock));
		689
		690	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		691	clock.m1++) {
		692	for (clock.m2 = limit->m2.min;
		693	clock.m2 <= limit->m2.max; clock.m2++) {
		694	for (clock.n = limit->n.min;
		695	clock.n <= limit->n.max; clock.n++) {
		696	for (clock.p1 = limit->p1.min;
		697	clock.p1 <= limit->p1.max; clock.p1++) {
		698	int this_err;
		699
		700	pineview_clock(refclk, &clock);
		701	if (!intel_PLL_is_valid(dev, limit,
		702	&clock))
		703	continue;
		704	if (match_clock &&
		705	clock.p != match_clock->p)
		706	continue;
		707
		708	this_err = abs(clock.dot - target);
		709	if (this_err < err) {
		710	*best_clock = clock;
		711	err = this_err;
		712	}
		713	}
		714	}
		715	}
		716	}
		717
		718	return (err != target);
		719	}
		720
		721	static bool
		722	g4x_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	723	int target, int refclk, intel_clock_t *match_clock,
		724	intel_clock_t *best_clock)
2327	Serge	725	{
		726	struct drm_device *dev = crtc->dev;
		727	intel_clock_t clock;
		728	int max_n;
		729	bool found;
		730	/* approximately equals target * 0.00585 */
		731	int err_most = (target >> 8) + (target >> 9);
		732	found = false;
		733
		734	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	735	if (intel_is_dual_link_lvds(dev))
2327	Serge	736	clock.p2 = limit->p2.p2_fast;
		737	else
		738	clock.p2 = limit->p2.p2_slow;
		739	} else {
		740	if (target < limit->p2.dot_limit)
		741	clock.p2 = limit->p2.p2_slow;
		742	else
		743	clock.p2 = limit->p2.p2_fast;
		744	}
		745
		746	memset(best_clock, 0, sizeof(*best_clock));
		747	max_n = limit->n.max;
		748	/* based on hardware requirement, prefer smaller n to precision */
		749	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		750	/* based on hardware requirement, prefere larger m1,m2 */
		751	for (clock.m1 = limit->m1.max;
		752	clock.m1 >= limit->m1.min; clock.m1--) {
		753	for (clock.m2 = limit->m2.max;
		754	clock.m2 >= limit->m2.min; clock.m2--) {
		755	for (clock.p1 = limit->p1.max;
		756	clock.p1 >= limit->p1.min; clock.p1--) {
		757	int this_err;
		758
4104	Serge	759	i9xx_clock(refclk, &clock);
2327	Serge	760	if (!intel_PLL_is_valid(dev, limit,
		761	&clock))
		762	continue;
		763
		764	this_err = abs(clock.dot - target);
		765	if (this_err < err_most) {
		766	*best_clock = clock;
		767	err_most = this_err;
		768	max_n = clock.n;
		769	found = true;
		770	}
		771	}
		772	}
		773	}
		774	}
		775	return found;
		776	}
		777
		778	static bool
4104	Serge	779	vlv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	780	int target, int refclk, intel_clock_t *match_clock,
		781	intel_clock_t *best_clock)
		782	{
4560	Serge	783	struct drm_device *dev = crtc->dev;
		784	intel_clock_t clock;
		785	unsigned int bestppm = 1000000;
		786	/* min update 19.2 MHz */
		787	int max_n = min(limit->n.max, refclk / 19200);
		788	bool found = false;
2327	Serge	789
4560	Serge	790	target = 5; / fast clock */
3031	serge	791
4560	Serge	792	memset(best_clock, 0, sizeof(*best_clock));
		793
3031	serge	794	/* based on hardware requirement, prefer smaller n to precision */
4560	Serge	795	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		796	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
		797	for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
		798	clock.p2 -= clock.p2 > 10 ? 2 : 1) {
		799	clock.p = clock.p1 * clock.p2;
3031	serge	800	/* based on hardware requirement, prefer bigger m1,m2 values */
4560	Serge	801	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
		802	unsigned int ppm, diff;
		803
		804	clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
		805	refclk * clock.m1);
		806
		807	vlv_clock(refclk, &clock);
		808
		809	if (!intel_PLL_is_valid(dev, limit,
		810	&clock))
		811	continue;
		812
		813	diff = abs(clock.dot - target);
		814	ppm = div_u64(1000000ULL * diff, target);
		815
		816	if (ppm < 100 && clock.p > best_clock->p) {
3031	serge	817	bestppm = 0;
4560	Serge	818	*best_clock = clock;
		819	found = true;
3031	serge	820	}
4560	Serge	821
		822	if (bestppm >= 10 && ppm < bestppm - 10) {
		823	bestppm = ppm;
		824	*best_clock = clock;
		825	found = true;
3031	serge	826	}
		827	}
		828	}
		829	}
		830	}
		831
4560	Serge	832	return found;
3031	serge	833	}
		834
5060	serge	835	static bool
		836	chv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
		837	int target, int refclk, intel_clock_t *match_clock,
		838	intel_clock_t *best_clock)
		839	{
		840	struct drm_device *dev = crtc->dev;
		841	intel_clock_t clock;
		842	uint64_t m2;
		843	int found = false;
		844
		845	memset(best_clock, 0, sizeof(*best_clock));
		846
		847	/*
		848	* Based on hardware doc, the n always set to 1, and m1 always
		849	* set to 2. If requires to support 200Mhz refclk, we need to
		850	* revisit this because n may not 1 anymore.
		851	*/
		852	clock.n = 1, clock.m1 = 2;
		853	target = 5; / fast clock */
		854
		855	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
		856	for (clock.p2 = limit->p2.p2_fast;
		857	clock.p2 >= limit->p2.p2_slow;
		858	clock.p2 -= clock.p2 > 10 ? 2 : 1) {
		859
		860	clock.p = clock.p1 * clock.p2;
		861
		862	m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
		863	clock.n) << 22, refclk * clock.m1);
		864
		865	if (m2 > INT_MAX/clock.m1)
		866	continue;
		867
		868	clock.m2 = m2;
		869
		870	chv_clock(refclk, &clock);
		871
		872	if (!intel_PLL_is_valid(dev, limit, &clock))
		873	continue;
		874
		875	/* based on hardware requirement, prefer bigger p
		876	*/
		877	if (clock.p > best_clock->p) {
		878	*best_clock = clock;
		879	found = true;
		880	}
		881	}
		882	}
		883
		884	return found;
		885	}
		886
4560	Serge	887	bool intel_crtc_active(struct drm_crtc *crtc)
		888	{
		889	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		890
		891	/* Be paranoid as we can arrive here with only partial
		892	* state retrieved from the hardware during setup.
		893	*
		894	* We can ditch the adjusted_mode.crtc_clock check as soon
		895	* as Haswell has gained clock readout/fastboot support.
		896	*
5060	serge	897	* We can ditch the crtc->primary->fb check as soon as we can
4560	Serge	898	* properly reconstruct framebuffers.
		899	*/
5060	serge	900	return intel_crtc->active && crtc->primary->fb &&
4560	Serge	901	intel_crtc->config.adjusted_mode.crtc_clock;
		902	}
		903
3243	Serge	904	enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
		905	enum pipe pipe)
		906	{
		907	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		908	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		909
3746	Serge	910	return intel_crtc->config.cpu_transcoder;
3243	Serge	911	}
		912
4560	Serge	913	static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
3031	serge	914	{
		915	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	916	u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
3031	serge	917
		918	frame = I915_READ(frame_reg);
		919
		920	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
5060	serge	921	WARN(1, "vblank wait timed out\n");
3031	serge	922	}
		923
2327	Serge	924	/**
		925	* intel_wait_for_vblank - wait for vblank on a given pipe
		926	* @dev: drm device
		927	* @pipe: pipe to wait for
		928	*
		929	* Wait for vblank to occur on a given pipe. Needed for various bits of
		930	* mode setting code.
		931	*/
		932	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		933	{
		934	struct drm_i915_private *dev_priv = dev->dev_private;
		935	int pipestat_reg = PIPESTAT(pipe);
		936
4560	Serge	937	if (IS_G4X(dev) \|\| INTEL_INFO(dev)->gen >= 5) {
		938	g4x_wait_for_vblank(dev, pipe);
3031	serge	939	return;
		940	}
		941
2327	Serge	942	/* Clear existing vblank status. Note this will clear any other
		943	* sticky status fields as well.
		944	*
		945	* This races with i915_driver_irq_handler() with the result
		946	* that either function could miss a vblank event. Here it is not
		947	* fatal, as we will either wait upon the next vblank interrupt or
		948	* timeout. Generally speaking intel_wait_for_vblank() is only
		949	* called during modeset at which time the GPU should be idle and
		950	* should not be performing page flips and thus not waiting on
		951	* vblanks...
		952	* Currently, the result of us stealing a vblank from the irq
		953	* handler is that a single frame will be skipped during swapbuffers.
		954	*/
		955	I915_WRITE(pipestat_reg,
		956	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		957
		958	/* Wait for vblank interrupt bit to set */
		959	if (wait_for(I915_READ(pipestat_reg) &
		960	PIPE_VBLANK_INTERRUPT_STATUS,
		961	50))
		962	DRM_DEBUG_KMS("vblank wait timed out\n");
		963	}
		964
4560	Serge	965	static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
		966	{
		967	struct drm_i915_private *dev_priv = dev->dev_private;
		968	u32 reg = PIPEDSL(pipe);
		969	u32 line1, line2;
		970	u32 line_mask;
		971
		972	if (IS_GEN2(dev))
		973	line_mask = DSL_LINEMASK_GEN2;
		974	else
		975	line_mask = DSL_LINEMASK_GEN3;
		976
		977	line1 = I915_READ(reg) & line_mask;
		978	mdelay(5);
		979	line2 = I915_READ(reg) & line_mask;
		980
		981	return line1 == line2;
		982	}
		983
2327	Serge	984	/*
		985	* intel_wait_for_pipe_off - wait for pipe to turn off
		986	* @dev: drm device
		987	* @pipe: pipe to wait for
		988	*
		989	* After disabling a pipe, we can't wait for vblank in the usual way,
		990	* spinning on the vblank interrupt status bit, since we won't actually
		991	* see an interrupt when the pipe is disabled.
		992	*
		993	* On Gen4 and above:
		994	* wait for the pipe register state bit to turn off
		995	*
		996	* Otherwise:
		997	* wait for the display line value to settle (it usually
		998	* ends up stopping at the start of the next frame).
		999	*
		1000	*/
		1001	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		1002	{
		1003	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	1004	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1005	pipe);
2327	Serge	1006
		1007	if (INTEL_INFO(dev)->gen >= 4) {
3243	Serge	1008	int reg = PIPECONF(cpu_transcoder);
2327	Serge	1009
		1010	/* Wait for the Pipe State to go off */
		1011	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		1012	100))
3031	serge	1013	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1014	} else {
		1015	/* Wait for the display line to settle */
4560	Serge	1016	if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
3031	serge	1017	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1018	}
		1019	}
		1020
3480	Serge	1021	/*
		1022	* ibx_digital_port_connected - is the specified port connected?
		1023	* @dev_priv: i915 private structure
		1024	* @port: the port to test
		1025	*
		1026	* Returns true if @port is connected, false otherwise.
		1027	*/
		1028	bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
		1029	struct intel_digital_port *port)
		1030	{
		1031	u32 bit;
		1032
		1033	if (HAS_PCH_IBX(dev_priv->dev)) {
5060	serge	1034	switch (port->port) {
3480	Serge	1035	case PORT_B:
		1036	bit = SDE_PORTB_HOTPLUG;
		1037	break;
		1038	case PORT_C:
		1039	bit = SDE_PORTC_HOTPLUG;
		1040	break;
		1041	case PORT_D:
		1042	bit = SDE_PORTD_HOTPLUG;
		1043	break;
		1044	default:
		1045	return true;
		1046	}
		1047	} else {
5060	serge	1048	switch (port->port) {
3480	Serge	1049	case PORT_B:
		1050	bit = SDE_PORTB_HOTPLUG_CPT;
		1051	break;
		1052	case PORT_C:
		1053	bit = SDE_PORTC_HOTPLUG_CPT;
		1054	break;
		1055	case PORT_D:
		1056	bit = SDE_PORTD_HOTPLUG_CPT;
		1057	break;
		1058	default:
		1059	return true;
		1060	}
		1061	}
		1062
		1063	return I915_READ(SDEISR) & bit;
		1064	}
		1065
2327	Serge	1066	static const char *state_string(bool enabled)
		1067	{
		1068	return enabled ? "on" : "off";
		1069	}
		1070
		1071	/* Only for pre-ILK configs */
4104	Serge	1072	void assert_pll(struct drm_i915_private *dev_priv,
2327	Serge	1073	enum pipe pipe, bool state)
		1074	{
		1075	int reg;
		1076	u32 val;
		1077	bool cur_state;
		1078
		1079	reg = DPLL(pipe);
		1080	val = I915_READ(reg);
		1081	cur_state = !!(val & DPLL_VCO_ENABLE);
		1082	WARN(cur_state != state,
		1083	"PLL state assertion failure (expected %s, current %s)\n",
		1084	state_string(state), state_string(cur_state));
		1085	}
		1086
4560	Serge	1087	/* XXX: the dsi pll is shared between MIPI DSI ports */
		1088	static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
		1089	{
		1090	u32 val;
		1091	bool cur_state;
		1092
		1093	mutex_lock(&dev_priv->dpio_lock);
		1094	val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
		1095	mutex_unlock(&dev_priv->dpio_lock);
		1096
		1097	cur_state = val & DSI_PLL_VCO_EN;
		1098	WARN(cur_state != state,
		1099	"DSI PLL state assertion failure (expected %s, current %s)\n",
		1100	state_string(state), state_string(cur_state));
		1101	}
		1102	#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
		1103	#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
		1104
4104	Serge	1105	struct intel_shared_dpll *
		1106	intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
		1107	{
		1108	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1109
		1110	if (crtc->config.shared_dpll < 0)
		1111	return NULL;
		1112
		1113	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
		1114	}
		1115
2327	Serge	1116	/* For ILK+ */
4104	Serge	1117	void assert_shared_dpll(struct drm_i915_private *dev_priv,
		1118	struct intel_shared_dpll *pll,
3031	serge	1119	bool state)
2327	Serge	1120	{
		1121	bool cur_state;
4104	Serge	1122	struct intel_dpll_hw_state hw_state;
2327	Serge	1123
3031	serge	1124	if (WARN (!pll,
4104	Serge	1125	"asserting DPLL %s with no DPLL\n", state_string(state)))
3031	serge	1126	return;
2342	Serge	1127
4104	Serge	1128	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
3031	serge	1129	WARN(cur_state != state,
4104	Serge	1130	"%s assertion failure (expected %s, current %s)\n",
		1131	pll->name, state_string(state), state_string(cur_state));
2327	Serge	1132	}
		1133
		1134	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		1135	enum pipe pipe, bool state)
		1136	{
		1137	int reg;
		1138	u32 val;
		1139	bool cur_state;
3243	Serge	1140	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1141	pipe);
2327	Serge	1142
3480	Serge	1143	if (HAS_DDI(dev_priv->dev)) {
		1144	/* DDI does not have a specific FDI_TX register */
3243	Serge	1145	reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3031	serge	1146	val = I915_READ(reg);
3243	Serge	1147	cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
3031	serge	1148	} else {
2327	Serge	1149	reg = FDI_TX_CTL(pipe);
		1150	val = I915_READ(reg);
		1151	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	1152	}
2327	Serge	1153	WARN(cur_state != state,
		1154	"FDI TX state assertion failure (expected %s, current %s)\n",
		1155	state_string(state), state_string(cur_state));
		1156	}
		1157	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		1158	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		1159
		1160	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		1161	enum pipe pipe, bool state)
		1162	{
		1163	int reg;
		1164	u32 val;
		1165	bool cur_state;
		1166
		1167	reg = FDI_RX_CTL(pipe);
		1168	val = I915_READ(reg);
		1169	cur_state = !!(val & FDI_RX_ENABLE);
		1170	WARN(cur_state != state,
		1171	"FDI RX state assertion failure (expected %s, current %s)\n",
		1172	state_string(state), state_string(cur_state));
		1173	}
		1174	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1175	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1176
		1177	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1178	enum pipe pipe)
		1179	{
		1180	int reg;
		1181	u32 val;
		1182
		1183	/* ILK FDI PLL is always enabled */
5060	serge	1184	if (INTEL_INFO(dev_priv->dev)->gen == 5)
2327	Serge	1185	return;
		1186
3031	serge	1187	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
3480	Serge	1188	if (HAS_DDI(dev_priv->dev))
3031	serge	1189	return;
		1190
2327	Serge	1191	reg = FDI_TX_CTL(pipe);
		1192	val = I915_READ(reg);
		1193	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		1194	}
		1195
4104	Serge	1196	void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		1197	enum pipe pipe, bool state)
2327	Serge	1198	{
		1199	int reg;
		1200	u32 val;
4104	Serge	1201	bool cur_state;
2327	Serge	1202
		1203	reg = FDI_RX_CTL(pipe);
		1204	val = I915_READ(reg);
4104	Serge	1205	cur_state = !!(val & FDI_RX_PLL_ENABLE);
		1206	WARN(cur_state != state,
		1207	"FDI RX PLL assertion failure (expected %s, current %s)\n",
		1208	state_string(state), state_string(cur_state));
2327	Serge	1209	}
		1210
		1211	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		1212	enum pipe pipe)
		1213	{
		1214	int pp_reg, lvds_reg;
		1215	u32 val;
		1216	enum pipe panel_pipe = PIPE_A;
		1217	bool locked = true;
		1218
		1219	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1220	pp_reg = PCH_PP_CONTROL;
		1221	lvds_reg = PCH_LVDS;
		1222	} else {
		1223	pp_reg = PP_CONTROL;
		1224	lvds_reg = LVDS;
		1225	}
		1226
		1227	val = I915_READ(pp_reg);
		1228	if (!(val & PANEL_POWER_ON) \|\|
		1229	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		1230	locked = false;
		1231
		1232	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		1233	panel_pipe = PIPE_B;
		1234
		1235	WARN(panel_pipe == pipe && locked,
		1236	"panel assertion failure, pipe %c regs locked\n",
		1237	pipe_name(pipe));
		1238	}
		1239
4560	Serge	1240	static void assert_cursor(struct drm_i915_private *dev_priv,
		1241	enum pipe pipe, bool state)
		1242	{
		1243	struct drm_device *dev = dev_priv->dev;
		1244	bool cur_state;
		1245
5060	serge	1246	if (IS_845G(dev) \|\| IS_I865G(dev))
4560	Serge	1247	cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
		1248	else
		1249	cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
		1250
		1251	WARN(cur_state != state,
		1252	"cursor on pipe %c assertion failure (expected %s, current %s)\n",
		1253	pipe_name(pipe), state_string(state), state_string(cur_state));
		1254	}
		1255	#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
		1256	#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
		1257
2342	Serge	1258	void assert_pipe(struct drm_i915_private *dev_priv,
2327	Serge	1259	enum pipe pipe, bool state)
		1260	{
		1261	int reg;
		1262	u32 val;
		1263	bool cur_state;
3243	Serge	1264	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1265	pipe);
2327	Serge	1266
3031	serge	1267	/* if we need the pipe A quirk it must be always on */
		1268	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		1269	state = true;
		1270
5060	serge	1271	if (!intel_display_power_enabled(dev_priv,
4104	Serge	1272	POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
3480	Serge	1273	cur_state = false;
		1274	} else {
3243	Serge	1275	reg = PIPECONF(cpu_transcoder);
2327	Serge	1276	val = I915_READ(reg);
		1277	cur_state = !!(val & PIPECONF_ENABLE);
3480	Serge	1278	}
		1279
2327	Serge	1280	WARN(cur_state != state,
		1281	"pipe %c assertion failure (expected %s, current %s)\n",
		1282	pipe_name(pipe), state_string(state), state_string(cur_state));
		1283	}
		1284
3031	serge	1285	static void assert_plane(struct drm_i915_private *dev_priv,
		1286	enum plane plane, bool state)
2327	Serge	1287	{
		1288	int reg;
		1289	u32 val;
3031	serge	1290	bool cur_state;
2327	Serge	1291
		1292	reg = DSPCNTR(plane);
		1293	val = I915_READ(reg);
3031	serge	1294	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
		1295	WARN(cur_state != state,
		1296	"plane %c assertion failure (expected %s, current %s)\n",
		1297	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1298	}
		1299
3031	serge	1300	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1301	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1302
2327	Serge	1303	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1304	enum pipe pipe)
		1305	{
4104	Serge	1306	struct drm_device *dev = dev_priv->dev;
2327	Serge	1307	int reg, i;
		1308	u32 val;
		1309	int cur_pipe;
		1310
4104	Serge	1311	/* Primary planes are fixed to pipes on gen4+ */
		1312	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	1313	reg = DSPCNTR(pipe);
		1314	val = I915_READ(reg);
5060	serge	1315	WARN(val & DISPLAY_PLANE_ENABLE,
3031	serge	1316	"plane %c assertion failure, should be disabled but not\n",
		1317	plane_name(pipe));
2327	Serge	1318	return;
3031	serge	1319	}
2327	Serge	1320
		1321	/* Need to check both planes against the pipe */
4104	Serge	1322	for_each_pipe(i) {
2327	Serge	1323	reg = DSPCNTR(i);
		1324	val = I915_READ(reg);
		1325	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		1326	DISPPLANE_SEL_PIPE_SHIFT;
		1327	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		1328	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1329	plane_name(i), pipe_name(pipe));
		1330	}
		1331	}
		1332
3746	Serge	1333	static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
		1334	enum pipe pipe)
		1335	{
4104	Serge	1336	struct drm_device *dev = dev_priv->dev;
5060	serge	1337	int reg, sprite;
3746	Serge	1338	u32 val;
		1339
4104	Serge	1340	if (IS_VALLEYVIEW(dev)) {
5060	serge	1341	for_each_sprite(pipe, sprite) {
		1342	reg = SPCNTR(pipe, sprite);
3746	Serge	1343	val = I915_READ(reg);
5060	serge	1344	WARN(val & SP_ENABLE,
4104	Serge	1345	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
5060	serge	1346	sprite_name(pipe, sprite), pipe_name(pipe));
4104	Serge	1347	}
		1348	} else if (INTEL_INFO(dev)->gen >= 7) {
		1349	reg = SPRCTL(pipe);
		1350	val = I915_READ(reg);
5060	serge	1351	WARN(val & SPRITE_ENABLE,
4104	Serge	1352	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1353	plane_name(pipe), pipe_name(pipe));
		1354	} else if (INTEL_INFO(dev)->gen >= 5) {
		1355	reg = DVSCNTR(pipe);
		1356	val = I915_READ(reg);
5060	serge	1357	WARN(val & DVS_ENABLE,
4104	Serge	1358	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1359	plane_name(pipe), pipe_name(pipe));
3746	Serge	1360	}
		1361	}
		1362
4560	Serge	1363	static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
2327	Serge	1364	{
		1365	u32 val;
		1366	bool enabled;
		1367
4560	Serge	1368	WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) \|\| HAS_PCH_CPT(dev_priv->dev)));
3031	serge	1369
2327	Serge	1370	val = I915_READ(PCH_DREF_CONTROL);
		1371	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1372	DREF_SUPERSPREAD_SOURCE_MASK));
		1373	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		1374	}
		1375
4104	Serge	1376	static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
2327	Serge	1377	enum pipe pipe)
		1378	{
		1379	int reg;
		1380	u32 val;
		1381	bool enabled;
		1382
4104	Serge	1383	reg = PCH_TRANSCONF(pipe);
2327	Serge	1384	val = I915_READ(reg);
		1385	enabled = !!(val & TRANS_ENABLE);
		1386	WARN(enabled,
		1387	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1388	pipe_name(pipe));
		1389	}
		1390
		1391	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1392	enum pipe pipe, u32 port_sel, u32 val)
		1393	{
		1394	if ((val & DP_PORT_EN) == 0)
		1395	return false;
		1396
		1397	if (HAS_PCH_CPT(dev_priv->dev)) {
		1398	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1399	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1400	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1401	return false;
5060	serge	1402	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
		1403	if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
		1404	return false;
2327	Serge	1405	} else {
		1406	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1407	return false;
		1408	}
		1409	return true;
		1410	}
		1411
		1412	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1413	enum pipe pipe, u32 val)
		1414	{
3746	Serge	1415	if ((val & SDVO_ENABLE) == 0)
2327	Serge	1416	return false;
		1417
		1418	if (HAS_PCH_CPT(dev_priv->dev)) {
3746	Serge	1419	if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
2327	Serge	1420	return false;
5060	serge	1421	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
		1422	if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
		1423	return false;
2327	Serge	1424	} else {
3746	Serge	1425	if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
2327	Serge	1426	return false;
		1427	}
		1428	return true;
		1429	}
		1430
		1431	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1432	enum pipe pipe, u32 val)
		1433	{
		1434	if ((val & LVDS_PORT_EN) == 0)
		1435	return false;
		1436
		1437	if (HAS_PCH_CPT(dev_priv->dev)) {
		1438	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1439	return false;
		1440	} else {
		1441	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1442	return false;
		1443	}
		1444	return true;
		1445	}
		1446
		1447	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1448	enum pipe pipe, u32 val)
		1449	{
		1450	if ((val & ADPA_DAC_ENABLE) == 0)
		1451	return false;
		1452	if (HAS_PCH_CPT(dev_priv->dev)) {
		1453	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1454	return false;
		1455	} else {
		1456	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1457	return false;
		1458	}
		1459	return true;
		1460	}
		1461
		1462	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1463	enum pipe pipe, int reg, u32 port_sel)
		1464	{
		1465	u32 val = I915_READ(reg);
		1466	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1467	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1468	reg, pipe_name(pipe));
3031	serge	1469
		1470	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
		1471	&& (val & DP_PIPEB_SELECT),
		1472	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1473	}
		1474
		1475	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1476	enum pipe pipe, int reg)
		1477	{
		1478	u32 val = I915_READ(reg);
3031	serge	1479	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
		1480	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1481	reg, pipe_name(pipe));
3031	serge	1482
3746	Serge	1483	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
3031	serge	1484	&& (val & SDVO_PIPE_B_SELECT),
		1485	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1486	}
		1487
		1488	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1489	enum pipe pipe)
		1490	{
		1491	int reg;
		1492	u32 val;
		1493
		1494	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1495	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1496	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1497
		1498	reg = PCH_ADPA;
		1499	val = I915_READ(reg);
3031	serge	1500	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1501	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1502	pipe_name(pipe));
		1503
		1504	reg = PCH_LVDS;
		1505	val = I915_READ(reg);
3031	serge	1506	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1507	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1508	pipe_name(pipe));
		1509
3746	Serge	1510	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
		1511	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
		1512	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
2327	Serge	1513	}
		1514
4560	Serge	1515	static void intel_init_dpio(struct drm_device *dev)
		1516	{
		1517	struct drm_i915_private *dev_priv = dev->dev_private;
		1518
		1519	if (!IS_VALLEYVIEW(dev))
		1520	return;
		1521
5060	serge	1522	/*
		1523	* IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
		1524	* CHV x1 PHY (DP/HDMI D)
		1525	* IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
		1526	*/
		1527	if (IS_CHERRYVIEW(dev)) {
		1528	DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
		1529	DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
		1530	} else {
4560	Serge	1531	DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
5060	serge	1532	}
4560	Serge	1533	}
		1534
		1535	static void intel_reset_dpio(struct drm_device *dev)
		1536	{
		1537	struct drm_i915_private *dev_priv = dev->dev_private;
		1538
5060	serge	1539	if (IS_CHERRYVIEW(dev)) {
		1540	enum dpio_phy phy;
		1541	u32 val;
4560	Serge	1542
5060	serge	1543	for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
		1544	/* Poll for phypwrgood signal */
		1545	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
		1546	PHY_POWERGOOD(phy), 1))
		1547	DRM_ERROR("Display PHY %d is not power up\n", phy);
4560	Serge	1548
		1549	/*
5060	serge	1550	* Deassert common lane reset for PHY.
		1551	*
		1552	* This should only be done on init and resume from S3
		1553	* with both PLLs disabled, or we risk losing DPIO and
		1554	* PLL synchronization.
		1555	*/
		1556	val = I915_READ(DISPLAY_PHY_CONTROL);
		1557	I915_WRITE(DISPLAY_PHY_CONTROL,
		1558	PHY_COM_LANE_RESET_DEASSERT(phy, val));
		1559	}
		1560	}
4560	Serge	1561	}
		1562
4104	Serge	1563	static void vlv_enable_pll(struct intel_crtc *crtc)
2327	Serge	1564	{
4104	Serge	1565	struct drm_device *dev = crtc->base.dev;
		1566	struct drm_i915_private *dev_priv = dev->dev_private;
		1567	int reg = DPLL(crtc->pipe);
		1568	u32 dpll = crtc->config.dpll_hw_state.dpll;
2327	Serge	1569
4104	Serge	1570	assert_pipe_disabled(dev_priv, crtc->pipe);
		1571
2327	Serge	1572	/* No really, not for ILK+ */
4104	Serge	1573	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
2327	Serge	1574
		1575	/* PLL is protected by panel, make sure we can write it */
		1576	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
4104	Serge	1577	assert_panel_unlocked(dev_priv, crtc->pipe);
2327	Serge	1578
4104	Serge	1579	I915_WRITE(reg, dpll);
		1580	POSTING_READ(reg);
		1581	udelay(150);
2327	Serge	1582
4104	Serge	1583	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		1584	DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
		1585
		1586	I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
		1587	POSTING_READ(DPLL_MD(crtc->pipe));
		1588
		1589	/* We do this three times for luck */
		1590	I915_WRITE(reg, dpll);
		1591	POSTING_READ(reg);
		1592	udelay(150); /* wait for warmup */
		1593	I915_WRITE(reg, dpll);
		1594	POSTING_READ(reg);
		1595	udelay(150); /* wait for warmup */
		1596	I915_WRITE(reg, dpll);
		1597	POSTING_READ(reg);
		1598	udelay(150); /* wait for warmup */
		1599	}
		1600
5060	serge	1601	static void chv_enable_pll(struct intel_crtc *crtc)
		1602	{
		1603	struct drm_device *dev = crtc->base.dev;
		1604	struct drm_i915_private *dev_priv = dev->dev_private;
		1605	int pipe = crtc->pipe;
		1606	enum dpio_channel port = vlv_pipe_to_channel(pipe);
		1607	u32 tmp;
		1608
		1609	assert_pipe_disabled(dev_priv, crtc->pipe);
		1610
		1611	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
		1612
		1613	mutex_lock(&dev_priv->dpio_lock);
		1614
		1615	/* Enable back the 10bit clock to display controller */
		1616	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
		1617	tmp \|= DPIO_DCLKP_EN;
		1618	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
		1619
		1620	/*
		1621	* Need to wait > 100ns between dclkp clock enable bit and PLL enable.
		1622	*/
		1623	udelay(1);
		1624
		1625	/* Enable PLL */
		1626	I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
		1627
		1628	/* Check PLL is locked */
		1629	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		1630	DRM_ERROR("PLL %d failed to lock\n", pipe);
		1631
		1632	/* not sure when this should be written */
		1633	I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
		1634	POSTING_READ(DPLL_MD(pipe));
		1635
		1636	mutex_unlock(&dev_priv->dpio_lock);
		1637	}
		1638
4104	Serge	1639	static void i9xx_enable_pll(struct intel_crtc *crtc)
		1640	{
		1641	struct drm_device *dev = crtc->base.dev;
		1642	struct drm_i915_private *dev_priv = dev->dev_private;
		1643	int reg = DPLL(crtc->pipe);
		1644	u32 dpll = crtc->config.dpll_hw_state.dpll;
		1645
		1646	assert_pipe_disabled(dev_priv, crtc->pipe);
		1647
		1648	/* No really, not for ILK+ */
5060	serge	1649	BUG_ON(INTEL_INFO(dev)->gen >= 5);
4104	Serge	1650
		1651	/* PLL is protected by panel, make sure we can write it */
		1652	if (IS_MOBILE(dev) && !IS_I830(dev))
		1653	assert_panel_unlocked(dev_priv, crtc->pipe);
		1654
		1655	I915_WRITE(reg, dpll);
		1656
		1657	/* Wait for the clocks to stabilize. */
		1658	POSTING_READ(reg);
		1659	udelay(150);
		1660
		1661	if (INTEL_INFO(dev)->gen >= 4) {
		1662	I915_WRITE(DPLL_MD(crtc->pipe),
		1663	crtc->config.dpll_hw_state.dpll_md);
		1664	} else {
		1665	/* The pixel multiplier can only be updated once the
		1666	* DPLL is enabled and the clocks are stable.
		1667	*
		1668	* So write it again.
		1669	*/
		1670	I915_WRITE(reg, dpll);
		1671	}
		1672
2327	Serge	1673	/* We do this three times for luck */
4104	Serge	1674	I915_WRITE(reg, dpll);
2327	Serge	1675	POSTING_READ(reg);
		1676	udelay(150); /* wait for warmup */
4104	Serge	1677	I915_WRITE(reg, dpll);
2327	Serge	1678	POSTING_READ(reg);
		1679	udelay(150); /* wait for warmup */
4104	Serge	1680	I915_WRITE(reg, dpll);
2327	Serge	1681	POSTING_READ(reg);
		1682	udelay(150); /* wait for warmup */
		1683	}
		1684
		1685	/**
4104	Serge	1686	* i9xx_disable_pll - disable a PLL
2327	Serge	1687	* @dev_priv: i915 private structure
		1688	* @pipe: pipe PLL to disable
		1689	*
		1690	* Disable the PLL for @pipe, making sure the pipe is off first.
		1691	*
		1692	* Note! This is for pre-ILK only.
		1693	*/
4104	Serge	1694	static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2327	Serge	1695	{
		1696	/* Don't disable pipe A or pipe A PLLs if needed */
		1697	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1698	return;
		1699
		1700	/* Make sure the pipe isn't still relying on us */
		1701	assert_pipe_disabled(dev_priv, pipe);
		1702
4104	Serge	1703	I915_WRITE(DPLL(pipe), 0);
		1704	POSTING_READ(DPLL(pipe));
2327	Serge	1705	}
		1706
4539	Serge	1707	static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1708	{
		1709	u32 val = 0;
		1710
		1711	/* Make sure the pipe isn't still relying on us */
		1712	assert_pipe_disabled(dev_priv, pipe);
		1713
4560	Serge	1714	/*
		1715	* Leave integrated clock source and reference clock enabled for pipe B.
		1716	* The latter is needed for VGA hotplug / manual detection.
		1717	*/
4539	Serge	1718	if (pipe == PIPE_B)
4560	Serge	1719	val = DPLL_INTEGRATED_CRI_CLK_VLV \| DPLL_REFA_CLK_ENABLE_VLV;
4539	Serge	1720	I915_WRITE(DPLL(pipe), val);
		1721	POSTING_READ(DPLL(pipe));
5060	serge	1722
4539	Serge	1723	}
		1724
5060	serge	1725	static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1726	{
		1727	enum dpio_channel port = vlv_pipe_to_channel(pipe);
		1728	u32 val;
		1729
		1730	/* Make sure the pipe isn't still relying on us */
		1731	assert_pipe_disabled(dev_priv, pipe);
		1732
		1733	/* Set PLL en = 0 */
		1734	val = DPLL_SSC_REF_CLOCK_CHV;
		1735	if (pipe != PIPE_A)
		1736	val \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		1737	I915_WRITE(DPLL(pipe), val);
		1738	POSTING_READ(DPLL(pipe));
		1739
		1740	mutex_lock(&dev_priv->dpio_lock);
		1741
		1742	/* Disable 10bit clock to display controller */
		1743	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
		1744	val &= ~DPIO_DCLKP_EN;
		1745	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
		1746
		1747	/* disable left/right clock distribution */
		1748	if (pipe != PIPE_B) {
		1749	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		1750	val &= ~(CHV_BUFLEFTENA1_MASK \| CHV_BUFRIGHTENA1_MASK);
		1751	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
		1752	} else {
		1753	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		1754	val &= ~(CHV_BUFLEFTENA2_MASK \| CHV_BUFRIGHTENA2_MASK);
		1755	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
		1756	}
		1757
		1758	mutex_unlock(&dev_priv->dpio_lock);
		1759	}
		1760
4560	Serge	1761	void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
		1762	struct intel_digital_port *dport)
3031	serge	1763	{
4104	Serge	1764	u32 port_mask;
5060	serge	1765	int dpll_reg;
3031	serge	1766
4560	Serge	1767	switch (dport->port) {
		1768	case PORT_B:
4104	Serge	1769	port_mask = DPLL_PORTB_READY_MASK;
5060	serge	1770	dpll_reg = DPLL(0);
4560	Serge	1771	break;
		1772	case PORT_C:
4104	Serge	1773	port_mask = DPLL_PORTC_READY_MASK;
5060	serge	1774	dpll_reg = DPLL(0);
4560	Serge	1775	break;
5060	serge	1776	case PORT_D:
		1777	port_mask = DPLL_PORTD_READY_MASK;
		1778	dpll_reg = DPIO_PHY_STATUS;
		1779	break;
4560	Serge	1780	default:
		1781	BUG();
		1782	}
3243	Serge	1783
5060	serge	1784	if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
4104	Serge	1785	WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
5060	serge	1786	port_name(dport->port), I915_READ(dpll_reg));
3031	serge	1787	}
		1788
5060	serge	1789	static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
		1790	{
		1791	struct drm_device *dev = crtc->base.dev;
		1792	struct drm_i915_private *dev_priv = dev->dev_private;
		1793	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
		1794
		1795	if (WARN_ON(pll == NULL))
		1796	return;
		1797
		1798	WARN_ON(!pll->refcount);
		1799	if (pll->active == 0) {
		1800	DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
		1801	WARN_ON(pll->on);
		1802	assert_shared_dpll_disabled(dev_priv, pll);
		1803
		1804	pll->mode_set(dev_priv, pll);
		1805	}
		1806	}
		1807
2327	Serge	1808	/**
5060	serge	1809	* intel_enable_shared_dpll - enable PCH PLL
2327	Serge	1810	* @dev_priv: i915 private structure
		1811	* @pipe: pipe PLL to enable
		1812	*
		1813	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1814	* drives the transcoder clock.
		1815	*/
5060	serge	1816	static void intel_enable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1817	{
5060	serge	1818	struct drm_device *dev = crtc->base.dev;
		1819	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1820	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1821
4104	Serge	1822	if (WARN_ON(pll == NULL))
2342	Serge	1823	return;
		1824
3031	serge	1825	if (WARN_ON(pll->refcount == 0))
		1826	return;
2327	Serge	1827
4104	Serge	1828	DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
		1829	pll->name, pll->active, pll->on,
		1830	crtc->base.base.id);
3031	serge	1831
4104	Serge	1832	if (pll->active++) {
		1833	WARN_ON(!pll->on);
		1834	assert_shared_dpll_enabled(dev_priv, pll);
3031	serge	1835	return;
		1836	}
4104	Serge	1837	WARN_ON(pll->on);
3031	serge	1838
5060	serge	1839	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
		1840
4104	Serge	1841	DRM_DEBUG_KMS("enabling %s\n", pll->name);
		1842	pll->enable(dev_priv, pll);
3031	serge	1843	pll->on = true;
2327	Serge	1844	}
		1845
5060	serge	1846	void intel_disable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1847	{
5060	serge	1848	struct drm_device *dev = crtc->base.dev;
		1849	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1850	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1851
		1852	/* PCH only available on ILK+ */
5060	serge	1853	BUG_ON(INTEL_INFO(dev)->gen < 5);
4104	Serge	1854	if (WARN_ON(pll == NULL))
3031	serge	1855	return;
2327	Serge	1856
3031	serge	1857	if (WARN_ON(pll->refcount == 0))
		1858	return;
2327	Serge	1859
4104	Serge	1860	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
		1861	pll->name, pll->active, pll->on,
		1862	crtc->base.base.id);
2342	Serge	1863
3031	serge	1864	if (WARN_ON(pll->active == 0)) {
4104	Serge	1865	assert_shared_dpll_disabled(dev_priv, pll);
3031	serge	1866	return;
		1867	}
2342	Serge	1868
4104	Serge	1869	assert_shared_dpll_enabled(dev_priv, pll);
		1870	WARN_ON(!pll->on);
		1871	if (--pll->active)
2342	Serge	1872	return;
		1873
4104	Serge	1874	DRM_DEBUG_KMS("disabling %s\n", pll->name);
		1875	pll->disable(dev_priv, pll);
3031	serge	1876	pll->on = false;
5060	serge	1877
		1878	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2327	Serge	1879	}
		1880
3243	Serge	1881	static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1882	enum pipe pipe)
		1883	{
3243	Serge	1884	struct drm_device *dev = dev_priv->dev;
3031	serge	1885	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4104	Serge	1886	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	1887	uint32_t reg, val, pipeconf_val;
2327	Serge	1888
		1889	/* PCH only available on ILK+ */
5060	serge	1890	BUG_ON(INTEL_INFO(dev)->gen < 5);
2327	Serge	1891
		1892	/* Make sure PCH DPLL is enabled */
4104	Serge	1893	assert_shared_dpll_enabled(dev_priv,
		1894	intel_crtc_to_shared_dpll(intel_crtc));
2327	Serge	1895
		1896	/* FDI must be feeding us bits for PCH ports */
		1897	assert_fdi_tx_enabled(dev_priv, pipe);
		1898	assert_fdi_rx_enabled(dev_priv, pipe);
		1899
3243	Serge	1900	if (HAS_PCH_CPT(dev)) {
		1901	/* Workaround: Set the timing override bit before enabling the
		1902	* pch transcoder. */
		1903	reg = TRANS_CHICKEN2(pipe);
		1904	val = I915_READ(reg);
		1905	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1906	I915_WRITE(reg, val);
3031	serge	1907	}
3243	Serge	1908
4104	Serge	1909	reg = PCH_TRANSCONF(pipe);
2327	Serge	1910	val = I915_READ(reg);
3031	serge	1911	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1912
		1913	if (HAS_PCH_IBX(dev_priv->dev)) {
		1914	/*
		1915	* make the BPC in transcoder be consistent with
		1916	* that in pipeconf reg.
		1917	*/
3480	Serge	1918	val &= ~PIPECONF_BPC_MASK;
		1919	val \|= pipeconf_val & PIPECONF_BPC_MASK;
2327	Serge	1920	}
3031	serge	1921
		1922	val &= ~TRANS_INTERLACE_MASK;
		1923	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		1924	if (HAS_PCH_IBX(dev_priv->dev) &&
		1925	intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
		1926	val \|= TRANS_LEGACY_INTERLACED_ILK;
		1927	else
		1928	val \|= TRANS_INTERLACED;
		1929	else
		1930	val \|= TRANS_PROGRESSIVE;
		1931
2327	Serge	1932	I915_WRITE(reg, val \| TRANS_ENABLE);
		1933	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4104	Serge	1934	DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2327	Serge	1935	}
		1936
3243	Serge	1937	static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
		1938	enum transcoder cpu_transcoder)
		1939	{
		1940	u32 val, pipeconf_val;
		1941
		1942	/* PCH only available on ILK+ */
5060	serge	1943	BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
3243	Serge	1944
		1945	/* FDI must be feeding us bits for PCH ports */
3480	Serge	1946	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
3243	Serge	1947	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
		1948
		1949	/* Workaround: set timing override bit. */
		1950	val = I915_READ(_TRANSA_CHICKEN2);
		1951	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1952	I915_WRITE(_TRANSA_CHICKEN2, val);
		1953
		1954	val = TRANS_ENABLE;
		1955	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
		1956
		1957	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
		1958	PIPECONF_INTERLACED_ILK)
		1959	val \|= TRANS_INTERLACED;
		1960	else
		1961	val \|= TRANS_PROGRESSIVE;
		1962
4104	Serge	1963	I915_WRITE(LPT_TRANSCONF, val);
		1964	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
3243	Serge	1965	DRM_ERROR("Failed to enable PCH transcoder\n");
		1966	}
		1967
		1968	static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1969	enum pipe pipe)
		1970	{
3243	Serge	1971	struct drm_device *dev = dev_priv->dev;
		1972	uint32_t reg, val;
2327	Serge	1973
		1974	/* FDI relies on the transcoder */
		1975	assert_fdi_tx_disabled(dev_priv, pipe);
		1976	assert_fdi_rx_disabled(dev_priv, pipe);
		1977
		1978	/* Ports must be off as well */
		1979	assert_pch_ports_disabled(dev_priv, pipe);
		1980
4104	Serge	1981	reg = PCH_TRANSCONF(pipe);
2327	Serge	1982	val = I915_READ(reg);
		1983	val &= ~TRANS_ENABLE;
		1984	I915_WRITE(reg, val);
		1985	/* wait for PCH transcoder off, transcoder state */
		1986	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4104	Serge	1987	DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
3243	Serge	1988
		1989	if (!HAS_PCH_IBX(dev)) {
		1990	/* Workaround: Clear the timing override chicken bit again. */
		1991	reg = TRANS_CHICKEN2(pipe);
		1992	val = I915_READ(reg);
		1993	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1994	I915_WRITE(reg, val);
		1995	}
2327	Serge	1996	}
		1997
3243	Serge	1998	static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
		1999	{
		2000	u32 val;
		2001
4104	Serge	2002	val = I915_READ(LPT_TRANSCONF);
3243	Serge	2003	val &= ~TRANS_ENABLE;
4104	Serge	2004	I915_WRITE(LPT_TRANSCONF, val);
3243	Serge	2005	/* wait for PCH transcoder off, transcoder state */
4104	Serge	2006	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
3243	Serge	2007	DRM_ERROR("Failed to disable PCH transcoder\n");
		2008
		2009	/* Workaround: clear timing override bit. */
		2010	val = I915_READ(_TRANSA_CHICKEN2);
		2011	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		2012	I915_WRITE(_TRANSA_CHICKEN2, val);
		2013	}
		2014
2327	Serge	2015	/**
		2016	* intel_enable_pipe - enable a pipe, asserting requirements
5060	serge	2017	* @crtc: crtc responsible for the pipe
2327	Serge	2018	*
5060	serge	2019	* Enable @crtc's pipe, making sure that various hardware specific requirements
2327	Serge	2020	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		2021	*/
5060	serge	2022	static void intel_enable_pipe(struct intel_crtc *crtc)
2327	Serge	2023	{
5060	serge	2024	struct drm_device *dev = crtc->base.dev;
		2025	struct drm_i915_private *dev_priv = dev->dev_private;
		2026	enum pipe pipe = crtc->pipe;
3243	Serge	2027	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		2028	pipe);
3480	Serge	2029	enum pipe pch_transcoder;
2327	Serge	2030	int reg;
		2031	u32 val;
		2032
4104	Serge	2033	assert_planes_disabled(dev_priv, pipe);
4560	Serge	2034	assert_cursor_disabled(dev_priv, pipe);
4104	Serge	2035	assert_sprites_disabled(dev_priv, pipe);
		2036
3480	Serge	2037	if (HAS_PCH_LPT(dev_priv->dev))
3243	Serge	2038	pch_transcoder = TRANSCODER_A;
		2039	else
		2040	pch_transcoder = pipe;
		2041
2327	Serge	2042	/*
		2043	* A pipe without a PLL won't actually be able to drive bits from
		2044	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		2045	* need the check.
		2046	*/
		2047	if (!HAS_PCH_SPLIT(dev_priv->dev))
5060	serge	2048	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
4560	Serge	2049	assert_dsi_pll_enabled(dev_priv);
		2050	else
2327	Serge	2051	assert_pll_enabled(dev_priv, pipe);
		2052	else {
5060	serge	2053	if (crtc->config.has_pch_encoder) {
2327	Serge	2054	/* if driving the PCH, we need FDI enabled */
3243	Serge	2055	assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
3480	Serge	2056	assert_fdi_tx_pll_enabled(dev_priv,
		2057	(enum pipe) cpu_transcoder);
2327	Serge	2058	}
		2059	/* FIXME: assert CPU port conditions for SNB+ */
		2060	}
		2061
3243	Serge	2062	reg = PIPECONF(cpu_transcoder);
2327	Serge	2063	val = I915_READ(reg);
5060	serge	2064	if (val & PIPECONF_ENABLE) {
		2065	WARN_ON(!(pipe == PIPE_A &&
		2066	dev_priv->quirks & QUIRK_PIPEA_FORCE));
2327	Serge	2067	return;
5060	serge	2068	}
2327	Serge	2069
		2070	I915_WRITE(reg, val \| PIPECONF_ENABLE);
5060	serge	2071	POSTING_READ(reg);
2327	Serge	2072	}
		2073
		2074	/**
		2075	* intel_disable_pipe - disable a pipe, asserting requirements
		2076	* @dev_priv: i915 private structure
		2077	* @pipe: pipe to disable
		2078	*
		2079	* Disable @pipe, making sure that various hardware specific requirements
		2080	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		2081	*
		2082	* @pipe should be %PIPE_A or %PIPE_B.
		2083	*
		2084	* Will wait until the pipe has shut down before returning.
		2085	*/
		2086	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		2087	enum pipe pipe)
		2088	{
3243	Serge	2089	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		2090	pipe);
2327	Serge	2091	int reg;
		2092	u32 val;
		2093
3031	serge	2094	/*
2327	Serge	2095	* Make sure planes won't keep trying to pump pixels to us,
		2096	* or we might hang the display.
		2097	*/
		2098	assert_planes_disabled(dev_priv, pipe);
4560	Serge	2099	assert_cursor_disabled(dev_priv, pipe);
3746	Serge	2100	assert_sprites_disabled(dev_priv, pipe);
2327	Serge	2101
		2102	/* Don't disable pipe A or pipe A PLLs if needed */
		2103	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		2104	return;
		2105
3243	Serge	2106	reg = PIPECONF(cpu_transcoder);
2327	Serge	2107	val = I915_READ(reg);
		2108	if ((val & PIPECONF_ENABLE) == 0)
		2109	return;
		2110
		2111	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		2112	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		2113	}
		2114
		2115	/*
		2116	* Plane regs are double buffered, going from enabled->disabled needs a
		2117	* trigger in order to latch. The display address reg provides this.
		2118	*/
4560	Serge	2119	void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2327	Serge	2120	enum plane plane)
		2121	{
5060	serge	2122	struct drm_device *dev = dev_priv->dev;
		2123	u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
4560	Serge	2124
		2125	I915_WRITE(reg, I915_READ(reg));
		2126	POSTING_READ(reg);
2327	Serge	2127	}
		2128
		2129	/**
5060	serge	2130	* intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2327	Serge	2131	* @dev_priv: i915 private structure
		2132	* @plane: plane to enable
		2133	* @pipe: pipe being fed
		2134	*
		2135	* Enable @plane on @pipe, making sure that @pipe is running first.
		2136	*/
5060	serge	2137	static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2327	Serge	2138	enum plane plane, enum pipe pipe)
		2139	{
5060	serge	2140	struct drm_device *dev = dev_priv->dev;
4560	Serge	2141	struct intel_crtc *intel_crtc =
		2142	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2327	Serge	2143	int reg;
		2144	u32 val;
		2145
		2146	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		2147	assert_pipe_enabled(dev_priv, pipe);
		2148
5060	serge	2149	if (intel_crtc->primary_enabled)
		2150	return;
4560	Serge	2151
		2152	intel_crtc->primary_enabled = true;
		2153
2327	Serge	2154	reg = DSPCNTR(plane);
		2155	val = I915_READ(reg);
5060	serge	2156	WARN_ON(val & DISPLAY_PLANE_ENABLE);
2327	Serge	2157
		2158	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
4560	Serge	2159	intel_flush_primary_plane(dev_priv, plane);
2327	Serge	2160	}
		2161
		2162	/**
5060	serge	2163	* intel_disable_primary_hw_plane - disable the primary hardware plane
2327	Serge	2164	* @dev_priv: i915 private structure
		2165	* @plane: plane to disable
		2166	* @pipe: pipe consuming the data
		2167	*
		2168	* Disable @plane; should be an independent operation.
		2169	*/
5060	serge	2170	static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2327	Serge	2171	enum plane plane, enum pipe pipe)
		2172	{
4560	Serge	2173	struct intel_crtc *intel_crtc =
		2174	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2327	Serge	2175	int reg;
		2176	u32 val;
		2177
5060	serge	2178	if (!intel_crtc->primary_enabled)
		2179	return;
4560	Serge	2180
		2181	intel_crtc->primary_enabled = false;
		2182
2327	Serge	2183	reg = DSPCNTR(plane);
		2184	val = I915_READ(reg);
5060	serge	2185	WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2327	Serge	2186
		2187	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
4560	Serge	2188	intel_flush_primary_plane(dev_priv, plane);
2327	Serge	2189	}
		2190
3746	Serge	2191	static bool need_vtd_wa(struct drm_device *dev)
		2192	{
		2193	#ifdef CONFIG_INTEL_IOMMU
		2194	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		2195	return true;
		2196	#endif
		2197	return false;
		2198	}
		2199
5060	serge	2200	static int intel_align_height(struct drm_device *dev, int height, bool tiled)
		2201	{
		2202	int tile_height;
		2203
		2204	tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
		2205	return ALIGN(height, tile_height);
		2206	}
		2207
2335	Serge	2208	int
		2209	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		2210	struct drm_i915_gem_object *obj,
5060	serge	2211	struct intel_engine_cs *pipelined)
2335	Serge	2212	{
		2213	struct drm_i915_private *dev_priv = dev->dev_private;
		2214	u32 alignment;
		2215	int ret;
2327	Serge	2216
5060	serge	2217	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
		2218
2335	Serge	2219	switch (obj->tiling_mode) {
		2220	case I915_TILING_NONE:
		2221	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		2222	alignment = 128 * 1024;
		2223	else if (INTEL_INFO(dev)->gen >= 4)
		2224	alignment = 4 * 1024;
		2225	else
		2226	alignment = 64 * 1024;
		2227	break;
		2228	case I915_TILING_X:
		2229	/* pin() will align the object as required by fence */
		2230	alignment = 0;
		2231	break;
		2232	case I915_TILING_Y:
4560	Serge	2233	WARN(1, "Y tiled bo slipped through, driver bug!\n");
2335	Serge	2234	return -EINVAL;
		2235	default:
		2236	BUG();
		2237	}
2327	Serge	2238
3746	Serge	2239	/* Note that the w/a also requires 64 PTE of padding following the
		2240	* bo. We currently fill all unused PTE with the shadow page and so
		2241	* we should always have valid PTE following the scanout preventing
		2242	* the VT-d warning.
		2243	*/
		2244	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		2245	alignment = 256 * 1024;
		2246
2335	Serge	2247	dev_priv->mm.interruptible = false;
		2248	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		2249	if (ret)
		2250	goto err_interruptible;
2327	Serge	2251
2335	Serge	2252	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		2253	* fence, whereas 965+ only requires a fence if using
		2254	* framebuffer compression. For simplicity, we always install
		2255	* a fence as the cost is not that onerous.
		2256	*/
3480	Serge	2257	ret = i915_gem_object_get_fence(obj);
		2258	if (ret)
		2259	goto err_unpin;
2327	Serge	2260
3480	Serge	2261	i915_gem_object_pin_fence(obj);
		2262
2335	Serge	2263	dev_priv->mm.interruptible = true;
		2264	return 0;
2327	Serge	2265
2335	Serge	2266	err_unpin:
4104	Serge	2267	i915_gem_object_unpin_from_display_plane(obj);
2335	Serge	2268	err_interruptible:
		2269	dev_priv->mm.interruptible = true;
		2270	return ret;
		2271	}
2327	Serge	2272
3031	serge	2273	void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
		2274	{
5060	serge	2275	WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
		2276
		2277	i915_gem_object_unpin_fence(obj);
		2278	// i915_gem_object_unpin_from_display_plane(obj);
3031	serge	2279	}
		2280
		2281	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		2282	* is assumed to be a power-of-two. */
3480	Serge	2283	unsigned long intel_gen4_compute_page_offset(int x, int y,
		2284	unsigned int tiling_mode,
		2285	unsigned int cpp,
3031	serge	2286	unsigned int pitch)
		2287	{
3480	Serge	2288	if (tiling_mode != I915_TILING_NONE) {
		2289	unsigned int tile_rows, tiles;
3031	serge	2290
		2291	tile_rows = *y / 8;
		2292	*y %= 8;
		2293
3480	Serge	2294	tiles = *x / (512/cpp);
		2295	*x %= 512/cpp;
		2296
3031	serge	2297	return tile_rows * pitch * 8 + tiles * 4096;
3480	Serge	2298	} else {
		2299	unsigned int offset;
		2300
		2301	offset = y pitch + x cpp;
		2302	*y = 0;
		2303	*x = (offset & 4095) / cpp;
		2304	return offset & -4096;
		2305	}
3031	serge	2306	}
		2307
5060	serge	2308	int intel_format_to_fourcc(int format)
2327	Serge	2309	{
5060	serge	2310	switch (format) {
		2311	case DISPPLANE_8BPP:
		2312	return DRM_FORMAT_C8;
		2313	case DISPPLANE_BGRX555:
		2314	return DRM_FORMAT_XRGB1555;
		2315	case DISPPLANE_BGRX565:
		2316	return DRM_FORMAT_RGB565;
		2317	default:
		2318	case DISPPLANE_BGRX888:
		2319	return DRM_FORMAT_XRGB8888;
		2320	case DISPPLANE_RGBX888:
		2321	return DRM_FORMAT_XBGR8888;
		2322	case DISPPLANE_BGRX101010:
		2323	return DRM_FORMAT_XRGB2101010;
		2324	case DISPPLANE_RGBX101010:
		2325	return DRM_FORMAT_XBGR2101010;
		2326	}
		2327	}
		2328
		2329	static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
		2330	struct intel_plane_config *plane_config)
		2331	{
		2332	struct drm_device *dev = crtc->base.dev;
		2333	struct drm_i915_gem_object *obj = NULL;
		2334	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
		2335	u32 base = plane_config->base;
		2336
		2337	if (plane_config->size == 0)
		2338	return false;
		2339
		2340	obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
		2341	plane_config->size);
		2342	if (!obj)
		2343	return false;
		2344
		2345	main_fb_obj = obj;
		2346
		2347	if (plane_config->tiled) {
		2348	obj->tiling_mode = I915_TILING_X;
		2349	obj->stride = crtc->base.primary->fb->pitches[0];
		2350	}
		2351
		2352	mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
		2353	mode_cmd.width = crtc->base.primary->fb->width;
		2354	mode_cmd.height = crtc->base.primary->fb->height;
		2355	mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
		2356
		2357	mutex_lock(&dev->struct_mutex);
		2358
		2359	if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
		2360	&mode_cmd, obj)) {
		2361	DRM_DEBUG_KMS("intel fb init failed\n");
		2362	goto out_unref_obj;
		2363	}
		2364
		2365	obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
		2366	mutex_unlock(&dev->struct_mutex);
		2367
		2368	DRM_DEBUG_KMS("plane fb obj %p\n", obj);
		2369	return true;
		2370
		2371	out_unref_obj:
		2372	drm_gem_object_unreference(&obj->base);
		2373	mutex_unlock(&dev->struct_mutex);
		2374	return false;
		2375	}
		2376
		2377	static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
		2378	struct intel_plane_config *plane_config)
		2379	{
		2380	struct drm_device *dev = intel_crtc->base.dev;
		2381	struct drm_crtc *c;
		2382	struct intel_crtc *i;
		2383	struct drm_i915_gem_object *obj;
		2384
		2385	if (!intel_crtc->base.primary->fb)
		2386	return;
		2387
		2388	if (intel_alloc_plane_obj(intel_crtc, plane_config))
		2389	return;
		2390
		2391	kfree(intel_crtc->base.primary->fb);
		2392	intel_crtc->base.primary->fb = NULL;
		2393
		2394	/*
		2395	* Failed to alloc the obj, check to see if we should share
		2396	* an fb with another CRTC instead
		2397	*/
		2398	for_each_crtc(dev, c) {
		2399	i = to_intel_crtc(c);
		2400
		2401	if (c == &intel_crtc->base)
		2402	continue;
		2403
		2404	if (!i->active)
		2405	continue;
		2406
		2407	obj = intel_fb_obj(c->primary->fb);
		2408	if (obj == NULL)
		2409	continue;
		2410
		2411	if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
		2412	drm_framebuffer_reference(c->primary->fb);
		2413	intel_crtc->base.primary->fb = c->primary->fb;
		2414	obj->frontbuffer_bits \|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
		2415	break;
		2416	}
		2417	}
		2418	}
		2419
		2420	static void i9xx_update_primary_plane(struct drm_crtc *crtc,
		2421	struct drm_framebuffer *fb,
		2422	int x, int y)
		2423	{
2327	Serge	2424	struct drm_device *dev = crtc->dev;
		2425	struct drm_i915_private *dev_priv = dev->dev_private;
		2426	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	2427	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2327	Serge	2428	int plane = intel_crtc->plane;
3031	serge	2429	unsigned long linear_offset;
2327	Serge	2430	u32 dspcntr;
		2431	u32 reg;
		2432
		2433	reg = DSPCNTR(plane);
		2434	dspcntr = I915_READ(reg);
		2435	/* Mask out pixel format bits in case we change it */
		2436	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	2437	switch (fb->pixel_format) {
		2438	case DRM_FORMAT_C8:
2327	Serge	2439	dspcntr \|= DISPPLANE_8BPP;
		2440	break;
3243	Serge	2441	case DRM_FORMAT_XRGB1555:
		2442	case DRM_FORMAT_ARGB1555:
		2443	dspcntr \|= DISPPLANE_BGRX555;
		2444	break;
		2445	case DRM_FORMAT_RGB565:
		2446	dspcntr \|= DISPPLANE_BGRX565;
		2447	break;
		2448	case DRM_FORMAT_XRGB8888:
		2449	case DRM_FORMAT_ARGB8888:
		2450	dspcntr \|= DISPPLANE_BGRX888;
		2451	break;
		2452	case DRM_FORMAT_XBGR8888:
		2453	case DRM_FORMAT_ABGR8888:
		2454	dspcntr \|= DISPPLANE_RGBX888;
		2455	break;
		2456	case DRM_FORMAT_XRGB2101010:
		2457	case DRM_FORMAT_ARGB2101010:
		2458	dspcntr \|= DISPPLANE_BGRX101010;
2327	Serge	2459	break;
3243	Serge	2460	case DRM_FORMAT_XBGR2101010:
		2461	case DRM_FORMAT_ABGR2101010:
		2462	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	2463	break;
		2464	default:
3746	Serge	2465	BUG();
2327	Serge	2466	}
3243	Serge	2467
2327	Serge	2468	if (INTEL_INFO(dev)->gen >= 4) {
		2469	if (obj->tiling_mode != I915_TILING_NONE)
		2470	dspcntr \|= DISPPLANE_TILED;
		2471	else
		2472	dspcntr &= ~DISPPLANE_TILED;
		2473	}
		2474
4104	Serge	2475	if (IS_G4X(dev))
		2476	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2477
2327	Serge	2478	I915_WRITE(reg, dspcntr);
		2479
3031	serge	2480	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327	Serge	2481
3031	serge	2482	if (INTEL_INFO(dev)->gen >= 4) {
		2483	intel_crtc->dspaddr_offset =
3480	Serge	2484	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2485	fb->bits_per_pixel / 8,
		2486	fb->pitches[0]);
		2487	linear_offset -= intel_crtc->dspaddr_offset;
		2488	} else {
		2489	intel_crtc->dspaddr_offset = linear_offset;
		2490	}
		2491
4104	Serge	2492	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2493	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2494	fb->pitches[0]);
2342	Serge	2495	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327	Serge	2496	if (INTEL_INFO(dev)->gen >= 4) {
4560	Serge	2497	I915_WRITE(DSPSURF(plane),
4104	Serge	2498	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	2499	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2500	I915_WRITE(DSPLINOFF(plane), linear_offset);
2327	Serge	2501	} else
4104	Serge	2502	I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2327	Serge	2503	POSTING_READ(reg);
		2504	}
		2505
5060	serge	2506	static void ironlake_update_primary_plane(struct drm_crtc *crtc,
		2507	struct drm_framebuffer *fb,
		2508	int x, int y)
2327	Serge	2509	{
		2510	struct drm_device *dev = crtc->dev;
		2511	struct drm_i915_private *dev_priv = dev->dev_private;
		2512	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	2513	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2327	Serge	2514	int plane = intel_crtc->plane;
3031	serge	2515	unsigned long linear_offset;
2327	Serge	2516	u32 dspcntr;
		2517	u32 reg;
		2518
		2519	reg = DSPCNTR(plane);
		2520	dspcntr = I915_READ(reg);
		2521	/* Mask out pixel format bits in case we change it */
		2522	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	2523	switch (fb->pixel_format) {
		2524	case DRM_FORMAT_C8:
2327	Serge	2525	dspcntr \|= DISPPLANE_8BPP;
		2526	break;
3243	Serge	2527	case DRM_FORMAT_RGB565:
		2528	dspcntr \|= DISPPLANE_BGRX565;
2327	Serge	2529	break;
3243	Serge	2530	case DRM_FORMAT_XRGB8888:
		2531	case DRM_FORMAT_ARGB8888:
		2532	dspcntr \|= DISPPLANE_BGRX888;
		2533	break;
		2534	case DRM_FORMAT_XBGR8888:
		2535	case DRM_FORMAT_ABGR8888:
		2536	dspcntr \|= DISPPLANE_RGBX888;
		2537	break;
		2538	case DRM_FORMAT_XRGB2101010:
		2539	case DRM_FORMAT_ARGB2101010:
		2540	dspcntr \|= DISPPLANE_BGRX101010;
		2541	break;
		2542	case DRM_FORMAT_XBGR2101010:
		2543	case DRM_FORMAT_ABGR2101010:
		2544	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	2545	break;
		2546	default:
3746	Serge	2547	BUG();
2327	Serge	2548	}
		2549
3480	Serge	2550	if (obj->tiling_mode != I915_TILING_NONE)
		2551	dspcntr \|= DISPPLANE_TILED;
		2552	else
2327	Serge	2553	dspcntr &= ~DISPPLANE_TILED;
		2554
4560	Serge	2555	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
4104	Serge	2556	dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
		2557	else
2327	Serge	2558	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2559
		2560	I915_WRITE(reg, dspcntr);
		2561
3031	serge	2562	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
		2563	intel_crtc->dspaddr_offset =
3480	Serge	2564	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2565	fb->bits_per_pixel / 8,
		2566	fb->pitches[0]);
		2567	linear_offset -= intel_crtc->dspaddr_offset;
2327	Serge	2568
4104	Serge	2569	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2570	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2571	fb->pitches[0]);
2342	Serge	2572	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
4560	Serge	2573	I915_WRITE(DSPSURF(plane),
4104	Serge	2574	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
4560	Serge	2575	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
3243	Serge	2576	I915_WRITE(DSPOFFSET(plane), (y << 16) \| x);
		2577	} else {
2330	Serge	2578	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2579	I915_WRITE(DSPLINOFF(plane), linear_offset);
3243	Serge	2580	}
2330	Serge	2581	POSTING_READ(reg);
2327	Serge	2582	}
		2583
		2584	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2585	static int
		2586	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2587	int x, int y, enum mode_set_atomic state)
		2588	{
		2589	struct drm_device *dev = crtc->dev;
		2590	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2591
		2592	if (dev_priv->display.disable_fbc)
		2593	dev_priv->display.disable_fbc(dev);
5060	serge	2594	intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
3031	serge	2595
5060	serge	2596	dev_priv->display.update_primary_plane(crtc, fb, x, y);
		2597
		2598	return 0;
3031	serge	2599	}
		2600
		2601	#if 0
4104	Serge	2602	void intel_display_handle_reset(struct drm_device *dev)
		2603	{
		2604	struct drm_i915_private *dev_priv = dev->dev_private;
		2605	struct drm_crtc *crtc;
		2606
		2607	/*
		2608	* Flips in the rings have been nuked by the reset,
		2609	* so complete all pending flips so that user space
		2610	* will get its events and not get stuck.
		2611	*
		2612	* Also update the base address of all primary
		2613	* planes to the the last fb to make sure we're
		2614	* showing the correct fb after a reset.
		2615	*
		2616	* Need to make two loops over the crtcs so that we
		2617	* don't try to grab a crtc mutex before the
		2618	* pending_flip_queue really got woken up.
		2619	*/
		2620
5060	serge	2621	for_each_crtc(dev, crtc) {
4104	Serge	2622	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2623	enum plane plane = intel_crtc->plane;
		2624
		2625	intel_prepare_page_flip(dev, plane);
		2626	intel_finish_page_flip_plane(dev, plane);
		2627	}
		2628
5060	serge	2629	for_each_crtc(dev, crtc) {
4104	Serge	2630	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2631
5060	serge	2632	drm_modeset_lock(&crtc->mutex, NULL);
4560	Serge	2633	/*
		2634	* FIXME: Once we have proper support for primary planes (and
		2635	* disabling them without disabling the entire crtc) allow again
5060	serge	2636	* a NULL crtc->primary->fb.
4560	Serge	2637	*/
5060	serge	2638	if (intel_crtc->active && crtc->primary->fb)
		2639	dev_priv->display.update_primary_plane(crtc,
		2640	crtc->primary->fb,
		2641	crtc->x,
		2642	crtc->y);
		2643	drm_modeset_unlock(&crtc->mutex);
4104	Serge	2644	}
		2645	}
		2646
3031	serge	2647	static int
		2648	intel_finish_fb(struct drm_framebuffer *old_fb)
		2649	{
5060	serge	2650	struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3031	serge	2651	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		2652	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	2653	int ret;
		2654
3031	serge	2655	/* Big Hammer, we also need to ensure that any pending
		2656	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2657	* current scanout is retired before unpinning the old
		2658	* framebuffer.
		2659	*
		2660	* This should only fail upon a hung GPU, in which case we
		2661	* can safely continue.
		2662	*/
		2663	dev_priv->mm.interruptible = false;
		2664	ret = i915_gem_object_finish_gpu(obj);
		2665	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	2666
3031	serge	2667	return ret;
2327	Serge	2668	}
4104	Serge	2669
5060	serge	2670	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
4104	Serge	2671	{
		2672	struct drm_device *dev = crtc->dev;
5060	serge	2673	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	2674	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	2675	unsigned long flags;
		2676	bool pending;
4104	Serge	2677
5060	serge	2678	if (i915_reset_in_progress(&dev_priv->gpu_error) \|\|
		2679	intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
		2680	return false;
4104	Serge	2681
5060	serge	2682	spin_lock_irqsave(&dev->event_lock, flags);
		2683	pending = to_intel_crtc(crtc)->unpin_work != NULL;
		2684	spin_unlock_irqrestore(&dev->event_lock, flags);
4104	Serge	2685
5060	serge	2686	return pending;
4104	Serge	2687	}
3031	serge	2688	#endif
2327	Serge	2689
		2690	static int
		2691	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
3031	serge	2692	struct drm_framebuffer *fb)
2327	Serge	2693	{
		2694	struct drm_device *dev = crtc->dev;
3031	serge	2695	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2696	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	2697	enum pipe pipe = intel_crtc->pipe;
		2698	struct drm_framebuffer *old_fb = crtc->primary->fb;
		2699	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
		2700	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2342	Serge	2701	int ret;
2327	Serge	2702
5060	serge	2703
2327	Serge	2704	/* no fb bound */
3031	serge	2705	if (!fb) {
2327	Serge	2706	DRM_ERROR("No FB bound\n");
		2707	return 0;
		2708	}
		2709
3746	Serge	2710	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
4104	Serge	2711	DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
		2712	plane_name(intel_crtc->plane),
3746	Serge	2713	INTEL_INFO(dev)->num_pipes);
2327	Serge	2714	return -EINVAL;
		2715	}
		2716
		2717	mutex_lock(&dev->struct_mutex);
5060	serge	2718	ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
		2719	if (ret == 0)
		2720	i915_gem_track_fb(old_obj, obj,
		2721	INTEL_FRONTBUFFER_PRIMARY(pipe));
		2722	mutex_unlock(&dev->struct_mutex);
4280	Serge	2723	if (ret != 0) {
		2724	DRM_ERROR("pin & fence failed\n");
		2725	return ret;
		2726	}
2327	Serge	2727
4560	Serge	2728	/*
		2729	* Update pipe size and adjust fitter if needed: the reason for this is
		2730	* that in compute_mode_changes we check the native mode (not the pfit
		2731	* mode) to see if we can flip rather than do a full mode set. In the
		2732	* fastboot case, we'll flip, but if we don't update the pipesrc and
		2733	* pfit state, we'll end up with a big fb scanned out into the wrong
		2734	* sized surface.
		2735	*
		2736	* To fix this properly, we need to hoist the checks up into
		2737	* compute_mode_changes (or above), check the actual pfit state and
		2738	* whether the platform allows pfit disable with pipe active, and only
		2739	* then update the pipesrc and pfit state, even on the flip path.
		2740	*/
5060	serge	2741	if (i915.fastboot) {
4560	Serge	2742	const struct drm_display_mode *adjusted_mode =
		2743	&intel_crtc->config.adjusted_mode;
		2744
4280	Serge	2745	I915_WRITE(PIPESRC(intel_crtc->pipe),
4560	Serge	2746	((adjusted_mode->crtc_hdisplay - 1) << 16) \|
		2747	(adjusted_mode->crtc_vdisplay - 1));
4280	Serge	2748	if (!intel_crtc->config.pch_pfit.enabled &&
		2749	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\|
		2750	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
		2751	I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
		2752	I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
		2753	I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
		2754	}
4560	Serge	2755	intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
		2756	intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
4280	Serge	2757	}
3031	serge	2758
5060	serge	2759	dev_priv->display.update_primary_plane(crtc, fb, x, y);
2327	Serge	2760
5060	serge	2761	if (intel_crtc->active)
		2762	intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
		2763
		2764	crtc->primary->fb = fb;
3031	serge	2765	crtc->x = x;
		2766	crtc->y = y;
		2767
		2768	if (old_fb) {
4104	Serge	2769	if (intel_crtc->active && old_fb != fb)
3031	serge	2770	intel_wait_for_vblank(dev, intel_crtc->pipe);
5060	serge	2771	mutex_lock(&dev->struct_mutex);
		2772	intel_unpin_fb_obj(old_obj);
		2773	mutex_unlock(&dev->struct_mutex);
3031	serge	2774	}
		2775
5060	serge	2776	mutex_lock(&dev->struct_mutex);
3031	serge	2777	intel_update_fbc(dev);
2336	Serge	2778	mutex_unlock(&dev->struct_mutex);
2327	Serge	2779
2336	Serge	2780	return 0;
2327	Serge	2781	}
		2782
		2783	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2784	{
		2785	struct drm_device *dev = crtc->dev;
		2786	struct drm_i915_private *dev_priv = dev->dev_private;
		2787	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2788	int pipe = intel_crtc->pipe;
		2789	u32 reg, temp;
		2790
		2791	/* enable normal train */
		2792	reg = FDI_TX_CTL(pipe);
		2793	temp = I915_READ(reg);
		2794	if (IS_IVYBRIDGE(dev)) {
		2795	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2796	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2797	} else {
		2798	temp &= ~FDI_LINK_TRAIN_NONE;
		2799	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2800	}
		2801	I915_WRITE(reg, temp);
		2802
		2803	reg = FDI_RX_CTL(pipe);
		2804	temp = I915_READ(reg);
		2805	if (HAS_PCH_CPT(dev)) {
		2806	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2807	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2808	} else {
		2809	temp &= ~FDI_LINK_TRAIN_NONE;
		2810	temp \|= FDI_LINK_TRAIN_NONE;
		2811	}
		2812	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2813
		2814	/* wait one idle pattern time */
		2815	POSTING_READ(reg);
		2816	udelay(1000);
		2817
		2818	/* IVB wants error correction enabled */
		2819	if (IS_IVYBRIDGE(dev))
		2820	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2821	FDI_FE_ERRC_ENABLE);
		2822	}
		2823
4280	Serge	2824	static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
4104	Serge	2825	{
4280	Serge	2826	return crtc->base.enabled && crtc->active &&
		2827	crtc->config.has_pch_encoder;
4104	Serge	2828	}
		2829
3243	Serge	2830	static void ivb_modeset_global_resources(struct drm_device *dev)
2327	Serge	2831	{
		2832	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2833	struct intel_crtc *pipe_B_crtc =
		2834	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		2835	struct intel_crtc *pipe_C_crtc =
		2836	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
		2837	uint32_t temp;
2327	Serge	2838
4104	Serge	2839	/*
		2840	* When everything is off disable fdi C so that we could enable fdi B
		2841	* with all lanes. Note that we don't care about enabled pipes without
		2842	* an enabled pch encoder.
		2843	*/
		2844	if (!pipe_has_enabled_pch(pipe_B_crtc) &&
		2845	!pipe_has_enabled_pch(pipe_C_crtc)) {
3243	Serge	2846	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		2847	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		2848
		2849	temp = I915_READ(SOUTH_CHICKEN1);
		2850	temp &= ~FDI_BC_BIFURCATION_SELECT;
		2851	DRM_DEBUG_KMS("disabling fdi C rx\n");
		2852	I915_WRITE(SOUTH_CHICKEN1, temp);
		2853	}
2327	Serge	2854	}
		2855
		2856	/* The FDI link training functions for ILK/Ibexpeak. */
		2857	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2858	{
		2859	struct drm_device *dev = crtc->dev;
		2860	struct drm_i915_private *dev_priv = dev->dev_private;
		2861	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2862	int pipe = intel_crtc->pipe;
		2863	u32 reg, temp, tries;
		2864
5060	serge	2865	/* FDI needs bits from pipe first */
2327	Serge	2866	assert_pipe_enabled(dev_priv, pipe);
		2867
		2868	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2869	for train result */
		2870	reg = FDI_RX_IMR(pipe);
		2871	temp = I915_READ(reg);
		2872	temp &= ~FDI_RX_SYMBOL_LOCK;
		2873	temp &= ~FDI_RX_BIT_LOCK;
		2874	I915_WRITE(reg, temp);
		2875	I915_READ(reg);
		2876	udelay(150);
		2877
		2878	/* enable CPU FDI TX and PCH FDI RX */
		2879	reg = FDI_TX_CTL(pipe);
		2880	temp = I915_READ(reg);
4104	Serge	2881	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2882	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2883	temp &= ~FDI_LINK_TRAIN_NONE;
		2884	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2885	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2886
		2887	reg = FDI_RX_CTL(pipe);
		2888	temp = I915_READ(reg);
		2889	temp &= ~FDI_LINK_TRAIN_NONE;
		2890	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2891	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2892
		2893	POSTING_READ(reg);
		2894	udelay(150);
		2895
		2896	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2897	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2898	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2899	FDI_RX_PHASE_SYNC_POINTER_EN);
		2900
		2901	reg = FDI_RX_IIR(pipe);
		2902	for (tries = 0; tries < 5; tries++) {
		2903	temp = I915_READ(reg);
		2904	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2905
		2906	if ((temp & FDI_RX_BIT_LOCK)) {
		2907	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2908	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2909	break;
		2910	}
		2911	}
		2912	if (tries == 5)
		2913	DRM_ERROR("FDI train 1 fail!\n");
		2914
		2915	/* Train 2 */
		2916	reg = FDI_TX_CTL(pipe);
		2917	temp = I915_READ(reg);
		2918	temp &= ~FDI_LINK_TRAIN_NONE;
		2919	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2920	I915_WRITE(reg, temp);
		2921
		2922	reg = FDI_RX_CTL(pipe);
		2923	temp = I915_READ(reg);
		2924	temp &= ~FDI_LINK_TRAIN_NONE;
		2925	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2926	I915_WRITE(reg, temp);
		2927
		2928	POSTING_READ(reg);
		2929	udelay(150);
		2930
		2931	reg = FDI_RX_IIR(pipe);
		2932	for (tries = 0; tries < 5; tries++) {
		2933	temp = I915_READ(reg);
		2934	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2935
		2936	if (temp & FDI_RX_SYMBOL_LOCK) {
		2937	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2938	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2939	break;
		2940	}
		2941	}
		2942	if (tries == 5)
		2943	DRM_ERROR("FDI train 2 fail!\n");
		2944
		2945	DRM_DEBUG_KMS("FDI train done\n");
		2946
		2947	}
		2948
2342	Serge	2949	static const int snb_b_fdi_train_param[] = {
2327	Serge	2950	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2951	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2952	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2953	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2954	};
		2955
		2956	/* The FDI link training functions for SNB/Cougarpoint. */
		2957	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2958	{
		2959	struct drm_device *dev = crtc->dev;
		2960	struct drm_i915_private *dev_priv = dev->dev_private;
		2961	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2962	int pipe = intel_crtc->pipe;
3031	serge	2963	u32 reg, temp, i, retry;
2327	Serge	2964
		2965	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2966	for train result */
		2967	reg = FDI_RX_IMR(pipe);
		2968	temp = I915_READ(reg);
		2969	temp &= ~FDI_RX_SYMBOL_LOCK;
		2970	temp &= ~FDI_RX_BIT_LOCK;
		2971	I915_WRITE(reg, temp);
		2972
		2973	POSTING_READ(reg);
		2974	udelay(150);
		2975
		2976	/* enable CPU FDI TX and PCH FDI RX */
		2977	reg = FDI_TX_CTL(pipe);
		2978	temp = I915_READ(reg);
4104	Serge	2979	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2980	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2981	temp &= ~FDI_LINK_TRAIN_NONE;
		2982	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2983	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2984	/* SNB-B */
		2985	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2986	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2987
3243	Serge	2988	I915_WRITE(FDI_RX_MISC(pipe),
		2989	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2990
2327	Serge	2991	reg = FDI_RX_CTL(pipe);
		2992	temp = I915_READ(reg);
		2993	if (HAS_PCH_CPT(dev)) {
		2994	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2995	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2996	} else {
		2997	temp &= ~FDI_LINK_TRAIN_NONE;
		2998	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2999	}
		3000	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		3001
		3002	POSTING_READ(reg);
		3003	udelay(150);
		3004
2342	Serge	3005	for (i = 0; i < 4; i++) {
2327	Serge	3006	reg = FDI_TX_CTL(pipe);
		3007	temp = I915_READ(reg);
		3008	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		3009	temp \|= snb_b_fdi_train_param[i];
		3010	I915_WRITE(reg, temp);
		3011
		3012	POSTING_READ(reg);
		3013	udelay(500);
		3014
3031	serge	3015	for (retry = 0; retry < 5; retry++) {
2327	Serge	3016	reg = FDI_RX_IIR(pipe);
		3017	temp = I915_READ(reg);
		3018	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		3019	if (temp & FDI_RX_BIT_LOCK) {
		3020	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		3021	DRM_DEBUG_KMS("FDI train 1 done.\n");
		3022	break;
		3023	}
3031	serge	3024	udelay(50);
		3025	}
		3026	if (retry < 5)
		3027	break;
2327	Serge	3028	}
		3029	if (i == 4)
		3030	DRM_ERROR("FDI train 1 fail!\n");
		3031
		3032	/* Train 2 */
		3033	reg = FDI_TX_CTL(pipe);
		3034	temp = I915_READ(reg);
		3035	temp &= ~FDI_LINK_TRAIN_NONE;
		3036	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		3037	if (IS_GEN6(dev)) {
		3038	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		3039	/* SNB-B */
		3040	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		3041	}
		3042	I915_WRITE(reg, temp);
		3043
		3044	reg = FDI_RX_CTL(pipe);
		3045	temp = I915_READ(reg);
		3046	if (HAS_PCH_CPT(dev)) {
		3047	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3048	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		3049	} else {
		3050	temp &= ~FDI_LINK_TRAIN_NONE;
		3051	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		3052	}
		3053	I915_WRITE(reg, temp);
		3054
		3055	POSTING_READ(reg);
		3056	udelay(150);
		3057
2342	Serge	3058	for (i = 0; i < 4; i++) {
2327	Serge	3059	reg = FDI_TX_CTL(pipe);
		3060	temp = I915_READ(reg);
		3061	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		3062	temp \|= snb_b_fdi_train_param[i];
		3063	I915_WRITE(reg, temp);
		3064
		3065	POSTING_READ(reg);
		3066	udelay(500);
		3067
3031	serge	3068	for (retry = 0; retry < 5; retry++) {
2327	Serge	3069	reg = FDI_RX_IIR(pipe);
		3070	temp = I915_READ(reg);
		3071	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		3072	if (temp & FDI_RX_SYMBOL_LOCK) {
		3073	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		3074	DRM_DEBUG_KMS("FDI train 2 done.\n");
		3075	break;
		3076	}
3031	serge	3077	udelay(50);
		3078	}
		3079	if (retry < 5)
		3080	break;
2327	Serge	3081	}
		3082	if (i == 4)
		3083	DRM_ERROR("FDI train 2 fail!\n");
		3084
		3085	DRM_DEBUG_KMS("FDI train done.\n");
		3086	}
		3087
		3088	/* Manual link training for Ivy Bridge A0 parts */
		3089	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		3090	{
		3091	struct drm_device *dev = crtc->dev;
		3092	struct drm_i915_private *dev_priv = dev->dev_private;
		3093	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3094	int pipe = intel_crtc->pipe;
4104	Serge	3095	u32 reg, temp, i, j;
2327	Serge	3096
		3097	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		3098	for train result */
		3099	reg = FDI_RX_IMR(pipe);
		3100	temp = I915_READ(reg);
		3101	temp &= ~FDI_RX_SYMBOL_LOCK;
		3102	temp &= ~FDI_RX_BIT_LOCK;
		3103	I915_WRITE(reg, temp);
		3104
		3105	POSTING_READ(reg);
		3106	udelay(150);
		3107
3243	Serge	3108	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		3109	I915_READ(FDI_RX_IIR(pipe)));
		3110
4104	Serge	3111	/* Try each vswing and preemphasis setting twice before moving on */
		3112	for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
		3113	/* disable first in case we need to retry */
		3114	reg = FDI_TX_CTL(pipe);
		3115	temp = I915_READ(reg);
		3116	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		3117	temp &= ~FDI_TX_ENABLE;
		3118	I915_WRITE(reg, temp);
		3119
		3120	reg = FDI_RX_CTL(pipe);
		3121	temp = I915_READ(reg);
		3122	temp &= ~FDI_LINK_TRAIN_AUTO;
		3123	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3124	temp &= ~FDI_RX_ENABLE;
		3125	I915_WRITE(reg, temp);
		3126
2327	Serge	3127	/* enable CPU FDI TX and PCH FDI RX */
		3128	reg = FDI_TX_CTL(pipe);
		3129	temp = I915_READ(reg);
4104	Serge	3130	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		3131	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	3132	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		3133	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4104	Serge	3134	temp \|= snb_b_fdi_train_param[j/2];
2342	Serge	3135	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	3136	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		3137
3243	Serge	3138	I915_WRITE(FDI_RX_MISC(pipe),
		3139	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		3140
2327	Serge	3141	reg = FDI_RX_CTL(pipe);
		3142	temp = I915_READ(reg);
		3143	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342	Serge	3144	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	3145	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		3146
		3147	POSTING_READ(reg);
4104	Serge	3148	udelay(1); /* should be 0.5us */
2327	Serge	3149
2342	Serge	3150	for (i = 0; i < 4; i++) {
2327	Serge	3151	reg = FDI_RX_IIR(pipe);
		3152	temp = I915_READ(reg);
		3153	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		3154
		3155	if (temp & FDI_RX_BIT_LOCK \|\|
		3156	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		3157	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
4104	Serge	3158	DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
		3159	i);
2327	Serge	3160	break;
		3161	}
4104	Serge	3162	udelay(1); /* should be 0.5us */
		3163	}
		3164	if (i == 4) {
		3165	DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
		3166	continue;
2327	Serge	3167	}
		3168
		3169	/* Train 2 */
		3170	reg = FDI_TX_CTL(pipe);
		3171	temp = I915_READ(reg);
		3172	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		3173	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		3174	I915_WRITE(reg, temp);
		3175
		3176	reg = FDI_RX_CTL(pipe);
		3177	temp = I915_READ(reg);
		3178	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3179	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		3180	I915_WRITE(reg, temp);
		3181
		3182	POSTING_READ(reg);
4104	Serge	3183	udelay(2); /* should be 1.5us */
2327	Serge	3184
2342	Serge	3185	for (i = 0; i < 4; i++) {
2327	Serge	3186	reg = FDI_RX_IIR(pipe);
		3187	temp = I915_READ(reg);
		3188	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		3189
4104	Serge	3190	if (temp & FDI_RX_SYMBOL_LOCK \|\|
		3191	(I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2327	Serge	3192	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
4104	Serge	3193	DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
		3194	i);
		3195	goto train_done;
2327	Serge	3196	}
4104	Serge	3197	udelay(2); /* should be 1.5us */
2327	Serge	3198	}
		3199	if (i == 4)
4104	Serge	3200	DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
		3201	}
2327	Serge	3202
4104	Serge	3203	train_done:
2327	Serge	3204	DRM_DEBUG_KMS("FDI train done.\n");
		3205	}
		3206
3031	serge	3207	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	3208	{
3031	serge	3209	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	3210	struct drm_i915_private *dev_priv = dev->dev_private;
		3211	int pipe = intel_crtc->pipe;
		3212	u32 reg, temp;
		3213
		3214
		3215	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		3216	reg = FDI_RX_CTL(pipe);
		3217	temp = I915_READ(reg);
4104	Serge	3218	temp &= ~(FDI_DP_PORT_WIDTH_MASK \| (0x7 << 16));
		3219	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3480	Serge	3220	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	3221	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		3222
		3223	POSTING_READ(reg);
		3224	udelay(200);
		3225
		3226	/* Switch from Rawclk to PCDclk */
		3227	temp = I915_READ(reg);
		3228	I915_WRITE(reg, temp \| FDI_PCDCLK);
		3229
		3230	POSTING_READ(reg);
		3231	udelay(200);
		3232
		3233	/* Enable CPU FDI TX PLL, always on for Ironlake */
		3234	reg = FDI_TX_CTL(pipe);
		3235	temp = I915_READ(reg);
		3236	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		3237	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		3238
		3239	POSTING_READ(reg);
		3240	udelay(100);
		3241	}
		3242	}
		3243
3031	serge	3244	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		3245	{
		3246	struct drm_device *dev = intel_crtc->base.dev;
		3247	struct drm_i915_private *dev_priv = dev->dev_private;
		3248	int pipe = intel_crtc->pipe;
		3249	u32 reg, temp;
		3250
		3251	/* Switch from PCDclk to Rawclk */
		3252	reg = FDI_RX_CTL(pipe);
		3253	temp = I915_READ(reg);
		3254	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		3255
		3256	/* Disable CPU FDI TX PLL */
		3257	reg = FDI_TX_CTL(pipe);
		3258	temp = I915_READ(reg);
		3259	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		3260
		3261	POSTING_READ(reg);
		3262	udelay(100);
		3263
		3264	reg = FDI_RX_CTL(pipe);
		3265	temp = I915_READ(reg);
		3266	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		3267
		3268	/* Wait for the clocks to turn off. */
		3269	POSTING_READ(reg);
		3270	udelay(100);
		3271	}
		3272
2327	Serge	3273	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		3274	{
		3275	struct drm_device *dev = crtc->dev;
		3276	struct drm_i915_private *dev_priv = dev->dev_private;
		3277	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3278	int pipe = intel_crtc->pipe;
		3279	u32 reg, temp;
		3280
		3281	/* disable CPU FDI tx and PCH FDI rx */
		3282	reg = FDI_TX_CTL(pipe);
		3283	temp = I915_READ(reg);
		3284	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		3285	POSTING_READ(reg);
		3286
		3287	reg = FDI_RX_CTL(pipe);
		3288	temp = I915_READ(reg);
		3289	temp &= ~(0x7 << 16);
3480	Serge	3290	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	3291	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		3292
		3293	POSTING_READ(reg);
		3294	udelay(100);
		3295
		3296	/* Ironlake workaround, disable clock pointer after downing FDI */
5060	serge	3297	if (HAS_PCH_IBX(dev))
2327	Serge	3298	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		3299
		3300	/* still set train pattern 1 */
		3301	reg = FDI_TX_CTL(pipe);
		3302	temp = I915_READ(reg);
		3303	temp &= ~FDI_LINK_TRAIN_NONE;
		3304	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		3305	I915_WRITE(reg, temp);
		3306
		3307	reg = FDI_RX_CTL(pipe);
		3308	temp = I915_READ(reg);
		3309	if (HAS_PCH_CPT(dev)) {
		3310	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		3311	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		3312	} else {
		3313	temp &= ~FDI_LINK_TRAIN_NONE;
		3314	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		3315	}
		3316	/* BPC in FDI rx is consistent with that in PIPECONF */
		3317	temp &= ~(0x07 << 16);
3480	Serge	3318	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	3319	I915_WRITE(reg, temp);
		3320
		3321	POSTING_READ(reg);
		3322	udelay(100);
		3323	}
		3324
5060	serge	3325	bool intel_has_pending_fb_unpin(struct drm_device *dev)
2327	Serge	3326	{
5060	serge	3327	struct intel_crtc *crtc;
2327	Serge	3328
5060	serge	3329	/* Note that we don't need to be called with mode_config.lock here
		3330	* as our list of CRTC objects is static for the lifetime of the
		3331	* device and so cannot disappear as we iterate. Similarly, we can
		3332	* happily treat the predicates as racy, atomic checks as userspace
		3333	* cannot claim and pin a new fb without at least acquring the
		3334	* struct_mutex and so serialising with us.
		3335	*/
		3336	for_each_intel_crtc(dev, crtc) {
		3337	if (atomic_read(&crtc->unpin_work_count) == 0)
		3338	continue;
2327	Serge	3339
5060	serge	3340	if (crtc->unpin_work)
		3341	intel_wait_for_vblank(dev, crtc->pipe);
3031	serge	3342
5060	serge	3343	return true;
		3344	}
		3345
		3346	return false;
2327	Serge	3347	}
		3348
3031	serge	3349	#if 0
5060	serge	3350	void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2327	Serge	3351	{
3031	serge	3352	struct drm_device *dev = crtc->dev;
		3353	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	3354
5060	serge	3355	if (crtc->primary->fb == NULL)
2327	Serge	3356	return;
		3357
3480	Serge	3358	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
		3359
5060	serge	3360	WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
		3361	!intel_crtc_has_pending_flip(crtc),
		3362	60*HZ) == 0);
3031	serge	3363
		3364	mutex_lock(&dev->struct_mutex);
5060	serge	3365	intel_finish_fb(crtc->primary->fb);
3031	serge	3366	mutex_unlock(&dev->struct_mutex);
2327	Serge	3367	}
3031	serge	3368	#endif
2327	Serge	3369
3031	serge	3370	/* Program iCLKIP clock to the desired frequency */
		3371	static void lpt_program_iclkip(struct drm_crtc *crtc)
		3372	{
		3373	struct drm_device *dev = crtc->dev;
		3374	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	3375	int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3031	serge	3376	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		3377	u32 temp;
		3378
3480	Serge	3379	mutex_lock(&dev_priv->dpio_lock);
		3380
3031	serge	3381	/* It is necessary to ungate the pixclk gate prior to programming
		3382	* the divisors, and gate it back when it is done.
		3383	*/
		3384	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		3385
		3386	/* Disable SSCCTL */
		3387	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3243	Serge	3388	intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) \|
		3389	SBI_SSCCTL_DISABLE,
		3390	SBI_ICLK);
3031	serge	3391
		3392	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
4560	Serge	3393	if (clock == 20000) {
3031	serge	3394	auxdiv = 1;
		3395	divsel = 0x41;
		3396	phaseinc = 0x20;
		3397	} else {
		3398	/* The iCLK virtual clock root frequency is in MHz,
4560	Serge	3399	* but the adjusted_mode->crtc_clock in in KHz. To get the
		3400	* divisors, it is necessary to divide one by another, so we
3031	serge	3401	* convert the virtual clock precision to KHz here for higher
		3402	* precision.
		3403	*/
		3404	u32 iclk_virtual_root_freq = 172800 * 1000;
		3405	u32 iclk_pi_range = 64;
		3406	u32 desired_divisor, msb_divisor_value, pi_value;
		3407
4560	Serge	3408	desired_divisor = (iclk_virtual_root_freq / clock);
3031	serge	3409	msb_divisor_value = desired_divisor / iclk_pi_range;
		3410	pi_value = desired_divisor % iclk_pi_range;
		3411
		3412	auxdiv = 0;
		3413	divsel = msb_divisor_value - 2;
		3414	phaseinc = pi_value;
		3415	}
		3416
		3417	/* This should not happen with any sane values */
		3418	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		3419	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		3420	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		3421	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		3422
		3423	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4560	Serge	3424	clock,
3031	serge	3425	auxdiv,
		3426	divsel,
		3427	phasedir,
		3428	phaseinc);
		3429
		3430	/* Program SSCDIVINTPHASE6 */
3243	Serge	3431	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3031	serge	3432	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		3433	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		3434	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		3435	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		3436	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		3437	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
3243	Serge	3438	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031	serge	3439
		3440	/* Program SSCAUXDIV */
3243	Serge	3441	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3031	serge	3442	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		3443	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3243	Serge	3444	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3031	serge	3445
		3446	/* Enable modulator and associated divider */
3243	Serge	3447	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3031	serge	3448	temp &= ~SBI_SSCCTL_DISABLE;
3243	Serge	3449	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3031	serge	3450
		3451	/* Wait for initialization time */
		3452	udelay(24);
		3453
		3454	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3480	Serge	3455
		3456	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	3457	}
		3458
4104	Serge	3459	static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
		3460	enum pipe pch_transcoder)
		3461	{
		3462	struct drm_device *dev = crtc->base.dev;
		3463	struct drm_i915_private *dev_priv = dev->dev_private;
		3464	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
		3465
		3466	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
		3467	I915_READ(HTOTAL(cpu_transcoder)));
		3468	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
		3469	I915_READ(HBLANK(cpu_transcoder)));
		3470	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
		3471	I915_READ(HSYNC(cpu_transcoder)));
		3472
		3473	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
		3474	I915_READ(VTOTAL(cpu_transcoder)));
		3475	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
		3476	I915_READ(VBLANK(cpu_transcoder)));
		3477	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
		3478	I915_READ(VSYNC(cpu_transcoder)));
		3479	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
		3480	I915_READ(VSYNCSHIFT(cpu_transcoder)));
		3481	}
		3482
4280	Serge	3483	static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
		3484	{
		3485	struct drm_i915_private *dev_priv = dev->dev_private;
		3486	uint32_t temp;
		3487
		3488	temp = I915_READ(SOUTH_CHICKEN1);
		3489	if (temp & FDI_BC_BIFURCATION_SELECT)
		3490	return;
		3491
		3492	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		3493	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		3494
		3495	temp \|= FDI_BC_BIFURCATION_SELECT;
		3496	DRM_DEBUG_KMS("enabling fdi C rx\n");
		3497	I915_WRITE(SOUTH_CHICKEN1, temp);
		3498	POSTING_READ(SOUTH_CHICKEN1);
		3499	}
		3500
		3501	static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
		3502	{
		3503	struct drm_device *dev = intel_crtc->base.dev;
		3504	struct drm_i915_private *dev_priv = dev->dev_private;
		3505
		3506	switch (intel_crtc->pipe) {
		3507	case PIPE_A:
		3508	break;
		3509	case PIPE_B:
		3510	if (intel_crtc->config.fdi_lanes > 2)
		3511	WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		3512	else
		3513	cpt_enable_fdi_bc_bifurcation(dev);
		3514
		3515	break;
		3516	case PIPE_C:
		3517	cpt_enable_fdi_bc_bifurcation(dev);
		3518
		3519	break;
		3520	default:
		3521	BUG();
		3522	}
		3523	}
		3524
2327	Serge	3525	/*
		3526	* Enable PCH resources required for PCH ports:
		3527	* - PCH PLLs
		3528	* - FDI training & RX/TX
		3529	* - update transcoder timings
		3530	* - DP transcoding bits
		3531	* - transcoder
		3532	*/
		3533	static void ironlake_pch_enable(struct drm_crtc *crtc)
		3534	{
		3535	struct drm_device *dev = crtc->dev;
		3536	struct drm_i915_private *dev_priv = dev->dev_private;
		3537	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3538	int pipe = intel_crtc->pipe;
3031	serge	3539	u32 reg, temp;
2327	Serge	3540
4104	Serge	3541	assert_pch_transcoder_disabled(dev_priv, pipe);
3031	serge	3542
4280	Serge	3543	if (IS_IVYBRIDGE(dev))
		3544	ivybridge_update_fdi_bc_bifurcation(intel_crtc);
		3545
3243	Serge	3546	/* Write the TU size bits before fdi link training, so that error
		3547	* detection works. */
		3548	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		3549	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		3550
2327	Serge	3551	/* For PCH output, training FDI link */
		3552	dev_priv->display.fdi_link_train(crtc);
		3553
4104	Serge	3554	/* We need to program the right clock selection before writing the pixel
		3555	* mutliplier into the DPLL. */
3243	Serge	3556	if (HAS_PCH_CPT(dev)) {
3031	serge	3557	u32 sel;
2342	Serge	3558
2327	Serge	3559	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3560	temp \|= TRANS_DPLL_ENABLE(pipe);
		3561	sel = TRANS_DPLLB_SEL(pipe);
		3562	if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3031	serge	3563	temp \|= sel;
		3564	else
		3565	temp &= ~sel;
2327	Serge	3566	I915_WRITE(PCH_DPLL_SEL, temp);
		3567	}
		3568
4104	Serge	3569	/* XXX: pch pll's can be enabled any time before we enable the PCH
		3570	* transcoder, and we actually should do this to not upset any PCH
		3571	* transcoder that already use the clock when we share it.
		3572	*
		3573	* Note that enable_shared_dpll tries to do the right thing, but
		3574	* get_shared_dpll unconditionally resets the pll - we need that to have
		3575	* the right LVDS enable sequence. */
5060	serge	3576	intel_enable_shared_dpll(intel_crtc);
4104	Serge	3577
2327	Serge	3578	/* set transcoder timing, panel must allow it */
		3579	assert_panel_unlocked(dev_priv, pipe);
4104	Serge	3580	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2327	Serge	3581
		3582	intel_fdi_normal_train(crtc);
		3583
		3584	/* For PCH DP, enable TRANS_DP_CTL */
		3585	if (HAS_PCH_CPT(dev) &&
2342	Serge	3586	(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		3587	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3480	Serge	3588	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2327	Serge	3589	reg = TRANS_DP_CTL(pipe);
		3590	temp = I915_READ(reg);
		3591	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		3592	TRANS_DP_SYNC_MASK \|
		3593	TRANS_DP_BPC_MASK);
		3594	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		3595	TRANS_DP_ENH_FRAMING);
		3596	temp \|= bpc << 9; /* same format but at 11:9 */
		3597
		3598	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		3599	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		3600	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		3601	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		3602
		3603	switch (intel_trans_dp_port_sel(crtc)) {
		3604	case PCH_DP_B:
		3605	temp \|= TRANS_DP_PORT_SEL_B;
		3606	break;
		3607	case PCH_DP_C:
		3608	temp \|= TRANS_DP_PORT_SEL_C;
		3609	break;
		3610	case PCH_DP_D:
		3611	temp \|= TRANS_DP_PORT_SEL_D;
		3612	break;
		3613	default:
3243	Serge	3614	BUG();
2327	Serge	3615	}
		3616
		3617	I915_WRITE(reg, temp);
		3618	}
		3619
3243	Serge	3620	ironlake_enable_pch_transcoder(dev_priv, pipe);
2327	Serge	3621	}
		3622
3243	Serge	3623	static void lpt_pch_enable(struct drm_crtc *crtc)
		3624	{
		3625	struct drm_device *dev = crtc->dev;
		3626	struct drm_i915_private *dev_priv = dev->dev_private;
		3627	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	3628	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3629
4104	Serge	3630	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3243	Serge	3631
		3632	lpt_program_iclkip(crtc);
		3633
		3634	/* Set transcoder timing. */
4104	Serge	3635	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3243	Serge	3636
		3637	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
		3638	}
		3639
5060	serge	3640	void intel_put_shared_dpll(struct intel_crtc *crtc)
3031	serge	3641	{
4104	Serge	3642	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3031	serge	3643
		3644	if (pll == NULL)
		3645	return;
		3646
		3647	if (pll->refcount == 0) {
4104	Serge	3648	WARN(1, "bad %s refcount\n", pll->name);
3031	serge	3649	return;
		3650	}
		3651
4104	Serge	3652	if (--pll->refcount == 0) {
		3653	WARN_ON(pll->on);
		3654	WARN_ON(pll->active);
		3655	}
		3656
		3657	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3031	serge	3658	}
		3659
5060	serge	3660	struct intel_shared_dpll intel_get_shared_dpll(struct intel_crtc crtc)
3031	serge	3661	{
4104	Serge	3662	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3663	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
		3664	enum intel_dpll_id i;
3031	serge	3665
		3666	if (pll) {
4104	Serge	3667	DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
		3668	crtc->base.base.id, pll->name);
		3669	intel_put_shared_dpll(crtc);
3031	serge	3670	}
		3671
		3672	if (HAS_PCH_IBX(dev_priv->dev)) {
		3673	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4104	Serge	3674	i = (enum intel_dpll_id) crtc->pipe;
		3675	pll = &dev_priv->shared_dplls[i];
3031	serge	3676
4104	Serge	3677	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
		3678	crtc->base.base.id, pll->name);
3031	serge	3679
5060	serge	3680	WARN_ON(pll->refcount);
		3681
3031	serge	3682	goto found;
		3683	}
		3684
4104	Serge	3685	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3686	pll = &dev_priv->shared_dplls[i];
3031	serge	3687
		3688	/* Only want to check enabled timings first */
		3689	if (pll->refcount == 0)
		3690	continue;
		3691
4104	Serge	3692	if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
		3693	sizeof(pll->hw_state)) == 0) {
		3694	DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
		3695	crtc->base.base.id,
		3696	pll->name, pll->refcount, pll->active);
3031	serge	3697
		3698	goto found;
		3699	}
		3700	}
		3701
		3702	/* Ok no matching timings, maybe there's a free one? */
4104	Serge	3703	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3704	pll = &dev_priv->shared_dplls[i];
3031	serge	3705	if (pll->refcount == 0) {
4104	Serge	3706	DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
		3707	crtc->base.base.id, pll->name);
3031	serge	3708	goto found;
		3709	}
		3710	}
		3711
		3712	return NULL;
		3713
		3714	found:
5060	serge	3715	if (pll->refcount == 0)
		3716	pll->hw_state = crtc->config.dpll_hw_state;
		3717
4104	Serge	3718	crtc->config.shared_dpll = i;
		3719	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
		3720	pipe_name(crtc->pipe));
		3721
3031	serge	3722	pll->refcount++;
		3723
		3724	return pll;
		3725	}
		3726
4104	Serge	3727	static void cpt_verify_modeset(struct drm_device *dev, int pipe)
2342	Serge	3728	{
		3729	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3730	int dslreg = PIPEDSL(pipe);
2342	Serge	3731	u32 temp;
		3732
		3733	temp = I915_READ(dslreg);
		3734	udelay(500);
		3735	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		3736	if (wait_for(I915_READ(dslreg) != temp, 5))
4104	Serge	3737	DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
2342	Serge	3738	}
		3739	}
		3740
4104	Serge	3741	static void ironlake_pfit_enable(struct intel_crtc *crtc)
		3742	{
		3743	struct drm_device *dev = crtc->base.dev;
		3744	struct drm_i915_private *dev_priv = dev->dev_private;
		3745	int pipe = crtc->pipe;
		3746
		3747	if (crtc->config.pch_pfit.enabled) {
		3748	/* Force use of hard-coded filter coefficients
		3749	* as some pre-programmed values are broken,
		3750	* e.g. x201.
		3751	*/
		3752	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		3753	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3 \|
		3754	PF_PIPE_SEL_IVB(pipe));
		3755	else
		3756	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		3757	I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
		3758	I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
		3759	}
		3760	}
		3761
		3762	static void intel_enable_planes(struct drm_crtc *crtc)
		3763	{
		3764	struct drm_device *dev = crtc->dev;
		3765	enum pipe pipe = to_intel_crtc(crtc)->pipe;
5060	serge	3766	struct drm_plane *plane;
4104	Serge	3767	struct intel_plane *intel_plane;
		3768
5060	serge	3769	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
		3770	intel_plane = to_intel_plane(plane);
4104	Serge	3771	if (intel_plane->pipe == pipe)
		3772	intel_plane_restore(&intel_plane->base);
5060	serge	3773	}
4104	Serge	3774	}
		3775
		3776	static void intel_disable_planes(struct drm_crtc *crtc)
		3777	{
		3778	struct drm_device *dev = crtc->dev;
		3779	enum pipe pipe = to_intel_crtc(crtc)->pipe;
5060	serge	3780	struct drm_plane *plane;
4104	Serge	3781	struct intel_plane *intel_plane;
		3782
5060	serge	3783	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
		3784	intel_plane = to_intel_plane(plane);
4104	Serge	3785	if (intel_plane->pipe == pipe)
		3786	intel_plane_disable(&intel_plane->base);
5060	serge	3787	}
4104	Serge	3788	}
		3789
4560	Serge	3790	void hsw_enable_ips(struct intel_crtc *crtc)
		3791	{
5060	serge	3792	struct drm_device *dev = crtc->base.dev;
		3793	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	3794
		3795	if (!crtc->config.ips_enabled)
		3796	return;
		3797
5060	serge	3798	/* We can only enable IPS after we enable a plane and wait for a vblank */
		3799	intel_wait_for_vblank(dev, crtc->pipe);
		3800
4560	Serge	3801	assert_plane_enabled(dev_priv, crtc->plane);
5060	serge	3802	if (IS_BROADWELL(dev)) {
4560	Serge	3803	mutex_lock(&dev_priv->rps.hw_lock);
		3804	WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
		3805	mutex_unlock(&dev_priv->rps.hw_lock);
		3806	/* Quoting Art Runyan: "its not safe to expect any particular
		3807	* value in IPS_CTL bit 31 after enabling IPS through the
		3808	* mailbox." Moreover, the mailbox may return a bogus state,
		3809	* so we need to just enable it and continue on.
		3810	*/
		3811	} else {
		3812	I915_WRITE(IPS_CTL, IPS_ENABLE);
		3813	/* The bit only becomes 1 in the next vblank, so this wait here
		3814	* is essentially intel_wait_for_vblank. If we don't have this
		3815	* and don't wait for vblanks until the end of crtc_enable, then
		3816	* the HW state readout code will complain that the expected
		3817	* IPS_CTL value is not the one we read. */
		3818	if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
		3819	DRM_ERROR("Timed out waiting for IPS enable\n");
		3820	}
		3821	}
		3822
		3823	void hsw_disable_ips(struct intel_crtc *crtc)
		3824	{
		3825	struct drm_device *dev = crtc->base.dev;
		3826	struct drm_i915_private *dev_priv = dev->dev_private;
		3827
		3828	if (!crtc->config.ips_enabled)
		3829	return;
		3830
		3831	assert_plane_enabled(dev_priv, crtc->plane);
5060	serge	3832	if (IS_BROADWELL(dev)) {
4560	Serge	3833	mutex_lock(&dev_priv->rps.hw_lock);
		3834	WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
		3835	mutex_unlock(&dev_priv->rps.hw_lock);
5060	serge	3836	/* wait for pcode to finish disabling IPS, which may take up to 42ms */
		3837	if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
		3838	DRM_ERROR("Timed out waiting for IPS disable\n");
4560	Serge	3839	} else {
		3840	I915_WRITE(IPS_CTL, 0);
		3841	POSTING_READ(IPS_CTL);
		3842	}
		3843
		3844	/* We need to wait for a vblank before we can disable the plane. */
		3845	intel_wait_for_vblank(dev, crtc->pipe);
		3846	}
		3847
		3848	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		3849	static void intel_crtc_load_lut(struct drm_crtc *crtc)
		3850	{
		3851	struct drm_device *dev = crtc->dev;
		3852	struct drm_i915_private *dev_priv = dev->dev_private;
		3853	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3854	enum pipe pipe = intel_crtc->pipe;
		3855	int palreg = PALETTE(pipe);
		3856	int i;
		3857	bool reenable_ips = false;
		3858
		3859	/* The clocks have to be on to load the palette. */
		3860	if (!crtc->enabled \|\| !intel_crtc->active)
		3861	return;
		3862
		3863	if (!HAS_PCH_SPLIT(dev_priv->dev)) {
		3864	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
		3865	assert_dsi_pll_enabled(dev_priv);
		3866	else
		3867	assert_pll_enabled(dev_priv, pipe);
		3868	}
		3869
		3870	/* use legacy palette for Ironlake */
5060	serge	3871	if (!HAS_GMCH_DISPLAY(dev))
4560	Serge	3872	palreg = LGC_PALETTE(pipe);
		3873
		3874	/* Workaround : Do not read or write the pipe palette/gamma data while
		3875	* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
		3876	*/
		3877	if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
		3878	((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
		3879	GAMMA_MODE_MODE_SPLIT)) {
		3880	hsw_disable_ips(intel_crtc);
		3881	reenable_ips = true;
		3882	}
		3883
		3884	for (i = 0; i < 256; i++) {
		3885	I915_WRITE(palreg + 4 * i,
		3886	(intel_crtc->lut_r[i] << 16) \|
		3887	(intel_crtc->lut_g[i] << 8) \|
		3888	intel_crtc->lut_b[i]);
		3889	}
		3890
		3891	if (reenable_ips)
		3892	hsw_enable_ips(intel_crtc);
		3893	}
		3894
5060	serge	3895	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3896	{
		3897	if (!enable && intel_crtc->overlay) {
		3898	struct drm_device *dev = intel_crtc->base.dev;
		3899	struct drm_i915_private *dev_priv = dev->dev_private;
		3900
		3901	mutex_lock(&dev->struct_mutex);
		3902	dev_priv->mm.interruptible = false;
		3903	dev_priv->mm.interruptible = true;
		3904	mutex_unlock(&dev->struct_mutex);
		3905	}
		3906
		3907	/* Let userspace switch the overlay on again. In most cases userspace
		3908	* has to recompute where to put it anyway.
		3909	*/
		3910	}
		3911
		3912	static void intel_crtc_enable_planes(struct drm_crtc *crtc)
		3913	{
		3914	struct drm_device *dev = crtc->dev;
		3915	struct drm_i915_private *dev_priv = dev->dev_private;
		3916	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3917	int pipe = intel_crtc->pipe;
		3918	int plane = intel_crtc->plane;
		3919
		3920	drm_vblank_on(dev, pipe);
		3921
		3922	intel_enable_primary_hw_plane(dev_priv, plane, pipe);
		3923	intel_enable_planes(crtc);
		3924	intel_crtc_update_cursor(crtc, true);
		3925	intel_crtc_dpms_overlay(intel_crtc, true);
		3926
		3927	hsw_enable_ips(intel_crtc);
		3928
		3929	mutex_lock(&dev->struct_mutex);
		3930	intel_update_fbc(dev);
		3931	mutex_unlock(&dev->struct_mutex);
		3932	}
		3933
		3934	static void intel_crtc_disable_planes(struct drm_crtc *crtc)
		3935	{
		3936	struct drm_device *dev = crtc->dev;
		3937	struct drm_i915_private *dev_priv = dev->dev_private;
		3938	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3939	int pipe = intel_crtc->pipe;
		3940	int plane = intel_crtc->plane;
		3941
		3942
		3943	if (dev_priv->fbc.plane == plane)
		3944	intel_disable_fbc(dev);
		3945
		3946	hsw_disable_ips(intel_crtc);
		3947
		3948	intel_crtc_dpms_overlay(intel_crtc, false);
		3949	intel_crtc_update_cursor(crtc, false);
		3950	intel_disable_planes(crtc);
		3951	intel_disable_primary_hw_plane(dev_priv, plane, pipe);
		3952	drm_vblank_off(dev, pipe);
		3953	}
		3954
2327	Serge	3955	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		3956	{
		3957	struct drm_device *dev = crtc->dev;
		3958	struct drm_i915_private *dev_priv = dev->dev_private;
		3959	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3960	struct intel_encoder *encoder;
2327	Serge	3961	int pipe = intel_crtc->pipe;
5060	serge	3962	enum plane plane = intel_crtc->plane;
2327	Serge	3963
3031	serge	3964	WARN_ON(!crtc->enabled);
		3965
2327	Serge	3966	if (intel_crtc->active)
		3967	return;
		3968
5060	serge	3969	if (intel_crtc->config.has_pch_encoder)
		3970	intel_prepare_shared_dpll(intel_crtc);
		3971
		3972	if (intel_crtc->config.has_dp_encoder)
		3973	intel_dp_set_m_n(intel_crtc);
		3974
		3975	intel_set_pipe_timings(intel_crtc);
		3976
		3977	if (intel_crtc->config.has_pch_encoder) {
		3978	intel_cpu_transcoder_set_m_n(intel_crtc,
		3979	&intel_crtc->config.fdi_m_n);
		3980	}
		3981
		3982	ironlake_set_pipeconf(crtc);
		3983
		3984	/* Set up the display plane register */
		3985	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
		3986	POSTING_READ(DSPCNTR(plane));
		3987
		3988	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
		3989	crtc->x, crtc->y);
		3990
2327	Serge	3991	intel_crtc->active = true;
4104	Serge	3992
		3993	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3994	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
		3995
		3996	for_each_encoder_on_crtc(dev, crtc, encoder)
		3997	if (encoder->pre_enable)
		3998	encoder->pre_enable(encoder);
2327	Serge	3999
3746	Serge	4000	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	4001	/* Note: FDI PLL enabling _must_ be done before we enable the
		4002	* cpu pipes, hence this is separate from all the other fdi/pch
		4003	* enabling. */
3031	serge	4004	ironlake_fdi_pll_enable(intel_crtc);
		4005	} else {
		4006	assert_fdi_tx_disabled(dev_priv, pipe);
		4007	assert_fdi_rx_disabled(dev_priv, pipe);
		4008	}
2327	Serge	4009
4104	Serge	4010	ironlake_pfit_enable(intel_crtc);
3031	serge	4011
2327	Serge	4012	/*
		4013	* On ILK+ LUT must be loaded before the pipe is running but with
		4014	* clocks enabled
		4015	*/
		4016	intel_crtc_load_lut(crtc);
		4017
4560	Serge	4018	intel_update_watermarks(crtc);
5060	serge	4019	intel_enable_pipe(intel_crtc);
2327	Serge	4020
3746	Serge	4021	if (intel_crtc->config.has_pch_encoder)
2327	Serge	4022	ironlake_pch_enable(crtc);
		4023
3031	serge	4024	for_each_encoder_on_crtc(dev, crtc, encoder)
		4025	encoder->enable(encoder);
		4026
		4027	if (HAS_PCH_CPT(dev))
4104	Serge	4028	cpt_verify_modeset(dev, intel_crtc->pipe);
3031	serge	4029
5060	serge	4030	intel_crtc_enable_planes(crtc);
2327	Serge	4031	}
		4032
4104	Serge	4033	/* IPS only exists on ULT machines and is tied to pipe A. */
		4034	static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
		4035	{
		4036	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
		4037	}
		4038
4560	Serge	4039	/*
		4040	* This implements the workaround described in the "notes" section of the mode
		4041	* set sequence documentation. When going from no pipes or single pipe to
		4042	* multiple pipes, and planes are enabled after the pipe, we need to wait at
		4043	* least 2 vblanks on the first pipe before enabling planes on the second pipe.
		4044	*/
		4045	static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
		4046	{
		4047	struct drm_device *dev = crtc->base.dev;
		4048	struct intel_crtc crtc_it, other_active_crtc = NULL;
		4049
		4050	/* We want to get the other_active_crtc only if there's only 1 other
		4051	* active crtc. */
5060	serge	4052	for_each_intel_crtc(dev, crtc_it) {
4560	Serge	4053	if (!crtc_it->active \|\| crtc_it == crtc)
		4054	continue;
		4055
		4056	if (other_active_crtc)
4104	Serge	4057	return;
		4058
4560	Serge	4059	other_active_crtc = crtc_it;
		4060	}
		4061	if (!other_active_crtc)
		4062	return;
4104	Serge	4063
4560	Serge	4064	intel_wait_for_vblank(dev, other_active_crtc->pipe);
		4065	intel_wait_for_vblank(dev, other_active_crtc->pipe);
4104	Serge	4066	}
		4067
3243	Serge	4068	static void haswell_crtc_enable(struct drm_crtc *crtc)
		4069	{
		4070	struct drm_device *dev = crtc->dev;
		4071	struct drm_i915_private *dev_priv = dev->dev_private;
		4072	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4073	struct intel_encoder *encoder;
		4074	int pipe = intel_crtc->pipe;
5060	serge	4075	enum plane plane = intel_crtc->plane;
3243	Serge	4076
		4077	WARN_ON(!crtc->enabled);
		4078
		4079	if (intel_crtc->active)
		4080	return;
		4081
5060	serge	4082	if (intel_crtc_to_shared_dpll(intel_crtc))
		4083	intel_enable_shared_dpll(intel_crtc);
		4084
		4085	if (intel_crtc->config.has_dp_encoder)
		4086	intel_dp_set_m_n(intel_crtc);
		4087
		4088	intel_set_pipe_timings(intel_crtc);
		4089
		4090	if (intel_crtc->config.has_pch_encoder) {
		4091	intel_cpu_transcoder_set_m_n(intel_crtc,
		4092	&intel_crtc->config.fdi_m_n);
		4093	}
		4094
		4095	haswell_set_pipeconf(crtc);
		4096
		4097	intel_set_pipe_csc(crtc);
		4098
		4099	/* Set up the display plane register */
		4100	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE \| DISPPLANE_PIPE_CSC_ENABLE);
		4101	POSTING_READ(DSPCNTR(plane));
		4102
		4103	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
		4104	crtc->x, crtc->y);
		4105
3243	Serge	4106	intel_crtc->active = true;
4104	Serge	4107
		4108	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3243	Serge	4109	for_each_encoder_on_crtc(dev, crtc, encoder)
		4110	if (encoder->pre_enable)
		4111	encoder->pre_enable(encoder);
		4112
5060	serge	4113	if (intel_crtc->config.has_pch_encoder) {
		4114	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
		4115	dev_priv->display.fdi_link_train(crtc);
		4116	}
		4117
3243	Serge	4118	intel_ddi_enable_pipe_clock(intel_crtc);
		4119
4104	Serge	4120	ironlake_pfit_enable(intel_crtc);
3243	Serge	4121
		4122	/*
		4123	* On ILK+ LUT must be loaded before the pipe is running but with
		4124	* clocks enabled
		4125	*/
		4126	intel_crtc_load_lut(crtc);
		4127
		4128	intel_ddi_set_pipe_settings(crtc);
3746	Serge	4129	intel_ddi_enable_transcoder_func(crtc);
3243	Serge	4130
4560	Serge	4131	intel_update_watermarks(crtc);
5060	serge	4132	intel_enable_pipe(intel_crtc);
3243	Serge	4133
3746	Serge	4134	if (intel_crtc->config.has_pch_encoder)
3243	Serge	4135	lpt_pch_enable(crtc);
		4136
5060	serge	4137	if (intel_crtc->config.dp_encoder_is_mst)
		4138	intel_ddi_set_vc_payload_alloc(crtc, true);
		4139
4560	Serge	4140	for_each_encoder_on_crtc(dev, crtc, encoder) {
3243	Serge	4141	encoder->enable(encoder);
4560	Serge	4142	intel_opregion_notify_encoder(encoder, true);
		4143	}
3243	Serge	4144
4560	Serge	4145	/* If we change the relative order between pipe/planes enabling, we need
		4146	* to change the workaround. */
		4147	haswell_mode_set_planes_workaround(intel_crtc);
5060	serge	4148	intel_crtc_enable_planes(crtc);
3243	Serge	4149	}
		4150
4104	Serge	4151	static void ironlake_pfit_disable(struct intel_crtc *crtc)
		4152	{
		4153	struct drm_device *dev = crtc->base.dev;
		4154	struct drm_i915_private *dev_priv = dev->dev_private;
		4155	int pipe = crtc->pipe;
		4156
		4157	/* To avoid upsetting the power well on haswell only disable the pfit if
		4158	* it's in use. The hw state code will make sure we get this right. */
		4159	if (crtc->config.pch_pfit.enabled) {
		4160	I915_WRITE(PF_CTL(pipe), 0);
		4161	I915_WRITE(PF_WIN_POS(pipe), 0);
		4162	I915_WRITE(PF_WIN_SZ(pipe), 0);
		4163	}
		4164	}
		4165
2327	Serge	4166	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		4167	{
		4168	struct drm_device *dev = crtc->dev;
		4169	struct drm_i915_private *dev_priv = dev->dev_private;
		4170	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	4171	struct intel_encoder *encoder;
2327	Serge	4172	int pipe = intel_crtc->pipe;
		4173	u32 reg, temp;
		4174
		4175	if (!intel_crtc->active)
		4176	return;
		4177
5060	serge	4178	intel_crtc_disable_planes(crtc);
		4179
3031	serge	4180	for_each_encoder_on_crtc(dev, crtc, encoder)
		4181	encoder->disable(encoder);
2336	Serge	4182
4104	Serge	4183	if (intel_crtc->config.has_pch_encoder)
		4184	intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
2327	Serge	4185
		4186	intel_disable_pipe(dev_priv, pipe);
		4187
5060	serge	4188	if (intel_crtc->config.dp_encoder_is_mst)
		4189	intel_ddi_set_vc_payload_alloc(crtc, false);
		4190
4104	Serge	4191	ironlake_pfit_disable(intel_crtc);
2327	Serge	4192
3031	serge	4193	for_each_encoder_on_crtc(dev, crtc, encoder)
		4194	if (encoder->post_disable)
		4195	encoder->post_disable(encoder);
		4196
4104	Serge	4197	if (intel_crtc->config.has_pch_encoder) {
2327	Serge	4198	ironlake_fdi_disable(crtc);
		4199
3243	Serge	4200	ironlake_disable_pch_transcoder(dev_priv, pipe);
4104	Serge	4201	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
2327	Serge	4202
		4203	if (HAS_PCH_CPT(dev)) {
		4204	/* disable TRANS_DP_CTL */
		4205	reg = TRANS_DP_CTL(pipe);
		4206	temp = I915_READ(reg);
4104	Serge	4207	temp &= ~(TRANS_DP_OUTPUT_ENABLE \|
		4208	TRANS_DP_PORT_SEL_MASK);
2327	Serge	4209	temp \|= TRANS_DP_PORT_SEL_NONE;
		4210	I915_WRITE(reg, temp);
		4211
		4212	/* disable DPLL_SEL */
		4213	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	4214	temp &= ~(TRANS_DPLL_ENABLE(pipe) \| TRANS_DPLLB_SEL(pipe));
2327	Serge	4215	I915_WRITE(PCH_DPLL_SEL, temp);
		4216	}
		4217
		4218	/* disable PCH DPLL */
4104	Serge	4219	intel_disable_shared_dpll(intel_crtc);
2327	Serge	4220
3031	serge	4221	ironlake_fdi_pll_disable(intel_crtc);
4104	Serge	4222	}
2327	Serge	4223
		4224	intel_crtc->active = false;
4560	Serge	4225	intel_update_watermarks(crtc);
2327	Serge	4226
		4227	mutex_lock(&dev->struct_mutex);
		4228	intel_update_fbc(dev);
		4229	mutex_unlock(&dev->struct_mutex);
		4230	}
		4231
3243	Serge	4232	static void haswell_crtc_disable(struct drm_crtc *crtc)
		4233	{
		4234	struct drm_device *dev = crtc->dev;
		4235	struct drm_i915_private *dev_priv = dev->dev_private;
		4236	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4237	struct intel_encoder *encoder;
		4238	int pipe = intel_crtc->pipe;
3746	Serge	4239	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	4240
		4241	if (!intel_crtc->active)
		4242	return;
		4243
5060	serge	4244	intel_crtc_disable_planes(crtc);
4560	Serge	4245
		4246	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4247	intel_opregion_notify_encoder(encoder, false);
3243	Serge	4248	encoder->disable(encoder);
4560	Serge	4249	}
3243	Serge	4250
4104	Serge	4251	if (intel_crtc->config.has_pch_encoder)
		4252	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3243	Serge	4253	intel_disable_pipe(dev_priv, pipe);
		4254
		4255	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
		4256
4104	Serge	4257	ironlake_pfit_disable(intel_crtc);
3243	Serge	4258
		4259	intel_ddi_disable_pipe_clock(intel_crtc);
		4260
3746	Serge	4261	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	4262	lpt_disable_pch_transcoder(dev_priv);
4104	Serge	4263	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3243	Serge	4264	intel_ddi_fdi_disable(crtc);
		4265	}
		4266
5060	serge	4267	for_each_encoder_on_crtc(dev, crtc, encoder)
		4268	if (encoder->post_disable)
		4269	encoder->post_disable(encoder);
		4270
3243	Serge	4271	intel_crtc->active = false;
4560	Serge	4272	intel_update_watermarks(crtc);
3243	Serge	4273
		4274	mutex_lock(&dev->struct_mutex);
		4275	intel_update_fbc(dev);
		4276	mutex_unlock(&dev->struct_mutex);
5060	serge	4277
		4278	if (intel_crtc_to_shared_dpll(intel_crtc))
		4279	intel_disable_shared_dpll(intel_crtc);
3243	Serge	4280	}
		4281
3031	serge	4282	static void ironlake_crtc_off(struct drm_crtc *crtc)
2327	Serge	4283	{
		4284	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	4285	intel_put_shared_dpll(intel_crtc);
2327	Serge	4286	}
		4287
3243	Serge	4288
4104	Serge	4289	static void i9xx_pfit_enable(struct intel_crtc *crtc)
		4290	{
		4291	struct drm_device *dev = crtc->base.dev;
		4292	struct drm_i915_private *dev_priv = dev->dev_private;
		4293	struct intel_crtc_config *pipe_config = &crtc->config;
		4294
		4295	if (!crtc->config.gmch_pfit.control)
		4296	return;
		4297
		4298	/*
		4299	* The panel fitter should only be adjusted whilst the pipe is disabled,
		4300	* according to register description and PRM.
		4301	*/
		4302	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
		4303	assert_pipe_disabled(dev_priv, crtc->pipe);
		4304
		4305	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
		4306	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
		4307
		4308	/* Border color in case we don't scale up to the full screen. Black by
		4309	* default, change to something else for debugging. */
		4310	I915_WRITE(BCLRPAT(crtc->pipe), 0);
		4311	}
		4312
5060	serge	4313	static enum intel_display_power_domain port_to_power_domain(enum port port)
4560	Serge	4314	{
5060	serge	4315	switch (port) {
		4316	case PORT_A:
		4317	return POWER_DOMAIN_PORT_DDI_A_4_LANES;
		4318	case PORT_B:
		4319	return POWER_DOMAIN_PORT_DDI_B_4_LANES;
		4320	case PORT_C:
		4321	return POWER_DOMAIN_PORT_DDI_C_4_LANES;
		4322	case PORT_D:
		4323	return POWER_DOMAIN_PORT_DDI_D_4_LANES;
		4324	default:
		4325	WARN_ON_ONCE(1);
		4326	return POWER_DOMAIN_PORT_OTHER;
		4327	}
		4328	}
		4329
		4330	#define for_each_power_domain(domain, mask) \
		4331	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
		4332	if ((1 << (domain)) & (mask))
		4333
		4334	enum intel_display_power_domain
		4335	intel_display_port_power_domain(struct intel_encoder *intel_encoder)
		4336	{
		4337	struct drm_device *dev = intel_encoder->base.dev;
		4338	struct intel_digital_port *intel_dig_port;
		4339
		4340	switch (intel_encoder->type) {
		4341	case INTEL_OUTPUT_UNKNOWN:
		4342	/* Only DDI platforms should ever use this output type */
		4343	WARN_ON_ONCE(!HAS_DDI(dev));
		4344	case INTEL_OUTPUT_DISPLAYPORT:
		4345	case INTEL_OUTPUT_HDMI:
		4346	case INTEL_OUTPUT_EDP:
		4347	intel_dig_port = enc_to_dig_port(&intel_encoder->base);
		4348	return port_to_power_domain(intel_dig_port->port);
		4349	case INTEL_OUTPUT_DP_MST:
		4350	intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
		4351	return port_to_power_domain(intel_dig_port->port);
		4352	case INTEL_OUTPUT_ANALOG:
		4353	return POWER_DOMAIN_PORT_CRT;
		4354	case INTEL_OUTPUT_DSI:
		4355	return POWER_DOMAIN_PORT_DSI;
		4356	default:
		4357	return POWER_DOMAIN_PORT_OTHER;
		4358	}
		4359	}
		4360
		4361	static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
		4362	{
		4363	struct drm_device *dev = crtc->dev;
		4364	struct intel_encoder *intel_encoder;
		4365	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4366	enum pipe pipe = intel_crtc->pipe;
		4367	unsigned long mask;
		4368	enum transcoder transcoder;
		4369
		4370	transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
		4371
		4372	mask = BIT(POWER_DOMAIN_PIPE(pipe));
		4373	mask \|= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
		4374	if (intel_crtc->config.pch_pfit.enabled \|\|
		4375	intel_crtc->config.pch_pfit.force_thru)
		4376	mask \|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
		4377
		4378	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		4379	mask \|= BIT(intel_display_port_power_domain(intel_encoder));
		4380
		4381	return mask;
		4382	}
		4383
		4384	void intel_display_set_init_power(struct drm_i915_private *dev_priv,
		4385	bool enable)
		4386	{
		4387	if (dev_priv->power_domains.init_power_on == enable)
		4388	return;
		4389
		4390	if (enable)
		4391	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
		4392	else
		4393	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
		4394
		4395	dev_priv->power_domains.init_power_on = enable;
		4396	}
		4397
		4398	static void modeset_update_crtc_power_domains(struct drm_device *dev)
		4399	{
		4400	struct drm_i915_private *dev_priv = dev->dev_private;
		4401	unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
		4402	struct intel_crtc *crtc;
		4403
		4404	/*
		4405	* First get all needed power domains, then put all unneeded, to avoid
		4406	* any unnecessary toggling of the power wells.
		4407	*/
		4408	for_each_intel_crtc(dev, crtc) {
		4409	enum intel_display_power_domain domain;
		4410
		4411	if (!crtc->base.enabled)
		4412	continue;
		4413
		4414	pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
		4415
		4416	for_each_power_domain(domain, pipe_domains[crtc->pipe])
		4417	intel_display_power_get(dev_priv, domain);
		4418	}
		4419
		4420	for_each_intel_crtc(dev, crtc) {
		4421	enum intel_display_power_domain domain;
		4422
		4423	for_each_power_domain(domain, crtc->enabled_power_domains)
		4424	intel_display_power_put(dev_priv, domain);
		4425
		4426	crtc->enabled_power_domains = pipe_domains[crtc->pipe];
		4427	}
		4428
		4429	intel_display_set_init_power(dev_priv, false);
		4430	}
		4431
		4432	/* returns HPLL frequency in kHz */
		4433	static int valleyview_get_vco(struct drm_i915_private *dev_priv)
		4434	{
4560	Serge	4435	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
		4436
		4437	/* Obtain SKU information */
		4438	mutex_lock(&dev_priv->dpio_lock);
		4439	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
		4440	CCK_FUSE_HPLL_FREQ_MASK;
		4441	mutex_unlock(&dev_priv->dpio_lock);
		4442
5060	serge	4443	return vco_freq[hpll_freq] * 1000;
4560	Serge	4444	}
		4445
5060	serge	4446	static void vlv_update_cdclk(struct drm_device *dev)
		4447	{
		4448	struct drm_i915_private *dev_priv = dev->dev_private;
		4449
		4450	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
		4451	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
		4452	dev_priv->vlv_cdclk_freq);
		4453
		4454	/*
		4455	* Program the gmbus_freq based on the cdclk frequency.
		4456	* BSpec erroneously claims we should aim for 4MHz, but
		4457	* in fact 1MHz is the correct frequency.
		4458	*/
		4459	I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
		4460	}
		4461
4560	Serge	4462	/* Adjust CDclk dividers to allow high res or save power if possible */
		4463	static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
		4464	{
		4465	struct drm_i915_private *dev_priv = dev->dev_private;
		4466	u32 val, cmd;
		4467
5060	serge	4468	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
		4469
		4470	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4560	Serge	4471	cmd = 2;
5060	serge	4472	else if (cdclk == 266667)
4560	Serge	4473	cmd = 1;
		4474	else
		4475	cmd = 0;
		4476
		4477	mutex_lock(&dev_priv->rps.hw_lock);
		4478	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
		4479	val &= ~DSPFREQGUAR_MASK;
		4480	val \|= (cmd << DSPFREQGUAR_SHIFT);
		4481	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
		4482	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
		4483	DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
		4484	50)) {
		4485	DRM_ERROR("timed out waiting for CDclk change\n");
		4486	}
		4487	mutex_unlock(&dev_priv->rps.hw_lock);
		4488
5060	serge	4489	if (cdclk == 400000) {
4560	Serge	4490	u32 divider, vco;
		4491
		4492	vco = valleyview_get_vco(dev_priv);
5060	serge	4493	divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4560	Serge	4494
		4495	mutex_lock(&dev_priv->dpio_lock);
		4496	/* adjust cdclk divider */
		4497	val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5060	serge	4498	val &= ~DISPLAY_FREQUENCY_VALUES;
4560	Serge	4499	val \|= divider;
		4500	vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5060	serge	4501
		4502	if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
		4503	DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
		4504	50))
		4505	DRM_ERROR("timed out waiting for CDclk change\n");
4560	Serge	4506	mutex_unlock(&dev_priv->dpio_lock);
		4507	}
		4508
		4509	mutex_lock(&dev_priv->dpio_lock);
		4510	/* adjust self-refresh exit latency value */
		4511	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
		4512	val &= ~0x7f;
		4513
		4514	/*
		4515	* For high bandwidth configs, we set a higher latency in the bunit
		4516	* so that the core display fetch happens in time to avoid underruns.
		4517	*/
5060	serge	4518	if (cdclk == 400000)
4560	Serge	4519	val \|= 4500 / 250; /* 4.5 usec */
		4520	else
		4521	val \|= 3000 / 250; /* 3.0 usec */
		4522	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
		4523	mutex_unlock(&dev_priv->dpio_lock);
		4524
5060	serge	4525	vlv_update_cdclk(dev);
4560	Serge	4526	}
		4527
		4528	static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
		4529	int max_pixclk)
		4530	{
5060	serge	4531	int vco = valleyview_get_vco(dev_priv);
		4532	int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4560	Serge	4533
		4534	/*
		4535	* Really only a few cases to deal with, as only 4 CDclks are supported:
		4536	* 200MHz
		4537	* 267MHz
5060	serge	4538	* 320/333MHz (depends on HPLL freq)
4560	Serge	4539	* 400MHz
		4540	* So we check to see whether we're above 90% of the lower bin and
		4541	* adjust if needed.
5060	serge	4542	*
		4543	* We seem to get an unstable or solid color picture at 200MHz.
		4544	* Not sure what's wrong. For now use 200MHz only when all pipes
		4545	* are off.
4560	Serge	4546	*/
5060	serge	4547	if (max_pixclk > freq_320*9/10)
		4548	return 400000;
		4549	else if (max_pixclk > 266667*9/10)
		4550	return freq_320;
		4551	else if (max_pixclk > 0)
		4552	return 266667;
		4553	else
		4554	return 200000;
4560	Serge	4555	}
		4556
5060	serge	4557	/* compute the max pixel clock for new configuration */
		4558	static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4560	Serge	4559	{
		4560	struct drm_device *dev = dev_priv->dev;
		4561	struct intel_crtc *intel_crtc;
		4562	int max_pixclk = 0;
		4563
5060	serge	4564	for_each_intel_crtc(dev, intel_crtc) {
		4565	if (intel_crtc->new_enabled)
4560	Serge	4566	max_pixclk = max(max_pixclk,
5060	serge	4567	intel_crtc->new_config->adjusted_mode.crtc_clock);
4560	Serge	4568	}
		4569
		4570	return max_pixclk;
		4571	}
		4572
		4573	static void valleyview_modeset_global_pipes(struct drm_device *dev,
5060	serge	4574	unsigned *prepare_pipes)
4560	Serge	4575	{
		4576	struct drm_i915_private *dev_priv = dev->dev_private;
		4577	struct intel_crtc *intel_crtc;
5060	serge	4578	int max_pixclk = intel_mode_max_pixclk(dev_priv);
4560	Serge	4579
5060	serge	4580	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
		4581	dev_priv->vlv_cdclk_freq)
4560	Serge	4582	return;
		4583
5060	serge	4584	/* disable/enable all currently active pipes while we change cdclk */
		4585	for_each_intel_crtc(dev, intel_crtc)
4560	Serge	4586	if (intel_crtc->base.enabled)
		4587	*prepare_pipes \|= (1 << intel_crtc->pipe);
		4588	}
		4589
		4590	static void valleyview_modeset_global_resources(struct drm_device *dev)
		4591	{
		4592	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	4593	int max_pixclk = intel_mode_max_pixclk(dev_priv);
4560	Serge	4594	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
		4595
5060	serge	4596	if (req_cdclk != dev_priv->vlv_cdclk_freq)
4560	Serge	4597	valleyview_set_cdclk(dev, req_cdclk);
5060	serge	4598	modeset_update_crtc_power_domains(dev);
4560	Serge	4599	}
		4600
4104	Serge	4601	static void valleyview_crtc_enable(struct drm_crtc *crtc)
		4602	{
		4603	struct drm_device *dev = crtc->dev;
		4604	struct drm_i915_private *dev_priv = dev->dev_private;
		4605	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4606	struct intel_encoder *encoder;
		4607	int pipe = intel_crtc->pipe;
		4608	int plane = intel_crtc->plane;
4560	Serge	4609	bool is_dsi;
5060	serge	4610	u32 dspcntr;
4104	Serge	4611
		4612	WARN_ON(!crtc->enabled);
		4613
		4614	if (intel_crtc->active)
		4615	return;
		4616
5060	serge	4617	is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
		4618
		4619	if (!is_dsi && !IS_CHERRYVIEW(dev))
		4620	vlv_prepare_pll(intel_crtc);
		4621
		4622	/* Set up the display plane register */
		4623	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4624
		4625	if (intel_crtc->config.has_dp_encoder)
		4626	intel_dp_set_m_n(intel_crtc);
		4627
		4628	intel_set_pipe_timings(intel_crtc);
		4629
		4630	/* pipesrc and dspsize control the size that is scaled from,
		4631	* which should always be the user's requested size.
		4632	*/
		4633	I915_WRITE(DSPSIZE(plane),
		4634	((intel_crtc->config.pipe_src_h - 1) << 16) \|
		4635	(intel_crtc->config.pipe_src_w - 1));
		4636	I915_WRITE(DSPPOS(plane), 0);
		4637
		4638	i9xx_set_pipeconf(intel_crtc);
		4639
		4640	I915_WRITE(DSPCNTR(plane), dspcntr);
		4641	POSTING_READ(DSPCNTR(plane));
		4642
		4643	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
		4644	crtc->x, crtc->y);
		4645
4104	Serge	4646	intel_crtc->active = true;
		4647
5060	serge	4648	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		4649
4104	Serge	4650	for_each_encoder_on_crtc(dev, crtc, encoder)
		4651	if (encoder->pre_pll_enable)
		4652	encoder->pre_pll_enable(encoder);
		4653
5060	serge	4654	if (!is_dsi) {
		4655	if (IS_CHERRYVIEW(dev))
		4656	chv_enable_pll(intel_crtc);
		4657	else
4104	Serge	4658	vlv_enable_pll(intel_crtc);
5060	serge	4659	}
4104	Serge	4660
		4661	for_each_encoder_on_crtc(dev, crtc, encoder)
		4662	if (encoder->pre_enable)
		4663	encoder->pre_enable(encoder);
		4664
		4665	i9xx_pfit_enable(intel_crtc);
		4666
		4667	intel_crtc_load_lut(crtc);
		4668
4560	Serge	4669	intel_update_watermarks(crtc);
5060	serge	4670	intel_enable_pipe(intel_crtc);
4104	Serge	4671
		4672	for_each_encoder_on_crtc(dev, crtc, encoder)
		4673	encoder->enable(encoder);
5060	serge	4674
		4675	intel_crtc_enable_planes(crtc);
		4676
		4677	/* Underruns don't raise interrupts, so check manually. */
		4678	i9xx_check_fifo_underruns(dev);
4104	Serge	4679	}
		4680
5060	serge	4681	static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
		4682	{
		4683	struct drm_device *dev = crtc->base.dev;
		4684	struct drm_i915_private *dev_priv = dev->dev_private;
		4685
		4686	I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
		4687	I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
		4688	}
		4689
2327	Serge	4690	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		4691	{
		4692	struct drm_device *dev = crtc->dev;
		4693	struct drm_i915_private *dev_priv = dev->dev_private;
		4694	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	4695	struct intel_encoder *encoder;
2327	Serge	4696	int pipe = intel_crtc->pipe;
		4697	int plane = intel_crtc->plane;
5060	serge	4698	u32 dspcntr;
2327	Serge	4699
3031	serge	4700	WARN_ON(!crtc->enabled);
		4701
2327	Serge	4702	if (intel_crtc->active)
		4703	return;
		4704
5060	serge	4705	i9xx_set_pll_dividers(intel_crtc);
		4706
		4707	/* Set up the display plane register */
		4708	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4709
		4710	if (pipe == 0)
		4711	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4712	else
		4713	dspcntr \|= DISPPLANE_SEL_PIPE_B;
		4714
		4715	if (intel_crtc->config.has_dp_encoder)
		4716	intel_dp_set_m_n(intel_crtc);
		4717
		4718	intel_set_pipe_timings(intel_crtc);
		4719
		4720	/* pipesrc and dspsize control the size that is scaled from,
		4721	* which should always be the user's requested size.
		4722	*/
		4723	I915_WRITE(DSPSIZE(plane),
		4724	((intel_crtc->config.pipe_src_h - 1) << 16) \|
		4725	(intel_crtc->config.pipe_src_w - 1));
		4726	I915_WRITE(DSPPOS(plane), 0);
		4727
		4728	i9xx_set_pipeconf(intel_crtc);
		4729
		4730	I915_WRITE(DSPCNTR(plane), dspcntr);
		4731	POSTING_READ(DSPCNTR(plane));
		4732
		4733	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
		4734	crtc->x, crtc->y);
		4735
2327	Serge	4736	intel_crtc->active = true;
		4737
5060	serge	4738	if (!IS_GEN2(dev))
		4739	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		4740
3480	Serge	4741	for_each_encoder_on_crtc(dev, crtc, encoder)
		4742	if (encoder->pre_enable)
		4743	encoder->pre_enable(encoder);
		4744
4104	Serge	4745	i9xx_enable_pll(intel_crtc);
		4746
		4747	i9xx_pfit_enable(intel_crtc);
		4748
		4749	intel_crtc_load_lut(crtc);
		4750
4560	Serge	4751	intel_update_watermarks(crtc);
5060	serge	4752	intel_enable_pipe(intel_crtc);
2327	Serge	4753
5060	serge	4754	for_each_encoder_on_crtc(dev, crtc, encoder)
		4755	encoder->enable(encoder);
3031	serge	4756
5060	serge	4757	intel_crtc_enable_planes(crtc);
4104	Serge	4758
5060	serge	4759	/*
		4760	* Gen2 reports pipe underruns whenever all planes are disabled.
		4761	* So don't enable underrun reporting before at least some planes
		4762	* are enabled.
		4763	* FIXME: Need to fix the logic to work when we turn off all planes
		4764	* but leave the pipe running.
		4765	*/
		4766	if (IS_GEN2(dev))
		4767	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		4768
		4769	/* Underruns don't raise interrupts, so check manually. */
		4770	i9xx_check_fifo_underruns(dev);
2327	Serge	4771	}
		4772
3746	Serge	4773	static void i9xx_pfit_disable(struct intel_crtc *crtc)
		4774	{
		4775	struct drm_device *dev = crtc->base.dev;
		4776	struct drm_i915_private *dev_priv = dev->dev_private;
		4777
4104	Serge	4778	if (!crtc->config.gmch_pfit.control)
		4779	return;
		4780
3746	Serge	4781	assert_pipe_disabled(dev_priv, crtc->pipe);
		4782
4104	Serge	4783	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
		4784	I915_READ(PFIT_CONTROL));
3746	Serge	4785	I915_WRITE(PFIT_CONTROL, 0);
		4786	}
		4787
2327	Serge	4788	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		4789	{
		4790	struct drm_device *dev = crtc->dev;
		4791	struct drm_i915_private *dev_priv = dev->dev_private;
		4792	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	4793	struct intel_encoder *encoder;
2327	Serge	4794	int pipe = intel_crtc->pipe;
		4795
		4796	if (!intel_crtc->active)
		4797	return;
		4798
5060	serge	4799	/*
		4800	* Gen2 reports pipe underruns whenever all planes are disabled.
		4801	* So diasble underrun reporting before all the planes get disabled.
		4802	* FIXME: Need to fix the logic to work when we turn off all planes
		4803	* but leave the pipe running.
		4804	*/
		4805	if (IS_GEN2(dev))
		4806	intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
		4807
		4808	/*
		4809	* Vblank time updates from the shadow to live plane control register
		4810	* are blocked if the memory self-refresh mode is active at that
		4811	* moment. So to make sure the plane gets truly disabled, disable
		4812	* first the self-refresh mode. The self-refresh enable bit in turn
		4813	* will be checked/applied by the HW only at the next frame start
		4814	* event which is after the vblank start event, so we need to have a
		4815	* wait-for-vblank between disabling the plane and the pipe.
		4816	*/
		4817	intel_set_memory_cxsr(dev_priv, false);
		4818	intel_crtc_disable_planes(crtc);
		4819
3031	serge	4820	for_each_encoder_on_crtc(dev, crtc, encoder)
		4821	encoder->disable(encoder);
		4822
5060	serge	4823	/*
		4824	* On gen2 planes are double buffered but the pipe isn't, so we must
		4825	* wait for planes to fully turn off before disabling the pipe.
		4826	* We also need to wait on all gmch platforms because of the
		4827	* self-refresh mode constraint explained above.
		4828	*/
		4829	intel_wait_for_vblank(dev, pipe);
2327	Serge	4830
		4831	intel_disable_pipe(dev_priv, pipe);
3480	Serge	4832
3746	Serge	4833	i9xx_pfit_disable(intel_crtc);
3480	Serge	4834
4104	Serge	4835	for_each_encoder_on_crtc(dev, crtc, encoder)
		4836	if (encoder->post_disable)
		4837	encoder->post_disable(encoder);
2327	Serge	4838
5060	serge	4839	if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
		4840	if (IS_CHERRYVIEW(dev))
		4841	chv_disable_pll(dev_priv, pipe);
		4842	else if (IS_VALLEYVIEW(dev))
4557	Serge	4843	vlv_disable_pll(dev_priv, pipe);
5060	serge	4844	else
4104	Serge	4845	i9xx_disable_pll(dev_priv, pipe);
5060	serge	4846	}
4104	Serge	4847
5060	serge	4848	if (!IS_GEN2(dev))
		4849	intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
		4850
2327	Serge	4851	intel_crtc->active = false;
4560	Serge	4852	intel_update_watermarks(crtc);
		4853
5060	serge	4854	mutex_lock(&dev->struct_mutex);
2327	Serge	4855	intel_update_fbc(dev);
5060	serge	4856	mutex_unlock(&dev->struct_mutex);
2327	Serge	4857	}
		4858
3031	serge	4859	static void i9xx_crtc_off(struct drm_crtc *crtc)
2327	Serge	4860	{
		4861	}
		4862
3031	serge	4863	static void intel_crtc_update_sarea(struct drm_crtc *crtc,
		4864	bool enabled)
2330	Serge	4865	{
		4866	struct drm_device *dev = crtc->dev;
		4867	struct drm_i915_master_private *master_priv;
		4868	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4869	int pipe = intel_crtc->pipe;
2327	Serge	4870
		4871
2340	Serge	4872	#if 0
2330	Serge	4873	if (!dev->primary->master)
		4874	return;
2327	Serge	4875
2330	Serge	4876	master_priv = dev->primary->master->driver_priv;
		4877	if (!master_priv->sarea_priv)
		4878	return;
2327	Serge	4879
2330	Serge	4880	switch (pipe) {
		4881	case 0:
		4882	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		4883	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		4884	break;
		4885	case 1:
		4886	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		4887	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		4888	break;
		4889	default:
		4890	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		4891	break;
		4892	}
2340	Serge	4893	#endif
5060	serge	4894	}
2340	Serge	4895
5060	serge	4896	/* Master function to enable/disable CRTC and corresponding power wells */
		4897	void intel_crtc_control(struct drm_crtc *crtc, bool enable)
		4898	{
		4899	struct drm_device *dev = crtc->dev;
		4900	struct drm_i915_private *dev_priv = dev->dev_private;
		4901	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4902	enum intel_display_power_domain domain;
		4903	unsigned long domains;
		4904
		4905	if (enable) {
		4906	if (!intel_crtc->active) {
		4907	domains = get_crtc_power_domains(crtc);
		4908	for_each_power_domain(domain, domains)
		4909	intel_display_power_get(dev_priv, domain);
		4910	intel_crtc->enabled_power_domains = domains;
		4911
		4912	dev_priv->display.crtc_enable(crtc);
		4913	}
		4914	} else {
		4915	if (intel_crtc->active) {
		4916	dev_priv->display.crtc_disable(crtc);
		4917
		4918	domains = intel_crtc->enabled_power_domains;
		4919	for_each_power_domain(domain, domains)
		4920	intel_display_power_put(dev_priv, domain);
		4921	intel_crtc->enabled_power_domains = 0;
		4922	}
		4923	}
2330	Serge	4924	}
2327	Serge	4925
3031	serge	4926	/**
		4927	* Sets the power management mode of the pipe and plane.
		4928	*/
		4929	void intel_crtc_update_dpms(struct drm_crtc *crtc)
		4930	{
		4931	struct drm_device *dev = crtc->dev;
		4932	struct intel_encoder *intel_encoder;
		4933	bool enable = false;
		4934
		4935	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		4936	enable \|= intel_encoder->connectors_active;
		4937
5060	serge	4938	intel_crtc_control(crtc, enable);
3031	serge	4939
		4940	intel_crtc_update_sarea(crtc, enable);
		4941	}
		4942
2330	Serge	4943	static void intel_crtc_disable(struct drm_crtc *crtc)
		4944	{
		4945	struct drm_device *dev = crtc->dev;
3031	serge	4946	struct drm_connector *connector;
		4947	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	4948	struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
		4949	enum pipe pipe = to_intel_crtc(crtc)->pipe;
2327	Serge	4950
3031	serge	4951	/* crtc should still be enabled when we disable it. */
		4952	WARN_ON(!crtc->enabled);
2327	Serge	4953
4104	Serge	4954	dev_priv->display.crtc_disable(crtc);
3031	serge	4955	intel_crtc_update_sarea(crtc, false);
		4956	dev_priv->display.off(crtc);
		4957
5060	serge	4958	if (crtc->primary->fb) {
4280	Serge	4959	mutex_lock(&dev->struct_mutex);
5060	serge	4960	intel_unpin_fb_obj(old_obj);
		4961	i915_gem_track_fb(old_obj, NULL,
		4962	INTEL_FRONTBUFFER_PRIMARY(pipe));
4280	Serge	4963	mutex_unlock(&dev->struct_mutex);
5060	serge	4964	crtc->primary->fb = NULL;
4280	Serge	4965	}
3031	serge	4966
		4967	/* Update computed state. */
		4968	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		4969	if (!connector->encoder \|\| !connector->encoder->crtc)
		4970	continue;
		4971
		4972	if (connector->encoder->crtc != crtc)
		4973	continue;
		4974
		4975	connector->dpms = DRM_MODE_DPMS_OFF;
		4976	to_intel_encoder(connector->encoder)->connectors_active = false;
2330	Serge	4977	}
		4978	}
2327	Serge	4979
3031	serge	4980	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	4981	{
3031	serge	4982	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		4983
		4984	drm_encoder_cleanup(encoder);
		4985	kfree(intel_encoder);
2330	Serge	4986	}
2327	Serge	4987
4104	Serge	4988	/* Simple dpms helper for encoders with just one connector, no cloning and only
3031	serge	4989	* one kind of off state. It clamps all !ON modes to fully OFF and changes the
		4990	* state of the entire output pipe. */
4104	Serge	4991	static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
2330	Serge	4992	{
3031	serge	4993	if (mode == DRM_MODE_DPMS_ON) {
		4994	encoder->connectors_active = true;
		4995
		4996	intel_crtc_update_dpms(encoder->base.crtc);
		4997	} else {
		4998	encoder->connectors_active = false;
		4999
		5000	intel_crtc_update_dpms(encoder->base.crtc);
		5001	}
2330	Serge	5002	}
2327	Serge	5003
3031	serge	5004	/* Cross check the actual hw state with our own modeset state tracking (and it's
		5005	* internal consistency). */
		5006	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	5007	{
3031	serge	5008	if (connector->get_hw_state(connector)) {
		5009	struct intel_encoder *encoder = connector->encoder;
		5010	struct drm_crtc *crtc;
		5011	bool encoder_enabled;
		5012	enum pipe pipe;
		5013
		5014	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		5015	connector->base.base.id,
5060	serge	5016	connector->base.name);
3031	serge	5017
5060	serge	5018	/* there is no real hw state for MST connectors */
		5019	if (connector->mst_port)
		5020	return;
		5021
3031	serge	5022	WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		5023	"wrong connector dpms state\n");
		5024	WARN(connector->base.encoder != &encoder->base,
		5025	"active connector not linked to encoder\n");
5060	serge	5026
		5027	if (encoder) {
3031	serge	5028	WARN(!encoder->connectors_active,
		5029	"encoder->connectors_active not set\n");
		5030
		5031	encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		5032	WARN(!encoder_enabled, "encoder not enabled\n");
		5033	if (WARN_ON(!encoder->base.crtc))
		5034	return;
		5035
		5036	crtc = encoder->base.crtc;
		5037
		5038	WARN(!crtc->enabled, "crtc not enabled\n");
		5039	WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		5040	WARN(pipe != to_intel_crtc(crtc)->pipe,
		5041	"encoder active on the wrong pipe\n");
		5042	}
5060	serge	5043	}
2330	Serge	5044	}
2327	Serge	5045
3031	serge	5046	/* Even simpler default implementation, if there's really no special case to
		5047	* consider. */
		5048	void intel_connector_dpms(struct drm_connector *connector, int mode)
2330	Serge	5049	{
3031	serge	5050	/* All the simple cases only support two dpms states. */
		5051	if (mode != DRM_MODE_DPMS_ON)
		5052	mode = DRM_MODE_DPMS_OFF;
2342	Serge	5053
3031	serge	5054	if (mode == connector->dpms)
		5055	return;
		5056
		5057	connector->dpms = mode;
		5058
		5059	/* Only need to change hw state when actually enabled */
4104	Serge	5060	if (connector->encoder)
		5061	intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
3031	serge	5062
		5063	intel_modeset_check_state(connector->dev);
2330	Serge	5064	}
2327	Serge	5065
3031	serge	5066	/* Simple connector->get_hw_state implementation for encoders that support only
		5067	* one connector and no cloning and hence the encoder state determines the state
		5068	* of the connector. */
		5069	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	5070	{
3031	serge	5071	enum pipe pipe = 0;
		5072	struct intel_encoder *encoder = connector->encoder;
2330	Serge	5073
3031	serge	5074	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	5075	}
		5076
4104	Serge	5077	static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
		5078	struct intel_crtc_config *pipe_config)
		5079	{
		5080	struct drm_i915_private *dev_priv = dev->dev_private;
		5081	struct intel_crtc *pipe_B_crtc =
		5082	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		5083
		5084	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
		5085	pipe_name(pipe), pipe_config->fdi_lanes);
		5086	if (pipe_config->fdi_lanes > 4) {
		5087	DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
		5088	pipe_name(pipe), pipe_config->fdi_lanes);
		5089	return false;
		5090	}
		5091
4560	Serge	5092	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
4104	Serge	5093	if (pipe_config->fdi_lanes > 2) {
		5094	DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
		5095	pipe_config->fdi_lanes);
		5096	return false;
		5097	} else {
		5098	return true;
		5099	}
		5100	}
		5101
		5102	if (INTEL_INFO(dev)->num_pipes == 2)
		5103	return true;
		5104
		5105	/* Ivybridge 3 pipe is really complicated */
		5106	switch (pipe) {
		5107	case PIPE_A:
		5108	return true;
		5109	case PIPE_B:
		5110	if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		5111	pipe_config->fdi_lanes > 2) {
		5112	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		5113	pipe_name(pipe), pipe_config->fdi_lanes);
		5114	return false;
		5115	}
		5116	return true;
		5117	case PIPE_C:
		5118	if (!pipe_has_enabled_pch(pipe_B_crtc) \|\|
		5119	pipe_B_crtc->config.fdi_lanes <= 2) {
		5120	if (pipe_config->fdi_lanes > 2) {
		5121	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		5122	pipe_name(pipe), pipe_config->fdi_lanes);
		5123	return false;
		5124	}
		5125	} else {
		5126	DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
		5127	return false;
		5128	}
		5129	return true;
		5130	default:
		5131	BUG();
		5132	}
		5133	}
		5134
		5135	#define RETRY 1
		5136	static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3746	Serge	5137	struct intel_crtc_config *pipe_config)
2330	Serge	5138	{
4104	Serge	5139	struct drm_device *dev = intel_crtc->base.dev;
3746	Serge	5140	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4104	Serge	5141	int lane, link_bw, fdi_dotclock;
		5142	bool setup_ok, needs_recompute = false;
2330	Serge	5143
4104	Serge	5144	retry:
		5145	/* FDI is a binary signal running at ~2.7GHz, encoding
		5146	* each output octet as 10 bits. The actual frequency
		5147	* is stored as a divider into a 100MHz clock, and the
		5148	* mode pixel clock is stored in units of 1KHz.
		5149	* Hence the bw of each lane in terms of the mode signal
		5150	* is:
		5151	*/
		5152	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		5153
4560	Serge	5154	fdi_dotclock = adjusted_mode->crtc_clock;
4104	Serge	5155
		5156	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
		5157	pipe_config->pipe_bpp);
		5158
		5159	pipe_config->fdi_lanes = lane;
		5160
		5161	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
		5162	link_bw, &pipe_config->fdi_m_n);
		5163
		5164	setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
		5165	intel_crtc->pipe, pipe_config);
		5166	if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
		5167	pipe_config->pipe_bpp -= 2*3;
		5168	DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
		5169	pipe_config->pipe_bpp);
		5170	needs_recompute = true;
		5171	pipe_config->bw_constrained = true;
		5172
		5173	goto retry;
		5174	}
		5175
		5176	if (needs_recompute)
		5177	return RETRY;
		5178
		5179	return setup_ok ? 0 : -EINVAL;
		5180	}
		5181
		5182	static void hsw_compute_ips_config(struct intel_crtc *crtc,
		5183	struct intel_crtc_config *pipe_config)
		5184	{
5060	serge	5185	pipe_config->ips_enabled = i915.enable_ips &&
4104	Serge	5186	hsw_crtc_supports_ips(crtc) &&
		5187	pipe_config->pipe_bpp <= 24;
		5188	}
		5189
		5190	static int intel_crtc_compute_config(struct intel_crtc *crtc,
		5191	struct intel_crtc_config *pipe_config)
		5192	{
		5193	struct drm_device *dev = crtc->base.dev;
		5194	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
		5195
4560	Serge	5196	/* FIXME should check pixel clock limits on all platforms */
		5197	if (INTEL_INFO(dev)->gen < 4) {
		5198	struct drm_i915_private *dev_priv = dev->dev_private;
		5199	int clock_limit =
		5200	dev_priv->display.get_display_clock_speed(dev);
		5201
		5202	/*
		5203	* Enable pixel doubling when the dot clock
		5204	* is > 90% of the (display) core speed.
		5205	*
		5206	* GDG double wide on either pipe,
		5207	* otherwise pipe A only.
		5208	*/
		5209	if ((crtc->pipe == PIPE_A \|\| IS_I915G(dev)) &&
		5210	adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
		5211	clock_limit *= 2;
		5212	pipe_config->double_wide = true;
		5213	}
		5214
		5215	if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4104	Serge	5216	return -EINVAL;
2330	Serge	5217	}
		5218
4560	Serge	5219	/*
		5220	* Pipe horizontal size must be even in:
		5221	* - DVO ganged mode
		5222	* - LVDS dual channel mode
		5223	* - Double wide pipe
		5224	*/
		5225	if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
		5226	intel_is_dual_link_lvds(dev)) \|\| pipe_config->double_wide)
		5227	pipe_config->pipe_src_w &= ~1;
		5228
4104	Serge	5229	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
		5230	* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
3031	serge	5231	*/
		5232	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
		5233	adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4104	Serge	5234	return -EINVAL;
3031	serge	5235
3746	Serge	5236	if ((IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
		5237	pipe_config->pipe_bpp = 103; / 12bpc is gen5+ */
		5238	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
		5239	/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		5240	* for lvds. */
		5241	pipe_config->pipe_bpp = 8*3;
		5242	}
		5243
4104	Serge	5244	if (HAS_IPS(dev))
		5245	hsw_compute_ips_config(crtc, pipe_config);
		5246
5060	serge	5247	/*
		5248	* XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
		5249	* old clock survives for now.
		5250	*/
		5251	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev) \|\| HAS_DDI(dev))
4104	Serge	5252	pipe_config->shared_dpll = crtc->config.shared_dpll;
		5253
		5254	if (pipe_config->has_pch_encoder)
		5255	return ironlake_fdi_compute_config(crtc, pipe_config);
		5256
		5257	return 0;
2330	Serge	5258	}
		5259
3031	serge	5260	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		5261	{
5060	serge	5262	struct drm_i915_private *dev_priv = dev->dev_private;
		5263	int vco = valleyview_get_vco(dev_priv);
		5264	u32 val;
		5265	int divider;
		5266
		5267	mutex_lock(&dev_priv->dpio_lock);
		5268	val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
		5269	mutex_unlock(&dev_priv->dpio_lock);
		5270
		5271	divider = val & DISPLAY_FREQUENCY_VALUES;
		5272
		5273	WARN((val & DISPLAY_FREQUENCY_STATUS) !=
		5274	(divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
		5275	"cdclk change in progress\n");
		5276
		5277	return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
3031	serge	5278	}
		5279
2327	Serge	5280	static int i945_get_display_clock_speed(struct drm_device *dev)
		5281	{
		5282	return 400000;
		5283	}
		5284
		5285	static int i915_get_display_clock_speed(struct drm_device *dev)
		5286	{
		5287	return 333000;
		5288	}
		5289
		5290	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		5291	{
		5292	return 200000;
		5293	}
		5294
4104	Serge	5295	static int pnv_get_display_clock_speed(struct drm_device *dev)
		5296	{
		5297	u16 gcfgc = 0;
		5298
		5299	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		5300
		5301	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		5302	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
		5303	return 267000;
		5304	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
		5305	return 333000;
		5306	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
		5307	return 444000;
		5308	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
		5309	return 200000;
		5310	default:
		5311	DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
		5312	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
		5313	return 133000;
		5314	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
		5315	return 167000;
		5316	}
		5317	}
		5318
2327	Serge	5319	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		5320	{
		5321	u16 gcfgc = 0;
		5322
		5323	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		5324
		5325	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		5326	return 133000;
		5327	else {
		5328	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		5329	case GC_DISPLAY_CLOCK_333_MHZ:
		5330	return 333000;
		5331	default:
		5332	case GC_DISPLAY_CLOCK_190_200_MHZ:
		5333	return 190000;
		5334	}
		5335	}
		5336	}
		5337
		5338	static int i865_get_display_clock_speed(struct drm_device *dev)
		5339	{
		5340	return 266000;
		5341	}
		5342
		5343	static int i855_get_display_clock_speed(struct drm_device *dev)
		5344	{
		5345	u16 hpllcc = 0;
		5346	/* Assume that the hardware is in the high speed state. This
		5347	* should be the default.
		5348	*/
		5349	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		5350	case GC_CLOCK_133_200:
		5351	case GC_CLOCK_100_200:
		5352	return 200000;
		5353	case GC_CLOCK_166_250:
		5354	return 250000;
		5355	case GC_CLOCK_100_133:
		5356	return 133000;
		5357	}
		5358
		5359	/* Shouldn't happen */
		5360	return 0;
		5361	}
		5362
		5363	static int i830_get_display_clock_speed(struct drm_device *dev)
		5364	{
		5365	return 133000;
		5366	}
		5367
		5368	static void
3746	Serge	5369	intel_reduce_m_n_ratio(uint32_t num, uint32_t den)
2327	Serge	5370	{
3746	Serge	5371	while (*num > DATA_LINK_M_N_MASK \|\|
		5372	*den > DATA_LINK_M_N_MASK) {
2327	Serge	5373	*num >>= 1;
		5374	*den >>= 1;
		5375	}
		5376	}
		5377
3746	Serge	5378	static void compute_m_n(unsigned int m, unsigned int n,
		5379	uint32_t ret_m, uint32_t ret_n)
		5380	{
		5381	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
		5382	ret_m = div_u64((uint64_t) m *ret_n, n);
		5383	intel_reduce_m_n_ratio(ret_m, ret_n);
		5384	}
		5385
3480	Serge	5386	void
		5387	intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		5388	int pixel_clock, int link_clock,
		5389	struct intel_link_m_n *m_n)
2327	Serge	5390	{
3480	Serge	5391	m_n->tu = 64;
3746	Serge	5392
		5393	compute_m_n(bits_per_pixel * pixel_clock,
		5394	link_clock * nlanes * 8,
		5395	&m_n->gmch_m, &m_n->gmch_n);
		5396
		5397	compute_m_n(pixel_clock, link_clock,
		5398	&m_n->link_m, &m_n->link_n);
2327	Serge	5399	}
		5400
		5401	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		5402	{
5060	serge	5403	if (i915.panel_use_ssc >= 0)
		5404	return i915.panel_use_ssc != 0;
4104	Serge	5405	return dev_priv->vbt.lvds_use_ssc
2327	Serge	5406	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		5407	}
		5408
3031	serge	5409	static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
		5410	{
		5411	struct drm_device *dev = crtc->dev;
		5412	struct drm_i915_private *dev_priv = dev->dev_private;
		5413	int refclk;
2327	Serge	5414
3031	serge	5415	if (IS_VALLEYVIEW(dev)) {
4560	Serge	5416	refclk = 100000;
3031	serge	5417	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		5418	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4560	Serge	5419	refclk = dev_priv->vbt.lvds_ssc_freq;
		5420	DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
3031	serge	5421	} else if (!IS_GEN2(dev)) {
		5422	refclk = 96000;
		5423	} else {
		5424	refclk = 48000;
		5425	}
2327	Serge	5426
3031	serge	5427	return refclk;
		5428	}
2327	Serge	5429
4104	Serge	5430	static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
3031	serge	5431	{
4104	Serge	5432	return (1 << dpll->n) << 16 \| dpll->m2;
		5433	}
3746	Serge	5434
4104	Serge	5435	static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
		5436	{
		5437	return dpll->n << 16 \| dpll->m1 << 8 \| dpll->m2;
3031	serge	5438	}
2327	Serge	5439
3746	Serge	5440	static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
3031	serge	5441	intel_clock_t *reduced_clock)
		5442	{
3746	Serge	5443	struct drm_device *dev = crtc->base.dev;
3031	serge	5444	u32 fp, fp2 = 0;
2327	Serge	5445
3031	serge	5446	if (IS_PINEVIEW(dev)) {
4104	Serge	5447	fp = pnv_dpll_compute_fp(&crtc->config.dpll);
3031	serge	5448	if (reduced_clock)
4104	Serge	5449	fp2 = pnv_dpll_compute_fp(reduced_clock);
3031	serge	5450	} else {
4104	Serge	5451	fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
3031	serge	5452	if (reduced_clock)
4104	Serge	5453	fp2 = i9xx_dpll_compute_fp(reduced_clock);
3031	serge	5454	}
2327	Serge	5455
4104	Serge	5456	crtc->config.dpll_hw_state.fp0 = fp;
2327	Serge	5457
3746	Serge	5458	crtc->lowfreq_avail = false;
		5459	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5060	serge	5460	reduced_clock && i915.powersave) {
4104	Serge	5461	crtc->config.dpll_hw_state.fp1 = fp2;
3746	Serge	5462	crtc->lowfreq_avail = true;
3031	serge	5463	} else {
4104	Serge	5464	crtc->config.dpll_hw_state.fp1 = fp;
3031	serge	5465	}
		5466	}
2327	Serge	5467
4560	Serge	5468	static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
		5469	pipe)
4104	Serge	5470	{
		5471	u32 reg_val;
		5472
		5473	/*
		5474	* PLLB opamp always calibrates to max value of 0x3f, force enable it
		5475	* and set it to a reasonable value instead.
		5476	*/
4560	Serge	5477	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4104	Serge	5478	reg_val &= 0xffffff00;
		5479	reg_val \|= 0x00000030;
4560	Serge	5480	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4104	Serge	5481
4560	Serge	5482	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4104	Serge	5483	reg_val &= 0x8cffffff;
		5484	reg_val = 0x8c000000;
4560	Serge	5485	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4104	Serge	5486
4560	Serge	5487	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4104	Serge	5488	reg_val &= 0xffffff00;
4560	Serge	5489	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4104	Serge	5490
4560	Serge	5491	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4104	Serge	5492	reg_val &= 0x00ffffff;
		5493	reg_val \|= 0xb0000000;
4560	Serge	5494	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4104	Serge	5495	}
		5496
		5497	static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
		5498	struct intel_link_m_n *m_n)
		5499	{
		5500	struct drm_device *dev = crtc->base.dev;
		5501	struct drm_i915_private *dev_priv = dev->dev_private;
		5502	int pipe = crtc->pipe;
		5503
		5504	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		5505	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
		5506	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
		5507	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
		5508	}
		5509
		5510	static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
		5511	struct intel_link_m_n *m_n)
		5512	{
		5513	struct drm_device *dev = crtc->base.dev;
		5514	struct drm_i915_private *dev_priv = dev->dev_private;
		5515	int pipe = crtc->pipe;
		5516	enum transcoder transcoder = crtc->config.cpu_transcoder;
		5517
		5518	if (INTEL_INFO(dev)->gen >= 5) {
		5519	I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		5520	I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		5521	I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		5522	I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
		5523	} else {
		5524	I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		5525	I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
		5526	I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
		5527	I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
		5528	}
		5529	}
		5530
3746	Serge	5531	static void intel_dp_set_m_n(struct intel_crtc *crtc)
3031	serge	5532	{
3746	Serge	5533	if (crtc->config.has_pch_encoder)
		5534	intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		5535	else
		5536	intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		5537	}
		5538
		5539	static void vlv_update_pll(struct intel_crtc *crtc)
		5540	{
5060	serge	5541	u32 dpll, dpll_md;
		5542
		5543	/*
		5544	* Enable DPIO clock input. We should never disable the reference
		5545	* clock for pipe B, since VGA hotplug / manual detection depends
		5546	* on it.
		5547	*/
		5548	dpll = DPLL_EXT_BUFFER_ENABLE_VLV \| DPLL_REFA_CLK_ENABLE_VLV \|
		5549	DPLL_VGA_MODE_DIS \| DPLL_INTEGRATED_CLOCK_VLV;
		5550	/* We should never disable this, set it here for state tracking */
		5551	if (crtc->pipe == PIPE_B)
		5552	dpll \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		5553	dpll \|= DPLL_VCO_ENABLE;
		5554	crtc->config.dpll_hw_state.dpll = dpll;
		5555
		5556	dpll_md = (crtc->config.pixel_multiplier - 1)
		5557	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		5558	crtc->config.dpll_hw_state.dpll_md = dpll_md;
		5559	}
		5560
		5561	static void vlv_prepare_pll(struct intel_crtc *crtc)
		5562	{
3746	Serge	5563	struct drm_device *dev = crtc->base.dev;
3031	serge	5564	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	5565	int pipe = crtc->pipe;
5060	serge	5566	u32 mdiv;
3031	serge	5567	u32 bestn, bestm1, bestm2, bestp1, bestp2;
5060	serge	5568	u32 coreclk, reg_val;
2327	Serge	5569
3480	Serge	5570	mutex_lock(&dev_priv->dpio_lock);
		5571
3746	Serge	5572	bestn = crtc->config.dpll.n;
		5573	bestm1 = crtc->config.dpll.m1;
		5574	bestm2 = crtc->config.dpll.m2;
		5575	bestp1 = crtc->config.dpll.p1;
		5576	bestp2 = crtc->config.dpll.p2;
3031	serge	5577
4104	Serge	5578	/* See eDP HDMI DPIO driver vbios notes doc */
		5579
		5580	/* PLL B needs special handling */
5060	serge	5581	if (pipe == PIPE_B)
4560	Serge	5582	vlv_pllb_recal_opamp(dev_priv, pipe);
4104	Serge	5583
		5584	/* Set up Tx target for periodic Rcomp update */
4560	Serge	5585	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4104	Serge	5586
		5587	/* Disable target IRef on PLL */
4560	Serge	5588	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4104	Serge	5589	reg_val &= 0x00ffffff;
4560	Serge	5590	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4104	Serge	5591
		5592	/* Disable fast lock */
4560	Serge	5593	vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4104	Serge	5594
		5595	/* Set idtafcrecal before PLL is enabled */
3031	serge	5596	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		5597	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		5598	mdiv \|= ((bestn << DPIO_N_SHIFT));
		5599	mdiv \|= (1 << DPIO_K_SHIFT);
4104	Serge	5600
		5601	/*
		5602	* Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
		5603	* but we don't support that).
		5604	* Note: don't use the DAC post divider as it seems unstable.
		5605	*/
		5606	mdiv \|= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4560	Serge	5607	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4104	Serge	5608
3031	serge	5609	mdiv \|= DPIO_ENABLE_CALIBRATION;
4560	Serge	5610	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
3031	serge	5611
4104	Serge	5612	/* Set HBR and RBR LPF coefficients */
		5613	if (crtc->config.port_clock == 162000 \|\|
		5614	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) \|\|
		5615	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4560	Serge	5616	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4104	Serge	5617	0x009f0003);
		5618	else
4560	Serge	5619	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4104	Serge	5620	0x00d0000f);
3031	serge	5621
4104	Serge	5622	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) \|\|
		5623	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
		5624	/* Use SSC source */
5060	serge	5625	if (pipe == PIPE_A)
4560	Serge	5626	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104	Serge	5627	0x0df40000);
		5628	else
4560	Serge	5629	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104	Serge	5630	0x0df70000);
		5631	} else { /* HDMI or VGA */
		5632	/* Use bend source */
5060	serge	5633	if (pipe == PIPE_A)
4560	Serge	5634	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104	Serge	5635	0x0df70000);
		5636	else
4560	Serge	5637	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4104	Serge	5638	0x0df40000);
		5639	}
3031	serge	5640
4560	Serge	5641	coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4104	Serge	5642	coreclk = (coreclk & 0x0000ff00) \| 0x01c00000;
		5643	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) \|\|
		5644	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
		5645	coreclk \|= 0x01000000;
4560	Serge	5646	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
3031	serge	5647
4560	Serge	5648	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5060	serge	5649	mutex_unlock(&dev_priv->dpio_lock);
		5650	}
4104	Serge	5651
5060	serge	5652	static void chv_update_pll(struct intel_crtc *crtc)
		5653	{
		5654	struct drm_device *dev = crtc->base.dev;
		5655	struct drm_i915_private *dev_priv = dev->dev_private;
		5656	int pipe = crtc->pipe;
		5657	int dpll_reg = DPLL(crtc->pipe);
		5658	enum dpio_channel port = vlv_pipe_to_channel(pipe);
		5659	u32 loopfilter, intcoeff;
		5660	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
		5661	int refclk;
		5662
		5663	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV \|
		5664	DPLL_REFA_CLK_ENABLE_VLV \| DPLL_VGA_MODE_DIS \|
		5665	DPLL_VCO_ENABLE;
		5666	if (pipe != PIPE_A)
		5667	crtc->config.dpll_hw_state.dpll \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		5668
		5669	crtc->config.dpll_hw_state.dpll_md =
		5670	(crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		5671
		5672	bestn = crtc->config.dpll.n;
		5673	bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
		5674	bestm1 = crtc->config.dpll.m1;
		5675	bestm2 = crtc->config.dpll.m2 >> 22;
		5676	bestp1 = crtc->config.dpll.p1;
		5677	bestp2 = crtc->config.dpll.p2;
		5678
4560	Serge	5679	/*
5060	serge	5680	* Enable Refclk and SSC
4560	Serge	5681	*/
5060	serge	5682	I915_WRITE(dpll_reg,
		5683	crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
3031	serge	5684
5060	serge	5685	mutex_lock(&dev_priv->dpio_lock);
3031	serge	5686
5060	serge	5687	/* p1 and p2 divider */
		5688	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
		5689	5 << DPIO_CHV_S1_DIV_SHIFT \|
		5690	bestp1 << DPIO_CHV_P1_DIV_SHIFT \|
		5691	bestp2 << DPIO_CHV_P2_DIV_SHIFT \|
		5692	1 << DPIO_CHV_K_DIV_SHIFT);
3243	Serge	5693
5060	serge	5694	/* Feedback post-divider - m2 */
		5695	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
		5696
		5697	/* Feedback refclk divider - n and m1 */
		5698	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
		5699	DPIO_CHV_M1_DIV_BY_2 \|
		5700	1 << DPIO_CHV_N_DIV_SHIFT);
		5701
		5702	/* M2 fraction division */
		5703	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
		5704
		5705	/* M2 fraction division enable */
		5706	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
		5707	DPIO_CHV_FRAC_DIV_EN \|
		5708	(2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
		5709
		5710	/* Loop filter */
		5711	refclk = i9xx_get_refclk(&crtc->base, 0);
		5712	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT \|
		5713	2 << DPIO_CHV_GAIN_CTRL_SHIFT;
		5714	if (refclk == 100000)
		5715	intcoeff = 11;
		5716	else if (refclk == 38400)
		5717	intcoeff = 10;
		5718	else
		5719	intcoeff = 9;
		5720	loopfilter \|= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
		5721	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
		5722
		5723	/* AFC Recal */
		5724	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
		5725	vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) \|
		5726	DPIO_AFC_RECAL);
		5727
3480	Serge	5728	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	5729	}
		5730
3746	Serge	5731	static void i9xx_update_pll(struct intel_crtc *crtc,
		5732	intel_clock_t *reduced_clock,
3031	serge	5733	int num_connectors)
		5734	{
3746	Serge	5735	struct drm_device *dev = crtc->base.dev;
3031	serge	5736	struct drm_i915_private *dev_priv = dev->dev_private;
		5737	u32 dpll;
		5738	bool is_sdvo;
3746	Serge	5739	struct dpll *clock = &crtc->config.dpll;
3031	serge	5740
3746	Serge	5741	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	5742
3746	Serge	5743	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) \|\|
		5744	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
3031	serge	5745
		5746	dpll = DPLL_VGA_MODE_DIS;
		5747
3746	Serge	5748	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
3031	serge	5749	dpll \|= DPLLB_MODE_LVDS;
		5750	else
		5751	dpll \|= DPLLB_MODE_DAC_SERIAL;
3746	Serge	5752
4104	Serge	5753	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
3746	Serge	5754	dpll \|= (crtc->config.pixel_multiplier - 1)
		5755	<< SDVO_MULTIPLIER_SHIFT_HIRES;
2342	Serge	5756	}
4104	Serge	5757
		5758	if (is_sdvo)
		5759	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5760
3746	Serge	5761	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4104	Serge	5762	dpll \|= DPLL_SDVO_HIGH_SPEED;
2342	Serge	5763
3031	serge	5764	/* compute bitmask from p1 value */
		5765	if (IS_PINEVIEW(dev))
		5766	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		5767	else {
		5768	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		5769	if (IS_G4X(dev) && reduced_clock)
		5770	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		5771	}
		5772	switch (clock->p2) {
		5773	case 5:
		5774	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		5775	break;
		5776	case 7:
		5777	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		5778	break;
		5779	case 10:
		5780	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		5781	break;
		5782	case 14:
		5783	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		5784	break;
		5785	}
		5786	if (INTEL_INFO(dev)->gen >= 4)
		5787	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	5788
4104	Serge	5789	if (crtc->config.sdvo_tv_clock)
3031	serge	5790	dpll \|= PLL_REF_INPUT_TVCLKINBC;
3746	Serge	5791	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	5792	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		5793	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5794	else
		5795	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	5796
3031	serge	5797	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	5798	crtc->config.dpll_hw_state.dpll = dpll;
2327	Serge	5799
4104	Serge	5800	if (INTEL_INFO(dev)->gen >= 4) {
		5801	u32 dpll_md = (crtc->config.pixel_multiplier - 1)
		5802	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		5803	crtc->config.dpll_hw_state.dpll_md = dpll_md;
		5804	}
3031	serge	5805	}
2327	Serge	5806
3746	Serge	5807	static void i8xx_update_pll(struct intel_crtc *crtc,
		5808	intel_clock_t *reduced_clock,
3031	serge	5809	int num_connectors)
		5810	{
3746	Serge	5811	struct drm_device *dev = crtc->base.dev;
3031	serge	5812	struct drm_i915_private *dev_priv = dev->dev_private;
		5813	u32 dpll;
3746	Serge	5814	struct dpll *clock = &crtc->config.dpll;
2327	Serge	5815
3746	Serge	5816	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	5817
3031	serge	5818	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	5819
3746	Serge	5820	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
3031	serge	5821	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		5822	} else {
		5823	if (clock->p1 == 2)
		5824	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		5825	else
		5826	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		5827	if (clock->p2 == 4)
		5828	dpll \|= PLL_P2_DIVIDE_BY_4;
		5829	}
2327	Serge	5830
4104	Serge	5831	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
		5832	dpll \|= DPLL_DVO_2X_MODE;
		5833
3746	Serge	5834	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	5835	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		5836	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5837	else
		5838	dpll \|= PLL_REF_INPUT_DREFCLK;
		5839
		5840	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	5841	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	5842	}
		5843
4104	Serge	5844	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
3243	Serge	5845	{
		5846	struct drm_device *dev = intel_crtc->base.dev;
		5847	struct drm_i915_private *dev_priv = dev->dev_private;
		5848	enum pipe pipe = intel_crtc->pipe;
3746	Serge	5849	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4104	Serge	5850	struct drm_display_mode *adjusted_mode =
		5851	&intel_crtc->config.adjusted_mode;
5060	serge	5852	uint32_t crtc_vtotal, crtc_vblank_end;
		5853	int vsyncshift = 0;
3243	Serge	5854
4104	Serge	5855	/* We need to be careful not to changed the adjusted mode, for otherwise
		5856	* the hw state checker will get angry at the mismatch. */
		5857	crtc_vtotal = adjusted_mode->crtc_vtotal;
		5858	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
		5859
5060	serge	5860	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3243	Serge	5861	/* the chip adds 2 halflines automatically */
4104	Serge	5862	crtc_vtotal -= 1;
		5863	crtc_vblank_end -= 1;
5060	serge	5864
		5865	if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
		5866	vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
		5867	else
		5868	vsyncshift = adjusted_mode->crtc_hsync_start -
		5869	adjusted_mode->crtc_htotal / 2;
		5870	if (vsyncshift < 0)
		5871	vsyncshift += adjusted_mode->crtc_htotal;
3243	Serge	5872	}
		5873
		5874	if (INTEL_INFO(dev)->gen > 3)
		5875	I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
		5876
		5877	I915_WRITE(HTOTAL(cpu_transcoder),
		5878	(adjusted_mode->crtc_hdisplay - 1) \|
		5879	((adjusted_mode->crtc_htotal - 1) << 16));
		5880	I915_WRITE(HBLANK(cpu_transcoder),
		5881	(adjusted_mode->crtc_hblank_start - 1) \|
		5882	((adjusted_mode->crtc_hblank_end - 1) << 16));
		5883	I915_WRITE(HSYNC(cpu_transcoder),
		5884	(adjusted_mode->crtc_hsync_start - 1) \|
		5885	((adjusted_mode->crtc_hsync_end - 1) << 16));
		5886
		5887	I915_WRITE(VTOTAL(cpu_transcoder),
		5888	(adjusted_mode->crtc_vdisplay - 1) \|
4104	Serge	5889	((crtc_vtotal - 1) << 16));
3243	Serge	5890	I915_WRITE(VBLANK(cpu_transcoder),
		5891	(adjusted_mode->crtc_vblank_start - 1) \|
4104	Serge	5892	((crtc_vblank_end - 1) << 16));
3243	Serge	5893	I915_WRITE(VSYNC(cpu_transcoder),
		5894	(adjusted_mode->crtc_vsync_start - 1) \|
		5895	((adjusted_mode->crtc_vsync_end - 1) << 16));
		5896
		5897	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
		5898	* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
		5899	* documented on the DDI_FUNC_CTL register description, EDP Input Select
		5900	* bits. */
		5901	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
		5902	(pipe == PIPE_B \|\| pipe == PIPE_C))
		5903	I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
		5904
		5905	/* pipesrc controls the size that is scaled from, which should
		5906	* always be the user's requested size.
		5907	*/
		5908	I915_WRITE(PIPESRC(pipe),
4560	Serge	5909	((intel_crtc->config.pipe_src_w - 1) << 16) \|
		5910	(intel_crtc->config.pipe_src_h - 1));
3243	Serge	5911	}
		5912
4104	Serge	5913	static void intel_get_pipe_timings(struct intel_crtc *crtc,
		5914	struct intel_crtc_config *pipe_config)
		5915	{
		5916	struct drm_device *dev = crtc->base.dev;
		5917	struct drm_i915_private *dev_priv = dev->dev_private;
		5918	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		5919	uint32_t tmp;
		5920
		5921	tmp = I915_READ(HTOTAL(cpu_transcoder));
		5922	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
		5923	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
		5924	tmp = I915_READ(HBLANK(cpu_transcoder));
		5925	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
		5926	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
		5927	tmp = I915_READ(HSYNC(cpu_transcoder));
		5928	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
		5929	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
		5930
		5931	tmp = I915_READ(VTOTAL(cpu_transcoder));
		5932	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
		5933	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
		5934	tmp = I915_READ(VBLANK(cpu_transcoder));
		5935	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
		5936	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
		5937	tmp = I915_READ(VSYNC(cpu_transcoder));
		5938	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
		5939	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
		5940
		5941	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
		5942	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		5943	pipe_config->adjusted_mode.crtc_vtotal += 1;
		5944	pipe_config->adjusted_mode.crtc_vblank_end += 1;
		5945	}
		5946
		5947	tmp = I915_READ(PIPESRC(crtc->pipe));
4560	Serge	5948	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
		5949	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
		5950
		5951	pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
		5952	pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4104	Serge	5953	}
		5954
5060	serge	5955	void intel_mode_from_pipe_config(struct drm_display_mode *mode,
4104	Serge	5956	struct intel_crtc_config *pipe_config)
		5957	{
5060	serge	5958	mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
		5959	mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
		5960	mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
		5961	mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4104	Serge	5962
5060	serge	5963	mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
		5964	mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
		5965	mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
		5966	mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4104	Serge	5967
5060	serge	5968	mode->flags = pipe_config->adjusted_mode.flags;
4104	Serge	5969
5060	serge	5970	mode->clock = pipe_config->adjusted_mode.crtc_clock;
		5971	mode->flags \|= pipe_config->adjusted_mode.flags;
4104	Serge	5972	}
		5973
3746	Serge	5974	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
		5975	{
		5976	struct drm_device *dev = intel_crtc->base.dev;
		5977	struct drm_i915_private *dev_priv = dev->dev_private;
		5978	uint32_t pipeconf;
		5979
4104	Serge	5980	pipeconf = 0;
3746	Serge	5981
4104	Serge	5982	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		5983	I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
		5984	pipeconf \|= PIPECONF_ENABLE;
		5985
4560	Serge	5986	if (intel_crtc->config.double_wide)
3746	Serge	5987	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		5988
4104	Serge	5989	/* only g4x and later have fancy bpc/dither controls */
		5990	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		5991	/* Bspec claims that we can't use dithering for 30bpp pipes. */
		5992	if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
		5993	pipeconf \|= PIPECONF_DITHER_EN \|
3746	Serge	5994	PIPECONF_DITHER_TYPE_SP;
		5995
4104	Serge	5996	switch (intel_crtc->config.pipe_bpp) {
		5997	case 18:
		5998	pipeconf \|= PIPECONF_6BPC;
		5999	break;
		6000	case 24:
		6001	pipeconf \|= PIPECONF_8BPC;
		6002	break;
		6003	case 30:
		6004	pipeconf \|= PIPECONF_10BPC;
		6005	break;
		6006	default:
		6007	/* Case prevented by intel_choose_pipe_bpp_dither. */
		6008	BUG();
3746	Serge	6009	}
		6010	}
		6011
		6012	if (HAS_PIPE_CXSR(dev)) {
		6013	if (intel_crtc->lowfreq_avail) {
		6014	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		6015	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		6016	} else {
		6017	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		6018	}
		6019	}
		6020
5060	serge	6021	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
		6022	if (INTEL_INFO(dev)->gen < 4 \|\|
		6023	intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
3746	Serge	6024	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		6025	else
5060	serge	6026	pipeconf \|= PIPECONF_INTERLACE_W_SYNC_SHIFT;
		6027	} else
3746	Serge	6028	pipeconf \|= PIPECONF_PROGRESSIVE;
		6029
4104	Serge	6030	if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
3746	Serge	6031	pipeconf \|= PIPECONF_COLOR_RANGE_SELECT;
		6032
		6033	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
		6034	POSTING_READ(PIPECONF(intel_crtc->pipe));
		6035	}
		6036
3031	serge	6037	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		6038	int x, int y,
		6039	struct drm_framebuffer *fb)
		6040	{
		6041	struct drm_device *dev = crtc->dev;
		6042	struct drm_i915_private *dev_priv = dev->dev_private;
		6043	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6044	int refclk, num_connectors = 0;
		6045	intel_clock_t clock, reduced_clock;
4104	Serge	6046	bool ok, has_reduced_clock = false;
4560	Serge	6047	bool is_lvds = false, is_dsi = false;
3031	serge	6048	struct intel_encoder *encoder;
		6049	const intel_limit_t *limit;
		6050
		6051	for_each_encoder_on_crtc(dev, crtc, encoder) {
		6052	switch (encoder->type) {
		6053	case INTEL_OUTPUT_LVDS:
		6054	is_lvds = true;
		6055	break;
4560	Serge	6056	case INTEL_OUTPUT_DSI:
		6057	is_dsi = true;
		6058	break;
3031	serge	6059	}
		6060
		6061	num_connectors++;
		6062	}
		6063
4560	Serge	6064	if (is_dsi)
5060	serge	6065	return 0;
4560	Serge	6066
		6067	if (!intel_crtc->config.clock_set) {
3031	serge	6068	refclk = i9xx_get_refclk(crtc, num_connectors);
		6069
		6070	/*
4560	Serge	6071	* Returns a set of divisors for the desired target clock with
		6072	* the given refclk, or FALSE. The returned values represent
		6073	* the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
		6074	* 2) / p1 / p2.
3031	serge	6075	*/
		6076	limit = intel_limit(crtc, refclk);
4104	Serge	6077	ok = dev_priv->display.find_dpll(limit, crtc,
		6078	intel_crtc->config.port_clock,
		6079	refclk, NULL, &clock);
4560	Serge	6080	if (!ok) {
3031	serge	6081	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		6082	return -EINVAL;
		6083	}
		6084
		6085	if (is_lvds && dev_priv->lvds_downclock_avail) {
		6086	/*
4560	Serge	6087	* Ensure we match the reduced clock's P to the target
		6088	* clock. If the clocks don't match, we can't switch
		6089	* the display clock by using the FP0/FP1. In such case
		6090	* we will disable the LVDS downclock feature.
3031	serge	6091	*/
4104	Serge	6092	has_reduced_clock =
		6093	dev_priv->display.find_dpll(limit, crtc,
3031	serge	6094	dev_priv->lvds_downclock,
4104	Serge	6095	refclk, &clock,
3031	serge	6096	&reduced_clock);
		6097	}
3746	Serge	6098	/* Compat-code for transition, will disappear. */
		6099	intel_crtc->config.dpll.n = clock.n;
		6100	intel_crtc->config.dpll.m1 = clock.m1;
		6101	intel_crtc->config.dpll.m2 = clock.m2;
		6102	intel_crtc->config.dpll.p1 = clock.p1;
		6103	intel_crtc->config.dpll.p2 = clock.p2;
		6104	}
3031	serge	6105
4560	Serge	6106	if (IS_GEN2(dev)) {
4104	Serge	6107	i8xx_update_pll(intel_crtc,
3243	Serge	6108	has_reduced_clock ? &reduced_clock : NULL,
		6109	num_connectors);
5060	serge	6110	} else if (IS_CHERRYVIEW(dev)) {
		6111	chv_update_pll(intel_crtc);
4560	Serge	6112	} else if (IS_VALLEYVIEW(dev)) {
3746	Serge	6113	vlv_update_pll(intel_crtc);
4560	Serge	6114	} else {
3746	Serge	6115	i9xx_update_pll(intel_crtc,
3031	serge	6116	has_reduced_clock ? &reduced_clock : NULL,
		6117	num_connectors);
4560	Serge	6118	}
3031	serge	6119
5060	serge	6120	return 0;
2327	Serge	6121	}
		6122
4104	Serge	6123	static void i9xx_get_pfit_config(struct intel_crtc *crtc,
		6124	struct intel_crtc_config *pipe_config)
		6125	{
		6126	struct drm_device *dev = crtc->base.dev;
		6127	struct drm_i915_private *dev_priv = dev->dev_private;
		6128	uint32_t tmp;
		6129
4560	Serge	6130	if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) \|\| !IS_MOBILE(dev)))
		6131	return;
		6132
4104	Serge	6133	tmp = I915_READ(PFIT_CONTROL);
		6134	if (!(tmp & PFIT_ENABLE))
		6135	return;
		6136
		6137	/* Check whether the pfit is attached to our pipe. */
		6138	if (INTEL_INFO(dev)->gen < 4) {
		6139	if (crtc->pipe != PIPE_B)
		6140	return;
		6141	} else {
		6142	if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
		6143	return;
		6144	}
		6145
		6146	pipe_config->gmch_pfit.control = tmp;
		6147	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
		6148	if (INTEL_INFO(dev)->gen < 5)
		6149	pipe_config->gmch_pfit.lvds_border_bits =
		6150	I915_READ(LVDS) & LVDS_BORDER_ENABLE;
		6151	}
		6152
4398	Serge	6153	static void vlv_crtc_clock_get(struct intel_crtc *crtc,
		6154	struct intel_crtc_config *pipe_config)
		6155	{
		6156	struct drm_device *dev = crtc->base.dev;
		6157	struct drm_i915_private *dev_priv = dev->dev_private;
		6158	int pipe = pipe_config->cpu_transcoder;
		6159	intel_clock_t clock;
		6160	u32 mdiv;
		6161	int refclk = 100000;
		6162
5060	serge	6163	/* In case of MIPI DPLL will not even be used */
		6164	if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
		6165	return;
		6166
4398	Serge	6167	mutex_lock(&dev_priv->dpio_lock);
4560	Serge	6168	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
4398	Serge	6169	mutex_unlock(&dev_priv->dpio_lock);
		6170
		6171	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
		6172	clock.m2 = mdiv & DPIO_M2DIV_MASK;
		6173	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
		6174	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
		6175	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
		6176
4560	Serge	6177	vlv_clock(refclk, &clock);
4398	Serge	6178
4560	Serge	6179	/* clock.dot is the fast clock */
		6180	pipe_config->port_clock = clock.dot / 5;
4398	Serge	6181	}
		6182
5060	serge	6183	static void i9xx_get_plane_config(struct intel_crtc *crtc,
		6184	struct intel_plane_config *plane_config)
		6185	{
		6186	struct drm_device *dev = crtc->base.dev;
		6187	struct drm_i915_private *dev_priv = dev->dev_private;
		6188	u32 val, base, offset;
		6189	int pipe = crtc->pipe, plane = crtc->plane;
		6190	int fourcc, pixel_format;
		6191	int aligned_height;
		6192
		6193	crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
		6194	if (!crtc->base.primary->fb) {
		6195	DRM_DEBUG_KMS("failed to alloc fb\n");
		6196	return;
		6197	}
		6198
		6199	val = I915_READ(DSPCNTR(plane));
		6200
		6201	if (INTEL_INFO(dev)->gen >= 4)
		6202	if (val & DISPPLANE_TILED)
		6203	plane_config->tiled = true;
		6204
		6205	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
		6206	fourcc = intel_format_to_fourcc(pixel_format);
		6207	crtc->base.primary->fb->pixel_format = fourcc;
		6208	crtc->base.primary->fb->bits_per_pixel =
		6209	drm_format_plane_cpp(fourcc, 0) * 8;
		6210
		6211	if (INTEL_INFO(dev)->gen >= 4) {
		6212	if (plane_config->tiled)
		6213	offset = I915_READ(DSPTILEOFF(plane));
		6214	else
		6215	offset = I915_READ(DSPLINOFF(plane));
		6216	base = I915_READ(DSPSURF(plane)) & 0xfffff000;
		6217	} else {
		6218	base = I915_READ(DSPADDR(plane));
		6219	}
		6220	plane_config->base = base;
		6221
		6222	val = I915_READ(PIPESRC(pipe));
		6223	crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
		6224	crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
		6225
		6226	val = I915_READ(DSPSTRIDE(pipe));
		6227	crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
		6228
		6229	aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
		6230	plane_config->tiled);
		6231
		6232	plane_config->size = 1610241024;
		6233
		6234
		6235	DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
		6236	pipe, plane, crtc->base.primary->fb->width,
		6237	crtc->base.primary->fb->height,
		6238	crtc->base.primary->fb->bits_per_pixel, base,
		6239	crtc->base.primary->fb->pitches[0],
		6240	plane_config->size);
		6241
		6242	}
		6243
		6244	static void chv_crtc_clock_get(struct intel_crtc *crtc,
		6245	struct intel_crtc_config *pipe_config)
		6246	{
		6247	struct drm_device *dev = crtc->base.dev;
		6248	struct drm_i915_private *dev_priv = dev->dev_private;
		6249	int pipe = pipe_config->cpu_transcoder;
		6250	enum dpio_channel port = vlv_pipe_to_channel(pipe);
		6251	intel_clock_t clock;
		6252	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
		6253	int refclk = 100000;
		6254
		6255	mutex_lock(&dev_priv->dpio_lock);
		6256	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
		6257	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
		6258	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
		6259	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
		6260	mutex_unlock(&dev_priv->dpio_lock);
		6261
		6262	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
		6263	clock.m2 = ((pll_dw0 & 0xff) << 22) \| (pll_dw2 & 0x3fffff);
		6264	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
		6265	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
		6266	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
		6267
		6268	chv_clock(refclk, &clock);
		6269
		6270	/* clock.dot is the fast clock */
		6271	pipe_config->port_clock = clock.dot / 5;
		6272	}
		6273
3746	Serge	6274	static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
		6275	struct intel_crtc_config *pipe_config)
		6276	{
		6277	struct drm_device *dev = crtc->base.dev;
		6278	struct drm_i915_private *dev_priv = dev->dev_private;
		6279	uint32_t tmp;
		6280
5060	serge	6281	if (!intel_display_power_enabled(dev_priv,
		6282	POWER_DOMAIN_PIPE(crtc->pipe)))
		6283	return false;
		6284
4104	Serge	6285	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		6286	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		6287
3746	Serge	6288	tmp = I915_READ(PIPECONF(crtc->pipe));
		6289	if (!(tmp & PIPECONF_ENABLE))
		6290	return false;
		6291
4280	Serge	6292	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		6293	switch (tmp & PIPECONF_BPC_MASK) {
		6294	case PIPECONF_6BPC:
		6295	pipe_config->pipe_bpp = 18;
		6296	break;
		6297	case PIPECONF_8BPC:
		6298	pipe_config->pipe_bpp = 24;
		6299	break;
		6300	case PIPECONF_10BPC:
		6301	pipe_config->pipe_bpp = 30;
		6302	break;
		6303	default:
		6304	break;
		6305	}
		6306	}
		6307
5060	serge	6308	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
		6309	pipe_config->limited_color_range = true;
		6310
4560	Serge	6311	if (INTEL_INFO(dev)->gen < 4)
		6312	pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
		6313
4104	Serge	6314	intel_get_pipe_timings(crtc, pipe_config);
		6315
		6316	i9xx_get_pfit_config(crtc, pipe_config);
		6317
		6318	if (INTEL_INFO(dev)->gen >= 4) {
		6319	tmp = I915_READ(DPLL_MD(crtc->pipe));
		6320	pipe_config->pixel_multiplier =
		6321	((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
		6322	>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
		6323	pipe_config->dpll_hw_state.dpll_md = tmp;
		6324	} else if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
		6325	tmp = I915_READ(DPLL(crtc->pipe));
		6326	pipe_config->pixel_multiplier =
		6327	((tmp & SDVO_MULTIPLIER_MASK)
		6328	>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
		6329	} else {
		6330	/* Note that on i915G/GM the pixel multiplier is in the sdvo
		6331	* port and will be fixed up in the encoder->get_config
		6332	* function. */
		6333	pipe_config->pixel_multiplier = 1;
		6334	}
		6335	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
		6336	if (!IS_VALLEYVIEW(dev)) {
		6337	pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
		6338	pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
		6339	} else {
		6340	/* Mask out read-only status bits. */
		6341	pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV \|
		6342	DPLL_PORTC_READY_MASK \|
		6343	DPLL_PORTB_READY_MASK);
		6344	}
		6345
5060	serge	6346	if (IS_CHERRYVIEW(dev))
		6347	chv_crtc_clock_get(crtc, pipe_config);
		6348	else if (IS_VALLEYVIEW(dev))
4560	Serge	6349	vlv_crtc_clock_get(crtc, pipe_config);
		6350	else
		6351	i9xx_crtc_clock_get(crtc, pipe_config);
		6352
3746	Serge	6353	return true;
		6354	}
		6355
3243	Serge	6356	static void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	6357	{
		6358	struct drm_i915_private *dev_priv = dev->dev_private;
		6359	struct drm_mode_config *mode_config = &dev->mode_config;
		6360	struct intel_encoder *encoder;
3746	Serge	6361	u32 val, final;
2327	Serge	6362	bool has_lvds = false;
2342	Serge	6363	bool has_cpu_edp = false;
		6364	bool has_panel = false;
		6365	bool has_ck505 = false;
		6366	bool can_ssc = false;
2327	Serge	6367
		6368	/* We need to take the global config into account */
		6369	list_for_each_entry(encoder, &mode_config->encoder_list,
		6370	base.head) {
		6371	switch (encoder->type) {
		6372	case INTEL_OUTPUT_LVDS:
2342	Serge	6373	has_panel = true;
2327	Serge	6374	has_lvds = true;
2342	Serge	6375	break;
2327	Serge	6376	case INTEL_OUTPUT_EDP:
2342	Serge	6377	has_panel = true;
4104	Serge	6378	if (enc_to_dig_port(&encoder->base)->port == PORT_A)
2342	Serge	6379	has_cpu_edp = true;
2327	Serge	6380	break;
		6381	}
		6382	}
2342	Serge	6383
		6384	if (HAS_PCH_IBX(dev)) {
4104	Serge	6385	has_ck505 = dev_priv->vbt.display_clock_mode;
2342	Serge	6386	can_ssc = has_ck505;
		6387	} else {
		6388	has_ck505 = false;
		6389	can_ssc = true;
2327	Serge	6390	}
		6391
4104	Serge	6392	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
		6393	has_panel, has_lvds, has_ck505);
2342	Serge	6394
2327	Serge	6395	/* Ironlake: try to setup display ref clock before DPLL
		6396	* enabling. This is only under driver's control after
		6397	* PCH B stepping, previous chipset stepping should be
		6398	* ignoring this setting.
		6399	*/
3746	Serge	6400	val = I915_READ(PCH_DREF_CONTROL);
		6401
		6402	/* As we must carefully and slowly disable/enable each source in turn,
		6403	* compute the final state we want first and check if we need to
		6404	* make any changes at all.
		6405	*/
		6406	final = val;
		6407	final &= ~DREF_NONSPREAD_SOURCE_MASK;
		6408	if (has_ck505)
		6409	final \|= DREF_NONSPREAD_CK505_ENABLE;
		6410	else
		6411	final \|= DREF_NONSPREAD_SOURCE_ENABLE;
		6412
		6413	final &= ~DREF_SSC_SOURCE_MASK;
		6414	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		6415	final &= ~DREF_SSC1_ENABLE;
		6416
		6417	if (has_panel) {
		6418	final \|= DREF_SSC_SOURCE_ENABLE;
		6419
		6420	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		6421	final \|= DREF_SSC1_ENABLE;
		6422
		6423	if (has_cpu_edp) {
		6424	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		6425	final \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		6426	else
		6427	final \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		6428	} else
		6429	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		6430	} else {
		6431	final \|= DREF_SSC_SOURCE_DISABLE;
		6432	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		6433	}
		6434
		6435	if (final == val)
		6436	return;
		6437
2327	Serge	6438	/* Always enable nonspread source */
3746	Serge	6439	val &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	6440
		6441	if (has_ck505)
3746	Serge	6442	val \|= DREF_NONSPREAD_CK505_ENABLE;
2342	Serge	6443	else
3746	Serge	6444	val \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	6445
		6446	if (has_panel) {
3746	Serge	6447	val &= ~DREF_SSC_SOURCE_MASK;
		6448	val \|= DREF_SSC_SOURCE_ENABLE;
2327	Serge	6449
2342	Serge	6450	/* SSC must be turned on before enabling the CPU output */
		6451	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		6452	DRM_DEBUG_KMS("Using SSC on panel\n");
3746	Serge	6453	val \|= DREF_SSC1_ENABLE;
3031	serge	6454	} else
3746	Serge	6455	val &= ~DREF_SSC1_ENABLE;
2327	Serge	6456
2342	Serge	6457	/* Get SSC going before enabling the outputs */
3746	Serge	6458	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	6459	POSTING_READ(PCH_DREF_CONTROL);
		6460	udelay(200);
2342	Serge	6461
3746	Serge	6462	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2327	Serge	6463
		6464	/* Enable CPU source on CPU attached eDP */
2342	Serge	6465	if (has_cpu_edp) {
		6466	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		6467	DRM_DEBUG_KMS("Using SSC on eDP\n");
3746	Serge	6468	val \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5060	serge	6469	} else
3746	Serge	6470	val \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	6471	} else
3746	Serge	6472	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	6473
3746	Serge	6474	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	6475	POSTING_READ(PCH_DREF_CONTROL);
		6476	udelay(200);
2327	Serge	6477	} else {
2342	Serge	6478	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		6479
3746	Serge	6480	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2342	Serge	6481
		6482	/* Turn off CPU output */
3746	Serge	6483	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	6484
3746	Serge	6485	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	6486	POSTING_READ(PCH_DREF_CONTROL);
		6487	udelay(200);
2342	Serge	6488
		6489	/* Turn off the SSC source */
3746	Serge	6490	val &= ~DREF_SSC_SOURCE_MASK;
		6491	val \|= DREF_SSC_SOURCE_DISABLE;
2342	Serge	6492
		6493	/* Turn off SSC1 */
3746	Serge	6494	val &= ~DREF_SSC1_ENABLE;
2342	Serge	6495
3746	Serge	6496	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	6497	POSTING_READ(PCH_DREF_CONTROL);
		6498	udelay(200);
2327	Serge	6499	}
3746	Serge	6500
		6501	BUG_ON(val != final);
2327	Serge	6502	}
		6503
4104	Serge	6504	static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
3243	Serge	6505	{
4104	Serge	6506	uint32_t tmp;
3243	Serge	6507
		6508	tmp = I915_READ(SOUTH_CHICKEN2);
		6509	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;
		6510	I915_WRITE(SOUTH_CHICKEN2, tmp);
		6511
		6512	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
		6513	FDI_MPHY_IOSFSB_RESET_STATUS, 100))
		6514	DRM_ERROR("FDI mPHY reset assert timeout\n");
		6515
		6516	tmp = I915_READ(SOUTH_CHICKEN2);
		6517	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		6518	I915_WRITE(SOUTH_CHICKEN2, tmp);
		6519
		6520	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4104	Serge	6521	FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
3243	Serge	6522	DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4539	Serge	6523	}
3243	Serge	6524
4104	Serge	6525	/* WaMPhyProgramming:hsw */
		6526	static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
		6527	{
		6528	uint32_t tmp;
		6529
3243	Serge	6530	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
		6531	tmp &= ~(0xFF << 24);
		6532	tmp \|= (0x12 << 24);
		6533	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
		6534
		6535	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
		6536	tmp \|= (1 << 11);
		6537	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
		6538
		6539	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
		6540	tmp \|= (1 << 11);
		6541	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
		6542
		6543	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
		6544	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		6545	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
		6546
		6547	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
		6548	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		6549	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
		6550
		6551	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		6552	tmp &= ~(7 << 13);
		6553	tmp \|= (5 << 13);
		6554	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
		6555
		6556	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		6557	tmp &= ~(7 << 13);
		6558	tmp \|= (5 << 13);
		6559	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
		6560
		6561	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
		6562	tmp &= ~0xFF;
		6563	tmp \|= 0x1C;
		6564	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
		6565
		6566	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
		6567	tmp &= ~0xFF;
		6568	tmp \|= 0x1C;
		6569	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
		6570
		6571	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
		6572	tmp &= ~(0xFF << 16);
		6573	tmp \|= (0x1C << 16);
		6574	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
		6575
		6576	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
		6577	tmp &= ~(0xFF << 16);
		6578	tmp \|= (0x1C << 16);
		6579	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
		6580
		6581	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		6582	tmp \|= (1 << 27);
		6583	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
		6584
		6585	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		6586	tmp \|= (1 << 27);
		6587	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
		6588
		6589	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		6590	tmp &= ~(0xF << 28);
		6591	tmp \|= (4 << 28);
		6592	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
		6593
		6594	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		6595	tmp &= ~(0xF << 28);
		6596	tmp \|= (4 << 28);
		6597	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
4539	Serge	6598	}
3243	Serge	6599
4104	Serge	6600	/* Implements 3 different sequences from BSpec chapter "Display iCLK
		6601	* Programming" based on the parameters passed:
		6602	* - Sequence to enable CLKOUT_DP
		6603	* - Sequence to enable CLKOUT_DP without spread
		6604	* - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
		6605	*/
		6606	static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
		6607	bool with_fdi)
		6608	{
		6609	struct drm_i915_private *dev_priv = dev->dev_private;
		6610	uint32_t reg, tmp;
3480	Serge	6611
4104	Serge	6612	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
		6613	with_spread = true;
		6614	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
		6615	with_fdi, "LP PCH doesn't have FDI\n"))
		6616	with_fdi = false;
		6617
		6618	mutex_lock(&dev_priv->dpio_lock);
		6619
		6620	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		6621	tmp &= ~SBI_SSCCTL_DISABLE;
		6622	tmp \|= SBI_SSCCTL_PATHALT;
		6623	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		6624
		6625	udelay(24);
		6626
		6627	if (with_spread) {
		6628	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		6629	tmp &= ~SBI_SSCCTL_PATHALT;
		6630	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		6631
		6632	if (with_fdi) {
		6633	lpt_reset_fdi_mphy(dev_priv);
		6634	lpt_program_fdi_mphy(dev_priv);
		6635	}
		6636	}
		6637
		6638	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		6639	SBI_GEN0 : SBI_DBUFF0;
		6640	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		6641	tmp \|= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		6642	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		6643
3480	Serge	6644	mutex_unlock(&dev_priv->dpio_lock);
3243	Serge	6645	}
		6646
4104	Serge	6647	/* Sequence to disable CLKOUT_DP */
		6648	static void lpt_disable_clkout_dp(struct drm_device *dev)
		6649	{
		6650	struct drm_i915_private *dev_priv = dev->dev_private;
		6651	uint32_t reg, tmp;
		6652
		6653	mutex_lock(&dev_priv->dpio_lock);
		6654
		6655	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		6656	SBI_GEN0 : SBI_DBUFF0;
		6657	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		6658	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		6659	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		6660
		6661	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		6662	if (!(tmp & SBI_SSCCTL_DISABLE)) {
		6663	if (!(tmp & SBI_SSCCTL_PATHALT)) {
		6664	tmp \|= SBI_SSCCTL_PATHALT;
		6665	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		6666	udelay(32);
		6667	}
		6668	tmp \|= SBI_SSCCTL_DISABLE;
		6669	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		6670	}
		6671
		6672	mutex_unlock(&dev_priv->dpio_lock);
		6673	}
		6674
		6675	static void lpt_init_pch_refclk(struct drm_device *dev)
		6676	{
		6677	struct drm_mode_config *mode_config = &dev->mode_config;
		6678	struct intel_encoder *encoder;
		6679	bool has_vga = false;
		6680
		6681	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		6682	switch (encoder->type) {
		6683	case INTEL_OUTPUT_ANALOG:
		6684	has_vga = true;
		6685	break;
		6686	}
		6687	}
		6688
		6689	if (has_vga)
		6690	lpt_enable_clkout_dp(dev, true, true);
		6691	else
		6692	lpt_disable_clkout_dp(dev);
		6693	}
		6694
3243	Serge	6695	/*
		6696	* Initialize reference clocks when the driver loads
		6697	*/
		6698	void intel_init_pch_refclk(struct drm_device *dev)
		6699	{
		6700	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		6701	ironlake_init_pch_refclk(dev);
		6702	else if (HAS_PCH_LPT(dev))
		6703	lpt_init_pch_refclk(dev);
		6704	}
		6705
2342	Serge	6706	static int ironlake_get_refclk(struct drm_crtc *crtc)
		6707	{
		6708	struct drm_device *dev = crtc->dev;
		6709	struct drm_i915_private *dev_priv = dev->dev_private;
		6710	struct intel_encoder *encoder;
		6711	int num_connectors = 0;
		6712	bool is_lvds = false;
		6713
3031	serge	6714	for_each_encoder_on_crtc(dev, crtc, encoder) {
2342	Serge	6715	switch (encoder->type) {
		6716	case INTEL_OUTPUT_LVDS:
		6717	is_lvds = true;
		6718	break;
		6719	}
		6720	num_connectors++;
		6721	}
		6722
		6723	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4560	Serge	6724	DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
4104	Serge	6725	dev_priv->vbt.lvds_ssc_freq);
4560	Serge	6726	return dev_priv->vbt.lvds_ssc_freq;
2342	Serge	6727	}
		6728
		6729	return 120000;
		6730	}
		6731
4104	Serge	6732	static void ironlake_set_pipeconf(struct drm_crtc *crtc)
3031	serge	6733	{
		6734	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		6735	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6736	int pipe = intel_crtc->pipe;
		6737	uint32_t val;
		6738
4104	Serge	6739	val = 0;
3031	serge	6740
3746	Serge	6741	switch (intel_crtc->config.pipe_bpp) {
3031	serge	6742	case 18:
3480	Serge	6743	val \|= PIPECONF_6BPC;
3031	serge	6744	break;
		6745	case 24:
3480	Serge	6746	val \|= PIPECONF_8BPC;
3031	serge	6747	break;
		6748	case 30:
3480	Serge	6749	val \|= PIPECONF_10BPC;
3031	serge	6750	break;
		6751	case 36:
3480	Serge	6752	val \|= PIPECONF_12BPC;
3031	serge	6753	break;
		6754	default:
3243	Serge	6755	/* Case prevented by intel_choose_pipe_bpp_dither. */
		6756	BUG();
3031	serge	6757	}
		6758
4104	Serge	6759	if (intel_crtc->config.dither)
3031	serge	6760	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		6761
4104	Serge	6762	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3031	serge	6763	val \|= PIPECONF_INTERLACED_ILK;
		6764	else
		6765	val \|= PIPECONF_PROGRESSIVE;
		6766
3746	Serge	6767	if (intel_crtc->config.limited_color_range)
3480	Serge	6768	val \|= PIPECONF_COLOR_RANGE_SELECT;
		6769
3031	serge	6770	I915_WRITE(PIPECONF(pipe), val);
		6771	POSTING_READ(PIPECONF(pipe));
		6772	}
		6773
3480	Serge	6774	/*
		6775	* Set up the pipe CSC unit.
		6776	*
		6777	* Currently only full range RGB to limited range RGB conversion
		6778	* is supported, but eventually this should handle various
		6779	* RGB<->YCbCr scenarios as well.
		6780	*/
3746	Serge	6781	static void intel_set_pipe_csc(struct drm_crtc *crtc)
3480	Serge	6782	{
		6783	struct drm_device *dev = crtc->dev;
		6784	struct drm_i915_private *dev_priv = dev->dev_private;
		6785	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6786	int pipe = intel_crtc->pipe;
		6787	uint16_t coeff = 0x7800; /* 1.0 */
		6788
		6789	/*
		6790	* TODO: Check what kind of values actually come out of the pipe
		6791	* with these coeff/postoff values and adjust to get the best
		6792	* accuracy. Perhaps we even need to take the bpc value into
		6793	* consideration.
		6794	*/
		6795
3746	Serge	6796	if (intel_crtc->config.limited_color_range)
3480	Serge	6797	coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
		6798
		6799	/*
		6800	* GY/GU and RY/RU should be the other way around according
		6801	* to BSpec, but reality doesn't agree. Just set them up in
		6802	* a way that results in the correct picture.
		6803	*/
		6804	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
		6805	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
		6806
		6807	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
		6808	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
		6809
		6810	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
		6811	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
		6812
		6813	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
		6814	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
		6815	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
		6816
		6817	if (INTEL_INFO(dev)->gen > 6) {
		6818	uint16_t postoff = 0;
		6819
3746	Serge	6820	if (intel_crtc->config.limited_color_range)
4398	Serge	6821	postoff = (16 * (1 << 12) / 255) & 0x1fff;
3480	Serge	6822
		6823	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		6824	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		6825	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
		6826
		6827	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
		6828	} else {
		6829	uint32_t mode = CSC_MODE_YUV_TO_RGB;
		6830
3746	Serge	6831	if (intel_crtc->config.limited_color_range)
3480	Serge	6832	mode \|= CSC_BLACK_SCREEN_OFFSET;
		6833
		6834	I915_WRITE(PIPE_CSC_MODE(pipe), mode);
		6835	}
		6836	}
		6837
4104	Serge	6838	static void haswell_set_pipeconf(struct drm_crtc *crtc)
3243	Serge	6839	{
4560	Serge	6840	struct drm_device *dev = crtc->dev;
		6841	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	6842	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4560	Serge	6843	enum pipe pipe = intel_crtc->pipe;
3746	Serge	6844	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	6845	uint32_t val;
		6846
4104	Serge	6847	val = 0;
3243	Serge	6848
4560	Serge	6849	if (IS_HASWELL(dev) && intel_crtc->config.dither)
3243	Serge	6850	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		6851
4104	Serge	6852	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3243	Serge	6853	val \|= PIPECONF_INTERLACED_ILK;
		6854	else
		6855	val \|= PIPECONF_PROGRESSIVE;
		6856
		6857	I915_WRITE(PIPECONF(cpu_transcoder), val);
		6858	POSTING_READ(PIPECONF(cpu_transcoder));
4104	Serge	6859
		6860	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
		6861	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
4560	Serge	6862
		6863	if (IS_BROADWELL(dev)) {
		6864	val = 0;
		6865
		6866	switch (intel_crtc->config.pipe_bpp) {
		6867	case 18:
		6868	val \|= PIPEMISC_DITHER_6_BPC;
		6869	break;
		6870	case 24:
		6871	val \|= PIPEMISC_DITHER_8_BPC;
		6872	break;
		6873	case 30:
		6874	val \|= PIPEMISC_DITHER_10_BPC;
		6875	break;
		6876	case 36:
		6877	val \|= PIPEMISC_DITHER_12_BPC;
		6878	break;
		6879	default:
		6880	/* Case prevented by pipe_config_set_bpp. */
		6881	BUG();
		6882	}
		6883
		6884	if (intel_crtc->config.dither)
		6885	val \|= PIPEMISC_DITHER_ENABLE \| PIPEMISC_DITHER_TYPE_SP;
		6886
		6887	I915_WRITE(PIPEMISC(pipe), val);
		6888	}
3243	Serge	6889	}
		6890
3031	serge	6891	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
		6892	intel_clock_t *clock,
		6893	bool *has_reduced_clock,
		6894	intel_clock_t *reduced_clock)
		6895	{
		6896	struct drm_device *dev = crtc->dev;
		6897	struct drm_i915_private *dev_priv = dev->dev_private;
		6898	struct intel_encoder *intel_encoder;
		6899	int refclk;
		6900	const intel_limit_t *limit;
4104	Serge	6901	bool ret, is_lvds = false;
3031	serge	6902
		6903	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		6904	switch (intel_encoder->type) {
		6905	case INTEL_OUTPUT_LVDS:
		6906	is_lvds = true;
		6907	break;
		6908	}
		6909	}
		6910
		6911	refclk = ironlake_get_refclk(crtc);
		6912
		6913	/*
		6914	* Returns a set of divisors for the desired target clock with the given
		6915	* refclk, or FALSE. The returned values represent the clock equation:
		6916	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		6917	*/
		6918	limit = intel_limit(crtc, refclk);
4104	Serge	6919	ret = dev_priv->display.find_dpll(limit, crtc,
		6920	to_intel_crtc(crtc)->config.port_clock,
		6921	refclk, NULL, clock);
3031	serge	6922	if (!ret)
		6923	return false;
		6924
		6925	if (is_lvds && dev_priv->lvds_downclock_avail) {
		6926	/*
		6927	* Ensure we match the reduced clock's P to the target clock.
		6928	* If the clocks don't match, we can't switch the display clock
		6929	* by using the FP0/FP1. In such case we will disable the LVDS
		6930	* downclock feature.
		6931	*/
4104	Serge	6932	*has_reduced_clock =
		6933	dev_priv->display.find_dpll(limit, crtc,
3031	serge	6934	dev_priv->lvds_downclock,
4104	Serge	6935	refclk, clock,
3031	serge	6936	reduced_clock);
		6937	}
		6938
		6939	return true;
		6940	}
		6941
3243	Serge	6942	int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
		6943	{
		6944	/*
		6945	* Account for spread spectrum to avoid
		6946	* oversubscribing the link. Max center spread
		6947	* is 2.5%; use 5% for safety's sake.
		6948	*/
		6949	u32 bps = target_clock * bpp * 21 / 20;
5060	serge	6950	return DIV_ROUND_UP(bps, link_bw * 8);
3243	Serge	6951	}
		6952
4104	Serge	6953	static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
2327	Serge	6954	{
4104	Serge	6955	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
3746	Serge	6956	}
		6957
3243	Serge	6958	static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4104	Serge	6959	u32 *fp,
3746	Serge	6960	intel_clock_t reduced_clock, u32 fp2)
3243	Serge	6961	{
		6962	struct drm_crtc *crtc = &intel_crtc->base;
		6963	struct drm_device *dev = crtc->dev;
		6964	struct drm_i915_private *dev_priv = dev->dev_private;
		6965	struct intel_encoder *intel_encoder;
		6966	uint32_t dpll;
3746	Serge	6967	int factor, num_connectors = 0;
4104	Serge	6968	bool is_lvds = false, is_sdvo = false;
3243	Serge	6969
		6970	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		6971	switch (intel_encoder->type) {
		6972	case INTEL_OUTPUT_LVDS:
		6973	is_lvds = true;
		6974	break;
		6975	case INTEL_OUTPUT_SDVO:
		6976	case INTEL_OUTPUT_HDMI:
		6977	is_sdvo = true;
		6978	break;
		6979	}
		6980
		6981	num_connectors++;
		6982	}
		6983
2327	Serge	6984	/* Enable autotuning of the PLL clock (if permissible) */
		6985	factor = 21;
		6986	if (is_lvds) {
		6987	if ((intel_panel_use_ssc(dev_priv) &&
4560	Serge	6988	dev_priv->vbt.lvds_ssc_freq == 100000) \|\|
3746	Serge	6989	(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
2327	Serge	6990	factor = 25;
4104	Serge	6991	} else if (intel_crtc->config.sdvo_tv_clock)
2327	Serge	6992	factor = 20;
		6993
4104	Serge	6994	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
3746	Serge	6995	*fp \|= FP_CB_TUNE;
2327	Serge	6996
3746	Serge	6997	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		6998	*fp2 \|= FP_CB_TUNE;
		6999
2327	Serge	7000	dpll = 0;
		7001
		7002	if (is_lvds)
		7003	dpll \|= DPLLB_MODE_LVDS;
		7004	else
		7005	dpll \|= DPLLB_MODE_DAC_SERIAL;
4104	Serge	7006
3746	Serge	7007	dpll \|= (intel_crtc->config.pixel_multiplier - 1)
		7008	<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2327	Serge	7009
4104	Serge	7010	if (is_sdvo)
		7011	dpll \|= DPLL_SDVO_HIGH_SPEED;
		7012	if (intel_crtc->config.has_dp_encoder)
		7013	dpll \|= DPLL_SDVO_HIGH_SPEED;
		7014
2327	Serge	7015	/* compute bitmask from p1 value */
4104	Serge	7016	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2327	Serge	7017	/* also FPA1 */
4104	Serge	7018	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2327	Serge	7019
4104	Serge	7020	switch (intel_crtc->config.dpll.p2) {
2327	Serge	7021	case 5:
		7022	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		7023	break;
		7024	case 7:
		7025	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		7026	break;
		7027	case 10:
		7028	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		7029	break;
		7030	case 14:
		7031	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		7032	break;
		7033	}
		7034
4104	Serge	7035	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
2327	Serge	7036	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		7037	else
		7038	dpll \|= PLL_REF_INPUT_DREFCLK;
		7039
4104	Serge	7040	return dpll \| DPLL_VCO_ENABLE;
3243	Serge	7041	}
		7042
		7043	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		7044	int x, int y,
		7045	struct drm_framebuffer *fb)
		7046	{
		7047	struct drm_device *dev = crtc->dev;
		7048	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7049	int num_connectors = 0;
		7050	intel_clock_t clock, reduced_clock;
4104	Serge	7051	u32 dpll = 0, fp = 0, fp2 = 0;
3243	Serge	7052	bool ok, has_reduced_clock = false;
3746	Serge	7053	bool is_lvds = false;
3243	Serge	7054	struct intel_encoder *encoder;
4104	Serge	7055	struct intel_shared_dpll *pll;
3243	Serge	7056
		7057	for_each_encoder_on_crtc(dev, crtc, encoder) {
		7058	switch (encoder->type) {
		7059	case INTEL_OUTPUT_LVDS:
		7060	is_lvds = true;
		7061	break;
		7062	}
		7063
		7064	num_connectors++;
		7065	}
		7066
		7067	WARN(!(HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)),
		7068	"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
		7069
4104	Serge	7070	ok = ironlake_compute_clocks(crtc, &clock,
3243	Serge	7071	&has_reduced_clock, &reduced_clock);
4104	Serge	7072	if (!ok && !intel_crtc->config.clock_set) {
3243	Serge	7073	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		7074	return -EINVAL;
		7075	}
3746	Serge	7076	/* Compat-code for transition, will disappear. */
		7077	if (!intel_crtc->config.clock_set) {
		7078	intel_crtc->config.dpll.n = clock.n;
		7079	intel_crtc->config.dpll.m1 = clock.m1;
		7080	intel_crtc->config.dpll.m2 = clock.m2;
		7081	intel_crtc->config.dpll.p1 = clock.p1;
		7082	intel_crtc->config.dpll.p2 = clock.p2;
		7083	}
3243	Serge	7084
4104	Serge	7085	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
		7086	if (intel_crtc->config.has_pch_encoder) {
		7087	fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
3243	Serge	7088	if (has_reduced_clock)
4104	Serge	7089	fp2 = i9xx_dpll_compute_fp(&reduced_clock);
3243	Serge	7090
4104	Serge	7091	dpll = ironlake_compute_dpll(intel_crtc,
		7092	&fp, &reduced_clock,
5060	serge	7093	has_reduced_clock ? &fp2 : NULL);
3243	Serge	7094
4104	Serge	7095	intel_crtc->config.dpll_hw_state.dpll = dpll;
		7096	intel_crtc->config.dpll_hw_state.fp0 = fp;
		7097	if (has_reduced_clock)
		7098	intel_crtc->config.dpll_hw_state.fp1 = fp2;
		7099	else
		7100	intel_crtc->config.dpll_hw_state.fp1 = fp;
2327	Serge	7101
4104	Serge	7102	pll = intel_get_shared_dpll(intel_crtc);
3031	serge	7103	if (pll == NULL) {
4104	Serge	7104	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5060	serge	7105	pipe_name(intel_crtc->pipe));
2342	Serge	7106	return -EINVAL;
2327	Serge	7107	}
3031	serge	7108	} else
4104	Serge	7109	intel_put_shared_dpll(intel_crtc);
2327	Serge	7110
5060	serge	7111	if (is_lvds && has_reduced_clock && i915.powersave)
4104	Serge	7112	intel_crtc->lowfreq_avail = true;
		7113	else
		7114	intel_crtc->lowfreq_avail = false;
2327	Serge	7115
5060	serge	7116	return 0;
4104	Serge	7117	}
3243	Serge	7118
4560	Serge	7119	static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
		7120	struct intel_link_m_n *m_n)
4104	Serge	7121	{
		7122	struct drm_device *dev = crtc->base.dev;
		7123	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	7124	enum pipe pipe = crtc->pipe;
4104	Serge	7125
4560	Serge	7126	m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
		7127	m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
		7128	m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
		7129	& ~TU_SIZE_MASK;
		7130	m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
		7131	m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
		7132	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
		7133	}
		7134
		7135	static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
		7136	enum transcoder transcoder,
		7137	struct intel_link_m_n *m_n)
		7138	{
		7139	struct drm_device *dev = crtc->base.dev;
		7140	struct drm_i915_private *dev_priv = dev->dev_private;
		7141	enum pipe pipe = crtc->pipe;
		7142
		7143	if (INTEL_INFO(dev)->gen >= 5) {
		7144	m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
		7145	m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
		7146	m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
4104	Serge	7147	& ~TU_SIZE_MASK;
4560	Serge	7148	m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
		7149	m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
4104	Serge	7150	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
4560	Serge	7151	} else {
		7152	m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
		7153	m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
		7154	m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
		7155	& ~TU_SIZE_MASK;
		7156	m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
		7157	m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
		7158	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
		7159	}
3243	Serge	7160	}
		7161
4560	Serge	7162	void intel_dp_get_m_n(struct intel_crtc *crtc,
		7163	struct intel_crtc_config *pipe_config)
		7164	{
		7165	if (crtc->config.has_pch_encoder)
		7166	intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
		7167	else
		7168	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
		7169	&pipe_config->dp_m_n);
		7170	}
		7171
		7172	static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
		7173	struct intel_crtc_config *pipe_config)
		7174	{
		7175	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
		7176	&pipe_config->fdi_m_n);
		7177	}
		7178
4104	Serge	7179	static void ironlake_get_pfit_config(struct intel_crtc *crtc,
		7180	struct intel_crtc_config *pipe_config)
		7181	{
		7182	struct drm_device *dev = crtc->base.dev;
		7183	struct drm_i915_private *dev_priv = dev->dev_private;
		7184	uint32_t tmp;
		7185
		7186	tmp = I915_READ(PF_CTL(crtc->pipe));
		7187
		7188	if (tmp & PF_ENABLE) {
		7189	pipe_config->pch_pfit.enabled = true;
		7190	pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
		7191	pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
		7192
		7193	/* We currently do not free assignements of panel fitters on
		7194	* ivb/hsw (since we don't use the higher upscaling modes which
		7195	* differentiates them) so just WARN about this case for now. */
		7196	if (IS_GEN7(dev)) {
		7197	WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
		7198	PF_PIPE_SEL_IVB(crtc->pipe));
		7199	}
		7200	}
		7201	}
		7202
5060	serge	7203	static void ironlake_get_plane_config(struct intel_crtc *crtc,
		7204	struct intel_plane_config *plane_config)
		7205	{
		7206	struct drm_device *dev = crtc->base.dev;
		7207	struct drm_i915_private *dev_priv = dev->dev_private;
		7208	u32 val, base, offset;
		7209	int pipe = crtc->pipe, plane = crtc->plane;
		7210	int fourcc, pixel_format;
		7211	int aligned_height;
		7212
		7213	crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
		7214	if (!crtc->base.primary->fb) {
		7215	DRM_DEBUG_KMS("failed to alloc fb\n");
		7216	return;
		7217	}
		7218
		7219	val = I915_READ(DSPCNTR(plane));
		7220
		7221	if (INTEL_INFO(dev)->gen >= 4)
		7222	if (val & DISPPLANE_TILED)
		7223	plane_config->tiled = true;
		7224
		7225	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
		7226	fourcc = intel_format_to_fourcc(pixel_format);
		7227	crtc->base.primary->fb->pixel_format = fourcc;
		7228	crtc->base.primary->fb->bits_per_pixel =
		7229	drm_format_plane_cpp(fourcc, 0) * 8;
		7230
		7231	base = I915_READ(DSPSURF(plane)) & 0xfffff000;
		7232	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
		7233	offset = I915_READ(DSPOFFSET(plane));
		7234	} else {
		7235	if (plane_config->tiled)
		7236	offset = I915_READ(DSPTILEOFF(plane));
		7237	else
		7238	offset = I915_READ(DSPLINOFF(plane));
		7239	}
		7240	plane_config->base = base;
		7241
		7242	val = I915_READ(PIPESRC(pipe));
		7243	crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
		7244	crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
		7245
		7246	val = I915_READ(DSPSTRIDE(pipe));
		7247	crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
		7248
		7249	aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
		7250	plane_config->tiled);
		7251
		7252	plane_config->size = 1610241024;
		7253
		7254	DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
		7255	pipe, plane, crtc->base.primary->fb->width,
		7256	crtc->base.primary->fb->height,
		7257	crtc->base.primary->fb->bits_per_pixel, base,
		7258	crtc->base.primary->fb->pitches[0],
		7259	plane_config->size);
		7260	}
		7261
3746	Serge	7262	static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
		7263	struct intel_crtc_config *pipe_config)
		7264	{
		7265	struct drm_device *dev = crtc->base.dev;
		7266	struct drm_i915_private *dev_priv = dev->dev_private;
		7267	uint32_t tmp;
		7268
5060	serge	7269	if (!intel_display_power_enabled(dev_priv,
		7270	POWER_DOMAIN_PIPE(crtc->pipe)))
		7271	return false;
		7272
4104	Serge	7273	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		7274	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		7275
3746	Serge	7276	tmp = I915_READ(PIPECONF(crtc->pipe));
		7277	if (!(tmp & PIPECONF_ENABLE))
		7278	return false;
		7279
4280	Serge	7280	switch (tmp & PIPECONF_BPC_MASK) {
		7281	case PIPECONF_6BPC:
		7282	pipe_config->pipe_bpp = 18;
		7283	break;
		7284	case PIPECONF_8BPC:
		7285	pipe_config->pipe_bpp = 24;
		7286	break;
		7287	case PIPECONF_10BPC:
		7288	pipe_config->pipe_bpp = 30;
		7289	break;
		7290	case PIPECONF_12BPC:
		7291	pipe_config->pipe_bpp = 36;
		7292	break;
		7293	default:
		7294	break;
		7295	}
		7296
5060	serge	7297	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
		7298	pipe_config->limited_color_range = true;
		7299
4104	Serge	7300	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
		7301	struct intel_shared_dpll *pll;
		7302
3746	Serge	7303	pipe_config->has_pch_encoder = true;
		7304
4104	Serge	7305	tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
		7306	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		7307	FDI_DP_PORT_WIDTH_SHIFT) + 1;
		7308
		7309	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		7310
		7311	if (HAS_PCH_IBX(dev_priv->dev)) {
		7312	pipe_config->shared_dpll =
		7313	(enum intel_dpll_id) crtc->pipe;
		7314	} else {
		7315	tmp = I915_READ(PCH_DPLL_SEL);
		7316	if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
		7317	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
		7318	else
		7319	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
		7320	}
		7321
		7322	pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
		7323
		7324	WARN_ON(!pll->get_hw_state(dev_priv, pll,
		7325	&pipe_config->dpll_hw_state));
		7326
		7327	tmp = pipe_config->dpll_hw_state.dpll;
		7328	pipe_config->pixel_multiplier =
		7329	((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
		7330	>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
4560	Serge	7331
		7332	ironlake_pch_clock_get(crtc, pipe_config);
4104	Serge	7333	} else {
		7334	pipe_config->pixel_multiplier = 1;
		7335	}
		7336
		7337	intel_get_pipe_timings(crtc, pipe_config);
		7338
		7339	ironlake_get_pfit_config(crtc, pipe_config);
		7340
3746	Serge	7341	return true;
		7342	}
		7343
4104	Serge	7344	static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
		7345	{
		7346	struct drm_device *dev = dev_priv->dev;
		7347	struct intel_crtc *crtc;
		7348
5060	serge	7349	for_each_intel_crtc(dev, crtc)
4539	Serge	7350	WARN(crtc->active, "CRTC for pipe %c enabled\n",
4104	Serge	7351	pipe_name(crtc->pipe));
		7352
		7353	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5060	serge	7354	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
		7355	WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
		7356	WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
4104	Serge	7357	WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
		7358	WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
		7359	"CPU PWM1 enabled\n");
5060	serge	7360	if (IS_HASWELL(dev))
4104	Serge	7361	WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
		7362	"CPU PWM2 enabled\n");
		7363	WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
		7364	"PCH PWM1 enabled\n");
		7365	WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
		7366	"Utility pin enabled\n");
		7367	WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
		7368
5060	serge	7369	/*
		7370	* In theory we can still leave IRQs enabled, as long as only the HPD
		7371	* interrupts remain enabled. We used to check for that, but since it's
		7372	* gen-specific and since we only disable LCPLL after we fully disable
		7373	* the interrupts, the check below should be enough.
		7374	*/
		7375	WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
4104	Serge	7376	}
		7377
5060	serge	7378	static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
		7379	{
		7380	struct drm_device *dev = dev_priv->dev;
		7381
		7382	if (IS_HASWELL(dev))
		7383	return I915_READ(D_COMP_HSW);
		7384	else
		7385	return I915_READ(D_COMP_BDW);
		7386	}
		7387
		7388	static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
		7389	{
		7390	struct drm_device *dev = dev_priv->dev;
		7391
		7392	if (IS_HASWELL(dev)) {
		7393	mutex_lock(&dev_priv->rps.hw_lock);
		7394	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
		7395	val))
		7396	DRM_ERROR("Failed to write to D_COMP\n");
		7397	mutex_unlock(&dev_priv->rps.hw_lock);
		7398	} else {
		7399	I915_WRITE(D_COMP_BDW, val);
		7400	POSTING_READ(D_COMP_BDW);
		7401	}
		7402	}
		7403
4104	Serge	7404	/*
		7405	* This function implements pieces of two sequences from BSpec:
		7406	* - Sequence for display software to disable LCPLL
		7407	* - Sequence for display software to allow package C8+
		7408	* The steps implemented here are just the steps that actually touch the LCPLL
		7409	* register. Callers should take care of disabling all the display engine
		7410	* functions, doing the mode unset, fixing interrupts, etc.
		7411	*/
4560	Serge	7412	static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
4104	Serge	7413	bool switch_to_fclk, bool allow_power_down)
		7414	{
		7415	uint32_t val;
		7416
		7417	assert_can_disable_lcpll(dev_priv);
		7418
		7419	val = I915_READ(LCPLL_CTL);
		7420
		7421	if (switch_to_fclk) {
		7422	val \|= LCPLL_CD_SOURCE_FCLK;
		7423	I915_WRITE(LCPLL_CTL, val);
		7424
		7425	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
		7426	LCPLL_CD_SOURCE_FCLK_DONE, 1))
		7427	DRM_ERROR("Switching to FCLK failed\n");
		7428
		7429	val = I915_READ(LCPLL_CTL);
		7430	}
		7431
		7432	val \|= LCPLL_PLL_DISABLE;
		7433	I915_WRITE(LCPLL_CTL, val);
		7434	POSTING_READ(LCPLL_CTL);
		7435
		7436	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
		7437	DRM_ERROR("LCPLL still locked\n");
		7438
5060	serge	7439	val = hsw_read_dcomp(dev_priv);
4104	Serge	7440	val \|= D_COMP_COMP_DISABLE;
5060	serge	7441	hsw_write_dcomp(dev_priv, val);
		7442	ndelay(100);
4104	Serge	7443
5060	serge	7444	if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
		7445	1))
4104	Serge	7446	DRM_ERROR("D_COMP RCOMP still in progress\n");
		7447
		7448	if (allow_power_down) {
		7449	val = I915_READ(LCPLL_CTL);
		7450	val \|= LCPLL_POWER_DOWN_ALLOW;
		7451	I915_WRITE(LCPLL_CTL, val);
		7452	POSTING_READ(LCPLL_CTL);
		7453	}
		7454	}
		7455
		7456	/*
		7457	* Fully restores LCPLL, disallowing power down and switching back to LCPLL
		7458	* source.
		7459	*/
4560	Serge	7460	static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
4104	Serge	7461	{
		7462	uint32_t val;
5060	serge	7463	unsigned long irqflags;
4104	Serge	7464
		7465	val = I915_READ(LCPLL_CTL);
		7466
		7467	if ((val & (LCPLL_PLL_LOCK \| LCPLL_PLL_DISABLE \| LCPLL_CD_SOURCE_FCLK \|
		7468	LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
		7469	return;
		7470
5060	serge	7471	/*
		7472	* Make sure we're not on PC8 state before disabling PC8, otherwise
		7473	* we'll hang the machine. To prevent PC8 state, just enable force_wake.
		7474	*
		7475	* The other problem is that hsw_restore_lcpll() is called as part of
		7476	* the runtime PM resume sequence, so we can't just call
		7477	* gen6_gt_force_wake_get() because that function calls
		7478	* intel_runtime_pm_get(), and we can't change the runtime PM refcount
		7479	* while we are on the resume sequence. So to solve this problem we have
		7480	* to call special forcewake code that doesn't touch runtime PM and
		7481	* doesn't enable the forcewake delayed work.
		7482	*/
		7483	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
		7484	if (dev_priv->uncore.forcewake_count++ == 0)
		7485	dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
		7486	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4104	Serge	7487
		7488	if (val & LCPLL_POWER_DOWN_ALLOW) {
		7489	val &= ~LCPLL_POWER_DOWN_ALLOW;
		7490	I915_WRITE(LCPLL_CTL, val);
		7491	POSTING_READ(LCPLL_CTL);
		7492	}
		7493
5060	serge	7494	val = hsw_read_dcomp(dev_priv);
4104	Serge	7495	val \|= D_COMP_COMP_FORCE;
		7496	val &= ~D_COMP_COMP_DISABLE;
5060	serge	7497	hsw_write_dcomp(dev_priv, val);
4104	Serge	7498
		7499	val = I915_READ(LCPLL_CTL);
		7500	val &= ~LCPLL_PLL_DISABLE;
		7501	I915_WRITE(LCPLL_CTL, val);
		7502
		7503	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
		7504	DRM_ERROR("LCPLL not locked yet\n");
		7505
		7506	if (val & LCPLL_CD_SOURCE_FCLK) {
		7507	val = I915_READ(LCPLL_CTL);
		7508	val &= ~LCPLL_CD_SOURCE_FCLK;
		7509	I915_WRITE(LCPLL_CTL, val);
		7510
		7511	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
		7512	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
		7513	DRM_ERROR("Switching back to LCPLL failed\n");
		7514	}
		7515
5060	serge	7516	/* See the big comment above. */
		7517	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
		7518	if (--dev_priv->uncore.forcewake_count == 0)
		7519	dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
		7520	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4104	Serge	7521	}
		7522
5060	serge	7523	/*
		7524	* Package states C8 and deeper are really deep PC states that can only be
		7525	* reached when all the devices on the system allow it, so even if the graphics
		7526	* device allows PC8+, it doesn't mean the system will actually get to these
		7527	* states. Our driver only allows PC8+ when going into runtime PM.
		7528	*
		7529	* The requirements for PC8+ are that all the outputs are disabled, the power
		7530	* well is disabled and most interrupts are disabled, and these are also
		7531	* requirements for runtime PM. When these conditions are met, we manually do
		7532	* the other conditions: disable the interrupts, clocks and switch LCPLL refclk
		7533	* to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
		7534	* hang the machine.
		7535	*
		7536	* When we really reach PC8 or deeper states (not just when we allow it) we lose
		7537	* the state of some registers, so when we come back from PC8+ we need to
		7538	* restore this state. We don't get into PC8+ if we're not in RC6, so we don't
		7539	* need to take care of the registers kept by RC6. Notice that this happens even
		7540	* if we don't put the device in PCI D3 state (which is what currently happens
		7541	* because of the runtime PM support).
		7542	*
		7543	* For more, read "Display Sequences for Package C8" on the hardware
		7544	* documentation.
		7545	*/
		7546	void hsw_enable_pc8(struct drm_i915_private *dev_priv)
4104	Serge	7547	{
		7548	struct drm_device *dev = dev_priv->dev;
		7549	uint32_t val;
		7550
		7551	DRM_DEBUG_KMS("Enabling package C8+\n");
		7552
		7553	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		7554	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		7555	val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
		7556	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		7557	}
		7558
		7559	lpt_disable_clkout_dp(dev);
		7560	hsw_disable_lcpll(dev_priv, true, true);
		7561	}
		7562
5060	serge	7563	void hsw_disable_pc8(struct drm_i915_private *dev_priv)
4104	Serge	7564	{
		7565	struct drm_device *dev = dev_priv->dev;
		7566	uint32_t val;
		7567
		7568	DRM_DEBUG_KMS("Disabling package C8+\n");
		7569
		7570	hsw_restore_lcpll(dev_priv);
		7571	lpt_init_pch_refclk(dev);
		7572
		7573	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		7574	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		7575	val \|= PCH_LP_PARTITION_LEVEL_DISABLE;
		7576	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		7577	}
		7578
		7579	intel_prepare_ddi(dev);
		7580	}
		7581
5060	serge	7582	static void snb_modeset_global_resources(struct drm_device *dev)
4104	Serge	7583	{
5060	serge	7584	modeset_update_crtc_power_domains(dev);
4104	Serge	7585	}
		7586
5060	serge	7587	static void haswell_modeset_global_resources(struct drm_device *dev)
4104	Serge	7588	{
5060	serge	7589	modeset_update_crtc_power_domains(dev);
4104	Serge	7590	}
		7591
5060	serge	7592	static int haswell_crtc_mode_set(struct drm_crtc *crtc,
		7593	int x, int y,
		7594	struct drm_framebuffer *fb)
4104	Serge	7595	{
5060	serge	7596	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	7597
5060	serge	7598	if (!intel_ddi_pll_select(intel_crtc))
		7599	return -EINVAL;
4104	Serge	7600
5060	serge	7601	intel_crtc->lowfreq_avail = false;
4104	Serge	7602
5060	serge	7603	return 0;
4104	Serge	7604	}
		7605
5060	serge	7606	static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
		7607	struct intel_crtc_config *pipe_config)
4104	Serge	7608	{
5060	serge	7609	struct drm_device *dev = crtc->base.dev;
4104	Serge	7610	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	7611	struct intel_shared_dpll *pll;
		7612	enum port port;
		7613	uint32_t tmp;
4104	Serge	7614
5060	serge	7615	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
4560	Serge	7616
5060	serge	7617	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
4104	Serge	7618
5060	serge	7619	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
4104	Serge	7620
5060	serge	7621	switch (pipe_config->ddi_pll_sel) {
		7622	case PORT_CLK_SEL_WRPLL1:
		7623	pipe_config->shared_dpll = DPLL_ID_WRPLL1;
		7624	break;
		7625	case PORT_CLK_SEL_WRPLL2:
		7626	pipe_config->shared_dpll = DPLL_ID_WRPLL2;
		7627	break;
4104	Serge	7628	}
		7629
5060	serge	7630	if (pipe_config->shared_dpll >= 0) {
		7631	pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
4560	Serge	7632
5060	serge	7633	WARN_ON(!pll->get_hw_state(dev_priv, pll,
		7634	&pipe_config->dpll_hw_state));
4104	Serge	7635	}
		7636
4560	Serge	7637	/*
5060	serge	7638	* Haswell has only FDI/PCH transcoder A. It is which is connected to
		7639	* DDI E. So just check whether this pipe is wired to DDI E and whether
		7640	* the PCH transcoder is on.
4560	Serge	7641	*/
5060	serge	7642	if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
		7643	pipe_config->has_pch_encoder = true;
4560	Serge	7644
5060	serge	7645	tmp = I915_READ(FDI_RX_CTL(PIPE_A));
		7646	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		7647	FDI_DP_PORT_WIDTH_SHIFT) + 1;
3480	Serge	7648
5060	serge	7649	ironlake_get_fdi_m_n_config(crtc, pipe_config);
3480	Serge	7650	}
4560	Serge	7651	}
		7652
3746	Serge	7653	static bool haswell_get_pipe_config(struct intel_crtc *crtc,
		7654	struct intel_crtc_config *pipe_config)
		7655	{
		7656	struct drm_device *dev = crtc->base.dev;
		7657	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	7658	enum intel_display_power_domain pfit_domain;
3746	Serge	7659	uint32_t tmp;
		7660
5060	serge	7661	if (!intel_display_power_enabled(dev_priv,
		7662	POWER_DOMAIN_PIPE(crtc->pipe)))
		7663	return false;
		7664
4104	Serge	7665	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		7666	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		7667
		7668	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
		7669	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		7670	enum pipe trans_edp_pipe;
		7671	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		7672	default:
		7673	WARN(1, "unknown pipe linked to edp transcoder\n");
		7674	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		7675	case TRANS_DDI_EDP_INPUT_A_ON:
		7676	trans_edp_pipe = PIPE_A;
		7677	break;
		7678	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		7679	trans_edp_pipe = PIPE_B;
		7680	break;
		7681	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		7682	trans_edp_pipe = PIPE_C;
		7683	break;
		7684	}
		7685
		7686	if (trans_edp_pipe == crtc->pipe)
		7687	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		7688	}
		7689
5060	serge	7690	if (!intel_display_power_enabled(dev_priv,
4104	Serge	7691	POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
		7692	return false;
		7693
		7694	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
3746	Serge	7695	if (!(tmp & PIPECONF_ENABLE))
		7696	return false;
		7697
5060	serge	7698	haswell_get_ddi_port_state(crtc, pipe_config);
3746	Serge	7699
4104	Serge	7700	intel_get_pipe_timings(crtc, pipe_config);
		7701
		7702	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5060	serge	7703	if (intel_display_power_enabled(dev_priv, pfit_domain))
4104	Serge	7704	ironlake_get_pfit_config(crtc, pipe_config);
		7705
4560	Serge	7706	if (IS_HASWELL(dev))
4104	Serge	7707	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
		7708	(I915_READ(IPS_CTL) & IPS_ENABLE);
		7709
		7710	pipe_config->pixel_multiplier = 1;
		7711
3746	Serge	7712	return true;
		7713	}
		7714
4560	Serge	7715	static struct {
		7716	int clock;
		7717	u32 config;
		7718	} hdmi_audio_clock[] = {
		7719	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
		7720	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
		7721	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
		7722	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
		7723	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
		7724	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
		7725	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
		7726	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
		7727	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
		7728	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
		7729	};
		7730
		7731	/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
		7732	static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
		7733	{
		7734	int i;
		7735
		7736	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
		7737	if (mode->clock == hdmi_audio_clock[i].clock)
		7738	break;
		7739	}
		7740
		7741	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
		7742	DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
		7743	i = 1;
		7744	}
		7745
		7746	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
		7747	hdmi_audio_clock[i].clock,
		7748	hdmi_audio_clock[i].config);
		7749
		7750	return hdmi_audio_clock[i].config;
		7751	}
		7752
2342	Serge	7753	static bool intel_eld_uptodate(struct drm_connector *connector,
		7754	int reg_eldv, uint32_t bits_eldv,
		7755	int reg_elda, uint32_t bits_elda,
		7756	int reg_edid)
		7757	{
		7758	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		7759	uint8_t *eld = connector->eld;
		7760	uint32_t i;
		7761
		7762	i = I915_READ(reg_eldv);
		7763	i &= bits_eldv;
		7764
		7765	if (!eld[0])
		7766	return !i;
		7767
		7768	if (!i)
		7769	return false;
		7770
		7771	i = I915_READ(reg_elda);
		7772	i &= ~bits_elda;
		7773	I915_WRITE(reg_elda, i);
		7774
		7775	for (i = 0; i < eld[2]; i++)
		7776	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
		7777	return false;
		7778
		7779	return true;
		7780	}
		7781
		7782	static void g4x_write_eld(struct drm_connector *connector,
4560	Serge	7783	struct drm_crtc *crtc,
		7784	struct drm_display_mode *mode)
2342	Serge	7785	{
		7786	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		7787	uint8_t *eld = connector->eld;
		7788	uint32_t eldv;
		7789	uint32_t len;
		7790	uint32_t i;
		7791
		7792	i = I915_READ(G4X_AUD_VID_DID);
		7793
		7794	if (i == INTEL_AUDIO_DEVBLC \|\| i == INTEL_AUDIO_DEVCL)
		7795	eldv = G4X_ELDV_DEVCL_DEVBLC;
		7796	else
		7797	eldv = G4X_ELDV_DEVCTG;
		7798
		7799	if (intel_eld_uptodate(connector,
		7800	G4X_AUD_CNTL_ST, eldv,
		7801	G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
		7802	G4X_HDMIW_HDMIEDID))
		7803	return;
		7804
		7805	i = I915_READ(G4X_AUD_CNTL_ST);
		7806	i &= ~(eldv \| G4X_ELD_ADDR);
		7807	len = (i >> 9) & 0x1f; /* ELD buffer size */
		7808	I915_WRITE(G4X_AUD_CNTL_ST, i);
		7809
		7810	if (!eld[0])
		7811	return;
		7812
		7813	len = min_t(uint8_t, eld[2], len);
		7814	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		7815	for (i = 0; i < len; i++)
		7816	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
		7817
		7818	i = I915_READ(G4X_AUD_CNTL_ST);
		7819	i \|= eldv;
		7820	I915_WRITE(G4X_AUD_CNTL_ST, i);
		7821	}
		7822
3031	serge	7823	static void haswell_write_eld(struct drm_connector *connector,
4560	Serge	7824	struct drm_crtc *crtc,
		7825	struct drm_display_mode *mode)
3031	serge	7826	{
		7827	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		7828	uint8_t *eld = connector->eld;
		7829	uint32_t eldv;
		7830	uint32_t i;
		7831	int len;
		7832	int pipe = to_intel_crtc(crtc)->pipe;
		7833	int tmp;
		7834
		7835	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
		7836	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
		7837	int aud_config = HSW_AUD_CFG(pipe);
		7838	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
		7839
		7840	/* Audio output enable */
		7841	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
		7842	tmp = I915_READ(aud_cntrl_st2);
		7843	tmp \|= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
		7844	I915_WRITE(aud_cntrl_st2, tmp);
5060	serge	7845	POSTING_READ(aud_cntrl_st2);
3031	serge	7846
5060	serge	7847	assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
3031	serge	7848
		7849	/* Set ELD valid state */
		7850	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	7851	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
3031	serge	7852	tmp \|= (AUDIO_ELD_VALID_A << (pipe * 4));
		7853	I915_WRITE(aud_cntrl_st2, tmp);
		7854	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	7855	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
3031	serge	7856
		7857	/* Enable HDMI mode */
		7858	tmp = I915_READ(aud_config);
4104	Serge	7859	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
3031	serge	7860	/* clear N_programing_enable and N_value_index */
		7861	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX \| AUD_CONFIG_N_PROG_ENABLE);
		7862	I915_WRITE(aud_config, tmp);
		7863
		7864	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
		7865
		7866	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
		7867
		7868	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		7869	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		7870	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
		7871	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4560	Serge	7872	} else {
		7873	I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
		7874	}
3031	serge	7875
		7876	if (intel_eld_uptodate(connector,
		7877	aud_cntrl_st2, eldv,
		7878	aud_cntl_st, IBX_ELD_ADDRESS,
		7879	hdmiw_hdmiedid))
		7880	return;
		7881
		7882	i = I915_READ(aud_cntrl_st2);
		7883	i &= ~eldv;
		7884	I915_WRITE(aud_cntrl_st2, i);
		7885
		7886	if (!eld[0])
		7887	return;
		7888
		7889	i = I915_READ(aud_cntl_st);
		7890	i &= ~IBX_ELD_ADDRESS;
		7891	I915_WRITE(aud_cntl_st, i);
		7892	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
		7893	DRM_DEBUG_DRIVER("port num:%d\n", i);
		7894
		7895	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		7896	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		7897	for (i = 0; i < len; i++)
		7898	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		7899
		7900	i = I915_READ(aud_cntrl_st2);
		7901	i \|= eldv;
		7902	I915_WRITE(aud_cntrl_st2, i);
		7903
		7904	}
		7905
2342	Serge	7906	static void ironlake_write_eld(struct drm_connector *connector,
4560	Serge	7907	struct drm_crtc *crtc,
		7908	struct drm_display_mode *mode)
2342	Serge	7909	{
		7910	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		7911	uint8_t *eld = connector->eld;
		7912	uint32_t eldv;
		7913	uint32_t i;
		7914	int len;
		7915	int hdmiw_hdmiedid;
3031	serge	7916	int aud_config;
2342	Serge	7917	int aud_cntl_st;
		7918	int aud_cntrl_st2;
3031	serge	7919	int pipe = to_intel_crtc(crtc)->pipe;
2342	Serge	7920
		7921	if (HAS_PCH_IBX(connector->dev)) {
3031	serge	7922	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		7923	aud_config = IBX_AUD_CFG(pipe);
		7924	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
2342	Serge	7925	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4560	Serge	7926	} else if (IS_VALLEYVIEW(connector->dev)) {
		7927	hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
		7928	aud_config = VLV_AUD_CFG(pipe);
		7929	aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
		7930	aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
2342	Serge	7931	} else {
3031	serge	7932	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		7933	aud_config = CPT_AUD_CFG(pipe);
		7934	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
2342	Serge	7935	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
		7936	}
		7937
3031	serge	7938	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
2342	Serge	7939
4560	Serge	7940	if (IS_VALLEYVIEW(connector->dev)) {
		7941	struct intel_encoder *intel_encoder;
		7942	struct intel_digital_port *intel_dig_port;
		7943
		7944	intel_encoder = intel_attached_encoder(connector);
		7945	intel_dig_port = enc_to_dig_port(&intel_encoder->base);
		7946	i = intel_dig_port->port;
		7947	} else {
2342	Serge	7948	i = I915_READ(aud_cntl_st);
4560	Serge	7949	i = (i >> 29) & DIP_PORT_SEL_MASK;
		7950	/* DIP_Port_Select, 0x1 = PortB */
		7951	}
		7952
2342	Serge	7953	if (!i) {
		7954	DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		7955	/* operate blindly on all ports */
		7956	eldv = IBX_ELD_VALIDB;
		7957	eldv \|= IBX_ELD_VALIDB << 4;
		7958	eldv \|= IBX_ELD_VALIDB << 8;
		7959	} else {
4104	Serge	7960	DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
2342	Serge	7961	eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
		7962	}
		7963
		7964	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		7965	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		7966	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
3031	serge	7967	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4560	Serge	7968	} else {
		7969	I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
		7970	}
2342	Serge	7971
		7972	if (intel_eld_uptodate(connector,
		7973	aud_cntrl_st2, eldv,
		7974	aud_cntl_st, IBX_ELD_ADDRESS,
		7975	hdmiw_hdmiedid))
		7976	return;
		7977
		7978	i = I915_READ(aud_cntrl_st2);
		7979	i &= ~eldv;
		7980	I915_WRITE(aud_cntrl_st2, i);
		7981
		7982	if (!eld[0])
		7983	return;
		7984
		7985	i = I915_READ(aud_cntl_st);
		7986	i &= ~IBX_ELD_ADDRESS;
		7987	I915_WRITE(aud_cntl_st, i);
		7988
		7989	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		7990	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		7991	for (i = 0; i < len; i++)
		7992	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		7993
		7994	i = I915_READ(aud_cntrl_st2);
		7995	i \|= eldv;
		7996	I915_WRITE(aud_cntrl_st2, i);
		7997	}
		7998
		7999	void intel_write_eld(struct drm_encoder *encoder,
		8000	struct drm_display_mode *mode)
		8001	{
		8002	struct drm_crtc *crtc = encoder->crtc;
		8003	struct drm_connector *connector;
		8004	struct drm_device *dev = encoder->dev;
		8005	struct drm_i915_private *dev_priv = dev->dev_private;
		8006
		8007	connector = drm_select_eld(encoder, mode);
		8008	if (!connector)
		8009	return;
		8010
		8011	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		8012	connector->base.id,
5060	serge	8013	connector->name,
2342	Serge	8014	connector->encoder->base.id,
5060	serge	8015	connector->encoder->name);
2342	Serge	8016
		8017	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
		8018
		8019	if (dev_priv->display.write_eld)
4560	Serge	8020	dev_priv->display.write_eld(connector, crtc, mode);
2342	Serge	8021	}
		8022
3031	serge	8023	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
		8024	{
		8025	struct drm_device *dev = crtc->dev;
		8026	struct drm_i915_private *dev_priv = dev->dev_private;
		8027	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	8028	uint32_t cntl;
2327	Serge	8029
5060	serge	8030	if (base != intel_crtc->cursor_base) {
3031	serge	8031	/* On these chipsets we can only modify the base whilst
		8032	* the cursor is disabled.
		8033	*/
5060	serge	8034	if (intel_crtc->cursor_cntl) {
		8035	I915_WRITE(_CURACNTR, 0);
		8036	POSTING_READ(_CURACNTR);
		8037	intel_crtc->cursor_cntl = 0;
		8038	}
		8039
3031	serge	8040	I915_WRITE(_CURABASE, base);
5060	serge	8041	POSTING_READ(_CURABASE);
		8042	}
2327	Serge	8043
3031	serge	8044	/* XXX width must be 64, stride 256 => 0x00 << 28 */
5060	serge	8045	cntl = 0;
		8046	if (base)
		8047	cntl = (CURSOR_ENABLE \|
3031	serge	8048	CURSOR_GAMMA_ENABLE \|
5060	serge	8049	CURSOR_FORMAT_ARGB);
		8050	if (intel_crtc->cursor_cntl != cntl) {
3031	serge	8051	I915_WRITE(_CURACNTR, cntl);
5060	serge	8052	POSTING_READ(_CURACNTR);
		8053	intel_crtc->cursor_cntl = cntl;
		8054	}
3031	serge	8055	}
2327	Serge	8056
3031	serge	8057	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
		8058	{
		8059	struct drm_device *dev = crtc->dev;
		8060	struct drm_i915_private *dev_priv = dev->dev_private;
		8061	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		8062	int pipe = intel_crtc->pipe;
5060	serge	8063	uint32_t cntl;
2327	Serge	8064
5060	serge	8065	cntl = 0;
3031	serge	8066	if (base) {
5060	serge	8067	cntl = MCURSOR_GAMMA_ENABLE;
		8068	switch (intel_crtc->cursor_width) {
		8069	case 64:
		8070	cntl \|= CURSOR_MODE_64_ARGB_AX;
		8071	break;
		8072	case 128:
		8073	cntl \|= CURSOR_MODE_128_ARGB_AX;
		8074	break;
		8075	case 256:
		8076	cntl \|= CURSOR_MODE_256_ARGB_AX;
		8077	break;
		8078	default:
		8079	WARN_ON(1);
		8080	return;
		8081	}
3031	serge	8082	cntl \|= pipe << 28; /* Connect to correct pipe */
		8083	}
5060	serge	8084	if (intel_crtc->cursor_cntl != cntl) {
3031	serge	8085	I915_WRITE(CURCNTR(pipe), cntl);
5060	serge	8086	POSTING_READ(CURCNTR(pipe));
		8087	intel_crtc->cursor_cntl = cntl;
		8088	}
2327	Serge	8089
3031	serge	8090	/* and commit changes on next vblank */
		8091	I915_WRITE(CURBASE(pipe), base);
4371	Serge	8092	POSTING_READ(CURBASE(pipe));
3031	serge	8093	}
2327	Serge	8094
3031	serge	8095	static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
		8096	{
		8097	struct drm_device *dev = crtc->dev;
		8098	struct drm_i915_private *dev_priv = dev->dev_private;
		8099	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		8100	int pipe = intel_crtc->pipe;
5060	serge	8101	uint32_t cntl;
2327	Serge	8102
5060	serge	8103	cntl = 0;
3031	serge	8104	if (base) {
5060	serge	8105	cntl = MCURSOR_GAMMA_ENABLE;
		8106	switch (intel_crtc->cursor_width) {
		8107	case 64:
		8108	cntl \|= CURSOR_MODE_64_ARGB_AX;
		8109	break;
		8110	case 128:
		8111	cntl \|= CURSOR_MODE_128_ARGB_AX;
		8112	break;
		8113	case 256:
		8114	cntl \|= CURSOR_MODE_256_ARGB_AX;
		8115	break;
		8116	default:
		8117	WARN_ON(1);
		8118	return;
		8119	}
3031	serge	8120	}
5060	serge	8121	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
3480	Serge	8122	cntl \|= CURSOR_PIPE_CSC_ENABLE;
5060	serge	8123
		8124	if (intel_crtc->cursor_cntl != cntl) {
		8125	I915_WRITE(CURCNTR(pipe), cntl);
		8126	POSTING_READ(CURCNTR(pipe));
		8127	intel_crtc->cursor_cntl = cntl;
4104	Serge	8128	}
2327	Serge	8129
3031	serge	8130	/* and commit changes on next vblank */
5060	serge	8131	I915_WRITE(CURBASE(pipe), base);
		8132	POSTING_READ(CURBASE(pipe));
3031	serge	8133	}
2327	Serge	8134
3031	serge	8135	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5060	serge	8136	void intel_crtc_update_cursor(struct drm_crtc *crtc,
3031	serge	8137	bool on)
		8138	{
		8139	struct drm_device *dev = crtc->dev;
		8140	struct drm_i915_private *dev_priv = dev->dev_private;
		8141	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		8142	int pipe = intel_crtc->pipe;
5060	serge	8143	int x = crtc->cursor_x;
		8144	int y = crtc->cursor_y;
4560	Serge	8145	u32 base = 0, pos = 0;
2327	Serge	8146
4560	Serge	8147	if (on)
		8148	base = intel_crtc->cursor_addr;
2327	Serge	8149
4560	Serge	8150	if (x >= intel_crtc->config.pipe_src_w)
3031	serge	8151	base = 0;
2327	Serge	8152
4560	Serge	8153	if (y >= intel_crtc->config.pipe_src_h)
3031	serge	8154	base = 0;
2327	Serge	8155
3031	serge	8156	if (x < 0) {
4560	Serge	8157	if (x + intel_crtc->cursor_width <= 0)
3031	serge	8158	base = 0;
2327	Serge	8159
3031	serge	8160	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		8161	x = -x;
		8162	}
		8163	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	8164
3031	serge	8165	if (y < 0) {
4560	Serge	8166	if (y + intel_crtc->cursor_height <= 0)
3031	serge	8167	base = 0;
2327	Serge	8168
3031	serge	8169	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		8170	y = -y;
		8171	}
		8172	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	8173
5060	serge	8174	if (base == 0 && intel_crtc->cursor_base == 0)
3031	serge	8175	return;
2327	Serge	8176
5060	serge	8177	I915_WRITE(CURPOS(pipe), pos);
		8178
		8179	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
3031	serge	8180	ivb_update_cursor(crtc, base);
5060	serge	8181	else if (IS_845G(dev) \|\| IS_I865G(dev))
		8182	i845_update_cursor(crtc, base);
		8183	else
4560	Serge	8184	i9xx_update_cursor(crtc, base);
5060	serge	8185	intel_crtc->cursor_base = base;
3031	serge	8186	}
2327	Serge	8187
5060	serge	8188	/*
		8189	* intel_crtc_cursor_set_obj - Set cursor to specified GEM object
		8190	*
		8191	* Note that the object's reference will be consumed if the update fails. If
		8192	* the update succeeds, the reference of the old object (if any) will be
		8193	* consumed.
		8194	*/
		8195	static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
		8196	struct drm_i915_gem_object *obj,
3031	serge	8197	uint32_t width, uint32_t height)
		8198	{
		8199	struct drm_device *dev = crtc->dev;
		8200	struct drm_i915_private *dev_priv = dev->dev_private;
		8201	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	8202	enum pipe pipe = intel_crtc->pipe;
		8203	unsigned old_width;
3031	serge	8204	uint32_t addr;
		8205	int ret;
2327	Serge	8206
3031	serge	8207	/* if we want to turn off the cursor ignore width and height */
5060	serge	8208	if (!obj) {
3031	serge	8209	DRM_DEBUG_KMS("cursor off\n");
		8210	addr = 0;
		8211	obj = NULL;
		8212	mutex_lock(&dev->struct_mutex);
		8213	goto finish;
		8214	}
2327	Serge	8215
5060	serge	8216	/* Check for which cursor types we support */
		8217	if (!((width == 64 && height == 64) \|\|
		8218	(width == 128 && height == 128 && !IS_GEN2(dev)) \|\|
		8219	(width == 256 && height == 256 && !IS_GEN2(dev)))) {
		8220	DRM_DEBUG("Cursor dimension not supported\n");
3031	serge	8221	return -EINVAL;
		8222	}
2327	Serge	8223
3031	serge	8224	if (obj->base.size < width * height * 4) {
5060	serge	8225	DRM_DEBUG_KMS("buffer is too small\n");
3031	serge	8226	ret = -ENOMEM;
		8227	goto fail;
		8228	}
2327	Serge	8229
3031	serge	8230	/* we only need to pin inside GTT if cursor is non-phy */
		8231	mutex_lock(&dev->struct_mutex);
5060	serge	8232	if (!INTEL_INFO(dev)->cursor_needs_physical) {
3746	Serge	8233	unsigned alignment;
		8234
3031	serge	8235	if (obj->tiling_mode) {
5060	serge	8236	DRM_DEBUG_KMS("cursor cannot be tiled\n");
3031	serge	8237	ret = -EINVAL;
		8238	goto fail_locked;
		8239	}
2327	Serge	8240
3746	Serge	8241	/* Note that the w/a also requires 2 PTE of padding following
		8242	* the bo. We currently fill all unused PTE with the shadow
		8243	* page and so we should always have valid PTE following the
		8244	* cursor preventing the VT-d warning.
		8245	*/
		8246	alignment = 0;
		8247	if (need_vtd_wa(dev))
		8248	alignment = 64*1024;
		8249
		8250	ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
3031	serge	8251	if (ret) {
5060	serge	8252	DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
3031	serge	8253	goto fail_locked;
		8254	}
2327	Serge	8255
3031	serge	8256	ret = i915_gem_object_put_fence(obj);
		8257	if (ret) {
5060	serge	8258	DRM_DEBUG_KMS("failed to release fence for cursor");
3031	serge	8259	goto fail_unpin;
		8260	}
2327	Serge	8261
4104	Serge	8262	addr = i915_gem_obj_ggtt_offset(obj);
3031	serge	8263	} else {
		8264	int align = IS_I830(dev) ? 16 * 1024 : 256;
5060	serge	8265	// ret = i915_gem_object_attach_phys(obj, align);
		8266	// if (ret) {
		8267	// DRM_DEBUG_KMS("failed to attach phys object\n");
		8268	// goto fail_locked;
		8269	// }
		8270	// addr = obj->phys_handle->busaddr;
3031	serge	8271	}
2327	Serge	8272
3031	serge	8273	if (IS_GEN2(dev))
		8274	I915_WRITE(CURSIZE, (height << 12) \| width);
2327	Serge	8275
3031	serge	8276	finish:
		8277	if (intel_crtc->cursor_bo) {
5060	serge	8278	if (!INTEL_INFO(dev)->cursor_needs_physical)
4104	Serge	8279	i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
3031	serge	8280	}
2327	Serge	8281
5060	serge	8282	i915_gem_track_fb(intel_crtc->cursor_bo, obj,
		8283	INTEL_FRONTBUFFER_CURSOR(pipe));
3031	serge	8284	mutex_unlock(&dev->struct_mutex);
2327	Serge	8285
5060	serge	8286	old_width = intel_crtc->cursor_width;
		8287
3031	serge	8288	intel_crtc->cursor_addr = addr;
		8289	intel_crtc->cursor_bo = obj;
		8290	intel_crtc->cursor_width = width;
		8291	intel_crtc->cursor_height = height;
2327	Serge	8292
5060	serge	8293	if (intel_crtc->active) {
		8294	if (old_width != width)
		8295	intel_update_watermarks(crtc);
4104	Serge	8296	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
5060	serge	8297	}
2327	Serge	8298
3031	serge	8299	return 0;
		8300	fail_unpin:
4104	Serge	8301	i915_gem_object_unpin_from_display_plane(obj);
3031	serge	8302	fail_locked:
		8303	mutex_unlock(&dev->struct_mutex);
		8304	fail:
		8305	drm_gem_object_unreference_unlocked(&obj->base);
		8306	return ret;
		8307	}
2327	Serge	8308
2330	Serge	8309	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		8310	u16 *blue, uint32_t start, uint32_t size)
		8311	{
		8312	int end = (start + size > 256) ? 256 : start + size, i;
		8313	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	8314
2330	Serge	8315	for (i = start; i < end; i++) {
		8316	intel_crtc->lut_r[i] = red[i] >> 8;
		8317	intel_crtc->lut_g[i] = green[i] >> 8;
		8318	intel_crtc->lut_b[i] = blue[i] >> 8;
		8319	}
2327	Serge	8320
2330	Serge	8321	intel_crtc_load_lut(crtc);
		8322	}
2327	Serge	8323
2330	Serge	8324	/* VESA 640x480x72Hz mode to set on the pipe */
		8325	static struct drm_display_mode load_detect_mode = {
		8326	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		8327	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		8328	};
2327	Serge	8329
4560	Serge	8330	struct drm_framebuffer *
5060	serge	8331	__intel_framebuffer_create(struct drm_device *dev,
3031	serge	8332	struct drm_mode_fb_cmd2 *mode_cmd,
		8333	struct drm_i915_gem_object *obj)
		8334	{
		8335	struct intel_framebuffer *intel_fb;
		8336	int ret;
2327	Serge	8337
3031	serge	8338	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		8339	if (!intel_fb) {
		8340	drm_gem_object_unreference_unlocked(&obj->base);
		8341	return ERR_PTR(-ENOMEM);
		8342	}
2327	Serge	8343
3031	serge	8344	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
4560	Serge	8345	if (ret)
		8346	goto err;
		8347
		8348	return &intel_fb->base;
		8349	err:
3031	serge	8350	drm_gem_object_unreference_unlocked(&obj->base);
		8351	kfree(intel_fb);
4560	Serge	8352
3031	serge	8353	return ERR_PTR(ret);
		8354	}
2327	Serge	8355
5060	serge	8356	static struct drm_framebuffer *
		8357	intel_framebuffer_create(struct drm_device *dev,
		8358	struct drm_mode_fb_cmd2 *mode_cmd,
		8359	struct drm_i915_gem_object *obj)
		8360	{
		8361	struct drm_framebuffer *fb;
		8362	int ret;
		8363
		8364	ret = i915_mutex_lock_interruptible(dev);
		8365	if (ret)
		8366	return ERR_PTR(ret);
		8367	fb = __intel_framebuffer_create(dev, mode_cmd, obj);
		8368	mutex_unlock(&dev->struct_mutex);
		8369
		8370	return fb;
		8371	}
		8372
2330	Serge	8373	static u32
		8374	intel_framebuffer_pitch_for_width(int width, int bpp)
		8375	{
		8376	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		8377	return ALIGN(pitch, 64);
		8378	}
2327	Serge	8379
2330	Serge	8380	static u32
		8381	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		8382	{
		8383	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5060	serge	8384	return PAGE_ALIGN(pitch * mode->vdisplay);
2330	Serge	8385	}
2327	Serge	8386
2330	Serge	8387	static struct drm_framebuffer *
		8388	intel_framebuffer_create_for_mode(struct drm_device *dev,
		8389	struct drm_display_mode *mode,
		8390	int depth, int bpp)
		8391	{
		8392	struct drm_i915_gem_object *obj;
3243	Serge	8393	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327	Serge	8394
5060	serge	8395	obj = i915_gem_alloc_object(dev,
		8396	intel_framebuffer_size_for_mode(mode, bpp));
		8397	if (obj == NULL)
		8398	return ERR_PTR(-ENOMEM);
		8399
		8400	mode_cmd.width = mode->hdisplay;
		8401	mode_cmd.height = mode->vdisplay;
		8402	mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
		8403	bpp);
		8404	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
		8405
		8406	return intel_framebuffer_create(dev, &mode_cmd, obj);
2330	Serge	8407	}
2327	Serge	8408
2330	Serge	8409	static struct drm_framebuffer *
		8410	mode_fits_in_fbdev(struct drm_device *dev,
		8411	struct drm_display_mode *mode)
		8412	{
4560	Serge	8413	#ifdef CONFIG_DRM_I915_FBDEV
2330	Serge	8414	struct drm_i915_private *dev_priv = dev->dev_private;
		8415	struct drm_i915_gem_object *obj;
		8416	struct drm_framebuffer *fb;
2327	Serge	8417
5060	serge	8418	if (!dev_priv->fbdev)
4280	Serge	8419	return NULL;
2327	Serge	8420
5060	serge	8421	if (!dev_priv->fbdev->fb)
2330	Serge	8422	return NULL;
2327	Serge	8423
5060	serge	8424	obj = dev_priv->fbdev->fb->obj;
		8425	BUG_ON(!obj);
		8426
		8427	fb = &dev_priv->fbdev->fb->base;
3031	serge	8428	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		8429	fb->bits_per_pixel))
4280	Serge	8430	return NULL;
2327	Serge	8431
3031	serge	8432	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		8433	return NULL;
		8434
4280	Serge	8435	return fb;
4560	Serge	8436	#else
		8437	return NULL;
		8438	#endif
2330	Serge	8439	}
2327	Serge	8440
3031	serge	8441	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	8442	struct drm_display_mode *mode,
5060	serge	8443	struct intel_load_detect_pipe *old,
		8444	struct drm_modeset_acquire_ctx *ctx)
2330	Serge	8445	{
		8446	struct intel_crtc *intel_crtc;
3031	serge	8447	struct intel_encoder *intel_encoder =
		8448	intel_attached_encoder(connector);
2330	Serge	8449	struct drm_crtc *possible_crtc;
		8450	struct drm_encoder *encoder = &intel_encoder->base;
		8451	struct drm_crtc *crtc = NULL;
		8452	struct drm_device *dev = encoder->dev;
3031	serge	8453	struct drm_framebuffer *fb;
5060	serge	8454	struct drm_mode_config *config = &dev->mode_config;
		8455	int ret, i = -1;
2327	Serge	8456
2330	Serge	8457	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5060	serge	8458	connector->base.id, connector->name,
		8459	encoder->base.id, encoder->name);
2327	Serge	8460
5060	serge	8461	retry:
		8462	ret = drm_modeset_lock(&config->connection_mutex, ctx);
		8463	if (ret)
		8464	goto fail_unlock;
		8465
2330	Serge	8466	/*
		8467	* Algorithm gets a little messy:
		8468	*
		8469	* - if the connector already has an assigned crtc, use it (but make
		8470	* sure it's on first)
		8471	*
		8472	* - try to find the first unused crtc that can drive this connector,
		8473	* and use that if we find one
		8474	*/
2327	Serge	8475
2330	Serge	8476	/* See if we already have a CRTC for this connector */
		8477	if (encoder->crtc) {
		8478	crtc = encoder->crtc;
2327	Serge	8479
5060	serge	8480	ret = drm_modeset_lock(&crtc->mutex, ctx);
		8481	if (ret)
		8482	goto fail_unlock;
3480	Serge	8483
3031	serge	8484	old->dpms_mode = connector->dpms;
2330	Serge	8485	old->load_detect_temp = false;
2327	Serge	8486
2330	Serge	8487	/* Make sure the crtc and connector are running */
3031	serge	8488	if (connector->dpms != DRM_MODE_DPMS_ON)
		8489	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	8490
2330	Serge	8491	return true;
		8492	}
2327	Serge	8493
2330	Serge	8494	/* Find an unused one (if possible) */
5060	serge	8495	for_each_crtc(dev, possible_crtc) {
2330	Serge	8496	i++;
		8497	if (!(encoder->possible_crtcs & (1 << i)))
		8498	continue;
5060	serge	8499	if (possible_crtc->enabled)
		8500	continue;
		8501	/* This can occur when applying the pipe A quirk on resume. */
		8502	if (to_intel_crtc(possible_crtc)->new_enabled)
		8503	continue;
		8504
2330	Serge	8505	crtc = possible_crtc;
		8506	break;
		8507	}
2327	Serge	8508
2330	Serge	8509	/*
		8510	* If we didn't find an unused CRTC, don't use any.
		8511	*/
		8512	if (!crtc) {
		8513	DRM_DEBUG_KMS("no pipe available for load-detect\n");
5060	serge	8514	goto fail_unlock;
2330	Serge	8515	}
2327	Serge	8516
5060	serge	8517	ret = drm_modeset_lock(&crtc->mutex, ctx);
		8518	if (ret)
		8519	goto fail_unlock;
3031	serge	8520	intel_encoder->new_crtc = to_intel_crtc(crtc);
		8521	to_intel_connector(connector)->new_encoder = intel_encoder;
2327	Serge	8522
2330	Serge	8523	intel_crtc = to_intel_crtc(crtc);
5060	serge	8524	intel_crtc->new_enabled = true;
		8525	intel_crtc->new_config = &intel_crtc->config;
3031	serge	8526	old->dpms_mode = connector->dpms;
2330	Serge	8527	old->load_detect_temp = true;
		8528	old->release_fb = NULL;
2327	Serge	8529
2330	Serge	8530	if (!mode)
		8531	mode = &load_detect_mode;
2327	Serge	8532
2330	Serge	8533	/* We need a framebuffer large enough to accommodate all accesses
		8534	* that the plane may generate whilst we perform load detection.
		8535	* We can not rely on the fbcon either being present (we get called
		8536	* during its initialisation to detect all boot displays, or it may
		8537	* not even exist) or that it is large enough to satisfy the
		8538	* requested mode.
		8539	*/
3031	serge	8540	fb = mode_fits_in_fbdev(dev, mode);
		8541	if (fb == NULL) {
2330	Serge	8542	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	8543	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		8544	old->release_fb = fb;
2330	Serge	8545	} else
		8546	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	8547	if (IS_ERR(fb)) {
2330	Serge	8548	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5060	serge	8549	goto fail;
2330	Serge	8550	}
2327	Serge	8551
3480	Serge	8552	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
2330	Serge	8553	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		8554	if (old->release_fb)
		8555	old->release_fb->funcs->destroy(old->release_fb);
5060	serge	8556	goto fail;
2330	Serge	8557	}
2327	Serge	8558
2330	Serge	8559	/* let the connector get through one full cycle before testing */
		8560	intel_wait_for_vblank(dev, intel_crtc->pipe);
		8561	return true;
5060	serge	8562
		8563	fail:
		8564	intel_crtc->new_enabled = crtc->enabled;
		8565	if (intel_crtc->new_enabled)
		8566	intel_crtc->new_config = &intel_crtc->config;
		8567	else
		8568	intel_crtc->new_config = NULL;
		8569	fail_unlock:
		8570	if (ret == -EDEADLK) {
		8571	drm_modeset_backoff(ctx);
		8572	goto retry;
		8573	}
		8574
		8575	return false;
2330	Serge	8576	}
2327	Serge	8577
3031	serge	8578	void intel_release_load_detect_pipe(struct drm_connector *connector,
2330	Serge	8579	struct intel_load_detect_pipe *old)
		8580	{
3031	serge	8581	struct intel_encoder *intel_encoder =
		8582	intel_attached_encoder(connector);
2330	Serge	8583	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	8584	struct drm_crtc *crtc = encoder->crtc;
5060	serge	8585	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	8586
2330	Serge	8587	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5060	serge	8588	connector->base.id, connector->name,
		8589	encoder->base.id, encoder->name);
2327	Serge	8590
2330	Serge	8591	if (old->load_detect_temp) {
3031	serge	8592	to_intel_connector(connector)->new_encoder = NULL;
		8593	intel_encoder->new_crtc = NULL;
5060	serge	8594	intel_crtc->new_enabled = false;
		8595	intel_crtc->new_config = NULL;
3031	serge	8596	intel_set_mode(crtc, NULL, 0, 0, NULL);
		8597
3480	Serge	8598	if (old->release_fb) {
		8599	drm_framebuffer_unregister_private(old->release_fb);
		8600	drm_framebuffer_unreference(old->release_fb);
		8601	}
2327	Serge	8602
2330	Serge	8603	return;
		8604	}
2327	Serge	8605
2330	Serge	8606	/* Switch crtc and encoder back off if necessary */
3031	serge	8607	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		8608	connector->funcs->dpms(connector, old->dpms_mode);
2330	Serge	8609	}
2327	Serge	8610
4560	Serge	8611	static int i9xx_pll_refclk(struct drm_device *dev,
		8612	const struct intel_crtc_config *pipe_config)
		8613	{
		8614	struct drm_i915_private *dev_priv = dev->dev_private;
		8615	u32 dpll = pipe_config->dpll_hw_state.dpll;
		8616
		8617	if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
		8618	return dev_priv->vbt.lvds_ssc_freq;
		8619	else if (HAS_PCH_SPLIT(dev))
		8620	return 120000;
		8621	else if (!IS_GEN2(dev))
		8622	return 96000;
		8623	else
		8624	return 48000;
		8625	}
		8626
2330	Serge	8627	/* Returns the clock of the currently programmed mode of the given pipe. */
4104	Serge	8628	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		8629	struct intel_crtc_config *pipe_config)
2330	Serge	8630	{
4104	Serge	8631	struct drm_device *dev = crtc->base.dev;
2330	Serge	8632	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	8633	int pipe = pipe_config->cpu_transcoder;
4560	Serge	8634	u32 dpll = pipe_config->dpll_hw_state.dpll;
2330	Serge	8635	u32 fp;
		8636	intel_clock_t clock;
4560	Serge	8637	int refclk = i9xx_pll_refclk(dev, pipe_config);
2327	Serge	8638
2330	Serge	8639	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4560	Serge	8640	fp = pipe_config->dpll_hw_state.fp0;
2330	Serge	8641	else
4560	Serge	8642	fp = pipe_config->dpll_hw_state.fp1;
2327	Serge	8643
2330	Serge	8644	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		8645	if (IS_PINEVIEW(dev)) {
		8646	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		8647	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		8648	} else {
		8649	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		8650	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		8651	}
2327	Serge	8652
2330	Serge	8653	if (!IS_GEN2(dev)) {
		8654	if (IS_PINEVIEW(dev))
		8655	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		8656	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		8657	else
		8658	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		8659	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	8660
2330	Serge	8661	switch (dpll & DPLL_MODE_MASK) {
		8662	case DPLLB_MODE_DAC_SERIAL:
		8663	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		8664	5 : 10;
		8665	break;
		8666	case DPLLB_MODE_LVDS:
		8667	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		8668	7 : 14;
		8669	break;
		8670	default:
		8671	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		8672	"mode\n", (int)(dpll & DPLL_MODE_MASK));
4104	Serge	8673	return;
2330	Serge	8674	}
2327	Serge	8675
4104	Serge	8676	if (IS_PINEVIEW(dev))
4560	Serge	8677	pineview_clock(refclk, &clock);
4104	Serge	8678	else
4560	Serge	8679	i9xx_clock(refclk, &clock);
2330	Serge	8680	} else {
4560	Serge	8681	u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
		8682	bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
2327	Serge	8683
2330	Serge	8684	if (is_lvds) {
		8685	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		8686	DPLL_FPA01_P1_POST_DIV_SHIFT);
4560	Serge	8687
		8688	if (lvds & LVDS_CLKB_POWER_UP)
		8689	clock.p2 = 7;
		8690	else
2330	Serge	8691	clock.p2 = 14;
		8692	} else {
		8693	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		8694	clock.p1 = 2;
		8695	else {
		8696	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		8697	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		8698	}
		8699	if (dpll & PLL_P2_DIVIDE_BY_4)
		8700	clock.p2 = 4;
		8701	else
		8702	clock.p2 = 2;
4560	Serge	8703	}
2327	Serge	8704
4560	Serge	8705	i9xx_clock(refclk, &clock);
2330	Serge	8706	}
2327	Serge	8707
4560	Serge	8708	/*
		8709	* This value includes pixel_multiplier. We will use
		8710	* port_clock to compute adjusted_mode.crtc_clock in the
		8711	* encoder's get_config() function.
		8712	*/
		8713	pipe_config->port_clock = clock.dot;
4104	Serge	8714	}
		8715
4560	Serge	8716	int intel_dotclock_calculate(int link_freq,
		8717	const struct intel_link_m_n *m_n)
4104	Serge	8718	{
		8719	/*
		8720	* The calculation for the data clock is:
4560	Serge	8721	* pixel_clock = ((m/n)(link_clock nr_lanes))/bpp
4104	Serge	8722	* But we want to avoid losing precison if possible, so:
4560	Serge	8723	* pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4104	Serge	8724	*
		8725	* and the link clock is simpler:
4560	Serge	8726	* link_clock = (m * link_clock) / n
2330	Serge	8727	*/
2327	Serge	8728
4560	Serge	8729	if (!m_n->link_n)
		8730	return 0;
4104	Serge	8731
4560	Serge	8732	return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
		8733	}
4104	Serge	8734
4560	Serge	8735	static void ironlake_pch_clock_get(struct intel_crtc *crtc,
		8736	struct intel_crtc_config *pipe_config)
		8737	{
		8738	struct drm_device *dev = crtc->base.dev;
4104	Serge	8739
4560	Serge	8740	/* read out port_clock from the DPLL */
		8741	i9xx_crtc_clock_get(crtc, pipe_config);
4104	Serge	8742
4560	Serge	8743	/*
		8744	* This value does not include pixel_multiplier.
		8745	* We will check that port_clock and adjusted_mode.crtc_clock
		8746	* agree once we know their relationship in the encoder's
		8747	* get_config() function.
		8748	*/
		8749	pipe_config->adjusted_mode.crtc_clock =
		8750	intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
		8751	&pipe_config->fdi_m_n);
2330	Serge	8752	}
2327	Serge	8753
2330	Serge	8754	/** Returns the currently programmed mode of the given pipe. */
		8755	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		8756	struct drm_crtc *crtc)
		8757	{
		8758	struct drm_i915_private *dev_priv = dev->dev_private;
		8759	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	8760	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
2330	Serge	8761	struct drm_display_mode *mode;
4104	Serge	8762	struct intel_crtc_config pipe_config;
3243	Serge	8763	int htot = I915_READ(HTOTAL(cpu_transcoder));
		8764	int hsync = I915_READ(HSYNC(cpu_transcoder));
		8765	int vtot = I915_READ(VTOTAL(cpu_transcoder));
		8766	int vsync = I915_READ(VSYNC(cpu_transcoder));
4560	Serge	8767	enum pipe pipe = intel_crtc->pipe;
2327	Serge	8768
2330	Serge	8769	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		8770	if (!mode)
		8771	return NULL;
		8772
4104	Serge	8773	/*
		8774	* Construct a pipe_config sufficient for getting the clock info
		8775	* back out of crtc_clock_get.
		8776	*
		8777	* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
		8778	* to use a real value here instead.
		8779	*/
4560	Serge	8780	pipe_config.cpu_transcoder = (enum transcoder) pipe;
4104	Serge	8781	pipe_config.pixel_multiplier = 1;
4560	Serge	8782	pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
		8783	pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
		8784	pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
4104	Serge	8785	i9xx_crtc_clock_get(intel_crtc, &pipe_config);
		8786
4560	Serge	8787	mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
2330	Serge	8788	mode->hdisplay = (htot & 0xffff) + 1;
		8789	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		8790	mode->hsync_start = (hsync & 0xffff) + 1;
		8791	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		8792	mode->vdisplay = (vtot & 0xffff) + 1;
		8793	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		8794	mode->vsync_start = (vsync & 0xffff) + 1;
		8795	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		8796
		8797	drm_mode_set_name(mode);
		8798
		8799	return mode;
		8800	}
		8801
5060	serge	8802	static void intel_increase_pllclock(struct drm_device *dev,
		8803	enum pipe pipe)
2327	Serge	8804	{
5060	serge	8805	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	8806	int dpll_reg = DPLL(pipe);
		8807	int dpll;
		8808
5060	serge	8809	if (!HAS_GMCH_DISPLAY(dev))
2327	Serge	8810	return;
		8811
		8812	if (!dev_priv->lvds_downclock_avail)
		8813	return;
		8814
		8815	dpll = I915_READ(dpll_reg);
		8816	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		8817	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		8818
3031	serge	8819	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	8820
		8821	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		8822	I915_WRITE(dpll_reg, dpll);
		8823	intel_wait_for_vblank(dev, pipe);
		8824
		8825	dpll = I915_READ(dpll_reg);
		8826	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		8827	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		8828	}
		8829	}
		8830
3031	serge	8831	static void intel_decrease_pllclock(struct drm_crtc *crtc)
		8832	{
		8833	struct drm_device *dev = crtc->dev;
5060	serge	8834	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8835	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	8836
5060	serge	8837	if (!HAS_GMCH_DISPLAY(dev))
3031	serge	8838	return;
2327	Serge	8839
3031	serge	8840	if (!dev_priv->lvds_downclock_avail)
		8841	return;
2327	Serge	8842
3031	serge	8843	/*
		8844	* Since this is called by a timer, we should never get here in
		8845	* the manual case.
		8846	*/
		8847	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		8848	int pipe = intel_crtc->pipe;
		8849	int dpll_reg = DPLL(pipe);
		8850	int dpll;
2327	Serge	8851
3031	serge	8852	DRM_DEBUG_DRIVER("downclocking LVDS\n");
2327	Serge	8853
3031	serge	8854	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	8855
3031	serge	8856	dpll = I915_READ(dpll_reg);
		8857	dpll \|= DISPLAY_RATE_SELECT_FPA1;
		8858	I915_WRITE(dpll_reg, dpll);
		8859	intel_wait_for_vblank(dev, pipe);
		8860	dpll = I915_READ(dpll_reg);
		8861	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
		8862	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
		8863	}
2327	Serge	8864
3031	serge	8865	}
2327	Serge	8866
3031	serge	8867	void intel_mark_busy(struct drm_device *dev)
		8868	{
4104	Serge	8869	struct drm_i915_private *dev_priv = dev->dev_private;
		8870
5060	serge	8871	if (dev_priv->mm.busy)
		8872	return;
		8873
		8874	intel_runtime_pm_get(dev_priv);
4104	Serge	8875	i915_update_gfx_val(dev_priv);
5060	serge	8876	dev_priv->mm.busy = true;
3031	serge	8877	}
2327	Serge	8878
3031	serge	8879	void intel_mark_idle(struct drm_device *dev)
		8880	{
4104	Serge	8881	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8882	struct drm_crtc *crtc;
2327	Serge	8883
5060	serge	8884	if (!dev_priv->mm.busy)
3031	serge	8885	return;
2327	Serge	8886
5060	serge	8887	dev_priv->mm.busy = false;
		8888
		8889	if (!i915.powersave)
		8890	goto out;
		8891
		8892	for_each_crtc(dev, crtc) {
		8893	if (!crtc->primary->fb)
3031	serge	8894	continue;
2327	Serge	8895
3480	Serge	8896	intel_decrease_pllclock(crtc);
3031	serge	8897	}
4560	Serge	8898
5060	serge	8899	if (INTEL_INFO(dev)->gen >= 6)
4560	Serge	8900	gen6_rps_idle(dev->dev_private);
5060	serge	8901
		8902	out:
		8903	intel_runtime_pm_put(dev_priv);
3031	serge	8904	}
2327	Serge	8905
5060	serge	8906
		8907	/**
		8908	* intel_mark_fb_busy - mark given planes as busy
		8909	* @dev: DRM device
		8910	* @frontbuffer_bits: bits for the affected planes
		8911	* @ring: optional ring for asynchronous commands
		8912	*
		8913	* This function gets called every time the screen contents change. It can be
		8914	* used to keep e.g. the update rate at the nominal refresh rate with DRRS.
		8915	*/
		8916	static void intel_mark_fb_busy(struct drm_device *dev,
		8917	unsigned frontbuffer_bits,
		8918	struct intel_engine_cs *ring)
3031	serge	8919	{
5060	serge	8920	enum pipe pipe;
2327	Serge	8921
5060	serge	8922	if (!i915.powersave)
3031	serge	8923	return;
2327	Serge	8924
5060	serge	8925	for_each_pipe(pipe) {
		8926	if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
3031	serge	8927	continue;
2327	Serge	8928
5060	serge	8929	intel_increase_pllclock(dev, pipe);
4104	Serge	8930	if (ring && intel_fbc_enabled(dev))
		8931	ring->fbc_dirty = true;
3031	serge	8932	}
		8933	}
2327	Serge	8934
5060	serge	8935	/**
		8936	* intel_fb_obj_invalidate - invalidate frontbuffer object
		8937	* @obj: GEM object to invalidate
		8938	* @ring: set for asynchronous rendering
		8939	*
		8940	* This function gets called every time rendering on the given object starts and
		8941	* frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
		8942	* be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
		8943	* until the rendering completes or a flip on this frontbuffer plane is
		8944	* scheduled.
		8945	*/
		8946	void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
		8947	struct intel_engine_cs *ring)
		8948	{
		8949	struct drm_device *dev = obj->base.dev;
		8950	struct drm_i915_private *dev_priv = dev->dev_private;
		8951
		8952	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
		8953
		8954	if (!obj->frontbuffer_bits)
		8955	return;
		8956
		8957	if (ring) {
		8958	mutex_lock(&dev_priv->fb_tracking.lock);
		8959	dev_priv->fb_tracking.busy_bits
		8960	\|= obj->frontbuffer_bits;
		8961	dev_priv->fb_tracking.flip_bits
		8962	&= ~obj->frontbuffer_bits;
		8963	mutex_unlock(&dev_priv->fb_tracking.lock);
		8964	}
		8965
		8966	intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
		8967
		8968	intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
		8969	}
		8970
		8971	/**
		8972	* intel_frontbuffer_flush - flush frontbuffer
		8973	* @dev: DRM device
		8974	* @frontbuffer_bits: frontbuffer plane tracking bits
		8975	*
		8976	* This function gets called every time rendering on the given planes has
		8977	* completed and frontbuffer caching can be started again. Flushes will get
		8978	* delayed if they're blocked by some oustanding asynchronous rendering.
		8979	*
		8980	* Can be called without any locks held.
		8981	*/
		8982	void intel_frontbuffer_flush(struct drm_device *dev,
		8983	unsigned frontbuffer_bits)
		8984	{
		8985	struct drm_i915_private *dev_priv = dev->dev_private;
		8986
		8987	/* Delay flushing when rings are still busy.*/
		8988	mutex_lock(&dev_priv->fb_tracking.lock);
		8989	frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
		8990	mutex_unlock(&dev_priv->fb_tracking.lock);
		8991
		8992	intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
		8993
		8994	intel_edp_psr_flush(dev, frontbuffer_bits);
		8995	}
2330	Serge	8996	static void intel_crtc_destroy(struct drm_crtc *crtc)
		8997	{
		8998	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		8999	struct drm_device *dev = crtc->dev;
		9000	struct intel_unpin_work *work;
		9001	unsigned long flags;
2327	Serge	9002
2330	Serge	9003	spin_lock_irqsave(&dev->event_lock, flags);
		9004	work = intel_crtc->unpin_work;
		9005	intel_crtc->unpin_work = NULL;
		9006	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	9007
2330	Serge	9008	if (work) {
4293	Serge	9009	cancel_work_sync(&work->work);
2330	Serge	9010	kfree(work);
		9011	}
2327	Serge	9012
2330	Serge	9013	drm_crtc_cleanup(crtc);
2327	Serge	9014
2330	Serge	9015	kfree(intel_crtc);
		9016	}
2327	Serge	9017
3031	serge	9018	#if 0
		9019	static void intel_unpin_work_fn(struct work_struct *__work)
		9020	{
		9021	struct intel_unpin_work *work =
		9022	container_of(__work, struct intel_unpin_work, work);
3243	Serge	9023	struct drm_device *dev = work->crtc->dev;
5060	serge	9024	enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
2327	Serge	9025
3243	Serge	9026	mutex_lock(&dev->struct_mutex);
3031	serge	9027	intel_unpin_fb_obj(work->old_fb_obj);
		9028	drm_gem_object_unreference(&work->pending_flip_obj->base);
		9029	drm_gem_object_unreference(&work->old_fb_obj->base);
2327	Serge	9030
3243	Serge	9031	intel_update_fbc(dev);
		9032	mutex_unlock(&dev->struct_mutex);
		9033
		9034	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
		9035	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
		9036
3031	serge	9037	kfree(work);
		9038	}
2327	Serge	9039
3031	serge	9040	static void do_intel_finish_page_flip(struct drm_device *dev,
		9041	struct drm_crtc *crtc)
		9042	{
5060	serge	9043	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9044	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		9045	struct intel_unpin_work *work;
		9046	unsigned long flags;
2327	Serge	9047
3031	serge	9048	/* Ignore early vblank irqs */
		9049	if (intel_crtc == NULL)
		9050	return;
2327	Serge	9051
3031	serge	9052	spin_lock_irqsave(&dev->event_lock, flags);
		9053	work = intel_crtc->unpin_work;
3243	Serge	9054
		9055	/* Ensure we don't miss a work->pending update ... */
		9056	smp_rmb();
		9057
		9058	if (work == NULL \|\| atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
3031	serge	9059	spin_unlock_irqrestore(&dev->event_lock, flags);
		9060	return;
		9061	}
2327	Serge	9062
3243	Serge	9063	/* and that the unpin work is consistent wrt ->pending. */
		9064	smp_rmb();
		9065
3031	serge	9066	intel_crtc->unpin_work = NULL;
2327	Serge	9067
3243	Serge	9068	if (work->event)
		9069	drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
2327	Serge	9070
5060	serge	9071	drm_crtc_vblank_put(crtc);
2327	Serge	9072
3031	serge	9073	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	9074
3480	Serge	9075	wake_up_all(&dev_priv->pending_flip_queue);
2327	Serge	9076
3243	Serge	9077	queue_work(dev_priv->wq, &work->work);
		9078
3031	serge	9079	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
		9080	}
2327	Serge	9081
3031	serge	9082	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		9083	{
5060	serge	9084	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9085	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	9086
3031	serge	9087	do_intel_finish_page_flip(dev, crtc);
		9088	}
2327	Serge	9089
3031	serge	9090	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		9091	{
5060	serge	9092	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9093	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	9094
3031	serge	9095	do_intel_finish_page_flip(dev, crtc);
		9096	}
2327	Serge	9097
5060	serge	9098	/* Is 'a' after or equal to 'b'? */
		9099	static bool g4x_flip_count_after_eq(u32 a, u32 b)
		9100	{
		9101	return !((a - b) & 0x80000000);
		9102	}
		9103
		9104	static bool page_flip_finished(struct intel_crtc *crtc)
		9105	{
		9106	struct drm_device *dev = crtc->base.dev;
		9107	struct drm_i915_private *dev_priv = dev->dev_private;
		9108
		9109	/*
		9110	* The relevant registers doen't exist on pre-ctg.
		9111	* As the flip done interrupt doesn't trigger for mmio
		9112	* flips on gmch platforms, a flip count check isn't
		9113	* really needed there. But since ctg has the registers,
		9114	* include it in the check anyway.
		9115	*/
		9116	if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
		9117	return true;
		9118
		9119	/*
		9120	* A DSPSURFLIVE check isn't enough in case the mmio and CS flips
		9121	* used the same base address. In that case the mmio flip might
		9122	* have completed, but the CS hasn't even executed the flip yet.
		9123	*
		9124	* A flip count check isn't enough as the CS might have updated
		9125	* the base address just after start of vblank, but before we
		9126	* managed to process the interrupt. This means we'd complete the
		9127	* CS flip too soon.
		9128	*
		9129	* Combining both checks should get us a good enough result. It may
		9130	* still happen that the CS flip has been executed, but has not
		9131	* yet actually completed. But in case the base address is the same
		9132	* anyway, we don't really care.
		9133	*/
		9134	return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
		9135	crtc->unpin_work->gtt_offset &&
		9136	g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
		9137	crtc->unpin_work->flip_count);
		9138	}
		9139
3031	serge	9140	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		9141	{
5060	serge	9142	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9143	struct intel_crtc *intel_crtc =
		9144	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		9145	unsigned long flags;
2327	Serge	9146
3243	Serge	9147	/* NB: An MMIO update of the plane base pointer will also
		9148	* generate a page-flip completion irq, i.e. every modeset
		9149	* is also accompanied by a spurious intel_prepare_page_flip().
		9150	*/
3031	serge	9151	spin_lock_irqsave(&dev->event_lock, flags);
5060	serge	9152	if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
3243	Serge	9153	atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
3031	serge	9154	spin_unlock_irqrestore(&dev->event_lock, flags);
		9155	}
2327	Serge	9156
5060	serge	9157	static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
3243	Serge	9158	{
		9159	/* Ensure that the work item is consistent when activating it ... */
		9160	smp_wmb();
		9161	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
		9162	/* and that it is marked active as soon as the irq could fire. */
		9163	smp_wmb();
		9164	}
		9165
3031	serge	9166	static int intel_gen2_queue_flip(struct drm_device *dev,
		9167	struct drm_crtc *crtc,
		9168	struct drm_framebuffer *fb,
4104	Serge	9169	struct drm_i915_gem_object *obj,
5060	serge	9170	struct intel_engine_cs *ring,
4104	Serge	9171	uint32_t flags)
3031	serge	9172	{
		9173	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		9174	u32 flip_mask;
		9175	int ret;
2327	Serge	9176
3031	serge	9177	ret = intel_ring_begin(ring, 6);
		9178	if (ret)
5060	serge	9179	return ret;
2327	Serge	9180
3031	serge	9181	/* Can't queue multiple flips, so wait for the previous
		9182	* one to finish before executing the next.
		9183	*/
		9184	if (intel_crtc->plane)
		9185	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		9186	else
		9187	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		9188	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		9189	intel_ring_emit(ring, MI_NOOP);
		9190	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		9191	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		9192	intel_ring_emit(ring, fb->pitches[0]);
5060	serge	9193	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031	serge	9194	intel_ring_emit(ring, 0); /* aux display base address, unused */
3243	Serge	9195
		9196	intel_mark_page_flip_active(intel_crtc);
4560	Serge	9197	__intel_ring_advance(ring);
3031	serge	9198	return 0;
		9199	}
2327	Serge	9200
3031	serge	9201	static int intel_gen3_queue_flip(struct drm_device *dev,
		9202	struct drm_crtc *crtc,
		9203	struct drm_framebuffer *fb,
4104	Serge	9204	struct drm_i915_gem_object *obj,
5060	serge	9205	struct intel_engine_cs *ring,
4104	Serge	9206	uint32_t flags)
3031	serge	9207	{
		9208	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		9209	u32 flip_mask;
		9210	int ret;
2327	Serge	9211
3031	serge	9212	ret = intel_ring_begin(ring, 6);
		9213	if (ret)
5060	serge	9214	return ret;
2327	Serge	9215
3031	serge	9216	if (intel_crtc->plane)
		9217	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		9218	else
		9219	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		9220	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		9221	intel_ring_emit(ring, MI_NOOP);
		9222	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		9223	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		9224	intel_ring_emit(ring, fb->pitches[0]);
5060	serge	9225	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031	serge	9226	intel_ring_emit(ring, MI_NOOP);
2327	Serge	9227
3243	Serge	9228	intel_mark_page_flip_active(intel_crtc);
4560	Serge	9229	__intel_ring_advance(ring);
3031	serge	9230	return 0;
		9231	}
2327	Serge	9232
3031	serge	9233	static int intel_gen4_queue_flip(struct drm_device *dev,
		9234	struct drm_crtc *crtc,
		9235	struct drm_framebuffer *fb,
4104	Serge	9236	struct drm_i915_gem_object *obj,
5060	serge	9237	struct intel_engine_cs *ring,
4104	Serge	9238	uint32_t flags)
3031	serge	9239	{
		9240	struct drm_i915_private *dev_priv = dev->dev_private;
		9241	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		9242	uint32_t pf, pipesrc;
		9243	int ret;
2327	Serge	9244
3031	serge	9245	ret = intel_ring_begin(ring, 4);
		9246	if (ret)
5060	serge	9247	return ret;
2327	Serge	9248
3031	serge	9249	/* i965+ uses the linear or tiled offsets from the
		9250	* Display Registers (which do not change across a page-flip)
		9251	* so we need only reprogram the base address.
		9252	*/
		9253	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		9254	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		9255	intel_ring_emit(ring, fb->pitches[0]);
5060	serge	9256	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset \|
3031	serge	9257	obj->tiling_mode);
2327	Serge	9258
3031	serge	9259	/* XXX Enabling the panel-fitter across page-flip is so far
		9260	* untested on non-native modes, so ignore it for now.
		9261	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		9262	*/
		9263	pf = 0;
		9264	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		9265	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	9266
		9267	intel_mark_page_flip_active(intel_crtc);
4560	Serge	9268	__intel_ring_advance(ring);
3031	serge	9269	return 0;
		9270	}
2327	Serge	9271
3031	serge	9272	static int intel_gen6_queue_flip(struct drm_device *dev,
		9273	struct drm_crtc *crtc,
		9274	struct drm_framebuffer *fb,
4104	Serge	9275	struct drm_i915_gem_object *obj,
5060	serge	9276	struct intel_engine_cs *ring,
4104	Serge	9277	uint32_t flags)
3031	serge	9278	{
		9279	struct drm_i915_private *dev_priv = dev->dev_private;
		9280	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		9281	uint32_t pf, pipesrc;
		9282	int ret;
2327	Serge	9283
3031	serge	9284	ret = intel_ring_begin(ring, 4);
		9285	if (ret)
5060	serge	9286	return ret;
2327	Serge	9287
3031	serge	9288	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		9289	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		9290	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
5060	serge	9291	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
2327	Serge	9292
3031	serge	9293	/* Contrary to the suggestions in the documentation,
		9294	* "Enable Panel Fitter" does not seem to be required when page
		9295	* flipping with a non-native mode, and worse causes a normal
		9296	* modeset to fail.
		9297	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		9298	*/
		9299	pf = 0;
		9300	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		9301	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	9302
		9303	intel_mark_page_flip_active(intel_crtc);
4560	Serge	9304	__intel_ring_advance(ring);
3031	serge	9305	return 0;
		9306	}
2327	Serge	9307
3031	serge	9308	static int intel_gen7_queue_flip(struct drm_device *dev,
		9309	struct drm_crtc *crtc,
		9310	struct drm_framebuffer *fb,
4104	Serge	9311	struct drm_i915_gem_object *obj,
5060	serge	9312	struct intel_engine_cs *ring,
4104	Serge	9313	uint32_t flags)
3031	serge	9314	{
		9315	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		9316	uint32_t plane_bit = 0;
4104	Serge	9317	int len, ret;
2327	Serge	9318
5060	serge	9319	switch (intel_crtc->plane) {
3031	serge	9320	case PLANE_A:
		9321	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		9322	break;
		9323	case PLANE_B:
		9324	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		9325	break;
		9326	case PLANE_C:
		9327	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		9328	break;
		9329	default:
		9330	WARN_ONCE(1, "unknown plane in flip command\n");
5060	serge	9331	return -ENODEV;
3031	serge	9332	}
2327	Serge	9333
4104	Serge	9334	len = 4;
5060	serge	9335	if (ring->id == RCS) {
4104	Serge	9336	len += 6;
5060	serge	9337	/*
		9338	* On Gen 8, SRM is now taking an extra dword to accommodate
		9339	* 48bits addresses, and we need a NOOP for the batch size to
		9340	* stay even.
		9341	*/
		9342	if (IS_GEN8(dev))
		9343	len += 2;
		9344	}
4104	Serge	9345
5060	serge	9346	/*
		9347	* BSpec MI_DISPLAY_FLIP for IVB:
		9348	* "The full packet must be contained within the same cache line."
		9349	*
		9350	* Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
		9351	* cacheline, if we ever start emitting more commands before
		9352	* the MI_DISPLAY_FLIP we may need to first emit everything else,
		9353	* then do the cacheline alignment, and finally emit the
		9354	* MI_DISPLAY_FLIP.
		9355	*/
		9356	ret = intel_ring_cacheline_align(ring);
		9357	if (ret)
		9358	return ret;
		9359
4104	Serge	9360	ret = intel_ring_begin(ring, len);
3031	serge	9361	if (ret)
5060	serge	9362	return ret;
2327	Serge	9363
4104	Serge	9364	/* Unmask the flip-done completion message. Note that the bspec says that
		9365	* we should do this for both the BCS and RCS, and that we must not unmask
		9366	* more than one flip event at any time (or ensure that one flip message
		9367	* can be sent by waiting for flip-done prior to queueing new flips).
		9368	* Experimentation says that BCS works despite DERRMR masking all
		9369	* flip-done completion events and that unmasking all planes at once
		9370	* for the RCS also doesn't appear to drop events. Setting the DERRMR
		9371	* to zero does lead to lockups within MI_DISPLAY_FLIP.
		9372	*/
		9373	if (ring->id == RCS) {
		9374	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		9375	intel_ring_emit(ring, DERRMR);
		9376	intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE \|
		9377	DERRMR_PIPEB_PRI_FLIP_DONE \|
		9378	DERRMR_PIPEC_PRI_FLIP_DONE));
5060	serge	9379	if (IS_GEN8(dev))
		9380	intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) \|
		9381	MI_SRM_LRM_GLOBAL_GTT);
		9382	else
4560	Serge	9383	intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) \|
		9384	MI_SRM_LRM_GLOBAL_GTT);
4104	Serge	9385	intel_ring_emit(ring, DERRMR);
		9386	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
5060	serge	9387	if (IS_GEN8(dev)) {
		9388	intel_ring_emit(ring, 0);
		9389	intel_ring_emit(ring, MI_NOOP);
		9390	}
4104	Serge	9391	}
		9392
3031	serge	9393	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		9394	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
5060	serge	9395	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
3031	serge	9396	intel_ring_emit(ring, (MI_NOOP));
3243	Serge	9397
		9398	intel_mark_page_flip_active(intel_crtc);
4560	Serge	9399	__intel_ring_advance(ring);
3031	serge	9400	return 0;
		9401	}
2327	Serge	9402
3031	serge	9403	static int intel_default_queue_flip(struct drm_device *dev,
		9404	struct drm_crtc *crtc,
		9405	struct drm_framebuffer *fb,
4104	Serge	9406	struct drm_i915_gem_object *obj,
5060	serge	9407	struct intel_engine_cs *ring,
4104	Serge	9408	uint32_t flags)
3031	serge	9409	{
		9410	return -ENODEV;
		9411	}
2327	Serge	9412
3031	serge	9413	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		9414	struct drm_framebuffer *fb,
4104	Serge	9415	struct drm_pending_vblank_event *event,
		9416	uint32_t page_flip_flags)
3031	serge	9417	{
		9418	struct drm_device *dev = crtc->dev;
		9419	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	9420	struct drm_framebuffer *old_fb = crtc->primary->fb;
		9421	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3031	serge	9422	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060	serge	9423	enum pipe pipe = intel_crtc->pipe;
3031	serge	9424	struct intel_unpin_work *work;
5060	serge	9425	struct intel_engine_cs *ring;
3031	serge	9426	unsigned long flags;
		9427	int ret;
2327	Serge	9428
5060	serge	9429	/*
		9430	* drm_mode_page_flip_ioctl() should already catch this, but double
		9431	* check to be safe. In the future we may enable pageflipping from
		9432	* a disabled primary plane.
		9433	*/
		9434	if (WARN_ON(intel_fb_obj(old_fb) == NULL))
		9435	return -EBUSY;
		9436
3031	serge	9437	/* Can't change pixel format via MI display flips. */
5060	serge	9438	if (fb->pixel_format != crtc->primary->fb->pixel_format)
3031	serge	9439	return -EINVAL;
2327	Serge	9440
3031	serge	9441	/*
		9442	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		9443	* Note that pitch changes could also affect these register.
		9444	*/
		9445	if (INTEL_INFO(dev)->gen > 3 &&
5060	serge	9446	(fb->offsets[0] != crtc->primary->fb->offsets[0] \|\|
		9447	fb->pitches[0] != crtc->primary->fb->pitches[0]))
3031	serge	9448	return -EINVAL;
2327	Serge	9449
4560	Serge	9450	work = kzalloc(sizeof(*work), GFP_KERNEL);
3031	serge	9451	if (work == NULL)
		9452	return -ENOMEM;
2327	Serge	9453
3031	serge	9454	work->event = event;
3243	Serge	9455	work->crtc = crtc;
5060	serge	9456	work->old_fb_obj = intel_fb_obj(old_fb);
3031	serge	9457	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	9458
5060	serge	9459	ret = drm_crtc_vblank_get(crtc);
3031	serge	9460	if (ret)
		9461	goto free_work;
2327	Serge	9462
3031	serge	9463	/* We borrow the event spin lock for protecting unpin_work */
		9464	spin_lock_irqsave(&dev->event_lock, flags);
		9465	if (intel_crtc->unpin_work) {
		9466	spin_unlock_irqrestore(&dev->event_lock, flags);
		9467	kfree(work);
5060	serge	9468	drm_crtc_vblank_put(crtc);
2327	Serge	9469
3031	serge	9470	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		9471	return -EBUSY;
		9472	}
		9473	intel_crtc->unpin_work = work;
		9474	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	9475
3243	Serge	9476	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		9477	flush_workqueue(dev_priv->wq);
		9478
3031	serge	9479	ret = i915_mutex_lock_interruptible(dev);
		9480	if (ret)
		9481	goto cleanup;
2327	Serge	9482
3031	serge	9483	/* Reference the objects for the scheduled work. */
		9484	drm_gem_object_reference(&work->old_fb_obj->base);
		9485	drm_gem_object_reference(&obj->base);
2327	Serge	9486
5060	serge	9487	crtc->primary->fb = fb;
2327	Serge	9488
3031	serge	9489	work->pending_flip_obj = obj;
2327	Serge	9490
3031	serge	9491	work->enable_stall_check = true;
		9492
3243	Serge	9493	atomic_inc(&intel_crtc->unpin_work_count);
3480	Serge	9494	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3031	serge	9495
5060	serge	9496	if (INTEL_INFO(dev)->gen >= 5 \|\| IS_G4X(dev))
		9497	work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
		9498
		9499	if (IS_VALLEYVIEW(dev)) {
		9500	ring = &dev_priv->ring[BCS];
		9501	if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
		9502	/* vlv: DISPLAY_FLIP fails to change tiling */
		9503	ring = NULL;
		9504	} else if (IS_IVYBRIDGE(dev)) {
		9505	ring = &dev_priv->ring[BCS];
		9506	} else if (INTEL_INFO(dev)->gen >= 7) {
		9507	ring = obj->ring;
		9508	if (ring == NULL \|\| ring->id != RCS)
		9509	ring = &dev_priv->ring[BCS];
		9510	} else {
		9511	ring = &dev_priv->ring[RCS];
		9512	}
		9513
		9514	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
3031	serge	9515	if (ret)
		9516	goto cleanup_pending;
		9517
5060	serge	9518	work->gtt_offset =
		9519	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
		9520
		9521	if (use_mmio_flip(ring, obj))
		9522	ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
		9523	page_flip_flags);
		9524	else
		9525	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
		9526	page_flip_flags);
		9527	if (ret)
		9528	goto cleanup_unpin;
		9529
		9530	i915_gem_track_fb(work->old_fb_obj, obj,
		9531	INTEL_FRONTBUFFER_PRIMARY(pipe));
		9532
3031	serge	9533	intel_disable_fbc(dev);
5060	serge	9534	intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
3031	serge	9535	mutex_unlock(&dev->struct_mutex);
		9536
		9537	trace_i915_flip_request(intel_crtc->plane, obj);
		9538
		9539	return 0;
		9540
5060	serge	9541	cleanup_unpin:
		9542	intel_unpin_fb_obj(obj);
3031	serge	9543	cleanup_pending:
3243	Serge	9544	atomic_dec(&intel_crtc->unpin_work_count);
5060	serge	9545	crtc->primary->fb = old_fb;
3031	serge	9546	drm_gem_object_unreference(&work->old_fb_obj->base);
		9547	drm_gem_object_unreference(&obj->base);
		9548	mutex_unlock(&dev->struct_mutex);
		9549
		9550	cleanup:
		9551	spin_lock_irqsave(&dev->event_lock, flags);
		9552	intel_crtc->unpin_work = NULL;
		9553	spin_unlock_irqrestore(&dev->event_lock, flags);
		9554
5060	serge	9555	drm_crtc_vblank_put(crtc);
3031	serge	9556	free_work:
		9557	kfree(work);
		9558
5060	serge	9559	if (ret == -EIO) {
		9560	out_hang:
		9561	intel_crtc_wait_for_pending_flips(crtc);
		9562	ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
		9563	if (ret == 0 && event)
		9564	drm_send_vblank_event(dev, pipe, event);
		9565	}
3031	serge	9566	return ret;
		9567	}
		9568	#endif
		9569
		9570	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		9571	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		9572	.load_lut = intel_crtc_load_lut,
		9573	};
		9574
		9575	/**
		9576	* intel_modeset_update_staged_output_state
		9577	*
		9578	* Updates the staged output configuration state, e.g. after we've read out the
		9579	* current hw state.
		9580	*/
		9581	static void intel_modeset_update_staged_output_state(struct drm_device *dev)
		9582	{
5060	serge	9583	struct intel_crtc *crtc;
3031	serge	9584	struct intel_encoder *encoder;
		9585	struct intel_connector *connector;
		9586
		9587	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9588	base.head) {
		9589	connector->new_encoder =
		9590	to_intel_encoder(connector->base.encoder);
		9591	}
		9592
		9593	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9594	base.head) {
		9595	encoder->new_crtc =
		9596	to_intel_crtc(encoder->base.crtc);
		9597	}
5060	serge	9598
		9599	for_each_intel_crtc(dev, crtc) {
		9600	crtc->new_enabled = crtc->base.enabled;
		9601
		9602	if (crtc->new_enabled)
		9603	crtc->new_config = &crtc->config;
		9604	else
		9605	crtc->new_config = NULL;
		9606	}
3031	serge	9607	}
		9608
		9609	/**
		9610	* intel_modeset_commit_output_state
		9611	*
		9612	* This function copies the stage display pipe configuration to the real one.
		9613	*/
		9614	static void intel_modeset_commit_output_state(struct drm_device *dev)
		9615	{
5060	serge	9616	struct intel_crtc *crtc;
3031	serge	9617	struct intel_encoder *encoder;
		9618	struct intel_connector *connector;
		9619
		9620	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9621	base.head) {
		9622	connector->base.encoder = &connector->new_encoder->base;
		9623	}
		9624
		9625	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9626	base.head) {
		9627	encoder->base.crtc = &encoder->new_crtc->base;
		9628	}
5060	serge	9629
		9630	for_each_intel_crtc(dev, crtc) {
		9631	crtc->base.enabled = crtc->new_enabled;
		9632	}
3031	serge	9633	}
		9634
4104	Serge	9635	static void
5060	serge	9636	connected_sink_compute_bpp(struct intel_connector *connector,
4104	Serge	9637	struct intel_crtc_config *pipe_config)
		9638	{
		9639	int bpp = pipe_config->pipe_bpp;
		9640
		9641	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
		9642	connector->base.base.id,
5060	serge	9643	connector->base.name);
4104	Serge	9644
		9645	/* Don't use an invalid EDID bpc value */
		9646	if (connector->base.display_info.bpc &&
		9647	connector->base.display_info.bpc * 3 < bpp) {
		9648	DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
		9649	bpp, connector->base.display_info.bpc*3);
		9650	pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
		9651	}
		9652
		9653	/* Clamp bpp to 8 on screens without EDID 1.4 */
		9654	if (connector->base.display_info.bpc == 0 && bpp > 24) {
		9655	DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
		9656	bpp);
		9657	pipe_config->pipe_bpp = 24;
		9658	}
		9659	}
		9660
3746	Serge	9661	static int
4104	Serge	9662	compute_baseline_pipe_bpp(struct intel_crtc *crtc,
3746	Serge	9663	struct drm_framebuffer *fb,
		9664	struct intel_crtc_config *pipe_config)
		9665	{
4104	Serge	9666	struct drm_device *dev = crtc->base.dev;
		9667	struct intel_connector *connector;
3746	Serge	9668	int bpp;
		9669
		9670	switch (fb->pixel_format) {
		9671	case DRM_FORMAT_C8:
		9672	bpp = 83; / since we go through a colormap */
		9673	break;
		9674	case DRM_FORMAT_XRGB1555:
		9675	case DRM_FORMAT_ARGB1555:
		9676	/* checked in intel_framebuffer_init already */
		9677	if (WARN_ON(INTEL_INFO(dev)->gen > 3))
		9678	return -EINVAL;
		9679	case DRM_FORMAT_RGB565:
		9680	bpp = 63; / min is 18bpp */
		9681	break;
		9682	case DRM_FORMAT_XBGR8888:
		9683	case DRM_FORMAT_ABGR8888:
		9684	/* checked in intel_framebuffer_init already */
		9685	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		9686	return -EINVAL;
		9687	case DRM_FORMAT_XRGB8888:
		9688	case DRM_FORMAT_ARGB8888:
		9689	bpp = 8*3;
		9690	break;
		9691	case DRM_FORMAT_XRGB2101010:
		9692	case DRM_FORMAT_ARGB2101010:
		9693	case DRM_FORMAT_XBGR2101010:
		9694	case DRM_FORMAT_ABGR2101010:
		9695	/* checked in intel_framebuffer_init already */
		9696	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		9697	return -EINVAL;
		9698	bpp = 10*3;
		9699	break;
		9700	/* TODO: gen4+ supports 16 bpc floating point, too. */
		9701	default:
		9702	DRM_DEBUG_KMS("unsupported depth\n");
		9703	return -EINVAL;
		9704	}
		9705
		9706	pipe_config->pipe_bpp = bpp;
		9707
		9708	/* Clamp display bpp to EDID value */
		9709	list_for_each_entry(connector, &dev->mode_config.connector_list,
4104	Serge	9710	base.head) {
		9711	if (!connector->new_encoder \|\|
		9712	connector->new_encoder->new_crtc != crtc)
3746	Serge	9713	continue;
		9714
4104	Serge	9715	connected_sink_compute_bpp(connector, pipe_config);
3746	Serge	9716	}
		9717
		9718	return bpp;
		9719	}
		9720
4560	Serge	9721	static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
		9722	{
		9723	DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
		9724	"type: 0x%x flags: 0x%x\n",
		9725	mode->crtc_clock,
		9726	mode->crtc_hdisplay, mode->crtc_hsync_start,
		9727	mode->crtc_hsync_end, mode->crtc_htotal,
		9728	mode->crtc_vdisplay, mode->crtc_vsync_start,
		9729	mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
		9730	}
		9731
4104	Serge	9732	static void intel_dump_pipe_config(struct intel_crtc *crtc,
		9733	struct intel_crtc_config *pipe_config,
		9734	const char *context)
		9735	{
		9736	DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
		9737	context, pipe_name(crtc->pipe));
		9738
		9739	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
		9740	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
		9741	pipe_config->pipe_bpp, pipe_config->dither);
		9742	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		9743	pipe_config->has_pch_encoder,
		9744	pipe_config->fdi_lanes,
		9745	pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
		9746	pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
		9747	pipe_config->fdi_m_n.tu);
4560	Serge	9748	DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		9749	pipe_config->has_dp_encoder,
		9750	pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
		9751	pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
		9752	pipe_config->dp_m_n.tu);
4104	Serge	9753	DRM_DEBUG_KMS("requested mode:\n");
		9754	drm_mode_debug_printmodeline(&pipe_config->requested_mode);
		9755	DRM_DEBUG_KMS("adjusted mode:\n");
		9756	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
4560	Serge	9757	intel_dump_crtc_timings(&pipe_config->adjusted_mode);
		9758	DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
		9759	DRM_DEBUG_KMS("pipe src size: %dx%d\n",
		9760	pipe_config->pipe_src_w, pipe_config->pipe_src_h);
4104	Serge	9761	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
		9762	pipe_config->gmch_pfit.control,
		9763	pipe_config->gmch_pfit.pgm_ratios,
		9764	pipe_config->gmch_pfit.lvds_border_bits);
		9765	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
		9766	pipe_config->pch_pfit.pos,
		9767	pipe_config->pch_pfit.size,
		9768	pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
		9769	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
4560	Serge	9770	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
4104	Serge	9771	}
		9772
5060	serge	9773	static bool encoders_cloneable(const struct intel_encoder *a,
		9774	const struct intel_encoder *b)
4104	Serge	9775	{
5060	serge	9776	/* masks could be asymmetric, so check both ways */
		9777	return a == b \|\| (a->cloneable & (1 << b->type) &&
		9778	b->cloneable & (1 << a->type));
		9779	}
		9780
		9781	static bool check_single_encoder_cloning(struct intel_crtc *crtc,
		9782	struct intel_encoder *encoder)
		9783	{
		9784	struct drm_device *dev = crtc->base.dev;
		9785	struct intel_encoder *source_encoder;
		9786
		9787	list_for_each_entry(source_encoder,
		9788	&dev->mode_config.encoder_list, base.head) {
		9789	if (source_encoder->new_crtc != crtc)
		9790	continue;
		9791
		9792	if (!encoders_cloneable(encoder, source_encoder))
		9793	return false;
		9794	}
		9795
		9796	return true;
		9797	}
		9798
		9799	static bool check_encoder_cloning(struct intel_crtc *crtc)
		9800	{
		9801	struct drm_device *dev = crtc->base.dev;
4104	Serge	9802	struct intel_encoder *encoder;
		9803
5060	serge	9804	list_for_each_entry(encoder,
		9805	&dev->mode_config.encoder_list, base.head) {
		9806	if (encoder->new_crtc != crtc)
4104	Serge	9807	continue;
		9808
5060	serge	9809	if (!check_single_encoder_cloning(crtc, encoder))
		9810	return false;
4104	Serge	9811	}
		9812
5060	serge	9813	return true;
4104	Serge	9814	}
		9815
3746	Serge	9816	static struct intel_crtc_config *
		9817	intel_modeset_pipe_config(struct drm_crtc *crtc,
		9818	struct drm_framebuffer *fb,
3031	serge	9819	struct drm_display_mode *mode)
		9820	{
		9821	struct drm_device *dev = crtc->dev;
		9822	struct intel_encoder *encoder;
3746	Serge	9823	struct intel_crtc_config *pipe_config;
4104	Serge	9824	int plane_bpp, ret = -EINVAL;
		9825	bool retry = true;
3031	serge	9826
5060	serge	9827	if (!check_encoder_cloning(to_intel_crtc(crtc))) {
4104	Serge	9828	DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
		9829	return ERR_PTR(-EINVAL);
		9830	}
		9831
3746	Serge	9832	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
		9833	if (!pipe_config)
3031	serge	9834	return ERR_PTR(-ENOMEM);
		9835
3746	Serge	9836	drm_mode_copy(&pipe_config->adjusted_mode, mode);
		9837	drm_mode_copy(&pipe_config->requested_mode, mode);
4560	Serge	9838
4104	Serge	9839	pipe_config->cpu_transcoder =
		9840	(enum transcoder) to_intel_crtc(crtc)->pipe;
		9841	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
3746	Serge	9842
4104	Serge	9843	/*
		9844	* Sanitize sync polarity flags based on requested ones. If neither
		9845	* positive or negative polarity is requested, treat this as meaning
		9846	* negative polarity.
		9847	*/
		9848	if (!(pipe_config->adjusted_mode.flags &
		9849	(DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NHSYNC)))
		9850	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		9851
		9852	if (!(pipe_config->adjusted_mode.flags &
		9853	(DRM_MODE_FLAG_PVSYNC \| DRM_MODE_FLAG_NVSYNC)))
		9854	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		9855
		9856	/* Compute a starting value for pipe_config->pipe_bpp taking the source
		9857	* plane pixel format and any sink constraints into account. Returns the
		9858	* source plane bpp so that dithering can be selected on mismatches
		9859	* after encoders and crtc also have had their say. */
		9860	plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
		9861	fb, pipe_config);
3746	Serge	9862	if (plane_bpp < 0)
		9863	goto fail;
		9864
4560	Serge	9865	/*
		9866	* Determine the real pipe dimensions. Note that stereo modes can
		9867	* increase the actual pipe size due to the frame doubling and
		9868	* insertion of additional space for blanks between the frame. This
		9869	* is stored in the crtc timings. We use the requested mode to do this
		9870	* computation to clearly distinguish it from the adjusted mode, which
		9871	* can be changed by the connectors in the below retry loop.
		9872	*/
		9873	drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
		9874	pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
		9875	pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
		9876
4104	Serge	9877	encoder_retry:
		9878	/* Ensure the port clock defaults are reset when retrying. */
		9879	pipe_config->port_clock = 0;
		9880	pipe_config->pixel_multiplier = 1;
		9881
		9882	/* Fill in default crtc timings, allow encoders to overwrite them. */
4560	Serge	9883	drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
4104	Serge	9884
3031	serge	9885	/* Pass our mode to the connectors and the CRTC to give them a chance to
		9886	* adjust it according to limitations or connector properties, and also
		9887	* a chance to reject the mode entirely.
2330	Serge	9888	*/
3031	serge	9889	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9890	base.head) {
2327	Serge	9891
3031	serge	9892	if (&encoder->new_crtc->base != crtc)
		9893	continue;
3746	Serge	9894
		9895	if (!(encoder->compute_config(encoder, pipe_config))) {
		9896	DRM_DEBUG_KMS("Encoder config failure\n");
		9897	goto fail;
		9898	}
		9899	}
		9900
4104	Serge	9901	/* Set default port clock if not overwritten by the encoder. Needs to be
		9902	* done afterwards in case the encoder adjusts the mode. */
		9903	if (!pipe_config->port_clock)
4560	Serge	9904	pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
		9905	* pipe_config->pixel_multiplier;
2327	Serge	9906
4104	Serge	9907	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
		9908	if (ret < 0) {
3031	serge	9909	DRM_DEBUG_KMS("CRTC fixup failed\n");
		9910	goto fail;
		9911	}
2327	Serge	9912
4104	Serge	9913	if (ret == RETRY) {
		9914	if (WARN(!retry, "loop in pipe configuration computation\n")) {
		9915	ret = -EINVAL;
		9916	goto fail;
		9917	}
		9918
		9919	DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
		9920	retry = false;
		9921	goto encoder_retry;
		9922	}
		9923
3746	Serge	9924	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
		9925	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		9926	plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
		9927
		9928	return pipe_config;
3031	serge	9929	fail:
3746	Serge	9930	kfree(pipe_config);
4104	Serge	9931	return ERR_PTR(ret);
3031	serge	9932	}
2327	Serge	9933
3031	serge	9934	/* Computes which crtcs are affected and sets the relevant bits in the mask. For
		9935	* simplicity we use the crtc's pipe number (because it's easier to obtain). */
		9936	static void
		9937	intel_modeset_affected_pipes(struct drm_crtc crtc, unsigned modeset_pipes,
		9938	unsigned prepare_pipes, unsigned disable_pipes)
		9939	{
		9940	struct intel_crtc *intel_crtc;
		9941	struct drm_device *dev = crtc->dev;
		9942	struct intel_encoder *encoder;
		9943	struct intel_connector *connector;
		9944	struct drm_crtc *tmp_crtc;
		9945
		9946	disable_pipes = modeset_pipes = *prepare_pipes = 0;
		9947
		9948	/* Check which crtcs have changed outputs connected to them, these need
		9949	* to be part of the prepare_pipes mask. We don't (yet) support global
		9950	* modeset across multiple crtcs, so modeset_pipes will only have one
		9951	* bit set at most. */
		9952	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9953	base.head) {
		9954	if (connector->base.encoder == &connector->new_encoder->base)
		9955	continue;
		9956
		9957	if (connector->base.encoder) {
		9958	tmp_crtc = connector->base.encoder->crtc;
		9959
		9960	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		9961	}
		9962
		9963	if (connector->new_encoder)
		9964	*prepare_pipes \|=
		9965	1 << connector->new_encoder->new_crtc->pipe;
		9966	}
		9967
		9968	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9969	base.head) {
		9970	if (encoder->base.crtc == &encoder->new_crtc->base)
		9971	continue;
		9972
		9973	if (encoder->base.crtc) {
		9974	tmp_crtc = encoder->base.crtc;
		9975
		9976	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		9977	}
		9978
		9979	if (encoder->new_crtc)
		9980	*prepare_pipes \|= 1 << encoder->new_crtc->pipe;
		9981	}
		9982
5060	serge	9983	/* Check for pipes that will be enabled/disabled ... */
		9984	for_each_intel_crtc(dev, intel_crtc) {
		9985	if (intel_crtc->base.enabled == intel_crtc->new_enabled)
3031	serge	9986	continue;
		9987
5060	serge	9988	if (!intel_crtc->new_enabled)
3031	serge	9989	*disable_pipes \|= 1 << intel_crtc->pipe;
5060	serge	9990	else
		9991	*prepare_pipes \|= 1 << intel_crtc->pipe;
3031	serge	9992	}
		9993
		9994
		9995	/* set_mode is also used to update properties on life display pipes. */
		9996	intel_crtc = to_intel_crtc(crtc);
5060	serge	9997	if (intel_crtc->new_enabled)
3031	serge	9998	*prepare_pipes \|= 1 << intel_crtc->pipe;
		9999
3746	Serge	10000	/*
		10001	* For simplicity do a full modeset on any pipe where the output routing
		10002	* changed. We could be more clever, but that would require us to be
		10003	* more careful with calling the relevant encoder->mode_set functions.
		10004	*/
3031	serge	10005	if (*prepare_pipes)
		10006	modeset_pipes = prepare_pipes;
		10007
		10008	/* ... and mask these out. */
		10009	modeset_pipes &= ~(disable_pipes);
		10010	prepare_pipes &= ~(disable_pipes);
3746	Serge	10011
		10012	/*
		10013	* HACK: We don't (yet) fully support global modesets. intel_set_config
		10014	* obies this rule, but the modeset restore mode of
		10015	* intel_modeset_setup_hw_state does not.
		10016	*/
		10017	*modeset_pipes &= 1 << intel_crtc->pipe;
		10018	*prepare_pipes &= 1 << intel_crtc->pipe;
4104	Serge	10019
		10020	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		10021	modeset_pipes, prepare_pipes, *disable_pipes);
2330	Serge	10022	}
2327	Serge	10023
3031	serge	10024	static bool intel_crtc_in_use(struct drm_crtc *crtc)
2330	Serge	10025	{
3031	serge	10026	struct drm_encoder *encoder;
2330	Serge	10027	struct drm_device *dev = crtc->dev;
2327	Serge	10028
3031	serge	10029	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		10030	if (encoder->crtc == crtc)
		10031	return true;
		10032
		10033	return false;
		10034	}
		10035
		10036	static void
		10037	intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
		10038	{
		10039	struct intel_encoder *intel_encoder;
		10040	struct intel_crtc *intel_crtc;
		10041	struct drm_connector *connector;
		10042
		10043	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
		10044	base.head) {
		10045	if (!intel_encoder->base.crtc)
		10046	continue;
		10047
		10048	intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
		10049
		10050	if (prepare_pipes & (1 << intel_crtc->pipe))
		10051	intel_encoder->connectors_active = false;
		10052	}
		10053
		10054	intel_modeset_commit_output_state(dev);
		10055
5060	serge	10056	/* Double check state. */
		10057	for_each_intel_crtc(dev, intel_crtc) {
		10058	WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
		10059	WARN_ON(intel_crtc->new_config &&
		10060	intel_crtc->new_config != &intel_crtc->config);
		10061	WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
3031	serge	10062	}
		10063
		10064	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		10065	if (!connector->encoder \|\| !connector->encoder->crtc)
		10066	continue;
		10067
		10068	intel_crtc = to_intel_crtc(connector->encoder->crtc);
		10069
		10070	if (prepare_pipes & (1 << intel_crtc->pipe)) {
		10071	struct drm_property *dpms_property =
		10072	dev->mode_config.dpms_property;
		10073
		10074	connector->dpms = DRM_MODE_DPMS_ON;
3243	Serge	10075	drm_object_property_set_value(&connector->base,
3031	serge	10076	dpms_property,
		10077	DRM_MODE_DPMS_ON);
		10078
		10079	intel_encoder = to_intel_encoder(connector->encoder);
		10080	intel_encoder->connectors_active = true;
		10081	}
		10082	}
		10083
		10084	}
		10085
4560	Serge	10086	static bool intel_fuzzy_clock_check(int clock1, int clock2)
4104	Serge	10087	{
4560	Serge	10088	int diff;
4104	Serge	10089
		10090	if (clock1 == clock2)
		10091	return true;
		10092
		10093	if (!clock1 \|\| !clock2)
		10094	return false;
		10095
		10096	diff = abs(clock1 - clock2);
		10097
		10098	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
		10099	return true;
		10100
		10101	return false;
		10102	}
		10103
3031	serge	10104	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		10105	list_for_each_entry((intel_crtc), \
		10106	&(dev)->mode_config.crtc_list, \
		10107	base.head) \
4104	Serge	10108	if (mask & (1 <<(intel_crtc)->pipe))
3031	serge	10109
3746	Serge	10110	static bool
4104	Serge	10111	intel_pipe_config_compare(struct drm_device *dev,
		10112	struct intel_crtc_config *current_config,
3746	Serge	10113	struct intel_crtc_config *pipe_config)
		10114	{
4104	Serge	10115	#define PIPE_CONF_CHECK_X(name) \
		10116	if (current_config->name != pipe_config->name) { \
		10117	DRM_ERROR("mismatch in " #name " " \
		10118	"(expected 0x%08x, found 0x%08x)\n", \
		10119	current_config->name, \
		10120	pipe_config->name); \
		10121	return false; \
3746	Serge	10122	}
		10123
4104	Serge	10124	#define PIPE_CONF_CHECK_I(name) \
		10125	if (current_config->name != pipe_config->name) { \
		10126	DRM_ERROR("mismatch in " #name " " \
		10127	"(expected %i, found %i)\n", \
		10128	current_config->name, \
		10129	pipe_config->name); \
		10130	return false; \
		10131	}
		10132
		10133	#define PIPE_CONF_CHECK_FLAGS(name, mask) \
		10134	if ((current_config->name ^ pipe_config->name) & (mask)) { \
		10135	DRM_ERROR("mismatch in " #name "(" #mask ") " \
		10136	"(expected %i, found %i)\n", \
		10137	current_config->name & (mask), \
		10138	pipe_config->name & (mask)); \
		10139	return false; \
		10140	}
		10141
4560	Serge	10142	#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
		10143	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
		10144	DRM_ERROR("mismatch in " #name " " \
		10145	"(expected %i, found %i)\n", \
		10146	current_config->name, \
		10147	pipe_config->name); \
		10148	return false; \
		10149	}
		10150
4104	Serge	10151	#define PIPE_CONF_QUIRK(quirk) \
		10152	((current_config->quirks \| pipe_config->quirks) & (quirk))
		10153
		10154	PIPE_CONF_CHECK_I(cpu_transcoder);
		10155
		10156	PIPE_CONF_CHECK_I(has_pch_encoder);
		10157	PIPE_CONF_CHECK_I(fdi_lanes);
		10158	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
		10159	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
		10160	PIPE_CONF_CHECK_I(fdi_m_n.link_m);
		10161	PIPE_CONF_CHECK_I(fdi_m_n.link_n);
		10162	PIPE_CONF_CHECK_I(fdi_m_n.tu);
		10163
4560	Serge	10164	PIPE_CONF_CHECK_I(has_dp_encoder);
		10165	PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
		10166	PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
		10167	PIPE_CONF_CHECK_I(dp_m_n.link_m);
		10168	PIPE_CONF_CHECK_I(dp_m_n.link_n);
		10169	PIPE_CONF_CHECK_I(dp_m_n.tu);
		10170
4104	Serge	10171	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
		10172	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
		10173	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
		10174	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
		10175	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
		10176	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
		10177
		10178	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
		10179	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
		10180	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
		10181	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
		10182	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
		10183	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
		10184
		10185	PIPE_CONF_CHECK_I(pixel_multiplier);
5060	serge	10186	PIPE_CONF_CHECK_I(has_hdmi_sink);
		10187	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) \|\|
		10188	IS_VALLEYVIEW(dev))
		10189	PIPE_CONF_CHECK_I(limited_color_range);
4104	Serge	10190
5060	serge	10191	PIPE_CONF_CHECK_I(has_audio);
		10192
4104	Serge	10193	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		10194	DRM_MODE_FLAG_INTERLACE);
		10195
		10196	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
		10197	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		10198	DRM_MODE_FLAG_PHSYNC);
		10199	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		10200	DRM_MODE_FLAG_NHSYNC);
		10201	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		10202	DRM_MODE_FLAG_PVSYNC);
		10203	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		10204	DRM_MODE_FLAG_NVSYNC);
		10205	}
		10206
4560	Serge	10207	PIPE_CONF_CHECK_I(pipe_src_w);
		10208	PIPE_CONF_CHECK_I(pipe_src_h);
4104	Serge	10209
5060	serge	10210	/*
		10211	* FIXME: BIOS likes to set up a cloned config with lvds+external
		10212	* screen. Since we don't yet re-compute the pipe config when moving
		10213	* just the lvds port away to another pipe the sw tracking won't match.
		10214	*
		10215	* Proper atomic modesets with recomputed global state will fix this.
		10216	* Until then just don't check gmch state for inherited modes.
		10217	*/
		10218	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
4104	Serge	10219	PIPE_CONF_CHECK_I(gmch_pfit.control);
		10220	/* pfit ratios are autocomputed by the hw on gen4+ */
		10221	if (INTEL_INFO(dev)->gen < 4)
		10222	PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
		10223	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
5060	serge	10224	}
		10225
4104	Serge	10226	PIPE_CONF_CHECK_I(pch_pfit.enabled);
		10227	if (current_config->pch_pfit.enabled) {
		10228	PIPE_CONF_CHECK_I(pch_pfit.pos);
		10229	PIPE_CONF_CHECK_I(pch_pfit.size);
		10230	}
		10231
4560	Serge	10232	/* BDW+ don't expose a synchronous way to read the state */
		10233	if (IS_HASWELL(dev))
4104	Serge	10234	PIPE_CONF_CHECK_I(ips_enabled);
		10235
4560	Serge	10236	PIPE_CONF_CHECK_I(double_wide);
		10237
5060	serge	10238	PIPE_CONF_CHECK_X(ddi_pll_sel);
		10239
4104	Serge	10240	PIPE_CONF_CHECK_I(shared_dpll);
		10241	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
		10242	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
		10243	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
		10244	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5060	serge	10245	PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
4104	Serge	10246
4280	Serge	10247	if (IS_G4X(dev) \|\| INTEL_INFO(dev)->gen >= 5)
		10248	PIPE_CONF_CHECK_I(pipe_bpp);
		10249
4560	Serge	10250	PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
		10251	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
		10252
4104	Serge	10253	#undef PIPE_CONF_CHECK_X
		10254	#undef PIPE_CONF_CHECK_I
		10255	#undef PIPE_CONF_CHECK_FLAGS
4560	Serge	10256	#undef PIPE_CONF_CHECK_CLOCK_FUZZY
4104	Serge	10257	#undef PIPE_CONF_QUIRK
		10258
3746	Serge	10259	return true;
		10260	}
		10261
4104	Serge	10262	static void
		10263	check_connector_state(struct drm_device *dev)
3031	serge	10264	{
		10265	struct intel_connector *connector;
		10266
		10267	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10268	base.head) {
		10269	/* This also checks the encoder/connector hw state with the
		10270	* ->get_hw_state callbacks. */
		10271	intel_connector_check_state(connector);
		10272
		10273	WARN(&connector->new_encoder->base != connector->base.encoder,
		10274	"connector's staged encoder doesn't match current encoder\n");
		10275	}
4104	Serge	10276	}
3031	serge	10277
4104	Serge	10278	static void
		10279	check_encoder_state(struct drm_device *dev)
		10280	{
		10281	struct intel_encoder *encoder;
		10282	struct intel_connector *connector;
		10283
3031	serge	10284	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10285	base.head) {
		10286	bool enabled = false;
		10287	bool active = false;
		10288	enum pipe pipe, tracked_pipe;
		10289
		10290	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		10291	encoder->base.base.id,
5060	serge	10292	encoder->base.name);
3031	serge	10293
		10294	WARN(&encoder->new_crtc->base != encoder->base.crtc,
		10295	"encoder's stage crtc doesn't match current crtc\n");
		10296	WARN(encoder->connectors_active && !encoder->base.crtc,
		10297	"encoder's active_connectors set, but no crtc\n");
		10298
		10299	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10300	base.head) {
		10301	if (connector->base.encoder != &encoder->base)
		10302	continue;
		10303	enabled = true;
		10304	if (connector->base.dpms != DRM_MODE_DPMS_OFF)
		10305	active = true;
		10306	}
5060	serge	10307	/*
		10308	* for MST connectors if we unplug the connector is gone
		10309	* away but the encoder is still connected to a crtc
		10310	* until a modeset happens in response to the hotplug.
		10311	*/
		10312	if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
		10313	continue;
		10314
3031	serge	10315	WARN(!!encoder->base.crtc != enabled,
		10316	"encoder's enabled state mismatch "
		10317	"(expected %i, found %i)\n",
		10318	!!encoder->base.crtc, enabled);
		10319	WARN(active && !encoder->base.crtc,
		10320	"active encoder with no crtc\n");
		10321
		10322	WARN(encoder->connectors_active != active,
		10323	"encoder's computed active state doesn't match tracked active state "
		10324	"(expected %i, found %i)\n", active, encoder->connectors_active);
		10325
		10326	active = encoder->get_hw_state(encoder, &pipe);
		10327	WARN(active != encoder->connectors_active,
		10328	"encoder's hw state doesn't match sw tracking "
		10329	"(expected %i, found %i)\n",
		10330	encoder->connectors_active, active);
		10331
		10332	if (!encoder->base.crtc)
		10333	continue;
		10334
		10335	tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		10336	WARN(active && pipe != tracked_pipe,
		10337	"active encoder's pipe doesn't match"
		10338	"(expected %i, found %i)\n",
		10339	tracked_pipe, pipe);
		10340
		10341	}
4104	Serge	10342	}
3031	serge	10343
4104	Serge	10344	static void
		10345	check_crtc_state(struct drm_device *dev)
		10346	{
5060	serge	10347	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	10348	struct intel_crtc *crtc;
		10349	struct intel_encoder *encoder;
		10350	struct intel_crtc_config pipe_config;
		10351
5060	serge	10352	for_each_intel_crtc(dev, crtc) {
3031	serge	10353	bool enabled = false;
		10354	bool active = false;
		10355
4104	Serge	10356	memset(&pipe_config, 0, sizeof(pipe_config));
		10357
3031	serge	10358	DRM_DEBUG_KMS("[CRTC:%d]\n",
		10359	crtc->base.base.id);
		10360
		10361	WARN(crtc->active && !crtc->base.enabled,
		10362	"active crtc, but not enabled in sw tracking\n");
		10363
		10364	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10365	base.head) {
		10366	if (encoder->base.crtc != &crtc->base)
		10367	continue;
		10368	enabled = true;
		10369	if (encoder->connectors_active)
		10370	active = true;
		10371	}
4104	Serge	10372
3031	serge	10373	WARN(active != crtc->active,
		10374	"crtc's computed active state doesn't match tracked active state "
		10375	"(expected %i, found %i)\n", active, crtc->active);
		10376	WARN(enabled != crtc->base.enabled,
		10377	"crtc's computed enabled state doesn't match tracked enabled state "
		10378	"(expected %i, found %i)\n", enabled, crtc->base.enabled);
		10379
3746	Serge	10380	active = dev_priv->display.get_pipe_config(crtc,
		10381	&pipe_config);
		10382
		10383	/* hw state is inconsistent with the pipe A quirk */
		10384	if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		10385	active = crtc->active;
		10386
4104	Serge	10387	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10388	base.head) {
		10389	enum pipe pipe;
		10390	if (encoder->base.crtc != &crtc->base)
		10391	continue;
4560	Serge	10392	if (encoder->get_hw_state(encoder, &pipe))
4104	Serge	10393	encoder->get_config(encoder, &pipe_config);
		10394	}
		10395
3746	Serge	10396	WARN(crtc->active != active,
		10397	"crtc active state doesn't match with hw state "
		10398	"(expected %i, found %i)\n", crtc->active, active);
		10399
4104	Serge	10400	if (active &&
		10401	!intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
		10402	WARN(1, "pipe state doesn't match!\n");
		10403	intel_dump_pipe_config(crtc, &pipe_config,
		10404	"[hw state]");
		10405	intel_dump_pipe_config(crtc, &crtc->config,
		10406	"[sw state]");
		10407	}
3031	serge	10408	}
		10409	}
		10410
4104	Serge	10411	static void
		10412	check_shared_dpll_state(struct drm_device *dev)
		10413	{
5060	serge	10414	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	10415	struct intel_crtc *crtc;
		10416	struct intel_dpll_hw_state dpll_hw_state;
		10417	int i;
		10418
		10419	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10420	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10421	int enabled_crtcs = 0, active_crtcs = 0;
		10422	bool active;
		10423
		10424	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
		10425
		10426	DRM_DEBUG_KMS("%s\n", pll->name);
		10427
		10428	active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
		10429
		10430	WARN(pll->active > pll->refcount,
		10431	"more active pll users than references: %i vs %i\n",
		10432	pll->active, pll->refcount);
		10433	WARN(pll->active && !pll->on,
		10434	"pll in active use but not on in sw tracking\n");
		10435	WARN(pll->on && !pll->active,
		10436	"pll in on but not on in use in sw tracking\n");
		10437	WARN(pll->on != active,
		10438	"pll on state mismatch (expected %i, found %i)\n",
		10439	pll->on, active);
		10440
5060	serge	10441	for_each_intel_crtc(dev, crtc) {
4104	Serge	10442	if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
		10443	enabled_crtcs++;
		10444	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		10445	active_crtcs++;
		10446	}
		10447	WARN(pll->active != active_crtcs,
		10448	"pll active crtcs mismatch (expected %i, found %i)\n",
		10449	pll->active, active_crtcs);
		10450	WARN(pll->refcount != enabled_crtcs,
		10451	"pll enabled crtcs mismatch (expected %i, found %i)\n",
		10452	pll->refcount, enabled_crtcs);
		10453
		10454	WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
		10455	sizeof(dpll_hw_state)),
		10456	"pll hw state mismatch\n");
		10457	}
		10458	}
		10459
		10460	void
		10461	intel_modeset_check_state(struct drm_device *dev)
		10462	{
		10463	check_connector_state(dev);
		10464	check_encoder_state(dev);
		10465	check_crtc_state(dev);
		10466	check_shared_dpll_state(dev);
		10467	}
		10468
4560	Serge	10469	void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
		10470	int dotclock)
		10471	{
		10472	/*
		10473	* FDI already provided one idea for the dotclock.
		10474	* Yell if the encoder disagrees.
		10475	*/
		10476	WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
		10477	"FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
		10478	pipe_config->adjusted_mode.crtc_clock, dotclock);
		10479	}
		10480
5060	serge	10481	static void update_scanline_offset(struct intel_crtc *crtc)
		10482	{
		10483	struct drm_device *dev = crtc->base.dev;
		10484
		10485	/*
		10486	* The scanline counter increments at the leading edge of hsync.
		10487	*
		10488	* On most platforms it starts counting from vtotal-1 on the
		10489	* first active line. That means the scanline counter value is
		10490	* always one less than what we would expect. Ie. just after
		10491	* start of vblank, which also occurs at start of hsync (on the
		10492	* last active line), the scanline counter will read vblank_start-1.
		10493	*
		10494	* On gen2 the scanline counter starts counting from 1 instead
		10495	* of vtotal-1, so we have to subtract one (or rather add vtotal-1
		10496	* to keep the value positive), instead of adding one.
		10497	*
		10498	* On HSW+ the behaviour of the scanline counter depends on the output
		10499	* type. For DP ports it behaves like most other platforms, but on HDMI
		10500	* there's an extra 1 line difference. So we need to add two instead of
		10501	* one to the value.
		10502	*/
		10503	if (IS_GEN2(dev)) {
		10504	const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
		10505	int vtotal;
		10506
		10507	vtotal = mode->crtc_vtotal;
		10508	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		10509	vtotal /= 2;
		10510
		10511	crtc->scanline_offset = vtotal - 1;
		10512	} else if (HAS_DDI(dev) &&
		10513	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
		10514	crtc->scanline_offset = 2;
		10515	} else
		10516	crtc->scanline_offset = 1;
		10517	}
		10518
3746	Serge	10519	static int __intel_set_mode(struct drm_crtc *crtc,
3031	serge	10520	struct drm_display_mode *mode,
		10521	int x, int y, struct drm_framebuffer *fb)
		10522	{
		10523	struct drm_device *dev = crtc->dev;
5060	serge	10524	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	10525	struct drm_display_mode *saved_mode;
3746	Serge	10526	struct intel_crtc_config *pipe_config = NULL;
3031	serge	10527	struct intel_crtc *intel_crtc;
		10528	unsigned disable_pipes, prepare_pipes, modeset_pipes;
3480	Serge	10529	int ret = 0;
3031	serge	10530
4560	Serge	10531	saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
3480	Serge	10532	if (!saved_mode)
		10533	return -ENOMEM;
		10534
3031	serge	10535	intel_modeset_affected_pipes(crtc, &modeset_pipes,
		10536	&prepare_pipes, &disable_pipes);
		10537
3480	Serge	10538	*saved_mode = crtc->mode;
3031	serge	10539
		10540	/* Hack: Because we don't (yet) support global modeset on multiple
		10541	* crtcs, we don't keep track of the new mode for more than one crtc.
		10542	* Hence simply check whether any bit is set in modeset_pipes in all the
		10543	* pieces of code that are not yet converted to deal with mutliple crtcs
		10544	* changing their mode at the same time. */
		10545	if (modeset_pipes) {
3746	Serge	10546	pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
		10547	if (IS_ERR(pipe_config)) {
		10548	ret = PTR_ERR(pipe_config);
		10549	pipe_config = NULL;
		10550
3480	Serge	10551	goto out;
3031	serge	10552	}
4104	Serge	10553	intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
		10554	"[modeset]");
5060	serge	10555	to_intel_crtc(crtc)->new_config = pipe_config;
3031	serge	10556	}
		10557
4560	Serge	10558	/*
		10559	* See if the config requires any additional preparation, e.g.
		10560	* to adjust global state with pipes off. We need to do this
		10561	* here so we can get the modeset_pipe updated config for the new
		10562	* mode set on this crtc. For other crtcs we need to use the
		10563	* adjusted_mode bits in the crtc directly.
		10564	*/
		10565	if (IS_VALLEYVIEW(dev)) {
5060	serge	10566	valleyview_modeset_global_pipes(dev, &prepare_pipes);
4560	Serge	10567
		10568	/* may have added more to prepare_pipes than we should */
		10569	prepare_pipes &= ~disable_pipes;
		10570	}
		10571
3746	Serge	10572	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		10573	intel_crtc_disable(&intel_crtc->base);
		10574
3031	serge	10575	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		10576	if (intel_crtc->base.enabled)
		10577	dev_priv->display.crtc_disable(&intel_crtc->base);
		10578	}
		10579
		10580	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
		10581	* to set it here already despite that we pass it down the callchain.
2330	Serge	10582	*/
3746	Serge	10583	if (modeset_pipes) {
3031	serge	10584	crtc->mode = *mode;
3746	Serge	10585	/* mode_set/enable/disable functions rely on a correct pipe
		10586	* config. */
		10587	to_intel_crtc(crtc)->config = *pipe_config;
5060	serge	10588	to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
4560	Serge	10589
		10590	/*
		10591	* Calculate and store various constants which
		10592	* are later needed by vblank and swap-completion
		10593	* timestamping. They are derived from true hwmode.
		10594	*/
		10595	drm_calc_timestamping_constants(crtc,
		10596	&pipe_config->adjusted_mode);
3746	Serge	10597	}
2327	Serge	10598
3031	serge	10599	/* Only after disabling all output pipelines that will be changed can we
		10600	* update the the output configuration. */
		10601	intel_modeset_update_state(dev, prepare_pipes);
		10602
3243	Serge	10603	if (dev_priv->display.modeset_global_resources)
		10604	dev_priv->display.modeset_global_resources(dev);
		10605
3031	serge	10606	/* Set up the DPLL and any encoders state that needs to adjust or depend
		10607	* on the DPLL.
2330	Serge	10608	*/
3031	serge	10609	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
5060	serge	10610	struct drm_framebuffer *old_fb = crtc->primary->fb;
		10611	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
		10612	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
		10613
		10614	mutex_lock(&dev->struct_mutex);
		10615	ret = intel_pin_and_fence_fb_obj(dev,
		10616	obj,
		10617	NULL);
		10618	if (ret != 0) {
		10619	DRM_ERROR("pin & fence failed\n");
		10620	mutex_unlock(&dev->struct_mutex);
		10621	goto done;
		10622	}
		10623	if (old_fb)
		10624	intel_unpin_fb_obj(old_obj);
		10625	i915_gem_track_fb(old_obj, obj,
		10626	INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
		10627	mutex_unlock(&dev->struct_mutex);
		10628
		10629	crtc->primary->fb = fb;
		10630	crtc->x = x;
		10631	crtc->y = y;
		10632
		10633	ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
3031	serge	10634	x, y, fb);
3480	Serge	10635	if (ret)
3031	serge	10636	goto done;
		10637	}
		10638
		10639	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
5060	serge	10640	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		10641	update_scanline_offset(intel_crtc);
		10642
3031	serge	10643	dev_priv->display.crtc_enable(&intel_crtc->base);
5060	serge	10644	}
3031	serge	10645
		10646	/* FIXME: add subpixel order */
		10647	done:
4560	Serge	10648	if (ret && crtc->enabled)
3480	Serge	10649	crtc->mode = *saved_mode;
3031	serge	10650
3480	Serge	10651	out:
3746	Serge	10652	kfree(pipe_config);
3480	Serge	10653	kfree(saved_mode);
3031	serge	10654	return ret;
2330	Serge	10655	}
2327	Serge	10656
4104	Serge	10657	static int intel_set_mode(struct drm_crtc *crtc,
3746	Serge	10658	struct drm_display_mode *mode,
		10659	int x, int y, struct drm_framebuffer *fb)
		10660	{
		10661	int ret;
		10662
		10663	ret = __intel_set_mode(crtc, mode, x, y, fb);
		10664
		10665	if (ret == 0)
		10666	intel_modeset_check_state(crtc->dev);
		10667
		10668	return ret;
		10669	}
		10670
3480	Serge	10671	void intel_crtc_restore_mode(struct drm_crtc *crtc)
		10672	{
5060	serge	10673	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
3480	Serge	10674	}
		10675
3031	serge	10676	#undef for_each_intel_crtc_masked
2327	Serge	10677
3031	serge	10678	static void intel_set_config_free(struct intel_set_config *config)
		10679	{
		10680	if (!config)
		10681	return;
		10682
		10683	kfree(config->save_connector_encoders);
		10684	kfree(config->save_encoder_crtcs);
5060	serge	10685	kfree(config->save_crtc_enabled);
3031	serge	10686	kfree(config);
		10687	}
		10688
		10689	static int intel_set_config_save_state(struct drm_device *dev,
		10690	struct intel_set_config *config)
		10691	{
5060	serge	10692	struct drm_crtc *crtc;
3031	serge	10693	struct drm_encoder *encoder;
		10694	struct drm_connector *connector;
		10695	int count;
		10696
5060	serge	10697	config->save_crtc_enabled =
		10698	kcalloc(dev->mode_config.num_crtc,
		10699	sizeof(bool), GFP_KERNEL);
		10700	if (!config->save_crtc_enabled)
		10701	return -ENOMEM;
		10702
3031	serge	10703	config->save_encoder_crtcs =
		10704	kcalloc(dev->mode_config.num_encoder,
		10705	sizeof(struct drm_crtc *), GFP_KERNEL);
		10706	if (!config->save_encoder_crtcs)
		10707	return -ENOMEM;
		10708
		10709	config->save_connector_encoders =
		10710	kcalloc(dev->mode_config.num_connector,
		10711	sizeof(struct drm_encoder *), GFP_KERNEL);
		10712	if (!config->save_connector_encoders)
		10713	return -ENOMEM;
		10714
		10715	/* Copy data. Note that driver private data is not affected.
		10716	* Should anything bad happen only the expected state is
		10717	* restored, not the drivers personal bookkeeping.
		10718	*/
		10719	count = 0;
5060	serge	10720	for_each_crtc(dev, crtc) {
		10721	config->save_crtc_enabled[count++] = crtc->enabled;
		10722	}
		10723
		10724	count = 0;
3031	serge	10725	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		10726	config->save_encoder_crtcs[count++] = encoder->crtc;
		10727	}
		10728
		10729	count = 0;
		10730	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		10731	config->save_connector_encoders[count++] = connector->encoder;
		10732	}
		10733
		10734	return 0;
		10735	}
		10736
		10737	static void intel_set_config_restore_state(struct drm_device *dev,
		10738	struct intel_set_config *config)
		10739	{
5060	serge	10740	struct intel_crtc *crtc;
3031	serge	10741	struct intel_encoder *encoder;
		10742	struct intel_connector *connector;
		10743	int count;
		10744
		10745	count = 0;
5060	serge	10746	for_each_intel_crtc(dev, crtc) {
		10747	crtc->new_enabled = config->save_crtc_enabled[count++];
		10748
		10749	if (crtc->new_enabled)
		10750	crtc->new_config = &crtc->config;
		10751	else
		10752	crtc->new_config = NULL;
		10753	}
		10754
		10755	count = 0;
3031	serge	10756	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		10757	encoder->new_crtc =
		10758	to_intel_crtc(config->save_encoder_crtcs[count++]);
		10759	}
		10760
		10761	count = 0;
		10762	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		10763	connector->new_encoder =
		10764	to_intel_encoder(config->save_connector_encoders[count++]);
		10765	}
		10766	}
		10767
3746	Serge	10768	static bool
4104	Serge	10769	is_crtc_connector_off(struct drm_mode_set *set)
3746	Serge	10770	{
		10771	int i;
		10772
4104	Serge	10773	if (set->num_connectors == 0)
		10774	return false;
		10775
		10776	if (WARN_ON(set->connectors == NULL))
		10777	return false;
		10778
		10779	for (i = 0; i < set->num_connectors; i++)
		10780	if (set->connectors[i]->encoder &&
		10781	set->connectors[i]->encoder->crtc == set->crtc &&
		10782	set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
3746	Serge	10783	return true;
		10784
		10785	return false;
		10786	}
		10787
3031	serge	10788	static void
		10789	intel_set_config_compute_mode_changes(struct drm_mode_set *set,
		10790	struct intel_set_config *config)
		10791	{
		10792
		10793	/* We should be able to check here if the fb has the same properties
		10794	* and then just flip_or_move it */
4104	Serge	10795	if (is_crtc_connector_off(set)) {
3746	Serge	10796	config->mode_changed = true;
5060	serge	10797	} else if (set->crtc->primary->fb != set->fb) {
		10798	/*
		10799	* If we have no fb, we can only flip as long as the crtc is
		10800	* active, otherwise we need a full mode set. The crtc may
		10801	* be active if we've only disabled the primary plane, or
		10802	* in fastboot situations.
		10803	*/
		10804	if (set->crtc->primary->fb == NULL) {
4104	Serge	10805	struct intel_crtc *intel_crtc =
		10806	to_intel_crtc(set->crtc);
		10807
5060	serge	10808	if (intel_crtc->active) {
4104	Serge	10809	DRM_DEBUG_KMS("crtc has no fb, will flip\n");
		10810	config->fb_changed = true;
		10811	} else {
		10812	DRM_DEBUG_KMS("inactive crtc, full mode set\n");
3031	serge	10813	config->mode_changed = true;
4104	Serge	10814	}
3031	serge	10815	} else if (set->fb == NULL) {
		10816	config->mode_changed = true;
3746	Serge	10817	} else if (set->fb->pixel_format !=
5060	serge	10818	set->crtc->primary->fb->pixel_format) {
3031	serge	10819	config->mode_changed = true;
3746	Serge	10820	} else {
3031	serge	10821	config->fb_changed = true;
		10822	}
3746	Serge	10823	}
3031	serge	10824
		10825	if (set->fb && (set->x != set->crtc->x \|\| set->y != set->crtc->y))
		10826	config->fb_changed = true;
		10827
		10828	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		10829	DRM_DEBUG_KMS("modes are different, full mode set\n");
		10830	drm_mode_debug_printmodeline(&set->crtc->mode);
		10831	drm_mode_debug_printmodeline(set->mode);
		10832	config->mode_changed = true;
		10833	}
4104	Serge	10834
		10835	DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
		10836	set->crtc->base.id, config->mode_changed, config->fb_changed);
3031	serge	10837	}
		10838
		10839	static int
		10840	intel_modeset_stage_output_state(struct drm_device *dev,
		10841	struct drm_mode_set *set,
		10842	struct intel_set_config *config)
		10843	{
		10844	struct intel_connector *connector;
		10845	struct intel_encoder *encoder;
5060	serge	10846	struct intel_crtc *crtc;
4104	Serge	10847	int ro;
3031	serge	10848
3480	Serge	10849	/* The upper layers ensure that we either disable a crtc or have a list
3031	serge	10850	* of connectors. For paranoia, double-check this. */
		10851	WARN_ON(!set->fb && (set->num_connectors != 0));
		10852	WARN_ON(set->fb && (set->num_connectors == 0));
		10853
		10854	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10855	base.head) {
		10856	/* Otherwise traverse passed in connector list and get encoders
		10857	* for them. */
		10858	for (ro = 0; ro < set->num_connectors; ro++) {
		10859	if (set->connectors[ro] == &connector->base) {
5060	serge	10860	connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
3031	serge	10861	break;
		10862	}
		10863	}
		10864
		10865	/* If we disable the crtc, disable all its connectors. Also, if
		10866	* the connector is on the changing crtc but not on the new
		10867	* connector list, disable it. */
		10868	if ((!set->fb \|\| ro == set->num_connectors) &&
		10869	connector->base.encoder &&
		10870	connector->base.encoder->crtc == set->crtc) {
		10871	connector->new_encoder = NULL;
		10872
		10873	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
		10874	connector->base.base.id,
5060	serge	10875	connector->base.name);
3031	serge	10876	}
		10877
		10878
		10879	if (&connector->new_encoder->base != connector->base.encoder) {
		10880	DRM_DEBUG_KMS("encoder changed, full mode switch\n");
		10881	config->mode_changed = true;
		10882	}
		10883	}
		10884	/* connector->new_encoder is now updated for all connectors. */
		10885
		10886	/* Update crtc of enabled connectors. */
		10887	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10888	base.head) {
5060	serge	10889	struct drm_crtc *new_crtc;
		10890
3031	serge	10891	if (!connector->new_encoder)
		10892	continue;
		10893
		10894	new_crtc = connector->new_encoder->base.crtc;
		10895
		10896	for (ro = 0; ro < set->num_connectors; ro++) {
		10897	if (set->connectors[ro] == &connector->base)
		10898	new_crtc = set->crtc;
		10899	}
		10900
		10901	/* Make sure the new CRTC will work with the encoder */
4560	Serge	10902	if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
3031	serge	10903	new_crtc)) {
		10904	return -EINVAL;
		10905	}
5060	serge	10906	connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
3031	serge	10907
		10908	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
		10909	connector->base.base.id,
5060	serge	10910	connector->base.name,
3031	serge	10911	new_crtc->base.id);
		10912	}
		10913
		10914	/* Check for any encoders that needs to be disabled. */
		10915	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10916	base.head) {
4560	Serge	10917	int num_connectors = 0;
3031	serge	10918	list_for_each_entry(connector,
		10919	&dev->mode_config.connector_list,
		10920	base.head) {
		10921	if (connector->new_encoder == encoder) {
		10922	WARN_ON(!connector->new_encoder->new_crtc);
4560	Serge	10923	num_connectors++;
3031	serge	10924	}
		10925	}
4560	Serge	10926
		10927	if (num_connectors == 0)
3031	serge	10928	encoder->new_crtc = NULL;
4560	Serge	10929	else if (num_connectors > 1)
		10930	return -EINVAL;
		10931
3031	serge	10932	/* Only now check for crtc changes so we don't miss encoders
		10933	* that will be disabled. */
		10934	if (&encoder->new_crtc->base != encoder->base.crtc) {
		10935	DRM_DEBUG_KMS("crtc changed, full mode switch\n");
		10936	config->mode_changed = true;
		10937	}
		10938	}
		10939	/* Now we've also updated encoder->new_crtc for all encoders. */
5060	serge	10940	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10941	base.head) {
		10942	if (connector->new_encoder)
		10943	if (connector->new_encoder != connector->encoder)
		10944	connector->encoder = connector->new_encoder;
		10945	}
		10946	for_each_intel_crtc(dev, crtc) {
		10947	crtc->new_enabled = false;
3031	serge	10948
5060	serge	10949	list_for_each_entry(encoder,
		10950	&dev->mode_config.encoder_list,
		10951	base.head) {
		10952	if (encoder->new_crtc == crtc) {
		10953	crtc->new_enabled = true;
		10954	break;
		10955	}
		10956	}
		10957
		10958	if (crtc->new_enabled != crtc->base.enabled) {
		10959	DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
		10960	crtc->new_enabled ? "en" : "dis");
		10961	config->mode_changed = true;
		10962	}
		10963
		10964	if (crtc->new_enabled)
		10965	crtc->new_config = &crtc->config;
		10966	else
		10967	crtc->new_config = NULL;
		10968	}
		10969
3031	serge	10970	return 0;
		10971	}
		10972
5060	serge	10973	static void disable_crtc_nofb(struct intel_crtc *crtc)
		10974	{
		10975	struct drm_device *dev = crtc->base.dev;
		10976	struct intel_encoder *encoder;
		10977	struct intel_connector *connector;
		10978
		10979	DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
		10980	pipe_name(crtc->pipe));
		10981
		10982	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		10983	if (connector->new_encoder &&
		10984	connector->new_encoder->new_crtc == crtc)
		10985	connector->new_encoder = NULL;
		10986	}
		10987
		10988	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		10989	if (encoder->new_crtc == crtc)
		10990	encoder->new_crtc = NULL;
		10991	}
		10992
		10993	crtc->new_enabled = false;
		10994	crtc->new_config = NULL;
		10995	}
		10996
3031	serge	10997	static int intel_crtc_set_config(struct drm_mode_set *set)
		10998	{
		10999	struct drm_device *dev;
		11000	struct drm_mode_set save_set;
		11001	struct intel_set_config *config;
		11002	int ret;
		11003
		11004	BUG_ON(!set);
		11005	BUG_ON(!set->crtc);
		11006	BUG_ON(!set->crtc->helper_private);
		11007
3480	Serge	11008	/* Enforce sane interface api - has been abused by the fb helper. */
		11009	BUG_ON(!set->mode && set->fb);
		11010	BUG_ON(set->fb && set->num_connectors == 0);
3031	serge	11011
		11012	if (set->fb) {
		11013	DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
		11014	set->crtc->base.id, set->fb->base.id,
		11015	(int)set->num_connectors, set->x, set->y);
		11016	} else {
		11017	DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
		11018	}
		11019
		11020	dev = set->crtc->dev;
		11021
		11022	ret = -ENOMEM;
		11023	config = kzalloc(sizeof(*config), GFP_KERNEL);
		11024	if (!config)
		11025	goto out_config;
		11026
		11027	ret = intel_set_config_save_state(dev, config);
		11028	if (ret)
		11029	goto out_config;
		11030
		11031	save_set.crtc = set->crtc;
		11032	save_set.mode = &set->crtc->mode;
		11033	save_set.x = set->crtc->x;
		11034	save_set.y = set->crtc->y;
5060	serge	11035	save_set.fb = set->crtc->primary->fb;
3031	serge	11036
		11037	/* Compute whether we need a full modeset, only an fb base update or no
		11038	* change at all. In the future we might also check whether only the
		11039	* mode changed, e.g. for LVDS where we only change the panel fitter in
		11040	* such cases. */
		11041	intel_set_config_compute_mode_changes(set, config);
		11042
		11043	ret = intel_modeset_stage_output_state(dev, set, config);
		11044	if (ret)
		11045	goto fail;
		11046
		11047	if (config->mode_changed) {
3480	Serge	11048	ret = intel_set_mode(set->crtc, set->mode,
		11049	set->x, set->y, set->fb);
3031	serge	11050	} else if (config->fb_changed) {
5060	serge	11051	struct drm_i915_private *dev_priv = dev->dev_private;
		11052	struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3746	Serge	11053
5060	serge	11054
3031	serge	11055	ret = intel_pipe_set_base(set->crtc,
		11056	set->x, set->y, set->fb);
5060	serge	11057
4560	Serge	11058	/*
5060	serge	11059	* We need to make sure the primary plane is re-enabled if it
		11060	* has previously been turned off.
		11061	*/
		11062	if (!intel_crtc->primary_enabled && ret == 0) {
		11063	WARN_ON(!intel_crtc->active);
		11064	intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
		11065	intel_crtc->pipe);
		11066	}
		11067
		11068	/*
4560	Serge	11069	* In the fastboot case this may be our only check of the
		11070	* state after boot. It would be better to only do it on
		11071	* the first update, but we don't have a nice way of doing that
		11072	* (and really, set_config isn't used much for high freq page
		11073	* flipping, so increasing its cost here shouldn't be a big
		11074	* deal).
		11075	*/
5060	serge	11076	if (i915.fastboot && ret == 0)
4560	Serge	11077	intel_modeset_check_state(set->crtc->dev);
3031	serge	11078	}
		11079
3746	Serge	11080	if (ret) {
4104	Serge	11081	DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
3746	Serge	11082	set->crtc->base.id, ret);
3031	serge	11083	fail:
		11084	intel_set_config_restore_state(dev, config);
		11085
5060	serge	11086	/*
		11087	* HACK: if the pipe was on, but we didn't have a framebuffer,
		11088	* force the pipe off to avoid oopsing in the modeset code
		11089	* due to fb==NULL. This should only happen during boot since
		11090	* we don't yet reconstruct the FB from the hardware state.
		11091	*/
		11092	if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
		11093	disable_crtc_nofb(to_intel_crtc(save_set.crtc));
		11094
3031	serge	11095	/* Try to restore the config */
		11096	if (config->mode_changed &&
3480	Serge	11097	intel_set_mode(save_set.crtc, save_set.mode,
3031	serge	11098	save_set.x, save_set.y, save_set.fb))
		11099	DRM_ERROR("failed to restore config after modeset failure\n");
3746	Serge	11100	}
3031	serge	11101
		11102	out_config:
		11103	intel_set_config_free(config);
		11104	return ret;
		11105	}
		11106
2330	Serge	11107	static const struct drm_crtc_funcs intel_crtc_funcs = {
		11108	.gamma_set = intel_crtc_gamma_set,
3031	serge	11109	.set_config = intel_crtc_set_config,
2330	Serge	11110	.destroy = intel_crtc_destroy,
		11111	// .page_flip = intel_crtc_page_flip,
		11112	};
2327	Serge	11113
4104	Serge	11114	static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
		11115	struct intel_shared_dpll *pll,
		11116	struct intel_dpll_hw_state *hw_state)
3031	serge	11117	{
4104	Serge	11118	uint32_t val;
3031	serge	11119
5060	serge	11120	if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
		11121	return false;
		11122
4104	Serge	11123	val = I915_READ(PCH_DPLL(pll->id));
		11124	hw_state->dpll = val;
		11125	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
		11126	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
		11127
		11128	return val & DPLL_VCO_ENABLE;
		11129	}
		11130
		11131	static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
		11132	struct intel_shared_dpll *pll)
		11133	{
		11134	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
		11135	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
		11136	}
		11137
		11138	static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
		11139	struct intel_shared_dpll *pll)
		11140	{
		11141	/* PCH refclock must be enabled first */
4560	Serge	11142	ibx_assert_pch_refclk_enabled(dev_priv);
4104	Serge	11143
		11144	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		11145
		11146	/* Wait for the clocks to stabilize. */
		11147	POSTING_READ(PCH_DPLL(pll->id));
		11148	udelay(150);
		11149
		11150	/* The pixel multiplier can only be updated once the
		11151	* DPLL is enabled and the clocks are stable.
		11152	*
		11153	* So write it again.
		11154	*/
		11155	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		11156	POSTING_READ(PCH_DPLL(pll->id));
		11157	udelay(200);
		11158	}
		11159
		11160	static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
		11161	struct intel_shared_dpll *pll)
		11162	{
		11163	struct drm_device *dev = dev_priv->dev;
		11164	struct intel_crtc *crtc;
		11165
		11166	/* Make sure no transcoder isn't still depending on us. */
5060	serge	11167	for_each_intel_crtc(dev, crtc) {
4104	Serge	11168	if (intel_crtc_to_shared_dpll(crtc) == pll)
		11169	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
3031	serge	11170	}
		11171
4104	Serge	11172	I915_WRITE(PCH_DPLL(pll->id), 0);
		11173	POSTING_READ(PCH_DPLL(pll->id));
		11174	udelay(200);
		11175	}
		11176
		11177	static char *ibx_pch_dpll_names[] = {
		11178	"PCH DPLL A",
		11179	"PCH DPLL B",
		11180	};
		11181
		11182	static void ibx_pch_dpll_init(struct drm_device *dev)
		11183	{
		11184	struct drm_i915_private *dev_priv = dev->dev_private;
		11185	int i;
		11186
		11187	dev_priv->num_shared_dpll = 2;
		11188
		11189	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		11190	dev_priv->shared_dplls[i].id = i;
		11191	dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
		11192	dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
		11193	dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
		11194	dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
		11195	dev_priv->shared_dplls[i].get_hw_state =
		11196	ibx_pch_dpll_get_hw_state;
3031	serge	11197	}
		11198	}
		11199
4104	Serge	11200	static void intel_shared_dpll_init(struct drm_device *dev)
		11201	{
		11202	struct drm_i915_private *dev_priv = dev->dev_private;
		11203
5060	serge	11204	if (HAS_DDI(dev))
		11205	intel_ddi_pll_init(dev);
		11206	else if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
4104	Serge	11207	ibx_pch_dpll_init(dev);
		11208	else
		11209	dev_priv->num_shared_dpll = 0;
		11210
		11211	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
		11212	}
		11213
5060	serge	11214	static int
		11215	intel_primary_plane_disable(struct drm_plane *plane)
		11216	{
		11217	struct drm_device *dev = plane->dev;
		11218	struct drm_i915_private *dev_priv = dev->dev_private;
		11219	struct intel_plane *intel_plane = to_intel_plane(plane);
		11220	struct intel_crtc *intel_crtc;
		11221
		11222	if (!plane->fb)
		11223	return 0;
		11224
		11225	BUG_ON(!plane->crtc);
		11226
		11227	intel_crtc = to_intel_crtc(plane->crtc);
		11228
		11229	/*
		11230	* Even though we checked plane->fb above, it's still possible that
		11231	* the primary plane has been implicitly disabled because the crtc
		11232	* coordinates given weren't visible, or because we detected
		11233	* that it was 100% covered by a sprite plane. Or, the CRTC may be
		11234	* off and we've set a fb, but haven't actually turned on the CRTC yet.
		11235	* In either case, we need to unpin the FB and let the fb pointer get
		11236	* updated, but otherwise we don't need to touch the hardware.
		11237	*/
		11238	if (!intel_crtc->primary_enabled)
		11239	goto disable_unpin;
		11240
		11241	intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
		11242	intel_plane->pipe);
		11243	disable_unpin:
		11244	mutex_lock(&dev->struct_mutex);
		11245	i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
		11246	INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
		11247	intel_unpin_fb_obj(intel_fb_obj(plane->fb));
		11248	mutex_unlock(&dev->struct_mutex);
		11249	plane->fb = NULL;
		11250
		11251	return 0;
		11252	}
		11253
		11254	static int
		11255	intel_primary_plane_setplane(struct drm_plane plane, struct drm_crtc crtc,
		11256	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		11257	unsigned int crtc_w, unsigned int crtc_h,
		11258	uint32_t src_x, uint32_t src_y,
		11259	uint32_t src_w, uint32_t src_h)
		11260	{
		11261	struct drm_device *dev = crtc->dev;
		11262	struct drm_i915_private *dev_priv = dev->dev_private;
		11263	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		11264	struct intel_plane *intel_plane = to_intel_plane(plane);
		11265	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
		11266	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
		11267	struct drm_rect dest = {
		11268	/* integer pixels */
		11269	.x1 = crtc_x,
		11270	.y1 = crtc_y,
		11271	.x2 = crtc_x + crtc_w,
		11272	.y2 = crtc_y + crtc_h,
		11273	};
		11274	struct drm_rect src = {
		11275	/* 16.16 fixed point */
		11276	.x1 = src_x,
		11277	.y1 = src_y,
		11278	.x2 = src_x + src_w,
		11279	.y2 = src_y + src_h,
		11280	};
		11281	const struct drm_rect clip = {
		11282	/* integer pixels */
		11283	.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
		11284	.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
		11285	};
		11286	bool visible;
		11287	int ret;
		11288
		11289	ret = drm_plane_helper_check_update(plane, crtc, fb,
		11290	&src, &dest, &clip,
		11291	DRM_PLANE_HELPER_NO_SCALING,
		11292	DRM_PLANE_HELPER_NO_SCALING,
		11293	false, true, &visible);
		11294
		11295	if (ret)
		11296	return ret;
		11297
		11298	/*
		11299	* If the CRTC isn't enabled, we're just pinning the framebuffer,
		11300	* updating the fb pointer, and returning without touching the
		11301	* hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
		11302	* turn on the display with all planes setup as desired.
		11303	*/
		11304	if (!crtc->enabled) {
		11305	mutex_lock(&dev->struct_mutex);
		11306
		11307	/*
		11308	* If we already called setplane while the crtc was disabled,
		11309	* we may have an fb pinned; unpin it.
		11310	*/
		11311	if (plane->fb)
		11312	intel_unpin_fb_obj(old_obj);
		11313
		11314	i915_gem_track_fb(old_obj, obj,
		11315	INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
		11316
		11317	/* Pin and return without programming hardware */
		11318	ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
		11319	mutex_unlock(&dev->struct_mutex);
		11320
		11321	return ret;
		11322	}
		11323
		11324
		11325	/*
		11326	* If clipping results in a non-visible primary plane, we'll disable
		11327	* the primary plane. Note that this is a bit different than what
		11328	* happens if userspace explicitly disables the plane by passing fb=0
		11329	* because plane->fb still gets set and pinned.
		11330	*/
		11331	if (!visible) {
		11332	mutex_lock(&dev->struct_mutex);
		11333
		11334	/*
		11335	* Try to pin the new fb first so that we can bail out if we
		11336	* fail.
		11337	*/
		11338	if (plane->fb != fb) {
		11339	ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
		11340	if (ret) {
		11341	mutex_unlock(&dev->struct_mutex);
		11342	return ret;
		11343	}
		11344	}
		11345
		11346	i915_gem_track_fb(old_obj, obj,
		11347	INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
		11348
		11349	if (intel_crtc->primary_enabled)
		11350	intel_disable_primary_hw_plane(dev_priv,
		11351	intel_plane->plane,
		11352	intel_plane->pipe);
		11353
		11354
		11355	if (plane->fb != fb)
		11356	if (plane->fb)
		11357	intel_unpin_fb_obj(old_obj);
		11358
		11359	mutex_unlock(&dev->struct_mutex);
		11360
		11361	return 0;
		11362	}
		11363
		11364	ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
		11365	if (ret)
		11366	return ret;
		11367
		11368	if (!intel_crtc->primary_enabled)
		11369	intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
		11370	intel_crtc->pipe);
		11371
		11372	return 0;
		11373	}
		11374
		11375	/* Common destruction function for both primary and cursor planes */
		11376	static void intel_plane_destroy(struct drm_plane *plane)
		11377	{
		11378	struct intel_plane *intel_plane = to_intel_plane(plane);
		11379	drm_plane_cleanup(plane);
		11380	kfree(intel_plane);
		11381	}
		11382
		11383	static const struct drm_plane_funcs intel_primary_plane_funcs = {
		11384	.update_plane = intel_primary_plane_setplane,
		11385	.disable_plane = intel_primary_plane_disable,
		11386	.destroy = intel_plane_destroy,
		11387	};
		11388
		11389	static struct drm_plane intel_primary_plane_create(struct drm_device dev,
		11390	int pipe)
		11391	{
		11392	struct intel_plane *primary;
		11393	const uint32_t *intel_primary_formats;
		11394	int num_formats;
		11395
		11396	primary = kzalloc(sizeof(*primary), GFP_KERNEL);
		11397	if (primary == NULL)
		11398	return NULL;
		11399
		11400	primary->can_scale = false;
		11401	primary->max_downscale = 1;
		11402	primary->pipe = pipe;
		11403	primary->plane = pipe;
		11404	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
		11405	primary->plane = !pipe;
		11406
		11407	if (INTEL_INFO(dev)->gen <= 3) {
		11408	intel_primary_formats = intel_primary_formats_gen2;
		11409	num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
		11410	} else {
		11411	intel_primary_formats = intel_primary_formats_gen4;
		11412	num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
		11413	}
		11414
		11415	drm_universal_plane_init(dev, &primary->base, 0,
		11416	&intel_primary_plane_funcs,
		11417	intel_primary_formats, num_formats,
		11418	DRM_PLANE_TYPE_PRIMARY);
		11419	return &primary->base;
		11420	}
		11421
		11422	static int
		11423	intel_cursor_plane_disable(struct drm_plane *plane)
		11424	{
		11425	if (!plane->fb)
		11426	return 0;
		11427
		11428	BUG_ON(!plane->crtc);
		11429
		11430	return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
		11431	}
		11432
		11433	static int
		11434	intel_cursor_plane_update(struct drm_plane plane, struct drm_crtc crtc,
		11435	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		11436	unsigned int crtc_w, unsigned int crtc_h,
		11437	uint32_t src_x, uint32_t src_y,
		11438	uint32_t src_w, uint32_t src_h)
		11439	{
		11440	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		11441	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		11442	struct drm_i915_gem_object *obj = intel_fb->obj;
		11443	struct drm_rect dest = {
		11444	/* integer pixels */
		11445	.x1 = crtc_x,
		11446	.y1 = crtc_y,
		11447	.x2 = crtc_x + crtc_w,
		11448	.y2 = crtc_y + crtc_h,
		11449	};
		11450	struct drm_rect src = {
		11451	/* 16.16 fixed point */
		11452	.x1 = src_x,
		11453	.y1 = src_y,
		11454	.x2 = src_x + src_w,
		11455	.y2 = src_y + src_h,
		11456	};
		11457	const struct drm_rect clip = {
		11458	/* integer pixels */
		11459	.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
		11460	.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
		11461	};
		11462	bool visible;
		11463	int ret;
		11464
		11465	ret = drm_plane_helper_check_update(plane, crtc, fb,
		11466	&src, &dest, &clip,
		11467	DRM_PLANE_HELPER_NO_SCALING,
		11468	DRM_PLANE_HELPER_NO_SCALING,
		11469	true, true, &visible);
		11470	if (ret)
		11471	return ret;
		11472
		11473	crtc->cursor_x = crtc_x;
		11474	crtc->cursor_y = crtc_y;
		11475	if (fb != crtc->cursor->fb) {
		11476	return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
		11477	} else {
		11478	intel_crtc_update_cursor(crtc, visible);
		11479	return 0;
		11480	}
		11481	}
		11482	static const struct drm_plane_funcs intel_cursor_plane_funcs = {
		11483	.update_plane = intel_cursor_plane_update,
		11484	.disable_plane = intel_cursor_plane_disable,
		11485	.destroy = intel_plane_destroy,
		11486	};
		11487
		11488	static struct drm_plane intel_cursor_plane_create(struct drm_device dev,
		11489	int pipe)
		11490	{
		11491	struct intel_plane *cursor;
		11492
		11493	cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
		11494	if (cursor == NULL)
		11495	return NULL;
		11496
		11497	cursor->can_scale = false;
		11498	cursor->max_downscale = 1;
		11499	cursor->pipe = pipe;
		11500	cursor->plane = pipe;
		11501
		11502	drm_universal_plane_init(dev, &cursor->base, 0,
		11503	&intel_cursor_plane_funcs,
		11504	intel_cursor_formats,
		11505	ARRAY_SIZE(intel_cursor_formats),
		11506	DRM_PLANE_TYPE_CURSOR);
		11507	return &cursor->base;
		11508	}
		11509
2330	Serge	11510	static void intel_crtc_init(struct drm_device *dev, int pipe)
		11511	{
5060	serge	11512	struct drm_i915_private *dev_priv = dev->dev_private;
2330	Serge	11513	struct intel_crtc *intel_crtc;
5060	serge	11514	struct drm_plane *primary = NULL;
		11515	struct drm_plane *cursor = NULL;
		11516	int i, ret;
2327	Serge	11517
4560	Serge	11518	intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
2330	Serge	11519	if (intel_crtc == NULL)
		11520	return;
2327	Serge	11521
5060	serge	11522	primary = intel_primary_plane_create(dev, pipe);
		11523	if (!primary)
		11524	goto fail;
2327	Serge	11525
5060	serge	11526	cursor = intel_cursor_plane_create(dev, pipe);
		11527	if (!cursor)
		11528	goto fail;
		11529
		11530	ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
		11531	cursor, &intel_crtc_funcs);
		11532	if (ret)
		11533	goto fail;
		11534
2330	Serge	11535	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		11536	for (i = 0; i < 256; i++) {
		11537	intel_crtc->lut_r[i] = i;
		11538	intel_crtc->lut_g[i] = i;
		11539	intel_crtc->lut_b[i] = i;
		11540	}
2327	Serge	11541
4560	Serge	11542	/*
		11543	* On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
5060	serge	11544	* is hooked to pipe B. Hence we want plane A feeding pipe B.
4560	Serge	11545	*/
2330	Serge	11546	intel_crtc->pipe = pipe;
		11547	intel_crtc->plane = pipe;
4560	Serge	11548	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
2330	Serge	11549	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		11550	intel_crtc->plane = !pipe;
		11551	}
2327	Serge	11552
5060	serge	11553	intel_crtc->cursor_base = ~0;
		11554	intel_crtc->cursor_cntl = ~0;
		11555
		11556	init_waitqueue_head(&intel_crtc->vbl_wait);
		11557
2330	Serge	11558	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		11559	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		11560	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		11561	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	11562
2330	Serge	11563	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5060	serge	11564
		11565	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
		11566	return;
		11567
		11568	fail:
		11569	if (primary)
		11570	drm_plane_cleanup(primary);
		11571	if (cursor)
		11572	drm_plane_cleanup(cursor);
		11573	kfree(intel_crtc);
2330	Serge	11574	}
2327	Serge	11575
4560	Serge	11576	enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
		11577	{
		11578	struct drm_encoder *encoder = connector->base.encoder;
5060	serge	11579	struct drm_device *dev = connector->base.dev;
4560	Serge	11580
5060	serge	11581	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4560	Serge	11582
		11583	if (!encoder)
		11584	return INVALID_PIPE;
		11585
		11586	return to_intel_crtc(encoder->crtc)->pipe;
		11587	}
		11588
3031	serge	11589	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		11590	struct drm_file *file)
		11591	{
		11592	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5060	serge	11593	struct drm_crtc *drmmode_crtc;
3031	serge	11594	struct intel_crtc *crtc;
2327	Serge	11595
3482	Serge	11596	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		11597	return -ENODEV;
		11598
5060	serge	11599	drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
2327	Serge	11600
5060	serge	11601	if (!drmmode_crtc) {
3031	serge	11602	DRM_ERROR("no such CRTC id\n");
4560	Serge	11603	return -ENOENT;
3031	serge	11604	}
2327	Serge	11605
5060	serge	11606	crtc = to_intel_crtc(drmmode_crtc);
3031	serge	11607	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	11608
3031	serge	11609	return 0;
		11610	}
2327	Serge	11611
3031	serge	11612	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	11613	{
3031	serge	11614	struct drm_device *dev = encoder->base.dev;
		11615	struct intel_encoder *source_encoder;
2330	Serge	11616	int index_mask = 0;
		11617	int entry = 0;
2327	Serge	11618
3031	serge	11619	list_for_each_entry(source_encoder,
		11620	&dev->mode_config.encoder_list, base.head) {
5060	serge	11621	if (encoders_cloneable(encoder, source_encoder))
2330	Serge	11622	index_mask \|= (1 << entry);
3031	serge	11623
2330	Serge	11624	entry++;
		11625	}
2327	Serge	11626
2330	Serge	11627	return index_mask;
		11628	}
2327	Serge	11629
2330	Serge	11630	static bool has_edp_a(struct drm_device *dev)
		11631	{
		11632	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	11633
2330	Serge	11634	if (!IS_MOBILE(dev))
		11635	return false;
2327	Serge	11636
2330	Serge	11637	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		11638	return false;
2327	Serge	11639
5060	serge	11640	if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
2330	Serge	11641	return false;
2327	Serge	11642
2330	Serge	11643	return true;
		11644	}
2327	Serge	11645
4560	Serge	11646	const char *intel_output_name(int output)
		11647	{
		11648	static const char *names[] = {
		11649	[INTEL_OUTPUT_UNUSED] = "Unused",
		11650	[INTEL_OUTPUT_ANALOG] = "Analog",
		11651	[INTEL_OUTPUT_DVO] = "DVO",
		11652	[INTEL_OUTPUT_SDVO] = "SDVO",
		11653	[INTEL_OUTPUT_LVDS] = "LVDS",
		11654	[INTEL_OUTPUT_TVOUT] = "TV",
		11655	[INTEL_OUTPUT_HDMI] = "HDMI",
		11656	[INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
		11657	[INTEL_OUTPUT_EDP] = "eDP",
		11658	[INTEL_OUTPUT_DSI] = "DSI",
		11659	[INTEL_OUTPUT_UNKNOWN] = "Unknown",
		11660	};
		11661
		11662	if (output < 0 \|\| output >= ARRAY_SIZE(names) \|\| !names[output])
		11663	return "Invalid";
		11664
		11665	return names[output];
		11666	}
		11667
5060	serge	11668	static bool intel_crt_present(struct drm_device *dev)
		11669	{
		11670	struct drm_i915_private *dev_priv = dev->dev_private;
		11671
		11672	if (IS_ULT(dev))
		11673	return false;
		11674
		11675	if (IS_CHERRYVIEW(dev))
		11676	return false;
		11677
		11678	if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
		11679	return false;
		11680
		11681	return true;
		11682	}
		11683
2330	Serge	11684	static void intel_setup_outputs(struct drm_device *dev)
		11685	{
		11686	struct drm_i915_private *dev_priv = dev->dev_private;
		11687	struct intel_encoder *encoder;
		11688	bool dpd_is_edp = false;
2327	Serge	11689
4104	Serge	11690	intel_lvds_init(dev);
2327	Serge	11691
5060	serge	11692	if (intel_crt_present(dev))
2330	Serge	11693	intel_crt_init(dev);
2327	Serge	11694
3480	Serge	11695	if (HAS_DDI(dev)) {
2330	Serge	11696	int found;
2327	Serge	11697
3031	serge	11698	/* Haswell uses DDI functions to detect digital outputs */
		11699	found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		11700	/* DDI A only supports eDP */
		11701	if (found)
		11702	intel_ddi_init(dev, PORT_A);
		11703
		11704	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		11705	* register */
		11706	found = I915_READ(SFUSE_STRAP);
		11707
		11708	if (found & SFUSE_STRAP_DDIB_DETECTED)
		11709	intel_ddi_init(dev, PORT_B);
		11710	if (found & SFUSE_STRAP_DDIC_DETECTED)
		11711	intel_ddi_init(dev, PORT_C);
		11712	if (found & SFUSE_STRAP_DDID_DETECTED)
		11713	intel_ddi_init(dev, PORT_D);
		11714	} else if (HAS_PCH_SPLIT(dev)) {
		11715	int found;
4560	Serge	11716	dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
3031	serge	11717
3243	Serge	11718	if (has_edp_a(dev))
		11719	intel_dp_init(dev, DP_A, PORT_A);
		11720
3746	Serge	11721	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
2330	Serge	11722	/* PCH SDVOB multiplex with HDMIB */
3031	serge	11723	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	11724	if (!found)
3746	Serge	11725	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
2330	Serge	11726	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	11727	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	11728	}
2327	Serge	11729
3746	Serge	11730	if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
		11731	intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
2327	Serge	11732
3746	Serge	11733	if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
		11734	intel_hdmi_init(dev, PCH_HDMID, PORT_D);
2327	Serge	11735
2330	Serge	11736	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	11737	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	11738
3243	Serge	11739	if (I915_READ(PCH_DP_D) & DP_DETECTED)
3031	serge	11740	intel_dp_init(dev, PCH_DP_D, PORT_D);
		11741	} else if (IS_VALLEYVIEW(dev)) {
4560	Serge	11742	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
		11743	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
		11744	PORT_B);
		11745	if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
		11746	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
		11747	}
		11748
4104	Serge	11749	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
		11750	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
		11751	PORT_C);
3480	Serge	11752	if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
4560	Serge	11753	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
4104	Serge	11754	}
3243	Serge	11755
5060	serge	11756	if (IS_CHERRYVIEW(dev)) {
		11757	if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
		11758	intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
		11759	PORT_D);
		11760	if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
		11761	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
		11762	}
		11763	}
		11764
4560	Serge	11765	intel_dsi_init(dev);
2330	Serge	11766	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		11767	bool found = false;
2327	Serge	11768
3746	Serge	11769	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	11770	DRM_DEBUG_KMS("probing SDVOB\n");
3746	Serge	11771	found = intel_sdvo_init(dev, GEN3_SDVOB, true);
2330	Serge	11772	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		11773	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3746	Serge	11774	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
2330	Serge	11775	}
2327	Serge	11776
4104	Serge	11777	if (!found && SUPPORTS_INTEGRATED_DP(dev))
3031	serge	11778	intel_dp_init(dev, DP_B, PORT_B);
2330	Serge	11779	}
2327	Serge	11780
2330	Serge	11781	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	11782
3746	Serge	11783	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	11784	DRM_DEBUG_KMS("probing SDVOC\n");
3746	Serge	11785	found = intel_sdvo_init(dev, GEN3_SDVOC, false);
2330	Serge	11786	}
2327	Serge	11787
3746	Serge	11788	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
2327	Serge	11789
2330	Serge	11790	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		11791	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3746	Serge	11792	intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
2330	Serge	11793	}
4104	Serge	11794	if (SUPPORTS_INTEGRATED_DP(dev))
3031	serge	11795	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	11796	}
2327	Serge	11797
2330	Serge	11798	if (SUPPORTS_INTEGRATED_DP(dev) &&
4104	Serge	11799	(I915_READ(DP_D) & DP_DETECTED))
3031	serge	11800	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	11801	} else if (IS_GEN2(dev))
		11802	intel_dvo_init(dev);
2327	Serge	11803
		11804
5060	serge	11805	intel_edp_psr_init(dev);
		11806
2330	Serge	11807	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		11808	encoder->base.possible_crtcs = encoder->crtc_mask;
		11809	encoder->base.possible_clones =
3031	serge	11810	intel_encoder_clones(encoder);
2330	Serge	11811	}
2327	Serge	11812
3243	Serge	11813	intel_init_pch_refclk(dev);
		11814
		11815	drm_helper_move_panel_connectors_to_head(dev);
2330	Serge	11816	}
		11817
		11818
		11819
2335	Serge	11820	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		11821	// .destroy = intel_user_framebuffer_destroy,
		11822	// .create_handle = intel_user_framebuffer_create_handle,
		11823	};
2327	Serge	11824
5060	serge	11825	static int intel_framebuffer_init(struct drm_device *dev,
2335	Serge	11826	struct intel_framebuffer *intel_fb,
2342	Serge	11827	struct drm_mode_fb_cmd2 *mode_cmd,
2335	Serge	11828	struct drm_i915_gem_object *obj)
		11829	{
5060	serge	11830	int aligned_height;
4104	Serge	11831	int pitch_limit;
2335	Serge	11832	int ret;
2327	Serge	11833
4560	Serge	11834	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
		11835
3243	Serge	11836	if (obj->tiling_mode == I915_TILING_Y) {
		11837	DRM_DEBUG("hardware does not support tiling Y\n");
2335	Serge	11838	return -EINVAL;
3243	Serge	11839	}
2327	Serge	11840
3243	Serge	11841	if (mode_cmd->pitches[0] & 63) {
		11842	DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
		11843	mode_cmd->pitches[0]);
		11844	return -EINVAL;
		11845	}
		11846
4104	Serge	11847	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
		11848	pitch_limit = 32*1024;
		11849	} else if (INTEL_INFO(dev)->gen >= 4) {
		11850	if (obj->tiling_mode)
		11851	pitch_limit = 16*1024;
		11852	else
		11853	pitch_limit = 32*1024;
		11854	} else if (INTEL_INFO(dev)->gen >= 3) {
		11855	if (obj->tiling_mode)
		11856	pitch_limit = 8*1024;
		11857	else
		11858	pitch_limit = 16*1024;
		11859	} else
		11860	/* XXX DSPC is limited to 4k tiled */
		11861	pitch_limit = 8*1024;
		11862
		11863	if (mode_cmd->pitches[0] > pitch_limit) {
		11864	DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
		11865	obj->tiling_mode ? "tiled" : "linear",
		11866	mode_cmd->pitches[0], pitch_limit);
3243	Serge	11867	return -EINVAL;
		11868	}
		11869
		11870	if (obj->tiling_mode != I915_TILING_NONE &&
		11871	mode_cmd->pitches[0] != obj->stride) {
		11872	DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
		11873	mode_cmd->pitches[0], obj->stride);
2335	Serge	11874	return -EINVAL;
3243	Serge	11875	}
2327	Serge	11876
3243	Serge	11877	/* Reject formats not supported by any plane early. */
2342	Serge	11878	switch (mode_cmd->pixel_format) {
3243	Serge	11879	case DRM_FORMAT_C8:
2342	Serge	11880	case DRM_FORMAT_RGB565:
		11881	case DRM_FORMAT_XRGB8888:
3243	Serge	11882	case DRM_FORMAT_ARGB8888:
		11883	break;
		11884	case DRM_FORMAT_XRGB1555:
		11885	case DRM_FORMAT_ARGB1555:
		11886	if (INTEL_INFO(dev)->gen > 3) {
4104	Serge	11887	DRM_DEBUG("unsupported pixel format: %s\n",
		11888	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	11889	return -EINVAL;
		11890	}
		11891	break;
3031	serge	11892	case DRM_FORMAT_XBGR8888:
3243	Serge	11893	case DRM_FORMAT_ABGR8888:
2342	Serge	11894	case DRM_FORMAT_XRGB2101010:
		11895	case DRM_FORMAT_ARGB2101010:
3243	Serge	11896	case DRM_FORMAT_XBGR2101010:
		11897	case DRM_FORMAT_ABGR2101010:
		11898	if (INTEL_INFO(dev)->gen < 4) {
4104	Serge	11899	DRM_DEBUG("unsupported pixel format: %s\n",
		11900	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	11901	return -EINVAL;
		11902	}
2335	Serge	11903	break;
2342	Serge	11904	case DRM_FORMAT_YUYV:
		11905	case DRM_FORMAT_UYVY:
		11906	case DRM_FORMAT_YVYU:
		11907	case DRM_FORMAT_VYUY:
3243	Serge	11908	if (INTEL_INFO(dev)->gen < 5) {
4104	Serge	11909	DRM_DEBUG("unsupported pixel format: %s\n",
		11910	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	11911	return -EINVAL;
		11912	}
2342	Serge	11913	break;
2335	Serge	11914	default:
4104	Serge	11915	DRM_DEBUG("unsupported pixel format: %s\n",
		11916	drm_get_format_name(mode_cmd->pixel_format));
2335	Serge	11917	return -EINVAL;
		11918	}
2327	Serge	11919
3243	Serge	11920	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
		11921	if (mode_cmd->offsets[0] != 0)
		11922	return -EINVAL;
		11923
5060	serge	11924	aligned_height = intel_align_height(dev, mode_cmd->height,
		11925	obj->tiling_mode);
4560	Serge	11926	/* FIXME drm helper for size checks (especially planar formats)? */
		11927	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
		11928	return -EINVAL;
		11929
3480	Serge	11930	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		11931	intel_fb->obj = obj;
4560	Serge	11932	intel_fb->obj->framebuffer_references++;
3480	Serge	11933
2335	Serge	11934	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		11935	if (ret) {
		11936	DRM_ERROR("framebuffer init failed %d\n", ret);
		11937	return ret;
		11938	}
2327	Serge	11939
2335	Serge	11940	return 0;
		11941	}
2327	Serge	11942
4560	Serge	11943	#ifndef CONFIG_DRM_I915_FBDEV
		11944	static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
		11945	{
		11946	}
		11947	#endif
2327	Serge	11948
2360	Serge	11949	static const struct drm_mode_config_funcs intel_mode_funcs = {
4560	Serge	11950	.fb_create = NULL,
		11951	.output_poll_changed = intel_fbdev_output_poll_changed,
2360	Serge	11952	};
2327	Serge	11953
3031	serge	11954	/* Set up chip specific display functions */
		11955	static void intel_init_display(struct drm_device *dev)
		11956	{
		11957	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	11958
4104	Serge	11959	if (HAS_PCH_SPLIT(dev) \|\| IS_G4X(dev))
		11960	dev_priv->display.find_dpll = g4x_find_best_dpll;
5060	serge	11961	else if (IS_CHERRYVIEW(dev))
		11962	dev_priv->display.find_dpll = chv_find_best_dpll;
4104	Serge	11963	else if (IS_VALLEYVIEW(dev))
		11964	dev_priv->display.find_dpll = vlv_find_best_dpll;
		11965	else if (IS_PINEVIEW(dev))
		11966	dev_priv->display.find_dpll = pnv_find_best_dpll;
		11967	else
		11968	dev_priv->display.find_dpll = i9xx_find_best_dpll;
		11969
3480	Serge	11970	if (HAS_DDI(dev)) {
3746	Serge	11971	dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5060	serge	11972	dev_priv->display.get_plane_config = ironlake_get_plane_config;
3243	Serge	11973	dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
		11974	dev_priv->display.crtc_enable = haswell_crtc_enable;
		11975	dev_priv->display.crtc_disable = haswell_crtc_disable;
5060	serge	11976	dev_priv->display.off = ironlake_crtc_off;
		11977	dev_priv->display.update_primary_plane =
		11978	ironlake_update_primary_plane;
3243	Serge	11979	} else if (HAS_PCH_SPLIT(dev)) {
3746	Serge	11980	dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5060	serge	11981	dev_priv->display.get_plane_config = ironlake_get_plane_config;
3031	serge	11982	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		11983	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		11984	dev_priv->display.crtc_disable = ironlake_crtc_disable;
		11985	dev_priv->display.off = ironlake_crtc_off;
5060	serge	11986	dev_priv->display.update_primary_plane =
		11987	ironlake_update_primary_plane;
4104	Serge	11988	} else if (IS_VALLEYVIEW(dev)) {
		11989	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5060	serge	11990	dev_priv->display.get_plane_config = i9xx_get_plane_config;
4104	Serge	11991	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		11992	dev_priv->display.crtc_enable = valleyview_crtc_enable;
		11993	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		11994	dev_priv->display.off = i9xx_crtc_off;
5060	serge	11995	dev_priv->display.update_primary_plane =
		11996	i9xx_update_primary_plane;
3031	serge	11997	} else {
3746	Serge	11998	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5060	serge	11999	dev_priv->display.get_plane_config = i9xx_get_plane_config;
3031	serge	12000	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		12001	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		12002	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		12003	dev_priv->display.off = i9xx_crtc_off;
5060	serge	12004	dev_priv->display.update_primary_plane =
		12005	i9xx_update_primary_plane;
3031	serge	12006	}
2327	Serge	12007
3031	serge	12008	/* Returns the core display clock speed */
		12009	if (IS_VALLEYVIEW(dev))
		12010	dev_priv->display.get_display_clock_speed =
		12011	valleyview_get_display_clock_speed;
		12012	else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		12013	dev_priv->display.get_display_clock_speed =
		12014	i945_get_display_clock_speed;
		12015	else if (IS_I915G(dev))
		12016	dev_priv->display.get_display_clock_speed =
		12017	i915_get_display_clock_speed;
4104	Serge	12018	else if (IS_I945GM(dev) \|\| IS_845G(dev))
3031	serge	12019	dev_priv->display.get_display_clock_speed =
		12020	i9xx_misc_get_display_clock_speed;
4104	Serge	12021	else if (IS_PINEVIEW(dev))
		12022	dev_priv->display.get_display_clock_speed =
		12023	pnv_get_display_clock_speed;
3031	serge	12024	else if (IS_I915GM(dev))
		12025	dev_priv->display.get_display_clock_speed =
		12026	i915gm_get_display_clock_speed;
		12027	else if (IS_I865G(dev))
		12028	dev_priv->display.get_display_clock_speed =
		12029	i865_get_display_clock_speed;
		12030	else if (IS_I85X(dev))
		12031	dev_priv->display.get_display_clock_speed =
		12032	i855_get_display_clock_speed;
		12033	else /* 852, 830 */
		12034	dev_priv->display.get_display_clock_speed =
		12035	i830_get_display_clock_speed;
2327	Serge	12036
3031	serge	12037	if (HAS_PCH_SPLIT(dev)) {
		12038	if (IS_GEN5(dev)) {
		12039	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		12040	dev_priv->display.write_eld = ironlake_write_eld;
		12041	} else if (IS_GEN6(dev)) {
		12042	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		12043	dev_priv->display.write_eld = ironlake_write_eld;
5060	serge	12044	dev_priv->display.modeset_global_resources =
		12045	snb_modeset_global_resources;
3031	serge	12046	} else if (IS_IVYBRIDGE(dev)) {
		12047	/* FIXME: detect B0+ stepping and use auto training */
		12048	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		12049	dev_priv->display.write_eld = ironlake_write_eld;
3243	Serge	12050	dev_priv->display.modeset_global_resources =
		12051	ivb_modeset_global_resources;
4560	Serge	12052	} else if (IS_HASWELL(dev) \|\| IS_GEN8(dev)) {
3031	serge	12053	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		12054	dev_priv->display.write_eld = haswell_write_eld;
3480	Serge	12055	dev_priv->display.modeset_global_resources =
		12056	haswell_modeset_global_resources;
		12057	}
3031	serge	12058	} else if (IS_G4X(dev)) {
		12059	dev_priv->display.write_eld = g4x_write_eld;
4560	Serge	12060	} else if (IS_VALLEYVIEW(dev)) {
		12061	dev_priv->display.modeset_global_resources =
		12062	valleyview_modeset_global_resources;
		12063	dev_priv->display.write_eld = ironlake_write_eld;
3031	serge	12064	}
2327	Serge	12065
3031	serge	12066	/* Default just returns -ENODEV to indicate unsupported */
		12067	// dev_priv->display.queue_flip = intel_default_queue_flip;
2327	Serge	12068
		12069
		12070
		12071
4560	Serge	12072	intel_panel_init_backlight_funcs(dev);
3031	serge	12073	}
		12074
		12075	/*
		12076	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		12077	* resume, or other times. This quirk makes sure that's the case for
		12078	* affected systems.
		12079	*/
		12080	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	12081	{
		12082	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	12083
3031	serge	12084	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		12085	DRM_INFO("applying pipe a force quirk\n");
		12086	}
2327	Serge	12087
3031	serge	12088	/*
		12089	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		12090	*/
		12091	static void quirk_ssc_force_disable(struct drm_device *dev)
		12092	{
		12093	struct drm_i915_private *dev_priv = dev->dev_private;
		12094	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		12095	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	12096	}
2327	Serge	12097
3031	serge	12098	/*
		12099	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		12100	* brightness value
		12101	*/
		12102	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	12103	{
		12104	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	12105	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		12106	DRM_INFO("applying inverted panel brightness quirk\n");
		12107	}
2327	Serge	12108
5060	serge	12109	/* Some VBT's incorrectly indicate no backlight is present */
		12110	static void quirk_backlight_present(struct drm_device *dev)
		12111	{
		12112	struct drm_i915_private *dev_priv = dev->dev_private;
		12113	dev_priv->quirks \|= QUIRK_BACKLIGHT_PRESENT;
		12114	DRM_INFO("applying backlight present quirk\n");
		12115	}
		12116
3031	serge	12117	struct intel_quirk {
		12118	int device;
		12119	int subsystem_vendor;
		12120	int subsystem_device;
		12121	void (hook)(struct drm_device dev);
		12122	};
2327	Serge	12123
3031	serge	12124	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		12125	struct intel_dmi_quirk {
		12126	void (hook)(struct drm_device dev);
		12127	const struct dmi_system_id (*dmi_id_list)[];
		12128	};
2327	Serge	12129
3031	serge	12130	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		12131	{
		12132	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		12133	return 1;
2330	Serge	12134	}
2327	Serge	12135
3031	serge	12136	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		12137	{
		12138	.dmi_id_list = &(const struct dmi_system_id[]) {
		12139	{
		12140	.callback = intel_dmi_reverse_brightness,
		12141	.ident = "NCR Corporation",
		12142	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		12143	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		12144	},
		12145	},
		12146	{ } /* terminating entry */
		12147	},
		12148	.hook = quirk_invert_brightness,
		12149	},
		12150	};
2327	Serge	12151
3031	serge	12152	static struct intel_quirk intel_quirks[] = {
		12153	/* HP Mini needs pipe A force quirk (LP: #322104) */
		12154	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327	Serge	12155
3031	serge	12156	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		12157	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	12158
3031	serge	12159	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		12160	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	12161
3031	serge	12162	/* Lenovo U160 cannot use SSC on LVDS */
		12163	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	12164
3031	serge	12165	/* Sony Vaio Y cannot use SSC on LVDS */
		12166	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	12167
3031	serge	12168	/* Acer Aspire 5734Z must invert backlight brightness */
		12169	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
3480	Serge	12170
		12171	/* Acer/eMachines G725 */
		12172	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
		12173
		12174	/* Acer/eMachines e725 */
		12175	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
		12176
		12177	/* Acer/Packard Bell NCL20 */
		12178	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
		12179
		12180	/* Acer Aspire 4736Z */
		12181	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
5060	serge	12182
		12183	/* Acer Aspire 5336 */
		12184	{ 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
		12185
		12186	/* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
		12187	{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
		12188
		12189	/* Toshiba CB35 Chromebook (Celeron 2955U) */
		12190	{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
		12191
		12192	/* HP Chromebook 14 (Celeron 2955U) */
		12193	{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
3031	serge	12194	};
2327	Serge	12195
3031	serge	12196	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	12197	{
3031	serge	12198	struct pci_dev *d = dev->pdev;
		12199	int i;
2327	Serge	12200
3031	serge	12201	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		12202	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	12203
3031	serge	12204	if (d->device == q->device &&
		12205	(d->subsystem_vendor == q->subsystem_vendor \|\|
		12206	q->subsystem_vendor == PCI_ANY_ID) &&
		12207	(d->subsystem_device == q->subsystem_device \|\|
		12208	q->subsystem_device == PCI_ANY_ID))
		12209	q->hook(dev);
		12210	}
2330	Serge	12211	}
2327	Serge	12212
3031	serge	12213	/* Disable the VGA plane that we never use */
		12214	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	12215	{
		12216	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	12217	u8 sr1;
3480	Serge	12218	u32 vga_reg = i915_vgacntrl_reg(dev);
2327	Serge	12219
4560	Serge	12220	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		12221	outb(SR01, VGA_SR_INDEX);
		12222	sr1 = inb(VGA_SR_DATA);
		12223	outb(sr1 \| 1<<5, VGA_SR_DATA);
		12224	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
3031	serge	12225	udelay(300);
2327	Serge	12226
3031	serge	12227	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		12228	POSTING_READ(vga_reg);
2330	Serge	12229	}
		12230
3031	serge	12231	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	12232	{
3031	serge	12233	intel_prepare_ddi(dev);
2342	Serge	12234
5060	serge	12235	if (IS_VALLEYVIEW(dev))
		12236	vlv_update_cdclk(dev);
		12237
3031	serge	12238	intel_init_clock_gating(dev);
		12239
4560	Serge	12240	intel_reset_dpio(dev);
4398	Serge	12241
3482	Serge	12242	intel_enable_gt_powersave(dev);
2342	Serge	12243	}
		12244
4398	Serge	12245	void intel_modeset_suspend_hw(struct drm_device *dev)
		12246	{
		12247	intel_suspend_hw(dev);
		12248	}
		12249
3031	serge	12250	void intel_modeset_init(struct drm_device *dev)
2330	Serge	12251	{
3031	serge	12252	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	12253	int sprite, ret;
		12254	enum pipe pipe;
		12255	struct intel_crtc *crtc;
2330	Serge	12256
3031	serge	12257	drm_mode_config_init(dev);
2330	Serge	12258
3031	serge	12259	dev->mode_config.min_width = 0;
		12260	dev->mode_config.min_height = 0;
2330	Serge	12261
3031	serge	12262	dev->mode_config.preferred_depth = 24;
		12263	dev->mode_config.prefer_shadow = 1;
2330	Serge	12264
3031	serge	12265	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	12266
3031	serge	12267	intel_init_quirks(dev);
2330	Serge	12268
3031	serge	12269	intel_init_pm(dev);
2330	Serge	12270
3746	Serge	12271	if (INTEL_INFO(dev)->num_pipes == 0)
		12272	return;
		12273
3031	serge	12274	intel_init_display(dev);
2330	Serge	12275
3031	serge	12276	if (IS_GEN2(dev)) {
		12277	dev->mode_config.max_width = 2048;
		12278	dev->mode_config.max_height = 2048;
		12279	} else if (IS_GEN3(dev)) {
		12280	dev->mode_config.max_width = 4096;
		12281	dev->mode_config.max_height = 4096;
		12282	} else {
		12283	dev->mode_config.max_width = 8192;
		12284	dev->mode_config.max_height = 8192;
		12285	}
5060	serge	12286
		12287	if (IS_GEN2(dev)) {
		12288	dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
		12289	dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
		12290	} else {
		12291	dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
		12292	dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
		12293	}
		12294
3480	Serge	12295	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
2330	Serge	12296
3031	serge	12297	DRM_DEBUG_KMS("%d display pipe%s available.\n",
3746	Serge	12298	INTEL_INFO(dev)->num_pipes,
		12299	INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
2330	Serge	12300
5060	serge	12301	for_each_pipe(pipe) {
		12302	intel_crtc_init(dev, pipe);
		12303	for_each_sprite(pipe, sprite) {
		12304	ret = intel_plane_init(dev, pipe, sprite);
3031	serge	12305	if (ret)
4104	Serge	12306	DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
5060	serge	12307	pipe_name(pipe), sprite_name(pipe, sprite), ret);
3746	Serge	12308	}
2330	Serge	12309	}
		12310
4560	Serge	12311	intel_init_dpio(dev);
		12312	intel_reset_dpio(dev);
		12313
4104	Serge	12314	intel_shared_dpll_init(dev);
2330	Serge	12315
3031	serge	12316	/* Just disable it once at startup */
		12317	i915_disable_vga(dev);
		12318	intel_setup_outputs(dev);
3480	Serge	12319
		12320	/* Just in case the BIOS is doing something questionable. */
		12321	intel_disable_fbc(dev);
2330	Serge	12322
5060	serge	12323	drm_modeset_lock_all(dev);
		12324	intel_modeset_setup_hw_state(dev, false);
		12325	drm_modeset_unlock_all(dev);
		12326
		12327	for_each_intel_crtc(dev, crtc) {
		12328	if (!crtc->active)
		12329	continue;
		12330
		12331	/*
		12332	* Note that reserving the BIOS fb up front prevents us
		12333	* from stuffing other stolen allocations like the ring
		12334	* on top. This prevents some ugliness at boot time, and
		12335	* can even allow for smooth boot transitions if the BIOS
		12336	* fb is large enough for the active pipe configuration.
		12337	*/
		12338	if (dev_priv->display.get_plane_config) {
		12339	dev_priv->display.get_plane_config(crtc,
		12340	&crtc->plane_config);
		12341	/*
		12342	* If the fb is shared between multiple heads, we'll
		12343	* just get the first one.
		12344	*/
		12345	intel_find_plane_obj(crtc, &crtc->plane_config);
		12346	}
		12347	}
2330	Serge	12348	}
		12349
3031	serge	12350	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	12351	{
3031	serge	12352	struct intel_connector *connector;
		12353	struct drm_connector *crt = NULL;
		12354	struct intel_load_detect_pipe load_detect_temp;
5060	serge	12355	struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
2330	Serge	12356
3031	serge	12357	/* We can't just switch on the pipe A, we need to set things up with a
		12358	* proper mode and output configuration. As a gross hack, enable pipe A
		12359	* by enabling the load detect pipe once. */
		12360	list_for_each_entry(connector,
		12361	&dev->mode_config.connector_list,
		12362	base.head) {
		12363	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		12364	crt = &connector->base;
		12365	break;
2330	Serge	12366	}
		12367	}
		12368
3031	serge	12369	if (!crt)
		12370	return;
2330	Serge	12371
5060	serge	12372	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
3031	serge	12373	intel_release_load_detect_pipe(crt, &load_detect_temp);
2327	Serge	12374	}
		12375
3031	serge	12376	static bool
		12377	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	12378	{
3746	Serge	12379	struct drm_device *dev = crtc->base.dev;
		12380	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	12381	u32 reg, val;
2327	Serge	12382
3746	Serge	12383	if (INTEL_INFO(dev)->num_pipes == 1)
3031	serge	12384	return true;
2327	Serge	12385
3031	serge	12386	reg = DSPCNTR(!crtc->plane);
		12387	val = I915_READ(reg);
2327	Serge	12388
3031	serge	12389	if ((val & DISPLAY_PLANE_ENABLE) &&
		12390	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		12391	return false;
2327	Serge	12392
3031	serge	12393	return true;
2327	Serge	12394	}
		12395
3031	serge	12396	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	12397	{
3031	serge	12398	struct drm_device *dev = crtc->base.dev;
2327	Serge	12399	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	12400	u32 reg;
2327	Serge	12401
3031	serge	12402	/* Clear any frame start delays used for debugging left by the BIOS */
3746	Serge	12403	reg = PIPECONF(crtc->config.cpu_transcoder);
3031	serge	12404	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	12405
5060	serge	12406	/* restore vblank interrupts to correct state */
		12407	if (crtc->active)
		12408	drm_vblank_on(dev, crtc->pipe);
		12409	else
		12410	drm_vblank_off(dev, crtc->pipe);
		12411
3031	serge	12412	/* We need to sanitize the plane -> pipe mapping first because this will
		12413	* disable the crtc (and hence change the state) if it is wrong. Note
		12414	* that gen4+ has a fixed plane -> pipe mapping. */
		12415	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		12416	struct intel_connector *connector;
		12417	bool plane;
2327	Serge	12418
3031	serge	12419	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		12420	crtc->base.base.id);
2327	Serge	12421
3031	serge	12422	/* Pipe has the wrong plane attached and the plane is active.
		12423	* Temporarily change the plane mapping and disable everything
		12424	* ... */
		12425	plane = crtc->plane;
		12426	crtc->plane = !plane;
5060	serge	12427	crtc->primary_enabled = true;
3031	serge	12428	dev_priv->display.crtc_disable(&crtc->base);
		12429	crtc->plane = plane;
2342	Serge	12430
3031	serge	12431	/* ... and break all links. */
		12432	list_for_each_entry(connector, &dev->mode_config.connector_list,
		12433	base.head) {
		12434	if (connector->encoder->base.crtc != &crtc->base)
		12435	continue;
2327	Serge	12436
5060	serge	12437	connector->base.dpms = DRM_MODE_DPMS_OFF;
		12438	connector->base.encoder = NULL;
3031	serge	12439	}
5060	serge	12440	/* multiple connectors may have the same encoder:
		12441	* handle them and break crtc link separately */
		12442	list_for_each_entry(connector, &dev->mode_config.connector_list,
		12443	base.head)
		12444	if (connector->encoder->base.crtc == &crtc->base) {
		12445	connector->encoder->base.crtc = NULL;
		12446	connector->encoder->connectors_active = false;
		12447	}
2327	Serge	12448
3031	serge	12449	WARN_ON(crtc->active);
		12450	crtc->base.enabled = false;
		12451	}
2327	Serge	12452
3031	serge	12453	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		12454	crtc->pipe == PIPE_A && !crtc->active) {
		12455	/* BIOS forgot to enable pipe A, this mostly happens after
		12456	* resume. Force-enable the pipe to fix this, the update_dpms
		12457	* call below we restore the pipe to the right state, but leave
		12458	* the required bits on. */
		12459	intel_enable_pipe_a(dev);
		12460	}
2327	Serge	12461
3031	serge	12462	/* Adjust the state of the output pipe according to whether we
		12463	* have active connectors/encoders. */
		12464	intel_crtc_update_dpms(&crtc->base);
2327	Serge	12465
3031	serge	12466	if (crtc->active != crtc->base.enabled) {
		12467	struct intel_encoder *encoder;
2327	Serge	12468
3031	serge	12469	/* This can happen either due to bugs in the get_hw_state
		12470	* functions or because the pipe is force-enabled due to the
		12471	* pipe A quirk. */
		12472	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		12473	crtc->base.base.id,
		12474	crtc->base.enabled ? "enabled" : "disabled",
		12475	crtc->active ? "enabled" : "disabled");
2327	Serge	12476
3031	serge	12477	crtc->base.enabled = crtc->active;
2327	Serge	12478
3031	serge	12479	/* Because we only establish the connector -> encoder ->
		12480	* crtc links if something is active, this means the
		12481	* crtc is now deactivated. Break the links. connector
		12482	* -> encoder links are only establish when things are
		12483	* actually up, hence no need to break them. */
		12484	WARN_ON(crtc->active);
2327	Serge	12485
3031	serge	12486	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		12487	WARN_ON(encoder->connectors_active);
		12488	encoder->base.crtc = NULL;
		12489	}
		12490	}
5060	serge	12491
		12492	if (crtc->active \|\| IS_VALLEYVIEW(dev) \|\| INTEL_INFO(dev)->gen < 5) {
		12493	/*
		12494	* We start out with underrun reporting disabled to avoid races.
		12495	* For correct bookkeeping mark this on active crtcs.
		12496	*
		12497	* Also on gmch platforms we dont have any hardware bits to
		12498	* disable the underrun reporting. Which means we need to start
		12499	* out with underrun reporting disabled also on inactive pipes,
		12500	* since otherwise we'll complain about the garbage we read when
		12501	* e.g. coming up after runtime pm.
		12502	*
		12503	* No protection against concurrent access is required - at
		12504	* worst a fifo underrun happens which also sets this to false.
		12505	*/
		12506	crtc->cpu_fifo_underrun_disabled = true;
		12507	crtc->pch_fifo_underrun_disabled = true;
		12508
		12509	update_scanline_offset(crtc);
		12510	}
2327	Serge	12511	}
		12512
3031	serge	12513	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	12514	{
3031	serge	12515	struct intel_connector *connector;
		12516	struct drm_device *dev = encoder->base.dev;
2327	Serge	12517
3031	serge	12518	/* We need to check both for a crtc link (meaning that the
		12519	* encoder is active and trying to read from a pipe) and the
		12520	* pipe itself being active. */
		12521	bool has_active_crtc = encoder->base.crtc &&
		12522	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	12523
3031	serge	12524	if (encoder->connectors_active && !has_active_crtc) {
		12525	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		12526	encoder->base.base.id,
5060	serge	12527	encoder->base.name);
2327	Serge	12528
3031	serge	12529	/* Connector is active, but has no active pipe. This is
		12530	* fallout from our resume register restoring. Disable
		12531	* the encoder manually again. */
		12532	if (encoder->base.crtc) {
		12533	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		12534	encoder->base.base.id,
5060	serge	12535	encoder->base.name);
3031	serge	12536	encoder->disable(encoder);
5060	serge	12537	if (encoder->post_disable)
		12538	encoder->post_disable(encoder);
3031	serge	12539	}
5060	serge	12540	encoder->base.crtc = NULL;
		12541	encoder->connectors_active = false;
2327	Serge	12542
3031	serge	12543	/* Inconsistent output/port/pipe state happens presumably due to
		12544	* a bug in one of the get_hw_state functions. Or someplace else
		12545	* in our code, like the register restore mess on resume. Clamp
		12546	* things to off as a safer default. */
		12547	list_for_each_entry(connector,
		12548	&dev->mode_config.connector_list,
		12549	base.head) {
		12550	if (connector->encoder != encoder)
		12551	continue;
5060	serge	12552	connector->base.dpms = DRM_MODE_DPMS_OFF;
		12553	connector->base.encoder = NULL;
3031	serge	12554	}
		12555	}
		12556	/* Enabled encoders without active connectors will be fixed in
		12557	* the crtc fixup. */
2327	Serge	12558	}
		12559
5060	serge	12560	void i915_redisable_vga_power_on(struct drm_device *dev)
3746	Serge	12561	{
		12562	struct drm_i915_private *dev_priv = dev->dev_private;
		12563	u32 vga_reg = i915_vgacntrl_reg(dev);
		12564
5060	serge	12565	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
		12566	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
		12567	i915_disable_vga(dev);
		12568	}
		12569	}
		12570
		12571	void i915_redisable_vga(struct drm_device *dev)
		12572	{
		12573	struct drm_i915_private *dev_priv = dev->dev_private;
		12574
4104	Serge	12575	/* This function can be called both from intel_modeset_setup_hw_state or
		12576	* at a very early point in our resume sequence, where the power well
		12577	* structures are not yet restored. Since this function is at a very
		12578	* paranoid "someone might have enabled VGA while we were not looking"
		12579	* level, just check if the power well is enabled instead of trying to
		12580	* follow the "don't touch the power well if we don't need it" policy
		12581	* the rest of the driver uses. */
5060	serge	12582	if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
4104	Serge	12583	return;
		12584
5060	serge	12585	i915_redisable_vga_power_on(dev);
3746	Serge	12586	}
		12587
5060	serge	12588	static bool primary_get_hw_state(struct intel_crtc *crtc)
		12589	{
		12590	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		12591
		12592	if (!crtc->active)
		12593	return false;
		12594
		12595	return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
		12596	}
		12597
4104	Serge	12598	static void intel_modeset_readout_hw_state(struct drm_device *dev)
2332	Serge	12599	{
		12600	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	12601	enum pipe pipe;
		12602	struct intel_crtc *crtc;
		12603	struct intel_encoder *encoder;
		12604	struct intel_connector *connector;
4104	Serge	12605	int i;
2327	Serge	12606
5060	serge	12607	for_each_intel_crtc(dev, crtc) {
3746	Serge	12608	memset(&crtc->config, 0, sizeof(crtc->config));
2327	Serge	12609
5060	serge	12610	crtc->config.quirks \|= PIPE_CONFIG_QUIRK_INHERITED_MODE;
		12611
3746	Serge	12612	crtc->active = dev_priv->display.get_pipe_config(crtc,
		12613	&crtc->config);
2327	Serge	12614
3031	serge	12615	crtc->base.enabled = crtc->active;
5060	serge	12616	crtc->primary_enabled = primary_get_hw_state(crtc);
2330	Serge	12617
3031	serge	12618	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		12619	crtc->base.base.id,
		12620	crtc->active ? "enabled" : "disabled");
2339	Serge	12621	}
2332	Serge	12622
4104	Serge	12623	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		12624	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		12625
		12626	pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
		12627	pll->active = 0;
5060	serge	12628	for_each_intel_crtc(dev, crtc) {
4104	Serge	12629	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		12630	pll->active++;
		12631	}
		12632	pll->refcount = pll->active;
		12633
		12634	DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
		12635	pll->name, pll->refcount, pll->on);
5060	serge	12636
		12637	if (pll->refcount)
		12638	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
4104	Serge	12639	}
		12640
3031	serge	12641	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		12642	base.head) {
		12643	pipe = 0;
2332	Serge	12644
3031	serge	12645	if (encoder->get_hw_state(encoder, &pipe)) {
4104	Serge	12646	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		12647	encoder->base.crtc = &crtc->base;
		12648	encoder->get_config(encoder, &crtc->config);
3031	serge	12649	} else {
		12650	encoder->base.crtc = NULL;
		12651	}
2332	Serge	12652
3031	serge	12653	encoder->connectors_active = false;
4560	Serge	12654	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
3031	serge	12655	encoder->base.base.id,
5060	serge	12656	encoder->base.name,
3031	serge	12657	encoder->base.crtc ? "enabled" : "disabled",
4560	Serge	12658	pipe_name(pipe));
3031	serge	12659	}
2332	Serge	12660
3031	serge	12661	list_for_each_entry(connector, &dev->mode_config.connector_list,
		12662	base.head) {
		12663	if (connector->get_hw_state(connector)) {
		12664	connector->base.dpms = DRM_MODE_DPMS_ON;
		12665	connector->encoder->connectors_active = true;
		12666	connector->base.encoder = &connector->encoder->base;
		12667	} else {
		12668	connector->base.dpms = DRM_MODE_DPMS_OFF;
		12669	connector->base.encoder = NULL;
		12670	}
		12671	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		12672	connector->base.base.id,
5060	serge	12673	connector->base.name,
3031	serge	12674	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	12675	}
4104	Serge	12676	}
2332	Serge	12677
4104	Serge	12678	/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
		12679	* and i915 state tracking structures. */
		12680	void intel_modeset_setup_hw_state(struct drm_device *dev,
		12681	bool force_restore)
		12682	{
		12683	struct drm_i915_private *dev_priv = dev->dev_private;
		12684	enum pipe pipe;
		12685	struct intel_crtc *crtc;
		12686	struct intel_encoder *encoder;
		12687	int i;
		12688
		12689	intel_modeset_readout_hw_state(dev);
		12690
		12691	/*
		12692	* Now that we have the config, copy it to each CRTC struct
		12693	* Note that this could go away if we move to using crtc_config
		12694	* checking everywhere.
		12695	*/
5060	serge	12696	for_each_intel_crtc(dev, crtc) {
		12697	if (crtc->active && i915.fastboot) {
		12698	intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
4104	Serge	12699	DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
		12700	crtc->base.base.id);
		12701	drm_mode_debug_printmodeline(&crtc->base.mode);
		12702	}
		12703	}
		12704
3031	serge	12705	/* HW state is read out, now we need to sanitize this mess. */
		12706	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		12707	base.head) {
		12708	intel_sanitize_encoder(encoder);
2332	Serge	12709	}
		12710
3031	serge	12711	for_each_pipe(pipe) {
		12712	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		12713	intel_sanitize_crtc(crtc);
4104	Serge	12714	intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
2332	Serge	12715	}
		12716
4104	Serge	12717	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		12718	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		12719
		12720	if (!pll->on \|\| pll->active)
		12721	continue;
		12722
		12723	DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
		12724
		12725	pll->disable(dev_priv, pll);
		12726	pll->on = false;
		12727	}
		12728
4560	Serge	12729	if (HAS_PCH_SPLIT(dev))
		12730	ilk_wm_get_hw_state(dev);
		12731
3243	Serge	12732	if (force_restore) {
4560	Serge	12733	i915_redisable_vga(dev);
		12734
3746	Serge	12735	/*
		12736	* We need to use raw interfaces for restoring state to avoid
		12737	* checking (bogus) intermediate states.
		12738	*/
3243	Serge	12739	for_each_pipe(pipe) {
3746	Serge	12740	struct drm_crtc *crtc =
		12741	dev_priv->pipe_to_crtc_mapping[pipe];
		12742
		12743	__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
5060	serge	12744	crtc->primary->fb);
3243	Serge	12745	}
		12746	} else {
3031	serge	12747	intel_modeset_update_staged_output_state(dev);
3243	Serge	12748	}
2332	Serge	12749
3031	serge	12750	intel_modeset_check_state(dev);
2332	Serge	12751	}
		12752
3031	serge	12753	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	12754	{
5060	serge	12755	struct drm_crtc *c;
		12756	struct drm_i915_gem_object *obj;
		12757
		12758	mutex_lock(&dev->struct_mutex);
		12759	intel_init_gt_powersave(dev);
		12760	mutex_unlock(&dev->struct_mutex);
		12761
3031	serge	12762	intel_modeset_init_hw(dev);
2330	Serge	12763
3031	serge	12764	// intel_setup_overlay(dev);
2330	Serge	12765
5060	serge	12766	/*
		12767	* Make sure any fbs we allocated at startup are properly
		12768	* pinned & fenced. When we do the allocation it's too early
		12769	* for this.
		12770	*/
		12771	mutex_lock(&dev->struct_mutex);
		12772	for_each_crtc(dev, c) {
		12773	obj = intel_fb_obj(c->primary->fb);
		12774	if (obj == NULL)
		12775	continue;
		12776
		12777	if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
		12778	DRM_ERROR("failed to pin boot fb on pipe %d\n",
		12779	to_intel_crtc(c)->pipe);
		12780	drm_framebuffer_unreference(c->primary->fb);
		12781	c->primary->fb = NULL;
		12782	}
		12783	}
		12784	mutex_unlock(&dev->struct_mutex);
2330	Serge	12785	}
		12786
5060	serge	12787	void intel_connector_unregister(struct intel_connector *intel_connector)
		12788	{
		12789	struct drm_connector *connector = &intel_connector->base;
		12790
		12791	intel_panel_destroy_backlight(connector);
		12792	drm_connector_unregister(connector);
		12793	}
		12794
3031	serge	12795	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	12796	{
3031	serge	12797	#if 0
		12798	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	12799	struct drm_connector *connector;
2327	Serge	12800
4104	Serge	12801	/*
		12802	* Interrupts and polling as the first thing to avoid creating havoc.
		12803	* Too much stuff here (turning of rps, connectors, ...) would
		12804	* experience fancy races otherwise.
		12805	*/
		12806	drm_irq_uninstall(dev);
5060	serge	12807	intel_hpd_cancel_work(dev_priv);
		12808	dev_priv->pm._irqs_disabled = true;
		12809
4104	Serge	12810	/*
		12811	* Due to the hpd irq storm handling the hotplug work can re-arm the
		12812	* poll handlers. Hence disable polling after hpd handling is shut down.
		12813	*/
4560	Serge	12814	drm_kms_helper_poll_fini(dev);
4104	Serge	12815
3031	serge	12816	mutex_lock(&dev->struct_mutex);
2327	Serge	12817
4560	Serge	12818	intel_unregister_dsm_handler();
2327	Serge	12819
3031	serge	12820	intel_disable_fbc(dev);
2342	Serge	12821
3031	serge	12822	intel_disable_gt_powersave(dev);
2342	Serge	12823
3031	serge	12824	ironlake_teardown_rc6(dev);
2327	Serge	12825
3031	serge	12826	mutex_unlock(&dev->struct_mutex);
2327	Serge	12827
4104	Serge	12828	/* flush any delayed tasks or pending work */
		12829	flush_scheduled_work();
2327	Serge	12830
4560	Serge	12831	/* destroy the backlight and sysfs files before encoders/connectors */
		12832	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5060	serge	12833	struct intel_connector *intel_connector;
		12834
		12835	intel_connector = to_intel_connector(connector);
		12836	intel_connector->unregister(intel_connector);
4560	Serge	12837	}
2327	Serge	12838
3031	serge	12839	drm_mode_config_cleanup(dev);
5060	serge	12840
		12841	intel_cleanup_overlay(dev);
		12842
		12843	mutex_lock(&dev->struct_mutex);
		12844	intel_cleanup_gt_powersave(dev);
		12845	mutex_unlock(&dev->struct_mutex);
2327	Serge	12846	#endif
		12847	}
		12848
		12849	/*
3031	serge	12850	* Return which encoder is currently attached for connector.
2327	Serge	12851	*/
3031	serge	12852	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	12853	{
3031	serge	12854	return &intel_attached_encoder(connector)->base;
		12855	}
2327	Serge	12856
3031	serge	12857	void intel_connector_attach_encoder(struct intel_connector *connector,
		12858	struct intel_encoder *encoder)
		12859	{
		12860	connector->encoder = encoder;
		12861	drm_mode_connector_attach_encoder(&connector->base,
		12862	&encoder->base);
2327	Serge	12863	}
		12864
		12865	/*
3031	serge	12866	* set vga decode state - true == enable VGA decode
2327	Serge	12867	*/
3031	serge	12868	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	12869	{
2330	Serge	12870	struct drm_i915_private *dev_priv = dev->dev_private;
4539	Serge	12871	unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
3031	serge	12872	u16 gmch_ctrl;
2327	Serge	12873
5060	serge	12874	if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
		12875	DRM_ERROR("failed to read control word\n");
		12876	return -EIO;
		12877	}
		12878
		12879	if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
		12880	return 0;
		12881
3031	serge	12882	if (state)
		12883	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	12884	else
3031	serge	12885	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
5060	serge	12886
		12887	if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
		12888	DRM_ERROR("failed to write control word\n");
		12889	return -EIO;
		12890	}
		12891
3031	serge	12892	return 0;
2330	Serge	12893	}
		12894
3031	serge	12895	#ifdef CONFIG_DEBUG_FS
2327	Serge	12896
3031	serge	12897	struct intel_display_error_state {
4104	Serge	12898
		12899	u32 power_well_driver;
		12900
		12901	int num_transcoders;
		12902
3031	serge	12903	struct intel_cursor_error_state {
		12904	u32 control;
		12905	u32 position;
		12906	u32 base;
		12907	u32 size;
		12908	} cursor[I915_MAX_PIPES];
2327	Serge	12909
3031	serge	12910	struct intel_pipe_error_state {
4560	Serge	12911	bool power_domain_on;
3031	serge	12912	u32 source;
5060	serge	12913	u32 stat;
3031	serge	12914	} pipe[I915_MAX_PIPES];
2327	Serge	12915
3031	serge	12916	struct intel_plane_error_state {
		12917	u32 control;
		12918	u32 stride;
		12919	u32 size;
		12920	u32 pos;
		12921	u32 addr;
		12922	u32 surface;
		12923	u32 tile_offset;
		12924	} plane[I915_MAX_PIPES];
4104	Serge	12925
		12926	struct intel_transcoder_error_state {
4560	Serge	12927	bool power_domain_on;
4104	Serge	12928	enum transcoder cpu_transcoder;
		12929
		12930	u32 conf;
		12931
		12932	u32 htotal;
		12933	u32 hblank;
		12934	u32 hsync;
		12935	u32 vtotal;
		12936	u32 vblank;
		12937	u32 vsync;
		12938	} transcoder[4];
3031	serge	12939	};
2327	Serge	12940
3031	serge	12941	struct intel_display_error_state *
		12942	intel_display_capture_error_state(struct drm_device *dev)
		12943	{
5060	serge	12944	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	12945	struct intel_display_error_state *error;
4104	Serge	12946	int transcoders[] = {
		12947	TRANSCODER_A,
		12948	TRANSCODER_B,
		12949	TRANSCODER_C,
		12950	TRANSCODER_EDP,
		12951	};
3031	serge	12952	int i;
2327	Serge	12953
4104	Serge	12954	if (INTEL_INFO(dev)->num_pipes == 0)
		12955	return NULL;
		12956
4560	Serge	12957	error = kzalloc(sizeof(*error), GFP_ATOMIC);
3031	serge	12958	if (error == NULL)
		12959	return NULL;
2327	Serge	12960
4560	Serge	12961	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
4104	Serge	12962	error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
		12963
3031	serge	12964	for_each_pipe(i) {
4560	Serge	12965	error->pipe[i].power_domain_on =
5060	serge	12966	intel_display_power_enabled_unlocked(dev_priv,
		12967	POWER_DOMAIN_PIPE(i));
4560	Serge	12968	if (!error->pipe[i].power_domain_on)
		12969	continue;
		12970
3031	serge	12971	error->cursor[i].control = I915_READ(CURCNTR(i));
		12972	error->cursor[i].position = I915_READ(CURPOS(i));
		12973	error->cursor[i].base = I915_READ(CURBASE(i));
2327	Serge	12974
3031	serge	12975	error->plane[i].control = I915_READ(DSPCNTR(i));
		12976	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
3746	Serge	12977	if (INTEL_INFO(dev)->gen <= 3) {
3031	serge	12978	error->plane[i].size = I915_READ(DSPSIZE(i));
		12979	error->plane[i].pos = I915_READ(DSPPOS(i));
3746	Serge	12980	}
		12981	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3031	serge	12982	error->plane[i].addr = I915_READ(DSPADDR(i));
		12983	if (INTEL_INFO(dev)->gen >= 4) {
		12984	error->plane[i].surface = I915_READ(DSPSURF(i));
		12985	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		12986	}
2327	Serge	12987
3031	serge	12988	error->pipe[i].source = I915_READ(PIPESRC(i));
5060	serge	12989
		12990	if (HAS_GMCH_DISPLAY(dev))
		12991	error->pipe[i].stat = I915_READ(PIPESTAT(i));
3031	serge	12992	}
2327	Serge	12993
4104	Serge	12994	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
		12995	if (HAS_DDI(dev_priv->dev))
		12996	error->num_transcoders++; /* Account for eDP. */
		12997
		12998	for (i = 0; i < error->num_transcoders; i++) {
		12999	enum transcoder cpu_transcoder = transcoders[i];
		13000
4560	Serge	13001	error->transcoder[i].power_domain_on =
5060	serge	13002	intel_display_power_enabled_unlocked(dev_priv,
4560	Serge	13003	POWER_DOMAIN_TRANSCODER(cpu_transcoder));
		13004	if (!error->transcoder[i].power_domain_on)
		13005	continue;
		13006
4104	Serge	13007	error->transcoder[i].cpu_transcoder = cpu_transcoder;
		13008
		13009	error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
		13010	error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		13011	error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		13012	error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		13013	error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		13014	error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		13015	error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
		13016	}
		13017
3031	serge	13018	return error;
2330	Serge	13019	}
2327	Serge	13020
4104	Serge	13021	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		13022
3031	serge	13023	void
4104	Serge	13024	intel_display_print_error_state(struct drm_i915_error_state_buf *m,
3031	serge	13025	struct drm_device *dev,
		13026	struct intel_display_error_state *error)
2332	Serge	13027	{
3031	serge	13028	int i;
2330	Serge	13029
4104	Serge	13030	if (!error)
		13031	return;
		13032
		13033	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
4560	Serge	13034	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
4104	Serge	13035	err_printf(m, "PWR_WELL_CTL2: %08x\n",
		13036	error->power_well_driver);
3031	serge	13037	for_each_pipe(i) {
4104	Serge	13038	err_printf(m, "Pipe [%d]:\n", i);
4560	Serge	13039	err_printf(m, " Power: %s\n",
		13040	error->pipe[i].power_domain_on ? "on" : "off");
4104	Serge	13041	err_printf(m, " SRC: %08x\n", error->pipe[i].source);
5060	serge	13042	err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
2332	Serge	13043
4104	Serge	13044	err_printf(m, "Plane [%d]:\n", i);
		13045	err_printf(m, " CNTR: %08x\n", error->plane[i].control);
		13046	err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
3746	Serge	13047	if (INTEL_INFO(dev)->gen <= 3) {
4104	Serge	13048	err_printf(m, " SIZE: %08x\n", error->plane[i].size);
		13049	err_printf(m, " POS: %08x\n", error->plane[i].pos);
3746	Serge	13050	}
		13051	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
4104	Serge	13052	err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
3031	serge	13053	if (INTEL_INFO(dev)->gen >= 4) {
4104	Serge	13054	err_printf(m, " SURF: %08x\n", error->plane[i].surface);
		13055	err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
3031	serge	13056	}
2332	Serge	13057
4104	Serge	13058	err_printf(m, "Cursor [%d]:\n", i);
		13059	err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		13060	err_printf(m, " POS: %08x\n", error->cursor[i].position);
		13061	err_printf(m, " BASE: %08x\n", error->cursor[i].base);
3031	serge	13062	}
4104	Serge	13063
		13064	for (i = 0; i < error->num_transcoders; i++) {
4560	Serge	13065	err_printf(m, "CPU transcoder: %c\n",
4104	Serge	13066	transcoder_name(error->transcoder[i].cpu_transcoder));
4560	Serge	13067	err_printf(m, " Power: %s\n",
		13068	error->transcoder[i].power_domain_on ? "on" : "off");
4104	Serge	13069	err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
		13070	err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
		13071	err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
		13072	err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
		13073	err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
		13074	err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
		13075	err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
		13076	}
2327	Serge	13077	}
3031	serge	13078	#endif

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(root)/drivers/video/drm/i915/intel_display.c – Rev 5060