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2327 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | */ |
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26 | |||
3746 | Serge | 27 | //#include |
2327 | Serge | 28 | #include |
29 | //#include |
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30 | #include |
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31 | #include |
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2330 | Serge | 32 | #include |
3746 | Serge | 33 | #include |
2342 | Serge | 34 | #include |
3031 | serge | 35 | #include |
2327 | Serge | 36 | #include "intel_drv.h" |
3031 | serge | 37 | #include |
2327 | Serge | 38 | #include "i915_drv.h" |
2351 | Serge | 39 | #include "i915_trace.h" |
3031 | serge | 40 | #include |
41 | #include |
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42 | //#include |
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2327 | Serge | 43 | |
4104 | Serge | 44 | #define MAX_ERRNO 4095 |
2327 | Serge | 45 | phys_addr_t get_bus_addr(void); |
46 | |||
2342 | Serge | 47 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
2327 | Serge | 48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
3243 | Serge | 49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
2327 | Serge | 50 | |
4104 | Serge | 51 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
52 | struct intel_crtc_config *pipe_config); |
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53 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
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54 | struct intel_crtc_config *pipe_config); |
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2327 | Serge | 55 | |
4104 | Serge | 56 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
57 | int x, int y, struct drm_framebuffer *old_fb); |
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58 | |||
59 | |||
2327 | Serge | 60 | typedef struct { |
61 | int min, max; |
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62 | } intel_range_t; |
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63 | |||
64 | typedef struct { |
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65 | int dot_limit; |
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66 | int p2_slow, p2_fast; |
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67 | } intel_p2_t; |
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68 | |||
69 | typedef struct intel_limit intel_limit_t; |
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70 | struct intel_limit { |
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71 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
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72 | intel_p2_t p2; |
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73 | }; |
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74 | |||
75 | /* FDI */ |
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76 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
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77 | |||
3243 | Serge | 78 | int |
79 | intel_pch_rawclk(struct drm_device *dev) |
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80 | { |
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81 | struct drm_i915_private *dev_priv = dev->dev_private; |
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82 | |||
83 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
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84 | |||
85 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
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86 | } |
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87 | |||
2327 | Serge | 88 | static inline u32 /* units of 100MHz */ |
89 | intel_fdi_link_freq(struct drm_device *dev) |
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90 | { |
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91 | if (IS_GEN5(dev)) { |
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92 | struct drm_i915_private *dev_priv = dev->dev_private; |
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93 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
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94 | } else |
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95 | return 27; |
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96 | } |
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97 | |||
4104 | Serge | 98 | static const intel_limit_t intel_limits_i8xx_dac = { |
99 | .dot = { .min = 25000, .max = 350000 }, |
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100 | .vco = { .min = 930000, .max = 1400000 }, |
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101 | .n = { .min = 3, .max = 16 }, |
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102 | .m = { .min = 96, .max = 140 }, |
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103 | .m1 = { .min = 18, .max = 26 }, |
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104 | .m2 = { .min = 6, .max = 16 }, |
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105 | .p = { .min = 4, .max = 128 }, |
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106 | .p1 = { .min = 2, .max = 33 }, |
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107 | .p2 = { .dot_limit = 165000, |
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108 | .p2_slow = 4, .p2_fast = 2 }, |
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109 | }; |
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110 | |||
2327 | Serge | 111 | static const intel_limit_t intel_limits_i8xx_dvo = { |
112 | .dot = { .min = 25000, .max = 350000 }, |
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113 | .vco = { .min = 930000, .max = 1400000 }, |
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114 | .n = { .min = 3, .max = 16 }, |
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115 | .m = { .min = 96, .max = 140 }, |
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116 | .m1 = { .min = 18, .max = 26 }, |
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117 | .m2 = { .min = 6, .max = 16 }, |
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118 | .p = { .min = 4, .max = 128 }, |
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119 | .p1 = { .min = 2, .max = 33 }, |
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120 | .p2 = { .dot_limit = 165000, |
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4104 | Serge | 121 | .p2_slow = 4, .p2_fast = 4 }, |
2327 | Serge | 122 | }; |
123 | |||
124 | static const intel_limit_t intel_limits_i8xx_lvds = { |
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125 | .dot = { .min = 25000, .max = 350000 }, |
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126 | .vco = { .min = 930000, .max = 1400000 }, |
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127 | .n = { .min = 3, .max = 16 }, |
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128 | .m = { .min = 96, .max = 140 }, |
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129 | .m1 = { .min = 18, .max = 26 }, |
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130 | .m2 = { .min = 6, .max = 16 }, |
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131 | .p = { .min = 4, .max = 128 }, |
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132 | .p1 = { .min = 1, .max = 6 }, |
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133 | .p2 = { .dot_limit = 165000, |
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134 | .p2_slow = 14, .p2_fast = 7 }, |
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135 | }; |
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136 | |||
137 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
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138 | .dot = { .min = 20000, .max = 400000 }, |
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139 | .vco = { .min = 1400000, .max = 2800000 }, |
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140 | .n = { .min = 1, .max = 6 }, |
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141 | .m = { .min = 70, .max = 120 }, |
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3480 | Serge | 142 | .m1 = { .min = 8, .max = 18 }, |
143 | .m2 = { .min = 3, .max = 7 }, |
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2327 | Serge | 144 | .p = { .min = 5, .max = 80 }, |
145 | .p1 = { .min = 1, .max = 8 }, |
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146 | .p2 = { .dot_limit = 200000, |
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147 | .p2_slow = 10, .p2_fast = 5 }, |
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148 | }; |
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149 | |||
150 | static const intel_limit_t intel_limits_i9xx_lvds = { |
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151 | .dot = { .min = 20000, .max = 400000 }, |
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152 | .vco = { .min = 1400000, .max = 2800000 }, |
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153 | .n = { .min = 1, .max = 6 }, |
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154 | .m = { .min = 70, .max = 120 }, |
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3480 | Serge | 155 | .m1 = { .min = 8, .max = 18 }, |
156 | .m2 = { .min = 3, .max = 7 }, |
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2327 | Serge | 157 | .p = { .min = 7, .max = 98 }, |
158 | .p1 = { .min = 1, .max = 8 }, |
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159 | .p2 = { .dot_limit = 112000, |
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160 | .p2_slow = 14, .p2_fast = 7 }, |
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161 | }; |
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162 | |||
163 | |||
164 | static const intel_limit_t intel_limits_g4x_sdvo = { |
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165 | .dot = { .min = 25000, .max = 270000 }, |
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166 | .vco = { .min = 1750000, .max = 3500000}, |
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167 | .n = { .min = 1, .max = 4 }, |
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168 | .m = { .min = 104, .max = 138 }, |
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169 | .m1 = { .min = 17, .max = 23 }, |
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170 | .m2 = { .min = 5, .max = 11 }, |
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171 | .p = { .min = 10, .max = 30 }, |
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172 | .p1 = { .min = 1, .max = 3}, |
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173 | .p2 = { .dot_limit = 270000, |
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174 | .p2_slow = 10, |
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175 | .p2_fast = 10 |
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176 | }, |
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177 | }; |
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178 | |||
179 | static const intel_limit_t intel_limits_g4x_hdmi = { |
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180 | .dot = { .min = 22000, .max = 400000 }, |
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181 | .vco = { .min = 1750000, .max = 3500000}, |
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182 | .n = { .min = 1, .max = 4 }, |
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183 | .m = { .min = 104, .max = 138 }, |
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184 | .m1 = { .min = 16, .max = 23 }, |
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185 | .m2 = { .min = 5, .max = 11 }, |
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186 | .p = { .min = 5, .max = 80 }, |
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187 | .p1 = { .min = 1, .max = 8}, |
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188 | .p2 = { .dot_limit = 165000, |
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189 | .p2_slow = 10, .p2_fast = 5 }, |
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190 | }; |
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191 | |||
192 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
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193 | .dot = { .min = 20000, .max = 115000 }, |
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194 | .vco = { .min = 1750000, .max = 3500000 }, |
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195 | .n = { .min = 1, .max = 3 }, |
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196 | .m = { .min = 104, .max = 138 }, |
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197 | .m1 = { .min = 17, .max = 23 }, |
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198 | .m2 = { .min = 5, .max = 11 }, |
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199 | .p = { .min = 28, .max = 112 }, |
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200 | .p1 = { .min = 2, .max = 8 }, |
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201 | .p2 = { .dot_limit = 0, |
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202 | .p2_slow = 14, .p2_fast = 14 |
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203 | }, |
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204 | }; |
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205 | |||
206 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
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207 | .dot = { .min = 80000, .max = 224000 }, |
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208 | .vco = { .min = 1750000, .max = 3500000 }, |
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209 | .n = { .min = 1, .max = 3 }, |
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210 | .m = { .min = 104, .max = 138 }, |
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211 | .m1 = { .min = 17, .max = 23 }, |
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212 | .m2 = { .min = 5, .max = 11 }, |
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213 | .p = { .min = 14, .max = 42 }, |
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214 | .p1 = { .min = 2, .max = 6 }, |
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215 | .p2 = { .dot_limit = 0, |
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216 | .p2_slow = 7, .p2_fast = 7 |
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217 | }, |
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218 | }; |
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219 | |||
220 | static const intel_limit_t intel_limits_pineview_sdvo = { |
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221 | .dot = { .min = 20000, .max = 400000}, |
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222 | .vco = { .min = 1700000, .max = 3500000 }, |
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223 | /* Pineview's Ncounter is a ring counter */ |
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224 | .n = { .min = 3, .max = 6 }, |
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225 | .m = { .min = 2, .max = 256 }, |
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226 | /* Pineview only has one combined m divider, which we treat as m2. */ |
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227 | .m1 = { .min = 0, .max = 0 }, |
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228 | .m2 = { .min = 0, .max = 254 }, |
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229 | .p = { .min = 5, .max = 80 }, |
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230 | .p1 = { .min = 1, .max = 8 }, |
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231 | .p2 = { .dot_limit = 200000, |
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232 | .p2_slow = 10, .p2_fast = 5 }, |
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233 | }; |
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234 | |||
235 | static const intel_limit_t intel_limits_pineview_lvds = { |
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236 | .dot = { .min = 20000, .max = 400000 }, |
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237 | .vco = { .min = 1700000, .max = 3500000 }, |
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238 | .n = { .min = 3, .max = 6 }, |
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239 | .m = { .min = 2, .max = 256 }, |
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240 | .m1 = { .min = 0, .max = 0 }, |
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241 | .m2 = { .min = 0, .max = 254 }, |
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242 | .p = { .min = 7, .max = 112 }, |
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243 | .p1 = { .min = 1, .max = 8 }, |
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244 | .p2 = { .dot_limit = 112000, |
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245 | .p2_slow = 14, .p2_fast = 14 }, |
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246 | }; |
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247 | |||
248 | /* Ironlake / Sandybridge |
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249 | * |
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250 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
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251 | * the range value for them is (actual_value - 2). |
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252 | */ |
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253 | static const intel_limit_t intel_limits_ironlake_dac = { |
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254 | .dot = { .min = 25000, .max = 350000 }, |
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255 | .vco = { .min = 1760000, .max = 3510000 }, |
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256 | .n = { .min = 1, .max = 5 }, |
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257 | .m = { .min = 79, .max = 127 }, |
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258 | .m1 = { .min = 12, .max = 22 }, |
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259 | .m2 = { .min = 5, .max = 9 }, |
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260 | .p = { .min = 5, .max = 80 }, |
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261 | .p1 = { .min = 1, .max = 8 }, |
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262 | .p2 = { .dot_limit = 225000, |
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263 | .p2_slow = 10, .p2_fast = 5 }, |
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264 | }; |
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265 | |||
266 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
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267 | .dot = { .min = 25000, .max = 350000 }, |
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268 | .vco = { .min = 1760000, .max = 3510000 }, |
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269 | .n = { .min = 1, .max = 3 }, |
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270 | .m = { .min = 79, .max = 118 }, |
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271 | .m1 = { .min = 12, .max = 22 }, |
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272 | .m2 = { .min = 5, .max = 9 }, |
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273 | .p = { .min = 28, .max = 112 }, |
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274 | .p1 = { .min = 2, .max = 8 }, |
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275 | .p2 = { .dot_limit = 225000, |
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276 | .p2_slow = 14, .p2_fast = 14 }, |
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277 | }; |
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278 | |||
279 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
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280 | .dot = { .min = 25000, .max = 350000 }, |
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281 | .vco = { .min = 1760000, .max = 3510000 }, |
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282 | .n = { .min = 1, .max = 3 }, |
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283 | .m = { .min = 79, .max = 127 }, |
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284 | .m1 = { .min = 12, .max = 22 }, |
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285 | .m2 = { .min = 5, .max = 9 }, |
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286 | .p = { .min = 14, .max = 56 }, |
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287 | .p1 = { .min = 2, .max = 8 }, |
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288 | .p2 = { .dot_limit = 225000, |
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289 | .p2_slow = 7, .p2_fast = 7 }, |
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290 | }; |
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291 | |||
292 | /* LVDS 100mhz refclk limits. */ |
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293 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
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294 | .dot = { .min = 25000, .max = 350000 }, |
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295 | .vco = { .min = 1760000, .max = 3510000 }, |
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296 | .n = { .min = 1, .max = 2 }, |
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297 | .m = { .min = 79, .max = 126 }, |
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298 | .m1 = { .min = 12, .max = 22 }, |
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299 | .m2 = { .min = 5, .max = 9 }, |
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300 | .p = { .min = 28, .max = 112 }, |
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2342 | Serge | 301 | .p1 = { .min = 2, .max = 8 }, |
2327 | Serge | 302 | .p2 = { .dot_limit = 225000, |
303 | .p2_slow = 14, .p2_fast = 14 }, |
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304 | }; |
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305 | |||
306 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
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307 | .dot = { .min = 25000, .max = 350000 }, |
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308 | .vco = { .min = 1760000, .max = 3510000 }, |
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309 | .n = { .min = 1, .max = 3 }, |
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310 | .m = { .min = 79, .max = 126 }, |
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311 | .m1 = { .min = 12, .max = 22 }, |
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312 | .m2 = { .min = 5, .max = 9 }, |
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313 | .p = { .min = 14, .max = 42 }, |
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2342 | Serge | 314 | .p1 = { .min = 2, .max = 6 }, |
2327 | Serge | 315 | .p2 = { .dot_limit = 225000, |
316 | .p2_slow = 7, .p2_fast = 7 }, |
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317 | }; |
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318 | |||
3031 | serge | 319 | static const intel_limit_t intel_limits_vlv_dac = { |
320 | .dot = { .min = 25000, .max = 270000 }, |
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321 | .vco = { .min = 4000000, .max = 6000000 }, |
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322 | .n = { .min = 1, .max = 7 }, |
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323 | .m = { .min = 22, .max = 450 }, /* guess */ |
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324 | .m1 = { .min = 2, .max = 3 }, |
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325 | .m2 = { .min = 11, .max = 156 }, |
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326 | .p = { .min = 10, .max = 30 }, |
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4104 | Serge | 327 | .p1 = { .min = 1, .max = 3 }, |
3031 | serge | 328 | .p2 = { .dot_limit = 270000, |
329 | .p2_slow = 2, .p2_fast = 20 }, |
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330 | }; |
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331 | |||
332 | static const intel_limit_t intel_limits_vlv_hdmi = { |
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4104 | Serge | 333 | .dot = { .min = 25000, .max = 270000 }, |
334 | .vco = { .min = 4000000, .max = 6000000 }, |
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3031 | serge | 335 | .n = { .min = 1, .max = 7 }, |
336 | .m = { .min = 60, .max = 300 }, /* guess */ |
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337 | .m1 = { .min = 2, .max = 3 }, |
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338 | .m2 = { .min = 11, .max = 156 }, |
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339 | .p = { .min = 10, .max = 30 }, |
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340 | .p1 = { .min = 2, .max = 3 }, |
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341 | .p2 = { .dot_limit = 270000, |
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342 | .p2_slow = 2, .p2_fast = 20 }, |
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343 | }; |
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344 | |||
345 | static const intel_limit_t intel_limits_vlv_dp = { |
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3243 | Serge | 346 | .dot = { .min = 25000, .max = 270000 }, |
347 | .vco = { .min = 4000000, .max = 6000000 }, |
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3031 | serge | 348 | .n = { .min = 1, .max = 7 }, |
3243 | Serge | 349 | .m = { .min = 22, .max = 450 }, |
3031 | serge | 350 | .m1 = { .min = 2, .max = 3 }, |
351 | .m2 = { .min = 11, .max = 156 }, |
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352 | .p = { .min = 10, .max = 30 }, |
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4104 | Serge | 353 | .p1 = { .min = 1, .max = 3 }, |
3031 | serge | 354 | .p2 = { .dot_limit = 270000, |
355 | .p2_slow = 2, .p2_fast = 20 }, |
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356 | }; |
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357 | |||
2327 | Serge | 358 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
359 | int refclk) |
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360 | { |
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361 | struct drm_device *dev = crtc->dev; |
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362 | const intel_limit_t *limit; |
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363 | |||
364 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
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3480 | Serge | 365 | if (intel_is_dual_link_lvds(dev)) { |
2327 | Serge | 366 | if (refclk == 100000) |
367 | limit = &intel_limits_ironlake_dual_lvds_100m; |
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368 | else |
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369 | limit = &intel_limits_ironlake_dual_lvds; |
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370 | } else { |
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371 | if (refclk == 100000) |
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372 | limit = &intel_limits_ironlake_single_lvds_100m; |
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373 | else |
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374 | limit = &intel_limits_ironlake_single_lvds; |
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375 | } |
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4104 | Serge | 376 | } else |
2327 | Serge | 377 | limit = &intel_limits_ironlake_dac; |
378 | |||
379 | return limit; |
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380 | } |
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381 | |||
382 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
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383 | { |
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384 | struct drm_device *dev = crtc->dev; |
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385 | const intel_limit_t *limit; |
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386 | |||
387 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
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3480 | Serge | 388 | if (intel_is_dual_link_lvds(dev)) |
2327 | Serge | 389 | limit = &intel_limits_g4x_dual_channel_lvds; |
390 | else |
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391 | limit = &intel_limits_g4x_single_channel_lvds; |
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392 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
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393 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
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394 | limit = &intel_limits_g4x_hdmi; |
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395 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
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396 | limit = &intel_limits_g4x_sdvo; |
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397 | } else /* The option is for other outputs */ |
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398 | limit = &intel_limits_i9xx_sdvo; |
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399 | |||
400 | return limit; |
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401 | } |
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402 | |||
403 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
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404 | { |
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405 | struct drm_device *dev = crtc->dev; |
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406 | const intel_limit_t *limit; |
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407 | |||
408 | if (HAS_PCH_SPLIT(dev)) |
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409 | limit = intel_ironlake_limit(crtc, refclk); |
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410 | else if (IS_G4X(dev)) { |
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411 | limit = intel_g4x_limit(crtc); |
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412 | } else if (IS_PINEVIEW(dev)) { |
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413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
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414 | limit = &intel_limits_pineview_lvds; |
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415 | else |
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416 | limit = &intel_limits_pineview_sdvo; |
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3031 | serge | 417 | } else if (IS_VALLEYVIEW(dev)) { |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
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419 | limit = &intel_limits_vlv_dac; |
||
420 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
||
421 | limit = &intel_limits_vlv_hdmi; |
||
422 | else |
||
423 | limit = &intel_limits_vlv_dp; |
||
2327 | Serge | 424 | } else if (!IS_GEN2(dev)) { |
425 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
||
426 | limit = &intel_limits_i9xx_lvds; |
||
427 | else |
||
428 | limit = &intel_limits_i9xx_sdvo; |
||
429 | } else { |
||
430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
||
431 | limit = &intel_limits_i8xx_lvds; |
||
4104 | Serge | 432 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
433 | limit = &intel_limits_i8xx_dvo; |
||
2327 | Serge | 434 | else |
4104 | Serge | 435 | limit = &intel_limits_i8xx_dac; |
2327 | Serge | 436 | } |
437 | return limit; |
||
438 | } |
||
439 | |||
440 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
||
441 | static void pineview_clock(int refclk, intel_clock_t *clock) |
||
442 | { |
||
443 | clock->m = clock->m2 + 2; |
||
444 | clock->p = clock->p1 * clock->p2; |
||
445 | clock->vco = refclk * clock->m / clock->n; |
||
446 | clock->dot = clock->vco / clock->p; |
||
447 | } |
||
448 | |||
4104 | Serge | 449 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
2327 | Serge | 450 | { |
4104 | Serge | 451 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
452 | } |
||
453 | |||
454 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
||
455 | { |
||
456 | clock->m = i9xx_dpll_compute_m(clock); |
||
2327 | Serge | 457 | clock->p = clock->p1 * clock->p2; |
458 | clock->vco = refclk * clock->m / (clock->n + 2); |
||
459 | clock->dot = clock->vco / clock->p; |
||
460 | } |
||
461 | |||
462 | /** |
||
463 | * Returns whether any output on the specified pipe is of the specified type |
||
464 | */ |
||
465 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
||
466 | { |
||
467 | struct drm_device *dev = crtc->dev; |
||
468 | struct intel_encoder *encoder; |
||
469 | |||
3031 | serge | 470 | for_each_encoder_on_crtc(dev, crtc, encoder) |
471 | if (encoder->type == type) |
||
2327 | Serge | 472 | return true; |
473 | |||
474 | return false; |
||
475 | } |
||
476 | |||
477 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
||
478 | /** |
||
479 | * Returns whether the given set of divisors are valid for a given refclk with |
||
480 | * the given connectors. |
||
481 | */ |
||
482 | |||
483 | static bool intel_PLL_is_valid(struct drm_device *dev, |
||
484 | const intel_limit_t *limit, |
||
485 | const intel_clock_t *clock) |
||
486 | { |
||
487 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
||
2342 | Serge | 488 | INTELPllInvalid("p1 out of range\n"); |
2327 | Serge | 489 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
2342 | Serge | 490 | INTELPllInvalid("p out of range\n"); |
2327 | Serge | 491 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
2342 | Serge | 492 | INTELPllInvalid("m2 out of range\n"); |
2327 | Serge | 493 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
2342 | Serge | 494 | INTELPllInvalid("m1 out of range\n"); |
2327 | Serge | 495 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
2342 | Serge | 496 | INTELPllInvalid("m1 <= m2\n"); |
2327 | Serge | 497 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
2342 | Serge | 498 | INTELPllInvalid("m out of range\n"); |
2327 | Serge | 499 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
2342 | Serge | 500 | INTELPllInvalid("n out of range\n"); |
2327 | Serge | 501 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
2342 | Serge | 502 | INTELPllInvalid("vco out of range\n"); |
2327 | Serge | 503 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
504 | * connector, etc., rather than just a single range. |
||
505 | */ |
||
506 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
||
2342 | Serge | 507 | INTELPllInvalid("dot out of range\n"); |
2327 | Serge | 508 | |
509 | return true; |
||
510 | } |
||
511 | |||
512 | static bool |
||
4104 | Serge | 513 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
3031 | serge | 514 | int target, int refclk, intel_clock_t *match_clock, |
515 | intel_clock_t *best_clock) |
||
2327 | Serge | 516 | { |
517 | struct drm_device *dev = crtc->dev; |
||
518 | intel_clock_t clock; |
||
519 | int err = target; |
||
520 | |||
3480 | Serge | 521 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2327 | Serge | 522 | /* |
3480 | Serge | 523 | * For LVDS just rely on its current settings for dual-channel. |
524 | * We haven't figured out how to reliably set up different |
||
525 | * single/dual channel state, if we even can. |
||
2327 | Serge | 526 | */ |
3480 | Serge | 527 | if (intel_is_dual_link_lvds(dev)) |
2327 | Serge | 528 | clock.p2 = limit->p2.p2_fast; |
529 | else |
||
530 | clock.p2 = limit->p2.p2_slow; |
||
531 | } else { |
||
532 | if (target < limit->p2.dot_limit) |
||
533 | clock.p2 = limit->p2.p2_slow; |
||
534 | else |
||
535 | clock.p2 = limit->p2.p2_fast; |
||
536 | } |
||
537 | |||
2342 | Serge | 538 | memset(best_clock, 0, sizeof(*best_clock)); |
2327 | Serge | 539 | |
540 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
||
541 | clock.m1++) { |
||
542 | for (clock.m2 = limit->m2.min; |
||
543 | clock.m2 <= limit->m2.max; clock.m2++) { |
||
4104 | Serge | 544 | if (clock.m2 >= clock.m1) |
2327 | Serge | 545 | break; |
546 | for (clock.n = limit->n.min; |
||
547 | clock.n <= limit->n.max; clock.n++) { |
||
548 | for (clock.p1 = limit->p1.min; |
||
549 | clock.p1 <= limit->p1.max; clock.p1++) { |
||
550 | int this_err; |
||
551 | |||
4104 | Serge | 552 | i9xx_clock(refclk, &clock); |
2327 | Serge | 553 | if (!intel_PLL_is_valid(dev, limit, |
554 | &clock)) |
||
555 | continue; |
||
3031 | serge | 556 | if (match_clock && |
557 | clock.p != match_clock->p) |
||
558 | continue; |
||
2327 | Serge | 559 | |
560 | this_err = abs(clock.dot - target); |
||
561 | if (this_err < err) { |
||
562 | *best_clock = clock; |
||
563 | err = this_err; |
||
564 | } |
||
565 | } |
||
566 | } |
||
567 | } |
||
568 | } |
||
569 | |||
570 | return (err != target); |
||
571 | } |
||
572 | |||
573 | static bool |
||
4104 | Serge | 574 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
575 | int target, int refclk, intel_clock_t *match_clock, |
||
576 | intel_clock_t *best_clock) |
||
577 | { |
||
578 | struct drm_device *dev = crtc->dev; |
||
579 | intel_clock_t clock; |
||
580 | int err = target; |
||
581 | |||
582 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
||
583 | /* |
||
584 | * For LVDS just rely on its current settings for dual-channel. |
||
585 | * We haven't figured out how to reliably set up different |
||
586 | * single/dual channel state, if we even can. |
||
587 | */ |
||
588 | if (intel_is_dual_link_lvds(dev)) |
||
589 | clock.p2 = limit->p2.p2_fast; |
||
590 | else |
||
591 | clock.p2 = limit->p2.p2_slow; |
||
592 | } else { |
||
593 | if (target < limit->p2.dot_limit) |
||
594 | clock.p2 = limit->p2.p2_slow; |
||
595 | else |
||
596 | clock.p2 = limit->p2.p2_fast; |
||
597 | } |
||
598 | |||
599 | memset(best_clock, 0, sizeof(*best_clock)); |
||
600 | |||
601 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
||
602 | clock.m1++) { |
||
603 | for (clock.m2 = limit->m2.min; |
||
604 | clock.m2 <= limit->m2.max; clock.m2++) { |
||
605 | for (clock.n = limit->n.min; |
||
606 | clock.n <= limit->n.max; clock.n++) { |
||
607 | for (clock.p1 = limit->p1.min; |
||
608 | clock.p1 <= limit->p1.max; clock.p1++) { |
||
609 | int this_err; |
||
610 | |||
611 | pineview_clock(refclk, &clock); |
||
612 | if (!intel_PLL_is_valid(dev, limit, |
||
613 | &clock)) |
||
614 | continue; |
||
615 | if (match_clock && |
||
616 | clock.p != match_clock->p) |
||
617 | continue; |
||
618 | |||
619 | this_err = abs(clock.dot - target); |
||
620 | if (this_err < err) { |
||
621 | *best_clock = clock; |
||
622 | err = this_err; |
||
623 | } |
||
624 | } |
||
625 | } |
||
626 | } |
||
627 | } |
||
628 | |||
629 | return (err != target); |
||
630 | } |
||
631 | |||
632 | static bool |
||
633 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
||
3031 | serge | 634 | int target, int refclk, intel_clock_t *match_clock, |
635 | intel_clock_t *best_clock) |
||
2327 | Serge | 636 | { |
637 | struct drm_device *dev = crtc->dev; |
||
638 | intel_clock_t clock; |
||
639 | int max_n; |
||
640 | bool found; |
||
641 | /* approximately equals target * 0.00585 */ |
||
642 | int err_most = (target >> 8) + (target >> 9); |
||
643 | found = false; |
||
644 | |||
645 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
||
3480 | Serge | 646 | if (intel_is_dual_link_lvds(dev)) |
2327 | Serge | 647 | clock.p2 = limit->p2.p2_fast; |
648 | else |
||
649 | clock.p2 = limit->p2.p2_slow; |
||
650 | } else { |
||
651 | if (target < limit->p2.dot_limit) |
||
652 | clock.p2 = limit->p2.p2_slow; |
||
653 | else |
||
654 | clock.p2 = limit->p2.p2_fast; |
||
655 | } |
||
656 | |||
657 | memset(best_clock, 0, sizeof(*best_clock)); |
||
658 | max_n = limit->n.max; |
||
659 | /* based on hardware requirement, prefer smaller n to precision */ |
||
660 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
||
661 | /* based on hardware requirement, prefere larger m1,m2 */ |
||
662 | for (clock.m1 = limit->m1.max; |
||
663 | clock.m1 >= limit->m1.min; clock.m1--) { |
||
664 | for (clock.m2 = limit->m2.max; |
||
665 | clock.m2 >= limit->m2.min; clock.m2--) { |
||
666 | for (clock.p1 = limit->p1.max; |
||
667 | clock.p1 >= limit->p1.min; clock.p1--) { |
||
668 | int this_err; |
||
669 | |||
4104 | Serge | 670 | i9xx_clock(refclk, &clock); |
2327 | Serge | 671 | if (!intel_PLL_is_valid(dev, limit, |
672 | &clock)) |
||
673 | continue; |
||
674 | |||
675 | this_err = abs(clock.dot - target); |
||
676 | if (this_err < err_most) { |
||
677 | *best_clock = clock; |
||
678 | err_most = this_err; |
||
679 | max_n = clock.n; |
||
680 | found = true; |
||
681 | } |
||
682 | } |
||
683 | } |
||
684 | } |
||
685 | } |
||
686 | return found; |
||
687 | } |
||
688 | |||
689 | static bool |
||
4104 | Serge | 690 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
3031 | serge | 691 | int target, int refclk, intel_clock_t *match_clock, |
692 | intel_clock_t *best_clock) |
||
693 | { |
||
694 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
||
695 | u32 m, n, fastclk; |
||
4104 | Serge | 696 | u32 updrate, minupdate, p; |
3031 | serge | 697 | unsigned long bestppm, ppm, absppm; |
698 | int dotclk, flag; |
||
2327 | Serge | 699 | |
3031 | serge | 700 | flag = 0; |
701 | dotclk = target * 1000; |
||
702 | bestppm = 1000000; |
||
703 | ppm = absppm = 0; |
||
704 | fastclk = dotclk / (2*100); |
||
705 | updrate = 0; |
||
706 | minupdate = 19200; |
||
707 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
||
708 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
||
709 | |||
710 | /* based on hardware requirement, prefer smaller n to precision */ |
||
711 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
||
712 | updrate = refclk / n; |
||
713 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
||
714 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
||
715 | if (p2 > 10) |
||
716 | p2 = p2 - 1; |
||
717 | p = p1 * p2; |
||
718 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
||
719 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
||
720 | m2 = (((2*(fastclk * p * n / m1 )) + |
||
721 | refclk) / (2*refclk)); |
||
722 | m = m1 * m2; |
||
723 | vco = updrate * m; |
||
724 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
||
725 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
||
726 | absppm = (ppm > 0) ? ppm : (-ppm); |
||
727 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
||
728 | bestppm = 0; |
||
729 | flag = 1; |
||
730 | } |
||
731 | if (absppm < bestppm - 10) { |
||
732 | bestppm = absppm; |
||
733 | flag = 1; |
||
734 | } |
||
735 | if (flag) { |
||
736 | bestn = n; |
||
737 | bestm1 = m1; |
||
738 | bestm2 = m2; |
||
739 | bestp1 = p1; |
||
740 | bestp2 = p2; |
||
741 | flag = 0; |
||
742 | } |
||
743 | } |
||
744 | } |
||
745 | } |
||
746 | } |
||
747 | } |
||
748 | best_clock->n = bestn; |
||
749 | best_clock->m1 = bestm1; |
||
750 | best_clock->m2 = bestm2; |
||
751 | best_clock->p1 = bestp1; |
||
752 | best_clock->p2 = bestp2; |
||
753 | |||
754 | return true; |
||
755 | } |
||
756 | |||
3243 | Serge | 757 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
758 | enum pipe pipe) |
||
759 | { |
||
760 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
||
761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
762 | |||
3746 | Serge | 763 | return intel_crtc->config.cpu_transcoder; |
3243 | Serge | 764 | } |
765 | |||
3031 | serge | 766 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
767 | { |
||
768 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
769 | u32 frame, frame_reg = PIPEFRAME(pipe); |
||
770 | |||
771 | frame = I915_READ(frame_reg); |
||
772 | |||
773 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
||
774 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
||
775 | } |
||
776 | |||
2327 | Serge | 777 | /** |
778 | * intel_wait_for_vblank - wait for vblank on a given pipe |
||
779 | * @dev: drm device |
||
780 | * @pipe: pipe to wait for |
||
781 | * |
||
782 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
||
783 | * mode setting code. |
||
784 | */ |
||
785 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
||
786 | { |
||
787 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
788 | int pipestat_reg = PIPESTAT(pipe); |
||
789 | |||
3031 | serge | 790 | if (INTEL_INFO(dev)->gen >= 5) { |
791 | ironlake_wait_for_vblank(dev, pipe); |
||
792 | return; |
||
793 | } |
||
794 | |||
2327 | Serge | 795 | /* Clear existing vblank status. Note this will clear any other |
796 | * sticky status fields as well. |
||
797 | * |
||
798 | * This races with i915_driver_irq_handler() with the result |
||
799 | * that either function could miss a vblank event. Here it is not |
||
800 | * fatal, as we will either wait upon the next vblank interrupt or |
||
801 | * timeout. Generally speaking intel_wait_for_vblank() is only |
||
802 | * called during modeset at which time the GPU should be idle and |
||
803 | * should *not* be performing page flips and thus not waiting on |
||
804 | * vblanks... |
||
805 | * Currently, the result of us stealing a vblank from the irq |
||
806 | * handler is that a single frame will be skipped during swapbuffers. |
||
807 | */ |
||
808 | I915_WRITE(pipestat_reg, |
||
809 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
||
810 | |||
811 | /* Wait for vblank interrupt bit to set */ |
||
812 | if (wait_for(I915_READ(pipestat_reg) & |
||
813 | PIPE_VBLANK_INTERRUPT_STATUS, |
||
814 | 50)) |
||
815 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
||
816 | } |
||
817 | |||
818 | /* |
||
819 | * intel_wait_for_pipe_off - wait for pipe to turn off |
||
820 | * @dev: drm device |
||
821 | * @pipe: pipe to wait for |
||
822 | * |
||
823 | * After disabling a pipe, we can't wait for vblank in the usual way, |
||
824 | * spinning on the vblank interrupt status bit, since we won't actually |
||
825 | * see an interrupt when the pipe is disabled. |
||
826 | * |
||
827 | * On Gen4 and above: |
||
828 | * wait for the pipe register state bit to turn off |
||
829 | * |
||
830 | * Otherwise: |
||
831 | * wait for the display line value to settle (it usually |
||
832 | * ends up stopping at the start of the next frame). |
||
833 | * |
||
834 | */ |
||
835 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
||
836 | { |
||
837 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3243 | Serge | 838 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
839 | pipe); |
||
2327 | Serge | 840 | |
841 | if (INTEL_INFO(dev)->gen >= 4) { |
||
3243 | Serge | 842 | int reg = PIPECONF(cpu_transcoder); |
2327 | Serge | 843 | |
844 | /* Wait for the Pipe State to go off */ |
||
845 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
||
846 | 100)) |
||
3031 | serge | 847 | WARN(1, "pipe_off wait timed out\n"); |
2327 | Serge | 848 | } else { |
3031 | serge | 849 | u32 last_line, line_mask; |
2327 | Serge | 850 | int reg = PIPEDSL(pipe); |
4104 | Serge | 851 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
2327 | Serge | 852 | |
3031 | serge | 853 | if (IS_GEN2(dev)) |
854 | line_mask = DSL_LINEMASK_GEN2; |
||
855 | else |
||
856 | line_mask = DSL_LINEMASK_GEN3; |
||
857 | |||
2327 | Serge | 858 | /* Wait for the display line to settle */ |
859 | do { |
||
3031 | serge | 860 | last_line = I915_READ(reg) & line_mask; |
2327 | Serge | 861 | mdelay(5); |
3031 | serge | 862 | } while (((I915_READ(reg) & line_mask) != last_line) && |
863 | time_after(timeout, GetTimerTicks())); |
||
864 | if (time_after(GetTimerTicks(), timeout)) |
||
865 | WARN(1, "pipe_off wait timed out\n"); |
||
2327 | Serge | 866 | } |
867 | } |
||
868 | |||
3480 | Serge | 869 | /* |
870 | * ibx_digital_port_connected - is the specified port connected? |
||
871 | * @dev_priv: i915 private structure |
||
872 | * @port: the port to test |
||
873 | * |
||
874 | * Returns true if @port is connected, false otherwise. |
||
875 | */ |
||
876 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
||
877 | struct intel_digital_port *port) |
||
878 | { |
||
879 | u32 bit; |
||
880 | |||
881 | if (HAS_PCH_IBX(dev_priv->dev)) { |
||
882 | switch(port->port) { |
||
883 | case PORT_B: |
||
884 | bit = SDE_PORTB_HOTPLUG; |
||
885 | break; |
||
886 | case PORT_C: |
||
887 | bit = SDE_PORTC_HOTPLUG; |
||
888 | break; |
||
889 | case PORT_D: |
||
890 | bit = SDE_PORTD_HOTPLUG; |
||
891 | break; |
||
892 | default: |
||
893 | return true; |
||
894 | } |
||
895 | } else { |
||
896 | switch(port->port) { |
||
897 | case PORT_B: |
||
898 | bit = SDE_PORTB_HOTPLUG_CPT; |
||
899 | break; |
||
900 | case PORT_C: |
||
901 | bit = SDE_PORTC_HOTPLUG_CPT; |
||
902 | break; |
||
903 | case PORT_D: |
||
904 | bit = SDE_PORTD_HOTPLUG_CPT; |
||
905 | break; |
||
906 | default: |
||
907 | return true; |
||
908 | } |
||
909 | } |
||
910 | |||
911 | return I915_READ(SDEISR) & bit; |
||
912 | } |
||
913 | |||
2327 | Serge | 914 | static const char *state_string(bool enabled) |
915 | { |
||
916 | return enabled ? "on" : "off"; |
||
917 | } |
||
918 | |||
919 | /* Only for pre-ILK configs */ |
||
4104 | Serge | 920 | void assert_pll(struct drm_i915_private *dev_priv, |
2327 | Serge | 921 | enum pipe pipe, bool state) |
922 | { |
||
923 | int reg; |
||
924 | u32 val; |
||
925 | bool cur_state; |
||
926 | |||
927 | reg = DPLL(pipe); |
||
928 | val = I915_READ(reg); |
||
929 | cur_state = !!(val & DPLL_VCO_ENABLE); |
||
930 | WARN(cur_state != state, |
||
931 | "PLL state assertion failure (expected %s, current %s)\n", |
||
932 | state_string(state), state_string(cur_state)); |
||
933 | } |
||
934 | |||
4104 | Serge | 935 | struct intel_shared_dpll * |
936 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
||
937 | { |
||
938 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
||
939 | |||
940 | if (crtc->config.shared_dpll < 0) |
||
941 | return NULL; |
||
942 | |||
943 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
||
944 | } |
||
945 | |||
2327 | Serge | 946 | /* For ILK+ */ |
4104 | Serge | 947 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
948 | struct intel_shared_dpll *pll, |
||
3031 | serge | 949 | bool state) |
2327 | Serge | 950 | { |
951 | bool cur_state; |
||
4104 | Serge | 952 | struct intel_dpll_hw_state hw_state; |
2327 | Serge | 953 | |
3031 | serge | 954 | if (HAS_PCH_LPT(dev_priv->dev)) { |
955 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
||
956 | return; |
||
957 | } |
||
2342 | Serge | 958 | |
3031 | serge | 959 | if (WARN (!pll, |
4104 | Serge | 960 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
3031 | serge | 961 | return; |
2342 | Serge | 962 | |
4104 | Serge | 963 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
3031 | serge | 964 | WARN(cur_state != state, |
4104 | Serge | 965 | "%s assertion failure (expected %s, current %s)\n", |
966 | pll->name, state_string(state), state_string(cur_state)); |
||
2327 | Serge | 967 | } |
968 | |||
969 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
||
970 | enum pipe pipe, bool state) |
||
971 | { |
||
972 | int reg; |
||
973 | u32 val; |
||
974 | bool cur_state; |
||
3243 | Serge | 975 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
976 | pipe); |
||
2327 | Serge | 977 | |
3480 | Serge | 978 | if (HAS_DDI(dev_priv->dev)) { |
979 | /* DDI does not have a specific FDI_TX register */ |
||
3243 | Serge | 980 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
3031 | serge | 981 | val = I915_READ(reg); |
3243 | Serge | 982 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
3031 | serge | 983 | } else { |
2327 | Serge | 984 | reg = FDI_TX_CTL(pipe); |
985 | val = I915_READ(reg); |
||
986 | cur_state = !!(val & FDI_TX_ENABLE); |
||
3031 | serge | 987 | } |
2327 | Serge | 988 | WARN(cur_state != state, |
989 | "FDI TX state assertion failure (expected %s, current %s)\n", |
||
990 | state_string(state), state_string(cur_state)); |
||
991 | } |
||
992 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
||
993 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
||
994 | |||
995 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
||
996 | enum pipe pipe, bool state) |
||
997 | { |
||
998 | int reg; |
||
999 | u32 val; |
||
1000 | bool cur_state; |
||
1001 | |||
1002 | reg = FDI_RX_CTL(pipe); |
||
1003 | val = I915_READ(reg); |
||
1004 | cur_state = !!(val & FDI_RX_ENABLE); |
||
1005 | WARN(cur_state != state, |
||
1006 | "FDI RX state assertion failure (expected %s, current %s)\n", |
||
1007 | state_string(state), state_string(cur_state)); |
||
1008 | } |
||
1009 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
||
1010 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
||
1011 | |||
1012 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
||
1013 | enum pipe pipe) |
||
1014 | { |
||
1015 | int reg; |
||
1016 | u32 val; |
||
1017 | |||
1018 | /* ILK FDI PLL is always enabled */ |
||
1019 | if (dev_priv->info->gen == 5) |
||
1020 | return; |
||
1021 | |||
3031 | serge | 1022 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
3480 | Serge | 1023 | if (HAS_DDI(dev_priv->dev)) |
3031 | serge | 1024 | return; |
1025 | |||
2327 | Serge | 1026 | reg = FDI_TX_CTL(pipe); |
1027 | val = I915_READ(reg); |
||
1028 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
||
1029 | } |
||
1030 | |||
4104 | Serge | 1031 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1032 | enum pipe pipe, bool state) |
||
2327 | Serge | 1033 | { |
1034 | int reg; |
||
1035 | u32 val; |
||
4104 | Serge | 1036 | bool cur_state; |
2327 | Serge | 1037 | |
1038 | reg = FDI_RX_CTL(pipe); |
||
1039 | val = I915_READ(reg); |
||
4104 | Serge | 1040 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1041 | WARN(cur_state != state, |
||
1042 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
||
1043 | state_string(state), state_string(cur_state)); |
||
2327 | Serge | 1044 | } |
1045 | |||
1046 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
||
1047 | enum pipe pipe) |
||
1048 | { |
||
1049 | int pp_reg, lvds_reg; |
||
1050 | u32 val; |
||
1051 | enum pipe panel_pipe = PIPE_A; |
||
1052 | bool locked = true; |
||
1053 | |||
1054 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
||
1055 | pp_reg = PCH_PP_CONTROL; |
||
1056 | lvds_reg = PCH_LVDS; |
||
1057 | } else { |
||
1058 | pp_reg = PP_CONTROL; |
||
1059 | lvds_reg = LVDS; |
||
1060 | } |
||
1061 | |||
1062 | val = I915_READ(pp_reg); |
||
1063 | if (!(val & PANEL_POWER_ON) || |
||
1064 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
||
1065 | locked = false; |
||
1066 | |||
1067 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
||
1068 | panel_pipe = PIPE_B; |
||
1069 | |||
1070 | WARN(panel_pipe == pipe && locked, |
||
1071 | "panel assertion failure, pipe %c regs locked\n", |
||
1072 | pipe_name(pipe)); |
||
1073 | } |
||
1074 | |||
2342 | Serge | 1075 | void assert_pipe(struct drm_i915_private *dev_priv, |
2327 | Serge | 1076 | enum pipe pipe, bool state) |
1077 | { |
||
1078 | int reg; |
||
1079 | u32 val; |
||
1080 | bool cur_state; |
||
3243 | Serge | 1081 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1082 | pipe); |
||
2327 | Serge | 1083 | |
3031 | serge | 1084 | /* if we need the pipe A quirk it must be always on */ |
1085 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
||
1086 | state = true; |
||
1087 | |||
4104 | Serge | 1088 | if (!intel_display_power_enabled(dev_priv->dev, |
1089 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
||
3480 | Serge | 1090 | cur_state = false; |
1091 | } else { |
||
3243 | Serge | 1092 | reg = PIPECONF(cpu_transcoder); |
2327 | Serge | 1093 | val = I915_READ(reg); |
1094 | cur_state = !!(val & PIPECONF_ENABLE); |
||
3480 | Serge | 1095 | } |
1096 | |||
2327 | Serge | 1097 | WARN(cur_state != state, |
1098 | "pipe %c assertion failure (expected %s, current %s)\n", |
||
1099 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
||
1100 | } |
||
1101 | |||
3031 | serge | 1102 | static void assert_plane(struct drm_i915_private *dev_priv, |
1103 | enum plane plane, bool state) |
||
2327 | Serge | 1104 | { |
1105 | int reg; |
||
1106 | u32 val; |
||
3031 | serge | 1107 | bool cur_state; |
2327 | Serge | 1108 | |
1109 | reg = DSPCNTR(plane); |
||
1110 | val = I915_READ(reg); |
||
3031 | serge | 1111 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1112 | WARN(cur_state != state, |
||
1113 | "plane %c assertion failure (expected %s, current %s)\n", |
||
1114 | plane_name(plane), state_string(state), state_string(cur_state)); |
||
2327 | Serge | 1115 | } |
1116 | |||
3031 | serge | 1117 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1118 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
||
1119 | |||
2327 | Serge | 1120 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1121 | enum pipe pipe) |
||
1122 | { |
||
4104 | Serge | 1123 | struct drm_device *dev = dev_priv->dev; |
2327 | Serge | 1124 | int reg, i; |
1125 | u32 val; |
||
1126 | int cur_pipe; |
||
1127 | |||
4104 | Serge | 1128 | /* Primary planes are fixed to pipes on gen4+ */ |
1129 | if (INTEL_INFO(dev)->gen >= 4) { |
||
3031 | serge | 1130 | reg = DSPCNTR(pipe); |
1131 | val = I915_READ(reg); |
||
1132 | WARN((val & DISPLAY_PLANE_ENABLE), |
||
1133 | "plane %c assertion failure, should be disabled but not\n", |
||
1134 | plane_name(pipe)); |
||
2327 | Serge | 1135 | return; |
3031 | serge | 1136 | } |
2327 | Serge | 1137 | |
1138 | /* Need to check both planes against the pipe */ |
||
4104 | Serge | 1139 | for_each_pipe(i) { |
2327 | Serge | 1140 | reg = DSPCNTR(i); |
1141 | val = I915_READ(reg); |
||
1142 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
||
1143 | DISPPLANE_SEL_PIPE_SHIFT; |
||
1144 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
||
1145 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
||
1146 | plane_name(i), pipe_name(pipe)); |
||
1147 | } |
||
1148 | } |
||
1149 | |||
3746 | Serge | 1150 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1151 | enum pipe pipe) |
||
1152 | { |
||
4104 | Serge | 1153 | struct drm_device *dev = dev_priv->dev; |
3746 | Serge | 1154 | int reg, i; |
1155 | u32 val; |
||
1156 | |||
4104 | Serge | 1157 | if (IS_VALLEYVIEW(dev)) { |
3746 | Serge | 1158 | for (i = 0; i < dev_priv->num_plane; i++) { |
1159 | reg = SPCNTR(pipe, i); |
||
1160 | val = I915_READ(reg); |
||
1161 | WARN((val & SP_ENABLE), |
||
4104 | Serge | 1162 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1163 | sprite_name(pipe, i), pipe_name(pipe)); |
||
1164 | } |
||
1165 | } else if (INTEL_INFO(dev)->gen >= 7) { |
||
1166 | reg = SPRCTL(pipe); |
||
1167 | val = I915_READ(reg); |
||
1168 | WARN((val & SPRITE_ENABLE), |
||
1169 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
||
1170 | plane_name(pipe), pipe_name(pipe)); |
||
1171 | } else if (INTEL_INFO(dev)->gen >= 5) { |
||
1172 | reg = DVSCNTR(pipe); |
||
1173 | val = I915_READ(reg); |
||
1174 | WARN((val & DVS_ENABLE), |
||
1175 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
||
1176 | plane_name(pipe), pipe_name(pipe)); |
||
3746 | Serge | 1177 | } |
1178 | } |
||
1179 | |||
2327 | Serge | 1180 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1181 | { |
||
1182 | u32 val; |
||
1183 | bool enabled; |
||
1184 | |||
3031 | serge | 1185 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1186 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
||
1187 | return; |
||
1188 | } |
||
1189 | |||
2327 | Serge | 1190 | val = I915_READ(PCH_DREF_CONTROL); |
1191 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
||
1192 | DREF_SUPERSPREAD_SOURCE_MASK)); |
||
1193 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
||
1194 | } |
||
1195 | |||
4104 | Serge | 1196 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
2327 | Serge | 1197 | enum pipe pipe) |
1198 | { |
||
1199 | int reg; |
||
1200 | u32 val; |
||
1201 | bool enabled; |
||
1202 | |||
4104 | Serge | 1203 | reg = PCH_TRANSCONF(pipe); |
2327 | Serge | 1204 | val = I915_READ(reg); |
1205 | enabled = !!(val & TRANS_ENABLE); |
||
1206 | WARN(enabled, |
||
1207 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
||
1208 | pipe_name(pipe)); |
||
1209 | } |
||
1210 | |||
1211 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
||
1212 | enum pipe pipe, u32 port_sel, u32 val) |
||
1213 | { |
||
1214 | if ((val & DP_PORT_EN) == 0) |
||
1215 | return false; |
||
1216 | |||
1217 | if (HAS_PCH_CPT(dev_priv->dev)) { |
||
1218 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
||
1219 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
||
1220 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
||
1221 | return false; |
||
1222 | } else { |
||
1223 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
||
1224 | return false; |
||
1225 | } |
||
1226 | return true; |
||
1227 | } |
||
1228 | |||
1229 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
||
1230 | enum pipe pipe, u32 val) |
||
1231 | { |
||
3746 | Serge | 1232 | if ((val & SDVO_ENABLE) == 0) |
2327 | Serge | 1233 | return false; |
1234 | |||
1235 | if (HAS_PCH_CPT(dev_priv->dev)) { |
||
3746 | Serge | 1236 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
2327 | Serge | 1237 | return false; |
1238 | } else { |
||
3746 | Serge | 1239 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
2327 | Serge | 1240 | return false; |
1241 | } |
||
1242 | return true; |
||
1243 | } |
||
1244 | |||
1245 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
||
1246 | enum pipe pipe, u32 val) |
||
1247 | { |
||
1248 | if ((val & LVDS_PORT_EN) == 0) |
||
1249 | return false; |
||
1250 | |||
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { |
||
1252 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
||
1253 | return false; |
||
1254 | } else { |
||
1255 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
||
1256 | return false; |
||
1257 | } |
||
1258 | return true; |
||
1259 | } |
||
1260 | |||
1261 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
||
1262 | enum pipe pipe, u32 val) |
||
1263 | { |
||
1264 | if ((val & ADPA_DAC_ENABLE) == 0) |
||
1265 | return false; |
||
1266 | if (HAS_PCH_CPT(dev_priv->dev)) { |
||
1267 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
||
1268 | return false; |
||
1269 | } else { |
||
1270 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
||
1271 | return false; |
||
1272 | } |
||
1273 | return true; |
||
1274 | } |
||
1275 | |||
1276 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
||
1277 | enum pipe pipe, int reg, u32 port_sel) |
||
1278 | { |
||
1279 | u32 val = I915_READ(reg); |
||
1280 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
||
1281 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
||
1282 | reg, pipe_name(pipe)); |
||
3031 | serge | 1283 | |
1284 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
||
1285 | && (val & DP_PIPEB_SELECT), |
||
1286 | "IBX PCH dp port still using transcoder B\n"); |
||
2327 | Serge | 1287 | } |
1288 | |||
1289 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
||
1290 | enum pipe pipe, int reg) |
||
1291 | { |
||
1292 | u32 val = I915_READ(reg); |
||
3031 | serge | 1293 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1294 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
||
2327 | Serge | 1295 | reg, pipe_name(pipe)); |
3031 | serge | 1296 | |
3746 | Serge | 1297 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
3031 | serge | 1298 | && (val & SDVO_PIPE_B_SELECT), |
1299 | "IBX PCH hdmi port still using transcoder B\n"); |
||
2327 | Serge | 1300 | } |
1301 | |||
1302 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
||
1303 | enum pipe pipe) |
||
1304 | { |
||
1305 | int reg; |
||
1306 | u32 val; |
||
1307 | |||
1308 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
||
1309 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
||
1310 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
||
1311 | |||
1312 | reg = PCH_ADPA; |
||
1313 | val = I915_READ(reg); |
||
3031 | serge | 1314 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
2327 | Serge | 1315 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1316 | pipe_name(pipe)); |
||
1317 | |||
1318 | reg = PCH_LVDS; |
||
1319 | val = I915_READ(reg); |
||
3031 | serge | 1320 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
2327 | Serge | 1321 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1322 | pipe_name(pipe)); |
||
1323 | |||
3746 | Serge | 1324 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1325 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
||
1326 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
||
2327 | Serge | 1327 | } |
1328 | |||
4104 | Serge | 1329 | static void vlv_enable_pll(struct intel_crtc *crtc) |
2327 | Serge | 1330 | { |
4104 | Serge | 1331 | struct drm_device *dev = crtc->base.dev; |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1333 | int reg = DPLL(crtc->pipe); |
||
1334 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
||
2327 | Serge | 1335 | |
4104 | Serge | 1336 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1337 | |||
2327 | Serge | 1338 | /* No really, not for ILK+ */ |
4104 | Serge | 1339 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
2327 | Serge | 1340 | |
1341 | /* PLL is protected by panel, make sure we can write it */ |
||
1342 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
||
4104 | Serge | 1343 | assert_panel_unlocked(dev_priv, crtc->pipe); |
2327 | Serge | 1344 | |
4104 | Serge | 1345 | I915_WRITE(reg, dpll); |
1346 | POSTING_READ(reg); |
||
1347 | udelay(150); |
||
2327 | Serge | 1348 | |
4104 | Serge | 1349 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
1350 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
||
1351 | |||
1352 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
||
1353 | POSTING_READ(DPLL_MD(crtc->pipe)); |
||
1354 | |||
1355 | /* We do this three times for luck */ |
||
1356 | I915_WRITE(reg, dpll); |
||
1357 | POSTING_READ(reg); |
||
1358 | udelay(150); /* wait for warmup */ |
||
1359 | I915_WRITE(reg, dpll); |
||
1360 | POSTING_READ(reg); |
||
1361 | udelay(150); /* wait for warmup */ |
||
1362 | I915_WRITE(reg, dpll); |
||
1363 | POSTING_READ(reg); |
||
1364 | udelay(150); /* wait for warmup */ |
||
1365 | } |
||
1366 | |||
1367 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
||
1368 | { |
||
1369 | struct drm_device *dev = crtc->base.dev; |
||
1370 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1371 | int reg = DPLL(crtc->pipe); |
||
1372 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
||
1373 | |||
1374 | assert_pipe_disabled(dev_priv, crtc->pipe); |
||
1375 | |||
1376 | /* No really, not for ILK+ */ |
||
1377 | BUG_ON(dev_priv->info->gen >= 5); |
||
1378 | |||
1379 | /* PLL is protected by panel, make sure we can write it */ |
||
1380 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
||
1381 | assert_panel_unlocked(dev_priv, crtc->pipe); |
||
1382 | |||
1383 | I915_WRITE(reg, dpll); |
||
1384 | |||
1385 | /* Wait for the clocks to stabilize. */ |
||
1386 | POSTING_READ(reg); |
||
1387 | udelay(150); |
||
1388 | |||
1389 | if (INTEL_INFO(dev)->gen >= 4) { |
||
1390 | I915_WRITE(DPLL_MD(crtc->pipe), |
||
1391 | crtc->config.dpll_hw_state.dpll_md); |
||
1392 | } else { |
||
1393 | /* The pixel multiplier can only be updated once the |
||
1394 | * DPLL is enabled and the clocks are stable. |
||
1395 | * |
||
1396 | * So write it again. |
||
1397 | */ |
||
1398 | I915_WRITE(reg, dpll); |
||
1399 | } |
||
1400 | |||
2327 | Serge | 1401 | /* We do this three times for luck */ |
4104 | Serge | 1402 | I915_WRITE(reg, dpll); |
2327 | Serge | 1403 | POSTING_READ(reg); |
1404 | udelay(150); /* wait for warmup */ |
||
4104 | Serge | 1405 | I915_WRITE(reg, dpll); |
2327 | Serge | 1406 | POSTING_READ(reg); |
1407 | udelay(150); /* wait for warmup */ |
||
4104 | Serge | 1408 | I915_WRITE(reg, dpll); |
2327 | Serge | 1409 | POSTING_READ(reg); |
1410 | udelay(150); /* wait for warmup */ |
||
1411 | } |
||
1412 | |||
1413 | /** |
||
4104 | Serge | 1414 | * i9xx_disable_pll - disable a PLL |
2327 | Serge | 1415 | * @dev_priv: i915 private structure |
1416 | * @pipe: pipe PLL to disable |
||
1417 | * |
||
1418 | * Disable the PLL for @pipe, making sure the pipe is off first. |
||
1419 | * |
||
1420 | * Note! This is for pre-ILK only. |
||
1421 | */ |
||
4104 | Serge | 1422 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
2327 | Serge | 1423 | { |
1424 | /* Don't disable pipe A or pipe A PLLs if needed */ |
||
1425 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
||
1426 | return; |
||
1427 | |||
1428 | /* Make sure the pipe isn't still relying on us */ |
||
1429 | assert_pipe_disabled(dev_priv, pipe); |
||
1430 | |||
4104 | Serge | 1431 | I915_WRITE(DPLL(pipe), 0); |
1432 | POSTING_READ(DPLL(pipe)); |
||
2327 | Serge | 1433 | } |
1434 | |||
4104 | Serge | 1435 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
3031 | serge | 1436 | { |
4104 | Serge | 1437 | u32 port_mask; |
3031 | serge | 1438 | |
4104 | Serge | 1439 | if (!port) |
1440 | port_mask = DPLL_PORTB_READY_MASK; |
||
3243 | Serge | 1441 | else |
4104 | Serge | 1442 | port_mask = DPLL_PORTC_READY_MASK; |
3243 | Serge | 1443 | |
4104 | Serge | 1444 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1445 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
||
1446 | 'B' + port, I915_READ(DPLL(0))); |
||
3031 | serge | 1447 | } |
1448 | |||
2327 | Serge | 1449 | /** |
4104 | Serge | 1450 | * ironlake_enable_shared_dpll - enable PCH PLL |
2327 | Serge | 1451 | * @dev_priv: i915 private structure |
1452 | * @pipe: pipe PLL to enable |
||
1453 | * |
||
1454 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
||
1455 | * drives the transcoder clock. |
||
1456 | */ |
||
4104 | Serge | 1457 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
2327 | Serge | 1458 | { |
4104 | Serge | 1459 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1460 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
||
2327 | Serge | 1461 | |
3031 | serge | 1462 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1463 | BUG_ON(dev_priv->info->gen < 5); |
||
4104 | Serge | 1464 | if (WARN_ON(pll == NULL)) |
2342 | Serge | 1465 | return; |
1466 | |||
3031 | serge | 1467 | if (WARN_ON(pll->refcount == 0)) |
1468 | return; |
||
2327 | Serge | 1469 | |
4104 | Serge | 1470 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1471 | pll->name, pll->active, pll->on, |
||
1472 | crtc->base.base.id); |
||
3031 | serge | 1473 | |
4104 | Serge | 1474 | if (pll->active++) { |
1475 | WARN_ON(!pll->on); |
||
1476 | assert_shared_dpll_enabled(dev_priv, pll); |
||
3031 | serge | 1477 | return; |
1478 | } |
||
4104 | Serge | 1479 | WARN_ON(pll->on); |
3031 | serge | 1480 | |
4104 | Serge | 1481 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1482 | pll->enable(dev_priv, pll); |
||
3031 | serge | 1483 | pll->on = true; |
2327 | Serge | 1484 | } |
1485 | |||
4104 | Serge | 1486 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
2327 | Serge | 1487 | { |
4104 | Serge | 1488 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1489 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
||
2327 | Serge | 1490 | |
1491 | /* PCH only available on ILK+ */ |
||
1492 | BUG_ON(dev_priv->info->gen < 5); |
||
4104 | Serge | 1493 | if (WARN_ON(pll == NULL)) |
3031 | serge | 1494 | return; |
2327 | Serge | 1495 | |
3031 | serge | 1496 | if (WARN_ON(pll->refcount == 0)) |
1497 | return; |
||
2327 | Serge | 1498 | |
4104 | Serge | 1499 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1500 | pll->name, pll->active, pll->on, |
||
1501 | crtc->base.base.id); |
||
2342 | Serge | 1502 | |
3031 | serge | 1503 | if (WARN_ON(pll->active == 0)) { |
4104 | Serge | 1504 | assert_shared_dpll_disabled(dev_priv, pll); |
3031 | serge | 1505 | return; |
1506 | } |
||
2342 | Serge | 1507 | |
4104 | Serge | 1508 | assert_shared_dpll_enabled(dev_priv, pll); |
1509 | WARN_ON(!pll->on); |
||
1510 | if (--pll->active) |
||
2342 | Serge | 1511 | return; |
1512 | |||
4104 | Serge | 1513 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1514 | pll->disable(dev_priv, pll); |
||
3031 | serge | 1515 | pll->on = false; |
2327 | Serge | 1516 | } |
1517 | |||
3243 | Serge | 1518 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
2327 | Serge | 1519 | enum pipe pipe) |
1520 | { |
||
3243 | Serge | 1521 | struct drm_device *dev = dev_priv->dev; |
3031 | serge | 1522 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
4104 | Serge | 1523 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3243 | Serge | 1524 | uint32_t reg, val, pipeconf_val; |
2327 | Serge | 1525 | |
1526 | /* PCH only available on ILK+ */ |
||
1527 | BUG_ON(dev_priv->info->gen < 5); |
||
1528 | |||
1529 | /* Make sure PCH DPLL is enabled */ |
||
4104 | Serge | 1530 | assert_shared_dpll_enabled(dev_priv, |
1531 | intel_crtc_to_shared_dpll(intel_crtc)); |
||
2327 | Serge | 1532 | |
1533 | /* FDI must be feeding us bits for PCH ports */ |
||
1534 | assert_fdi_tx_enabled(dev_priv, pipe); |
||
1535 | assert_fdi_rx_enabled(dev_priv, pipe); |
||
1536 | |||
3243 | Serge | 1537 | if (HAS_PCH_CPT(dev)) { |
1538 | /* Workaround: Set the timing override bit before enabling the |
||
1539 | * pch transcoder. */ |
||
1540 | reg = TRANS_CHICKEN2(pipe); |
||
1541 | val = I915_READ(reg); |
||
1542 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
||
1543 | I915_WRITE(reg, val); |
||
3031 | serge | 1544 | } |
3243 | Serge | 1545 | |
4104 | Serge | 1546 | reg = PCH_TRANSCONF(pipe); |
2327 | Serge | 1547 | val = I915_READ(reg); |
3031 | serge | 1548 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
2327 | Serge | 1549 | |
1550 | if (HAS_PCH_IBX(dev_priv->dev)) { |
||
1551 | /* |
||
1552 | * make the BPC in transcoder be consistent with |
||
1553 | * that in pipeconf reg. |
||
1554 | */ |
||
3480 | Serge | 1555 | val &= ~PIPECONF_BPC_MASK; |
1556 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
||
2327 | Serge | 1557 | } |
3031 | serge | 1558 | |
1559 | val &= ~TRANS_INTERLACE_MASK; |
||
1560 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
||
1561 | if (HAS_PCH_IBX(dev_priv->dev) && |
||
1562 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
||
1563 | val |= TRANS_LEGACY_INTERLACED_ILK; |
||
1564 | else |
||
1565 | val |= TRANS_INTERLACED; |
||
1566 | else |
||
1567 | val |= TRANS_PROGRESSIVE; |
||
1568 | |||
2327 | Serge | 1569 | I915_WRITE(reg, val | TRANS_ENABLE); |
1570 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
||
4104 | Serge | 1571 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
2327 | Serge | 1572 | } |
1573 | |||
3243 | Serge | 1574 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1575 | enum transcoder cpu_transcoder) |
||
1576 | { |
||
1577 | u32 val, pipeconf_val; |
||
1578 | |||
1579 | /* PCH only available on ILK+ */ |
||
1580 | BUG_ON(dev_priv->info->gen < 5); |
||
1581 | |||
1582 | /* FDI must be feeding us bits for PCH ports */ |
||
3480 | Serge | 1583 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
3243 | Serge | 1584 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
1585 | |||
1586 | /* Workaround: set timing override bit. */ |
||
1587 | val = I915_READ(_TRANSA_CHICKEN2); |
||
1588 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
||
1589 | I915_WRITE(_TRANSA_CHICKEN2, val); |
||
1590 | |||
1591 | val = TRANS_ENABLE; |
||
1592 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
||
1593 | |||
1594 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
||
1595 | PIPECONF_INTERLACED_ILK) |
||
1596 | val |= TRANS_INTERLACED; |
||
1597 | else |
||
1598 | val |= TRANS_PROGRESSIVE; |
||
1599 | |||
4104 | Serge | 1600 | I915_WRITE(LPT_TRANSCONF, val); |
1601 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
||
3243 | Serge | 1602 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
1603 | } |
||
1604 | |||
1605 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
||
2327 | Serge | 1606 | enum pipe pipe) |
1607 | { |
||
3243 | Serge | 1608 | struct drm_device *dev = dev_priv->dev; |
1609 | uint32_t reg, val; |
||
2327 | Serge | 1610 | |
1611 | /* FDI relies on the transcoder */ |
||
1612 | assert_fdi_tx_disabled(dev_priv, pipe); |
||
1613 | assert_fdi_rx_disabled(dev_priv, pipe); |
||
1614 | |||
1615 | /* Ports must be off as well */ |
||
1616 | assert_pch_ports_disabled(dev_priv, pipe); |
||
1617 | |||
4104 | Serge | 1618 | reg = PCH_TRANSCONF(pipe); |
2327 | Serge | 1619 | val = I915_READ(reg); |
1620 | val &= ~TRANS_ENABLE; |
||
1621 | I915_WRITE(reg, val); |
||
1622 | /* wait for PCH transcoder off, transcoder state */ |
||
1623 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
||
4104 | Serge | 1624 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
3243 | Serge | 1625 | |
1626 | if (!HAS_PCH_IBX(dev)) { |
||
1627 | /* Workaround: Clear the timing override chicken bit again. */ |
||
1628 | reg = TRANS_CHICKEN2(pipe); |
||
1629 | val = I915_READ(reg); |
||
1630 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
||
1631 | I915_WRITE(reg, val); |
||
1632 | } |
||
2327 | Serge | 1633 | } |
1634 | |||
3243 | Serge | 1635 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
1636 | { |
||
1637 | u32 val; |
||
1638 | |||
4104 | Serge | 1639 | val = I915_READ(LPT_TRANSCONF); |
3243 | Serge | 1640 | val &= ~TRANS_ENABLE; |
4104 | Serge | 1641 | I915_WRITE(LPT_TRANSCONF, val); |
3243 | Serge | 1642 | /* wait for PCH transcoder off, transcoder state */ |
4104 | Serge | 1643 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
3243 | Serge | 1644 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
1645 | |||
1646 | /* Workaround: clear timing override bit. */ |
||
1647 | val = I915_READ(_TRANSA_CHICKEN2); |
||
1648 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
||
1649 | I915_WRITE(_TRANSA_CHICKEN2, val); |
||
1650 | } |
||
1651 | |||
2327 | Serge | 1652 | /** |
1653 | * intel_enable_pipe - enable a pipe, asserting requirements |
||
1654 | * @dev_priv: i915 private structure |
||
1655 | * @pipe: pipe to enable |
||
1656 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
||
1657 | * |
||
1658 | * Enable @pipe, making sure that various hardware specific requirements |
||
1659 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
||
1660 | * |
||
1661 | * @pipe should be %PIPE_A or %PIPE_B. |
||
1662 | * |
||
1663 | * Will wait until the pipe is actually running (i.e. first vblank) before |
||
1664 | * returning. |
||
1665 | */ |
||
1666 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
||
1667 | bool pch_port) |
||
1668 | { |
||
3243 | Serge | 1669 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1670 | pipe); |
||
3480 | Serge | 1671 | enum pipe pch_transcoder; |
2327 | Serge | 1672 | int reg; |
1673 | u32 val; |
||
1674 | |||
4104 | Serge | 1675 | assert_planes_disabled(dev_priv, pipe); |
1676 | assert_sprites_disabled(dev_priv, pipe); |
||
1677 | |||
3480 | Serge | 1678 | if (HAS_PCH_LPT(dev_priv->dev)) |
3243 | Serge | 1679 | pch_transcoder = TRANSCODER_A; |
1680 | else |
||
1681 | pch_transcoder = pipe; |
||
1682 | |||
2327 | Serge | 1683 | /* |
1684 | * A pipe without a PLL won't actually be able to drive bits from |
||
1685 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
||
1686 | * need the check. |
||
1687 | */ |
||
1688 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
||
1689 | assert_pll_enabled(dev_priv, pipe); |
||
1690 | else { |
||
1691 | if (pch_port) { |
||
1692 | /* if driving the PCH, we need FDI enabled */ |
||
3243 | Serge | 1693 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
3480 | Serge | 1694 | assert_fdi_tx_pll_enabled(dev_priv, |
1695 | (enum pipe) cpu_transcoder); |
||
2327 | Serge | 1696 | } |
1697 | /* FIXME: assert CPU port conditions for SNB+ */ |
||
1698 | } |
||
1699 | |||
3243 | Serge | 1700 | reg = PIPECONF(cpu_transcoder); |
2327 | Serge | 1701 | val = I915_READ(reg); |
1702 | if (val & PIPECONF_ENABLE) |
||
1703 | return; |
||
1704 | |||
1705 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
||
1706 | intel_wait_for_vblank(dev_priv->dev, pipe); |
||
1707 | } |
||
1708 | |||
1709 | /** |
||
1710 | * intel_disable_pipe - disable a pipe, asserting requirements |
||
1711 | * @dev_priv: i915 private structure |
||
1712 | * @pipe: pipe to disable |
||
1713 | * |
||
1714 | * Disable @pipe, making sure that various hardware specific requirements |
||
1715 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
||
1716 | * |
||
1717 | * @pipe should be %PIPE_A or %PIPE_B. |
||
1718 | * |
||
1719 | * Will wait until the pipe has shut down before returning. |
||
1720 | */ |
||
1721 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
||
1722 | enum pipe pipe) |
||
1723 | { |
||
3243 | Serge | 1724 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1725 | pipe); |
||
2327 | Serge | 1726 | int reg; |
1727 | u32 val; |
||
1728 | |||
3031 | serge | 1729 | /* |
2327 | Serge | 1730 | * Make sure planes won't keep trying to pump pixels to us, |
1731 | * or we might hang the display. |
||
1732 | */ |
||
1733 | assert_planes_disabled(dev_priv, pipe); |
||
3746 | Serge | 1734 | assert_sprites_disabled(dev_priv, pipe); |
2327 | Serge | 1735 | |
1736 | /* Don't disable pipe A or pipe A PLLs if needed */ |
||
1737 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
||
1738 | return; |
||
1739 | |||
3243 | Serge | 1740 | reg = PIPECONF(cpu_transcoder); |
2327 | Serge | 1741 | val = I915_READ(reg); |
1742 | if ((val & PIPECONF_ENABLE) == 0) |
||
1743 | return; |
||
1744 | |||
1745 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
||
1746 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
||
1747 | } |
||
1748 | |||
1749 | /* |
||
1750 | * Plane regs are double buffered, going from enabled->disabled needs a |
||
1751 | * trigger in order to latch. The display address reg provides this. |
||
1752 | */ |
||
3031 | serge | 1753 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
2327 | Serge | 1754 | enum plane plane) |
1755 | { |
||
3243 | Serge | 1756 | if (dev_priv->info->gen >= 4) |
1757 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
||
1758 | else |
||
2327 | Serge | 1759 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
1760 | } |
||
1761 | |||
1762 | /** |
||
1763 | * intel_enable_plane - enable a display plane on a given pipe |
||
1764 | * @dev_priv: i915 private structure |
||
1765 | * @plane: plane to enable |
||
1766 | * @pipe: pipe being fed |
||
1767 | * |
||
1768 | * Enable @plane on @pipe, making sure that @pipe is running first. |
||
1769 | */ |
||
1770 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
||
1771 | enum plane plane, enum pipe pipe) |
||
1772 | { |
||
1773 | int reg; |
||
1774 | u32 val; |
||
1775 | |||
1776 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
||
1777 | assert_pipe_enabled(dev_priv, pipe); |
||
1778 | |||
1779 | reg = DSPCNTR(plane); |
||
1780 | val = I915_READ(reg); |
||
1781 | if (val & DISPLAY_PLANE_ENABLE) |
||
1782 | return; |
||
1783 | |||
1784 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
||
1785 | intel_flush_display_plane(dev_priv, plane); |
||
1786 | intel_wait_for_vblank(dev_priv->dev, pipe); |
||
1787 | } |
||
1788 | |||
1789 | /** |
||
1790 | * intel_disable_plane - disable a display plane |
||
1791 | * @dev_priv: i915 private structure |
||
1792 | * @plane: plane to disable |
||
1793 | * @pipe: pipe consuming the data |
||
1794 | * |
||
1795 | * Disable @plane; should be an independent operation. |
||
1796 | */ |
||
1797 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
||
1798 | enum plane plane, enum pipe pipe) |
||
1799 | { |
||
1800 | int reg; |
||
1801 | u32 val; |
||
1802 | |||
1803 | reg = DSPCNTR(plane); |
||
1804 | val = I915_READ(reg); |
||
1805 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
||
1806 | return; |
||
1807 | |||
1808 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
||
1809 | intel_flush_display_plane(dev_priv, plane); |
||
3031 | serge | 1810 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2327 | Serge | 1811 | } |
1812 | |||
3746 | Serge | 1813 | static bool need_vtd_wa(struct drm_device *dev) |
1814 | { |
||
1815 | #ifdef CONFIG_INTEL_IOMMU |
||
1816 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
||
1817 | return true; |
||
1818 | #endif |
||
1819 | return false; |
||
1820 | } |
||
1821 | |||
2335 | Serge | 1822 | int |
1823 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
||
1824 | struct drm_i915_gem_object *obj, |
||
1825 | struct intel_ring_buffer *pipelined) |
||
1826 | { |
||
1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1828 | u32 alignment; |
||
1829 | int ret; |
||
2327 | Serge | 1830 | |
2335 | Serge | 1831 | switch (obj->tiling_mode) { |
1832 | case I915_TILING_NONE: |
||
1833 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
||
1834 | alignment = 128 * 1024; |
||
1835 | else if (INTEL_INFO(dev)->gen >= 4) |
||
1836 | alignment = 4 * 1024; |
||
1837 | else |
||
1838 | alignment = 64 * 1024; |
||
1839 | break; |
||
1840 | case I915_TILING_X: |
||
1841 | /* pin() will align the object as required by fence */ |
||
1842 | alignment = 0; |
||
1843 | break; |
||
1844 | case I915_TILING_Y: |
||
3746 | Serge | 1845 | /* Despite that we check this in framebuffer_init userspace can |
1846 | * screw us over and change the tiling after the fact. Only |
||
1847 | * pinned buffers can't change their tiling. */ |
||
1848 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); |
||
2335 | Serge | 1849 | return -EINVAL; |
1850 | default: |
||
1851 | BUG(); |
||
1852 | } |
||
2327 | Serge | 1853 | |
3746 | Serge | 1854 | /* Note that the w/a also requires 64 PTE of padding following the |
1855 | * bo. We currently fill all unused PTE with the shadow page and so |
||
1856 | * we should always have valid PTE following the scanout preventing |
||
1857 | * the VT-d warning. |
||
1858 | */ |
||
1859 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
||
1860 | alignment = 256 * 1024; |
||
1861 | |||
2335 | Serge | 1862 | dev_priv->mm.interruptible = false; |
1863 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
||
1864 | if (ret) |
||
1865 | goto err_interruptible; |
||
2327 | Serge | 1866 | |
2335 | Serge | 1867 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1868 | * fence, whereas 965+ only requires a fence if using |
||
1869 | * framebuffer compression. For simplicity, we always install |
||
1870 | * a fence as the cost is not that onerous. |
||
1871 | */ |
||
3480 | Serge | 1872 | ret = i915_gem_object_get_fence(obj); |
1873 | if (ret) |
||
1874 | goto err_unpin; |
||
2327 | Serge | 1875 | |
3480 | Serge | 1876 | i915_gem_object_pin_fence(obj); |
1877 | |||
2335 | Serge | 1878 | dev_priv->mm.interruptible = true; |
1879 | return 0; |
||
2327 | Serge | 1880 | |
2335 | Serge | 1881 | err_unpin: |
4104 | Serge | 1882 | i915_gem_object_unpin_from_display_plane(obj); |
2335 | Serge | 1883 | err_interruptible: |
1884 | dev_priv->mm.interruptible = true; |
||
1885 | return ret; |
||
1886 | } |
||
2327 | Serge | 1887 | |
3031 | serge | 1888 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1889 | { |
||
1890 | // i915_gem_object_unpin_fence(obj); |
||
1891 | // i915_gem_object_unpin(obj); |
||
1892 | } |
||
1893 | |||
1894 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
||
1895 | * is assumed to be a power-of-two. */ |
||
3480 | Serge | 1896 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1897 | unsigned int tiling_mode, |
||
1898 | unsigned int cpp, |
||
3031 | serge | 1899 | unsigned int pitch) |
1900 | { |
||
3480 | Serge | 1901 | if (tiling_mode != I915_TILING_NONE) { |
1902 | unsigned int tile_rows, tiles; |
||
3031 | serge | 1903 | |
1904 | tile_rows = *y / 8; |
||
1905 | *y %= 8; |
||
1906 | |||
3480 | Serge | 1907 | tiles = *x / (512/cpp); |
1908 | *x %= 512/cpp; |
||
1909 | |||
3031 | serge | 1910 | return tile_rows * pitch * 8 + tiles * 4096; |
3480 | Serge | 1911 | } else { |
1912 | unsigned int offset; |
||
1913 | |||
1914 | offset = *y * pitch + *x * cpp; |
||
1915 | *y = 0; |
||
1916 | *x = (offset & 4095) / cpp; |
||
1917 | return offset & -4096; |
||
1918 | } |
||
3031 | serge | 1919 | } |
1920 | |||
2327 | Serge | 1921 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1922 | int x, int y) |
||
1923 | { |
||
1924 | struct drm_device *dev = crtc->dev; |
||
1925 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1926 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
1927 | struct intel_framebuffer *intel_fb; |
||
1928 | struct drm_i915_gem_object *obj; |
||
1929 | int plane = intel_crtc->plane; |
||
3031 | serge | 1930 | unsigned long linear_offset; |
2327 | Serge | 1931 | u32 dspcntr; |
1932 | u32 reg; |
||
1933 | |||
1934 | switch (plane) { |
||
1935 | case 0: |
||
1936 | case 1: |
||
1937 | break; |
||
1938 | default: |
||
4104 | Serge | 1939 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
2327 | Serge | 1940 | return -EINVAL; |
1941 | } |
||
1942 | |||
1943 | intel_fb = to_intel_framebuffer(fb); |
||
1944 | obj = intel_fb->obj; |
||
1945 | |||
1946 | reg = DSPCNTR(plane); |
||
1947 | dspcntr = I915_READ(reg); |
||
1948 | /* Mask out pixel format bits in case we change it */ |
||
1949 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
||
3243 | Serge | 1950 | switch (fb->pixel_format) { |
1951 | case DRM_FORMAT_C8: |
||
2327 | Serge | 1952 | dspcntr |= DISPPLANE_8BPP; |
1953 | break; |
||
3243 | Serge | 1954 | case DRM_FORMAT_XRGB1555: |
1955 | case DRM_FORMAT_ARGB1555: |
||
1956 | dspcntr |= DISPPLANE_BGRX555; |
||
1957 | break; |
||
1958 | case DRM_FORMAT_RGB565: |
||
1959 | dspcntr |= DISPPLANE_BGRX565; |
||
1960 | break; |
||
1961 | case DRM_FORMAT_XRGB8888: |
||
1962 | case DRM_FORMAT_ARGB8888: |
||
1963 | dspcntr |= DISPPLANE_BGRX888; |
||
1964 | break; |
||
1965 | case DRM_FORMAT_XBGR8888: |
||
1966 | case DRM_FORMAT_ABGR8888: |
||
1967 | dspcntr |= DISPPLANE_RGBX888; |
||
1968 | break; |
||
1969 | case DRM_FORMAT_XRGB2101010: |
||
1970 | case DRM_FORMAT_ARGB2101010: |
||
1971 | dspcntr |= DISPPLANE_BGRX101010; |
||
2327 | Serge | 1972 | break; |
3243 | Serge | 1973 | case DRM_FORMAT_XBGR2101010: |
1974 | case DRM_FORMAT_ABGR2101010: |
||
1975 | dspcntr |= DISPPLANE_RGBX101010; |
||
2327 | Serge | 1976 | break; |
1977 | default: |
||
3746 | Serge | 1978 | BUG(); |
2327 | Serge | 1979 | } |
3243 | Serge | 1980 | |
2327 | Serge | 1981 | if (INTEL_INFO(dev)->gen >= 4) { |
1982 | if (obj->tiling_mode != I915_TILING_NONE) |
||
1983 | dspcntr |= DISPPLANE_TILED; |
||
1984 | else |
||
1985 | dspcntr &= ~DISPPLANE_TILED; |
||
1986 | } |
||
1987 | |||
4104 | Serge | 1988 | if (IS_G4X(dev)) |
1989 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
||
1990 | |||
2327 | Serge | 1991 | I915_WRITE(reg, dspcntr); |
1992 | |||
3031 | serge | 1993 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2327 | Serge | 1994 | |
3031 | serge | 1995 | if (INTEL_INFO(dev)->gen >= 4) { |
1996 | intel_crtc->dspaddr_offset = |
||
3480 | Serge | 1997 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
3031 | serge | 1998 | fb->bits_per_pixel / 8, |
1999 | fb->pitches[0]); |
||
2000 | linear_offset -= intel_crtc->dspaddr_offset; |
||
2001 | } else { |
||
2002 | intel_crtc->dspaddr_offset = linear_offset; |
||
2003 | } |
||
2004 | |||
4104 | Serge | 2005 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2006 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
||
2007 | fb->pitches[0]); |
||
2342 | Serge | 2008 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2327 | Serge | 2009 | if (INTEL_INFO(dev)->gen >= 4) { |
3031 | serge | 2010 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
4104 | Serge | 2011 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2327 | Serge | 2012 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
3031 | serge | 2013 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2327 | Serge | 2014 | } else |
4104 | Serge | 2015 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2327 | Serge | 2016 | POSTING_READ(reg); |
2017 | |||
2018 | return 0; |
||
2019 | } |
||
2020 | |||
2021 | static int ironlake_update_plane(struct drm_crtc *crtc, |
||
2022 | struct drm_framebuffer *fb, int x, int y) |
||
2023 | { |
||
2024 | struct drm_device *dev = crtc->dev; |
||
2025 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2026 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2027 | struct intel_framebuffer *intel_fb; |
||
2028 | struct drm_i915_gem_object *obj; |
||
2029 | int plane = intel_crtc->plane; |
||
3031 | serge | 2030 | unsigned long linear_offset; |
2327 | Serge | 2031 | u32 dspcntr; |
2032 | u32 reg; |
||
2033 | |||
2034 | switch (plane) { |
||
2035 | case 0: |
||
2036 | case 1: |
||
2342 | Serge | 2037 | case 2: |
2327 | Serge | 2038 | break; |
2039 | default: |
||
4104 | Serge | 2040 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
2327 | Serge | 2041 | return -EINVAL; |
2042 | } |
||
2043 | |||
2044 | intel_fb = to_intel_framebuffer(fb); |
||
2045 | obj = intel_fb->obj; |
||
2046 | |||
2047 | reg = DSPCNTR(plane); |
||
2048 | dspcntr = I915_READ(reg); |
||
2049 | /* Mask out pixel format bits in case we change it */ |
||
2050 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
||
3243 | Serge | 2051 | switch (fb->pixel_format) { |
2052 | case DRM_FORMAT_C8: |
||
2327 | Serge | 2053 | dspcntr |= DISPPLANE_8BPP; |
2054 | break; |
||
3243 | Serge | 2055 | case DRM_FORMAT_RGB565: |
2056 | dspcntr |= DISPPLANE_BGRX565; |
||
2327 | Serge | 2057 | break; |
3243 | Serge | 2058 | case DRM_FORMAT_XRGB8888: |
2059 | case DRM_FORMAT_ARGB8888: |
||
2060 | dspcntr |= DISPPLANE_BGRX888; |
||
2061 | break; |
||
2062 | case DRM_FORMAT_XBGR8888: |
||
2063 | case DRM_FORMAT_ABGR8888: |
||
2064 | dspcntr |= DISPPLANE_RGBX888; |
||
2065 | break; |
||
2066 | case DRM_FORMAT_XRGB2101010: |
||
2067 | case DRM_FORMAT_ARGB2101010: |
||
2068 | dspcntr |= DISPPLANE_BGRX101010; |
||
2069 | break; |
||
2070 | case DRM_FORMAT_XBGR2101010: |
||
2071 | case DRM_FORMAT_ABGR2101010: |
||
2072 | dspcntr |= DISPPLANE_RGBX101010; |
||
2327 | Serge | 2073 | break; |
2074 | default: |
||
3746 | Serge | 2075 | BUG(); |
2327 | Serge | 2076 | } |
2077 | |||
3480 | Serge | 2078 | if (obj->tiling_mode != I915_TILING_NONE) |
2079 | dspcntr |= DISPPLANE_TILED; |
||
2080 | else |
||
2327 | Serge | 2081 | dspcntr &= ~DISPPLANE_TILED; |
2082 | |||
4104 | Serge | 2083 | if (IS_HASWELL(dev)) |
2084 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
||
2085 | else |
||
2327 | Serge | 2086 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2087 | |||
2088 | I915_WRITE(reg, dspcntr); |
||
2089 | |||
3031 | serge | 2090 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2091 | intel_crtc->dspaddr_offset = |
||
3480 | Serge | 2092 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
3031 | serge | 2093 | fb->bits_per_pixel / 8, |
2094 | fb->pitches[0]); |
||
2095 | linear_offset -= intel_crtc->dspaddr_offset; |
||
2327 | Serge | 2096 | |
4104 | Serge | 2097 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2098 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
||
2099 | fb->pitches[0]); |
||
2342 | Serge | 2100 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
3031 | serge | 2101 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
4104 | Serge | 2102 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
3243 | Serge | 2103 | if (IS_HASWELL(dev)) { |
2104 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
||
2105 | } else { |
||
2330 | Serge | 2106 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
3031 | serge | 2107 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
3243 | Serge | 2108 | } |
2330 | Serge | 2109 | POSTING_READ(reg); |
2327 | Serge | 2110 | |
2111 | return 0; |
||
2112 | } |
||
2113 | |||
2114 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
||
2115 | static int |
||
2116 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
||
2117 | int x, int y, enum mode_set_atomic state) |
||
2118 | { |
||
2119 | struct drm_device *dev = crtc->dev; |
||
2120 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 2121 | |
2122 | if (dev_priv->display.disable_fbc) |
||
2123 | dev_priv->display.disable_fbc(dev); |
||
2124 | intel_increase_pllclock(crtc); |
||
2125 | |||
2126 | return dev_priv->display.update_plane(crtc, fb, x, y); |
||
2127 | } |
||
2128 | |||
2129 | #if 0 |
||
4104 | Serge | 2130 | void intel_display_handle_reset(struct drm_device *dev) |
2131 | { |
||
2132 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2133 | struct drm_crtc *crtc; |
||
2134 | |||
2135 | /* |
||
2136 | * Flips in the rings have been nuked by the reset, |
||
2137 | * so complete all pending flips so that user space |
||
2138 | * will get its events and not get stuck. |
||
2139 | * |
||
2140 | * Also update the base address of all primary |
||
2141 | * planes to the the last fb to make sure we're |
||
2142 | * showing the correct fb after a reset. |
||
2143 | * |
||
2144 | * Need to make two loops over the crtcs so that we |
||
2145 | * don't try to grab a crtc mutex before the |
||
2146 | * pending_flip_queue really got woken up. |
||
2147 | */ |
||
2148 | |||
2149 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
||
2150 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2151 | enum plane plane = intel_crtc->plane; |
||
2152 | |||
2153 | intel_prepare_page_flip(dev, plane); |
||
2154 | intel_finish_page_flip_plane(dev, plane); |
||
2155 | } |
||
2156 | |||
2157 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
||
2158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2159 | |||
2160 | mutex_lock(&crtc->mutex); |
||
2161 | if (intel_crtc->active) |
||
2162 | dev_priv->display.update_plane(crtc, crtc->fb, |
||
2163 | crtc->x, crtc->y); |
||
2164 | mutex_unlock(&crtc->mutex); |
||
2165 | } |
||
2166 | } |
||
2167 | |||
3031 | serge | 2168 | static int |
2169 | intel_finish_fb(struct drm_framebuffer *old_fb) |
||
2170 | { |
||
2171 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
||
2172 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
2173 | bool was_interruptible = dev_priv->mm.interruptible; |
||
2327 | Serge | 2174 | int ret; |
2175 | |||
3031 | serge | 2176 | /* Big Hammer, we also need to ensure that any pending |
2177 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
||
2178 | * current scanout is retired before unpinning the old |
||
2179 | * framebuffer. |
||
2180 | * |
||
2181 | * This should only fail upon a hung GPU, in which case we |
||
2182 | * can safely continue. |
||
2183 | */ |
||
2184 | dev_priv->mm.interruptible = false; |
||
2185 | ret = i915_gem_object_finish_gpu(obj); |
||
2186 | dev_priv->mm.interruptible = was_interruptible; |
||
2327 | Serge | 2187 | |
3031 | serge | 2188 | return ret; |
2327 | Serge | 2189 | } |
4104 | Serge | 2190 | |
2191 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
||
2192 | { |
||
2193 | struct drm_device *dev = crtc->dev; |
||
2194 | struct drm_i915_master_private *master_priv; |
||
2195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2196 | |||
2197 | if (!dev->primary->master) |
||
2198 | return; |
||
2199 | |||
2200 | master_priv = dev->primary->master->driver_priv; |
||
2201 | if (!master_priv->sarea_priv) |
||
2202 | return; |
||
2203 | |||
2204 | switch (intel_crtc->pipe) { |
||
2205 | case 0: |
||
2206 | master_priv->sarea_priv->pipeA_x = x; |
||
2207 | master_priv->sarea_priv->pipeA_y = y; |
||
2208 | break; |
||
2209 | case 1: |
||
2210 | master_priv->sarea_priv->pipeB_x = x; |
||
2211 | master_priv->sarea_priv->pipeB_y = y; |
||
2212 | break; |
||
2213 | default: |
||
2214 | break; |
||
2215 | } |
||
2216 | } |
||
3031 | serge | 2217 | #endif |
2327 | Serge | 2218 | |
2219 | static int |
||
2220 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
||
3031 | serge | 2221 | struct drm_framebuffer *fb) |
2327 | Serge | 2222 | { |
2223 | struct drm_device *dev = crtc->dev; |
||
3031 | serge | 2224 | struct drm_i915_private *dev_priv = dev->dev_private; |
2327 | Serge | 2225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3031 | serge | 2226 | struct drm_framebuffer *old_fb; |
2342 | Serge | 2227 | int ret; |
2327 | Serge | 2228 | |
2229 | /* no fb bound */ |
||
3031 | serge | 2230 | if (!fb) { |
2327 | Serge | 2231 | DRM_ERROR("No FB bound\n"); |
2232 | return 0; |
||
2233 | } |
||
2234 | |||
3746 | Serge | 2235 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
4104 | Serge | 2236 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2237 | plane_name(intel_crtc->plane), |
||
3746 | Serge | 2238 | INTEL_INFO(dev)->num_pipes); |
2327 | Serge | 2239 | return -EINVAL; |
2240 | } |
||
2241 | |||
2242 | mutex_lock(&dev->struct_mutex); |
||
4280 | Serge | 2243 | ret = intel_pin_and_fence_fb_obj(dev, |
2244 | to_intel_framebuffer(fb)->obj, |
||
2245 | NULL); |
||
2246 | if (ret != 0) { |
||
2247 | mutex_unlock(&dev->struct_mutex); |
||
2248 | DRM_ERROR("pin & fence failed\n"); |
||
2249 | return ret; |
||
2250 | } |
||
2327 | Serge | 2251 | |
4280 | Serge | 2252 | /* Update pipe size and adjust fitter if needed */ |
2253 | if (i915_fastboot) { |
||
2254 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
||
2255 | ((crtc->mode.hdisplay - 1) << 16) | |
||
2256 | (crtc->mode.vdisplay - 1)); |
||
2257 | if (!intel_crtc->config.pch_pfit.enabled && |
||
2258 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
||
2259 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
||
2260 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
||
2261 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
||
2262 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
||
2263 | } |
||
2264 | } |
||
3031 | serge | 2265 | |
2266 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
||
2327 | Serge | 2267 | if (ret) { |
3031 | serge | 2268 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2327 | Serge | 2269 | mutex_unlock(&dev->struct_mutex); |
2270 | DRM_ERROR("failed to update base address\n"); |
||
3243 | Serge | 2271 | return ret; |
2327 | Serge | 2272 | } |
2273 | |||
3031 | serge | 2274 | old_fb = crtc->fb; |
2275 | crtc->fb = fb; |
||
2276 | crtc->x = x; |
||
2277 | crtc->y = y; |
||
2278 | |||
2279 | if (old_fb) { |
||
4104 | Serge | 2280 | if (intel_crtc->active && old_fb != fb) |
3031 | serge | 2281 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2282 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
||
2283 | } |
||
2284 | |||
2285 | intel_update_fbc(dev); |
||
4104 | Serge | 2286 | intel_edp_psr_update(dev); |
2336 | Serge | 2287 | mutex_unlock(&dev->struct_mutex); |
2327 | Serge | 2288 | |
2336 | Serge | 2289 | return 0; |
2327 | Serge | 2290 | } |
2291 | |||
2292 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
||
2293 | { |
||
2294 | struct drm_device *dev = crtc->dev; |
||
2295 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2297 | int pipe = intel_crtc->pipe; |
||
2298 | u32 reg, temp; |
||
2299 | |||
2300 | /* enable normal train */ |
||
2301 | reg = FDI_TX_CTL(pipe); |
||
2302 | temp = I915_READ(reg); |
||
2303 | if (IS_IVYBRIDGE(dev)) { |
||
2304 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
||
2305 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
||
2306 | } else { |
||
2307 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2308 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
||
2309 | } |
||
2310 | I915_WRITE(reg, temp); |
||
2311 | |||
2312 | reg = FDI_RX_CTL(pipe); |
||
2313 | temp = I915_READ(reg); |
||
2314 | if (HAS_PCH_CPT(dev)) { |
||
2315 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2316 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
||
2317 | } else { |
||
2318 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2319 | temp |= FDI_LINK_TRAIN_NONE; |
||
2320 | } |
||
2321 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
||
2322 | |||
2323 | /* wait one idle pattern time */ |
||
2324 | POSTING_READ(reg); |
||
2325 | udelay(1000); |
||
2326 | |||
2327 | /* IVB wants error correction enabled */ |
||
2328 | if (IS_IVYBRIDGE(dev)) |
||
2329 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
||
2330 | FDI_FE_ERRC_ENABLE); |
||
2331 | } |
||
2332 | |||
4280 | Serge | 2333 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
4104 | Serge | 2334 | { |
4280 | Serge | 2335 | return crtc->base.enabled && crtc->active && |
2336 | crtc->config.has_pch_encoder; |
||
4104 | Serge | 2337 | } |
2338 | |||
3243 | Serge | 2339 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2327 | Serge | 2340 | { |
2341 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3243 | Serge | 2342 | struct intel_crtc *pipe_B_crtc = |
2343 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
||
2344 | struct intel_crtc *pipe_C_crtc = |
||
2345 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
||
2346 | uint32_t temp; |
||
2327 | Serge | 2347 | |
4104 | Serge | 2348 | /* |
2349 | * When everything is off disable fdi C so that we could enable fdi B |
||
2350 | * with all lanes. Note that we don't care about enabled pipes without |
||
2351 | * an enabled pch encoder. |
||
2352 | */ |
||
2353 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
||
2354 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
||
3243 | Serge | 2355 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2356 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
||
2357 | |||
2358 | temp = I915_READ(SOUTH_CHICKEN1); |
||
2359 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
||
2360 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
||
2361 | I915_WRITE(SOUTH_CHICKEN1, temp); |
||
2362 | } |
||
2327 | Serge | 2363 | } |
2364 | |||
2365 | /* The FDI link training functions for ILK/Ibexpeak. */ |
||
2366 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
||
2367 | { |
||
2368 | struct drm_device *dev = crtc->dev; |
||
2369 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2370 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2371 | int pipe = intel_crtc->pipe; |
||
2372 | int plane = intel_crtc->plane; |
||
2373 | u32 reg, temp, tries; |
||
2374 | |||
2375 | /* FDI needs bits from pipe & plane first */ |
||
2376 | assert_pipe_enabled(dev_priv, pipe); |
||
2377 | assert_plane_enabled(dev_priv, plane); |
||
2378 | |||
2379 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
||
2380 | for train result */ |
||
2381 | reg = FDI_RX_IMR(pipe); |
||
2382 | temp = I915_READ(reg); |
||
2383 | temp &= ~FDI_RX_SYMBOL_LOCK; |
||
2384 | temp &= ~FDI_RX_BIT_LOCK; |
||
2385 | I915_WRITE(reg, temp); |
||
2386 | I915_READ(reg); |
||
2387 | udelay(150); |
||
2388 | |||
2389 | /* enable CPU FDI TX and PCH FDI RX */ |
||
2390 | reg = FDI_TX_CTL(pipe); |
||
2391 | temp = I915_READ(reg); |
||
4104 | Serge | 2392 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2393 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
||
2327 | Serge | 2394 | temp &= ~FDI_LINK_TRAIN_NONE; |
2395 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2396 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
||
2397 | |||
2398 | reg = FDI_RX_CTL(pipe); |
||
2399 | temp = I915_READ(reg); |
||
2400 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2401 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2402 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
||
2403 | |||
2404 | POSTING_READ(reg); |
||
2405 | udelay(150); |
||
2406 | |||
2407 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
||
2408 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
||
2409 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
||
2410 | FDI_RX_PHASE_SYNC_POINTER_EN); |
||
2411 | |||
2412 | reg = FDI_RX_IIR(pipe); |
||
2413 | for (tries = 0; tries < 5; tries++) { |
||
2414 | temp = I915_READ(reg); |
||
2415 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2416 | |||
2417 | if ((temp & FDI_RX_BIT_LOCK)) { |
||
2418 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
||
2419 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
||
2420 | break; |
||
2421 | } |
||
2422 | } |
||
2423 | if (tries == 5) |
||
2424 | DRM_ERROR("FDI train 1 fail!\n"); |
||
2425 | |||
2426 | /* Train 2 */ |
||
2427 | reg = FDI_TX_CTL(pipe); |
||
2428 | temp = I915_READ(reg); |
||
2429 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2430 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
||
2431 | I915_WRITE(reg, temp); |
||
2432 | |||
2433 | reg = FDI_RX_CTL(pipe); |
||
2434 | temp = I915_READ(reg); |
||
2435 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2436 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
||
2437 | I915_WRITE(reg, temp); |
||
2438 | |||
2439 | POSTING_READ(reg); |
||
2440 | udelay(150); |
||
2441 | |||
2442 | reg = FDI_RX_IIR(pipe); |
||
2443 | for (tries = 0; tries < 5; tries++) { |
||
2444 | temp = I915_READ(reg); |
||
2445 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2446 | |||
2447 | if (temp & FDI_RX_SYMBOL_LOCK) { |
||
2448 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
||
2449 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
||
2450 | break; |
||
2451 | } |
||
2452 | } |
||
2453 | if (tries == 5) |
||
2454 | DRM_ERROR("FDI train 2 fail!\n"); |
||
2455 | |||
2456 | DRM_DEBUG_KMS("FDI train done\n"); |
||
2457 | |||
2458 | } |
||
2459 | |||
2342 | Serge | 2460 | static const int snb_b_fdi_train_param[] = { |
2327 | Serge | 2461 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2462 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
||
2463 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
||
2464 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
||
2465 | }; |
||
2466 | |||
2467 | /* The FDI link training functions for SNB/Cougarpoint. */ |
||
2468 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
||
2469 | { |
||
2470 | struct drm_device *dev = crtc->dev; |
||
2471 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2472 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2473 | int pipe = intel_crtc->pipe; |
||
3031 | serge | 2474 | u32 reg, temp, i, retry; |
2327 | Serge | 2475 | |
2476 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
||
2477 | for train result */ |
||
2478 | reg = FDI_RX_IMR(pipe); |
||
2479 | temp = I915_READ(reg); |
||
2480 | temp &= ~FDI_RX_SYMBOL_LOCK; |
||
2481 | temp &= ~FDI_RX_BIT_LOCK; |
||
2482 | I915_WRITE(reg, temp); |
||
2483 | |||
2484 | POSTING_READ(reg); |
||
2485 | udelay(150); |
||
2486 | |||
2487 | /* enable CPU FDI TX and PCH FDI RX */ |
||
2488 | reg = FDI_TX_CTL(pipe); |
||
2489 | temp = I915_READ(reg); |
||
4104 | Serge | 2490 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2491 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
||
2327 | Serge | 2492 | temp &= ~FDI_LINK_TRAIN_NONE; |
2493 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2494 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2495 | /* SNB-B */ |
||
2496 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
||
2497 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
||
2498 | |||
3243 | Serge | 2499 | I915_WRITE(FDI_RX_MISC(pipe), |
2500 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
||
2501 | |||
2327 | Serge | 2502 | reg = FDI_RX_CTL(pipe); |
2503 | temp = I915_READ(reg); |
||
2504 | if (HAS_PCH_CPT(dev)) { |
||
2505 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2506 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
||
2507 | } else { |
||
2508 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2509 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2510 | } |
||
2511 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
||
2512 | |||
2513 | POSTING_READ(reg); |
||
2514 | udelay(150); |
||
2515 | |||
2342 | Serge | 2516 | for (i = 0; i < 4; i++) { |
2327 | Serge | 2517 | reg = FDI_TX_CTL(pipe); |
2518 | temp = I915_READ(reg); |
||
2519 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2520 | temp |= snb_b_fdi_train_param[i]; |
||
2521 | I915_WRITE(reg, temp); |
||
2522 | |||
2523 | POSTING_READ(reg); |
||
2524 | udelay(500); |
||
2525 | |||
3031 | serge | 2526 | for (retry = 0; retry < 5; retry++) { |
2327 | Serge | 2527 | reg = FDI_RX_IIR(pipe); |
2528 | temp = I915_READ(reg); |
||
2529 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2530 | if (temp & FDI_RX_BIT_LOCK) { |
||
2531 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
||
2532 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
||
2533 | break; |
||
2534 | } |
||
3031 | serge | 2535 | udelay(50); |
2536 | } |
||
2537 | if (retry < 5) |
||
2538 | break; |
||
2327 | Serge | 2539 | } |
2540 | if (i == 4) |
||
2541 | DRM_ERROR("FDI train 1 fail!\n"); |
||
2542 | |||
2543 | /* Train 2 */ |
||
2544 | reg = FDI_TX_CTL(pipe); |
||
2545 | temp = I915_READ(reg); |
||
2546 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2547 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
||
2548 | if (IS_GEN6(dev)) { |
||
2549 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2550 | /* SNB-B */ |
||
2551 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
||
2552 | } |
||
2553 | I915_WRITE(reg, temp); |
||
2554 | |||
2555 | reg = FDI_RX_CTL(pipe); |
||
2556 | temp = I915_READ(reg); |
||
2557 | if (HAS_PCH_CPT(dev)) { |
||
2558 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2559 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
||
2560 | } else { |
||
2561 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2562 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
||
2563 | } |
||
2564 | I915_WRITE(reg, temp); |
||
2565 | |||
2566 | POSTING_READ(reg); |
||
2567 | udelay(150); |
||
2568 | |||
2342 | Serge | 2569 | for (i = 0; i < 4; i++) { |
2327 | Serge | 2570 | reg = FDI_TX_CTL(pipe); |
2571 | temp = I915_READ(reg); |
||
2572 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2573 | temp |= snb_b_fdi_train_param[i]; |
||
2574 | I915_WRITE(reg, temp); |
||
2575 | |||
2576 | POSTING_READ(reg); |
||
2577 | udelay(500); |
||
2578 | |||
3031 | serge | 2579 | for (retry = 0; retry < 5; retry++) { |
2327 | Serge | 2580 | reg = FDI_RX_IIR(pipe); |
2581 | temp = I915_READ(reg); |
||
2582 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2583 | if (temp & FDI_RX_SYMBOL_LOCK) { |
||
2584 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
||
2585 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
||
2586 | break; |
||
2587 | } |
||
3031 | serge | 2588 | udelay(50); |
2589 | } |
||
2590 | if (retry < 5) |
||
2591 | break; |
||
2327 | Serge | 2592 | } |
2593 | if (i == 4) |
||
2594 | DRM_ERROR("FDI train 2 fail!\n"); |
||
2595 | |||
2596 | DRM_DEBUG_KMS("FDI train done.\n"); |
||
2597 | } |
||
2598 | |||
2599 | /* Manual link training for Ivy Bridge A0 parts */ |
||
2600 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
||
2601 | { |
||
2602 | struct drm_device *dev = crtc->dev; |
||
2603 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2605 | int pipe = intel_crtc->pipe; |
||
4104 | Serge | 2606 | u32 reg, temp, i, j; |
2327 | Serge | 2607 | |
2608 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
||
2609 | for train result */ |
||
2610 | reg = FDI_RX_IMR(pipe); |
||
2611 | temp = I915_READ(reg); |
||
2612 | temp &= ~FDI_RX_SYMBOL_LOCK; |
||
2613 | temp &= ~FDI_RX_BIT_LOCK; |
||
2614 | I915_WRITE(reg, temp); |
||
2615 | |||
2616 | POSTING_READ(reg); |
||
2617 | udelay(150); |
||
2618 | |||
3243 | Serge | 2619 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2620 | I915_READ(FDI_RX_IIR(pipe))); |
||
2621 | |||
4104 | Serge | 2622 | /* Try each vswing and preemphasis setting twice before moving on */ |
2623 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
||
2624 | /* disable first in case we need to retry */ |
||
2625 | reg = FDI_TX_CTL(pipe); |
||
2626 | temp = I915_READ(reg); |
||
2627 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
||
2628 | temp &= ~FDI_TX_ENABLE; |
||
2629 | I915_WRITE(reg, temp); |
||
2630 | |||
2631 | reg = FDI_RX_CTL(pipe); |
||
2632 | temp = I915_READ(reg); |
||
2633 | temp &= ~FDI_LINK_TRAIN_AUTO; |
||
2634 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2635 | temp &= ~FDI_RX_ENABLE; |
||
2636 | I915_WRITE(reg, temp); |
||
2637 | |||
2327 | Serge | 2638 | /* enable CPU FDI TX and PCH FDI RX */ |
2639 | reg = FDI_TX_CTL(pipe); |
||
2640 | temp = I915_READ(reg); |
||
4104 | Serge | 2641 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2642 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
||
2327 | Serge | 2643 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2644 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
4104 | Serge | 2645 | temp |= snb_b_fdi_train_param[j/2]; |
2342 | Serge | 2646 | temp |= FDI_COMPOSITE_SYNC; |
2327 | Serge | 2647 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2648 | |||
3243 | Serge | 2649 | I915_WRITE(FDI_RX_MISC(pipe), |
2650 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
||
2651 | |||
2327 | Serge | 2652 | reg = FDI_RX_CTL(pipe); |
2653 | temp = I915_READ(reg); |
||
2654 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
||
2342 | Serge | 2655 | temp |= FDI_COMPOSITE_SYNC; |
2327 | Serge | 2656 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2657 | |||
2658 | POSTING_READ(reg); |
||
4104 | Serge | 2659 | udelay(1); /* should be 0.5us */ |
2327 | Serge | 2660 | |
2342 | Serge | 2661 | for (i = 0; i < 4; i++) { |
2327 | Serge | 2662 | reg = FDI_RX_IIR(pipe); |
2663 | temp = I915_READ(reg); |
||
2664 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2665 | |||
2666 | if (temp & FDI_RX_BIT_LOCK || |
||
2667 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
||
2668 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
||
4104 | Serge | 2669 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
2670 | i); |
||
2327 | Serge | 2671 | break; |
2672 | } |
||
4104 | Serge | 2673 | udelay(1); /* should be 0.5us */ |
2674 | } |
||
2675 | if (i == 4) { |
||
2676 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
||
2677 | continue; |
||
2327 | Serge | 2678 | } |
2679 | |||
2680 | /* Train 2 */ |
||
2681 | reg = FDI_TX_CTL(pipe); |
||
2682 | temp = I915_READ(reg); |
||
2683 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
||
2684 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
||
2685 | I915_WRITE(reg, temp); |
||
2686 | |||
2687 | reg = FDI_RX_CTL(pipe); |
||
2688 | temp = I915_READ(reg); |
||
2689 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2690 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
||
2691 | I915_WRITE(reg, temp); |
||
2692 | |||
2693 | POSTING_READ(reg); |
||
4104 | Serge | 2694 | udelay(2); /* should be 1.5us */ |
2327 | Serge | 2695 | |
2342 | Serge | 2696 | for (i = 0; i < 4; i++) { |
2327 | Serge | 2697 | reg = FDI_RX_IIR(pipe); |
2698 | temp = I915_READ(reg); |
||
2699 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2700 | |||
4104 | Serge | 2701 | if (temp & FDI_RX_SYMBOL_LOCK || |
2702 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
||
2327 | Serge | 2703 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
4104 | Serge | 2704 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
2705 | i); |
||
2706 | goto train_done; |
||
2327 | Serge | 2707 | } |
4104 | Serge | 2708 | udelay(2); /* should be 1.5us */ |
2327 | Serge | 2709 | } |
2710 | if (i == 4) |
||
4104 | Serge | 2711 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
2712 | } |
||
2327 | Serge | 2713 | |
4104 | Serge | 2714 | train_done: |
2327 | Serge | 2715 | DRM_DEBUG_KMS("FDI train done.\n"); |
2716 | } |
||
2717 | |||
3031 | serge | 2718 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2327 | Serge | 2719 | { |
3031 | serge | 2720 | struct drm_device *dev = intel_crtc->base.dev; |
2327 | Serge | 2721 | struct drm_i915_private *dev_priv = dev->dev_private; |
2722 | int pipe = intel_crtc->pipe; |
||
2723 | u32 reg, temp; |
||
2724 | |||
2725 | |||
2726 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
||
2727 | reg = FDI_RX_CTL(pipe); |
||
2728 | temp = I915_READ(reg); |
||
4104 | Serge | 2729 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2730 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
||
3480 | Serge | 2731 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2327 | Serge | 2732 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2733 | |||
2734 | POSTING_READ(reg); |
||
2735 | udelay(200); |
||
2736 | |||
2737 | /* Switch from Rawclk to PCDclk */ |
||
2738 | temp = I915_READ(reg); |
||
2739 | I915_WRITE(reg, temp | FDI_PCDCLK); |
||
2740 | |||
2741 | POSTING_READ(reg); |
||
2742 | udelay(200); |
||
2743 | |||
2744 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
||
2745 | reg = FDI_TX_CTL(pipe); |
||
2746 | temp = I915_READ(reg); |
||
2747 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
||
2748 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
||
2749 | |||
2750 | POSTING_READ(reg); |
||
2751 | udelay(100); |
||
2752 | } |
||
2753 | } |
||
2754 | |||
3031 | serge | 2755 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2756 | { |
||
2757 | struct drm_device *dev = intel_crtc->base.dev; |
||
2758 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2759 | int pipe = intel_crtc->pipe; |
||
2760 | u32 reg, temp; |
||
2761 | |||
2762 | /* Switch from PCDclk to Rawclk */ |
||
2763 | reg = FDI_RX_CTL(pipe); |
||
2764 | temp = I915_READ(reg); |
||
2765 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
||
2766 | |||
2767 | /* Disable CPU FDI TX PLL */ |
||
2768 | reg = FDI_TX_CTL(pipe); |
||
2769 | temp = I915_READ(reg); |
||
2770 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
||
2771 | |||
2772 | POSTING_READ(reg); |
||
2773 | udelay(100); |
||
2774 | |||
2775 | reg = FDI_RX_CTL(pipe); |
||
2776 | temp = I915_READ(reg); |
||
2777 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
||
2778 | |||
2779 | /* Wait for the clocks to turn off. */ |
||
2780 | POSTING_READ(reg); |
||
2781 | udelay(100); |
||
2782 | } |
||
2783 | |||
2327 | Serge | 2784 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2785 | { |
||
2786 | struct drm_device *dev = crtc->dev; |
||
2787 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2789 | int pipe = intel_crtc->pipe; |
||
2790 | u32 reg, temp; |
||
2791 | |||
2792 | /* disable CPU FDI tx and PCH FDI rx */ |
||
2793 | reg = FDI_TX_CTL(pipe); |
||
2794 | temp = I915_READ(reg); |
||
2795 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
||
2796 | POSTING_READ(reg); |
||
2797 | |||
2798 | reg = FDI_RX_CTL(pipe); |
||
2799 | temp = I915_READ(reg); |
||
2800 | temp &= ~(0x7 << 16); |
||
3480 | Serge | 2801 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2327 | Serge | 2802 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2803 | |||
2804 | POSTING_READ(reg); |
||
2805 | udelay(100); |
||
2806 | |||
2807 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
||
2808 | if (HAS_PCH_IBX(dev)) { |
||
2809 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
||
2810 | } |
||
2811 | |||
2812 | /* still set train pattern 1 */ |
||
2813 | reg = FDI_TX_CTL(pipe); |
||
2814 | temp = I915_READ(reg); |
||
2815 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2816 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2817 | I915_WRITE(reg, temp); |
||
2818 | |||
2819 | reg = FDI_RX_CTL(pipe); |
||
2820 | temp = I915_READ(reg); |
||
2821 | if (HAS_PCH_CPT(dev)) { |
||
2822 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2823 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
||
2824 | } else { |
||
2825 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2826 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2827 | } |
||
2828 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
||
2829 | temp &= ~(0x07 << 16); |
||
3480 | Serge | 2830 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2327 | Serge | 2831 | I915_WRITE(reg, temp); |
2832 | |||
2833 | POSTING_READ(reg); |
||
2834 | udelay(100); |
||
2835 | } |
||
2836 | |||
3031 | serge | 2837 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2327 | Serge | 2838 | { |
3031 | serge | 2839 | struct drm_device *dev = crtc->dev; |
2327 | Serge | 2840 | struct drm_i915_private *dev_priv = dev->dev_private; |
3480 | Serge | 2841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3031 | serge | 2842 | unsigned long flags; |
2843 | bool pending; |
||
2327 | Serge | 2844 | |
3480 | Serge | 2845 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2846 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
||
3031 | serge | 2847 | return false; |
2327 | Serge | 2848 | |
3031 | serge | 2849 | spin_lock_irqsave(&dev->event_lock, flags); |
2850 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
||
2851 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
2852 | |||
2853 | return pending; |
||
2327 | Serge | 2854 | } |
2855 | |||
3031 | serge | 2856 | #if 0 |
2327 | Serge | 2857 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2858 | { |
||
3031 | serge | 2859 | struct drm_device *dev = crtc->dev; |
2860 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 2861 | |
2862 | if (crtc->fb == NULL) |
||
2863 | return; |
||
2864 | |||
3480 | Serge | 2865 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2866 | |||
2360 | Serge | 2867 | wait_event(dev_priv->pending_flip_queue, |
3031 | serge | 2868 | !intel_crtc_has_pending_flip(crtc)); |
2869 | |||
2870 | mutex_lock(&dev->struct_mutex); |
||
2871 | intel_finish_fb(crtc->fb); |
||
2872 | mutex_unlock(&dev->struct_mutex); |
||
2327 | Serge | 2873 | } |
3031 | serge | 2874 | #endif |
2327 | Serge | 2875 | |
3031 | serge | 2876 | /* Program iCLKIP clock to the desired frequency */ |
2877 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
||
2878 | { |
||
2879 | struct drm_device *dev = crtc->dev; |
||
2880 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2881 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
||
2882 | u32 temp; |
||
2883 | |||
3480 | Serge | 2884 | mutex_lock(&dev_priv->dpio_lock); |
2885 | |||
3031 | serge | 2886 | /* It is necessary to ungate the pixclk gate prior to programming |
2887 | * the divisors, and gate it back when it is done. |
||
2888 | */ |
||
2889 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
||
2890 | |||
2891 | /* Disable SSCCTL */ |
||
2892 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
||
3243 | Serge | 2893 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2894 | SBI_SSCCTL_DISABLE, |
||
2895 | SBI_ICLK); |
||
3031 | serge | 2896 | |
2897 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
||
2898 | if (crtc->mode.clock == 20000) { |
||
2899 | auxdiv = 1; |
||
2900 | divsel = 0x41; |
||
2901 | phaseinc = 0x20; |
||
2902 | } else { |
||
2903 | /* The iCLK virtual clock root frequency is in MHz, |
||
2904 | * but the crtc->mode.clock in in KHz. To get the divisors, |
||
2905 | * it is necessary to divide one by another, so we |
||
2906 | * convert the virtual clock precision to KHz here for higher |
||
2907 | * precision. |
||
2908 | */ |
||
2909 | u32 iclk_virtual_root_freq = 172800 * 1000; |
||
2910 | u32 iclk_pi_range = 64; |
||
2911 | u32 desired_divisor, msb_divisor_value, pi_value; |
||
2912 | |||
2913 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
||
2914 | msb_divisor_value = desired_divisor / iclk_pi_range; |
||
2915 | pi_value = desired_divisor % iclk_pi_range; |
||
2916 | |||
2917 | auxdiv = 0; |
||
2918 | divsel = msb_divisor_value - 2; |
||
2919 | phaseinc = pi_value; |
||
2920 | } |
||
2921 | |||
2922 | /* This should not happen with any sane values */ |
||
2923 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
||
2924 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
||
2925 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
||
2926 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
||
2927 | |||
2928 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
||
2929 | crtc->mode.clock, |
||
2930 | auxdiv, |
||
2931 | divsel, |
||
2932 | phasedir, |
||
2933 | phaseinc); |
||
2934 | |||
2935 | /* Program SSCDIVINTPHASE6 */ |
||
3243 | Serge | 2936 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
3031 | serge | 2937 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2938 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
||
2939 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
||
2940 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
||
2941 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
||
2942 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
||
3243 | Serge | 2943 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
3031 | serge | 2944 | |
2945 | /* Program SSCAUXDIV */ |
||
3243 | Serge | 2946 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
3031 | serge | 2947 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2948 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
||
3243 | Serge | 2949 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
3031 | serge | 2950 | |
2951 | /* Enable modulator and associated divider */ |
||
3243 | Serge | 2952 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
3031 | serge | 2953 | temp &= ~SBI_SSCCTL_DISABLE; |
3243 | Serge | 2954 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
3031 | serge | 2955 | |
2956 | /* Wait for initialization time */ |
||
2957 | udelay(24); |
||
2958 | |||
2959 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
||
3480 | Serge | 2960 | |
2961 | mutex_unlock(&dev_priv->dpio_lock); |
||
3031 | serge | 2962 | } |
2963 | |||
4104 | Serge | 2964 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
2965 | enum pipe pch_transcoder) |
||
2966 | { |
||
2967 | struct drm_device *dev = crtc->base.dev; |
||
2968 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2969 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
||
2970 | |||
2971 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
||
2972 | I915_READ(HTOTAL(cpu_transcoder))); |
||
2973 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
||
2974 | I915_READ(HBLANK(cpu_transcoder))); |
||
2975 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
||
2976 | I915_READ(HSYNC(cpu_transcoder))); |
||
2977 | |||
2978 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
||
2979 | I915_READ(VTOTAL(cpu_transcoder))); |
||
2980 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
||
2981 | I915_READ(VBLANK(cpu_transcoder))); |
||
2982 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
||
2983 | I915_READ(VSYNC(cpu_transcoder))); |
||
2984 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
||
2985 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
||
2986 | } |
||
2987 | |||
4280 | Serge | 2988 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
2989 | { |
||
2990 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2991 | uint32_t temp; |
||
2992 | |||
2993 | temp = I915_READ(SOUTH_CHICKEN1); |
||
2994 | if (temp & FDI_BC_BIFURCATION_SELECT) |
||
2995 | return; |
||
2996 | |||
2997 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
||
2998 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
||
2999 | |||
3000 | temp |= FDI_BC_BIFURCATION_SELECT; |
||
3001 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
||
3002 | I915_WRITE(SOUTH_CHICKEN1, temp); |
||
3003 | POSTING_READ(SOUTH_CHICKEN1); |
||
3004 | } |
||
3005 | |||
3006 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
||
3007 | { |
||
3008 | struct drm_device *dev = intel_crtc->base.dev; |
||
3009 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3010 | |||
3011 | switch (intel_crtc->pipe) { |
||
3012 | case PIPE_A: |
||
3013 | break; |
||
3014 | case PIPE_B: |
||
3015 | if (intel_crtc->config.fdi_lanes > 2) |
||
3016 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
||
3017 | else |
||
3018 | cpt_enable_fdi_bc_bifurcation(dev); |
||
3019 | |||
3020 | break; |
||
3021 | case PIPE_C: |
||
3022 | cpt_enable_fdi_bc_bifurcation(dev); |
||
3023 | |||
3024 | break; |
||
3025 | default: |
||
3026 | BUG(); |
||
3027 | } |
||
3028 | } |
||
3029 | |||
2327 | Serge | 3030 | /* |
3031 | * Enable PCH resources required for PCH ports: |
||
3032 | * - PCH PLLs |
||
3033 | * - FDI training & RX/TX |
||
3034 | * - update transcoder timings |
||
3035 | * - DP transcoding bits |
||
3036 | * - transcoder |
||
3037 | */ |
||
3038 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
||
3039 | { |
||
3040 | struct drm_device *dev = crtc->dev; |
||
3041 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3043 | int pipe = intel_crtc->pipe; |
||
3031 | serge | 3044 | u32 reg, temp; |
2327 | Serge | 3045 | |
4104 | Serge | 3046 | assert_pch_transcoder_disabled(dev_priv, pipe); |
3031 | serge | 3047 | |
4280 | Serge | 3048 | if (IS_IVYBRIDGE(dev)) |
3049 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
||
3050 | |||
3243 | Serge | 3051 | /* Write the TU size bits before fdi link training, so that error |
3052 | * detection works. */ |
||
3053 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
||
3054 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
||
3055 | |||
2327 | Serge | 3056 | /* For PCH output, training FDI link */ |
3057 | dev_priv->display.fdi_link_train(crtc); |
||
3058 | |||
4104 | Serge | 3059 | /* We need to program the right clock selection before writing the pixel |
3060 | * mutliplier into the DPLL. */ |
||
3243 | Serge | 3061 | if (HAS_PCH_CPT(dev)) { |
3031 | serge | 3062 | u32 sel; |
2342 | Serge | 3063 | |
2327 | Serge | 3064 | temp = I915_READ(PCH_DPLL_SEL); |
4104 | Serge | 3065 | temp |= TRANS_DPLL_ENABLE(pipe); |
3066 | sel = TRANS_DPLLB_SEL(pipe); |
||
3067 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
||
3031 | serge | 3068 | temp |= sel; |
3069 | else |
||
3070 | temp &= ~sel; |
||
2327 | Serge | 3071 | I915_WRITE(PCH_DPLL_SEL, temp); |
3072 | } |
||
3073 | |||
4104 | Serge | 3074 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3075 | * transcoder, and we actually should do this to not upset any PCH |
||
3076 | * transcoder that already use the clock when we share it. |
||
3077 | * |
||
3078 | * Note that enable_shared_dpll tries to do the right thing, but |
||
3079 | * get_shared_dpll unconditionally resets the pll - we need that to have |
||
3080 | * the right LVDS enable sequence. */ |
||
3081 | ironlake_enable_shared_dpll(intel_crtc); |
||
3082 | |||
2327 | Serge | 3083 | /* set transcoder timing, panel must allow it */ |
3084 | assert_panel_unlocked(dev_priv, pipe); |
||
4104 | Serge | 3085 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
2327 | Serge | 3086 | |
3087 | intel_fdi_normal_train(crtc); |
||
3088 | |||
3089 | /* For PCH DP, enable TRANS_DP_CTL */ |
||
3090 | if (HAS_PCH_CPT(dev) && |
||
2342 | Serge | 3091 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3092 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
||
3480 | Serge | 3093 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
2327 | Serge | 3094 | reg = TRANS_DP_CTL(pipe); |
3095 | temp = I915_READ(reg); |
||
3096 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
||
3097 | TRANS_DP_SYNC_MASK | |
||
3098 | TRANS_DP_BPC_MASK); |
||
3099 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
||
3100 | TRANS_DP_ENH_FRAMING); |
||
3101 | temp |= bpc << 9; /* same format but at 11:9 */ |
||
3102 | |||
3103 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
||
3104 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
||
3105 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
||
3106 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
||
3107 | |||
3108 | switch (intel_trans_dp_port_sel(crtc)) { |
||
3109 | case PCH_DP_B: |
||
3110 | temp |= TRANS_DP_PORT_SEL_B; |
||
3111 | break; |
||
3112 | case PCH_DP_C: |
||
3113 | temp |= TRANS_DP_PORT_SEL_C; |
||
3114 | break; |
||
3115 | case PCH_DP_D: |
||
3116 | temp |= TRANS_DP_PORT_SEL_D; |
||
3117 | break; |
||
3118 | default: |
||
3243 | Serge | 3119 | BUG(); |
2327 | Serge | 3120 | } |
3121 | |||
3122 | I915_WRITE(reg, temp); |
||
3123 | } |
||
3124 | |||
3243 | Serge | 3125 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
2327 | Serge | 3126 | } |
3127 | |||
3243 | Serge | 3128 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3129 | { |
||
3130 | struct drm_device *dev = crtc->dev; |
||
3131 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3746 | Serge | 3133 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3243 | Serge | 3134 | |
4104 | Serge | 3135 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
3243 | Serge | 3136 | |
3137 | lpt_program_iclkip(crtc); |
||
3138 | |||
3139 | /* Set transcoder timing. */ |
||
4104 | Serge | 3140 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3243 | Serge | 3141 | |
3142 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
||
3143 | } |
||
3144 | |||
4104 | Serge | 3145 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
3031 | serge | 3146 | { |
4104 | Serge | 3147 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3031 | serge | 3148 | |
3149 | if (pll == NULL) |
||
3150 | return; |
||
3151 | |||
3152 | if (pll->refcount == 0) { |
||
4104 | Serge | 3153 | WARN(1, "bad %s refcount\n", pll->name); |
3031 | serge | 3154 | return; |
3155 | } |
||
3156 | |||
4104 | Serge | 3157 | if (--pll->refcount == 0) { |
3158 | WARN_ON(pll->on); |
||
3159 | WARN_ON(pll->active); |
||
3160 | } |
||
3161 | |||
3162 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
||
3031 | serge | 3163 | } |
3164 | |||
4104 | Serge | 3165 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3031 | serge | 3166 | { |
4104 | Serge | 3167 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3168 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
||
3169 | enum intel_dpll_id i; |
||
3031 | serge | 3170 | |
3171 | if (pll) { |
||
4104 | Serge | 3172 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3173 | crtc->base.base.id, pll->name); |
||
3174 | intel_put_shared_dpll(crtc); |
||
3031 | serge | 3175 | } |
3176 | |||
3177 | if (HAS_PCH_IBX(dev_priv->dev)) { |
||
3178 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
||
4104 | Serge | 3179 | i = (enum intel_dpll_id) crtc->pipe; |
3180 | pll = &dev_priv->shared_dplls[i]; |
||
3031 | serge | 3181 | |
4104 | Serge | 3182 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3183 | crtc->base.base.id, pll->name); |
||
3031 | serge | 3184 | |
3185 | goto found; |
||
3186 | } |
||
3187 | |||
4104 | Serge | 3188 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3189 | pll = &dev_priv->shared_dplls[i]; |
||
3031 | serge | 3190 | |
3191 | /* Only want to check enabled timings first */ |
||
3192 | if (pll->refcount == 0) |
||
3193 | continue; |
||
3194 | |||
4104 | Serge | 3195 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3196 | sizeof(pll->hw_state)) == 0) { |
||
3197 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
||
3198 | crtc->base.base.id, |
||
3199 | pll->name, pll->refcount, pll->active); |
||
3031 | serge | 3200 | |
3201 | goto found; |
||
3202 | } |
||
3203 | } |
||
3204 | |||
3205 | /* Ok no matching timings, maybe there's a free one? */ |
||
4104 | Serge | 3206 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3207 | pll = &dev_priv->shared_dplls[i]; |
||
3031 | serge | 3208 | if (pll->refcount == 0) { |
4104 | Serge | 3209 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3210 | crtc->base.base.id, pll->name); |
||
3031 | serge | 3211 | goto found; |
3212 | } |
||
3213 | } |
||
3214 | |||
3215 | return NULL; |
||
3216 | |||
3217 | found: |
||
4104 | Serge | 3218 | crtc->config.shared_dpll = i; |
3219 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
||
3220 | pipe_name(crtc->pipe)); |
||
3221 | |||
3222 | if (pll->active == 0) { |
||
3223 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
||
3224 | sizeof(pll->hw_state)); |
||
3225 | |||
3226 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
||
3227 | WARN_ON(pll->on); |
||
3228 | assert_shared_dpll_disabled(dev_priv, pll); |
||
3229 | |||
3230 | pll->mode_set(dev_priv, pll); |
||
3231 | } |
||
3031 | serge | 3232 | pll->refcount++; |
3233 | |||
3234 | return pll; |
||
3235 | } |
||
3236 | |||
4104 | Serge | 3237 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
2342 | Serge | 3238 | { |
3239 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3243 | Serge | 3240 | int dslreg = PIPEDSL(pipe); |
2342 | Serge | 3241 | u32 temp; |
3242 | |||
3243 | temp = I915_READ(dslreg); |
||
3244 | udelay(500); |
||
3245 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
||
3246 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
||
4104 | Serge | 3247 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
2342 | Serge | 3248 | } |
3249 | } |
||
3250 | |||
4104 | Serge | 3251 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3252 | { |
||
3253 | struct drm_device *dev = crtc->base.dev; |
||
3254 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3255 | int pipe = crtc->pipe; |
||
3256 | |||
3257 | if (crtc->config.pch_pfit.enabled) { |
||
3258 | /* Force use of hard-coded filter coefficients |
||
3259 | * as some pre-programmed values are broken, |
||
3260 | * e.g. x201. |
||
3261 | */ |
||
3262 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
||
3263 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
||
3264 | PF_PIPE_SEL_IVB(pipe)); |
||
3265 | else |
||
3266 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
||
3267 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
||
3268 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
||
3269 | } |
||
3270 | } |
||
3271 | |||
3272 | static void intel_enable_planes(struct drm_crtc *crtc) |
||
3273 | { |
||
3274 | struct drm_device *dev = crtc->dev; |
||
3275 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
||
3276 | struct intel_plane *intel_plane; |
||
3277 | |||
3278 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
||
3279 | if (intel_plane->pipe == pipe) |
||
3280 | intel_plane_restore(&intel_plane->base); |
||
3281 | } |
||
3282 | |||
3283 | static void intel_disable_planes(struct drm_crtc *crtc) |
||
3284 | { |
||
3285 | struct drm_device *dev = crtc->dev; |
||
3286 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
||
3287 | struct intel_plane *intel_plane; |
||
3288 | |||
3289 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
||
3290 | if (intel_plane->pipe == pipe) |
||
3291 | intel_plane_disable(&intel_plane->base); |
||
3292 | } |
||
3293 | |||
2327 | Serge | 3294 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3295 | { |
||
3296 | struct drm_device *dev = crtc->dev; |
||
3297 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3298 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3299 | struct intel_encoder *encoder; |
2327 | Serge | 3300 | int pipe = intel_crtc->pipe; |
3301 | int plane = intel_crtc->plane; |
||
3302 | |||
3031 | serge | 3303 | WARN_ON(!crtc->enabled); |
3304 | |||
2327 | Serge | 3305 | if (intel_crtc->active) |
3306 | return; |
||
3307 | |||
3308 | intel_crtc->active = true; |
||
4104 | Serge | 3309 | |
3310 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
||
3311 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
||
3312 | |||
2327 | Serge | 3313 | intel_update_watermarks(dev); |
3314 | |||
4104 | Serge | 3315 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3316 | if (encoder->pre_enable) |
||
3317 | encoder->pre_enable(encoder); |
||
2327 | Serge | 3318 | |
3746 | Serge | 3319 | if (intel_crtc->config.has_pch_encoder) { |
3243 | Serge | 3320 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3321 | * cpu pipes, hence this is separate from all the other fdi/pch |
||
3322 | * enabling. */ |
||
3031 | serge | 3323 | ironlake_fdi_pll_enable(intel_crtc); |
3324 | } else { |
||
3325 | assert_fdi_tx_disabled(dev_priv, pipe); |
||
3326 | assert_fdi_rx_disabled(dev_priv, pipe); |
||
3327 | } |
||
2327 | Serge | 3328 | |
4104 | Serge | 3329 | ironlake_pfit_enable(intel_crtc); |
3031 | serge | 3330 | |
2327 | Serge | 3331 | /* |
3332 | * On ILK+ LUT must be loaded before the pipe is running but with |
||
3333 | * clocks enabled |
||
3334 | */ |
||
3335 | intel_crtc_load_lut(crtc); |
||
3336 | |||
3746 | Serge | 3337 | intel_enable_pipe(dev_priv, pipe, |
3338 | intel_crtc->config.has_pch_encoder); |
||
2327 | Serge | 3339 | intel_enable_plane(dev_priv, plane, pipe); |
4104 | Serge | 3340 | intel_enable_planes(crtc); |
3341 | // intel_crtc_update_cursor(crtc, true); |
||
2327 | Serge | 3342 | |
3746 | Serge | 3343 | if (intel_crtc->config.has_pch_encoder) |
2327 | Serge | 3344 | ironlake_pch_enable(crtc); |
3345 | |||
3346 | mutex_lock(&dev->struct_mutex); |
||
3347 | intel_update_fbc(dev); |
||
3348 | mutex_unlock(&dev->struct_mutex); |
||
3349 | |||
3031 | serge | 3350 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3351 | encoder->enable(encoder); |
||
3352 | |||
3353 | if (HAS_PCH_CPT(dev)) |
||
4104 | Serge | 3354 | cpt_verify_modeset(dev, intel_crtc->pipe); |
3031 | serge | 3355 | |
3356 | /* |
||
3357 | * There seems to be a race in PCH platform hw (at least on some |
||
3358 | * outputs) where an enabled pipe still completes any pageflip right |
||
3359 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
||
3360 | * as the first vblank happend, everything works as expected. Hence just |
||
3361 | * wait for one vblank before returning to avoid strange things |
||
3362 | * happening. |
||
3363 | */ |
||
3364 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
2327 | Serge | 3365 | } |
3366 | |||
4104 | Serge | 3367 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3368 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
||
3369 | { |
||
3370 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
||
3371 | } |
||
3372 | |||
3373 | static void hsw_enable_ips(struct intel_crtc *crtc) |
||
3374 | { |
||
3375 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
||
3376 | |||
3377 | if (!crtc->config.ips_enabled) |
||
3378 | return; |
||
3379 | |||
3380 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
||
3381 | * We guarantee that the plane is enabled by calling intel_enable_ips |
||
3382 | * only after intel_enable_plane. And intel_enable_plane already waits |
||
3383 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
||
3384 | assert_plane_enabled(dev_priv, crtc->plane); |
||
3385 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
||
3386 | } |
||
3387 | |||
3388 | static void hsw_disable_ips(struct intel_crtc *crtc) |
||
3389 | { |
||
3390 | struct drm_device *dev = crtc->base.dev; |
||
3391 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3392 | |||
3393 | if (!crtc->config.ips_enabled) |
||
3394 | return; |
||
3395 | |||
3396 | assert_plane_enabled(dev_priv, crtc->plane); |
||
3397 | I915_WRITE(IPS_CTL, 0); |
||
3398 | |||
3399 | /* We need to wait for a vblank before we can disable the plane. */ |
||
3400 | intel_wait_for_vblank(dev, crtc->pipe); |
||
3401 | } |
||
3402 | |||
3243 | Serge | 3403 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3404 | { |
||
3405 | struct drm_device *dev = crtc->dev; |
||
3406 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3407 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3408 | struct intel_encoder *encoder; |
||
3409 | int pipe = intel_crtc->pipe; |
||
3410 | int plane = intel_crtc->plane; |
||
3411 | |||
3412 | WARN_ON(!crtc->enabled); |
||
3413 | |||
3414 | if (intel_crtc->active) |
||
3415 | return; |
||
3416 | |||
3417 | intel_crtc->active = true; |
||
4104 | Serge | 3418 | |
3419 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
||
3420 | if (intel_crtc->config.has_pch_encoder) |
||
3421 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
||
3422 | |||
3243 | Serge | 3423 | intel_update_watermarks(dev); |
3424 | |||
3746 | Serge | 3425 | if (intel_crtc->config.has_pch_encoder) |
3243 | Serge | 3426 | dev_priv->display.fdi_link_train(crtc); |
3427 | |||
3428 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3429 | if (encoder->pre_enable) |
||
3430 | encoder->pre_enable(encoder); |
||
3431 | |||
3432 | intel_ddi_enable_pipe_clock(intel_crtc); |
||
3433 | |||
4104 | Serge | 3434 | ironlake_pfit_enable(intel_crtc); |
3243 | Serge | 3435 | |
3436 | /* |
||
3437 | * On ILK+ LUT must be loaded before the pipe is running but with |
||
3438 | * clocks enabled |
||
3439 | */ |
||
3440 | intel_crtc_load_lut(crtc); |
||
3441 | |||
3442 | intel_ddi_set_pipe_settings(crtc); |
||
3746 | Serge | 3443 | intel_ddi_enable_transcoder_func(crtc); |
3243 | Serge | 3444 | |
3746 | Serge | 3445 | intel_enable_pipe(dev_priv, pipe, |
3446 | intel_crtc->config.has_pch_encoder); |
||
3243 | Serge | 3447 | intel_enable_plane(dev_priv, plane, pipe); |
4104 | Serge | 3448 | intel_enable_planes(crtc); |
3449 | // intel_crtc_update_cursor(crtc, true); |
||
3243 | Serge | 3450 | |
4104 | Serge | 3451 | hsw_enable_ips(intel_crtc); |
3452 | |||
3746 | Serge | 3453 | if (intel_crtc->config.has_pch_encoder) |
3243 | Serge | 3454 | lpt_pch_enable(crtc); |
3455 | |||
3456 | mutex_lock(&dev->struct_mutex); |
||
3457 | intel_update_fbc(dev); |
||
3458 | mutex_unlock(&dev->struct_mutex); |
||
3459 | |||
3460 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3461 | encoder->enable(encoder); |
||
3462 | |||
3463 | /* |
||
3464 | * There seems to be a race in PCH platform hw (at least on some |
||
3465 | * outputs) where an enabled pipe still completes any pageflip right |
||
3466 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
||
3467 | * as the first vblank happend, everything works as expected. Hence just |
||
3468 | * wait for one vblank before returning to avoid strange things |
||
3469 | * happening. |
||
3470 | */ |
||
3471 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
3472 | } |
||
3473 | |||
4104 | Serge | 3474 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3475 | { |
||
3476 | struct drm_device *dev = crtc->base.dev; |
||
3477 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3478 | int pipe = crtc->pipe; |
||
3479 | |||
3480 | /* To avoid upsetting the power well on haswell only disable the pfit if |
||
3481 | * it's in use. The hw state code will make sure we get this right. */ |
||
3482 | if (crtc->config.pch_pfit.enabled) { |
||
3483 | I915_WRITE(PF_CTL(pipe), 0); |
||
3484 | I915_WRITE(PF_WIN_POS(pipe), 0); |
||
3485 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
||
3486 | } |
||
3487 | } |
||
3488 | |||
2327 | Serge | 3489 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3490 | { |
||
3491 | struct drm_device *dev = crtc->dev; |
||
3492 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3493 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3494 | struct intel_encoder *encoder; |
2327 | Serge | 3495 | int pipe = intel_crtc->pipe; |
3496 | int plane = intel_crtc->plane; |
||
3497 | u32 reg, temp; |
||
3498 | |||
3031 | serge | 3499 | |
2327 | Serge | 3500 | if (!intel_crtc->active) |
3501 | return; |
||
3502 | |||
3031 | serge | 3503 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3504 | encoder->disable(encoder); |
||
2336 | Serge | 3505 | |
3031 | serge | 3506 | // intel_crtc_wait_for_pending_flips(crtc); |
2327 | Serge | 3507 | // drm_vblank_off(dev, pipe); |
3508 | |||
4104 | Serge | 3509 | if (dev_priv->fbc.plane == plane) |
3510 | intel_disable_fbc(dev); |
||
3511 | |||
3512 | // intel_crtc_update_cursor(crtc, false); |
||
3513 | intel_disable_planes(crtc); |
||
2327 | Serge | 3514 | intel_disable_plane(dev_priv, plane, pipe); |
3515 | |||
4104 | Serge | 3516 | if (intel_crtc->config.has_pch_encoder) |
3517 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
||
2327 | Serge | 3518 | |
3519 | intel_disable_pipe(dev_priv, pipe); |
||
3520 | |||
4104 | Serge | 3521 | ironlake_pfit_disable(intel_crtc); |
2327 | Serge | 3522 | |
3031 | serge | 3523 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3524 | if (encoder->post_disable) |
||
3525 | encoder->post_disable(encoder); |
||
3526 | |||
4104 | Serge | 3527 | if (intel_crtc->config.has_pch_encoder) { |
2327 | Serge | 3528 | ironlake_fdi_disable(crtc); |
3529 | |||
3243 | Serge | 3530 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4104 | Serge | 3531 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
2327 | Serge | 3532 | |
3533 | if (HAS_PCH_CPT(dev)) { |
||
3534 | /* disable TRANS_DP_CTL */ |
||
3535 | reg = TRANS_DP_CTL(pipe); |
||
3536 | temp = I915_READ(reg); |
||
4104 | Serge | 3537 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
3538 | TRANS_DP_PORT_SEL_MASK); |
||
2327 | Serge | 3539 | temp |= TRANS_DP_PORT_SEL_NONE; |
3540 | I915_WRITE(reg, temp); |
||
3541 | |||
3542 | /* disable DPLL_SEL */ |
||
3543 | temp = I915_READ(PCH_DPLL_SEL); |
||
4104 | Serge | 3544 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
2327 | Serge | 3545 | I915_WRITE(PCH_DPLL_SEL, temp); |
3546 | } |
||
3547 | |||
3548 | /* disable PCH DPLL */ |
||
4104 | Serge | 3549 | intel_disable_shared_dpll(intel_crtc); |
2327 | Serge | 3550 | |
3031 | serge | 3551 | ironlake_fdi_pll_disable(intel_crtc); |
4104 | Serge | 3552 | } |
2327 | Serge | 3553 | |
3554 | intel_crtc->active = false; |
||
3555 | intel_update_watermarks(dev); |
||
3556 | |||
3557 | mutex_lock(&dev->struct_mutex); |
||
3558 | intel_update_fbc(dev); |
||
3559 | mutex_unlock(&dev->struct_mutex); |
||
3560 | } |
||
3561 | |||
3243 | Serge | 3562 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
3563 | { |
||
3564 | struct drm_device *dev = crtc->dev; |
||
3565 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3566 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3567 | struct intel_encoder *encoder; |
||
3568 | int pipe = intel_crtc->pipe; |
||
3569 | int plane = intel_crtc->plane; |
||
3746 | Serge | 3570 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3243 | Serge | 3571 | |
3572 | if (!intel_crtc->active) |
||
3573 | return; |
||
3574 | |||
3575 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3576 | encoder->disable(encoder); |
||
3577 | |||
3578 | |||
4104 | Serge | 3579 | /* FBC must be disabled before disabling the plane on HSW. */ |
3580 | if (dev_priv->fbc.plane == plane) |
||
3581 | intel_disable_fbc(dev); |
||
3582 | |||
3583 | hsw_disable_ips(intel_crtc); |
||
3584 | |||
3585 | // intel_crtc_update_cursor(crtc, false); |
||
3586 | intel_disable_planes(crtc); |
||
3243 | Serge | 3587 | intel_disable_plane(dev_priv, plane, pipe); |
3588 | |||
4104 | Serge | 3589 | if (intel_crtc->config.has_pch_encoder) |
3590 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
||
3243 | Serge | 3591 | intel_disable_pipe(dev_priv, pipe); |
3592 | |||
3593 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
||
3594 | |||
4104 | Serge | 3595 | ironlake_pfit_disable(intel_crtc); |
3243 | Serge | 3596 | |
3597 | intel_ddi_disable_pipe_clock(intel_crtc); |
||
3598 | |||
3599 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3600 | if (encoder->post_disable) |
||
3601 | encoder->post_disable(encoder); |
||
3602 | |||
3746 | Serge | 3603 | if (intel_crtc->config.has_pch_encoder) { |
3243 | Serge | 3604 | lpt_disable_pch_transcoder(dev_priv); |
4104 | Serge | 3605 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3243 | Serge | 3606 | intel_ddi_fdi_disable(crtc); |
3607 | } |
||
3608 | |||
3609 | intel_crtc->active = false; |
||
3610 | intel_update_watermarks(dev); |
||
3611 | |||
3612 | mutex_lock(&dev->struct_mutex); |
||
3613 | intel_update_fbc(dev); |
||
3614 | mutex_unlock(&dev->struct_mutex); |
||
3615 | } |
||
3616 | |||
3031 | serge | 3617 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
2327 | Serge | 3618 | { |
3619 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4104 | Serge | 3620 | intel_put_shared_dpll(intel_crtc); |
2327 | Serge | 3621 | } |
3622 | |||
3243 | Serge | 3623 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3624 | { |
||
3625 | intel_ddi_put_crtc_pll(crtc); |
||
3626 | } |
||
3627 | |||
2327 | Serge | 3628 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3629 | { |
||
3630 | if (!enable && intel_crtc->overlay) { |
||
3631 | struct drm_device *dev = intel_crtc->base.dev; |
||
3632 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3633 | |||
3634 | mutex_lock(&dev->struct_mutex); |
||
3635 | dev_priv->mm.interruptible = false; |
||
3636 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
||
3637 | dev_priv->mm.interruptible = true; |
||
3638 | mutex_unlock(&dev->struct_mutex); |
||
3639 | } |
||
3640 | |||
3641 | /* Let userspace switch the overlay on again. In most cases userspace |
||
3642 | * has to recompute where to put it anyway. |
||
3643 | */ |
||
3644 | } |
||
3645 | |||
3480 | Serge | 3646 | /** |
3647 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
||
3648 | * cursor plane briefly if not already running after enabling the display |
||
3649 | * plane. |
||
3650 | * This workaround avoids occasional blank screens when self refresh is |
||
3651 | * enabled. |
||
3652 | */ |
||
3653 | static void |
||
3654 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) |
||
3655 | { |
||
3656 | u32 cntl = I915_READ(CURCNTR(pipe)); |
||
3657 | |||
3658 | if ((cntl & CURSOR_MODE) == 0) { |
||
3659 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
||
3660 | |||
3661 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
||
3662 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
||
3663 | intel_wait_for_vblank(dev_priv->dev, pipe); |
||
3664 | I915_WRITE(CURCNTR(pipe), cntl); |
||
3665 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
||
3666 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); |
||
3667 | } |
||
3668 | } |
||
3669 | |||
4104 | Serge | 3670 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3671 | { |
||
3672 | struct drm_device *dev = crtc->base.dev; |
||
3673 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3674 | struct intel_crtc_config *pipe_config = &crtc->config; |
||
3675 | |||
3676 | if (!crtc->config.gmch_pfit.control) |
||
3677 | return; |
||
3678 | |||
3679 | /* |
||
3680 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
||
3681 | * according to register description and PRM. |
||
3682 | */ |
||
3683 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
||
3684 | assert_pipe_disabled(dev_priv, crtc->pipe); |
||
3685 | |||
3686 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
||
3687 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
||
3688 | |||
3689 | /* Border color in case we don't scale up to the full screen. Black by |
||
3690 | * default, change to something else for debugging. */ |
||
3691 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
||
3692 | } |
||
3693 | |||
3694 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
||
3695 | { |
||
3696 | struct drm_device *dev = crtc->dev; |
||
3697 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3698 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3699 | struct intel_encoder *encoder; |
||
3700 | int pipe = intel_crtc->pipe; |
||
3701 | int plane = intel_crtc->plane; |
||
3702 | |||
3703 | WARN_ON(!crtc->enabled); |
||
3704 | |||
3705 | if (intel_crtc->active) |
||
3706 | return; |
||
3707 | |||
3708 | intel_crtc->active = true; |
||
3709 | intel_update_watermarks(dev); |
||
3710 | |||
3711 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3712 | if (encoder->pre_pll_enable) |
||
3713 | encoder->pre_pll_enable(encoder); |
||
3714 | |||
3715 | vlv_enable_pll(intel_crtc); |
||
3716 | |||
3717 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3718 | if (encoder->pre_enable) |
||
3719 | encoder->pre_enable(encoder); |
||
3720 | |||
3721 | i9xx_pfit_enable(intel_crtc); |
||
3722 | |||
3723 | intel_crtc_load_lut(crtc); |
||
3724 | |||
3725 | intel_enable_pipe(dev_priv, pipe, false); |
||
3726 | intel_enable_plane(dev_priv, plane, pipe); |
||
3727 | intel_enable_planes(crtc); |
||
3728 | // intel_crtc_update_cursor(crtc, true); |
||
3729 | |||
3730 | intel_update_fbc(dev); |
||
3731 | |||
3732 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3733 | encoder->enable(encoder); |
||
3734 | } |
||
3735 | |||
2327 | Serge | 3736 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
3737 | { |
||
3738 | struct drm_device *dev = crtc->dev; |
||
3739 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3741 | struct intel_encoder *encoder; |
2327 | Serge | 3742 | int pipe = intel_crtc->pipe; |
3743 | int plane = intel_crtc->plane; |
||
3744 | |||
3031 | serge | 3745 | WARN_ON(!crtc->enabled); |
3746 | |||
2327 | Serge | 3747 | if (intel_crtc->active) |
3748 | return; |
||
3749 | |||
3750 | intel_crtc->active = true; |
||
3751 | intel_update_watermarks(dev); |
||
3752 | |||
3480 | Serge | 3753 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3754 | if (encoder->pre_enable) |
||
3755 | encoder->pre_enable(encoder); |
||
3756 | |||
4104 | Serge | 3757 | i9xx_enable_pll(intel_crtc); |
3758 | |||
3759 | i9xx_pfit_enable(intel_crtc); |
||
3760 | |||
3761 | intel_crtc_load_lut(crtc); |
||
3762 | |||
2327 | Serge | 3763 | intel_enable_pipe(dev_priv, pipe, false); |
3764 | intel_enable_plane(dev_priv, plane, pipe); |
||
4104 | Serge | 3765 | intel_enable_planes(crtc); |
3766 | /* The fixup needs to happen before cursor is enabled */ |
||
3480 | Serge | 3767 | if (IS_G4X(dev)) |
3768 | g4x_fixup_plane(dev_priv, pipe); |
||
4104 | Serge | 3769 | // intel_crtc_update_cursor(crtc, true); |
2327 | Serge | 3770 | |
3771 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
||
3772 | intel_crtc_dpms_overlay(intel_crtc, true); |
||
3031 | serge | 3773 | |
4104 | Serge | 3774 | intel_update_fbc(dev); |
3775 | |||
3031 | serge | 3776 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3777 | encoder->enable(encoder); |
||
2327 | Serge | 3778 | } |
3779 | |||
3746 | Serge | 3780 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3781 | { |
||
3782 | struct drm_device *dev = crtc->base.dev; |
||
3783 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3784 | |||
4104 | Serge | 3785 | if (!crtc->config.gmch_pfit.control) |
3786 | return; |
||
3787 | |||
3746 | Serge | 3788 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3789 | |||
4104 | Serge | 3790 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
3791 | I915_READ(PFIT_CONTROL)); |
||
3746 | Serge | 3792 | I915_WRITE(PFIT_CONTROL, 0); |
3793 | } |
||
3794 | |||
2327 | Serge | 3795 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3796 | { |
||
3797 | struct drm_device *dev = crtc->dev; |
||
3798 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3800 | struct intel_encoder *encoder; |
2327 | Serge | 3801 | int pipe = intel_crtc->pipe; |
3802 | int plane = intel_crtc->plane; |
||
3803 | |||
3804 | if (!intel_crtc->active) |
||
3805 | return; |
||
3806 | |||
3031 | serge | 3807 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3808 | encoder->disable(encoder); |
||
3809 | |||
2327 | Serge | 3810 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
3031 | serge | 3811 | // intel_crtc_wait_for_pending_flips(crtc); |
2327 | Serge | 3812 | // drm_vblank_off(dev, pipe); |
3813 | |||
4104 | Serge | 3814 | if (dev_priv->fbc.plane == plane) |
2327 | Serge | 3815 | intel_disable_fbc(dev); |
3816 | |||
4104 | Serge | 3817 | intel_crtc_dpms_overlay(intel_crtc, false); |
3818 | // intel_crtc_update_cursor(crtc, false); |
||
3819 | intel_disable_planes(crtc); |
||
2327 | Serge | 3820 | intel_disable_plane(dev_priv, plane, pipe); |
4104 | Serge | 3821 | |
2327 | Serge | 3822 | intel_disable_pipe(dev_priv, pipe); |
3480 | Serge | 3823 | |
3746 | Serge | 3824 | i9xx_pfit_disable(intel_crtc); |
3480 | Serge | 3825 | |
4104 | Serge | 3826 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3827 | if (encoder->post_disable) |
||
3828 | encoder->post_disable(encoder); |
||
2327 | Serge | 3829 | |
4104 | Serge | 3830 | i9xx_disable_pll(dev_priv, pipe); |
3831 | |||
2327 | Serge | 3832 | intel_crtc->active = false; |
3833 | intel_update_fbc(dev); |
||
3834 | intel_update_watermarks(dev); |
||
3835 | } |
||
3836 | |||
3031 | serge | 3837 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
2327 | Serge | 3838 | { |
3839 | } |
||
3840 | |||
3031 | serge | 3841 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3842 | bool enabled) |
||
2330 | Serge | 3843 | { |
3844 | struct drm_device *dev = crtc->dev; |
||
3845 | struct drm_i915_master_private *master_priv; |
||
3846 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3847 | int pipe = intel_crtc->pipe; |
||
2327 | Serge | 3848 | |
3849 | |||
2340 | Serge | 3850 | #if 0 |
2330 | Serge | 3851 | if (!dev->primary->master) |
3852 | return; |
||
2327 | Serge | 3853 | |
2330 | Serge | 3854 | master_priv = dev->primary->master->driver_priv; |
3855 | if (!master_priv->sarea_priv) |
||
3856 | return; |
||
2327 | Serge | 3857 | |
2330 | Serge | 3858 | switch (pipe) { |
3859 | case 0: |
||
3860 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
||
3861 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
||
3862 | break; |
||
3863 | case 1: |
||
3864 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
||
3865 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
||
3866 | break; |
||
3867 | default: |
||
3868 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
||
3869 | break; |
||
3870 | } |
||
2340 | Serge | 3871 | #endif |
3872 | |||
2330 | Serge | 3873 | } |
2327 | Serge | 3874 | |
3031 | serge | 3875 | /** |
3876 | * Sets the power management mode of the pipe and plane. |
||
3877 | */ |
||
3878 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
||
3879 | { |
||
3880 | struct drm_device *dev = crtc->dev; |
||
3881 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3882 | struct intel_encoder *intel_encoder; |
||
3883 | bool enable = false; |
||
3884 | |||
3885 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
||
3886 | enable |= intel_encoder->connectors_active; |
||
3887 | |||
3888 | if (enable) |
||
3889 | dev_priv->display.crtc_enable(crtc); |
||
3890 | else |
||
3891 | dev_priv->display.crtc_disable(crtc); |
||
3892 | |||
3893 | intel_crtc_update_sarea(crtc, enable); |
||
3894 | } |
||
3895 | |||
2330 | Serge | 3896 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3897 | { |
||
3898 | struct drm_device *dev = crtc->dev; |
||
3031 | serge | 3899 | struct drm_connector *connector; |
3900 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3480 | Serge | 3901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2327 | Serge | 3902 | |
3031 | serge | 3903 | /* crtc should still be enabled when we disable it. */ |
3904 | WARN_ON(!crtc->enabled); |
||
2327 | Serge | 3905 | |
4104 | Serge | 3906 | dev_priv->display.crtc_disable(crtc); |
3480 | Serge | 3907 | intel_crtc->eld_vld = false; |
3031 | serge | 3908 | intel_crtc_update_sarea(crtc, false); |
3909 | dev_priv->display.off(crtc); |
||
3910 | |||
3911 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
||
3912 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
||
3913 | |||
4280 | Serge | 3914 | if (crtc->fb) { |
3915 | mutex_lock(&dev->struct_mutex); |
||
3916 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
||
3917 | mutex_unlock(&dev->struct_mutex); |
||
3918 | crtc->fb = NULL; |
||
3919 | } |
||
3031 | serge | 3920 | |
3921 | /* Update computed state. */ |
||
3922 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
3923 | if (!connector->encoder || !connector->encoder->crtc) |
||
3924 | continue; |
||
3925 | |||
3926 | if (connector->encoder->crtc != crtc) |
||
3927 | continue; |
||
3928 | |||
3929 | connector->dpms = DRM_MODE_DPMS_OFF; |
||
3930 | to_intel_encoder(connector->encoder)->connectors_active = false; |
||
2330 | Serge | 3931 | } |
3932 | } |
||
2327 | Serge | 3933 | |
3031 | serge | 3934 | void intel_encoder_destroy(struct drm_encoder *encoder) |
2330 | Serge | 3935 | { |
3031 | serge | 3936 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
3937 | |||
3938 | drm_encoder_cleanup(encoder); |
||
3939 | kfree(intel_encoder); |
||
2330 | Serge | 3940 | } |
2327 | Serge | 3941 | |
4104 | Serge | 3942 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
3031 | serge | 3943 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3944 | * state of the entire output pipe. */ |
||
4104 | Serge | 3945 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
2330 | Serge | 3946 | { |
3031 | serge | 3947 | if (mode == DRM_MODE_DPMS_ON) { |
3948 | encoder->connectors_active = true; |
||
3949 | |||
3950 | intel_crtc_update_dpms(encoder->base.crtc); |
||
3951 | } else { |
||
3952 | encoder->connectors_active = false; |
||
3953 | |||
3954 | intel_crtc_update_dpms(encoder->base.crtc); |
||
3955 | } |
||
2330 | Serge | 3956 | } |
2327 | Serge | 3957 | |
3031 | serge | 3958 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3959 | * internal consistency). */ |
||
3960 | static void intel_connector_check_state(struct intel_connector *connector) |
||
2330 | Serge | 3961 | { |
3031 | serge | 3962 | if (connector->get_hw_state(connector)) { |
3963 | struct intel_encoder *encoder = connector->encoder; |
||
3964 | struct drm_crtc *crtc; |
||
3965 | bool encoder_enabled; |
||
3966 | enum pipe pipe; |
||
3967 | |||
3968 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
||
3969 | connector->base.base.id, |
||
3970 | drm_get_connector_name(&connector->base)); |
||
3971 | |||
3972 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
||
3973 | "wrong connector dpms state\n"); |
||
3974 | WARN(connector->base.encoder != &encoder->base, |
||
3975 | "active connector not linked to encoder\n"); |
||
3976 | WARN(!encoder->connectors_active, |
||
3977 | "encoder->connectors_active not set\n"); |
||
3978 | |||
3979 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
||
3980 | WARN(!encoder_enabled, "encoder not enabled\n"); |
||
3981 | if (WARN_ON(!encoder->base.crtc)) |
||
3982 | return; |
||
3983 | |||
3984 | crtc = encoder->base.crtc; |
||
3985 | |||
3986 | WARN(!crtc->enabled, "crtc not enabled\n"); |
||
3987 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
||
3988 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
||
3989 | "encoder active on the wrong pipe\n"); |
||
3990 | } |
||
2330 | Serge | 3991 | } |
2327 | Serge | 3992 | |
3031 | serge | 3993 | /* Even simpler default implementation, if there's really no special case to |
3994 | * consider. */ |
||
3995 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
||
2330 | Serge | 3996 | { |
3031 | serge | 3997 | /* All the simple cases only support two dpms states. */ |
3998 | if (mode != DRM_MODE_DPMS_ON) |
||
3999 | mode = DRM_MODE_DPMS_OFF; |
||
2342 | Serge | 4000 | |
3031 | serge | 4001 | if (mode == connector->dpms) |
4002 | return; |
||
4003 | |||
4004 | connector->dpms = mode; |
||
4005 | |||
4006 | /* Only need to change hw state when actually enabled */ |
||
4104 | Serge | 4007 | if (connector->encoder) |
4008 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
||
3031 | serge | 4009 | |
4010 | intel_modeset_check_state(connector->dev); |
||
2330 | Serge | 4011 | } |
2327 | Serge | 4012 | |
3031 | serge | 4013 | /* Simple connector->get_hw_state implementation for encoders that support only |
4014 | * one connector and no cloning and hence the encoder state determines the state |
||
4015 | * of the connector. */ |
||
4016 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
||
2330 | Serge | 4017 | { |
3031 | serge | 4018 | enum pipe pipe = 0; |
4019 | struct intel_encoder *encoder = connector->encoder; |
||
2330 | Serge | 4020 | |
3031 | serge | 4021 | return encoder->get_hw_state(encoder, &pipe); |
2330 | Serge | 4022 | } |
4023 | |||
4104 | Serge | 4024 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4025 | struct intel_crtc_config *pipe_config) |
||
4026 | { |
||
4027 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4028 | struct intel_crtc *pipe_B_crtc = |
||
4029 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
||
4030 | |||
4031 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
||
4032 | pipe_name(pipe), pipe_config->fdi_lanes); |
||
4033 | if (pipe_config->fdi_lanes > 4) { |
||
4034 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
||
4035 | pipe_name(pipe), pipe_config->fdi_lanes); |
||
4036 | return false; |
||
4037 | } |
||
4038 | |||
4039 | if (IS_HASWELL(dev)) { |
||
4040 | if (pipe_config->fdi_lanes > 2) { |
||
4041 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
||
4042 | pipe_config->fdi_lanes); |
||
4043 | return false; |
||
4044 | } else { |
||
4045 | return true; |
||
4046 | } |
||
4047 | } |
||
4048 | |||
4049 | if (INTEL_INFO(dev)->num_pipes == 2) |
||
4050 | return true; |
||
4051 | |||
4052 | /* Ivybridge 3 pipe is really complicated */ |
||
4053 | switch (pipe) { |
||
4054 | case PIPE_A: |
||
4055 | return true; |
||
4056 | case PIPE_B: |
||
4057 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
||
4058 | pipe_config->fdi_lanes > 2) { |
||
4059 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
||
4060 | pipe_name(pipe), pipe_config->fdi_lanes); |
||
4061 | return false; |
||
4062 | } |
||
4063 | return true; |
||
4064 | case PIPE_C: |
||
4065 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
||
4066 | pipe_B_crtc->config.fdi_lanes <= 2) { |
||
4067 | if (pipe_config->fdi_lanes > 2) { |
||
4068 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
||
4069 | pipe_name(pipe), pipe_config->fdi_lanes); |
||
4070 | return false; |
||
4071 | } |
||
4072 | } else { |
||
4073 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
||
4074 | return false; |
||
4075 | } |
||
4076 | return true; |
||
4077 | default: |
||
4078 | BUG(); |
||
4079 | } |
||
4080 | } |
||
4081 | |||
4082 | #define RETRY 1 |
||
4083 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
||
3746 | Serge | 4084 | struct intel_crtc_config *pipe_config) |
2330 | Serge | 4085 | { |
4104 | Serge | 4086 | struct drm_device *dev = intel_crtc->base.dev; |
3746 | Serge | 4087 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4104 | Serge | 4088 | int lane, link_bw, fdi_dotclock; |
4089 | bool setup_ok, needs_recompute = false; |
||
2330 | Serge | 4090 | |
4104 | Serge | 4091 | retry: |
4092 | /* FDI is a binary signal running at ~2.7GHz, encoding |
||
4093 | * each output octet as 10 bits. The actual frequency |
||
4094 | * is stored as a divider into a 100MHz clock, and the |
||
4095 | * mode pixel clock is stored in units of 1KHz. |
||
4096 | * Hence the bw of each lane in terms of the mode signal |
||
4097 | * is: |
||
4098 | */ |
||
4099 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
||
4100 | |||
4101 | fdi_dotclock = adjusted_mode->clock; |
||
4102 | fdi_dotclock /= pipe_config->pixel_multiplier; |
||
4103 | |||
4104 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
||
4105 | pipe_config->pipe_bpp); |
||
4106 | |||
4107 | pipe_config->fdi_lanes = lane; |
||
4108 | |||
4109 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
||
4110 | link_bw, &pipe_config->fdi_m_n); |
||
4111 | |||
4112 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
||
4113 | intel_crtc->pipe, pipe_config); |
||
4114 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
||
4115 | pipe_config->pipe_bpp -= 2*3; |
||
4116 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
||
4117 | pipe_config->pipe_bpp); |
||
4118 | needs_recompute = true; |
||
4119 | pipe_config->bw_constrained = true; |
||
4120 | |||
4121 | goto retry; |
||
4122 | } |
||
4123 | |||
4124 | if (needs_recompute) |
||
4125 | return RETRY; |
||
4126 | |||
4127 | return setup_ok ? 0 : -EINVAL; |
||
4128 | } |
||
4129 | |||
4130 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
||
4131 | struct intel_crtc_config *pipe_config) |
||
4132 | { |
||
4133 | pipe_config->ips_enabled = i915_enable_ips && |
||
4134 | hsw_crtc_supports_ips(crtc) && |
||
4135 | pipe_config->pipe_bpp <= 24; |
||
4136 | } |
||
4137 | |||
4138 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
||
4139 | struct intel_crtc_config *pipe_config) |
||
4140 | { |
||
4141 | struct drm_device *dev = crtc->base.dev; |
||
4142 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
||
4143 | |||
2330 | Serge | 4144 | if (HAS_PCH_SPLIT(dev)) { |
4145 | /* FDI link clock is fixed at 2.7G */ |
||
3746 | Serge | 4146 | if (pipe_config->requested_mode.clock * 3 |
4147 | > IRONLAKE_FDI_FREQ * 4) |
||
4104 | Serge | 4148 | return -EINVAL; |
2330 | Serge | 4149 | } |
4150 | |||
4104 | Serge | 4151 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4152 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
||
3031 | serge | 4153 | */ |
4154 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
||
4155 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
||
4104 | Serge | 4156 | return -EINVAL; |
3031 | serge | 4157 | |
3746 | Serge | 4158 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
4159 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
||
4160 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
||
4161 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
||
4162 | * for lvds. */ |
||
4163 | pipe_config->pipe_bpp = 8*3; |
||
4164 | } |
||
4165 | |||
4104 | Serge | 4166 | if (HAS_IPS(dev)) |
4167 | hsw_compute_ips_config(crtc, pipe_config); |
||
4168 | |||
4169 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
||
4170 | * clock survives for now. */ |
||
4171 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
||
4172 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
||
4173 | |||
4174 | if (pipe_config->has_pch_encoder) |
||
4175 | return ironlake_fdi_compute_config(crtc, pipe_config); |
||
4176 | |||
4177 | return 0; |
||
2330 | Serge | 4178 | } |
4179 | |||
3031 | serge | 4180 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4181 | { |
||
4182 | return 400000; /* FIXME */ |
||
4183 | } |
||
4184 | |||
2327 | Serge | 4185 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4186 | { |
||
4187 | return 400000; |
||
4188 | } |
||
4189 | |||
4190 | static int i915_get_display_clock_speed(struct drm_device *dev) |
||
4191 | { |
||
4192 | return 333000; |
||
4193 | } |
||
4194 | |||
4195 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
||
4196 | { |
||
4197 | return 200000; |
||
4198 | } |
||
4199 | |||
4104 | Serge | 4200 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4201 | { |
||
4202 | u16 gcfgc = 0; |
||
4203 | |||
4204 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
||
4205 | |||
4206 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
||
4207 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
||
4208 | return 267000; |
||
4209 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
||
4210 | return 333000; |
||
4211 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
||
4212 | return 444000; |
||
4213 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
||
4214 | return 200000; |
||
4215 | default: |
||
4216 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
||
4217 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
||
4218 | return 133000; |
||
4219 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
||
4220 | return 167000; |
||
4221 | } |
||
4222 | } |
||
4223 | |||
2327 | Serge | 4224 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4225 | { |
||
4226 | u16 gcfgc = 0; |
||
4227 | |||
4228 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
||
4229 | |||
4230 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
||
4231 | return 133000; |
||
4232 | else { |
||
4233 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
||
4234 | case GC_DISPLAY_CLOCK_333_MHZ: |
||
4235 | return 333000; |
||
4236 | default: |
||
4237 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
||
4238 | return 190000; |
||
4239 | } |
||
4240 | } |
||
4241 | } |
||
4242 | |||
4243 | static int i865_get_display_clock_speed(struct drm_device *dev) |
||
4244 | { |
||
4245 | return 266000; |
||
4246 | } |
||
4247 | |||
4248 | static int i855_get_display_clock_speed(struct drm_device *dev) |
||
4249 | { |
||
4250 | u16 hpllcc = 0; |
||
4251 | /* Assume that the hardware is in the high speed state. This |
||
4252 | * should be the default. |
||
4253 | */ |
||
4254 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
||
4255 | case GC_CLOCK_133_200: |
||
4256 | case GC_CLOCK_100_200: |
||
4257 | return 200000; |
||
4258 | case GC_CLOCK_166_250: |
||
4259 | return 250000; |
||
4260 | case GC_CLOCK_100_133: |
||
4261 | return 133000; |
||
4262 | } |
||
4263 | |||
4264 | /* Shouldn't happen */ |
||
4265 | return 0; |
||
4266 | } |
||
4267 | |||
4268 | static int i830_get_display_clock_speed(struct drm_device *dev) |
||
4269 | { |
||
4270 | return 133000; |
||
4271 | } |
||
4272 | |||
4273 | static void |
||
3746 | Serge | 4274 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2327 | Serge | 4275 | { |
3746 | Serge | 4276 | while (*num > DATA_LINK_M_N_MASK || |
4277 | *den > DATA_LINK_M_N_MASK) { |
||
2327 | Serge | 4278 | *num >>= 1; |
4279 | *den >>= 1; |
||
4280 | } |
||
4281 | } |
||
4282 | |||
3746 | Serge | 4283 | static void compute_m_n(unsigned int m, unsigned int n, |
4284 | uint32_t *ret_m, uint32_t *ret_n) |
||
4285 | { |
||
4286 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
||
4287 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
||
4288 | intel_reduce_m_n_ratio(ret_m, ret_n); |
||
4289 | } |
||
4290 | |||
3480 | Serge | 4291 | void |
4292 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
||
4293 | int pixel_clock, int link_clock, |
||
4294 | struct intel_link_m_n *m_n) |
||
2327 | Serge | 4295 | { |
3480 | Serge | 4296 | m_n->tu = 64; |
3746 | Serge | 4297 | |
4298 | compute_m_n(bits_per_pixel * pixel_clock, |
||
4299 | link_clock * nlanes * 8, |
||
4300 | &m_n->gmch_m, &m_n->gmch_n); |
||
4301 | |||
4302 | compute_m_n(pixel_clock, link_clock, |
||
4303 | &m_n->link_m, &m_n->link_n); |
||
2327 | Serge | 4304 | } |
4305 | |||
4306 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
||
4307 | { |
||
2342 | Serge | 4308 | if (i915_panel_use_ssc >= 0) |
4309 | return i915_panel_use_ssc != 0; |
||
4104 | Serge | 4310 | return dev_priv->vbt.lvds_use_ssc |
2327 | Serge | 4311 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
4312 | } |
||
4313 | |||
3031 | serge | 4314 | static int vlv_get_refclk(struct drm_crtc *crtc) |
2327 | Serge | 4315 | { |
3031 | serge | 4316 | struct drm_device *dev = crtc->dev; |
4317 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4318 | int refclk = 27000; /* for DP & HDMI */ |
||
2327 | Serge | 4319 | |
3031 | serge | 4320 | return 100000; /* only one validated so far */ |
2327 | Serge | 4321 | |
3031 | serge | 4322 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
4323 | refclk = 96000; |
||
4324 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
||
4325 | if (intel_panel_use_ssc(dev_priv)) |
||
4326 | refclk = 100000; |
||
4327 | else |
||
4328 | refclk = 96000; |
||
4329 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
||
4330 | refclk = 100000; |
||
4331 | } |
||
2327 | Serge | 4332 | |
3031 | serge | 4333 | return refclk; |
4334 | } |
||
2327 | Serge | 4335 | |
3031 | serge | 4336 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4337 | { |
||
4338 | struct drm_device *dev = crtc->dev; |
||
4339 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4340 | int refclk; |
||
2327 | Serge | 4341 | |
3031 | serge | 4342 | if (IS_VALLEYVIEW(dev)) { |
4343 | refclk = vlv_get_refclk(crtc); |
||
4344 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
||
4345 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
||
4104 | Serge | 4346 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
3031 | serge | 4347 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4348 | refclk / 1000); |
||
4349 | } else if (!IS_GEN2(dev)) { |
||
4350 | refclk = 96000; |
||
4351 | } else { |
||
4352 | refclk = 48000; |
||
4353 | } |
||
2327 | Serge | 4354 | |
3031 | serge | 4355 | return refclk; |
4356 | } |
||
2327 | Serge | 4357 | |
4104 | Serge | 4358 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
3031 | serge | 4359 | { |
4104 | Serge | 4360 | return (1 << dpll->n) << 16 | dpll->m2; |
4361 | } |
||
3746 | Serge | 4362 | |
4104 | Serge | 4363 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4364 | { |
||
4365 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
||
3031 | serge | 4366 | } |
2327 | Serge | 4367 | |
3746 | Serge | 4368 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
3031 | serge | 4369 | intel_clock_t *reduced_clock) |
4370 | { |
||
3746 | Serge | 4371 | struct drm_device *dev = crtc->base.dev; |
3031 | serge | 4372 | struct drm_i915_private *dev_priv = dev->dev_private; |
3746 | Serge | 4373 | int pipe = crtc->pipe; |
3031 | serge | 4374 | u32 fp, fp2 = 0; |
2327 | Serge | 4375 | |
3031 | serge | 4376 | if (IS_PINEVIEW(dev)) { |
4104 | Serge | 4377 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
3031 | serge | 4378 | if (reduced_clock) |
4104 | Serge | 4379 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
3031 | serge | 4380 | } else { |
4104 | Serge | 4381 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
3031 | serge | 4382 | if (reduced_clock) |
4104 | Serge | 4383 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
3031 | serge | 4384 | } |
2327 | Serge | 4385 | |
3031 | serge | 4386 | I915_WRITE(FP0(pipe), fp); |
4104 | Serge | 4387 | crtc->config.dpll_hw_state.fp0 = fp; |
2327 | Serge | 4388 | |
3746 | Serge | 4389 | crtc->lowfreq_avail = false; |
4390 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
||
3031 | serge | 4391 | reduced_clock && i915_powersave) { |
4392 | I915_WRITE(FP1(pipe), fp2); |
||
4104 | Serge | 4393 | crtc->config.dpll_hw_state.fp1 = fp2; |
3746 | Serge | 4394 | crtc->lowfreq_avail = true; |
3031 | serge | 4395 | } else { |
4396 | I915_WRITE(FP1(pipe), fp); |
||
4104 | Serge | 4397 | crtc->config.dpll_hw_state.fp1 = fp; |
3031 | serge | 4398 | } |
4399 | } |
||
2327 | Serge | 4400 | |
4104 | Serge | 4401 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) |
4402 | { |
||
4403 | u32 reg_val; |
||
4404 | |||
4405 | /* |
||
4406 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
||
4407 | * and set it to a reasonable value instead. |
||
4408 | */ |
||
4409 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
||
4410 | reg_val &= 0xffffff00; |
||
4411 | reg_val |= 0x00000030; |
||
4412 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
||
4413 | |||
4414 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
||
4415 | reg_val &= 0x8cffffff; |
||
4416 | reg_val = 0x8c000000; |
||
4417 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
||
4418 | |||
4419 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
||
4420 | reg_val &= 0xffffff00; |
||
4421 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
||
4422 | |||
4423 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
||
4424 | reg_val &= 0x00ffffff; |
||
4425 | reg_val |= 0xb0000000; |
||
4426 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
||
4427 | } |
||
4428 | |||
4429 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
||
4430 | struct intel_link_m_n *m_n) |
||
4431 | { |
||
4432 | struct drm_device *dev = crtc->base.dev; |
||
4433 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4434 | int pipe = crtc->pipe; |
||
4435 | |||
4436 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
||
4437 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
||
4438 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
||
4439 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
||
4440 | } |
||
4441 | |||
4442 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
||
4443 | struct intel_link_m_n *m_n) |
||
4444 | { |
||
4445 | struct drm_device *dev = crtc->base.dev; |
||
4446 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4447 | int pipe = crtc->pipe; |
||
4448 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
||
4449 | |||
4450 | if (INTEL_INFO(dev)->gen >= 5) { |
||
4451 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
||
4452 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
||
4453 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
||
4454 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
||
4455 | } else { |
||
4456 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
||
4457 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
||
4458 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
||
4459 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
||
4460 | } |
||
4461 | } |
||
4462 | |||
3746 | Serge | 4463 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
3031 | serge | 4464 | { |
3746 | Serge | 4465 | if (crtc->config.has_pch_encoder) |
4466 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
||
4467 | else |
||
4468 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
||
4469 | } |
||
4470 | |||
4471 | static void vlv_update_pll(struct intel_crtc *crtc) |
||
4472 | { |
||
4473 | struct drm_device *dev = crtc->base.dev; |
||
3031 | serge | 4474 | struct drm_i915_private *dev_priv = dev->dev_private; |
3746 | Serge | 4475 | int pipe = crtc->pipe; |
4104 | Serge | 4476 | u32 dpll, mdiv; |
3031 | serge | 4477 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
4104 | Serge | 4478 | u32 coreclk, reg_val, dpll_md; |
2327 | Serge | 4479 | |
3480 | Serge | 4480 | mutex_lock(&dev_priv->dpio_lock); |
4481 | |||
3746 | Serge | 4482 | bestn = crtc->config.dpll.n; |
4483 | bestm1 = crtc->config.dpll.m1; |
||
4484 | bestm2 = crtc->config.dpll.m2; |
||
4485 | bestp1 = crtc->config.dpll.p1; |
||
4486 | bestp2 = crtc->config.dpll.p2; |
||
3031 | serge | 4487 | |
4104 | Serge | 4488 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4489 | |||
4490 | /* PLL B needs special handling */ |
||
4491 | if (pipe) |
||
4492 | vlv_pllb_recal_opamp(dev_priv); |
||
4493 | |||
4494 | /* Set up Tx target for periodic Rcomp update */ |
||
4495 | vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f); |
||
4496 | |||
4497 | /* Disable target IRef on PLL */ |
||
4498 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe)); |
||
4499 | reg_val &= 0x00ffffff; |
||
4500 | vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val); |
||
4501 | |||
4502 | /* Disable fast lock */ |
||
4503 | vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610); |
||
4504 | |||
4505 | /* Set idtafcrecal before PLL is enabled */ |
||
3031 | serge | 4506 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4507 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
||
4508 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
||
4509 | mdiv |= (1 << DPIO_K_SHIFT); |
||
4104 | Serge | 4510 | |
4511 | /* |
||
4512 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
||
4513 | * but we don't support that). |
||
4514 | * Note: don't use the DAC post divider as it seems unstable. |
||
4515 | */ |
||
4516 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
||
4517 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
||
4518 | |||
3031 | serge | 4519 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4104 | Serge | 4520 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
3031 | serge | 4521 | |
4104 | Serge | 4522 | /* Set HBR and RBR LPF coefficients */ |
4523 | if (crtc->config.port_clock == 162000 || |
||
4524 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
||
4525 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
||
4526 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
||
4527 | 0x009f0003); |
||
4528 | else |
||
4529 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
||
4530 | 0x00d0000f); |
||
3031 | serge | 4531 | |
4104 | Serge | 4532 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4533 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
||
4534 | /* Use SSC source */ |
||
4535 | if (!pipe) |
||
4536 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
||
4537 | 0x0df40000); |
||
4538 | else |
||
4539 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
||
4540 | 0x0df70000); |
||
4541 | } else { /* HDMI or VGA */ |
||
4542 | /* Use bend source */ |
||
4543 | if (!pipe) |
||
4544 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
||
4545 | 0x0df70000); |
||
4546 | else |
||
4547 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
||
4548 | 0x0df40000); |
||
4549 | } |
||
3031 | serge | 4550 | |
4104 | Serge | 4551 | coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe)); |
4552 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
||
4553 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
||
4554 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
||
4555 | coreclk |= 0x01000000; |
||
4556 | vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk); |
||
3031 | serge | 4557 | |
4104 | Serge | 4558 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
4559 | |||
4560 | /* Enable DPIO clock input */ |
||
4561 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
||
4562 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
||
4398 | Serge | 4563 | /* We should never disable this, set it here for state tracking */ |
4564 | if (pipe == PIPE_B) |
||
4104 | Serge | 4565 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
3031 | serge | 4566 | dpll |= DPLL_VCO_ENABLE; |
4104 | Serge | 4567 | crtc->config.dpll_hw_state.dpll = dpll; |
3031 | serge | 4568 | |
4104 | Serge | 4569 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4570 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
||
4571 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
||
3031 | serge | 4572 | |
3746 | Serge | 4573 | if (crtc->config.has_dp_encoder) |
4574 | intel_dp_set_m_n(crtc); |
||
3243 | Serge | 4575 | |
3480 | Serge | 4576 | mutex_unlock(&dev_priv->dpio_lock); |
3031 | serge | 4577 | } |
4578 | |||
3746 | Serge | 4579 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4580 | intel_clock_t *reduced_clock, |
||
3031 | serge | 4581 | int num_connectors) |
4582 | { |
||
3746 | Serge | 4583 | struct drm_device *dev = crtc->base.dev; |
3031 | serge | 4584 | struct drm_i915_private *dev_priv = dev->dev_private; |
4585 | u32 dpll; |
||
4586 | bool is_sdvo; |
||
3746 | Serge | 4587 | struct dpll *clock = &crtc->config.dpll; |
3031 | serge | 4588 | |
3746 | Serge | 4589 | i9xx_update_pll_dividers(crtc, reduced_clock); |
3243 | Serge | 4590 | |
3746 | Serge | 4591 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4592 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
||
3031 | serge | 4593 | |
4594 | dpll = DPLL_VGA_MODE_DIS; |
||
4595 | |||
3746 | Serge | 4596 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
3031 | serge | 4597 | dpll |= DPLLB_MODE_LVDS; |
4598 | else |
||
4599 | dpll |= DPLLB_MODE_DAC_SERIAL; |
||
3746 | Serge | 4600 | |
4104 | Serge | 4601 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
3746 | Serge | 4602 | dpll |= (crtc->config.pixel_multiplier - 1) |
4603 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
||
2342 | Serge | 4604 | } |
4104 | Serge | 4605 | |
4606 | if (is_sdvo) |
||
4607 | dpll |= DPLL_SDVO_HIGH_SPEED; |
||
4608 | |||
3746 | Serge | 4609 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4104 | Serge | 4610 | dpll |= DPLL_SDVO_HIGH_SPEED; |
2342 | Serge | 4611 | |
3031 | serge | 4612 | /* compute bitmask from p1 value */ |
4613 | if (IS_PINEVIEW(dev)) |
||
4614 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
||
4615 | else { |
||
4616 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
||
4617 | if (IS_G4X(dev) && reduced_clock) |
||
4618 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
||
4619 | } |
||
4620 | switch (clock->p2) { |
||
4621 | case 5: |
||
4622 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
||
4623 | break; |
||
4624 | case 7: |
||
4625 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
||
4626 | break; |
||
4627 | case 10: |
||
4628 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
||
4629 | break; |
||
4630 | case 14: |
||
4631 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
||
4632 | break; |
||
4633 | } |
||
4634 | if (INTEL_INFO(dev)->gen >= 4) |
||
4635 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
||
2327 | Serge | 4636 | |
4104 | Serge | 4637 | if (crtc->config.sdvo_tv_clock) |
3031 | serge | 4638 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
3746 | Serge | 4639 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
3031 | serge | 4640 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4641 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
||
4642 | else |
||
4643 | dpll |= PLL_REF_INPUT_DREFCLK; |
||
2327 | Serge | 4644 | |
3031 | serge | 4645 | dpll |= DPLL_VCO_ENABLE; |
4104 | Serge | 4646 | crtc->config.dpll_hw_state.dpll = dpll; |
2327 | Serge | 4647 | |
4104 | Serge | 4648 | if (INTEL_INFO(dev)->gen >= 4) { |
4649 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
||
4650 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
||
4651 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
||
4652 | } |
||
2327 | Serge | 4653 | |
3746 | Serge | 4654 | if (crtc->config.has_dp_encoder) |
4655 | intel_dp_set_m_n(crtc); |
||
3031 | serge | 4656 | } |
2327 | Serge | 4657 | |
3746 | Serge | 4658 | static void i8xx_update_pll(struct intel_crtc *crtc, |
4659 | intel_clock_t *reduced_clock, |
||
3031 | serge | 4660 | int num_connectors) |
4661 | { |
||
3746 | Serge | 4662 | struct drm_device *dev = crtc->base.dev; |
3031 | serge | 4663 | struct drm_i915_private *dev_priv = dev->dev_private; |
4664 | u32 dpll; |
||
3746 | Serge | 4665 | struct dpll *clock = &crtc->config.dpll; |
2327 | Serge | 4666 | |
3746 | Serge | 4667 | i9xx_update_pll_dividers(crtc, reduced_clock); |
3243 | Serge | 4668 | |
3031 | serge | 4669 | dpll = DPLL_VGA_MODE_DIS; |
2327 | Serge | 4670 | |
3746 | Serge | 4671 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
3031 | serge | 4672 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4673 | } else { |
||
4674 | if (clock->p1 == 2) |
||
4675 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
||
4676 | else |
||
4677 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
||
4678 | if (clock->p2 == 4) |
||
4679 | dpll |= PLL_P2_DIVIDE_BY_4; |
||
4680 | } |
||
2327 | Serge | 4681 | |
4104 | Serge | 4682 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4683 | dpll |= DPLL_DVO_2X_MODE; |
||
4684 | |||
3746 | Serge | 4685 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
3031 | serge | 4686 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4687 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
||
4688 | else |
||
4689 | dpll |= PLL_REF_INPUT_DREFCLK; |
||
4690 | |||
4691 | dpll |= DPLL_VCO_ENABLE; |
||
4104 | Serge | 4692 | crtc->config.dpll_hw_state.dpll = dpll; |
3031 | serge | 4693 | } |
4694 | |||
4104 | Serge | 4695 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
3243 | Serge | 4696 | { |
4697 | struct drm_device *dev = intel_crtc->base.dev; |
||
4698 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4699 | enum pipe pipe = intel_crtc->pipe; |
||
3746 | Serge | 4700 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4104 | Serge | 4701 | struct drm_display_mode *adjusted_mode = |
4702 | &intel_crtc->config.adjusted_mode; |
||
4703 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
||
4704 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
||
3243 | Serge | 4705 | |
4104 | Serge | 4706 | /* We need to be careful not to changed the adjusted mode, for otherwise |
4707 | * the hw state checker will get angry at the mismatch. */ |
||
4708 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
||
4709 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
||
4710 | |||
3243 | Serge | 4711 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4712 | /* the chip adds 2 halflines automatically */ |
||
4104 | Serge | 4713 | crtc_vtotal -= 1; |
4714 | crtc_vblank_end -= 1; |
||
3243 | Serge | 4715 | vsyncshift = adjusted_mode->crtc_hsync_start |
4716 | - adjusted_mode->crtc_htotal / 2; |
||
4717 | } else { |
||
4718 | vsyncshift = 0; |
||
4719 | } |
||
4720 | |||
4721 | if (INTEL_INFO(dev)->gen > 3) |
||
4722 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
||
4723 | |||
4724 | I915_WRITE(HTOTAL(cpu_transcoder), |
||
4725 | (adjusted_mode->crtc_hdisplay - 1) | |
||
4726 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
||
4727 | I915_WRITE(HBLANK(cpu_transcoder), |
||
4728 | (adjusted_mode->crtc_hblank_start - 1) | |
||
4729 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
||
4730 | I915_WRITE(HSYNC(cpu_transcoder), |
||
4731 | (adjusted_mode->crtc_hsync_start - 1) | |
||
4732 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
||
4733 | |||
4734 | I915_WRITE(VTOTAL(cpu_transcoder), |
||
4735 | (adjusted_mode->crtc_vdisplay - 1) | |
||
4104 | Serge | 4736 | ((crtc_vtotal - 1) << 16)); |
3243 | Serge | 4737 | I915_WRITE(VBLANK(cpu_transcoder), |
4738 | (adjusted_mode->crtc_vblank_start - 1) | |
||
4104 | Serge | 4739 | ((crtc_vblank_end - 1) << 16)); |
3243 | Serge | 4740 | I915_WRITE(VSYNC(cpu_transcoder), |
4741 | (adjusted_mode->crtc_vsync_start - 1) | |
||
4742 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
||
4743 | |||
4744 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
||
4745 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
||
4746 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
||
4747 | * bits. */ |
||
4748 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
||
4749 | (pipe == PIPE_B || pipe == PIPE_C)) |
||
4750 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
||
4751 | |||
4752 | /* pipesrc controls the size that is scaled from, which should |
||
4753 | * always be the user's requested size. |
||
4754 | */ |
||
4755 | I915_WRITE(PIPESRC(pipe), |
||
4756 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
||
4757 | } |
||
4758 | |||
4104 | Serge | 4759 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4760 | struct intel_crtc_config *pipe_config) |
||
4761 | { |
||
4762 | struct drm_device *dev = crtc->base.dev; |
||
4763 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4764 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
||
4765 | uint32_t tmp; |
||
4766 | |||
4767 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
||
4768 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
||
4769 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
||
4770 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
||
4771 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
||
4772 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
||
4773 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
||
4774 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
||
4775 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
||
4776 | |||
4777 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
||
4778 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
||
4779 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
||
4780 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
||
4781 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
||
4782 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
||
4783 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
||
4784 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
||
4785 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
||
4786 | |||
4787 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
||
4788 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
||
4789 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
||
4790 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
||
4791 | } |
||
4792 | |||
4793 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
||
4794 | pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; |
||
4795 | pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; |
||
4796 | } |
||
4797 | |||
4798 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
||
4799 | struct intel_crtc_config *pipe_config) |
||
4800 | { |
||
4801 | struct drm_crtc *crtc = &intel_crtc->base; |
||
4802 | |||
4803 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
||
4804 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; |
||
4805 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
||
4806 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
||
4807 | |||
4808 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
||
4809 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
||
4810 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
||
4811 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
||
4812 | |||
4813 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
||
4814 | |||
4815 | crtc->mode.clock = pipe_config->adjusted_mode.clock; |
||
4816 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
||
4817 | } |
||
4818 | |||
3746 | Serge | 4819 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4820 | { |
||
4821 | struct drm_device *dev = intel_crtc->base.dev; |
||
4822 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4823 | uint32_t pipeconf; |
||
4824 | |||
4104 | Serge | 4825 | pipeconf = 0; |
3746 | Serge | 4826 | |
4104 | Serge | 4827 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
4828 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
||
4829 | pipeconf |= PIPECONF_ENABLE; |
||
4830 | |||
3746 | Serge | 4831 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
4832 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
||
4833 | * core speed. |
||
4834 | * |
||
4835 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
||
4836 | * pipe == 0 check? |
||
4837 | */ |
||
4838 | if (intel_crtc->config.requested_mode.clock > |
||
4839 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
||
4840 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
||
4841 | } |
||
4842 | |||
4104 | Serge | 4843 | /* only g4x and later have fancy bpc/dither controls */ |
4844 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
||
4845 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
||
4846 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
||
4847 | pipeconf |= PIPECONF_DITHER_EN | |
||
3746 | Serge | 4848 | PIPECONF_DITHER_TYPE_SP; |
4849 | |||
4104 | Serge | 4850 | switch (intel_crtc->config.pipe_bpp) { |
4851 | case 18: |
||
4852 | pipeconf |= PIPECONF_6BPC; |
||
4853 | break; |
||
4854 | case 24: |
||
4855 | pipeconf |= PIPECONF_8BPC; |
||
4856 | break; |
||
4857 | case 30: |
||
4858 | pipeconf |= PIPECONF_10BPC; |
||
4859 | break; |
||
4860 | default: |
||
4861 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
||
4862 | BUG(); |
||
3746 | Serge | 4863 | } |
4864 | } |
||
4865 | |||
4866 | if (HAS_PIPE_CXSR(dev)) { |
||
4867 | if (intel_crtc->lowfreq_avail) { |
||
4868 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
||
4869 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
||
4870 | } else { |
||
4871 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
||
4872 | } |
||
4873 | } |
||
4874 | |||
4875 | if (!IS_GEN2(dev) && |
||
4876 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
||
4877 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
||
4878 | else |
||
4879 | pipeconf |= PIPECONF_PROGRESSIVE; |
||
4880 | |||
4104 | Serge | 4881 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
3746 | Serge | 4882 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
4883 | |||
4884 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
||
4885 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
||
4886 | } |
||
4887 | |||
3031 | serge | 4888 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4889 | int x, int y, |
||
4890 | struct drm_framebuffer *fb) |
||
4891 | { |
||
4892 | struct drm_device *dev = crtc->dev; |
||
4893 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3746 | Serge | 4895 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
3031 | serge | 4896 | int pipe = intel_crtc->pipe; |
4897 | int plane = intel_crtc->plane; |
||
4898 | int refclk, num_connectors = 0; |
||
4899 | intel_clock_t clock, reduced_clock; |
||
3746 | Serge | 4900 | u32 dspcntr; |
4104 | Serge | 4901 | bool ok, has_reduced_clock = false; |
4902 | bool is_lvds = false; |
||
3031 | serge | 4903 | struct intel_encoder *encoder; |
4904 | const intel_limit_t *limit; |
||
4905 | int ret; |
||
4906 | |||
4907 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
||
4908 | switch (encoder->type) { |
||
4909 | case INTEL_OUTPUT_LVDS: |
||
4910 | is_lvds = true; |
||
4911 | break; |
||
4912 | } |
||
4913 | |||
4914 | num_connectors++; |
||
4915 | } |
||
4916 | |||
4917 | refclk = i9xx_get_refclk(crtc, num_connectors); |
||
4918 | |||
4919 | /* |
||
4920 | * Returns a set of divisors for the desired target clock with the given |
||
4921 | * refclk, or FALSE. The returned values represent the clock equation: |
||
4922 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
||
4923 | */ |
||
4924 | limit = intel_limit(crtc, refclk); |
||
4104 | Serge | 4925 | ok = dev_priv->display.find_dpll(limit, crtc, |
4926 | intel_crtc->config.port_clock, |
||
4927 | refclk, NULL, &clock); |
||
4928 | if (!ok && !intel_crtc->config.clock_set) { |
||
3031 | serge | 4929 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4930 | return -EINVAL; |
||
4931 | } |
||
4932 | |||
4933 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
||
4934 | /* |
||
4935 | * Ensure we match the reduced clock's P to the target clock. |
||
4936 | * If the clocks don't match, we can't switch the display clock |
||
4937 | * by using the FP0/FP1. In such case we will disable the LVDS |
||
4938 | * downclock feature. |
||
4939 | */ |
||
4104 | Serge | 4940 | has_reduced_clock = |
4941 | dev_priv->display.find_dpll(limit, crtc, |
||
3031 | serge | 4942 | dev_priv->lvds_downclock, |
4104 | Serge | 4943 | refclk, &clock, |
3031 | serge | 4944 | &reduced_clock); |
4945 | } |
||
3746 | Serge | 4946 | /* Compat-code for transition, will disappear. */ |
4947 | if (!intel_crtc->config.clock_set) { |
||
4948 | intel_crtc->config.dpll.n = clock.n; |
||
4949 | intel_crtc->config.dpll.m1 = clock.m1; |
||
4950 | intel_crtc->config.dpll.m2 = clock.m2; |
||
4951 | intel_crtc->config.dpll.p1 = clock.p1; |
||
4952 | intel_crtc->config.dpll.p2 = clock.p2; |
||
4953 | } |
||
3031 | serge | 4954 | |
4955 | if (IS_GEN2(dev)) |
||
4104 | Serge | 4956 | i8xx_update_pll(intel_crtc, |
3243 | Serge | 4957 | has_reduced_clock ? &reduced_clock : NULL, |
4958 | num_connectors); |
||
3031 | serge | 4959 | else if (IS_VALLEYVIEW(dev)) |
3746 | Serge | 4960 | vlv_update_pll(intel_crtc); |
3031 | serge | 4961 | else |
3746 | Serge | 4962 | i9xx_update_pll(intel_crtc, |
3031 | serge | 4963 | has_reduced_clock ? &reduced_clock : NULL, |
4964 | num_connectors); |
||
4965 | |||
4966 | /* Set up the display plane register */ |
||
4967 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
||
4968 | |||
3746 | Serge | 4969 | if (!IS_VALLEYVIEW(dev)) { |
3031 | serge | 4970 | if (pipe == 0) |
4971 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
||
4972 | else |
||
4973 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
||
3243 | Serge | 4974 | } |
4975 | |||
4104 | Serge | 4976 | intel_set_pipe_timings(intel_crtc); |
3031 | serge | 4977 | |
4978 | /* pipesrc and dspsize control the size that is scaled from, |
||
4979 | * which should always be the user's requested size. |
||
4980 | */ |
||
4981 | I915_WRITE(DSPSIZE(plane), |
||
4982 | ((mode->vdisplay - 1) << 16) | |
||
4983 | (mode->hdisplay - 1)); |
||
4984 | I915_WRITE(DSPPOS(plane), 0); |
||
2327 | Serge | 4985 | |
3746 | Serge | 4986 | i9xx_set_pipeconf(intel_crtc); |
4987 | |||
3031 | serge | 4988 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4989 | POSTING_READ(DSPCNTR(plane)); |
||
2327 | Serge | 4990 | |
3031 | serge | 4991 | ret = intel_pipe_set_base(crtc, x, y, fb); |
2327 | Serge | 4992 | |
3031 | serge | 4993 | intel_update_watermarks(dev); |
4994 | |||
2327 | Serge | 4995 | return ret; |
4996 | } |
||
4997 | |||
4104 | Serge | 4998 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
4999 | struct intel_crtc_config *pipe_config) |
||
5000 | { |
||
5001 | struct drm_device *dev = crtc->base.dev; |
||
5002 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5003 | uint32_t tmp; |
||
5004 | |||
5005 | tmp = I915_READ(PFIT_CONTROL); |
||
5006 | if (!(tmp & PFIT_ENABLE)) |
||
5007 | return; |
||
5008 | |||
5009 | /* Check whether the pfit is attached to our pipe. */ |
||
5010 | if (INTEL_INFO(dev)->gen < 4) { |
||
5011 | if (crtc->pipe != PIPE_B) |
||
5012 | return; |
||
5013 | } else { |
||
5014 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
||
5015 | return; |
||
5016 | } |
||
5017 | |||
5018 | pipe_config->gmch_pfit.control = tmp; |
||
5019 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
||
5020 | if (INTEL_INFO(dev)->gen < 5) |
||
5021 | pipe_config->gmch_pfit.lvds_border_bits = |
||
5022 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
||
5023 | } |
||
5024 | |||
4398 | Serge | 5025 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5026 | struct intel_crtc_config *pipe_config) |
||
5027 | { |
||
5028 | struct drm_device *dev = crtc->base.dev; |
||
5029 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5030 | int pipe = pipe_config->cpu_transcoder; |
||
5031 | intel_clock_t clock; |
||
5032 | u32 mdiv; |
||
5033 | int refclk = 100000; |
||
5034 | |||
5035 | mutex_lock(&dev_priv->dpio_lock); |
||
5036 | mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); |
||
5037 | mutex_unlock(&dev_priv->dpio_lock); |
||
5038 | |||
5039 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
||
5040 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
||
5041 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
||
5042 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
||
5043 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
||
5044 | |||
5045 | clock.vco = refclk * clock.m1 * clock.m2 / clock.n; |
||
5046 | clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); |
||
5047 | |||
5048 | pipe_config->adjusted_mode.clock = clock.dot / 10; |
||
5049 | } |
||
5050 | |||
3746 | Serge | 5051 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5052 | struct intel_crtc_config *pipe_config) |
||
5053 | { |
||
5054 | struct drm_device *dev = crtc->base.dev; |
||
5055 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5056 | uint32_t tmp; |
||
5057 | |||
4104 | Serge | 5058 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5059 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
||
5060 | |||
3746 | Serge | 5061 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5062 | if (!(tmp & PIPECONF_ENABLE)) |
||
5063 | return false; |
||
5064 | |||
4280 | Serge | 5065 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5066 | switch (tmp & PIPECONF_BPC_MASK) { |
||
5067 | case PIPECONF_6BPC: |
||
5068 | pipe_config->pipe_bpp = 18; |
||
5069 | break; |
||
5070 | case PIPECONF_8BPC: |
||
5071 | pipe_config->pipe_bpp = 24; |
||
5072 | break; |
||
5073 | case PIPECONF_10BPC: |
||
5074 | pipe_config->pipe_bpp = 30; |
||
5075 | break; |
||
5076 | default: |
||
5077 | break; |
||
5078 | } |
||
5079 | } |
||
5080 | |||
4104 | Serge | 5081 | intel_get_pipe_timings(crtc, pipe_config); |
5082 | |||
5083 | i9xx_get_pfit_config(crtc, pipe_config); |
||
5084 | |||
5085 | if (INTEL_INFO(dev)->gen >= 4) { |
||
5086 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
||
5087 | pipe_config->pixel_multiplier = |
||
5088 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
||
5089 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
||
5090 | pipe_config->dpll_hw_state.dpll_md = tmp; |
||
5091 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
||
5092 | tmp = I915_READ(DPLL(crtc->pipe)); |
||
5093 | pipe_config->pixel_multiplier = |
||
5094 | ((tmp & SDVO_MULTIPLIER_MASK) |
||
5095 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
||
5096 | } else { |
||
5097 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
||
5098 | * port and will be fixed up in the encoder->get_config |
||
5099 | * function. */ |
||
5100 | pipe_config->pixel_multiplier = 1; |
||
5101 | } |
||
5102 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
||
5103 | if (!IS_VALLEYVIEW(dev)) { |
||
5104 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
||
5105 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
||
5106 | } else { |
||
5107 | /* Mask out read-only status bits. */ |
||
5108 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
||
5109 | DPLL_PORTC_READY_MASK | |
||
5110 | DPLL_PORTB_READY_MASK); |
||
5111 | } |
||
5112 | |||
3746 | Serge | 5113 | return true; |
5114 | } |
||
5115 | |||
3243 | Serge | 5116 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
2327 | Serge | 5117 | { |
5118 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5119 | struct drm_mode_config *mode_config = &dev->mode_config; |
||
5120 | struct intel_encoder *encoder; |
||
3746 | Serge | 5121 | u32 val, final; |
2327 | Serge | 5122 | bool has_lvds = false; |
2342 | Serge | 5123 | bool has_cpu_edp = false; |
5124 | bool has_panel = false; |
||
5125 | bool has_ck505 = false; |
||
5126 | bool can_ssc = false; |
||
2327 | Serge | 5127 | |
5128 | /* We need to take the global config into account */ |
||
5129 | list_for_each_entry(encoder, &mode_config->encoder_list, |
||
5130 | base.head) { |
||
5131 | switch (encoder->type) { |
||
5132 | case INTEL_OUTPUT_LVDS: |
||
2342 | Serge | 5133 | has_panel = true; |
2327 | Serge | 5134 | has_lvds = true; |
2342 | Serge | 5135 | break; |
2327 | Serge | 5136 | case INTEL_OUTPUT_EDP: |
2342 | Serge | 5137 | has_panel = true; |
4104 | Serge | 5138 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
2342 | Serge | 5139 | has_cpu_edp = true; |
2327 | Serge | 5140 | break; |
5141 | } |
||
5142 | } |
||
2342 | Serge | 5143 | |
5144 | if (HAS_PCH_IBX(dev)) { |
||
4104 | Serge | 5145 | has_ck505 = dev_priv->vbt.display_clock_mode; |
2342 | Serge | 5146 | can_ssc = has_ck505; |
5147 | } else { |
||
5148 | has_ck505 = false; |
||
5149 | can_ssc = true; |
||
2327 | Serge | 5150 | } |
5151 | |||
4104 | Serge | 5152 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5153 | has_panel, has_lvds, has_ck505); |
||
2342 | Serge | 5154 | |
2327 | Serge | 5155 | /* Ironlake: try to setup display ref clock before DPLL |
5156 | * enabling. This is only under driver's control after |
||
5157 | * PCH B stepping, previous chipset stepping should be |
||
5158 | * ignoring this setting. |
||
5159 | */ |
||
3746 | Serge | 5160 | val = I915_READ(PCH_DREF_CONTROL); |
5161 | |||
5162 | /* As we must carefully and slowly disable/enable each source in turn, |
||
5163 | * compute the final state we want first and check if we need to |
||
5164 | * make any changes at all. |
||
5165 | */ |
||
5166 | final = val; |
||
5167 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
||
5168 | if (has_ck505) |
||
5169 | final |= DREF_NONSPREAD_CK505_ENABLE; |
||
5170 | else |
||
5171 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
||
5172 | |||
5173 | final &= ~DREF_SSC_SOURCE_MASK; |
||
5174 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
||
5175 | final &= ~DREF_SSC1_ENABLE; |
||
5176 | |||
5177 | if (has_panel) { |
||
5178 | final |= DREF_SSC_SOURCE_ENABLE; |
||
5179 | |||
5180 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
||
5181 | final |= DREF_SSC1_ENABLE; |
||
5182 | |||
5183 | if (has_cpu_edp) { |
||
5184 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
||
5185 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
||
5186 | else |
||
5187 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
||
5188 | } else |
||
5189 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
||
5190 | } else { |
||
5191 | final |= DREF_SSC_SOURCE_DISABLE; |
||
5192 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
||
5193 | } |
||
5194 | |||
5195 | if (final == val) |
||
5196 | return; |
||
5197 | |||
2327 | Serge | 5198 | /* Always enable nonspread source */ |
3746 | Serge | 5199 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
2342 | Serge | 5200 | |
5201 | if (has_ck505) |
||
3746 | Serge | 5202 | val |= DREF_NONSPREAD_CK505_ENABLE; |
2342 | Serge | 5203 | else |
3746 | Serge | 5204 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
2342 | Serge | 5205 | |
5206 | if (has_panel) { |
||
3746 | Serge | 5207 | val &= ~DREF_SSC_SOURCE_MASK; |
5208 | val |= DREF_SSC_SOURCE_ENABLE; |
||
2327 | Serge | 5209 | |
2342 | Serge | 5210 | /* SSC must be turned on before enabling the CPU output */ |
5211 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
||
5212 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
||
3746 | Serge | 5213 | val |= DREF_SSC1_ENABLE; |
3031 | serge | 5214 | } else |
3746 | Serge | 5215 | val &= ~DREF_SSC1_ENABLE; |
2327 | Serge | 5216 | |
2342 | Serge | 5217 | /* Get SSC going before enabling the outputs */ |
3746 | Serge | 5218 | I915_WRITE(PCH_DREF_CONTROL, val); |
2327 | Serge | 5219 | POSTING_READ(PCH_DREF_CONTROL); |
5220 | udelay(200); |
||
2342 | Serge | 5221 | |
3746 | Serge | 5222 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
2327 | Serge | 5223 | |
5224 | /* Enable CPU source on CPU attached eDP */ |
||
2342 | Serge | 5225 | if (has_cpu_edp) { |
5226 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
||
5227 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
||
3746 | Serge | 5228 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
2342 | Serge | 5229 | } |
2327 | Serge | 5230 | else |
3746 | Serge | 5231 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
2342 | Serge | 5232 | } else |
3746 | Serge | 5233 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
2342 | Serge | 5234 | |
3746 | Serge | 5235 | I915_WRITE(PCH_DREF_CONTROL, val); |
2342 | Serge | 5236 | POSTING_READ(PCH_DREF_CONTROL); |
5237 | udelay(200); |
||
2327 | Serge | 5238 | } else { |
2342 | Serge | 5239 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
5240 | |||
3746 | Serge | 5241 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
2342 | Serge | 5242 | |
5243 | /* Turn off CPU output */ |
||
3746 | Serge | 5244 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
2342 | Serge | 5245 | |
3746 | Serge | 5246 | I915_WRITE(PCH_DREF_CONTROL, val); |
2327 | Serge | 5247 | POSTING_READ(PCH_DREF_CONTROL); |
5248 | udelay(200); |
||
2342 | Serge | 5249 | |
5250 | /* Turn off the SSC source */ |
||
3746 | Serge | 5251 | val &= ~DREF_SSC_SOURCE_MASK; |
5252 | val |= DREF_SSC_SOURCE_DISABLE; |
||
2342 | Serge | 5253 | |
5254 | /* Turn off SSC1 */ |
||
3746 | Serge | 5255 | val &= ~DREF_SSC1_ENABLE; |
2342 | Serge | 5256 | |
3746 | Serge | 5257 | I915_WRITE(PCH_DREF_CONTROL, val); |
2342 | Serge | 5258 | POSTING_READ(PCH_DREF_CONTROL); |
5259 | udelay(200); |
||
2327 | Serge | 5260 | } |
3746 | Serge | 5261 | |
5262 | BUG_ON(val != final); |
||
2327 | Serge | 5263 | } |
5264 | |||
4104 | Serge | 5265 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
3243 | Serge | 5266 | { |
4104 | Serge | 5267 | uint32_t tmp; |
3243 | Serge | 5268 | |
5269 | tmp = I915_READ(SOUTH_CHICKEN2); |
||
5270 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
||
5271 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
||
5272 | |||
5273 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
||
5274 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
||
5275 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
||
5276 | |||
5277 | tmp = I915_READ(SOUTH_CHICKEN2); |
||
5278 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
||
5279 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
||
5280 | |||
5281 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
||
4104 | Serge | 5282 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
3243 | Serge | 5283 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
5284 | } |
||
5285 | |||
4104 | Serge | 5286 | /* WaMPhyProgramming:hsw */ |
5287 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
||
5288 | { |
||
5289 | uint32_t tmp; |
||
5290 | |||
3243 | Serge | 5291 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
5292 | tmp &= ~(0xFF << 24); |
||
5293 | tmp |= (0x12 << 24); |
||
5294 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
||
5295 | |||
5296 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
||
5297 | tmp |= (1 << 11); |
||
5298 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
||
5299 | |||
5300 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
||
5301 | tmp |= (1 << 11); |
||
5302 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
||
5303 | |||
5304 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
||
5305 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
||
5306 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
||
5307 | |||
5308 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
||
5309 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
||
5310 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
||
5311 | |||
5312 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
||
5313 | tmp &= ~(7 << 13); |
||
5314 | tmp |= (5 << 13); |
||
5315 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
||
5316 | |||
5317 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
||
5318 | tmp &= ~(7 << 13); |
||
5319 | tmp |= (5 << 13); |
||
5320 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
||
5321 | |||
5322 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
||
5323 | tmp &= ~0xFF; |
||
5324 | tmp |= 0x1C; |
||
5325 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
||
5326 | |||
5327 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
||
5328 | tmp &= ~0xFF; |
||
5329 | tmp |= 0x1C; |
||
5330 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
||
5331 | |||
5332 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
||
5333 | tmp &= ~(0xFF << 16); |
||
5334 | tmp |= (0x1C << 16); |
||
5335 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
||
5336 | |||
5337 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
||
5338 | tmp &= ~(0xFF << 16); |
||
5339 | tmp |= (0x1C << 16); |
||
5340 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
||
5341 | |||
5342 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
||
5343 | tmp |= (1 << 27); |
||
5344 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
||
5345 | |||
5346 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
||
5347 | tmp |= (1 << 27); |
||
5348 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
||
5349 | |||
5350 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
||
5351 | tmp &= ~(0xF << 28); |
||
5352 | tmp |= (4 << 28); |
||
5353 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
||
5354 | |||
5355 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
||
5356 | tmp &= ~(0xF << 28); |
||
5357 | tmp |= (4 << 28); |
||
5358 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
||
5359 | } |
||
5360 | |||
4104 | Serge | 5361 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5362 | * Programming" based on the parameters passed: |
||
5363 | * - Sequence to enable CLKOUT_DP |
||
5364 | * - Sequence to enable CLKOUT_DP without spread |
||
5365 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
||
5366 | */ |
||
5367 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
||
5368 | bool with_fdi) |
||
5369 | { |
||
5370 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5371 | uint32_t reg, tmp; |
||
3480 | Serge | 5372 | |
4104 | Serge | 5373 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
5374 | with_spread = true; |
||
5375 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
||
5376 | with_fdi, "LP PCH doesn't have FDI\n")) |
||
5377 | with_fdi = false; |
||
5378 | |||
5379 | mutex_lock(&dev_priv->dpio_lock); |
||
5380 | |||
5381 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
||
5382 | tmp &= ~SBI_SSCCTL_DISABLE; |
||
5383 | tmp |= SBI_SSCCTL_PATHALT; |
||
5384 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
||
5385 | |||
5386 | udelay(24); |
||
5387 | |||
5388 | if (with_spread) { |
||
5389 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
||
5390 | tmp &= ~SBI_SSCCTL_PATHALT; |
||
5391 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
||
5392 | |||
5393 | if (with_fdi) { |
||
5394 | lpt_reset_fdi_mphy(dev_priv); |
||
5395 | lpt_program_fdi_mphy(dev_priv); |
||
5396 | } |
||
5397 | } |
||
5398 | |||
5399 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
||
5400 | SBI_GEN0 : SBI_DBUFF0; |
||
5401 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
||
5402 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
||
5403 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
||
5404 | |||
3480 | Serge | 5405 | mutex_unlock(&dev_priv->dpio_lock); |
3243 | Serge | 5406 | } |
5407 | |||
4104 | Serge | 5408 | /* Sequence to disable CLKOUT_DP */ |
5409 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
||
5410 | { |
||
5411 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5412 | uint32_t reg, tmp; |
||
5413 | |||
5414 | mutex_lock(&dev_priv->dpio_lock); |
||
5415 | |||
5416 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
||
5417 | SBI_GEN0 : SBI_DBUFF0; |
||
5418 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
||
5419 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
||
5420 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
||
5421 | |||
5422 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
||
5423 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
||
5424 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
||
5425 | tmp |= SBI_SSCCTL_PATHALT; |
||
5426 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
||
5427 | udelay(32); |
||
5428 | } |
||
5429 | tmp |= SBI_SSCCTL_DISABLE; |
||
5430 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
||
5431 | } |
||
5432 | |||
5433 | mutex_unlock(&dev_priv->dpio_lock); |
||
5434 | } |
||
5435 | |||
5436 | static void lpt_init_pch_refclk(struct drm_device *dev) |
||
5437 | { |
||
5438 | struct drm_mode_config *mode_config = &dev->mode_config; |
||
5439 | struct intel_encoder *encoder; |
||
5440 | bool has_vga = false; |
||
5441 | |||
5442 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
||
5443 | switch (encoder->type) { |
||
5444 | case INTEL_OUTPUT_ANALOG: |
||
5445 | has_vga = true; |
||
5446 | break; |
||
5447 | } |
||
5448 | } |
||
5449 | |||
5450 | if (has_vga) |
||
5451 | lpt_enable_clkout_dp(dev, true, true); |
||
5452 | else |
||
5453 | lpt_disable_clkout_dp(dev); |
||
5454 | } |
||
5455 | |||
3243 | Serge | 5456 | /* |
5457 | * Initialize reference clocks when the driver loads |
||
5458 | */ |
||
5459 | void intel_init_pch_refclk(struct drm_device *dev) |
||
5460 | { |
||
5461 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
||
5462 | ironlake_init_pch_refclk(dev); |
||
5463 | else if (HAS_PCH_LPT(dev)) |
||
5464 | lpt_init_pch_refclk(dev); |
||
5465 | } |
||
5466 | |||
2342 | Serge | 5467 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5468 | { |
||
5469 | struct drm_device *dev = crtc->dev; |
||
5470 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5471 | struct intel_encoder *encoder; |
||
5472 | int num_connectors = 0; |
||
5473 | bool is_lvds = false; |
||
5474 | |||
3031 | serge | 5475 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
2342 | Serge | 5476 | switch (encoder->type) { |
5477 | case INTEL_OUTPUT_LVDS: |
||
5478 | is_lvds = true; |
||
5479 | break; |
||
5480 | } |
||
5481 | num_connectors++; |
||
5482 | } |
||
5483 | |||
5484 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
||
5485 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
||
4104 | Serge | 5486 | dev_priv->vbt.lvds_ssc_freq); |
5487 | return dev_priv->vbt.lvds_ssc_freq * 1000; |
||
2342 | Serge | 5488 | } |
5489 | |||
5490 | return 120000; |
||
5491 | } |
||
5492 | |||
4104 | Serge | 5493 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
3031 | serge | 5494 | { |
5495 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
||
5496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5497 | int pipe = intel_crtc->pipe; |
||
5498 | uint32_t val; |
||
5499 | |||
4104 | Serge | 5500 | val = 0; |
3031 | serge | 5501 | |
3746 | Serge | 5502 | switch (intel_crtc->config.pipe_bpp) { |
3031 | serge | 5503 | case 18: |
3480 | Serge | 5504 | val |= PIPECONF_6BPC; |
3031 | serge | 5505 | break; |
5506 | case 24: |
||
3480 | Serge | 5507 | val |= PIPECONF_8BPC; |
3031 | serge | 5508 | break; |
5509 | case 30: |
||
3480 | Serge | 5510 | val |= PIPECONF_10BPC; |
3031 | serge | 5511 | break; |
5512 | case 36: |
||
3480 | Serge | 5513 | val |= PIPECONF_12BPC; |
3031 | serge | 5514 | break; |
5515 | default: |
||
3243 | Serge | 5516 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5517 | BUG(); |
||
3031 | serge | 5518 | } |
5519 | |||
4104 | Serge | 5520 | if (intel_crtc->config.dither) |
3031 | serge | 5521 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5522 | |||
4104 | Serge | 5523 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
3031 | serge | 5524 | val |= PIPECONF_INTERLACED_ILK; |
5525 | else |
||
5526 | val |= PIPECONF_PROGRESSIVE; |
||
5527 | |||
3746 | Serge | 5528 | if (intel_crtc->config.limited_color_range) |
3480 | Serge | 5529 | val |= PIPECONF_COLOR_RANGE_SELECT; |
5530 | |||
3031 | serge | 5531 | I915_WRITE(PIPECONF(pipe), val); |
5532 | POSTING_READ(PIPECONF(pipe)); |
||
5533 | } |
||
5534 | |||
3480 | Serge | 5535 | /* |
5536 | * Set up the pipe CSC unit. |
||
5537 | * |
||
5538 | * Currently only full range RGB to limited range RGB conversion |
||
5539 | * is supported, but eventually this should handle various |
||
5540 | * RGB<->YCbCr scenarios as well. |
||
5541 | */ |
||
3746 | Serge | 5542 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
3480 | Serge | 5543 | { |
5544 | struct drm_device *dev = crtc->dev; |
||
5545 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5546 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5547 | int pipe = intel_crtc->pipe; |
||
5548 | uint16_t coeff = 0x7800; /* 1.0 */ |
||
5549 | |||
5550 | /* |
||
5551 | * TODO: Check what kind of values actually come out of the pipe |
||
5552 | * with these coeff/postoff values and adjust to get the best |
||
5553 | * accuracy. Perhaps we even need to take the bpc value into |
||
5554 | * consideration. |
||
5555 | */ |
||
5556 | |||
3746 | Serge | 5557 | if (intel_crtc->config.limited_color_range) |
3480 | Serge | 5558 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5559 | |||
5560 | /* |
||
5561 | * GY/GU and RY/RU should be the other way around according |
||
5562 | * to BSpec, but reality doesn't agree. Just set them up in |
||
5563 | * a way that results in the correct picture. |
||
5564 | */ |
||
5565 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
||
5566 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
||
5567 | |||
5568 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
||
5569 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
||
5570 | |||
5571 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
||
5572 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
||
5573 | |||
5574 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
||
5575 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
||
5576 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
||
5577 | |||
5578 | if (INTEL_INFO(dev)->gen > 6) { |
||
5579 | uint16_t postoff = 0; |
||
5580 | |||
3746 | Serge | 5581 | if (intel_crtc->config.limited_color_range) |
4398 | Serge | 5582 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
3480 | Serge | 5583 | |
5584 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
||
5585 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
||
5586 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
||
5587 | |||
5588 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
||
5589 | } else { |
||
5590 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
||
5591 | |||
3746 | Serge | 5592 | if (intel_crtc->config.limited_color_range) |
3480 | Serge | 5593 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5594 | |||
5595 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
||
5596 | } |
||
5597 | } |
||
5598 | |||
4104 | Serge | 5599 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
3243 | Serge | 5600 | { |
5601 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
||
5602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3746 | Serge | 5603 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3243 | Serge | 5604 | uint32_t val; |
5605 | |||
4104 | Serge | 5606 | val = 0; |
3243 | Serge | 5607 | |
4104 | Serge | 5608 | if (intel_crtc->config.dither) |
3243 | Serge | 5609 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5610 | |||
4104 | Serge | 5611 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
3243 | Serge | 5612 | val |= PIPECONF_INTERLACED_ILK; |
5613 | else |
||
5614 | val |= PIPECONF_PROGRESSIVE; |
||
5615 | |||
5616 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
||
5617 | POSTING_READ(PIPECONF(cpu_transcoder)); |
||
4104 | Serge | 5618 | |
5619 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
||
5620 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
||
3243 | Serge | 5621 | } |
5622 | |||
3031 | serge | 5623 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5624 | intel_clock_t *clock, |
||
5625 | bool *has_reduced_clock, |
||
5626 | intel_clock_t *reduced_clock) |
||
5627 | { |
||
5628 | struct drm_device *dev = crtc->dev; |
||
5629 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5630 | struct intel_encoder *intel_encoder; |
||
5631 | int refclk; |
||
5632 | const intel_limit_t *limit; |
||
4104 | Serge | 5633 | bool ret, is_lvds = false; |
3031 | serge | 5634 | |
5635 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
||
5636 | switch (intel_encoder->type) { |
||
5637 | case INTEL_OUTPUT_LVDS: |
||
5638 | is_lvds = true; |
||
5639 | break; |
||
5640 | } |
||
5641 | } |
||
5642 | |||
5643 | refclk = ironlake_get_refclk(crtc); |
||
5644 | |||
5645 | /* |
||
5646 | * Returns a set of divisors for the desired target clock with the given |
||
5647 | * refclk, or FALSE. The returned values represent the clock equation: |
||
5648 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
||
5649 | */ |
||
5650 | limit = intel_limit(crtc, refclk); |
||
4104 | Serge | 5651 | ret = dev_priv->display.find_dpll(limit, crtc, |
5652 | to_intel_crtc(crtc)->config.port_clock, |
||
5653 | refclk, NULL, clock); |
||
3031 | serge | 5654 | if (!ret) |
5655 | return false; |
||
5656 | |||
5657 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
||
5658 | /* |
||
5659 | * Ensure we match the reduced clock's P to the target clock. |
||
5660 | * If the clocks don't match, we can't switch the display clock |
||
5661 | * by using the FP0/FP1. In such case we will disable the LVDS |
||
5662 | * downclock feature. |
||
5663 | */ |
||
4104 | Serge | 5664 | *has_reduced_clock = |
5665 | dev_priv->display.find_dpll(limit, crtc, |
||
3031 | serge | 5666 | dev_priv->lvds_downclock, |
4104 | Serge | 5667 | refclk, clock, |
3031 | serge | 5668 | reduced_clock); |
5669 | } |
||
5670 | |||
5671 | return true; |
||
5672 | } |
||
5673 | |||
3243 | Serge | 5674 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5675 | { |
||
5676 | /* |
||
5677 | * Account for spread spectrum to avoid |
||
5678 | * oversubscribing the link. Max center spread |
||
5679 | * is 2.5%; use 5% for safety's sake. |
||
5680 | */ |
||
5681 | u32 bps = target_clock * bpp * 21 / 20; |
||
5682 | return bps / (link_bw * 8) + 1; |
||
5683 | } |
||
5684 | |||
4104 | Serge | 5685 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
2327 | Serge | 5686 | { |
4104 | Serge | 5687 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
3746 | Serge | 5688 | } |
5689 | |||
3243 | Serge | 5690 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
4104 | Serge | 5691 | u32 *fp, |
3746 | Serge | 5692 | intel_clock_t *reduced_clock, u32 *fp2) |
3243 | Serge | 5693 | { |
5694 | struct drm_crtc *crtc = &intel_crtc->base; |
||
5695 | struct drm_device *dev = crtc->dev; |
||
5696 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5697 | struct intel_encoder *intel_encoder; |
||
5698 | uint32_t dpll; |
||
3746 | Serge | 5699 | int factor, num_connectors = 0; |
4104 | Serge | 5700 | bool is_lvds = false, is_sdvo = false; |
3243 | Serge | 5701 | |
5702 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
||
5703 | switch (intel_encoder->type) { |
||
5704 | case INTEL_OUTPUT_LVDS: |
||
5705 | is_lvds = true; |
||
5706 | break; |
||
5707 | case INTEL_OUTPUT_SDVO: |
||
5708 | case INTEL_OUTPUT_HDMI: |
||
5709 | is_sdvo = true; |
||
5710 | break; |
||
5711 | } |
||
5712 | |||
5713 | num_connectors++; |
||
5714 | } |
||
5715 | |||
2327 | Serge | 5716 | /* Enable autotuning of the PLL clock (if permissible) */ |
5717 | factor = 21; |
||
5718 | if (is_lvds) { |
||
5719 | if ((intel_panel_use_ssc(dev_priv) && |
||
4104 | Serge | 5720 | dev_priv->vbt.lvds_ssc_freq == 100) || |
3746 | Serge | 5721 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
2327 | Serge | 5722 | factor = 25; |
4104 | Serge | 5723 | } else if (intel_crtc->config.sdvo_tv_clock) |
2327 | Serge | 5724 | factor = 20; |
5725 | |||
4104 | Serge | 5726 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
3746 | Serge | 5727 | *fp |= FP_CB_TUNE; |
2327 | Serge | 5728 | |
3746 | Serge | 5729 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5730 | *fp2 |= FP_CB_TUNE; |
||
5731 | |||
2327 | Serge | 5732 | dpll = 0; |
5733 | |||
5734 | if (is_lvds) |
||
5735 | dpll |= DPLLB_MODE_LVDS; |
||
5736 | else |
||
5737 | dpll |= DPLLB_MODE_DAC_SERIAL; |
||
4104 | Serge | 5738 | |
3746 | Serge | 5739 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
5740 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
||
2327 | Serge | 5741 | |
4104 | Serge | 5742 | if (is_sdvo) |
5743 | dpll |= DPLL_SDVO_HIGH_SPEED; |
||
5744 | if (intel_crtc->config.has_dp_encoder) |
||
5745 | dpll |= DPLL_SDVO_HIGH_SPEED; |
||
5746 | |||
2327 | Serge | 5747 | /* compute bitmask from p1 value */ |
4104 | Serge | 5748 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2327 | Serge | 5749 | /* also FPA1 */ |
4104 | Serge | 5750 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
2327 | Serge | 5751 | |
4104 | Serge | 5752 | switch (intel_crtc->config.dpll.p2) { |
2327 | Serge | 5753 | case 5: |
5754 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
||
5755 | break; |
||
5756 | case 7: |
||
5757 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
||
5758 | break; |
||
5759 | case 10: |
||
5760 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
||
5761 | break; |
||
5762 | case 14: |
||
5763 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
||
5764 | break; |
||
5765 | } |
||
5766 | |||
4104 | Serge | 5767 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
2327 | Serge | 5768 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5769 | else |
||
5770 | dpll |= PLL_REF_INPUT_DREFCLK; |
||
5771 | |||
4104 | Serge | 5772 | return dpll | DPLL_VCO_ENABLE; |
3243 | Serge | 5773 | } |
5774 | |||
5775 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
||
5776 | int x, int y, |
||
5777 | struct drm_framebuffer *fb) |
||
5778 | { |
||
5779 | struct drm_device *dev = crtc->dev; |
||
5780 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5782 | int pipe = intel_crtc->pipe; |
||
5783 | int plane = intel_crtc->plane; |
||
5784 | int num_connectors = 0; |
||
5785 | intel_clock_t clock, reduced_clock; |
||
4104 | Serge | 5786 | u32 dpll = 0, fp = 0, fp2 = 0; |
3243 | Serge | 5787 | bool ok, has_reduced_clock = false; |
3746 | Serge | 5788 | bool is_lvds = false; |
3243 | Serge | 5789 | struct intel_encoder *encoder; |
4104 | Serge | 5790 | struct intel_shared_dpll *pll; |
3243 | Serge | 5791 | int ret; |
5792 | |||
5793 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
||
5794 | switch (encoder->type) { |
||
5795 | case INTEL_OUTPUT_LVDS: |
||
5796 | is_lvds = true; |
||
5797 | break; |
||
5798 | } |
||
5799 | |||
5800 | num_connectors++; |
||
5801 | } |
||
5802 | |||
5803 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
||
5804 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
||
5805 | |||
4104 | Serge | 5806 | ok = ironlake_compute_clocks(crtc, &clock, |
3243 | Serge | 5807 | &has_reduced_clock, &reduced_clock); |
4104 | Serge | 5808 | if (!ok && !intel_crtc->config.clock_set) { |
3243 | Serge | 5809 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5810 | return -EINVAL; |
||
5811 | } |
||
3746 | Serge | 5812 | /* Compat-code for transition, will disappear. */ |
5813 | if (!intel_crtc->config.clock_set) { |
||
5814 | intel_crtc->config.dpll.n = clock.n; |
||
5815 | intel_crtc->config.dpll.m1 = clock.m1; |
||
5816 | intel_crtc->config.dpll.m2 = clock.m2; |
||
5817 | intel_crtc->config.dpll.p1 = clock.p1; |
||
5818 | intel_crtc->config.dpll.p2 = clock.p2; |
||
5819 | } |
||
3243 | Serge | 5820 | |
4104 | Serge | 5821 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
5822 | if (intel_crtc->config.has_pch_encoder) { |
||
5823 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
||
3243 | Serge | 5824 | if (has_reduced_clock) |
4104 | Serge | 5825 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
3243 | Serge | 5826 | |
4104 | Serge | 5827 | dpll = ironlake_compute_dpll(intel_crtc, |
5828 | &fp, &reduced_clock, |
||
3746 | Serge | 5829 | has_reduced_clock ? &fp2 : NULL); |
3243 | Serge | 5830 | |
4104 | Serge | 5831 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
5832 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
||
5833 | if (has_reduced_clock) |
||
5834 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
||
5835 | else |
||
5836 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
||
2327 | Serge | 5837 | |
4104 | Serge | 5838 | pll = intel_get_shared_dpll(intel_crtc); |
3031 | serge | 5839 | if (pll == NULL) { |
4104 | Serge | 5840 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
5841 | pipe_name(pipe)); |
||
2342 | Serge | 5842 | return -EINVAL; |
2327 | Serge | 5843 | } |
3031 | serge | 5844 | } else |
4104 | Serge | 5845 | intel_put_shared_dpll(intel_crtc); |
2327 | Serge | 5846 | |
3746 | Serge | 5847 | if (intel_crtc->config.has_dp_encoder) |
5848 | intel_dp_set_m_n(intel_crtc); |
||
2342 | Serge | 5849 | |
4104 | Serge | 5850 | if (is_lvds && has_reduced_clock && i915_powersave) |
5851 | intel_crtc->lowfreq_avail = true; |
||
5852 | else |
||
5853 | intel_crtc->lowfreq_avail = false; |
||
2327 | Serge | 5854 | |
4104 | Serge | 5855 | if (intel_crtc->config.has_pch_encoder) { |
5856 | pll = intel_crtc_to_shared_dpll(intel_crtc); |
||
2327 | Serge | 5857 | |
4104 | Serge | 5858 | } |
2327 | Serge | 5859 | |
4104 | Serge | 5860 | intel_set_pipe_timings(intel_crtc); |
2327 | Serge | 5861 | |
4104 | Serge | 5862 | if (intel_crtc->config.has_pch_encoder) { |
5863 | intel_cpu_transcoder_set_m_n(intel_crtc, |
||
5864 | &intel_crtc->config.fdi_m_n); |
||
2342 | Serge | 5865 | } |
2327 | Serge | 5866 | |
4104 | Serge | 5867 | ironlake_set_pipeconf(crtc); |
3243 | Serge | 5868 | |
5869 | /* Set up the display plane register */ |
||
5870 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
||
5871 | POSTING_READ(DSPCNTR(plane)); |
||
5872 | |||
5873 | ret = intel_pipe_set_base(crtc, x, y, fb); |
||
5874 | |||
5875 | intel_update_watermarks(dev); |
||
5876 | |||
4104 | Serge | 5877 | return ret; |
5878 | } |
||
3243 | Serge | 5879 | |
4104 | Serge | 5880 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5881 | struct intel_crtc_config *pipe_config) |
||
5882 | { |
||
5883 | struct drm_device *dev = crtc->base.dev; |
||
5884 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5885 | enum transcoder transcoder = pipe_config->cpu_transcoder; |
||
5886 | |||
5887 | pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
||
5888 | pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
||
5889 | pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
||
5890 | & ~TU_SIZE_MASK; |
||
5891 | pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
||
5892 | pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
||
5893 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
||
3243 | Serge | 5894 | } |
5895 | |||
4104 | Serge | 5896 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5897 | struct intel_crtc_config *pipe_config) |
||
5898 | { |
||
5899 | struct drm_device *dev = crtc->base.dev; |
||
5900 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5901 | uint32_t tmp; |
||
5902 | |||
5903 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
||
5904 | |||
5905 | if (tmp & PF_ENABLE) { |
||
5906 | pipe_config->pch_pfit.enabled = true; |
||
5907 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
||
5908 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
||
5909 | |||
5910 | /* We currently do not free assignements of panel fitters on |
||
5911 | * ivb/hsw (since we don't use the higher upscaling modes which |
||
5912 | * differentiates them) so just WARN about this case for now. */ |
||
5913 | if (IS_GEN7(dev)) { |
||
5914 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
||
5915 | PF_PIPE_SEL_IVB(crtc->pipe)); |
||
5916 | } |
||
5917 | } |
||
5918 | } |
||
5919 | |||
3746 | Serge | 5920 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5921 | struct intel_crtc_config *pipe_config) |
||
5922 | { |
||
5923 | struct drm_device *dev = crtc->base.dev; |
||
5924 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5925 | uint32_t tmp; |
||
5926 | |||
4104 | Serge | 5927 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5928 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
||
5929 | |||
3746 | Serge | 5930 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5931 | if (!(tmp & PIPECONF_ENABLE)) |
||
5932 | return false; |
||
5933 | |||
4280 | Serge | 5934 | switch (tmp & PIPECONF_BPC_MASK) { |
5935 | case PIPECONF_6BPC: |
||
5936 | pipe_config->pipe_bpp = 18; |
||
5937 | break; |
||
5938 | case PIPECONF_8BPC: |
||
5939 | pipe_config->pipe_bpp = 24; |
||
5940 | break; |
||
5941 | case PIPECONF_10BPC: |
||
5942 | pipe_config->pipe_bpp = 30; |
||
5943 | break; |
||
5944 | case PIPECONF_12BPC: |
||
5945 | pipe_config->pipe_bpp = 36; |
||
5946 | break; |
||
5947 | default: |
||
5948 | break; |
||
5949 | } |
||
5950 | |||
4104 | Serge | 5951 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
5952 | struct intel_shared_dpll *pll; |
||
5953 | |||
3746 | Serge | 5954 | pipe_config->has_pch_encoder = true; |
5955 | |||
4104 | Serge | 5956 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
5957 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
||
5958 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
||
5959 | |||
5960 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
||
5961 | |||
5962 | if (HAS_PCH_IBX(dev_priv->dev)) { |
||
5963 | pipe_config->shared_dpll = |
||
5964 | (enum intel_dpll_id) crtc->pipe; |
||
5965 | } else { |
||
5966 | tmp = I915_READ(PCH_DPLL_SEL); |
||
5967 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
||
5968 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
||
5969 | else |
||
5970 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
||
5971 | } |
||
5972 | |||
5973 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
||
5974 | |||
5975 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
||
5976 | &pipe_config->dpll_hw_state)); |
||
5977 | |||
5978 | tmp = pipe_config->dpll_hw_state.dpll; |
||
5979 | pipe_config->pixel_multiplier = |
||
5980 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
||
5981 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
||
5982 | } else { |
||
5983 | pipe_config->pixel_multiplier = 1; |
||
5984 | } |
||
5985 | |||
5986 | intel_get_pipe_timings(crtc, pipe_config); |
||
5987 | |||
5988 | ironlake_get_pfit_config(crtc, pipe_config); |
||
5989 | |||
3746 | Serge | 5990 | return true; |
5991 | } |
||
5992 | |||
4104 | Serge | 5993 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
5994 | { |
||
5995 | struct drm_device *dev = dev_priv->dev; |
||
5996 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
||
5997 | struct intel_crtc *crtc; |
||
5998 | unsigned long irqflags; |
||
5999 | uint32_t val; |
||
6000 | |||
6001 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
||
6002 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", |
||
6003 | pipe_name(crtc->pipe)); |
||
6004 | |||
6005 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
||
6006 | WARN(plls->spll_refcount, "SPLL enabled\n"); |
||
6007 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); |
||
6008 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); |
||
6009 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
||
6010 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
||
6011 | "CPU PWM1 enabled\n"); |
||
6012 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
||
6013 | "CPU PWM2 enabled\n"); |
||
6014 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
||
6015 | "PCH PWM1 enabled\n"); |
||
6016 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
||
6017 | "Utility pin enabled\n"); |
||
6018 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
||
6019 | |||
6020 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
||
6021 | val = I915_READ(DEIMR); |
||
6022 | WARN((val & ~DE_PCH_EVENT_IVB) != val, |
||
6023 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
||
6024 | val = I915_READ(SDEIMR); |
||
6025 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
||
6026 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
||
6027 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
||
6028 | } |
||
6029 | |||
6030 | /* |
||
6031 | * This function implements pieces of two sequences from BSpec: |
||
6032 | * - Sequence for display software to disable LCPLL |
||
6033 | * - Sequence for display software to allow package C8+ |
||
6034 | * The steps implemented here are just the steps that actually touch the LCPLL |
||
6035 | * register. Callers should take care of disabling all the display engine |
||
6036 | * functions, doing the mode unset, fixing interrupts, etc. |
||
6037 | */ |
||
6038 | void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
||
6039 | bool switch_to_fclk, bool allow_power_down) |
||
6040 | { |
||
6041 | uint32_t val; |
||
6042 | |||
6043 | assert_can_disable_lcpll(dev_priv); |
||
6044 | |||
6045 | val = I915_READ(LCPLL_CTL); |
||
6046 | |||
6047 | if (switch_to_fclk) { |
||
6048 | val |= LCPLL_CD_SOURCE_FCLK; |
||
6049 | I915_WRITE(LCPLL_CTL, val); |
||
6050 | |||
6051 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
||
6052 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
||
6053 | DRM_ERROR("Switching to FCLK failed\n"); |
||
6054 | |||
6055 | val = I915_READ(LCPLL_CTL); |
||
6056 | } |
||
6057 | |||
6058 | val |= LCPLL_PLL_DISABLE; |
||
6059 | I915_WRITE(LCPLL_CTL, val); |
||
6060 | POSTING_READ(LCPLL_CTL); |
||
6061 | |||
6062 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
||
6063 | DRM_ERROR("LCPLL still locked\n"); |
||
6064 | |||
6065 | val = I915_READ(D_COMP); |
||
6066 | val |= D_COMP_COMP_DISABLE; |
||
6067 | I915_WRITE(D_COMP, val); |
||
6068 | POSTING_READ(D_COMP); |
||
6069 | udelay(100); |
||
6070 | |||
6071 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
||
6072 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
||
6073 | |||
6074 | if (allow_power_down) { |
||
6075 | val = I915_READ(LCPLL_CTL); |
||
6076 | val |= LCPLL_POWER_DOWN_ALLOW; |
||
6077 | I915_WRITE(LCPLL_CTL, val); |
||
6078 | POSTING_READ(LCPLL_CTL); |
||
6079 | } |
||
6080 | } |
||
6081 | |||
6082 | /* |
||
6083 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
||
6084 | * source. |
||
6085 | */ |
||
6086 | void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
||
6087 | { |
||
6088 | uint32_t val; |
||
6089 | |||
6090 | val = I915_READ(LCPLL_CTL); |
||
6091 | |||
6092 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
||
6093 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
||
6094 | return; |
||
6095 | |||
6096 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
||
6097 | * we'll hang the machine! */ |
||
4398 | Serge | 6098 | gen6_gt_force_wake_get(dev_priv); |
4104 | Serge | 6099 | |
6100 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
||
6101 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
||
6102 | I915_WRITE(LCPLL_CTL, val); |
||
6103 | POSTING_READ(LCPLL_CTL); |
||
6104 | } |
||
6105 | |||
6106 | val = I915_READ(D_COMP); |
||
6107 | val |= D_COMP_COMP_FORCE; |
||
6108 | val &= ~D_COMP_COMP_DISABLE; |
||
6109 | I915_WRITE(D_COMP, val); |
||
6110 | POSTING_READ(D_COMP); |
||
6111 | |||
6112 | val = I915_READ(LCPLL_CTL); |
||
6113 | val &= ~LCPLL_PLL_DISABLE; |
||
6114 | I915_WRITE(LCPLL_CTL, val); |
||
6115 | |||
6116 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
||
6117 | DRM_ERROR("LCPLL not locked yet\n"); |
||
6118 | |||
6119 | if (val & LCPLL_CD_SOURCE_FCLK) { |
||
6120 | val = I915_READ(LCPLL_CTL); |
||
6121 | val &= ~LCPLL_CD_SOURCE_FCLK; |
||
6122 | I915_WRITE(LCPLL_CTL, val); |
||
6123 | |||
6124 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
||
6125 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
||
6126 | DRM_ERROR("Switching back to LCPLL failed\n"); |
||
6127 | } |
||
6128 | |||
4398 | Serge | 6129 | gen6_gt_force_wake_put(dev_priv); |
4104 | Serge | 6130 | } |
6131 | |||
6132 | void hsw_enable_pc8_work(struct work_struct *__work) |
||
6133 | { |
||
6134 | struct drm_i915_private *dev_priv = |
||
6135 | container_of(to_delayed_work(__work), struct drm_i915_private, |
||
6136 | pc8.enable_work); |
||
6137 | struct drm_device *dev = dev_priv->dev; |
||
6138 | uint32_t val; |
||
6139 | |||
6140 | if (dev_priv->pc8.enabled) |
||
6141 | return; |
||
6142 | |||
6143 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
||
6144 | |||
6145 | dev_priv->pc8.enabled = true; |
||
6146 | |||
6147 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
||
6148 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
||
6149 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
||
6150 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
||
6151 | } |
||
6152 | |||
6153 | lpt_disable_clkout_dp(dev); |
||
6154 | hsw_pc8_disable_interrupts(dev); |
||
6155 | hsw_disable_lcpll(dev_priv, true, true); |
||
6156 | } |
||
6157 | |||
6158 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
||
6159 | { |
||
6160 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
||
6161 | WARN(dev_priv->pc8.disable_count < 1, |
||
6162 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
||
6163 | |||
6164 | dev_priv->pc8.disable_count--; |
||
6165 | if (dev_priv->pc8.disable_count != 0) |
||
6166 | return; |
||
6167 | |||
6168 | schedule_delayed_work(&dev_priv->pc8.enable_work, |
||
6169 | msecs_to_jiffies(i915_pc8_timeout)); |
||
6170 | } |
||
6171 | |||
6172 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
||
6173 | { |
||
6174 | struct drm_device *dev = dev_priv->dev; |
||
6175 | uint32_t val; |
||
6176 | |||
6177 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
||
6178 | WARN(dev_priv->pc8.disable_count < 0, |
||
6179 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
||
6180 | |||
6181 | dev_priv->pc8.disable_count++; |
||
6182 | if (dev_priv->pc8.disable_count != 1) |
||
6183 | return; |
||
6184 | |||
4293 | Serge | 6185 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
4104 | Serge | 6186 | if (!dev_priv->pc8.enabled) |
6187 | return; |
||
6188 | |||
6189 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
||
6190 | |||
6191 | hsw_restore_lcpll(dev_priv); |
||
6192 | hsw_pc8_restore_interrupts(dev); |
||
6193 | lpt_init_pch_refclk(dev); |
||
6194 | |||
6195 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
||
6196 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
||
6197 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
||
6198 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
||
6199 | } |
||
6200 | |||
6201 | intel_prepare_ddi(dev); |
||
6202 | i915_gem_init_swizzling(dev); |
||
6203 | mutex_lock(&dev_priv->rps.hw_lock); |
||
6204 | gen6_update_ring_freq(dev); |
||
6205 | mutex_unlock(&dev_priv->rps.hw_lock); |
||
6206 | dev_priv->pc8.enabled = false; |
||
6207 | } |
||
6208 | |||
6209 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
||
6210 | { |
||
6211 | mutex_lock(&dev_priv->pc8.lock); |
||
6212 | __hsw_enable_package_c8(dev_priv); |
||
6213 | mutex_unlock(&dev_priv->pc8.lock); |
||
6214 | } |
||
6215 | |||
6216 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
||
6217 | { |
||
6218 | mutex_lock(&dev_priv->pc8.lock); |
||
6219 | __hsw_disable_package_c8(dev_priv); |
||
6220 | mutex_unlock(&dev_priv->pc8.lock); |
||
6221 | } |
||
6222 | |||
6223 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) |
||
6224 | { |
||
6225 | struct drm_device *dev = dev_priv->dev; |
||
6226 | struct intel_crtc *crtc; |
||
6227 | uint32_t val; |
||
6228 | |||
6229 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
||
6230 | if (crtc->base.enabled) |
||
6231 | return false; |
||
6232 | |||
6233 | /* This case is still possible since we have the i915.disable_power_well |
||
6234 | * parameter and also the KVMr or something else might be requesting the |
||
6235 | * power well. */ |
||
6236 | val = I915_READ(HSW_PWR_WELL_DRIVER); |
||
6237 | if (val != 0) { |
||
6238 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); |
||
6239 | return false; |
||
6240 | } |
||
6241 | |||
6242 | return true; |
||
6243 | } |
||
6244 | |||
6245 | /* Since we're called from modeset_global_resources there's no way to |
||
6246 | * symmetrically increase and decrease the refcount, so we use |
||
6247 | * dev_priv->pc8.requirements_met to track whether we already have the refcount |
||
6248 | * or not. |
||
6249 | */ |
||
6250 | static void hsw_update_package_c8(struct drm_device *dev) |
||
6251 | { |
||
6252 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6253 | bool allow; |
||
6254 | |||
6255 | if (!i915_enable_pc8) |
||
6256 | return; |
||
6257 | |||
6258 | mutex_lock(&dev_priv->pc8.lock); |
||
6259 | |||
6260 | allow = hsw_can_enable_package_c8(dev_priv); |
||
6261 | |||
6262 | if (allow == dev_priv->pc8.requirements_met) |
||
6263 | goto done; |
||
6264 | |||
6265 | dev_priv->pc8.requirements_met = allow; |
||
6266 | |||
6267 | if (allow) |
||
6268 | __hsw_enable_package_c8(dev_priv); |
||
6269 | else |
||
6270 | __hsw_disable_package_c8(dev_priv); |
||
6271 | |||
6272 | done: |
||
6273 | mutex_unlock(&dev_priv->pc8.lock); |
||
6274 | } |
||
6275 | |||
6276 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
||
6277 | { |
||
6278 | if (!dev_priv->pc8.gpu_idle) { |
||
6279 | dev_priv->pc8.gpu_idle = true; |
||
6280 | hsw_enable_package_c8(dev_priv); |
||
6281 | } |
||
6282 | } |
||
6283 | |||
6284 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
||
6285 | { |
||
6286 | if (dev_priv->pc8.gpu_idle) { |
||
6287 | dev_priv->pc8.gpu_idle = false; |
||
6288 | hsw_disable_package_c8(dev_priv); |
||
6289 | } |
||
6290 | } |
||
6291 | |||
3480 | Serge | 6292 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6293 | { |
||
6294 | bool enable = false; |
||
6295 | struct intel_crtc *crtc; |
||
6296 | |||
6297 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
||
4104 | Serge | 6298 | if (!crtc->base.enabled) |
6299 | continue; |
||
3480 | Serge | 6300 | |
4104 | Serge | 6301 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
6302 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
||
3480 | Serge | 6303 | enable = true; |
6304 | } |
||
6305 | |||
4104 | Serge | 6306 | intel_set_power_well(dev, enable); |
3480 | Serge | 6307 | |
4104 | Serge | 6308 | hsw_update_package_c8(dev); |
3480 | Serge | 6309 | } |
6310 | |||
3243 | Serge | 6311 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
6312 | int x, int y, |
||
6313 | struct drm_framebuffer *fb) |
||
6314 | { |
||
6315 | struct drm_device *dev = crtc->dev; |
||
6316 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6318 | int plane = intel_crtc->plane; |
||
6319 | int ret; |
||
6320 | |||
4104 | Serge | 6321 | if (!intel_ddi_pll_mode_set(crtc)) |
3243 | Serge | 6322 | return -EINVAL; |
6323 | |||
3746 | Serge | 6324 | if (intel_crtc->config.has_dp_encoder) |
6325 | intel_dp_set_m_n(intel_crtc); |
||
2327 | Serge | 6326 | |
3243 | Serge | 6327 | intel_crtc->lowfreq_avail = false; |
2327 | Serge | 6328 | |
4104 | Serge | 6329 | intel_set_pipe_timings(intel_crtc); |
3243 | Serge | 6330 | |
4104 | Serge | 6331 | if (intel_crtc->config.has_pch_encoder) { |
6332 | intel_cpu_transcoder_set_m_n(intel_crtc, |
||
6333 | &intel_crtc->config.fdi_m_n); |
||
6334 | } |
||
3243 | Serge | 6335 | |
4104 | Serge | 6336 | haswell_set_pipeconf(crtc); |
2327 | Serge | 6337 | |
3746 | Serge | 6338 | intel_set_pipe_csc(crtc); |
3480 | Serge | 6339 | |
3031 | serge | 6340 | /* Set up the display plane register */ |
3480 | Serge | 6341 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
2327 | Serge | 6342 | POSTING_READ(DSPCNTR(plane)); |
6343 | |||
3031 | serge | 6344 | ret = intel_pipe_set_base(crtc, x, y, fb); |
2327 | Serge | 6345 | |
6346 | intel_update_watermarks(dev); |
||
6347 | |||
6348 | return ret; |
||
6349 | } |
||
6350 | |||
3746 | Serge | 6351 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6352 | struct intel_crtc_config *pipe_config) |
||
6353 | { |
||
6354 | struct drm_device *dev = crtc->base.dev; |
||
6355 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4104 | Serge | 6356 | enum intel_display_power_domain pfit_domain; |
3746 | Serge | 6357 | uint32_t tmp; |
6358 | |||
4104 | Serge | 6359 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6360 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
||
6361 | |||
6362 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
||
6363 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
||
6364 | enum pipe trans_edp_pipe; |
||
6365 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
||
6366 | default: |
||
6367 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
||
6368 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
||
6369 | case TRANS_DDI_EDP_INPUT_A_ON: |
||
6370 | trans_edp_pipe = PIPE_A; |
||
6371 | break; |
||
6372 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
||
6373 | trans_edp_pipe = PIPE_B; |
||
6374 | break; |
||
6375 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
||
6376 | trans_edp_pipe = PIPE_C; |
||
6377 | break; |
||
6378 | } |
||
6379 | |||
6380 | if (trans_edp_pipe == crtc->pipe) |
||
6381 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
||
6382 | } |
||
6383 | |||
6384 | if (!intel_display_power_enabled(dev, |
||
6385 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
||
6386 | return false; |
||
6387 | |||
6388 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
||
3746 | Serge | 6389 | if (!(tmp & PIPECONF_ENABLE)) |
6390 | return false; |
||
6391 | |||
6392 | /* |
||
4104 | Serge | 6393 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
3746 | Serge | 6394 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6395 | * the PCH transcoder is on. |
||
6396 | */ |
||
4104 | Serge | 6397 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
3746 | Serge | 6398 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
4104 | Serge | 6399 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
3746 | Serge | 6400 | pipe_config->has_pch_encoder = true; |
6401 | |||
4104 | Serge | 6402 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6403 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
||
6404 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
||
3746 | Serge | 6405 | |
4104 | Serge | 6406 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
6407 | } |
||
6408 | |||
6409 | intel_get_pipe_timings(crtc, pipe_config); |
||
6410 | |||
6411 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
||
6412 | if (intel_display_power_enabled(dev, pfit_domain)) |
||
6413 | ironlake_get_pfit_config(crtc, pipe_config); |
||
6414 | |||
6415 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
||
6416 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
||
6417 | |||
6418 | pipe_config->pixel_multiplier = 1; |
||
6419 | |||
3746 | Serge | 6420 | return true; |
6421 | } |
||
6422 | |||
2330 | Serge | 6423 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6424 | int x, int y, |
||
3031 | serge | 6425 | struct drm_framebuffer *fb) |
2330 | Serge | 6426 | { |
6427 | struct drm_device *dev = crtc->dev; |
||
6428 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3243 | Serge | 6429 | struct intel_encoder *encoder; |
2330 | Serge | 6430 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3746 | Serge | 6431 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
2330 | Serge | 6432 | int pipe = intel_crtc->pipe; |
6433 | int ret; |
||
2327 | Serge | 6434 | |
3031 | serge | 6435 | drm_vblank_pre_modeset(dev, pipe); |
2327 | Serge | 6436 | |
3746 | Serge | 6437 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6438 | |||
3031 | serge | 6439 | drm_vblank_post_modeset(dev, pipe); |
2327 | Serge | 6440 | |
3243 | Serge | 6441 | if (ret != 0) |
2330 | Serge | 6442 | return ret; |
3243 | Serge | 6443 | |
6444 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
||
6445 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
||
6446 | encoder->base.base.id, |
||
6447 | drm_get_encoder_name(&encoder->base), |
||
6448 | mode->base.id, mode->name); |
||
3746 | Serge | 6449 | encoder->mode_set(encoder); |
3243 | Serge | 6450 | } |
6451 | |||
6452 | return 0; |
||
2330 | Serge | 6453 | } |
2327 | Serge | 6454 | |
2342 | Serge | 6455 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6456 | int reg_eldv, uint32_t bits_eldv, |
||
6457 | int reg_elda, uint32_t bits_elda, |
||
6458 | int reg_edid) |
||
6459 | { |
||
6460 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
6461 | uint8_t *eld = connector->eld; |
||
6462 | uint32_t i; |
||
6463 | |||
6464 | i = I915_READ(reg_eldv); |
||
6465 | i &= bits_eldv; |
||
6466 | |||
6467 | if (!eld[0]) |
||
6468 | return !i; |
||
6469 | |||
6470 | if (!i) |
||
6471 | return false; |
||
6472 | |||
6473 | i = I915_READ(reg_elda); |
||
6474 | i &= ~bits_elda; |
||
6475 | I915_WRITE(reg_elda, i); |
||
6476 | |||
6477 | for (i = 0; i < eld[2]; i++) |
||
6478 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
||
6479 | return false; |
||
6480 | |||
6481 | return true; |
||
6482 | } |
||
6483 | |||
6484 | static void g4x_write_eld(struct drm_connector *connector, |
||
6485 | struct drm_crtc *crtc) |
||
6486 | { |
||
6487 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
6488 | uint8_t *eld = connector->eld; |
||
6489 | uint32_t eldv; |
||
6490 | uint32_t len; |
||
6491 | uint32_t i; |
||
6492 | |||
6493 | i = I915_READ(G4X_AUD_VID_DID); |
||
6494 | |||
6495 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
||
6496 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
||
6497 | else |
||
6498 | eldv = G4X_ELDV_DEVCTG; |
||
6499 | |||
6500 | if (intel_eld_uptodate(connector, |
||
6501 | G4X_AUD_CNTL_ST, eldv, |
||
6502 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
||
6503 | G4X_HDMIW_HDMIEDID)) |
||
6504 | return; |
||
6505 | |||
6506 | i = I915_READ(G4X_AUD_CNTL_ST); |
||
6507 | i &= ~(eldv | G4X_ELD_ADDR); |
||
6508 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
||
6509 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
||
6510 | |||
6511 | if (!eld[0]) |
||
6512 | return; |
||
6513 | |||
6514 | len = min_t(uint8_t, eld[2], len); |
||
6515 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
||
6516 | for (i = 0; i < len; i++) |
||
6517 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
||
6518 | |||
6519 | i = I915_READ(G4X_AUD_CNTL_ST); |
||
6520 | i |= eldv; |
||
6521 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
||
6522 | } |
||
6523 | |||
3031 | serge | 6524 | static void haswell_write_eld(struct drm_connector *connector, |
6525 | struct drm_crtc *crtc) |
||
6526 | { |
||
6527 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
6528 | uint8_t *eld = connector->eld; |
||
6529 | struct drm_device *dev = crtc->dev; |
||
3480 | Serge | 6530 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3031 | serge | 6531 | uint32_t eldv; |
6532 | uint32_t i; |
||
6533 | int len; |
||
6534 | int pipe = to_intel_crtc(crtc)->pipe; |
||
6535 | int tmp; |
||
6536 | |||
6537 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
||
6538 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
||
6539 | int aud_config = HSW_AUD_CFG(pipe); |
||
6540 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
||
6541 | |||
6542 | |||
6543 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
||
6544 | |||
6545 | /* Audio output enable */ |
||
6546 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
||
6547 | tmp = I915_READ(aud_cntrl_st2); |
||
6548 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
||
6549 | I915_WRITE(aud_cntrl_st2, tmp); |
||
6550 | |||
6551 | /* Wait for 1 vertical blank */ |
||
6552 | intel_wait_for_vblank(dev, pipe); |
||
6553 | |||
6554 | /* Set ELD valid state */ |
||
6555 | tmp = I915_READ(aud_cntrl_st2); |
||
4104 | Serge | 6556 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
3031 | serge | 6557 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
6558 | I915_WRITE(aud_cntrl_st2, tmp); |
||
6559 | tmp = I915_READ(aud_cntrl_st2); |
||
4104 | Serge | 6560 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
3031 | serge | 6561 | |
6562 | /* Enable HDMI mode */ |
||
6563 | tmp = I915_READ(aud_config); |
||
4104 | Serge | 6564 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
3031 | serge | 6565 | /* clear N_programing_enable and N_value_index */ |
6566 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
||
6567 | I915_WRITE(aud_config, tmp); |
||
6568 | |||
6569 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
||
6570 | |||
6571 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
||
3480 | Serge | 6572 | intel_crtc->eld_vld = true; |
3031 | serge | 6573 | |
6574 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
||
6575 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
||
6576 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
||
6577 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
||
6578 | } else |
||
6579 | I915_WRITE(aud_config, 0); |
||
6580 | |||
6581 | if (intel_eld_uptodate(connector, |
||
6582 | aud_cntrl_st2, eldv, |
||
6583 | aud_cntl_st, IBX_ELD_ADDRESS, |
||
6584 | hdmiw_hdmiedid)) |
||
6585 | return; |
||
6586 | |||
6587 | i = I915_READ(aud_cntrl_st2); |
||
6588 | i &= ~eldv; |
||
6589 | I915_WRITE(aud_cntrl_st2, i); |
||
6590 | |||
6591 | if (!eld[0]) |
||
6592 | return; |
||
6593 | |||
6594 | i = I915_READ(aud_cntl_st); |
||
6595 | i &= ~IBX_ELD_ADDRESS; |
||
6596 | I915_WRITE(aud_cntl_st, i); |
||
6597 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
||
6598 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
||
6599 | |||
6600 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
||
6601 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
||
6602 | for (i = 0; i < len; i++) |
||
6603 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
||
6604 | |||
6605 | i = I915_READ(aud_cntrl_st2); |
||
6606 | i |= eldv; |
||
6607 | I915_WRITE(aud_cntrl_st2, i); |
||
6608 | |||
6609 | } |
||
6610 | |||
2342 | Serge | 6611 | static void ironlake_write_eld(struct drm_connector *connector, |
6612 | struct drm_crtc *crtc) |
||
6613 | { |
||
6614 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
6615 | uint8_t *eld = connector->eld; |
||
6616 | uint32_t eldv; |
||
6617 | uint32_t i; |
||
6618 | int len; |
||
6619 | int hdmiw_hdmiedid; |
||
3031 | serge | 6620 | int aud_config; |
2342 | Serge | 6621 | int aud_cntl_st; |
6622 | int aud_cntrl_st2; |
||
3031 | serge | 6623 | int pipe = to_intel_crtc(crtc)->pipe; |
2342 | Serge | 6624 | |
6625 | if (HAS_PCH_IBX(connector->dev)) { |
||
3031 | serge | 6626 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6627 | aud_config = IBX_AUD_CFG(pipe); |
||
6628 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
||
2342 | Serge | 6629 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
6630 | } else { |
||
3031 | serge | 6631 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6632 | aud_config = CPT_AUD_CFG(pipe); |
||
6633 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
||
2342 | Serge | 6634 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
6635 | } |
||
6636 | |||
3031 | serge | 6637 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
2342 | Serge | 6638 | |
6639 | i = I915_READ(aud_cntl_st); |
||
3031 | serge | 6640 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
2342 | Serge | 6641 | if (!i) { |
6642 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
||
6643 | /* operate blindly on all ports */ |
||
6644 | eldv = IBX_ELD_VALIDB; |
||
6645 | eldv |= IBX_ELD_VALIDB << 4; |
||
6646 | eldv |= IBX_ELD_VALIDB << 8; |
||
6647 | } else { |
||
4104 | Serge | 6648 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
2342 | Serge | 6649 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
6650 | } |
||
6651 | |||
6652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
||
6653 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
||
6654 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
||
3031 | serge | 6655 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6656 | } else |
||
6657 | I915_WRITE(aud_config, 0); |
||
2342 | Serge | 6658 | |
6659 | if (intel_eld_uptodate(connector, |
||
6660 | aud_cntrl_st2, eldv, |
||
6661 | aud_cntl_st, IBX_ELD_ADDRESS, |
||
6662 | hdmiw_hdmiedid)) |
||
6663 | return; |
||
6664 | |||
6665 | i = I915_READ(aud_cntrl_st2); |
||
6666 | i &= ~eldv; |
||
6667 | I915_WRITE(aud_cntrl_st2, i); |
||
6668 | |||
6669 | if (!eld[0]) |
||
6670 | return; |
||
6671 | |||
6672 | i = I915_READ(aud_cntl_st); |
||
6673 | i &= ~IBX_ELD_ADDRESS; |
||
6674 | I915_WRITE(aud_cntl_st, i); |
||
6675 | |||
6676 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
||
6677 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
||
6678 | for (i = 0; i < len; i++) |
||
6679 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
||
6680 | |||
6681 | i = I915_READ(aud_cntrl_st2); |
||
6682 | i |= eldv; |
||
6683 | I915_WRITE(aud_cntrl_st2, i); |
||
6684 | } |
||
6685 | |||
6686 | void intel_write_eld(struct drm_encoder *encoder, |
||
6687 | struct drm_display_mode *mode) |
||
6688 | { |
||
6689 | struct drm_crtc *crtc = encoder->crtc; |
||
6690 | struct drm_connector *connector; |
||
6691 | struct drm_device *dev = encoder->dev; |
||
6692 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6693 | |||
6694 | connector = drm_select_eld(encoder, mode); |
||
6695 | if (!connector) |
||
6696 | return; |
||
6697 | |||
6698 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
||
6699 | connector->base.id, |
||
6700 | drm_get_connector_name(connector), |
||
6701 | connector->encoder->base.id, |
||
6702 | drm_get_encoder_name(connector->encoder)); |
||
6703 | |||
6704 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
||
6705 | |||
6706 | if (dev_priv->display.write_eld) |
||
6707 | dev_priv->display.write_eld(connector, crtc); |
||
6708 | } |
||
6709 | |||
2327 | Serge | 6710 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6711 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
||
6712 | { |
||
6713 | struct drm_device *dev = crtc->dev; |
||
6714 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4104 | Serge | 6716 | enum pipe pipe = intel_crtc->pipe; |
6717 | int palreg = PALETTE(pipe); |
||
2327 | Serge | 6718 | int i; |
4104 | Serge | 6719 | bool reenable_ips = false; |
2327 | Serge | 6720 | |
6721 | /* The clocks have to be on to load the palette. */ |
||
3031 | serge | 6722 | if (!crtc->enabled || !intel_crtc->active) |
2327 | Serge | 6723 | return; |
6724 | |||
4104 | Serge | 6725 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
6726 | assert_pll_enabled(dev_priv, pipe); |
||
6727 | |||
2327 | Serge | 6728 | /* use legacy palette for Ironlake */ |
6729 | if (HAS_PCH_SPLIT(dev)) |
||
4104 | Serge | 6730 | palreg = LGC_PALETTE(pipe); |
2327 | Serge | 6731 | |
4104 | Serge | 6732 | /* Workaround : Do not read or write the pipe palette/gamma data while |
6733 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
||
6734 | */ |
||
6735 | if (intel_crtc->config.ips_enabled && |
||
6736 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
||
6737 | GAMMA_MODE_MODE_SPLIT)) { |
||
6738 | hsw_disable_ips(intel_crtc); |
||
6739 | reenable_ips = true; |
||
6740 | } |
||
6741 | |||
2327 | Serge | 6742 | for (i = 0; i < 256; i++) { |
6743 | I915_WRITE(palreg + 4 * i, |
||
6744 | (intel_crtc->lut_r[i] << 16) | |
||
6745 | (intel_crtc->lut_g[i] << 8) | |
||
6746 | intel_crtc->lut_b[i]); |
||
6747 | } |
||
4104 | Serge | 6748 | |
6749 | if (reenable_ips) |
||
6750 | hsw_enable_ips(intel_crtc); |
||
2327 | Serge | 6751 | } |
6752 | |||
3031 | serge | 6753 | #if 0 |
6754 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
||
6755 | { |
||
6756 | struct drm_device *dev = crtc->dev; |
||
6757 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6758 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6759 | bool visible = base != 0; |
||
6760 | u32 cntl; |
||
2327 | Serge | 6761 | |
3031 | serge | 6762 | if (intel_crtc->cursor_visible == visible) |
6763 | return; |
||
2327 | Serge | 6764 | |
3031 | serge | 6765 | cntl = I915_READ(_CURACNTR); |
6766 | if (visible) { |
||
6767 | /* On these chipsets we can only modify the base whilst |
||
6768 | * the cursor is disabled. |
||
6769 | */ |
||
6770 | I915_WRITE(_CURABASE, base); |
||
2327 | Serge | 6771 | |
3031 | serge | 6772 | cntl &= ~(CURSOR_FORMAT_MASK); |
6773 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
||
6774 | cntl |= CURSOR_ENABLE | |
||
6775 | CURSOR_GAMMA_ENABLE | |
||
6776 | CURSOR_FORMAT_ARGB; |
||
6777 | } else |
||
6778 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
||
6779 | I915_WRITE(_CURACNTR, cntl); |
||
2327 | Serge | 6780 | |
3031 | serge | 6781 | intel_crtc->cursor_visible = visible; |
6782 | } |
||
2327 | Serge | 6783 | |
3031 | serge | 6784 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
6785 | { |
||
6786 | struct drm_device *dev = crtc->dev; |
||
6787 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6789 | int pipe = intel_crtc->pipe; |
||
6790 | bool visible = base != 0; |
||
2327 | Serge | 6791 | |
3031 | serge | 6792 | if (intel_crtc->cursor_visible != visible) { |
6793 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
||
6794 | if (base) { |
||
6795 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
||
6796 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
||
6797 | cntl |= pipe << 28; /* Connect to correct pipe */ |
||
6798 | } else { |
||
6799 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
||
6800 | cntl |= CURSOR_MODE_DISABLE; |
||
6801 | } |
||
6802 | I915_WRITE(CURCNTR(pipe), cntl); |
||
2327 | Serge | 6803 | |
3031 | serge | 6804 | intel_crtc->cursor_visible = visible; |
6805 | } |
||
6806 | /* and commit changes on next vblank */ |
||
4371 | Serge | 6807 | POSTING_READ(CURCNTR(pipe)); |
3031 | serge | 6808 | I915_WRITE(CURBASE(pipe), base); |
4371 | Serge | 6809 | POSTING_READ(CURBASE(pipe)); |
3031 | serge | 6810 | } |
2327 | Serge | 6811 | |
3031 | serge | 6812 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6813 | { |
||
6814 | struct drm_device *dev = crtc->dev; |
||
6815 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6816 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6817 | int pipe = intel_crtc->pipe; |
||
6818 | bool visible = base != 0; |
||
2327 | Serge | 6819 | |
3031 | serge | 6820 | if (intel_crtc->cursor_visible != visible) { |
6821 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
||
6822 | if (base) { |
||
6823 | cntl &= ~CURSOR_MODE; |
||
6824 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
||
6825 | } else { |
||
6826 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
||
6827 | cntl |= CURSOR_MODE_DISABLE; |
||
6828 | } |
||
4104 | Serge | 6829 | if (IS_HASWELL(dev)) { |
3480 | Serge | 6830 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
4104 | Serge | 6831 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
6832 | } |
||
3031 | serge | 6833 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
2327 | Serge | 6834 | |
3031 | serge | 6835 | intel_crtc->cursor_visible = visible; |
6836 | } |
||
6837 | /* and commit changes on next vblank */ |
||
4371 | Serge | 6838 | POSTING_READ(CURCNTR_IVB(pipe)); |
3031 | serge | 6839 | I915_WRITE(CURBASE_IVB(pipe), base); |
4371 | Serge | 6840 | POSTING_READ(CURBASE_IVB(pipe)); |
3031 | serge | 6841 | } |
2327 | Serge | 6842 | |
3031 | serge | 6843 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6844 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
||
6845 | bool on) |
||
6846 | { |
||
6847 | struct drm_device *dev = crtc->dev; |
||
6848 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6850 | int pipe = intel_crtc->pipe; |
||
6851 | int x = intel_crtc->cursor_x; |
||
6852 | int y = intel_crtc->cursor_y; |
||
6853 | u32 base, pos; |
||
6854 | bool visible; |
||
2327 | Serge | 6855 | |
3031 | serge | 6856 | pos = 0; |
2327 | Serge | 6857 | |
3031 | serge | 6858 | if (on && crtc->enabled && crtc->fb) { |
6859 | base = intel_crtc->cursor_addr; |
||
6860 | if (x > (int) crtc->fb->width) |
||
6861 | base = 0; |
||
2327 | Serge | 6862 | |
3031 | serge | 6863 | if (y > (int) crtc->fb->height) |
6864 | base = 0; |
||
6865 | } else |
||
6866 | base = 0; |
||
2327 | Serge | 6867 | |
3031 | serge | 6868 | if (x < 0) { |
6869 | if (x + intel_crtc->cursor_width < 0) |
||
6870 | base = 0; |
||
2327 | Serge | 6871 | |
3031 | serge | 6872 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
6873 | x = -x; |
||
6874 | } |
||
6875 | pos |= x << CURSOR_X_SHIFT; |
||
2327 | Serge | 6876 | |
3031 | serge | 6877 | if (y < 0) { |
6878 | if (y + intel_crtc->cursor_height < 0) |
||
6879 | base = 0; |
||
2327 | Serge | 6880 | |
3031 | serge | 6881 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
6882 | y = -y; |
||
6883 | } |
||
6884 | pos |= y << CURSOR_Y_SHIFT; |
||
2327 | Serge | 6885 | |
3031 | serge | 6886 | visible = base != 0; |
6887 | if (!visible && !intel_crtc->cursor_visible) |
||
6888 | return; |
||
2327 | Serge | 6889 | |
3031 | serge | 6890 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
6891 | I915_WRITE(CURPOS_IVB(pipe), pos); |
||
6892 | ivb_update_cursor(crtc, base); |
||
6893 | } else { |
||
6894 | I915_WRITE(CURPOS(pipe), pos); |
||
6895 | if (IS_845G(dev) || IS_I865G(dev)) |
||
6896 | i845_update_cursor(crtc, base); |
||
6897 | else |
||
6898 | i9xx_update_cursor(crtc, base); |
||
6899 | } |
||
6900 | } |
||
2327 | Serge | 6901 | |
3031 | serge | 6902 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
6903 | struct drm_file *file, |
||
6904 | uint32_t handle, |
||
6905 | uint32_t width, uint32_t height) |
||
6906 | { |
||
6907 | struct drm_device *dev = crtc->dev; |
||
6908 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6909 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6910 | struct drm_i915_gem_object *obj; |
||
6911 | uint32_t addr; |
||
6912 | int ret; |
||
2327 | Serge | 6913 | |
3031 | serge | 6914 | /* if we want to turn off the cursor ignore width and height */ |
6915 | if (!handle) { |
||
6916 | DRM_DEBUG_KMS("cursor off\n"); |
||
6917 | addr = 0; |
||
6918 | obj = NULL; |
||
6919 | mutex_lock(&dev->struct_mutex); |
||
6920 | goto finish; |
||
6921 | } |
||
2327 | Serge | 6922 | |
3031 | serge | 6923 | /* Currently we only support 64x64 cursors */ |
6924 | if (width != 64 || height != 64) { |
||
6925 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
||
6926 | return -EINVAL; |
||
6927 | } |
||
2327 | Serge | 6928 | |
3031 | serge | 6929 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
6930 | if (&obj->base == NULL) |
||
6931 | return -ENOENT; |
||
2327 | Serge | 6932 | |
3031 | serge | 6933 | if (obj->base.size < width * height * 4) { |
6934 | DRM_ERROR("buffer is to small\n"); |
||
6935 | ret = -ENOMEM; |
||
6936 | goto fail; |
||
6937 | } |
||
2327 | Serge | 6938 | |
3031 | serge | 6939 | /* we only need to pin inside GTT if cursor is non-phy */ |
6940 | mutex_lock(&dev->struct_mutex); |
||
6941 | if (!dev_priv->info->cursor_needs_physical) { |
||
3746 | Serge | 6942 | unsigned alignment; |
6943 | |||
3031 | serge | 6944 | if (obj->tiling_mode) { |
6945 | DRM_ERROR("cursor cannot be tiled\n"); |
||
6946 | ret = -EINVAL; |
||
6947 | goto fail_locked; |
||
6948 | } |
||
2327 | Serge | 6949 | |
3746 | Serge | 6950 | /* Note that the w/a also requires 2 PTE of padding following |
6951 | * the bo. We currently fill all unused PTE with the shadow |
||
6952 | * page and so we should always have valid PTE following the |
||
6953 | * cursor preventing the VT-d warning. |
||
6954 | */ |
||
6955 | alignment = 0; |
||
6956 | if (need_vtd_wa(dev)) |
||
6957 | alignment = 64*1024; |
||
6958 | |||
6959 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
||
3031 | serge | 6960 | if (ret) { |
6961 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
||
6962 | goto fail_locked; |
||
6963 | } |
||
2327 | Serge | 6964 | |
3031 | serge | 6965 | ret = i915_gem_object_put_fence(obj); |
6966 | if (ret) { |
||
6967 | DRM_ERROR("failed to release fence for cursor"); |
||
6968 | goto fail_unpin; |
||
6969 | } |
||
2327 | Serge | 6970 | |
4104 | Serge | 6971 | addr = i915_gem_obj_ggtt_offset(obj); |
3031 | serge | 6972 | } else { |
6973 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
||
6974 | ret = i915_gem_attach_phys_object(dev, obj, |
||
6975 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
||
6976 | align); |
||
6977 | if (ret) { |
||
6978 | DRM_ERROR("failed to attach phys object\n"); |
||
6979 | goto fail_locked; |
||
6980 | } |
||
6981 | addr = obj->phys_obj->handle->busaddr; |
||
6982 | } |
||
2327 | Serge | 6983 | |
3031 | serge | 6984 | if (IS_GEN2(dev)) |
6985 | I915_WRITE(CURSIZE, (height << 12) | width); |
||
2327 | Serge | 6986 | |
3031 | serge | 6987 | finish: |
6988 | if (intel_crtc->cursor_bo) { |
||
6989 | if (dev_priv->info->cursor_needs_physical) { |
||
6990 | if (intel_crtc->cursor_bo != obj) |
||
6991 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
||
6992 | } else |
||
4104 | Serge | 6993 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3031 | serge | 6994 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
6995 | } |
||
2327 | Serge | 6996 | |
3031 | serge | 6997 | mutex_unlock(&dev->struct_mutex); |
2327 | Serge | 6998 | |
3031 | serge | 6999 | intel_crtc->cursor_addr = addr; |
7000 | intel_crtc->cursor_bo = obj; |
||
7001 | intel_crtc->cursor_width = width; |
||
7002 | intel_crtc->cursor_height = height; |
||
2327 | Serge | 7003 | |
4104 | Serge | 7004 | if (intel_crtc->active) |
7005 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
||
2327 | Serge | 7006 | |
3031 | serge | 7007 | return 0; |
7008 | fail_unpin: |
||
4104 | Serge | 7009 | i915_gem_object_unpin_from_display_plane(obj); |
3031 | serge | 7010 | fail_locked: |
7011 | mutex_unlock(&dev->struct_mutex); |
||
7012 | fail: |
||
7013 | drm_gem_object_unreference_unlocked(&obj->base); |
||
7014 | return ret; |
||
7015 | } |
||
2327 | Serge | 7016 | |
3031 | serge | 7017 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
7018 | { |
||
7019 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
7020 | |||
7021 | intel_crtc->cursor_x = x; |
||
7022 | intel_crtc->cursor_y = y; |
||
7023 | |||
4104 | Serge | 7024 | if (intel_crtc->active) |
7025 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
||
3031 | serge | 7026 | |
7027 | return 0; |
||
7028 | } |
||
7029 | #endif |
||
7030 | |||
2332 | Serge | 7031 | /** Sets the color ramps on behalf of RandR */ |
7032 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
||
7033 | u16 blue, int regno) |
||
7034 | { |
||
7035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2327 | Serge | 7036 | |
2332 | Serge | 7037 | intel_crtc->lut_r[regno] = red >> 8; |
7038 | intel_crtc->lut_g[regno] = green >> 8; |
||
7039 | intel_crtc->lut_b[regno] = blue >> 8; |
||
7040 | } |
||
2327 | Serge | 7041 | |
2332 | Serge | 7042 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
7043 | u16 *blue, int regno) |
||
7044 | { |
||
7045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2327 | Serge | 7046 | |
2332 | Serge | 7047 | *red = intel_crtc->lut_r[regno] << 8; |
7048 | *green = intel_crtc->lut_g[regno] << 8; |
||
7049 | *blue = intel_crtc->lut_b[regno] << 8; |
||
7050 | } |
||
2327 | Serge | 7051 | |
2330 | Serge | 7052 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7053 | u16 *blue, uint32_t start, uint32_t size) |
||
7054 | { |
||
7055 | int end = (start + size > 256) ? 256 : start + size, i; |
||
7056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2327 | Serge | 7057 | |
2330 | Serge | 7058 | for (i = start; i < end; i++) { |
7059 | intel_crtc->lut_r[i] = red[i] >> 8; |
||
7060 | intel_crtc->lut_g[i] = green[i] >> 8; |
||
7061 | intel_crtc->lut_b[i] = blue[i] >> 8; |
||
7062 | } |
||
2327 | Serge | 7063 | |
2330 | Serge | 7064 | intel_crtc_load_lut(crtc); |
7065 | } |
||
2327 | Serge | 7066 | |
2330 | Serge | 7067 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7068 | static struct drm_display_mode load_detect_mode = { |
||
7069 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
||
7070 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
||
7071 | }; |
||
2327 | Serge | 7072 | |
3031 | serge | 7073 | static struct drm_framebuffer * |
7074 | intel_framebuffer_create(struct drm_device *dev, |
||
7075 | struct drm_mode_fb_cmd2 *mode_cmd, |
||
7076 | struct drm_i915_gem_object *obj) |
||
7077 | { |
||
7078 | struct intel_framebuffer *intel_fb; |
||
7079 | int ret; |
||
2327 | Serge | 7080 | |
3031 | serge | 7081 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
7082 | if (!intel_fb) { |
||
7083 | drm_gem_object_unreference_unlocked(&obj->base); |
||
7084 | return ERR_PTR(-ENOMEM); |
||
7085 | } |
||
2327 | Serge | 7086 | |
3031 | serge | 7087 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7088 | if (ret) { |
||
7089 | drm_gem_object_unreference_unlocked(&obj->base); |
||
7090 | kfree(intel_fb); |
||
7091 | return ERR_PTR(ret); |
||
7092 | } |
||
2327 | Serge | 7093 | |
3031 | serge | 7094 | return &intel_fb->base; |
7095 | } |
||
2327 | Serge | 7096 | |
2330 | Serge | 7097 | static u32 |
7098 | intel_framebuffer_pitch_for_width(int width, int bpp) |
||
7099 | { |
||
7100 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
||
7101 | return ALIGN(pitch, 64); |
||
7102 | } |
||
2327 | Serge | 7103 | |
2330 | Serge | 7104 | static u32 |
7105 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
||
7106 | { |
||
7107 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
||
7108 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
||
7109 | } |
||
2327 | Serge | 7110 | |
2330 | Serge | 7111 | static struct drm_framebuffer * |
7112 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
||
7113 | struct drm_display_mode *mode, |
||
7114 | int depth, int bpp) |
||
7115 | { |
||
7116 | struct drm_i915_gem_object *obj; |
||
3243 | Serge | 7117 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
2327 | Serge | 7118 | |
4104 | Serge | 7119 | return NULL; |
2330 | Serge | 7120 | } |
2327 | Serge | 7121 | |
2330 | Serge | 7122 | static struct drm_framebuffer * |
7123 | mode_fits_in_fbdev(struct drm_device *dev, |
||
7124 | struct drm_display_mode *mode) |
||
7125 | { |
||
7126 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7127 | struct drm_i915_gem_object *obj; |
||
7128 | struct drm_framebuffer *fb; |
||
2327 | Serge | 7129 | |
4280 | Serge | 7130 | if (dev_priv->fbdev == NULL) |
7131 | return NULL; |
||
2327 | Serge | 7132 | |
4280 | Serge | 7133 | obj = dev_priv->fbdev->ifb.obj; |
7134 | if (obj == NULL) |
||
2330 | Serge | 7135 | return NULL; |
2327 | Serge | 7136 | |
4280 | Serge | 7137 | fb = &dev_priv->fbdev->ifb.base; |
3031 | serge | 7138 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7139 | fb->bits_per_pixel)) |
||
4280 | Serge | 7140 | return NULL; |
2327 | Serge | 7141 | |
3031 | serge | 7142 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7143 | return NULL; |
||
7144 | |||
4280 | Serge | 7145 | return fb; |
2330 | Serge | 7146 | } |
2327 | Serge | 7147 | |
3031 | serge | 7148 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
2330 | Serge | 7149 | struct drm_display_mode *mode, |
7150 | struct intel_load_detect_pipe *old) |
||
7151 | { |
||
7152 | struct intel_crtc *intel_crtc; |
||
3031 | serge | 7153 | struct intel_encoder *intel_encoder = |
7154 | intel_attached_encoder(connector); |
||
2330 | Serge | 7155 | struct drm_crtc *possible_crtc; |
7156 | struct drm_encoder *encoder = &intel_encoder->base; |
||
7157 | struct drm_crtc *crtc = NULL; |
||
7158 | struct drm_device *dev = encoder->dev; |
||
3031 | serge | 7159 | struct drm_framebuffer *fb; |
2330 | Serge | 7160 | int i = -1; |
2327 | Serge | 7161 | |
2330 | Serge | 7162 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7163 | connector->base.id, drm_get_connector_name(connector), |
||
7164 | encoder->base.id, drm_get_encoder_name(encoder)); |
||
2327 | Serge | 7165 | |
2330 | Serge | 7166 | /* |
7167 | * Algorithm gets a little messy: |
||
7168 | * |
||
7169 | * - if the connector already has an assigned crtc, use it (but make |
||
7170 | * sure it's on first) |
||
7171 | * |
||
7172 | * - try to find the first unused crtc that can drive this connector, |
||
7173 | * and use that if we find one |
||
7174 | */ |
||
2327 | Serge | 7175 | |
2330 | Serge | 7176 | /* See if we already have a CRTC for this connector */ |
7177 | if (encoder->crtc) { |
||
7178 | crtc = encoder->crtc; |
||
2327 | Serge | 7179 | |
3480 | Serge | 7180 | mutex_lock(&crtc->mutex); |
7181 | |||
3031 | serge | 7182 | old->dpms_mode = connector->dpms; |
2330 | Serge | 7183 | old->load_detect_temp = false; |
2327 | Serge | 7184 | |
2330 | Serge | 7185 | /* Make sure the crtc and connector are running */ |
3031 | serge | 7186 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7187 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
||
2327 | Serge | 7188 | |
2330 | Serge | 7189 | return true; |
7190 | } |
||
2327 | Serge | 7191 | |
2330 | Serge | 7192 | /* Find an unused one (if possible) */ |
7193 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
||
7194 | i++; |
||
7195 | if (!(encoder->possible_crtcs & (1 << i))) |
||
7196 | continue; |
||
7197 | if (!possible_crtc->enabled) { |
||
7198 | crtc = possible_crtc; |
||
7199 | break; |
||
7200 | } |
||
7201 | } |
||
2327 | Serge | 7202 | |
2330 | Serge | 7203 | /* |
7204 | * If we didn't find an unused CRTC, don't use any. |
||
7205 | */ |
||
7206 | if (!crtc) { |
||
7207 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
||
7208 | return false; |
||
7209 | } |
||
2327 | Serge | 7210 | |
3480 | Serge | 7211 | mutex_lock(&crtc->mutex); |
3031 | serge | 7212 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7213 | to_intel_connector(connector)->new_encoder = intel_encoder; |
||
2327 | Serge | 7214 | |
2330 | Serge | 7215 | intel_crtc = to_intel_crtc(crtc); |
3031 | serge | 7216 | old->dpms_mode = connector->dpms; |
2330 | Serge | 7217 | old->load_detect_temp = true; |
7218 | old->release_fb = NULL; |
||
2327 | Serge | 7219 | |
2330 | Serge | 7220 | if (!mode) |
7221 | mode = &load_detect_mode; |
||
2327 | Serge | 7222 | |
2330 | Serge | 7223 | /* We need a framebuffer large enough to accommodate all accesses |
7224 | * that the plane may generate whilst we perform load detection. |
||
7225 | * We can not rely on the fbcon either being present (we get called |
||
7226 | * during its initialisation to detect all boot displays, or it may |
||
7227 | * not even exist) or that it is large enough to satisfy the |
||
7228 | * requested mode. |
||
7229 | */ |
||
3031 | serge | 7230 | fb = mode_fits_in_fbdev(dev, mode); |
7231 | if (fb == NULL) { |
||
2330 | Serge | 7232 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
3031 | serge | 7233 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7234 | old->release_fb = fb; |
||
2330 | Serge | 7235 | } else |
7236 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
||
3031 | serge | 7237 | if (IS_ERR(fb)) { |
2330 | Serge | 7238 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
3480 | Serge | 7239 | mutex_unlock(&crtc->mutex); |
3243 | Serge | 7240 | return false; |
2330 | Serge | 7241 | } |
2327 | Serge | 7242 | |
3480 | Serge | 7243 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
2330 | Serge | 7244 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
7245 | if (old->release_fb) |
||
7246 | old->release_fb->funcs->destroy(old->release_fb); |
||
3480 | Serge | 7247 | mutex_unlock(&crtc->mutex); |
3243 | Serge | 7248 | return false; |
2330 | Serge | 7249 | } |
2327 | Serge | 7250 | |
2330 | Serge | 7251 | /* let the connector get through one full cycle before testing */ |
7252 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
7253 | return true; |
||
7254 | } |
||
2327 | Serge | 7255 | |
3031 | serge | 7256 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
2330 | Serge | 7257 | struct intel_load_detect_pipe *old) |
7258 | { |
||
3031 | serge | 7259 | struct intel_encoder *intel_encoder = |
7260 | intel_attached_encoder(connector); |
||
2330 | Serge | 7261 | struct drm_encoder *encoder = &intel_encoder->base; |
3480 | Serge | 7262 | struct drm_crtc *crtc = encoder->crtc; |
2327 | Serge | 7263 | |
2330 | Serge | 7264 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7265 | connector->base.id, drm_get_connector_name(connector), |
||
7266 | encoder->base.id, drm_get_encoder_name(encoder)); |
||
2327 | Serge | 7267 | |
2330 | Serge | 7268 | if (old->load_detect_temp) { |
3031 | serge | 7269 | to_intel_connector(connector)->new_encoder = NULL; |
7270 | intel_encoder->new_crtc = NULL; |
||
7271 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
||
7272 | |||
3480 | Serge | 7273 | if (old->release_fb) { |
7274 | drm_framebuffer_unregister_private(old->release_fb); |
||
7275 | drm_framebuffer_unreference(old->release_fb); |
||
7276 | } |
||
2327 | Serge | 7277 | |
3480 | Serge | 7278 | mutex_unlock(&crtc->mutex); |
2330 | Serge | 7279 | return; |
7280 | } |
||
2327 | Serge | 7281 | |
2330 | Serge | 7282 | /* Switch crtc and encoder back off if necessary */ |
3031 | serge | 7283 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7284 | connector->funcs->dpms(connector, old->dpms_mode); |
||
3480 | Serge | 7285 | |
7286 | mutex_unlock(&crtc->mutex); |
||
2330 | Serge | 7287 | } |
2327 | Serge | 7288 | |
2330 | Serge | 7289 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
4104 | Serge | 7290 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7291 | struct intel_crtc_config *pipe_config) |
||
2330 | Serge | 7292 | { |
4104 | Serge | 7293 | struct drm_device *dev = crtc->base.dev; |
2330 | Serge | 7294 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 7295 | int pipe = pipe_config->cpu_transcoder; |
2330 | Serge | 7296 | u32 dpll = I915_READ(DPLL(pipe)); |
7297 | u32 fp; |
||
7298 | intel_clock_t clock; |
||
2327 | Serge | 7299 | |
2330 | Serge | 7300 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
7301 | fp = I915_READ(FP0(pipe)); |
||
7302 | else |
||
7303 | fp = I915_READ(FP1(pipe)); |
||
2327 | Serge | 7304 | |
2330 | Serge | 7305 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
7306 | if (IS_PINEVIEW(dev)) { |
||
7307 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
||
7308 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
||
7309 | } else { |
||
7310 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
||
7311 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
||
7312 | } |
||
2327 | Serge | 7313 | |
2330 | Serge | 7314 | if (!IS_GEN2(dev)) { |
7315 | if (IS_PINEVIEW(dev)) |
||
7316 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
||
7317 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
||
7318 | else |
||
7319 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
||
7320 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
||
2327 | Serge | 7321 | |
2330 | Serge | 7322 | switch (dpll & DPLL_MODE_MASK) { |
7323 | case DPLLB_MODE_DAC_SERIAL: |
||
7324 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
||
7325 | 5 : 10; |
||
7326 | break; |
||
7327 | case DPLLB_MODE_LVDS: |
||
7328 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
||
7329 | 7 : 14; |
||
7330 | break; |
||
7331 | default: |
||
7332 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
||
7333 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
||
4104 | Serge | 7334 | pipe_config->adjusted_mode.clock = 0; |
7335 | return; |
||
2330 | Serge | 7336 | } |
2327 | Serge | 7337 | |
4104 | Serge | 7338 | if (IS_PINEVIEW(dev)) |
7339 | pineview_clock(96000, &clock); |
||
7340 | else |
||
7341 | i9xx_clock(96000, &clock); |
||
2330 | Serge | 7342 | } else { |
7343 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
||
2327 | Serge | 7344 | |
2330 | Serge | 7345 | if (is_lvds) { |
7346 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
||
7347 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
||
7348 | clock.p2 = 14; |
||
2327 | Serge | 7349 | |
2330 | Serge | 7350 | if ((dpll & PLL_REF_INPUT_MASK) == |
7351 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
||
7352 | /* XXX: might not be 66MHz */ |
||
4104 | Serge | 7353 | i9xx_clock(66000, &clock); |
2330 | Serge | 7354 | } else |
4104 | Serge | 7355 | i9xx_clock(48000, &clock); |
2330 | Serge | 7356 | } else { |
7357 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
||
7358 | clock.p1 = 2; |
||
7359 | else { |
||
7360 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
||
7361 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
||
7362 | } |
||
7363 | if (dpll & PLL_P2_DIVIDE_BY_4) |
||
7364 | clock.p2 = 4; |
||
7365 | else |
||
7366 | clock.p2 = 2; |
||
2327 | Serge | 7367 | |
4104 | Serge | 7368 | i9xx_clock(48000, &clock); |
2330 | Serge | 7369 | } |
7370 | } |
||
2327 | Serge | 7371 | |
4104 | Serge | 7372 | pipe_config->adjusted_mode.clock = clock.dot; |
7373 | } |
||
7374 | |||
7375 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
||
7376 | struct intel_crtc_config *pipe_config) |
||
7377 | { |
||
7378 | struct drm_device *dev = crtc->base.dev; |
||
7379 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7380 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
||
7381 | int link_freq, repeat; |
||
7382 | u64 clock; |
||
7383 | u32 link_m, link_n; |
||
7384 | |||
7385 | repeat = pipe_config->pixel_multiplier; |
||
7386 | |||
7387 | /* |
||
7388 | * The calculation for the data clock is: |
||
7389 | * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp |
||
7390 | * But we want to avoid losing precison if possible, so: |
||
7391 | * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp)) |
||
7392 | * |
||
7393 | * and the link clock is simpler: |
||
7394 | * link_clock = (m * link_clock * repeat) / n |
||
2330 | Serge | 7395 | */ |
2327 | Serge | 7396 | |
4104 | Serge | 7397 | /* |
7398 | * We need to get the FDI or DP link clock here to derive |
||
7399 | * the M/N dividers. |
||
7400 | * |
||
7401 | * For FDI, we read it from the BIOS or use a fixed 2.7GHz. |
||
7402 | * For DP, it's either 1.62GHz or 2.7GHz. |
||
7403 | * We do our calculations in 10*MHz since we don't need much precison. |
||
7404 | */ |
||
7405 | if (pipe_config->has_pch_encoder) |
||
7406 | link_freq = intel_fdi_link_freq(dev) * 10000; |
||
7407 | else |
||
7408 | link_freq = pipe_config->port_clock; |
||
7409 | |||
7410 | link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder)); |
||
7411 | link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder)); |
||
7412 | |||
7413 | if (!link_m || !link_n) |
||
7414 | return; |
||
7415 | |||
7416 | clock = ((u64)link_m * (u64)link_freq * (u64)repeat); |
||
7417 | do_div(clock, link_n); |
||
7418 | |||
7419 | pipe_config->adjusted_mode.clock = clock; |
||
2330 | Serge | 7420 | } |
2327 | Serge | 7421 | |
2330 | Serge | 7422 | /** Returns the currently programmed mode of the given pipe. */ |
7423 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
||
7424 | struct drm_crtc *crtc) |
||
7425 | { |
||
7426 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7427 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3746 | Serge | 7428 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
2330 | Serge | 7429 | struct drm_display_mode *mode; |
4104 | Serge | 7430 | struct intel_crtc_config pipe_config; |
3243 | Serge | 7431 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7432 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
||
7433 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
||
7434 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
||
2327 | Serge | 7435 | |
2330 | Serge | 7436 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
7437 | if (!mode) |
||
7438 | return NULL; |
||
7439 | |||
4104 | Serge | 7440 | /* |
7441 | * Construct a pipe_config sufficient for getting the clock info |
||
7442 | * back out of crtc_clock_get. |
||
7443 | * |
||
7444 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
||
7445 | * to use a real value here instead. |
||
7446 | */ |
||
7447 | pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
||
7448 | pipe_config.pixel_multiplier = 1; |
||
7449 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
||
7450 | |||
7451 | mode->clock = pipe_config.adjusted_mode.clock; |
||
2330 | Serge | 7452 | mode->hdisplay = (htot & 0xffff) + 1; |
7453 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
||
7454 | mode->hsync_start = (hsync & 0xffff) + 1; |
||
7455 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
||
7456 | mode->vdisplay = (vtot & 0xffff) + 1; |
||
7457 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
||
7458 | mode->vsync_start = (vsync & 0xffff) + 1; |
||
7459 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
||
7460 | |||
7461 | drm_mode_set_name(mode); |
||
7462 | |||
7463 | return mode; |
||
7464 | } |
||
7465 | |||
2327 | Serge | 7466 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
7467 | { |
||
7468 | struct drm_device *dev = crtc->dev; |
||
7469 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7470 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
7471 | int pipe = intel_crtc->pipe; |
||
7472 | int dpll_reg = DPLL(pipe); |
||
7473 | int dpll; |
||
7474 | |||
7475 | if (HAS_PCH_SPLIT(dev)) |
||
7476 | return; |
||
7477 | |||
7478 | if (!dev_priv->lvds_downclock_avail) |
||
7479 | return; |
||
7480 | |||
7481 | dpll = I915_READ(dpll_reg); |
||
7482 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
||
7483 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
||
7484 | |||
3031 | serge | 7485 | assert_panel_unlocked(dev_priv, pipe); |
2327 | Serge | 7486 | |
7487 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
||
7488 | I915_WRITE(dpll_reg, dpll); |
||
7489 | intel_wait_for_vblank(dev, pipe); |
||
7490 | |||
7491 | dpll = I915_READ(dpll_reg); |
||
7492 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
||
7493 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
||
7494 | } |
||
7495 | } |
||
7496 | |||
3031 | serge | 7497 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
7498 | { |
||
7499 | struct drm_device *dev = crtc->dev; |
||
7500 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7501 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2327 | Serge | 7502 | |
3031 | serge | 7503 | if (HAS_PCH_SPLIT(dev)) |
7504 | return; |
||
2327 | Serge | 7505 | |
3031 | serge | 7506 | if (!dev_priv->lvds_downclock_avail) |
7507 | return; |
||
2327 | Serge | 7508 | |
3031 | serge | 7509 | /* |
7510 | * Since this is called by a timer, we should never get here in |
||
7511 | * the manual case. |
||
7512 | */ |
||
7513 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
||
7514 | int pipe = intel_crtc->pipe; |
||
7515 | int dpll_reg = DPLL(pipe); |
||
7516 | int dpll; |
||
2327 | Serge | 7517 | |
3031 | serge | 7518 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
2327 | Serge | 7519 | |
3031 | serge | 7520 | assert_panel_unlocked(dev_priv, pipe); |
2327 | Serge | 7521 | |
3031 | serge | 7522 | dpll = I915_READ(dpll_reg); |
7523 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
||
7524 | I915_WRITE(dpll_reg, dpll); |
||
7525 | intel_wait_for_vblank(dev, pipe); |
||
7526 | dpll = I915_READ(dpll_reg); |
||
7527 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
||
7528 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
||
7529 | } |
||
2327 | Serge | 7530 | |
3031 | serge | 7531 | } |
2327 | Serge | 7532 | |
3031 | serge | 7533 | void intel_mark_busy(struct drm_device *dev) |
7534 | { |
||
4104 | Serge | 7535 | struct drm_i915_private *dev_priv = dev->dev_private; |
7536 | |||
7537 | hsw_package_c8_gpu_busy(dev_priv); |
||
7538 | i915_update_gfx_val(dev_priv); |
||
3031 | serge | 7539 | } |
2327 | Serge | 7540 | |
3031 | serge | 7541 | void intel_mark_idle(struct drm_device *dev) |
7542 | { |
||
4104 | Serge | 7543 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 7544 | struct drm_crtc *crtc; |
2327 | Serge | 7545 | |
4104 | Serge | 7546 | hsw_package_c8_gpu_idle(dev_priv); |
7547 | |||
3031 | serge | 7548 | if (!i915_powersave) |
7549 | return; |
||
2327 | Serge | 7550 | |
3031 | serge | 7551 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7552 | if (!crtc->fb) |
||
7553 | continue; |
||
2327 | Serge | 7554 | |
3480 | Serge | 7555 | intel_decrease_pllclock(crtc); |
3031 | serge | 7556 | } |
7557 | } |
||
2327 | Serge | 7558 | |
4104 | Serge | 7559 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
7560 | struct intel_ring_buffer *ring) |
||
3031 | serge | 7561 | { |
7562 | struct drm_device *dev = obj->base.dev; |
||
7563 | struct drm_crtc *crtc; |
||
2327 | Serge | 7564 | |
3031 | serge | 7565 | if (!i915_powersave) |
7566 | return; |
||
2327 | Serge | 7567 | |
3031 | serge | 7568 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7569 | if (!crtc->fb) |
||
7570 | continue; |
||
2327 | Serge | 7571 | |
4104 | Serge | 7572 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
7573 | continue; |
||
7574 | |||
3480 | Serge | 7575 | intel_increase_pllclock(crtc); |
4104 | Serge | 7576 | if (ring && intel_fbc_enabled(dev)) |
7577 | ring->fbc_dirty = true; |
||
3031 | serge | 7578 | } |
7579 | } |
||
2327 | Serge | 7580 | |
2330 | Serge | 7581 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7582 | { |
||
7583 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
7584 | struct drm_device *dev = crtc->dev; |
||
7585 | struct intel_unpin_work *work; |
||
7586 | unsigned long flags; |
||
2327 | Serge | 7587 | |
2330 | Serge | 7588 | spin_lock_irqsave(&dev->event_lock, flags); |
7589 | work = intel_crtc->unpin_work; |
||
7590 | intel_crtc->unpin_work = NULL; |
||
7591 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
2327 | Serge | 7592 | |
2330 | Serge | 7593 | if (work) { |
4293 | Serge | 7594 | cancel_work_sync(&work->work); |
2330 | Serge | 7595 | kfree(work); |
7596 | } |
||
2327 | Serge | 7597 | |
2330 | Serge | 7598 | drm_crtc_cleanup(crtc); |
2327 | Serge | 7599 | |
2330 | Serge | 7600 | kfree(intel_crtc); |
7601 | } |
||
2327 | Serge | 7602 | |
3031 | serge | 7603 | #if 0 |
7604 | static void intel_unpin_work_fn(struct work_struct *__work) |
||
7605 | { |
||
7606 | struct intel_unpin_work *work = |
||
7607 | container_of(__work, struct intel_unpin_work, work); |
||
3243 | Serge | 7608 | struct drm_device *dev = work->crtc->dev; |
2327 | Serge | 7609 | |
3243 | Serge | 7610 | mutex_lock(&dev->struct_mutex); |
3031 | serge | 7611 | intel_unpin_fb_obj(work->old_fb_obj); |
7612 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
||
7613 | drm_gem_object_unreference(&work->old_fb_obj->base); |
||
2327 | Serge | 7614 | |
3243 | Serge | 7615 | intel_update_fbc(dev); |
7616 | mutex_unlock(&dev->struct_mutex); |
||
7617 | |||
7618 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
||
7619 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
||
7620 | |||
3031 | serge | 7621 | kfree(work); |
7622 | } |
||
2327 | Serge | 7623 | |
3031 | serge | 7624 | static void do_intel_finish_page_flip(struct drm_device *dev, |
7625 | struct drm_crtc *crtc) |
||
7626 | { |
||
7627 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
7629 | struct intel_unpin_work *work; |
||
7630 | unsigned long flags; |
||
2327 | Serge | 7631 | |
3031 | serge | 7632 | /* Ignore early vblank irqs */ |
7633 | if (intel_crtc == NULL) |
||
7634 | return; |
||
2327 | Serge | 7635 | |
3031 | serge | 7636 | spin_lock_irqsave(&dev->event_lock, flags); |
7637 | work = intel_crtc->unpin_work; |
||
3243 | Serge | 7638 | |
7639 | /* Ensure we don't miss a work->pending update ... */ |
||
7640 | smp_rmb(); |
||
7641 | |||
7642 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
||
3031 | serge | 7643 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7644 | return; |
||
7645 | } |
||
2327 | Serge | 7646 | |
3243 | Serge | 7647 | /* and that the unpin work is consistent wrt ->pending. */ |
7648 | smp_rmb(); |
||
7649 | |||
3031 | serge | 7650 | intel_crtc->unpin_work = NULL; |
2327 | Serge | 7651 | |
3243 | Serge | 7652 | if (work->event) |
7653 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
||
2327 | Serge | 7654 | |
3031 | serge | 7655 | drm_vblank_put(dev, intel_crtc->pipe); |
2327 | Serge | 7656 | |
3031 | serge | 7657 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2327 | Serge | 7658 | |
3480 | Serge | 7659 | wake_up_all(&dev_priv->pending_flip_queue); |
2327 | Serge | 7660 | |
3243 | Serge | 7661 | queue_work(dev_priv->wq, &work->work); |
7662 | |||
3031 | serge | 7663 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
7664 | } |
||
2327 | Serge | 7665 | |
3031 | serge | 7666 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7667 | { |
||
7668 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7669 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
||
2327 | Serge | 7670 | |
3031 | serge | 7671 | do_intel_finish_page_flip(dev, crtc); |
7672 | } |
||
2327 | Serge | 7673 | |
3031 | serge | 7674 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
7675 | { |
||
7676 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7677 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
||
2327 | Serge | 7678 | |
3031 | serge | 7679 | do_intel_finish_page_flip(dev, crtc); |
7680 | } |
||
2327 | Serge | 7681 | |
3031 | serge | 7682 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7683 | { |
||
7684 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7685 | struct intel_crtc *intel_crtc = |
||
7686 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
||
7687 | unsigned long flags; |
||
2327 | Serge | 7688 | |
3243 | Serge | 7689 | /* NB: An MMIO update of the plane base pointer will also |
7690 | * generate a page-flip completion irq, i.e. every modeset |
||
7691 | * is also accompanied by a spurious intel_prepare_page_flip(). |
||
7692 | */ |
||
3031 | serge | 7693 | spin_lock_irqsave(&dev->event_lock, flags); |
3243 | Serge | 7694 | if (intel_crtc->unpin_work) |
7695 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
||
3031 | serge | 7696 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7697 | } |
||
2327 | Serge | 7698 | |
3243 | Serge | 7699 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7700 | { |
||
7701 | /* Ensure that the work item is consistent when activating it ... */ |
||
7702 | smp_wmb(); |
||
7703 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
||
7704 | /* and that it is marked active as soon as the irq could fire. */ |
||
7705 | smp_wmb(); |
||
7706 | } |
||
7707 | |||
3031 | serge | 7708 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7709 | struct drm_crtc *crtc, |
||
7710 | struct drm_framebuffer *fb, |
||
4104 | Serge | 7711 | struct drm_i915_gem_object *obj, |
7712 | uint32_t flags) |
||
3031 | serge | 7713 | { |
7714 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
7716 | u32 flip_mask; |
||
7717 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
7718 | int ret; |
||
2327 | Serge | 7719 | |
3031 | serge | 7720 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7721 | if (ret) |
||
7722 | goto err; |
||
2327 | Serge | 7723 | |
3031 | serge | 7724 | ret = intel_ring_begin(ring, 6); |
7725 | if (ret) |
||
7726 | goto err_unpin; |
||
2327 | Serge | 7727 | |
3031 | serge | 7728 | /* Can't queue multiple flips, so wait for the previous |
7729 | * one to finish before executing the next. |
||
7730 | */ |
||
7731 | if (intel_crtc->plane) |
||
7732 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
||
7733 | else |
||
7734 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
||
7735 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
||
7736 | intel_ring_emit(ring, MI_NOOP); |
||
7737 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
||
7738 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
||
7739 | intel_ring_emit(ring, fb->pitches[0]); |
||
4104 | Serge | 7740 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
3031 | serge | 7741 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
3243 | Serge | 7742 | |
7743 | intel_mark_page_flip_active(intel_crtc); |
||
3031 | serge | 7744 | intel_ring_advance(ring); |
7745 | return 0; |
||
2327 | Serge | 7746 | |
3031 | serge | 7747 | err_unpin: |
7748 | intel_unpin_fb_obj(obj); |
||
7749 | err: |
||
7750 | return ret; |
||
7751 | } |
||
2327 | Serge | 7752 | |
3031 | serge | 7753 | static int intel_gen3_queue_flip(struct drm_device *dev, |
7754 | struct drm_crtc *crtc, |
||
7755 | struct drm_framebuffer *fb, |
||
4104 | Serge | 7756 | struct drm_i915_gem_object *obj, |
7757 | uint32_t flags) |
||
3031 | serge | 7758 | { |
7759 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
7761 | u32 flip_mask; |
||
7762 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
7763 | int ret; |
||
2327 | Serge | 7764 | |
3031 | serge | 7765 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7766 | if (ret) |
||
7767 | goto err; |
||
2327 | Serge | 7768 | |
3031 | serge | 7769 | ret = intel_ring_begin(ring, 6); |
7770 | if (ret) |
||
7771 | goto err_unpin; |
||
2327 | Serge | 7772 | |
3031 | serge | 7773 | if (intel_crtc->plane) |
7774 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
||
7775 | else |
||
7776 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
||
7777 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
||
7778 | intel_ring_emit(ring, MI_NOOP); |
||
7779 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
||
7780 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
||
7781 | intel_ring_emit(ring, fb->pitches[0]); |
||
4104 | Serge | 7782 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
3031 | serge | 7783 | intel_ring_emit(ring, MI_NOOP); |
2327 | Serge | 7784 | |
3243 | Serge | 7785 | intel_mark_page_flip_active(intel_crtc); |
3031 | serge | 7786 | intel_ring_advance(ring); |
7787 | return 0; |
||
2327 | Serge | 7788 | |
3031 | serge | 7789 | err_unpin: |
7790 | intel_unpin_fb_obj(obj); |
||
7791 | err: |
||
7792 | return ret; |
||
7793 | } |
||
2327 | Serge | 7794 | |
3031 | serge | 7795 | static int intel_gen4_queue_flip(struct drm_device *dev, |
7796 | struct drm_crtc *crtc, |
||
7797 | struct drm_framebuffer *fb, |
||
4104 | Serge | 7798 | struct drm_i915_gem_object *obj, |
7799 | uint32_t flags) |
||
3031 | serge | 7800 | { |
7801 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
7803 | uint32_t pf, pipesrc; |
||
7804 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
7805 | int ret; |
||
2327 | Serge | 7806 | |
3031 | serge | 7807 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7808 | if (ret) |
||
7809 | goto err; |
||
2327 | Serge | 7810 | |
3031 | serge | 7811 | ret = intel_ring_begin(ring, 4); |
7812 | if (ret) |
||
7813 | goto err_unpin; |
||
2327 | Serge | 7814 | |
3031 | serge | 7815 | /* i965+ uses the linear or tiled offsets from the |
7816 | * Display Registers (which do not change across a page-flip) |
||
7817 | * so we need only reprogram the base address. |
||
7818 | */ |
||
7819 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
||
7820 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
||
7821 | intel_ring_emit(ring, fb->pitches[0]); |
||
7822 | intel_ring_emit(ring, |
||
4104 | Serge | 7823 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
3031 | serge | 7824 | obj->tiling_mode); |
2327 | Serge | 7825 | |
3031 | serge | 7826 | /* XXX Enabling the panel-fitter across page-flip is so far |
7827 | * untested on non-native modes, so ignore it for now. |
||
7828 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
||
7829 | */ |
||
7830 | pf = 0; |
||
7831 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
||
7832 | intel_ring_emit(ring, pf | pipesrc); |
||
3243 | Serge | 7833 | |
7834 | intel_mark_page_flip_active(intel_crtc); |
||
3031 | serge | 7835 | intel_ring_advance(ring); |
7836 | return 0; |
||
2327 | Serge | 7837 | |
3031 | serge | 7838 | err_unpin: |
7839 | intel_unpin_fb_obj(obj); |
||
7840 | err: |
||
7841 | return ret; |
||
7842 | } |
||
2327 | Serge | 7843 | |
3031 | serge | 7844 | static int intel_gen6_queue_flip(struct drm_device *dev, |
7845 | struct drm_crtc *crtc, |
||
7846 | struct drm_framebuffer *fb, |
||
4104 | Serge | 7847 | struct drm_i915_gem_object *obj, |
7848 | uint32_t flags) |
||
3031 | serge | 7849 | { |
7850 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7851 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
7852 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
7853 | uint32_t pf, pipesrc; |
||
7854 | int ret; |
||
2327 | Serge | 7855 | |
3031 | serge | 7856 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7857 | if (ret) |
||
7858 | goto err; |
||
2327 | Serge | 7859 | |
3031 | serge | 7860 | ret = intel_ring_begin(ring, 4); |
7861 | if (ret) |
||
7862 | goto err_unpin; |
||
2327 | Serge | 7863 | |
3031 | serge | 7864 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7865 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
||
7866 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
||
4104 | Serge | 7867 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2327 | Serge | 7868 | |
3031 | serge | 7869 | /* Contrary to the suggestions in the documentation, |
7870 | * "Enable Panel Fitter" does not seem to be required when page |
||
7871 | * flipping with a non-native mode, and worse causes a normal |
||
7872 | * modeset to fail. |
||
7873 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
||
7874 | */ |
||
7875 | pf = 0; |
||
7876 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
||
7877 | intel_ring_emit(ring, pf | pipesrc); |
||
3243 | Serge | 7878 | |
7879 | intel_mark_page_flip_active(intel_crtc); |
||
3031 | serge | 7880 | intel_ring_advance(ring); |
7881 | return 0; |
||
2327 | Serge | 7882 | |
3031 | serge | 7883 | err_unpin: |
7884 | intel_unpin_fb_obj(obj); |
||
7885 | err: |
||
7886 | return ret; |
||
7887 | } |
||
2327 | Serge | 7888 | |
3031 | serge | 7889 | static int intel_gen7_queue_flip(struct drm_device *dev, |
7890 | struct drm_crtc *crtc, |
||
7891 | struct drm_framebuffer *fb, |
||
4104 | Serge | 7892 | struct drm_i915_gem_object *obj, |
7893 | uint32_t flags) |
||
3031 | serge | 7894 | { |
7895 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7896 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4104 | Serge | 7897 | struct intel_ring_buffer *ring; |
3031 | serge | 7898 | uint32_t plane_bit = 0; |
4104 | Serge | 7899 | int len, ret; |
2327 | Serge | 7900 | |
4104 | Serge | 7901 | ring = obj->ring; |
7902 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
||
7903 | ring = &dev_priv->ring[BCS]; |
||
7904 | |||
3031 | serge | 7905 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7906 | if (ret) |
||
7907 | goto err; |
||
2327 | Serge | 7908 | |
3031 | serge | 7909 | switch(intel_crtc->plane) { |
7910 | case PLANE_A: |
||
7911 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
||
7912 | break; |
||
7913 | case PLANE_B: |
||
7914 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
||
7915 | break; |
||
7916 | case PLANE_C: |
||
7917 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
||
7918 | break; |
||
7919 | default: |
||
7920 | WARN_ONCE(1, "unknown plane in flip command\n"); |
||
7921 | ret = -ENODEV; |
||
7922 | goto err_unpin; |
||
7923 | } |
||
2327 | Serge | 7924 | |
4104 | Serge | 7925 | len = 4; |
7926 | if (ring->id == RCS) |
||
7927 | len += 6; |
||
7928 | |||
7929 | ret = intel_ring_begin(ring, len); |
||
3031 | serge | 7930 | if (ret) |
7931 | goto err_unpin; |
||
2327 | Serge | 7932 | |
4104 | Serge | 7933 | /* Unmask the flip-done completion message. Note that the bspec says that |
7934 | * we should do this for both the BCS and RCS, and that we must not unmask |
||
7935 | * more than one flip event at any time (or ensure that one flip message |
||
7936 | * can be sent by waiting for flip-done prior to queueing new flips). |
||
7937 | * Experimentation says that BCS works despite DERRMR masking all |
||
7938 | * flip-done completion events and that unmasking all planes at once |
||
7939 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
||
7940 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
||
7941 | */ |
||
7942 | if (ring->id == RCS) { |
||
7943 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
||
7944 | intel_ring_emit(ring, DERRMR); |
||
7945 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
||
7946 | DERRMR_PIPEB_PRI_FLIP_DONE | |
||
7947 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
||
7948 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); |
||
7949 | intel_ring_emit(ring, DERRMR); |
||
7950 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
||
7951 | } |
||
7952 | |||
3031 | serge | 7953 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
7954 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
||
4104 | Serge | 7955 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
3031 | serge | 7956 | intel_ring_emit(ring, (MI_NOOP)); |
3243 | Serge | 7957 | |
7958 | intel_mark_page_flip_active(intel_crtc); |
||
3031 | serge | 7959 | intel_ring_advance(ring); |
7960 | return 0; |
||
2327 | Serge | 7961 | |
3031 | serge | 7962 | err_unpin: |
7963 | intel_unpin_fb_obj(obj); |
||
7964 | err: |
||
7965 | return ret; |
||
7966 | } |
||
2327 | Serge | 7967 | |
3031 | serge | 7968 | static int intel_default_queue_flip(struct drm_device *dev, |
7969 | struct drm_crtc *crtc, |
||
7970 | struct drm_framebuffer *fb, |
||
4104 | Serge | 7971 | struct drm_i915_gem_object *obj, |
7972 | uint32_t flags) |
||
3031 | serge | 7973 | { |
7974 | return -ENODEV; |
||
7975 | } |
||
2327 | Serge | 7976 | |
3031 | serge | 7977 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7978 | struct drm_framebuffer *fb, |
||
4104 | Serge | 7979 | struct drm_pending_vblank_event *event, |
7980 | uint32_t page_flip_flags) |
||
3031 | serge | 7981 | { |
7982 | struct drm_device *dev = crtc->dev; |
||
7983 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3480 | Serge | 7984 | struct drm_framebuffer *old_fb = crtc->fb; |
7985 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
||
3031 | serge | 7986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7987 | struct intel_unpin_work *work; |
||
7988 | unsigned long flags; |
||
7989 | int ret; |
||
2327 | Serge | 7990 | |
3031 | serge | 7991 | /* Can't change pixel format via MI display flips. */ |
7992 | if (fb->pixel_format != crtc->fb->pixel_format) |
||
7993 | return -EINVAL; |
||
2327 | Serge | 7994 | |
3031 | serge | 7995 | /* |
7996 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
||
7997 | * Note that pitch changes could also affect these register. |
||
7998 | */ |
||
7999 | if (INTEL_INFO(dev)->gen > 3 && |
||
8000 | (fb->offsets[0] != crtc->fb->offsets[0] || |
||
8001 | fb->pitches[0] != crtc->fb->pitches[0])) |
||
8002 | return -EINVAL; |
||
2327 | Serge | 8003 | |
3031 | serge | 8004 | work = kzalloc(sizeof *work, GFP_KERNEL); |
8005 | if (work == NULL) |
||
8006 | return -ENOMEM; |
||
2327 | Serge | 8007 | |
3031 | serge | 8008 | work->event = event; |
3243 | Serge | 8009 | work->crtc = crtc; |
3480 | Serge | 8010 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
3031 | serge | 8011 | INIT_WORK(&work->work, intel_unpin_work_fn); |
2327 | Serge | 8012 | |
3031 | serge | 8013 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8014 | if (ret) |
||
8015 | goto free_work; |
||
2327 | Serge | 8016 | |
3031 | serge | 8017 | /* We borrow the event spin lock for protecting unpin_work */ |
8018 | spin_lock_irqsave(&dev->event_lock, flags); |
||
8019 | if (intel_crtc->unpin_work) { |
||
8020 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
8021 | kfree(work); |
||
8022 | drm_vblank_put(dev, intel_crtc->pipe); |
||
2327 | Serge | 8023 | |
3031 | serge | 8024 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
8025 | return -EBUSY; |
||
8026 | } |
||
8027 | intel_crtc->unpin_work = work; |
||
8028 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
2327 | Serge | 8029 | |
3243 | Serge | 8030 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8031 | flush_workqueue(dev_priv->wq); |
||
8032 | |||
3031 | serge | 8033 | ret = i915_mutex_lock_interruptible(dev); |
8034 | if (ret) |
||
8035 | goto cleanup; |
||
2327 | Serge | 8036 | |
3031 | serge | 8037 | /* Reference the objects for the scheduled work. */ |
8038 | drm_gem_object_reference(&work->old_fb_obj->base); |
||
8039 | drm_gem_object_reference(&obj->base); |
||
2327 | Serge | 8040 | |
3031 | serge | 8041 | crtc->fb = fb; |
2327 | Serge | 8042 | |
3031 | serge | 8043 | work->pending_flip_obj = obj; |
2327 | Serge | 8044 | |
3031 | serge | 8045 | work->enable_stall_check = true; |
8046 | |||
3243 | Serge | 8047 | atomic_inc(&intel_crtc->unpin_work_count); |
3480 | Serge | 8048 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3031 | serge | 8049 | |
4104 | Serge | 8050 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
3031 | serge | 8051 | if (ret) |
8052 | goto cleanup_pending; |
||
8053 | |||
8054 | intel_disable_fbc(dev); |
||
4104 | Serge | 8055 | intel_mark_fb_busy(obj, NULL); |
3031 | serge | 8056 | mutex_unlock(&dev->struct_mutex); |
8057 | |||
8058 | trace_i915_flip_request(intel_crtc->plane, obj); |
||
8059 | |||
8060 | return 0; |
||
8061 | |||
8062 | cleanup_pending: |
||
3243 | Serge | 8063 | atomic_dec(&intel_crtc->unpin_work_count); |
3480 | Serge | 8064 | crtc->fb = old_fb; |
3031 | serge | 8065 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8066 | drm_gem_object_unreference(&obj->base); |
||
8067 | mutex_unlock(&dev->struct_mutex); |
||
8068 | |||
8069 | cleanup: |
||
8070 | spin_lock_irqsave(&dev->event_lock, flags); |
||
8071 | intel_crtc->unpin_work = NULL; |
||
8072 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
8073 | |||
8074 | drm_vblank_put(dev, intel_crtc->pipe); |
||
8075 | free_work: |
||
8076 | kfree(work); |
||
8077 | |||
8078 | return ret; |
||
8079 | } |
||
8080 | #endif |
||
8081 | |||
8082 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
||
8083 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
||
8084 | .load_lut = intel_crtc_load_lut, |
||
8085 | }; |
||
8086 | |||
8087 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
||
8088 | struct drm_crtc *crtc) |
||
8089 | { |
||
8090 | struct drm_device *dev; |
||
8091 | struct drm_crtc *tmp; |
||
8092 | int crtc_mask = 1; |
||
8093 | |||
8094 | WARN(!crtc, "checking null crtc?\n"); |
||
8095 | |||
8096 | dev = crtc->dev; |
||
8097 | |||
8098 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
||
8099 | if (tmp == crtc) |
||
8100 | break; |
||
8101 | crtc_mask <<= 1; |
||
8102 | } |
||
8103 | |||
8104 | if (encoder->possible_crtcs & crtc_mask) |
||
8105 | return true; |
||
8106 | return false; |
||
8107 | } |
||
8108 | |||
8109 | /** |
||
8110 | * intel_modeset_update_staged_output_state |
||
8111 | * |
||
8112 | * Updates the staged output configuration state, e.g. after we've read out the |
||
8113 | * current hw state. |
||
8114 | */ |
||
8115 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
||
8116 | { |
||
8117 | struct intel_encoder *encoder; |
||
8118 | struct intel_connector *connector; |
||
8119 | |||
8120 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
8121 | base.head) { |
||
8122 | connector->new_encoder = |
||
8123 | to_intel_encoder(connector->base.encoder); |
||
8124 | } |
||
8125 | |||
8126 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
8127 | base.head) { |
||
8128 | encoder->new_crtc = |
||
8129 | to_intel_crtc(encoder->base.crtc); |
||
8130 | } |
||
8131 | } |
||
8132 | |||
8133 | /** |
||
8134 | * intel_modeset_commit_output_state |
||
8135 | * |
||
8136 | * This function copies the stage display pipe configuration to the real one. |
||
8137 | */ |
||
8138 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
||
8139 | { |
||
8140 | struct intel_encoder *encoder; |
||
8141 | struct intel_connector *connector; |
||
8142 | |||
8143 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
8144 | base.head) { |
||
8145 | connector->base.encoder = &connector->new_encoder->base; |
||
8146 | } |
||
8147 | |||
8148 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
8149 | base.head) { |
||
8150 | encoder->base.crtc = &encoder->new_crtc->base; |
||
8151 | } |
||
8152 | } |
||
8153 | |||
4104 | Serge | 8154 | static void |
8155 | connected_sink_compute_bpp(struct intel_connector * connector, |
||
8156 | struct intel_crtc_config *pipe_config) |
||
8157 | { |
||
8158 | int bpp = pipe_config->pipe_bpp; |
||
8159 | |||
8160 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
||
8161 | connector->base.base.id, |
||
8162 | drm_get_connector_name(&connector->base)); |
||
8163 | |||
8164 | /* Don't use an invalid EDID bpc value */ |
||
8165 | if (connector->base.display_info.bpc && |
||
8166 | connector->base.display_info.bpc * 3 < bpp) { |
||
8167 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
||
8168 | bpp, connector->base.display_info.bpc*3); |
||
8169 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
||
8170 | } |
||
8171 | |||
8172 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
||
8173 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
||
8174 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
||
8175 | bpp); |
||
8176 | pipe_config->pipe_bpp = 24; |
||
8177 | } |
||
8178 | } |
||
8179 | |||
3746 | Serge | 8180 | static int |
4104 | Serge | 8181 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
3746 | Serge | 8182 | struct drm_framebuffer *fb, |
8183 | struct intel_crtc_config *pipe_config) |
||
8184 | { |
||
4104 | Serge | 8185 | struct drm_device *dev = crtc->base.dev; |
8186 | struct intel_connector *connector; |
||
3746 | Serge | 8187 | int bpp; |
8188 | |||
8189 | switch (fb->pixel_format) { |
||
8190 | case DRM_FORMAT_C8: |
||
8191 | bpp = 8*3; /* since we go through a colormap */ |
||
8192 | break; |
||
8193 | case DRM_FORMAT_XRGB1555: |
||
8194 | case DRM_FORMAT_ARGB1555: |
||
8195 | /* checked in intel_framebuffer_init already */ |
||
8196 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
||
8197 | return -EINVAL; |
||
8198 | case DRM_FORMAT_RGB565: |
||
8199 | bpp = 6*3; /* min is 18bpp */ |
||
8200 | break; |
||
8201 | case DRM_FORMAT_XBGR8888: |
||
8202 | case DRM_FORMAT_ABGR8888: |
||
8203 | /* checked in intel_framebuffer_init already */ |
||
8204 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
||
8205 | return -EINVAL; |
||
8206 | case DRM_FORMAT_XRGB8888: |
||
8207 | case DRM_FORMAT_ARGB8888: |
||
8208 | bpp = 8*3; |
||
8209 | break; |
||
8210 | case DRM_FORMAT_XRGB2101010: |
||
8211 | case DRM_FORMAT_ARGB2101010: |
||
8212 | case DRM_FORMAT_XBGR2101010: |
||
8213 | case DRM_FORMAT_ABGR2101010: |
||
8214 | /* checked in intel_framebuffer_init already */ |
||
8215 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
||
8216 | return -EINVAL; |
||
8217 | bpp = 10*3; |
||
8218 | break; |
||
8219 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
||
8220 | default: |
||
8221 | DRM_DEBUG_KMS("unsupported depth\n"); |
||
8222 | return -EINVAL; |
||
8223 | } |
||
8224 | |||
8225 | pipe_config->pipe_bpp = bpp; |
||
8226 | |||
8227 | /* Clamp display bpp to EDID value */ |
||
8228 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
4104 | Serge | 8229 | base.head) { |
8230 | if (!connector->new_encoder || |
||
8231 | connector->new_encoder->new_crtc != crtc) |
||
3746 | Serge | 8232 | continue; |
8233 | |||
4104 | Serge | 8234 | connected_sink_compute_bpp(connector, pipe_config); |
3746 | Serge | 8235 | } |
8236 | |||
8237 | return bpp; |
||
8238 | } |
||
8239 | |||
4104 | Serge | 8240 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8241 | struct intel_crtc_config *pipe_config, |
||
8242 | const char *context) |
||
8243 | { |
||
8244 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
||
8245 | context, pipe_name(crtc->pipe)); |
||
8246 | |||
8247 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
||
8248 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
||
8249 | pipe_config->pipe_bpp, pipe_config->dither); |
||
8250 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
||
8251 | pipe_config->has_pch_encoder, |
||
8252 | pipe_config->fdi_lanes, |
||
8253 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
||
8254 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
||
8255 | pipe_config->fdi_m_n.tu); |
||
8256 | DRM_DEBUG_KMS("requested mode:\n"); |
||
8257 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
||
8258 | DRM_DEBUG_KMS("adjusted mode:\n"); |
||
8259 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
||
8260 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
||
8261 | pipe_config->gmch_pfit.control, |
||
8262 | pipe_config->gmch_pfit.pgm_ratios, |
||
8263 | pipe_config->gmch_pfit.lvds_border_bits); |
||
8264 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
||
8265 | pipe_config->pch_pfit.pos, |
||
8266 | pipe_config->pch_pfit.size, |
||
8267 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
||
8268 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
||
8269 | } |
||
8270 | |||
8271 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
||
8272 | { |
||
8273 | int num_encoders = 0; |
||
8274 | bool uncloneable_encoders = false; |
||
8275 | struct intel_encoder *encoder; |
||
8276 | |||
8277 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, |
||
8278 | base.head) { |
||
8279 | if (&encoder->new_crtc->base != crtc) |
||
8280 | continue; |
||
8281 | |||
8282 | num_encoders++; |
||
8283 | if (!encoder->cloneable) |
||
8284 | uncloneable_encoders = true; |
||
8285 | } |
||
8286 | |||
8287 | return !(num_encoders > 1 && uncloneable_encoders); |
||
8288 | } |
||
8289 | |||
3746 | Serge | 8290 | static struct intel_crtc_config * |
8291 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
||
8292 | struct drm_framebuffer *fb, |
||
3031 | serge | 8293 | struct drm_display_mode *mode) |
8294 | { |
||
8295 | struct drm_device *dev = crtc->dev; |
||
8296 | struct intel_encoder *encoder; |
||
3746 | Serge | 8297 | struct intel_crtc_config *pipe_config; |
4104 | Serge | 8298 | int plane_bpp, ret = -EINVAL; |
8299 | bool retry = true; |
||
3031 | serge | 8300 | |
4104 | Serge | 8301 | if (!check_encoder_cloning(crtc)) { |
8302 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
||
8303 | return ERR_PTR(-EINVAL); |
||
8304 | } |
||
8305 | |||
3746 | Serge | 8306 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8307 | if (!pipe_config) |
||
3031 | serge | 8308 | return ERR_PTR(-ENOMEM); |
8309 | |||
3746 | Serge | 8310 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8311 | drm_mode_copy(&pipe_config->requested_mode, mode); |
||
4104 | Serge | 8312 | pipe_config->cpu_transcoder = |
8313 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
||
8314 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
||
3746 | Serge | 8315 | |
4104 | Serge | 8316 | /* |
8317 | * Sanitize sync polarity flags based on requested ones. If neither |
||
8318 | * positive or negative polarity is requested, treat this as meaning |
||
8319 | * negative polarity. |
||
8320 | */ |
||
8321 | if (!(pipe_config->adjusted_mode.flags & |
||
8322 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
||
8323 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
||
8324 | |||
8325 | if (!(pipe_config->adjusted_mode.flags & |
||
8326 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
||
8327 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
||
8328 | |||
8329 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
||
8330 | * plane pixel format and any sink constraints into account. Returns the |
||
8331 | * source plane bpp so that dithering can be selected on mismatches |
||
8332 | * after encoders and crtc also have had their say. */ |
||
8333 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
||
8334 | fb, pipe_config); |
||
3746 | Serge | 8335 | if (plane_bpp < 0) |
8336 | goto fail; |
||
8337 | |||
4104 | Serge | 8338 | encoder_retry: |
8339 | /* Ensure the port clock defaults are reset when retrying. */ |
||
8340 | pipe_config->port_clock = 0; |
||
8341 | pipe_config->pixel_multiplier = 1; |
||
8342 | |||
8343 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
||
8344 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0); |
||
8345 | |||
3031 | serge | 8346 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8347 | * adjust it according to limitations or connector properties, and also |
||
8348 | * a chance to reject the mode entirely. |
||
2330 | Serge | 8349 | */ |
3031 | serge | 8350 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8351 | base.head) { |
||
2327 | Serge | 8352 | |
3031 | serge | 8353 | if (&encoder->new_crtc->base != crtc) |
8354 | continue; |
||
3746 | Serge | 8355 | |
8356 | if (!(encoder->compute_config(encoder, pipe_config))) { |
||
8357 | DRM_DEBUG_KMS("Encoder config failure\n"); |
||
8358 | goto fail; |
||
8359 | } |
||
8360 | } |
||
8361 | |||
4104 | Serge | 8362 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8363 | * done afterwards in case the encoder adjusts the mode. */ |
||
8364 | if (!pipe_config->port_clock) |
||
8365 | pipe_config->port_clock = pipe_config->adjusted_mode.clock; |
||
2327 | Serge | 8366 | |
4104 | Serge | 8367 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
8368 | if (ret < 0) { |
||
3031 | serge | 8369 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8370 | goto fail; |
||
8371 | } |
||
2327 | Serge | 8372 | |
4104 | Serge | 8373 | if (ret == RETRY) { |
8374 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
||
8375 | ret = -EINVAL; |
||
8376 | goto fail; |
||
8377 | } |
||
8378 | |||
8379 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
||
8380 | retry = false; |
||
8381 | goto encoder_retry; |
||
8382 | } |
||
8383 | |||
3746 | Serge | 8384 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8385 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
||
8386 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
||
8387 | |||
8388 | return pipe_config; |
||
3031 | serge | 8389 | fail: |
3746 | Serge | 8390 | kfree(pipe_config); |
4104 | Serge | 8391 | return ERR_PTR(ret); |
3031 | serge | 8392 | } |
2327 | Serge | 8393 | |
3031 | serge | 8394 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8395 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
||
8396 | static void |
||
8397 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
||
8398 | unsigned *prepare_pipes, unsigned *disable_pipes) |
||
8399 | { |
||
8400 | struct intel_crtc *intel_crtc; |
||
8401 | struct drm_device *dev = crtc->dev; |
||
8402 | struct intel_encoder *encoder; |
||
8403 | struct intel_connector *connector; |
||
8404 | struct drm_crtc *tmp_crtc; |
||
8405 | |||
8406 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
||
8407 | |||
8408 | /* Check which crtcs have changed outputs connected to them, these need |
||
8409 | * to be part of the prepare_pipes mask. We don't (yet) support global |
||
8410 | * modeset across multiple crtcs, so modeset_pipes will only have one |
||
8411 | * bit set at most. */ |
||
8412 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
8413 | base.head) { |
||
8414 | if (connector->base.encoder == &connector->new_encoder->base) |
||
8415 | continue; |
||
8416 | |||
8417 | if (connector->base.encoder) { |
||
8418 | tmp_crtc = connector->base.encoder->crtc; |
||
8419 | |||
8420 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
||
8421 | } |
||
8422 | |||
8423 | if (connector->new_encoder) |
||
8424 | *prepare_pipes |= |
||
8425 | 1 << connector->new_encoder->new_crtc->pipe; |
||
8426 | } |
||
8427 | |||
8428 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
8429 | base.head) { |
||
8430 | if (encoder->base.crtc == &encoder->new_crtc->base) |
||
8431 | continue; |
||
8432 | |||
8433 | if (encoder->base.crtc) { |
||
8434 | tmp_crtc = encoder->base.crtc; |
||
8435 | |||
8436 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
||
8437 | } |
||
8438 | |||
8439 | if (encoder->new_crtc) |
||
8440 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
||
8441 | } |
||
8442 | |||
8443 | /* Check for any pipes that will be fully disabled ... */ |
||
8444 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
||
8445 | base.head) { |
||
8446 | bool used = false; |
||
8447 | |||
8448 | /* Don't try to disable disabled crtcs. */ |
||
8449 | if (!intel_crtc->base.enabled) |
||
8450 | continue; |
||
8451 | |||
8452 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
8453 | base.head) { |
||
8454 | if (encoder->new_crtc == intel_crtc) |
||
8455 | used = true; |
||
8456 | } |
||
8457 | |||
8458 | if (!used) |
||
8459 | *disable_pipes |= 1 << intel_crtc->pipe; |
||
8460 | } |
||
8461 | |||
8462 | |||
8463 | /* set_mode is also used to update properties on life display pipes. */ |
||
8464 | intel_crtc = to_intel_crtc(crtc); |
||
8465 | if (crtc->enabled) |
||
8466 | *prepare_pipes |= 1 << intel_crtc->pipe; |
||
8467 | |||
3746 | Serge | 8468 | /* |
8469 | * For simplicity do a full modeset on any pipe where the output routing |
||
8470 | * changed. We could be more clever, but that would require us to be |
||
8471 | * more careful with calling the relevant encoder->mode_set functions. |
||
8472 | */ |
||
3031 | serge | 8473 | if (*prepare_pipes) |
8474 | *modeset_pipes = *prepare_pipes; |
||
8475 | |||
8476 | /* ... and mask these out. */ |
||
8477 | *modeset_pipes &= ~(*disable_pipes); |
||
8478 | *prepare_pipes &= ~(*disable_pipes); |
||
3746 | Serge | 8479 | |
8480 | /* |
||
8481 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
||
8482 | * obies this rule, but the modeset restore mode of |
||
8483 | * intel_modeset_setup_hw_state does not. |
||
8484 | */ |
||
8485 | *modeset_pipes &= 1 << intel_crtc->pipe; |
||
8486 | *prepare_pipes &= 1 << intel_crtc->pipe; |
||
4104 | Serge | 8487 | |
8488 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
||
8489 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
||
2330 | Serge | 8490 | } |
2327 | Serge | 8491 | |
3031 | serge | 8492 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
2330 | Serge | 8493 | { |
3031 | serge | 8494 | struct drm_encoder *encoder; |
2330 | Serge | 8495 | struct drm_device *dev = crtc->dev; |
2327 | Serge | 8496 | |
3031 | serge | 8497 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
8498 | if (encoder->crtc == crtc) |
||
8499 | return true; |
||
8500 | |||
8501 | return false; |
||
8502 | } |
||
8503 | |||
8504 | static void |
||
8505 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
||
8506 | { |
||
8507 | struct intel_encoder *intel_encoder; |
||
8508 | struct intel_crtc *intel_crtc; |
||
8509 | struct drm_connector *connector; |
||
8510 | |||
8511 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
||
8512 | base.head) { |
||
8513 | if (!intel_encoder->base.crtc) |
||
8514 | continue; |
||
8515 | |||
8516 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
||
8517 | |||
8518 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
||
8519 | intel_encoder->connectors_active = false; |
||
8520 | } |
||
8521 | |||
8522 | intel_modeset_commit_output_state(dev); |
||
8523 | |||
8524 | /* Update computed state. */ |
||
8525 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
||
8526 | base.head) { |
||
8527 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
||
8528 | } |
||
8529 | |||
8530 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
8531 | if (!connector->encoder || !connector->encoder->crtc) |
||
8532 | continue; |
||
8533 | |||
8534 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
||
8535 | |||
8536 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
||
8537 | struct drm_property *dpms_property = |
||
8538 | dev->mode_config.dpms_property; |
||
8539 | |||
8540 | connector->dpms = DRM_MODE_DPMS_ON; |
||
3243 | Serge | 8541 | drm_object_property_set_value(&connector->base, |
3031 | serge | 8542 | dpms_property, |
8543 | DRM_MODE_DPMS_ON); |
||
8544 | |||
8545 | intel_encoder = to_intel_encoder(connector->encoder); |
||
8546 | intel_encoder->connectors_active = true; |
||
8547 | } |
||
8548 | } |
||
8549 | |||
8550 | } |
||
8551 | |||
4104 | Serge | 8552 | static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur, |
8553 | struct intel_crtc_config *new) |
||
8554 | { |
||
8555 | int clock1, clock2, diff; |
||
8556 | |||
8557 | clock1 = cur->adjusted_mode.clock; |
||
8558 | clock2 = new->adjusted_mode.clock; |
||
8559 | |||
8560 | if (clock1 == clock2) |
||
8561 | return true; |
||
8562 | |||
8563 | if (!clock1 || !clock2) |
||
8564 | return false; |
||
8565 | |||
8566 | diff = abs(clock1 - clock2); |
||
8567 | |||
8568 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
||
8569 | return true; |
||
8570 | |||
8571 | return false; |
||
8572 | } |
||
8573 | |||
3031 | serge | 8574 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8575 | list_for_each_entry((intel_crtc), \ |
||
8576 | &(dev)->mode_config.crtc_list, \ |
||
8577 | base.head) \ |
||
4104 | Serge | 8578 | if (mask & (1 <<(intel_crtc)->pipe)) |
3031 | serge | 8579 | |
3746 | Serge | 8580 | static bool |
4104 | Serge | 8581 | intel_pipe_config_compare(struct drm_device *dev, |
8582 | struct intel_crtc_config *current_config, |
||
3746 | Serge | 8583 | struct intel_crtc_config *pipe_config) |
8584 | { |
||
4104 | Serge | 8585 | #define PIPE_CONF_CHECK_X(name) \ |
8586 | if (current_config->name != pipe_config->name) { \ |
||
8587 | DRM_ERROR("mismatch in " #name " " \ |
||
8588 | "(expected 0x%08x, found 0x%08x)\n", \ |
||
8589 | current_config->name, \ |
||
8590 | pipe_config->name); \ |
||
8591 | return false; \ |
||
3746 | Serge | 8592 | } |
8593 | |||
4104 | Serge | 8594 | #define PIPE_CONF_CHECK_I(name) \ |
8595 | if (current_config->name != pipe_config->name) { \ |
||
8596 | DRM_ERROR("mismatch in " #name " " \ |
||
8597 | "(expected %i, found %i)\n", \ |
||
8598 | current_config->name, \ |
||
8599 | pipe_config->name); \ |
||
8600 | return false; \ |
||
8601 | } |
||
8602 | |||
8603 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
||
8604 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
||
8605 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
||
8606 | "(expected %i, found %i)\n", \ |
||
8607 | current_config->name & (mask), \ |
||
8608 | pipe_config->name & (mask)); \ |
||
8609 | return false; \ |
||
8610 | } |
||
8611 | |||
8612 | #define PIPE_CONF_QUIRK(quirk) \ |
||
8613 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
||
8614 | |||
8615 | PIPE_CONF_CHECK_I(cpu_transcoder); |
||
8616 | |||
8617 | PIPE_CONF_CHECK_I(has_pch_encoder); |
||
8618 | PIPE_CONF_CHECK_I(fdi_lanes); |
||
8619 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
||
8620 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
||
8621 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
||
8622 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
||
8623 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
||
8624 | |||
8625 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
||
8626 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
||
8627 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
||
8628 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
||
8629 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
||
8630 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
||
8631 | |||
8632 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
||
8633 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
||
8634 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
||
8635 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
||
8636 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
||
8637 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
||
8638 | |||
8639 | PIPE_CONF_CHECK_I(pixel_multiplier); |
||
8640 | |||
8641 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
||
8642 | DRM_MODE_FLAG_INTERLACE); |
||
8643 | |||
8644 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
||
8645 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
||
8646 | DRM_MODE_FLAG_PHSYNC); |
||
8647 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
||
8648 | DRM_MODE_FLAG_NHSYNC); |
||
8649 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
||
8650 | DRM_MODE_FLAG_PVSYNC); |
||
8651 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
||
8652 | DRM_MODE_FLAG_NVSYNC); |
||
8653 | } |
||
8654 | |||
8655 | PIPE_CONF_CHECK_I(requested_mode.hdisplay); |
||
8656 | PIPE_CONF_CHECK_I(requested_mode.vdisplay); |
||
8657 | |||
8658 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
||
8659 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
||
8660 | if (INTEL_INFO(dev)->gen < 4) |
||
8661 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
||
8662 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
||
8663 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
||
8664 | if (current_config->pch_pfit.enabled) { |
||
8665 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
||
8666 | PIPE_CONF_CHECK_I(pch_pfit.size); |
||
8667 | } |
||
8668 | |||
8669 | PIPE_CONF_CHECK_I(ips_enabled); |
||
8670 | |||
8671 | PIPE_CONF_CHECK_I(shared_dpll); |
||
8672 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
||
8673 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
||
8674 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
||
8675 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
||
8676 | |||
4280 | Serge | 8677 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
8678 | PIPE_CONF_CHECK_I(pipe_bpp); |
||
8679 | |||
4104 | Serge | 8680 | #undef PIPE_CONF_CHECK_X |
8681 | #undef PIPE_CONF_CHECK_I |
||
8682 | #undef PIPE_CONF_CHECK_FLAGS |
||
8683 | #undef PIPE_CONF_QUIRK |
||
8684 | |||
8685 | if (!IS_HASWELL(dev)) { |
||
8686 | if (!intel_fuzzy_clock_check(current_config, pipe_config)) { |
||
8687 | DRM_ERROR("mismatch in clock (expected %d, found %d)\n", |
||
8688 | current_config->adjusted_mode.clock, |
||
8689 | pipe_config->adjusted_mode.clock); |
||
8690 | return false; |
||
8691 | } |
||
8692 | } |
||
8693 | |||
3746 | Serge | 8694 | return true; |
8695 | } |
||
8696 | |||
4104 | Serge | 8697 | static void |
8698 | check_connector_state(struct drm_device *dev) |
||
3031 | serge | 8699 | { |
8700 | struct intel_connector *connector; |
||
8701 | |||
8702 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
8703 | base.head) { |
||
8704 | /* This also checks the encoder/connector hw state with the |
||
8705 | * ->get_hw_state callbacks. */ |
||
8706 | intel_connector_check_state(connector); |
||
8707 | |||
8708 | WARN(&connector->new_encoder->base != connector->base.encoder, |
||
8709 | "connector's staged encoder doesn't match current encoder\n"); |
||
8710 | } |
||
4104 | Serge | 8711 | } |
3031 | serge | 8712 | |
4104 | Serge | 8713 | static void |
8714 | check_encoder_state(struct drm_device *dev) |
||
8715 | { |
||
8716 | struct intel_encoder *encoder; |
||
8717 | struct intel_connector *connector; |
||
8718 | |||
3031 | serge | 8719 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8720 | base.head) { |
||
8721 | bool enabled = false; |
||
8722 | bool active = false; |
||
8723 | enum pipe pipe, tracked_pipe; |
||
8724 | |||
8725 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
||
8726 | encoder->base.base.id, |
||
8727 | drm_get_encoder_name(&encoder->base)); |
||
8728 | |||
8729 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
||
8730 | "encoder's stage crtc doesn't match current crtc\n"); |
||
8731 | WARN(encoder->connectors_active && !encoder->base.crtc, |
||
8732 | "encoder's active_connectors set, but no crtc\n"); |
||
8733 | |||
8734 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
8735 | base.head) { |
||
8736 | if (connector->base.encoder != &encoder->base) |
||
8737 | continue; |
||
8738 | enabled = true; |
||
8739 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
||
8740 | active = true; |
||
8741 | } |
||
8742 | WARN(!!encoder->base.crtc != enabled, |
||
8743 | "encoder's enabled state mismatch " |
||
8744 | "(expected %i, found %i)\n", |
||
8745 | !!encoder->base.crtc, enabled); |
||
8746 | WARN(active && !encoder->base.crtc, |
||
8747 | "active encoder with no crtc\n"); |
||
8748 | |||
8749 | WARN(encoder->connectors_active != active, |
||
8750 | "encoder's computed active state doesn't match tracked active state " |
||
8751 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
||
8752 | |||
8753 | active = encoder->get_hw_state(encoder, &pipe); |
||
8754 | WARN(active != encoder->connectors_active, |
||
8755 | "encoder's hw state doesn't match sw tracking " |
||
8756 | "(expected %i, found %i)\n", |
||
8757 | encoder->connectors_active, active); |
||
8758 | |||
8759 | if (!encoder->base.crtc) |
||
8760 | continue; |
||
8761 | |||
8762 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
||
8763 | WARN(active && pipe != tracked_pipe, |
||
8764 | "active encoder's pipe doesn't match" |
||
8765 | "(expected %i, found %i)\n", |
||
8766 | tracked_pipe, pipe); |
||
8767 | |||
8768 | } |
||
4104 | Serge | 8769 | } |
3031 | serge | 8770 | |
4104 | Serge | 8771 | static void |
8772 | check_crtc_state(struct drm_device *dev) |
||
8773 | { |
||
8774 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
8775 | struct intel_crtc *crtc; |
||
8776 | struct intel_encoder *encoder; |
||
8777 | struct intel_crtc_config pipe_config; |
||
8778 | |||
3031 | serge | 8779 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8780 | base.head) { |
||
8781 | bool enabled = false; |
||
8782 | bool active = false; |
||
8783 | |||
4104 | Serge | 8784 | memset(&pipe_config, 0, sizeof(pipe_config)); |
8785 | |||
3031 | serge | 8786 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
8787 | crtc->base.base.id); |
||
8788 | |||
8789 | WARN(crtc->active && !crtc->base.enabled, |
||
8790 | "active crtc, but not enabled in sw tracking\n"); |
||
8791 | |||
8792 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
8793 | base.head) { |
||
8794 | if (encoder->base.crtc != &crtc->base) |
||
8795 | continue; |
||
8796 | enabled = true; |
||
8797 | if (encoder->connectors_active) |
||
8798 | active = true; |
||
8799 | } |
||
4104 | Serge | 8800 | |
3031 | serge | 8801 | WARN(active != crtc->active, |
8802 | "crtc's computed active state doesn't match tracked active state " |
||
8803 | "(expected %i, found %i)\n", active, crtc->active); |
||
8804 | WARN(enabled != crtc->base.enabled, |
||
8805 | "crtc's computed enabled state doesn't match tracked enabled state " |
||
8806 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
||
8807 | |||
3746 | Serge | 8808 | active = dev_priv->display.get_pipe_config(crtc, |
8809 | &pipe_config); |
||
8810 | |||
8811 | /* hw state is inconsistent with the pipe A quirk */ |
||
8812 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
||
8813 | active = crtc->active; |
||
8814 | |||
4104 | Serge | 8815 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8816 | base.head) { |
||
8817 | enum pipe pipe; |
||
8818 | if (encoder->base.crtc != &crtc->base) |
||
8819 | continue; |
||
8820 | if (encoder->get_config && |
||
8821 | encoder->get_hw_state(encoder, &pipe)) |
||
8822 | encoder->get_config(encoder, &pipe_config); |
||
8823 | } |
||
8824 | |||
8825 | if (dev_priv->display.get_clock) |
||
8826 | dev_priv->display.get_clock(crtc, &pipe_config); |
||
8827 | |||
3746 | Serge | 8828 | WARN(crtc->active != active, |
8829 | "crtc active state doesn't match with hw state " |
||
8830 | "(expected %i, found %i)\n", crtc->active, active); |
||
8831 | |||
4104 | Serge | 8832 | if (active && |
8833 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
||
8834 | WARN(1, "pipe state doesn't match!\n"); |
||
8835 | intel_dump_pipe_config(crtc, &pipe_config, |
||
8836 | "[hw state]"); |
||
8837 | intel_dump_pipe_config(crtc, &crtc->config, |
||
8838 | "[sw state]"); |
||
8839 | } |
||
3031 | serge | 8840 | } |
8841 | } |
||
8842 | |||
4104 | Serge | 8843 | static void |
8844 | check_shared_dpll_state(struct drm_device *dev) |
||
8845 | { |
||
8846 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
8847 | struct intel_crtc *crtc; |
||
8848 | struct intel_dpll_hw_state dpll_hw_state; |
||
8849 | int i; |
||
8850 | |||
8851 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
||
8852 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
||
8853 | int enabled_crtcs = 0, active_crtcs = 0; |
||
8854 | bool active; |
||
8855 | |||
8856 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
||
8857 | |||
8858 | DRM_DEBUG_KMS("%s\n", pll->name); |
||
8859 | |||
8860 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
||
8861 | |||
8862 | WARN(pll->active > pll->refcount, |
||
8863 | "more active pll users than references: %i vs %i\n", |
||
8864 | pll->active, pll->refcount); |
||
8865 | WARN(pll->active && !pll->on, |
||
8866 | "pll in active use but not on in sw tracking\n"); |
||
8867 | WARN(pll->on && !pll->active, |
||
8868 | "pll in on but not on in use in sw tracking\n"); |
||
8869 | WARN(pll->on != active, |
||
8870 | "pll on state mismatch (expected %i, found %i)\n", |
||
8871 | pll->on, active); |
||
8872 | |||
8873 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
||
8874 | base.head) { |
||
8875 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
||
8876 | enabled_crtcs++; |
||
8877 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
||
8878 | active_crtcs++; |
||
8879 | } |
||
8880 | WARN(pll->active != active_crtcs, |
||
8881 | "pll active crtcs mismatch (expected %i, found %i)\n", |
||
8882 | pll->active, active_crtcs); |
||
8883 | WARN(pll->refcount != enabled_crtcs, |
||
8884 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
||
8885 | pll->refcount, enabled_crtcs); |
||
8886 | |||
8887 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
||
8888 | sizeof(dpll_hw_state)), |
||
8889 | "pll hw state mismatch\n"); |
||
8890 | } |
||
8891 | } |
||
8892 | |||
8893 | void |
||
8894 | intel_modeset_check_state(struct drm_device *dev) |
||
8895 | { |
||
8896 | check_connector_state(dev); |
||
8897 | check_encoder_state(dev); |
||
8898 | check_crtc_state(dev); |
||
8899 | check_shared_dpll_state(dev); |
||
8900 | } |
||
8901 | |||
3746 | Serge | 8902 | static int __intel_set_mode(struct drm_crtc *crtc, |
3031 | serge | 8903 | struct drm_display_mode *mode, |
8904 | int x, int y, struct drm_framebuffer *fb) |
||
8905 | { |
||
8906 | struct drm_device *dev = crtc->dev; |
||
8907 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
3746 | Serge | 8908 | struct drm_display_mode *saved_mode, *saved_hwmode; |
8909 | struct intel_crtc_config *pipe_config = NULL; |
||
3031 | serge | 8910 | struct intel_crtc *intel_crtc; |
8911 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
||
3480 | Serge | 8912 | int ret = 0; |
3031 | serge | 8913 | |
3480 | Serge | 8914 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
8915 | if (!saved_mode) |
||
8916 | return -ENOMEM; |
||
8917 | saved_hwmode = saved_mode + 1; |
||
8918 | |||
3031 | serge | 8919 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
8920 | &prepare_pipes, &disable_pipes); |
||
8921 | |||
3480 | Serge | 8922 | *saved_hwmode = crtc->hwmode; |
8923 | *saved_mode = crtc->mode; |
||
3031 | serge | 8924 | |
8925 | /* Hack: Because we don't (yet) support global modeset on multiple |
||
8926 | * crtcs, we don't keep track of the new mode for more than one crtc. |
||
8927 | * Hence simply check whether any bit is set in modeset_pipes in all the |
||
8928 | * pieces of code that are not yet converted to deal with mutliple crtcs |
||
8929 | * changing their mode at the same time. */ |
||
8930 | if (modeset_pipes) { |
||
3746 | Serge | 8931 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
8932 | if (IS_ERR(pipe_config)) { |
||
8933 | ret = PTR_ERR(pipe_config); |
||
8934 | pipe_config = NULL; |
||
8935 | |||
3480 | Serge | 8936 | goto out; |
3031 | serge | 8937 | } |
4104 | Serge | 8938 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
8939 | "[modeset]"); |
||
3031 | serge | 8940 | } |
8941 | |||
3746 | Serge | 8942 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
8943 | intel_crtc_disable(&intel_crtc->base); |
||
8944 | |||
3031 | serge | 8945 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
8946 | if (intel_crtc->base.enabled) |
||
8947 | dev_priv->display.crtc_disable(&intel_crtc->base); |
||
8948 | } |
||
8949 | |||
8950 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
||
8951 | * to set it here already despite that we pass it down the callchain. |
||
2330 | Serge | 8952 | */ |
3746 | Serge | 8953 | if (modeset_pipes) { |
3031 | serge | 8954 | crtc->mode = *mode; |
3746 | Serge | 8955 | /* mode_set/enable/disable functions rely on a correct pipe |
8956 | * config. */ |
||
8957 | to_intel_crtc(crtc)->config = *pipe_config; |
||
8958 | } |
||
2327 | Serge | 8959 | |
3031 | serge | 8960 | /* Only after disabling all output pipelines that will be changed can we |
8961 | * update the the output configuration. */ |
||
8962 | intel_modeset_update_state(dev, prepare_pipes); |
||
8963 | |||
3243 | Serge | 8964 | if (dev_priv->display.modeset_global_resources) |
8965 | dev_priv->display.modeset_global_resources(dev); |
||
8966 | |||
3031 | serge | 8967 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
8968 | * on the DPLL. |
||
2330 | Serge | 8969 | */ |
3031 | serge | 8970 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
3480 | Serge | 8971 | ret = intel_crtc_mode_set(&intel_crtc->base, |
3031 | serge | 8972 | x, y, fb); |
3480 | Serge | 8973 | if (ret) |
3031 | serge | 8974 | goto done; |
8975 | } |
||
8976 | |||
8977 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
||
8978 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
||
8979 | dev_priv->display.crtc_enable(&intel_crtc->base); |
||
8980 | |||
8981 | if (modeset_pipes) { |
||
8982 | /* Store real post-adjustment hardware mode. */ |
||
3746 | Serge | 8983 | crtc->hwmode = pipe_config->adjusted_mode; |
3031 | serge | 8984 | |
8985 | /* Calculate and store various constants which |
||
8986 | * are later needed by vblank and swap-completion |
||
8987 | * timestamping. They are derived from true hwmode. |
||
8988 | */ |
||
8989 | drm_calc_timestamping_constants(crtc); |
||
8990 | } |
||
8991 | |||
8992 | /* FIXME: add subpixel order */ |
||
8993 | done: |
||
3480 | Serge | 8994 | if (ret && crtc->enabled) { |
8995 | crtc->hwmode = *saved_hwmode; |
||
8996 | crtc->mode = *saved_mode; |
||
3031 | serge | 8997 | } |
8998 | |||
3480 | Serge | 8999 | out: |
3746 | Serge | 9000 | kfree(pipe_config); |
3480 | Serge | 9001 | kfree(saved_mode); |
3031 | serge | 9002 | return ret; |
2330 | Serge | 9003 | } |
2327 | Serge | 9004 | |
4104 | Serge | 9005 | static int intel_set_mode(struct drm_crtc *crtc, |
3746 | Serge | 9006 | struct drm_display_mode *mode, |
9007 | int x, int y, struct drm_framebuffer *fb) |
||
9008 | { |
||
9009 | int ret; |
||
9010 | |||
9011 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
||
9012 | |||
9013 | if (ret == 0) |
||
9014 | intel_modeset_check_state(crtc->dev); |
||
9015 | |||
9016 | return ret; |
||
9017 | } |
||
9018 | |||
3480 | Serge | 9019 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9020 | { |
||
9021 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); |
||
9022 | } |
||
9023 | |||
3031 | serge | 9024 | #undef for_each_intel_crtc_masked |
2327 | Serge | 9025 | |
3031 | serge | 9026 | static void intel_set_config_free(struct intel_set_config *config) |
9027 | { |
||
9028 | if (!config) |
||
9029 | return; |
||
9030 | |||
9031 | kfree(config->save_connector_encoders); |
||
9032 | kfree(config->save_encoder_crtcs); |
||
9033 | kfree(config); |
||
9034 | } |
||
9035 | |||
9036 | static int intel_set_config_save_state(struct drm_device *dev, |
||
9037 | struct intel_set_config *config) |
||
9038 | { |
||
9039 | struct drm_encoder *encoder; |
||
9040 | struct drm_connector *connector; |
||
9041 | int count; |
||
9042 | |||
9043 | config->save_encoder_crtcs = |
||
9044 | kcalloc(dev->mode_config.num_encoder, |
||
9045 | sizeof(struct drm_crtc *), GFP_KERNEL); |
||
9046 | if (!config->save_encoder_crtcs) |
||
9047 | return -ENOMEM; |
||
9048 | |||
9049 | config->save_connector_encoders = |
||
9050 | kcalloc(dev->mode_config.num_connector, |
||
9051 | sizeof(struct drm_encoder *), GFP_KERNEL); |
||
9052 | if (!config->save_connector_encoders) |
||
9053 | return -ENOMEM; |
||
9054 | |||
9055 | /* Copy data. Note that driver private data is not affected. |
||
9056 | * Should anything bad happen only the expected state is |
||
9057 | * restored, not the drivers personal bookkeeping. |
||
9058 | */ |
||
9059 | count = 0; |
||
9060 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
9061 | config->save_encoder_crtcs[count++] = encoder->crtc; |
||
9062 | } |
||
9063 | |||
9064 | count = 0; |
||
9065 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
9066 | config->save_connector_encoders[count++] = connector->encoder; |
||
9067 | } |
||
9068 | |||
9069 | return 0; |
||
9070 | } |
||
9071 | |||
9072 | static void intel_set_config_restore_state(struct drm_device *dev, |
||
9073 | struct intel_set_config *config) |
||
9074 | { |
||
9075 | struct intel_encoder *encoder; |
||
9076 | struct intel_connector *connector; |
||
9077 | int count; |
||
9078 | |||
9079 | count = 0; |
||
9080 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
||
9081 | encoder->new_crtc = |
||
9082 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
||
9083 | } |
||
9084 | |||
9085 | count = 0; |
||
9086 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
||
9087 | connector->new_encoder = |
||
9088 | to_intel_encoder(config->save_connector_encoders[count++]); |
||
9089 | } |
||
9090 | } |
||
9091 | |||
3746 | Serge | 9092 | static bool |
4104 | Serge | 9093 | is_crtc_connector_off(struct drm_mode_set *set) |
3746 | Serge | 9094 | { |
9095 | int i; |
||
9096 | |||
4104 | Serge | 9097 | if (set->num_connectors == 0) |
9098 | return false; |
||
9099 | |||
9100 | if (WARN_ON(set->connectors == NULL)) |
||
9101 | return false; |
||
9102 | |||
9103 | for (i = 0; i < set->num_connectors; i++) |
||
9104 | if (set->connectors[i]->encoder && |
||
9105 | set->connectors[i]->encoder->crtc == set->crtc && |
||
9106 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
||
3746 | Serge | 9107 | return true; |
9108 | |||
9109 | return false; |
||
9110 | } |
||
9111 | |||
3031 | serge | 9112 | static void |
9113 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
||
9114 | struct intel_set_config *config) |
||
9115 | { |
||
9116 | |||
9117 | /* We should be able to check here if the fb has the same properties |
||
9118 | * and then just flip_or_move it */ |
||
4104 | Serge | 9119 | if (is_crtc_connector_off(set)) { |
3746 | Serge | 9120 | config->mode_changed = true; |
9121 | } else if (set->crtc->fb != set->fb) { |
||
3031 | serge | 9122 | /* If we have no fb then treat it as a full mode set */ |
9123 | if (set->crtc->fb == NULL) { |
||
4104 | Serge | 9124 | struct intel_crtc *intel_crtc = |
9125 | to_intel_crtc(set->crtc); |
||
9126 | |||
9127 | if (intel_crtc->active && i915_fastboot) { |
||
9128 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
||
9129 | config->fb_changed = true; |
||
9130 | } else { |
||
9131 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
||
3031 | serge | 9132 | config->mode_changed = true; |
4104 | Serge | 9133 | } |
3031 | serge | 9134 | } else if (set->fb == NULL) { |
9135 | config->mode_changed = true; |
||
3746 | Serge | 9136 | } else if (set->fb->pixel_format != |
9137 | set->crtc->fb->pixel_format) { |
||
3031 | serge | 9138 | config->mode_changed = true; |
3746 | Serge | 9139 | } else { |
3031 | serge | 9140 | config->fb_changed = true; |
9141 | } |
||
3746 | Serge | 9142 | } |
3031 | serge | 9143 | |
9144 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
||
9145 | config->fb_changed = true; |
||
9146 | |||
9147 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
||
9148 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
||
9149 | drm_mode_debug_printmodeline(&set->crtc->mode); |
||
9150 | drm_mode_debug_printmodeline(set->mode); |
||
9151 | config->mode_changed = true; |
||
9152 | } |
||
4104 | Serge | 9153 | |
9154 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
||
9155 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
||
3031 | serge | 9156 | } |
9157 | |||
9158 | static int |
||
9159 | intel_modeset_stage_output_state(struct drm_device *dev, |
||
9160 | struct drm_mode_set *set, |
||
9161 | struct intel_set_config *config) |
||
9162 | { |
||
9163 | struct drm_crtc *new_crtc; |
||
9164 | struct intel_connector *connector; |
||
9165 | struct intel_encoder *encoder; |
||
4104 | Serge | 9166 | int ro; |
3031 | serge | 9167 | |
3480 | Serge | 9168 | /* The upper layers ensure that we either disable a crtc or have a list |
3031 | serge | 9169 | * of connectors. For paranoia, double-check this. */ |
9170 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
||
9171 | WARN_ON(set->fb && (set->num_connectors == 0)); |
||
9172 | |||
9173 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
9174 | base.head) { |
||
9175 | /* Otherwise traverse passed in connector list and get encoders |
||
9176 | * for them. */ |
||
9177 | for (ro = 0; ro < set->num_connectors; ro++) { |
||
9178 | if (set->connectors[ro] == &connector->base) { |
||
9179 | connector->new_encoder = connector->encoder; |
||
9180 | break; |
||
9181 | } |
||
9182 | } |
||
9183 | |||
9184 | /* If we disable the crtc, disable all its connectors. Also, if |
||
9185 | * the connector is on the changing crtc but not on the new |
||
9186 | * connector list, disable it. */ |
||
9187 | if ((!set->fb || ro == set->num_connectors) && |
||
9188 | connector->base.encoder && |
||
9189 | connector->base.encoder->crtc == set->crtc) { |
||
9190 | connector->new_encoder = NULL; |
||
9191 | |||
9192 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
||
9193 | connector->base.base.id, |
||
9194 | drm_get_connector_name(&connector->base)); |
||
9195 | } |
||
9196 | |||
9197 | |||
9198 | if (&connector->new_encoder->base != connector->base.encoder) { |
||
9199 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
||
9200 | config->mode_changed = true; |
||
9201 | } |
||
9202 | } |
||
9203 | /* connector->new_encoder is now updated for all connectors. */ |
||
9204 | |||
9205 | /* Update crtc of enabled connectors. */ |
||
9206 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
9207 | base.head) { |
||
9208 | if (!connector->new_encoder) |
||
9209 | continue; |
||
9210 | |||
9211 | new_crtc = connector->new_encoder->base.crtc; |
||
9212 | |||
9213 | for (ro = 0; ro < set->num_connectors; ro++) { |
||
9214 | if (set->connectors[ro] == &connector->base) |
||
9215 | new_crtc = set->crtc; |
||
9216 | } |
||
9217 | |||
9218 | /* Make sure the new CRTC will work with the encoder */ |
||
9219 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
||
9220 | new_crtc)) { |
||
9221 | return -EINVAL; |
||
9222 | } |
||
9223 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
||
9224 | |||
9225 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
||
9226 | connector->base.base.id, |
||
9227 | drm_get_connector_name(&connector->base), |
||
9228 | new_crtc->base.id); |
||
9229 | } |
||
9230 | |||
9231 | /* Check for any encoders that needs to be disabled. */ |
||
9232 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
9233 | base.head) { |
||
9234 | list_for_each_entry(connector, |
||
9235 | &dev->mode_config.connector_list, |
||
9236 | base.head) { |
||
9237 | if (connector->new_encoder == encoder) { |
||
9238 | WARN_ON(!connector->new_encoder->new_crtc); |
||
9239 | |||
9240 | goto next_encoder; |
||
9241 | } |
||
9242 | } |
||
9243 | encoder->new_crtc = NULL; |
||
9244 | next_encoder: |
||
9245 | /* Only now check for crtc changes so we don't miss encoders |
||
9246 | * that will be disabled. */ |
||
9247 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
||
9248 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
||
9249 | config->mode_changed = true; |
||
9250 | } |
||
9251 | } |
||
9252 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
||
9253 | |||
9254 | return 0; |
||
9255 | } |
||
9256 | |||
9257 | static int intel_crtc_set_config(struct drm_mode_set *set) |
||
9258 | { |
||
9259 | struct drm_device *dev; |
||
9260 | struct drm_mode_set save_set; |
||
9261 | struct intel_set_config *config; |
||
9262 | int ret; |
||
9263 | |||
9264 | BUG_ON(!set); |
||
9265 | BUG_ON(!set->crtc); |
||
9266 | BUG_ON(!set->crtc->helper_private); |
||
9267 | |||
3480 | Serge | 9268 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9269 | BUG_ON(!set->mode && set->fb); |
||
9270 | BUG_ON(set->fb && set->num_connectors == 0); |
||
3031 | serge | 9271 | |
9272 | if (set->fb) { |
||
9273 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
||
9274 | set->crtc->base.id, set->fb->base.id, |
||
9275 | (int)set->num_connectors, set->x, set->y); |
||
9276 | } else { |
||
9277 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
||
9278 | } |
||
9279 | |||
9280 | dev = set->crtc->dev; |
||
9281 | |||
9282 | ret = -ENOMEM; |
||
9283 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
||
9284 | if (!config) |
||
9285 | goto out_config; |
||
9286 | |||
9287 | ret = intel_set_config_save_state(dev, config); |
||
9288 | if (ret) |
||
9289 | goto out_config; |
||
9290 | |||
9291 | save_set.crtc = set->crtc; |
||
9292 | save_set.mode = &set->crtc->mode; |
||
9293 | save_set.x = set->crtc->x; |
||
9294 | save_set.y = set->crtc->y; |
||
9295 | save_set.fb = set->crtc->fb; |
||
9296 | |||
9297 | /* Compute whether we need a full modeset, only an fb base update or no |
||
9298 | * change at all. In the future we might also check whether only the |
||
9299 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
||
9300 | * such cases. */ |
||
9301 | intel_set_config_compute_mode_changes(set, config); |
||
9302 | |||
9303 | ret = intel_modeset_stage_output_state(dev, set, config); |
||
9304 | if (ret) |
||
9305 | goto fail; |
||
9306 | |||
9307 | if (config->mode_changed) { |
||
3480 | Serge | 9308 | ret = intel_set_mode(set->crtc, set->mode, |
9309 | set->x, set->y, set->fb); |
||
3031 | serge | 9310 | } else if (config->fb_changed) { |
3746 | Serge | 9311 | // intel_crtc_wait_for_pending_flips(set->crtc); |
9312 | |||
3031 | serge | 9313 | ret = intel_pipe_set_base(set->crtc, |
9314 | set->x, set->y, set->fb); |
||
9315 | } |
||
9316 | |||
3746 | Serge | 9317 | if (ret) { |
4104 | Serge | 9318 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
3746 | Serge | 9319 | set->crtc->base.id, ret); |
3031 | serge | 9320 | fail: |
9321 | intel_set_config_restore_state(dev, config); |
||
9322 | |||
9323 | /* Try to restore the config */ |
||
9324 | if (config->mode_changed && |
||
3480 | Serge | 9325 | intel_set_mode(save_set.crtc, save_set.mode, |
3031 | serge | 9326 | save_set.x, save_set.y, save_set.fb)) |
9327 | DRM_ERROR("failed to restore config after modeset failure\n"); |
||
3746 | Serge | 9328 | } |
3031 | serge | 9329 | |
9330 | out_config: |
||
9331 | intel_set_config_free(config); |
||
9332 | return ret; |
||
9333 | } |
||
9334 | |||
2330 | Serge | 9335 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
9336 | // .cursor_set = intel_crtc_cursor_set, |
||
9337 | // .cursor_move = intel_crtc_cursor_move, |
||
9338 | .gamma_set = intel_crtc_gamma_set, |
||
3031 | serge | 9339 | .set_config = intel_crtc_set_config, |
2330 | Serge | 9340 | .destroy = intel_crtc_destroy, |
9341 | // .page_flip = intel_crtc_page_flip, |
||
9342 | }; |
||
2327 | Serge | 9343 | |
3243 | Serge | 9344 | static void intel_cpu_pll_init(struct drm_device *dev) |
9345 | { |
||
3480 | Serge | 9346 | if (HAS_DDI(dev)) |
3243 | Serge | 9347 | intel_ddi_pll_init(dev); |
9348 | } |
||
9349 | |||
4104 | Serge | 9350 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9351 | struct intel_shared_dpll *pll, |
||
9352 | struct intel_dpll_hw_state *hw_state) |
||
3031 | serge | 9353 | { |
4104 | Serge | 9354 | uint32_t val; |
3031 | serge | 9355 | |
4104 | Serge | 9356 | val = I915_READ(PCH_DPLL(pll->id)); |
9357 | hw_state->dpll = val; |
||
9358 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
||
9359 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
||
9360 | |||
9361 | return val & DPLL_VCO_ENABLE; |
||
9362 | } |
||
9363 | |||
9364 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
||
9365 | struct intel_shared_dpll *pll) |
||
9366 | { |
||
9367 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
||
9368 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
||
9369 | } |
||
9370 | |||
9371 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
||
9372 | struct intel_shared_dpll *pll) |
||
9373 | { |
||
9374 | /* PCH refclock must be enabled first */ |
||
9375 | assert_pch_refclk_enabled(dev_priv); |
||
9376 | |||
9377 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
||
9378 | |||
9379 | /* Wait for the clocks to stabilize. */ |
||
9380 | POSTING_READ(PCH_DPLL(pll->id)); |
||
9381 | udelay(150); |
||
9382 | |||
9383 | /* The pixel multiplier can only be updated once the |
||
9384 | * DPLL is enabled and the clocks are stable. |
||
9385 | * |
||
9386 | * So write it again. |
||
9387 | */ |
||
9388 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
||
9389 | POSTING_READ(PCH_DPLL(pll->id)); |
||
9390 | udelay(200); |
||
9391 | } |
||
9392 | |||
9393 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
||
9394 | struct intel_shared_dpll *pll) |
||
9395 | { |
||
9396 | struct drm_device *dev = dev_priv->dev; |
||
9397 | struct intel_crtc *crtc; |
||
9398 | |||
9399 | /* Make sure no transcoder isn't still depending on us. */ |
||
9400 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
||
9401 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
||
9402 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
||
3031 | serge | 9403 | } |
9404 | |||
4104 | Serge | 9405 | I915_WRITE(PCH_DPLL(pll->id), 0); |
9406 | POSTING_READ(PCH_DPLL(pll->id)); |
||
9407 | udelay(200); |
||
9408 | } |
||
9409 | |||
9410 | static char *ibx_pch_dpll_names[] = { |
||
9411 | "PCH DPLL A", |
||
9412 | "PCH DPLL B", |
||
9413 | }; |
||
9414 | |||
9415 | static void ibx_pch_dpll_init(struct drm_device *dev) |
||
9416 | { |
||
9417 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
9418 | int i; |
||
9419 | |||
9420 | dev_priv->num_shared_dpll = 2; |
||
9421 | |||
9422 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
||
9423 | dev_priv->shared_dplls[i].id = i; |
||
9424 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
||
9425 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
||
9426 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
||
9427 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
||
9428 | dev_priv->shared_dplls[i].get_hw_state = |
||
9429 | ibx_pch_dpll_get_hw_state; |
||
3031 | serge | 9430 | } |
9431 | } |
||
9432 | |||
4104 | Serge | 9433 | static void intel_shared_dpll_init(struct drm_device *dev) |
9434 | { |
||
9435 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
9436 | |||
9437 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
||
9438 | ibx_pch_dpll_init(dev); |
||
9439 | else |
||
9440 | dev_priv->num_shared_dpll = 0; |
||
9441 | |||
9442 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
||
9443 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", |
||
9444 | dev_priv->num_shared_dpll); |
||
9445 | } |
||
9446 | |||
2330 | Serge | 9447 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
9448 | { |
||
9449 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
9450 | struct intel_crtc *intel_crtc; |
||
9451 | int i; |
||
2327 | Serge | 9452 | |
2330 | Serge | 9453 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
9454 | if (intel_crtc == NULL) |
||
9455 | return; |
||
2327 | Serge | 9456 | |
2330 | Serge | 9457 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
2327 | Serge | 9458 | |
2330 | Serge | 9459 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
9460 | for (i = 0; i < 256; i++) { |
||
9461 | intel_crtc->lut_r[i] = i; |
||
9462 | intel_crtc->lut_g[i] = i; |
||
9463 | intel_crtc->lut_b[i] = i; |
||
9464 | } |
||
2327 | Serge | 9465 | |
2330 | Serge | 9466 | /* Swap pipes & planes for FBC on pre-965 */ |
9467 | intel_crtc->pipe = pipe; |
||
9468 | intel_crtc->plane = pipe; |
||
9469 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
||
9470 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
||
9471 | intel_crtc->plane = !pipe; |
||
9472 | } |
||
2327 | Serge | 9473 | |
2330 | Serge | 9474 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
9475 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
||
9476 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
||
9477 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
||
2327 | Serge | 9478 | |
2330 | Serge | 9479 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
9480 | } |
||
2327 | Serge | 9481 | |
3031 | serge | 9482 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
9483 | struct drm_file *file) |
||
9484 | { |
||
9485 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
||
9486 | struct drm_mode_object *drmmode_obj; |
||
9487 | struct intel_crtc *crtc; |
||
2327 | Serge | 9488 | |
3482 | Serge | 9489 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
9490 | return -ENODEV; |
||
9491 | |||
3031 | serge | 9492 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9493 | DRM_MODE_OBJECT_CRTC); |
||
2327 | Serge | 9494 | |
3031 | serge | 9495 | if (!drmmode_obj) { |
9496 | DRM_ERROR("no such CRTC id\n"); |
||
9497 | return -EINVAL; |
||
9498 | } |
||
2327 | Serge | 9499 | |
3031 | serge | 9500 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
9501 | pipe_from_crtc_id->pipe = crtc->pipe; |
||
2327 | Serge | 9502 | |
3031 | serge | 9503 | return 0; |
9504 | } |
||
2327 | Serge | 9505 | |
3031 | serge | 9506 | static int intel_encoder_clones(struct intel_encoder *encoder) |
2330 | Serge | 9507 | { |
3031 | serge | 9508 | struct drm_device *dev = encoder->base.dev; |
9509 | struct intel_encoder *source_encoder; |
||
2330 | Serge | 9510 | int index_mask = 0; |
9511 | int entry = 0; |
||
2327 | Serge | 9512 | |
3031 | serge | 9513 | list_for_each_entry(source_encoder, |
9514 | &dev->mode_config.encoder_list, base.head) { |
||
9515 | |||
9516 | if (encoder == source_encoder) |
||
2330 | Serge | 9517 | index_mask |= (1 << entry); |
3031 | serge | 9518 | |
9519 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
||
9520 | if (encoder->cloneable && source_encoder->cloneable) |
||
9521 | index_mask |= (1 << entry); |
||
9522 | |||
2330 | Serge | 9523 | entry++; |
9524 | } |
||
2327 | Serge | 9525 | |
2330 | Serge | 9526 | return index_mask; |
9527 | } |
||
2327 | Serge | 9528 | |
2330 | Serge | 9529 | static bool has_edp_a(struct drm_device *dev) |
9530 | { |
||
9531 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 9532 | |
2330 | Serge | 9533 | if (!IS_MOBILE(dev)) |
9534 | return false; |
||
2327 | Serge | 9535 | |
2330 | Serge | 9536 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
9537 | return false; |
||
2327 | Serge | 9538 | |
2330 | Serge | 9539 | if (IS_GEN5(dev) && |
9540 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
||
9541 | return false; |
||
2327 | Serge | 9542 | |
2330 | Serge | 9543 | return true; |
9544 | } |
||
2327 | Serge | 9545 | |
2330 | Serge | 9546 | static void intel_setup_outputs(struct drm_device *dev) |
9547 | { |
||
9548 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
9549 | struct intel_encoder *encoder; |
||
9550 | bool dpd_is_edp = false; |
||
2327 | Serge | 9551 | |
4104 | Serge | 9552 | intel_lvds_init(dev); |
2327 | Serge | 9553 | |
3746 | Serge | 9554 | if (!IS_ULT(dev)) |
2330 | Serge | 9555 | intel_crt_init(dev); |
2327 | Serge | 9556 | |
3480 | Serge | 9557 | if (HAS_DDI(dev)) { |
2330 | Serge | 9558 | int found; |
2327 | Serge | 9559 | |
3031 | serge | 9560 | /* Haswell uses DDI functions to detect digital outputs */ |
9561 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
||
9562 | /* DDI A only supports eDP */ |
||
9563 | if (found) |
||
9564 | intel_ddi_init(dev, PORT_A); |
||
9565 | |||
9566 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
||
9567 | * register */ |
||
9568 | found = I915_READ(SFUSE_STRAP); |
||
9569 | |||
9570 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
||
9571 | intel_ddi_init(dev, PORT_B); |
||
9572 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
||
9573 | intel_ddi_init(dev, PORT_C); |
||
9574 | if (found & SFUSE_STRAP_DDID_DETECTED) |
||
9575 | intel_ddi_init(dev, PORT_D); |
||
9576 | } else if (HAS_PCH_SPLIT(dev)) { |
||
9577 | int found; |
||
3243 | Serge | 9578 | dpd_is_edp = intel_dpd_is_edp(dev); |
3031 | serge | 9579 | |
3243 | Serge | 9580 | if (has_edp_a(dev)) |
9581 | intel_dp_init(dev, DP_A, PORT_A); |
||
9582 | |||
3746 | Serge | 9583 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
2330 | Serge | 9584 | /* PCH SDVOB multiplex with HDMIB */ |
3031 | serge | 9585 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
2330 | Serge | 9586 | if (!found) |
3746 | Serge | 9587 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
2330 | Serge | 9588 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
3031 | serge | 9589 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
2330 | Serge | 9590 | } |
2327 | Serge | 9591 | |
3746 | Serge | 9592 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
9593 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
||
2327 | Serge | 9594 | |
3746 | Serge | 9595 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
9596 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
||
2327 | Serge | 9597 | |
2330 | Serge | 9598 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
3031 | serge | 9599 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
2327 | Serge | 9600 | |
3243 | Serge | 9601 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
3031 | serge | 9602 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
9603 | } else if (IS_VALLEYVIEW(dev)) { |
||
3243 | Serge | 9604 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
4104 | Serge | 9605 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
9606 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
||
9607 | PORT_C); |
||
3480 | Serge | 9608 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
4104 | Serge | 9609 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, |
9610 | PORT_C); |
||
9611 | } |
||
3243 | Serge | 9612 | |
3746 | Serge | 9613 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
9614 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
||
9615 | PORT_B); |
||
3480 | Serge | 9616 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9617 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
||
3031 | serge | 9618 | } |
2330 | Serge | 9619 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
9620 | bool found = false; |
||
2327 | Serge | 9621 | |
3746 | Serge | 9622 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
2330 | Serge | 9623 | DRM_DEBUG_KMS("probing SDVOB\n"); |
3746 | Serge | 9624 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
2330 | Serge | 9625 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
9626 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
||
3746 | Serge | 9627 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
2330 | Serge | 9628 | } |
2327 | Serge | 9629 | |
4104 | Serge | 9630 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
3031 | serge | 9631 | intel_dp_init(dev, DP_B, PORT_B); |
2330 | Serge | 9632 | } |
2327 | Serge | 9633 | |
2330 | Serge | 9634 | /* Before G4X SDVOC doesn't have its own detect register */ |
2327 | Serge | 9635 | |
3746 | Serge | 9636 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
2330 | Serge | 9637 | DRM_DEBUG_KMS("probing SDVOC\n"); |
3746 | Serge | 9638 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
2330 | Serge | 9639 | } |
2327 | Serge | 9640 | |
3746 | Serge | 9641 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
2327 | Serge | 9642 | |
2330 | Serge | 9643 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
9644 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
||
3746 | Serge | 9645 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
2330 | Serge | 9646 | } |
4104 | Serge | 9647 | if (SUPPORTS_INTEGRATED_DP(dev)) |
3031 | serge | 9648 | intel_dp_init(dev, DP_C, PORT_C); |
2330 | Serge | 9649 | } |
2327 | Serge | 9650 | |
2330 | Serge | 9651 | if (SUPPORTS_INTEGRATED_DP(dev) && |
4104 | Serge | 9652 | (I915_READ(DP_D) & DP_DETECTED)) |
3031 | serge | 9653 | intel_dp_init(dev, DP_D, PORT_D); |
2330 | Serge | 9654 | } else if (IS_GEN2(dev)) |
9655 | intel_dvo_init(dev); |
||
2327 | Serge | 9656 | |
2330 | Serge | 9657 | // if (SUPPORTS_TV(dev)) |
9658 | // intel_tv_init(dev); |
||
2327 | Serge | 9659 | |
2330 | Serge | 9660 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9661 | encoder->base.possible_crtcs = encoder->crtc_mask; |
||
9662 | encoder->base.possible_clones = |
||
3031 | serge | 9663 | intel_encoder_clones(encoder); |
2330 | Serge | 9664 | } |
2327 | Serge | 9665 | |
3243 | Serge | 9666 | intel_init_pch_refclk(dev); |
9667 | |||
9668 | drm_helper_move_panel_connectors_to_head(dev); |
||
2330 | Serge | 9669 | } |
9670 | |||
9671 | |||
9672 | |||
2335 | Serge | 9673 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
9674 | // .destroy = intel_user_framebuffer_destroy, |
||
9675 | // .create_handle = intel_user_framebuffer_create_handle, |
||
9676 | }; |
||
2327 | Serge | 9677 | |
2335 | Serge | 9678 | int intel_framebuffer_init(struct drm_device *dev, |
9679 | struct intel_framebuffer *intel_fb, |
||
2342 | Serge | 9680 | struct drm_mode_fb_cmd2 *mode_cmd, |
2335 | Serge | 9681 | struct drm_i915_gem_object *obj) |
9682 | { |
||
4104 | Serge | 9683 | int pitch_limit; |
2335 | Serge | 9684 | int ret; |
2327 | Serge | 9685 | |
3243 | Serge | 9686 | if (obj->tiling_mode == I915_TILING_Y) { |
9687 | DRM_DEBUG("hardware does not support tiling Y\n"); |
||
2335 | Serge | 9688 | return -EINVAL; |
3243 | Serge | 9689 | } |
2327 | Serge | 9690 | |
3243 | Serge | 9691 | if (mode_cmd->pitches[0] & 63) { |
9692 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
||
9693 | mode_cmd->pitches[0]); |
||
9694 | return -EINVAL; |
||
9695 | } |
||
9696 | |||
4104 | Serge | 9697 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
9698 | pitch_limit = 32*1024; |
||
9699 | } else if (INTEL_INFO(dev)->gen >= 4) { |
||
9700 | if (obj->tiling_mode) |
||
9701 | pitch_limit = 16*1024; |
||
9702 | else |
||
9703 | pitch_limit = 32*1024; |
||
9704 | } else if (INTEL_INFO(dev)->gen >= 3) { |
||
9705 | if (obj->tiling_mode) |
||
9706 | pitch_limit = 8*1024; |
||
9707 | else |
||
9708 | pitch_limit = 16*1024; |
||
9709 | } else |
||
9710 | /* XXX DSPC is limited to 4k tiled */ |
||
9711 | pitch_limit = 8*1024; |
||
9712 | |||
9713 | if (mode_cmd->pitches[0] > pitch_limit) { |
||
9714 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
||
9715 | obj->tiling_mode ? "tiled" : "linear", |
||
9716 | mode_cmd->pitches[0], pitch_limit); |
||
3243 | Serge | 9717 | return -EINVAL; |
9718 | } |
||
9719 | |||
9720 | if (obj->tiling_mode != I915_TILING_NONE && |
||
9721 | mode_cmd->pitches[0] != obj->stride) { |
||
9722 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
||
9723 | mode_cmd->pitches[0], obj->stride); |
||
2335 | Serge | 9724 | return -EINVAL; |
3243 | Serge | 9725 | } |
2327 | Serge | 9726 | |
3243 | Serge | 9727 | /* Reject formats not supported by any plane early. */ |
2342 | Serge | 9728 | switch (mode_cmd->pixel_format) { |
3243 | Serge | 9729 | case DRM_FORMAT_C8: |
2342 | Serge | 9730 | case DRM_FORMAT_RGB565: |
9731 | case DRM_FORMAT_XRGB8888: |
||
3243 | Serge | 9732 | case DRM_FORMAT_ARGB8888: |
9733 | break; |
||
9734 | case DRM_FORMAT_XRGB1555: |
||
9735 | case DRM_FORMAT_ARGB1555: |
||
9736 | if (INTEL_INFO(dev)->gen > 3) { |
||
4104 | Serge | 9737 | DRM_DEBUG("unsupported pixel format: %s\n", |
9738 | drm_get_format_name(mode_cmd->pixel_format)); |
||
3243 | Serge | 9739 | return -EINVAL; |
9740 | } |
||
9741 | break; |
||
3031 | serge | 9742 | case DRM_FORMAT_XBGR8888: |
3243 | Serge | 9743 | case DRM_FORMAT_ABGR8888: |
2342 | Serge | 9744 | case DRM_FORMAT_XRGB2101010: |
9745 | case DRM_FORMAT_ARGB2101010: |
||
3243 | Serge | 9746 | case DRM_FORMAT_XBGR2101010: |
9747 | case DRM_FORMAT_ABGR2101010: |
||
9748 | if (INTEL_INFO(dev)->gen < 4) { |
||
4104 | Serge | 9749 | DRM_DEBUG("unsupported pixel format: %s\n", |
9750 | drm_get_format_name(mode_cmd->pixel_format)); |
||
3243 | Serge | 9751 | return -EINVAL; |
9752 | } |
||
2335 | Serge | 9753 | break; |
2342 | Serge | 9754 | case DRM_FORMAT_YUYV: |
9755 | case DRM_FORMAT_UYVY: |
||
9756 | case DRM_FORMAT_YVYU: |
||
9757 | case DRM_FORMAT_VYUY: |
||
3243 | Serge | 9758 | if (INTEL_INFO(dev)->gen < 5) { |
4104 | Serge | 9759 | DRM_DEBUG("unsupported pixel format: %s\n", |
9760 | drm_get_format_name(mode_cmd->pixel_format)); |
||
3243 | Serge | 9761 | return -EINVAL; |
9762 | } |
||
2342 | Serge | 9763 | break; |
2335 | Serge | 9764 | default: |
4104 | Serge | 9765 | DRM_DEBUG("unsupported pixel format: %s\n", |
9766 | drm_get_format_name(mode_cmd->pixel_format)); |
||
2335 | Serge | 9767 | return -EINVAL; |
9768 | } |
||
2327 | Serge | 9769 | |
3243 | Serge | 9770 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
9771 | if (mode_cmd->offsets[0] != 0) |
||
9772 | return -EINVAL; |
||
9773 | |||
3480 | Serge | 9774 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
9775 | intel_fb->obj = obj; |
||
9776 | |||
2335 | Serge | 9777 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
9778 | if (ret) { |
||
9779 | DRM_ERROR("framebuffer init failed %d\n", ret); |
||
9780 | return ret; |
||
9781 | } |
||
2327 | Serge | 9782 | |
2335 | Serge | 9783 | return 0; |
9784 | } |
||
2327 | Serge | 9785 | |
9786 | |||
2360 | Serge | 9787 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
9788 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
||
3480 | Serge | 9789 | .output_poll_changed = intel_fb_output_poll_changed, |
2360 | Serge | 9790 | }; |
2327 | Serge | 9791 | |
3031 | serge | 9792 | /* Set up chip specific display functions */ |
9793 | static void intel_init_display(struct drm_device *dev) |
||
9794 | { |
||
9795 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 9796 | |
4104 | Serge | 9797 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
9798 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
||
9799 | else if (IS_VALLEYVIEW(dev)) |
||
9800 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
||
9801 | else if (IS_PINEVIEW(dev)) |
||
9802 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
||
9803 | else |
||
9804 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
||
9805 | |||
3480 | Serge | 9806 | if (HAS_DDI(dev)) { |
3746 | Serge | 9807 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
3243 | Serge | 9808 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
9809 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
||
9810 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
||
9811 | dev_priv->display.off = haswell_crtc_off; |
||
9812 | dev_priv->display.update_plane = ironlake_update_plane; |
||
9813 | } else if (HAS_PCH_SPLIT(dev)) { |
||
3746 | Serge | 9814 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4104 | Serge | 9815 | dev_priv->display.get_clock = ironlake_crtc_clock_get; |
3031 | serge | 9816 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
9817 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
||
9818 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
||
9819 | dev_priv->display.off = ironlake_crtc_off; |
||
9820 | dev_priv->display.update_plane = ironlake_update_plane; |
||
4104 | Serge | 9821 | } else if (IS_VALLEYVIEW(dev)) { |
9822 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
||
4398 | Serge | 9823 | dev_priv->display.get_clock = vlv_crtc_clock_get; |
4104 | Serge | 9824 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9825 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
||
9826 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
||
9827 | dev_priv->display.off = i9xx_crtc_off; |
||
9828 | dev_priv->display.update_plane = i9xx_update_plane; |
||
3031 | serge | 9829 | } else { |
3746 | Serge | 9830 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
4104 | Serge | 9831 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
3031 | serge | 9832 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9833 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
||
9834 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
||
9835 | dev_priv->display.off = i9xx_crtc_off; |
||
9836 | dev_priv->display.update_plane = i9xx_update_plane; |
||
9837 | } |
||
2327 | Serge | 9838 | |
3031 | serge | 9839 | /* Returns the core display clock speed */ |
9840 | if (IS_VALLEYVIEW(dev)) |
||
9841 | dev_priv->display.get_display_clock_speed = |
||
9842 | valleyview_get_display_clock_speed; |
||
9843 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
||
9844 | dev_priv->display.get_display_clock_speed = |
||
9845 | i945_get_display_clock_speed; |
||
9846 | else if (IS_I915G(dev)) |
||
9847 | dev_priv->display.get_display_clock_speed = |
||
9848 | i915_get_display_clock_speed; |
||
4104 | Serge | 9849 | else if (IS_I945GM(dev) || IS_845G(dev)) |
3031 | serge | 9850 | dev_priv->display.get_display_clock_speed = |
9851 | i9xx_misc_get_display_clock_speed; |
||
4104 | Serge | 9852 | else if (IS_PINEVIEW(dev)) |
9853 | dev_priv->display.get_display_clock_speed = |
||
9854 | pnv_get_display_clock_speed; |
||
3031 | serge | 9855 | else if (IS_I915GM(dev)) |
9856 | dev_priv->display.get_display_clock_speed = |
||
9857 | i915gm_get_display_clock_speed; |
||
9858 | else if (IS_I865G(dev)) |
||
9859 | dev_priv->display.get_display_clock_speed = |
||
9860 | i865_get_display_clock_speed; |
||
9861 | else if (IS_I85X(dev)) |
||
9862 | dev_priv->display.get_display_clock_speed = |
||
9863 | i855_get_display_clock_speed; |
||
9864 | else /* 852, 830 */ |
||
9865 | dev_priv->display.get_display_clock_speed = |
||
9866 | i830_get_display_clock_speed; |
||
2327 | Serge | 9867 | |
3031 | serge | 9868 | if (HAS_PCH_SPLIT(dev)) { |
9869 | if (IS_GEN5(dev)) { |
||
9870 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
||
9871 | dev_priv->display.write_eld = ironlake_write_eld; |
||
9872 | } else if (IS_GEN6(dev)) { |
||
9873 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
||
9874 | dev_priv->display.write_eld = ironlake_write_eld; |
||
9875 | } else if (IS_IVYBRIDGE(dev)) { |
||
9876 | /* FIXME: detect B0+ stepping and use auto training */ |
||
9877 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
||
9878 | dev_priv->display.write_eld = ironlake_write_eld; |
||
3243 | Serge | 9879 | dev_priv->display.modeset_global_resources = |
9880 | ivb_modeset_global_resources; |
||
3031 | serge | 9881 | } else if (IS_HASWELL(dev)) { |
9882 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
||
9883 | dev_priv->display.write_eld = haswell_write_eld; |
||
3480 | Serge | 9884 | dev_priv->display.modeset_global_resources = |
9885 | haswell_modeset_global_resources; |
||
9886 | } |
||
3031 | serge | 9887 | } else if (IS_G4X(dev)) { |
9888 | dev_priv->display.write_eld = g4x_write_eld; |
||
9889 | } |
||
2327 | Serge | 9890 | |
3031 | serge | 9891 | /* Default just returns -ENODEV to indicate unsupported */ |
9892 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
||
2327 | Serge | 9893 | |
9894 | |||
9895 | |||
9896 | |||
3031 | serge | 9897 | } |
9898 | |||
9899 | /* |
||
9900 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
||
9901 | * resume, or other times. This quirk makes sure that's the case for |
||
9902 | * affected systems. |
||
9903 | */ |
||
9904 | static void quirk_pipea_force(struct drm_device *dev) |
||
2330 | Serge | 9905 | { |
9906 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 9907 | |
3031 | serge | 9908 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
9909 | DRM_INFO("applying pipe a force quirk\n"); |
||
9910 | } |
||
2327 | Serge | 9911 | |
3031 | serge | 9912 | /* |
9913 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
||
9914 | */ |
||
9915 | static void quirk_ssc_force_disable(struct drm_device *dev) |
||
9916 | { |
||
9917 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
9918 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
||
9919 | DRM_INFO("applying lvds SSC disable quirk\n"); |
||
2330 | Serge | 9920 | } |
2327 | Serge | 9921 | |
3031 | serge | 9922 | /* |
9923 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
||
9924 | * brightness value |
||
9925 | */ |
||
9926 | static void quirk_invert_brightness(struct drm_device *dev) |
||
2330 | Serge | 9927 | { |
9928 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 9929 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
9930 | DRM_INFO("applying inverted panel brightness quirk\n"); |
||
9931 | } |
||
2327 | Serge | 9932 | |
4104 | Serge | 9933 | /* |
9934 | * Some machines (Dell XPS13) suffer broken backlight controls if |
||
9935 | * BLM_PCH_PWM_ENABLE is set. |
||
9936 | */ |
||
9937 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) |
||
9938 | { |
||
9939 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
9940 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; |
||
9941 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); |
||
9942 | } |
||
9943 | |||
3031 | serge | 9944 | struct intel_quirk { |
9945 | int device; |
||
9946 | int subsystem_vendor; |
||
9947 | int subsystem_device; |
||
9948 | void (*hook)(struct drm_device *dev); |
||
9949 | }; |
||
2327 | Serge | 9950 | |
3031 | serge | 9951 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
9952 | struct intel_dmi_quirk { |
||
9953 | void (*hook)(struct drm_device *dev); |
||
9954 | const struct dmi_system_id (*dmi_id_list)[]; |
||
9955 | }; |
||
2327 | Serge | 9956 | |
3031 | serge | 9957 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
9958 | { |
||
9959 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
||
9960 | return 1; |
||
2330 | Serge | 9961 | } |
2327 | Serge | 9962 | |
3031 | serge | 9963 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
9964 | { |
||
9965 | .dmi_id_list = &(const struct dmi_system_id[]) { |
||
9966 | { |
||
9967 | .callback = intel_dmi_reverse_brightness, |
||
9968 | .ident = "NCR Corporation", |
||
9969 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
||
9970 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
||
9971 | }, |
||
9972 | }, |
||
9973 | { } /* terminating entry */ |
||
9974 | }, |
||
9975 | .hook = quirk_invert_brightness, |
||
9976 | }, |
||
9977 | }; |
||
2327 | Serge | 9978 | |
3031 | serge | 9979 | static struct intel_quirk intel_quirks[] = { |
9980 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
||
9981 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
||
2327 | Serge | 9982 | |
3031 | serge | 9983 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
9984 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
||
2327 | Serge | 9985 | |
3031 | serge | 9986 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
9987 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
||
2327 | Serge | 9988 | |
3031 | serge | 9989 | /* 830/845 need to leave pipe A & dpll A up */ |
9990 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
||
9991 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
||
2327 | Serge | 9992 | |
3031 | serge | 9993 | /* Lenovo U160 cannot use SSC on LVDS */ |
9994 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
||
2327 | Serge | 9995 | |
3031 | serge | 9996 | /* Sony Vaio Y cannot use SSC on LVDS */ |
9997 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
||
2327 | Serge | 9998 | |
3031 | serge | 9999 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10000 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
||
3480 | Serge | 10001 | |
10002 | /* Acer/eMachines G725 */ |
||
10003 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
||
10004 | |||
10005 | /* Acer/eMachines e725 */ |
||
10006 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
||
10007 | |||
10008 | /* Acer/Packard Bell NCL20 */ |
||
10009 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
||
10010 | |||
10011 | /* Acer Aspire 4736Z */ |
||
10012 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
||
4104 | Serge | 10013 | |
10014 | /* Dell XPS13 HD Sandy Bridge */ |
||
10015 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, |
||
10016 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ |
||
10017 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, |
||
3031 | serge | 10018 | }; |
2327 | Serge | 10019 | |
3031 | serge | 10020 | static void intel_init_quirks(struct drm_device *dev) |
2330 | Serge | 10021 | { |
3031 | serge | 10022 | struct pci_dev *d = dev->pdev; |
10023 | int i; |
||
2327 | Serge | 10024 | |
3031 | serge | 10025 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
10026 | struct intel_quirk *q = &intel_quirks[i]; |
||
2327 | Serge | 10027 | |
3031 | serge | 10028 | if (d->device == q->device && |
10029 | (d->subsystem_vendor == q->subsystem_vendor || |
||
10030 | q->subsystem_vendor == PCI_ANY_ID) && |
||
10031 | (d->subsystem_device == q->subsystem_device || |
||
10032 | q->subsystem_device == PCI_ANY_ID)) |
||
10033 | q->hook(dev); |
||
10034 | } |
||
2330 | Serge | 10035 | } |
2327 | Serge | 10036 | |
3031 | serge | 10037 | /* Disable the VGA plane that we never use */ |
10038 | static void i915_disable_vga(struct drm_device *dev) |
||
2330 | Serge | 10039 | { |
10040 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 10041 | u8 sr1; |
3480 | Serge | 10042 | u32 vga_reg = i915_vgacntrl_reg(dev); |
2327 | Serge | 10043 | |
3031 | serge | 10044 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
10045 | out8(SR01, VGA_SR_INDEX); |
||
10046 | sr1 = in8(VGA_SR_DATA); |
||
10047 | out8(sr1 | 1<<5, VGA_SR_DATA); |
||
10048 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
||
10049 | udelay(300); |
||
2327 | Serge | 10050 | |
3031 | serge | 10051 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
10052 | POSTING_READ(vga_reg); |
||
2330 | Serge | 10053 | } |
10054 | |||
3031 | serge | 10055 | void intel_modeset_init_hw(struct drm_device *dev) |
2342 | Serge | 10056 | { |
4398 | Serge | 10057 | struct drm_i915_private *dev_priv = dev->dev_private; |
10058 | |||
3480 | Serge | 10059 | intel_init_power_well(dev); |
2342 | Serge | 10060 | |
3031 | serge | 10061 | intel_prepare_ddi(dev); |
2342 | Serge | 10062 | |
3031 | serge | 10063 | intel_init_clock_gating(dev); |
10064 | |||
4398 | Serge | 10065 | /* Enable the CRI clock source so we can get at the display */ |
10066 | if (IS_VALLEYVIEW(dev)) |
||
10067 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
||
10068 | DPLL_INTEGRATED_CRI_CLK_VLV); |
||
10069 | |||
3482 | Serge | 10070 | mutex_lock(&dev->struct_mutex); |
10071 | intel_enable_gt_powersave(dev); |
||
10072 | mutex_unlock(&dev->struct_mutex); |
||
2342 | Serge | 10073 | } |
10074 | |||
4398 | Serge | 10075 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10076 | { |
||
10077 | intel_suspend_hw(dev); |
||
10078 | } |
||
10079 | |||
3031 | serge | 10080 | void intel_modeset_init(struct drm_device *dev) |
2330 | Serge | 10081 | { |
3031 | serge | 10082 | struct drm_i915_private *dev_priv = dev->dev_private; |
3746 | Serge | 10083 | int i, j, ret; |
2330 | Serge | 10084 | |
3031 | serge | 10085 | drm_mode_config_init(dev); |
2330 | Serge | 10086 | |
3031 | serge | 10087 | dev->mode_config.min_width = 0; |
10088 | dev->mode_config.min_height = 0; |
||
2330 | Serge | 10089 | |
3031 | serge | 10090 | dev->mode_config.preferred_depth = 24; |
10091 | dev->mode_config.prefer_shadow = 1; |
||
2330 | Serge | 10092 | |
3031 | serge | 10093 | dev->mode_config.funcs = &intel_mode_funcs; |
2330 | Serge | 10094 | |
3031 | serge | 10095 | intel_init_quirks(dev); |
2330 | Serge | 10096 | |
3031 | serge | 10097 | intel_init_pm(dev); |
2330 | Serge | 10098 | |
3746 | Serge | 10099 | if (INTEL_INFO(dev)->num_pipes == 0) |
10100 | return; |
||
10101 | |||
3031 | serge | 10102 | intel_init_display(dev); |
2330 | Serge | 10103 | |
3031 | serge | 10104 | if (IS_GEN2(dev)) { |
10105 | dev->mode_config.max_width = 2048; |
||
10106 | dev->mode_config.max_height = 2048; |
||
10107 | } else if (IS_GEN3(dev)) { |
||
10108 | dev->mode_config.max_width = 4096; |
||
10109 | dev->mode_config.max_height = 4096; |
||
10110 | } else { |
||
10111 | dev->mode_config.max_width = 8192; |
||
10112 | dev->mode_config.max_height = 8192; |
||
10113 | } |
||
3480 | Serge | 10114 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
2330 | Serge | 10115 | |
3031 | serge | 10116 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
3746 | Serge | 10117 | INTEL_INFO(dev)->num_pipes, |
10118 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
||
2330 | Serge | 10119 | |
4104 | Serge | 10120 | for_each_pipe(i) { |
3031 | serge | 10121 | intel_crtc_init(dev, i); |
3746 | Serge | 10122 | for (j = 0; j < dev_priv->num_plane; j++) { |
10123 | ret = intel_plane_init(dev, i, j); |
||
3031 | serge | 10124 | if (ret) |
4104 | Serge | 10125 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10126 | pipe_name(i), sprite_name(i, j), ret); |
||
3746 | Serge | 10127 | } |
2330 | Serge | 10128 | } |
10129 | |||
3243 | Serge | 10130 | intel_cpu_pll_init(dev); |
4104 | Serge | 10131 | intel_shared_dpll_init(dev); |
2330 | Serge | 10132 | |
3031 | serge | 10133 | /* Just disable it once at startup */ |
10134 | i915_disable_vga(dev); |
||
10135 | intel_setup_outputs(dev); |
||
3480 | Serge | 10136 | |
10137 | /* Just in case the BIOS is doing something questionable. */ |
||
10138 | intel_disable_fbc(dev); |
||
3031 | serge | 10139 | } |
2330 | Serge | 10140 | |
3031 | serge | 10141 | static void |
10142 | intel_connector_break_all_links(struct intel_connector *connector) |
||
10143 | { |
||
10144 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
||
10145 | connector->base.encoder = NULL; |
||
10146 | connector->encoder->connectors_active = false; |
||
10147 | connector->encoder->base.crtc = NULL; |
||
2330 | Serge | 10148 | } |
10149 | |||
3031 | serge | 10150 | static void intel_enable_pipe_a(struct drm_device *dev) |
2330 | Serge | 10151 | { |
3031 | serge | 10152 | struct intel_connector *connector; |
10153 | struct drm_connector *crt = NULL; |
||
10154 | struct intel_load_detect_pipe load_detect_temp; |
||
2330 | Serge | 10155 | |
3031 | serge | 10156 | /* We can't just switch on the pipe A, we need to set things up with a |
10157 | * proper mode and output configuration. As a gross hack, enable pipe A |
||
10158 | * by enabling the load detect pipe once. */ |
||
10159 | list_for_each_entry(connector, |
||
10160 | &dev->mode_config.connector_list, |
||
10161 | base.head) { |
||
10162 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
||
10163 | crt = &connector->base; |
||
10164 | break; |
||
2330 | Serge | 10165 | } |
10166 | } |
||
10167 | |||
3031 | serge | 10168 | if (!crt) |
10169 | return; |
||
2330 | Serge | 10170 | |
3031 | serge | 10171 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
10172 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
||
2327 | Serge | 10173 | |
10174 | |||
10175 | } |
||
10176 | |||
3031 | serge | 10177 | static bool |
10178 | intel_check_plane_mapping(struct intel_crtc *crtc) |
||
2327 | Serge | 10179 | { |
3746 | Serge | 10180 | struct drm_device *dev = crtc->base.dev; |
10181 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 10182 | u32 reg, val; |
2327 | Serge | 10183 | |
3746 | Serge | 10184 | if (INTEL_INFO(dev)->num_pipes == 1) |
3031 | serge | 10185 | return true; |
2327 | Serge | 10186 | |
3031 | serge | 10187 | reg = DSPCNTR(!crtc->plane); |
10188 | val = I915_READ(reg); |
||
2327 | Serge | 10189 | |
3031 | serge | 10190 | if ((val & DISPLAY_PLANE_ENABLE) && |
10191 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
||
10192 | return false; |
||
2327 | Serge | 10193 | |
3031 | serge | 10194 | return true; |
2327 | Serge | 10195 | } |
10196 | |||
3031 | serge | 10197 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
2327 | Serge | 10198 | { |
3031 | serge | 10199 | struct drm_device *dev = crtc->base.dev; |
2327 | Serge | 10200 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 10201 | u32 reg; |
2327 | Serge | 10202 | |
3031 | serge | 10203 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3746 | Serge | 10204 | reg = PIPECONF(crtc->config.cpu_transcoder); |
3031 | serge | 10205 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
2327 | Serge | 10206 | |
3031 | serge | 10207 | /* We need to sanitize the plane -> pipe mapping first because this will |
10208 | * disable the crtc (and hence change the state) if it is wrong. Note |
||
10209 | * that gen4+ has a fixed plane -> pipe mapping. */ |
||
10210 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
||
10211 | struct intel_connector *connector; |
||
10212 | bool plane; |
||
2327 | Serge | 10213 | |
3031 | serge | 10214 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10215 | crtc->base.base.id); |
||
2327 | Serge | 10216 | |
3031 | serge | 10217 | /* Pipe has the wrong plane attached and the plane is active. |
10218 | * Temporarily change the plane mapping and disable everything |
||
10219 | * ... */ |
||
10220 | plane = crtc->plane; |
||
10221 | crtc->plane = !plane; |
||
10222 | dev_priv->display.crtc_disable(&crtc->base); |
||
10223 | crtc->plane = plane; |
||
2342 | Serge | 10224 | |
3031 | serge | 10225 | /* ... and break all links. */ |
10226 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
10227 | base.head) { |
||
10228 | if (connector->encoder->base.crtc != &crtc->base) |
||
10229 | continue; |
||
2327 | Serge | 10230 | |
3031 | serge | 10231 | intel_connector_break_all_links(connector); |
10232 | } |
||
2327 | Serge | 10233 | |
3031 | serge | 10234 | WARN_ON(crtc->active); |
10235 | crtc->base.enabled = false; |
||
10236 | } |
||
2327 | Serge | 10237 | |
3031 | serge | 10238 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10239 | crtc->pipe == PIPE_A && !crtc->active) { |
||
10240 | /* BIOS forgot to enable pipe A, this mostly happens after |
||
10241 | * resume. Force-enable the pipe to fix this, the update_dpms |
||
10242 | * call below we restore the pipe to the right state, but leave |
||
10243 | * the required bits on. */ |
||
10244 | intel_enable_pipe_a(dev); |
||
10245 | } |
||
2327 | Serge | 10246 | |
3031 | serge | 10247 | /* Adjust the state of the output pipe according to whether we |
10248 | * have active connectors/encoders. */ |
||
10249 | intel_crtc_update_dpms(&crtc->base); |
||
2327 | Serge | 10250 | |
3031 | serge | 10251 | if (crtc->active != crtc->base.enabled) { |
10252 | struct intel_encoder *encoder; |
||
2327 | Serge | 10253 | |
3031 | serge | 10254 | /* This can happen either due to bugs in the get_hw_state |
10255 | * functions or because the pipe is force-enabled due to the |
||
10256 | * pipe A quirk. */ |
||
10257 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
||
10258 | crtc->base.base.id, |
||
10259 | crtc->base.enabled ? "enabled" : "disabled", |
||
10260 | crtc->active ? "enabled" : "disabled"); |
||
2327 | Serge | 10261 | |
3031 | serge | 10262 | crtc->base.enabled = crtc->active; |
2327 | Serge | 10263 | |
3031 | serge | 10264 | /* Because we only establish the connector -> encoder -> |
10265 | * crtc links if something is active, this means the |
||
10266 | * crtc is now deactivated. Break the links. connector |
||
10267 | * -> encoder links are only establish when things are |
||
10268 | * actually up, hence no need to break them. */ |
||
10269 | WARN_ON(crtc->active); |
||
2327 | Serge | 10270 | |
3031 | serge | 10271 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
10272 | WARN_ON(encoder->connectors_active); |
||
10273 | encoder->base.crtc = NULL; |
||
10274 | } |
||
10275 | } |
||
2327 | Serge | 10276 | } |
10277 | |||
3031 | serge | 10278 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
2327 | Serge | 10279 | { |
3031 | serge | 10280 | struct intel_connector *connector; |
10281 | struct drm_device *dev = encoder->base.dev; |
||
2327 | Serge | 10282 | |
3031 | serge | 10283 | /* We need to check both for a crtc link (meaning that the |
10284 | * encoder is active and trying to read from a pipe) and the |
||
10285 | * pipe itself being active. */ |
||
10286 | bool has_active_crtc = encoder->base.crtc && |
||
10287 | to_intel_crtc(encoder->base.crtc)->active; |
||
2327 | Serge | 10288 | |
3031 | serge | 10289 | if (encoder->connectors_active && !has_active_crtc) { |
10290 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
||
10291 | encoder->base.base.id, |
||
10292 | drm_get_encoder_name(&encoder->base)); |
||
2327 | Serge | 10293 | |
3031 | serge | 10294 | /* Connector is active, but has no active pipe. This is |
10295 | * fallout from our resume register restoring. Disable |
||
10296 | * the encoder manually again. */ |
||
10297 | if (encoder->base.crtc) { |
||
10298 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
||
10299 | encoder->base.base.id, |
||
10300 | drm_get_encoder_name(&encoder->base)); |
||
10301 | encoder->disable(encoder); |
||
10302 | } |
||
2327 | Serge | 10303 | |
3031 | serge | 10304 | /* Inconsistent output/port/pipe state happens presumably due to |
10305 | * a bug in one of the get_hw_state functions. Or someplace else |
||
10306 | * in our code, like the register restore mess on resume. Clamp |
||
10307 | * things to off as a safer default. */ |
||
10308 | list_for_each_entry(connector, |
||
10309 | &dev->mode_config.connector_list, |
||
10310 | base.head) { |
||
10311 | if (connector->encoder != encoder) |
||
10312 | continue; |
||
2327 | Serge | 10313 | |
3031 | serge | 10314 | intel_connector_break_all_links(connector); |
10315 | } |
||
10316 | } |
||
10317 | /* Enabled encoders without active connectors will be fixed in |
||
10318 | * the crtc fixup. */ |
||
2327 | Serge | 10319 | } |
10320 | |||
3746 | Serge | 10321 | void i915_redisable_vga(struct drm_device *dev) |
10322 | { |
||
10323 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
10324 | u32 vga_reg = i915_vgacntrl_reg(dev); |
||
10325 | |||
4104 | Serge | 10326 | /* This function can be called both from intel_modeset_setup_hw_state or |
10327 | * at a very early point in our resume sequence, where the power well |
||
10328 | * structures are not yet restored. Since this function is at a very |
||
10329 | * paranoid "someone might have enabled VGA while we were not looking" |
||
10330 | * level, just check if the power well is enabled instead of trying to |
||
10331 | * follow the "don't touch the power well if we don't need it" policy |
||
10332 | * the rest of the driver uses. */ |
||
10333 | if (HAS_POWER_WELL(dev) && |
||
10334 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
||
10335 | return; |
||
10336 | |||
3746 | Serge | 10337 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
10338 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
||
10339 | i915_disable_vga(dev); |
||
10340 | } |
||
10341 | } |
||
10342 | |||
4104 | Serge | 10343 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
2332 | Serge | 10344 | { |
10345 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 10346 | enum pipe pipe; |
10347 | struct intel_crtc *crtc; |
||
10348 | struct intel_encoder *encoder; |
||
10349 | struct intel_connector *connector; |
||
4104 | Serge | 10350 | int i; |
2327 | Serge | 10351 | |
3746 | Serge | 10352 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10353 | base.head) { |
||
10354 | memset(&crtc->config, 0, sizeof(crtc->config)); |
||
2327 | Serge | 10355 | |
3746 | Serge | 10356 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
10357 | &crtc->config); |
||
2327 | Serge | 10358 | |
3031 | serge | 10359 | crtc->base.enabled = crtc->active; |
2330 | Serge | 10360 | |
3031 | serge | 10361 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
10362 | crtc->base.base.id, |
||
10363 | crtc->active ? "enabled" : "disabled"); |
||
2339 | Serge | 10364 | } |
2332 | Serge | 10365 | |
4104 | Serge | 10366 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
3480 | Serge | 10367 | if (HAS_DDI(dev)) |
3243 | Serge | 10368 | intel_ddi_setup_hw_pll_state(dev); |
10369 | |||
4104 | Serge | 10370 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10371 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
||
10372 | |||
10373 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
||
10374 | pll->active = 0; |
||
10375 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
||
10376 | base.head) { |
||
10377 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
||
10378 | pll->active++; |
||
10379 | } |
||
10380 | pll->refcount = pll->active; |
||
10381 | |||
10382 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
||
10383 | pll->name, pll->refcount, pll->on); |
||
10384 | } |
||
10385 | |||
3031 | serge | 10386 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10387 | base.head) { |
||
10388 | pipe = 0; |
||
2332 | Serge | 10389 | |
3031 | serge | 10390 | if (encoder->get_hw_state(encoder, &pipe)) { |
4104 | Serge | 10391 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10392 | encoder->base.crtc = &crtc->base; |
||
10393 | if (encoder->get_config) |
||
10394 | encoder->get_config(encoder, &crtc->config); |
||
3031 | serge | 10395 | } else { |
10396 | encoder->base.crtc = NULL; |
||
10397 | } |
||
2332 | Serge | 10398 | |
3031 | serge | 10399 | encoder->connectors_active = false; |
10400 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
||
10401 | encoder->base.base.id, |
||
10402 | drm_get_encoder_name(&encoder->base), |
||
10403 | encoder->base.crtc ? "enabled" : "disabled", |
||
10404 | pipe); |
||
10405 | } |
||
2332 | Serge | 10406 | |
4104 | Serge | 10407 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10408 | base.head) { |
||
10409 | if (!crtc->active) |
||
10410 | continue; |
||
10411 | if (dev_priv->display.get_clock) |
||
10412 | dev_priv->display.get_clock(crtc, |
||
10413 | &crtc->config); |
||
10414 | } |
||
10415 | |||
3031 | serge | 10416 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10417 | base.head) { |
||
10418 | if (connector->get_hw_state(connector)) { |
||
10419 | connector->base.dpms = DRM_MODE_DPMS_ON; |
||
10420 | connector->encoder->connectors_active = true; |
||
10421 | connector->base.encoder = &connector->encoder->base; |
||
10422 | } else { |
||
10423 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
||
10424 | connector->base.encoder = NULL; |
||
10425 | } |
||
10426 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
||
10427 | connector->base.base.id, |
||
10428 | drm_get_connector_name(&connector->base), |
||
10429 | connector->base.encoder ? "enabled" : "disabled"); |
||
2332 | Serge | 10430 | } |
4104 | Serge | 10431 | } |
2332 | Serge | 10432 | |
4104 | Serge | 10433 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
10434 | * and i915 state tracking structures. */ |
||
10435 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
||
10436 | bool force_restore) |
||
10437 | { |
||
10438 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
10439 | enum pipe pipe; |
||
10440 | struct drm_plane *plane; |
||
10441 | struct intel_crtc *crtc; |
||
10442 | struct intel_encoder *encoder; |
||
10443 | int i; |
||
10444 | |||
10445 | intel_modeset_readout_hw_state(dev); |
||
10446 | |||
10447 | /* |
||
10448 | * Now that we have the config, copy it to each CRTC struct |
||
10449 | * Note that this could go away if we move to using crtc_config |
||
10450 | * checking everywhere. |
||
10451 | */ |
||
10452 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
||
10453 | base.head) { |
||
10454 | if (crtc->active && i915_fastboot) { |
||
10455 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
||
10456 | |||
10457 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
||
10458 | crtc->base.base.id); |
||
10459 | drm_mode_debug_printmodeline(&crtc->base.mode); |
||
10460 | } |
||
10461 | } |
||
10462 | |||
3031 | serge | 10463 | /* HW state is read out, now we need to sanitize this mess. */ |
10464 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
10465 | base.head) { |
||
10466 | intel_sanitize_encoder(encoder); |
||
2332 | Serge | 10467 | } |
10468 | |||
3031 | serge | 10469 | for_each_pipe(pipe) { |
10470 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
||
10471 | intel_sanitize_crtc(crtc); |
||
4104 | Serge | 10472 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
2332 | Serge | 10473 | } |
10474 | |||
4104 | Serge | 10475 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10476 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
||
10477 | |||
10478 | if (!pll->on || pll->active) |
||
10479 | continue; |
||
10480 | |||
10481 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
||
10482 | |||
10483 | pll->disable(dev_priv, pll); |
||
10484 | pll->on = false; |
||
10485 | } |
||
10486 | |||
3243 | Serge | 10487 | if (force_restore) { |
3746 | Serge | 10488 | /* |
10489 | * We need to use raw interfaces for restoring state to avoid |
||
10490 | * checking (bogus) intermediate states. |
||
10491 | */ |
||
3243 | Serge | 10492 | for_each_pipe(pipe) { |
3746 | Serge | 10493 | struct drm_crtc *crtc = |
10494 | dev_priv->pipe_to_crtc_mapping[pipe]; |
||
10495 | |||
10496 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
||
10497 | crtc->fb); |
||
3243 | Serge | 10498 | } |
3746 | Serge | 10499 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
10500 | intel_plane_restore(plane); |
||
3243 | Serge | 10501 | |
3746 | Serge | 10502 | i915_redisable_vga(dev); |
3243 | Serge | 10503 | } else { |
3031 | serge | 10504 | intel_modeset_update_staged_output_state(dev); |
3243 | Serge | 10505 | } |
2332 | Serge | 10506 | |
3031 | serge | 10507 | intel_modeset_check_state(dev); |
3243 | Serge | 10508 | |
10509 | drm_mode_config_reset(dev); |
||
2332 | Serge | 10510 | } |
10511 | |||
3031 | serge | 10512 | void intel_modeset_gem_init(struct drm_device *dev) |
2330 | Serge | 10513 | { |
3031 | serge | 10514 | intel_modeset_init_hw(dev); |
2330 | Serge | 10515 | |
3031 | serge | 10516 | // intel_setup_overlay(dev); |
2330 | Serge | 10517 | |
3243 | Serge | 10518 | intel_modeset_setup_hw_state(dev, false); |
2330 | Serge | 10519 | } |
10520 | |||
3031 | serge | 10521 | void intel_modeset_cleanup(struct drm_device *dev) |
2327 | Serge | 10522 | { |
3031 | serge | 10523 | #if 0 |
10524 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
10525 | struct drm_crtc *crtc; |
||
2327 | Serge | 10526 | |
4104 | Serge | 10527 | /* |
10528 | * Interrupts and polling as the first thing to avoid creating havoc. |
||
10529 | * Too much stuff here (turning of rps, connectors, ...) would |
||
10530 | * experience fancy races otherwise. |
||
10531 | */ |
||
10532 | drm_irq_uninstall(dev); |
||
10533 | cancel_work_sync(&dev_priv->hotplug_work); |
||
10534 | /* |
||
10535 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
||
10536 | * poll handlers. Hence disable polling after hpd handling is shut down. |
||
10537 | */ |
||
3031 | serge | 10538 | // drm_kms_helper_poll_fini(dev); |
4104 | Serge | 10539 | |
3031 | serge | 10540 | mutex_lock(&dev->struct_mutex); |
2327 | Serge | 10541 | |
3031 | serge | 10542 | // intel_unregister_dsm_handler(); |
2327 | Serge | 10543 | |
3031 | serge | 10544 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10545 | /* Skip inactive CRTCs */ |
||
10546 | if (!crtc->fb) |
||
10547 | continue; |
||
2342 | Serge | 10548 | |
3031 | serge | 10549 | intel_increase_pllclock(crtc); |
10550 | } |
||
2342 | Serge | 10551 | |
3031 | serge | 10552 | intel_disable_fbc(dev); |
2342 | Serge | 10553 | |
3031 | serge | 10554 | intel_disable_gt_powersave(dev); |
2342 | Serge | 10555 | |
3031 | serge | 10556 | ironlake_teardown_rc6(dev); |
2327 | Serge | 10557 | |
3031 | serge | 10558 | mutex_unlock(&dev->struct_mutex); |
2327 | Serge | 10559 | |
4104 | Serge | 10560 | /* flush any delayed tasks or pending work */ |
10561 | flush_scheduled_work(); |
||
2327 | Serge | 10562 | |
4280 | Serge | 10563 | /* destroy backlight, if any, before the connectors */ |
10564 | intel_panel_destroy_backlight(dev); |
||
2327 | Serge | 10565 | |
3031 | serge | 10566 | drm_mode_config_cleanup(dev); |
2327 | Serge | 10567 | #endif |
10568 | } |
||
10569 | |||
10570 | /* |
||
3031 | serge | 10571 | * Return which encoder is currently attached for connector. |
2327 | Serge | 10572 | */ |
3031 | serge | 10573 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
2327 | Serge | 10574 | { |
3031 | serge | 10575 | return &intel_attached_encoder(connector)->base; |
10576 | } |
||
2327 | Serge | 10577 | |
3031 | serge | 10578 | void intel_connector_attach_encoder(struct intel_connector *connector, |
10579 | struct intel_encoder *encoder) |
||
10580 | { |
||
10581 | connector->encoder = encoder; |
||
10582 | drm_mode_connector_attach_encoder(&connector->base, |
||
10583 | &encoder->base); |
||
2327 | Serge | 10584 | } |
10585 | |||
10586 | /* |
||
3031 | serge | 10587 | * set vga decode state - true == enable VGA decode |
2327 | Serge | 10588 | */ |
3031 | serge | 10589 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
2327 | Serge | 10590 | { |
2330 | Serge | 10591 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 10592 | u16 gmch_ctrl; |
2327 | Serge | 10593 | |
3031 | serge | 10594 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
10595 | if (state) |
||
10596 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
||
2330 | Serge | 10597 | else |
3031 | serge | 10598 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
10599 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
||
10600 | return 0; |
||
2330 | Serge | 10601 | } |
10602 | |||
3031 | serge | 10603 | #ifdef CONFIG_DEBUG_FS |
10604 | #include |
||
2327 | Serge | 10605 | |
3031 | serge | 10606 | struct intel_display_error_state { |
4104 | Serge | 10607 | |
10608 | u32 power_well_driver; |
||
10609 | |||
10610 | int num_transcoders; |
||
10611 | |||
3031 | serge | 10612 | struct intel_cursor_error_state { |
10613 | u32 control; |
||
10614 | u32 position; |
||
10615 | u32 base; |
||
10616 | u32 size; |
||
10617 | } cursor[I915_MAX_PIPES]; |
||
2327 | Serge | 10618 | |
3031 | serge | 10619 | struct intel_pipe_error_state { |
10620 | u32 source; |
||
10621 | } pipe[I915_MAX_PIPES]; |
||
2327 | Serge | 10622 | |
3031 | serge | 10623 | struct intel_plane_error_state { |
10624 | u32 control; |
||
10625 | u32 stride; |
||
10626 | u32 size; |
||
10627 | u32 pos; |
||
10628 | u32 addr; |
||
10629 | u32 surface; |
||
10630 | u32 tile_offset; |
||
10631 | } plane[I915_MAX_PIPES]; |
||
4104 | Serge | 10632 | |
10633 | struct intel_transcoder_error_state { |
||
10634 | enum transcoder cpu_transcoder; |
||
10635 | |||
10636 | u32 conf; |
||
10637 | |||
10638 | u32 htotal; |
||
10639 | u32 hblank; |
||
10640 | u32 hsync; |
||
10641 | u32 vtotal; |
||
10642 | u32 vblank; |
||
10643 | u32 vsync; |
||
10644 | } transcoder[4]; |
||
3031 | serge | 10645 | }; |
2327 | Serge | 10646 | |
3031 | serge | 10647 | struct intel_display_error_state * |
10648 | intel_display_capture_error_state(struct drm_device *dev) |
||
10649 | { |
||
10650 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
10651 | struct intel_display_error_state *error; |
||
4104 | Serge | 10652 | int transcoders[] = { |
10653 | TRANSCODER_A, |
||
10654 | TRANSCODER_B, |
||
10655 | TRANSCODER_C, |
||
10656 | TRANSCODER_EDP, |
||
10657 | }; |
||
3031 | serge | 10658 | int i; |
2327 | Serge | 10659 | |
4104 | Serge | 10660 | if (INTEL_INFO(dev)->num_pipes == 0) |
10661 | return NULL; |
||
10662 | |||
3031 | serge | 10663 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
10664 | if (error == NULL) |
||
10665 | return NULL; |
||
2327 | Serge | 10666 | |
4104 | Serge | 10667 | if (HAS_POWER_WELL(dev)) |
10668 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
||
10669 | |||
3031 | serge | 10670 | for_each_pipe(i) { |
3746 | Serge | 10671 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
3031 | serge | 10672 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
10673 | error->cursor[i].position = I915_READ(CURPOS(i)); |
||
10674 | error->cursor[i].base = I915_READ(CURBASE(i)); |
||
3746 | Serge | 10675 | } else { |
10676 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
||
10677 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
||
10678 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
||
10679 | } |
||
2327 | Serge | 10680 | |
3031 | serge | 10681 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
10682 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
||
3746 | Serge | 10683 | if (INTEL_INFO(dev)->gen <= 3) { |
3031 | serge | 10684 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
10685 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
||
3746 | Serge | 10686 | } |
10687 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
||
3031 | serge | 10688 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
10689 | if (INTEL_INFO(dev)->gen >= 4) { |
||
10690 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
||
10691 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
||
10692 | } |
||
2327 | Serge | 10693 | |
3031 | serge | 10694 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
10695 | } |
||
2327 | Serge | 10696 | |
4104 | Serge | 10697 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
10698 | if (HAS_DDI(dev_priv->dev)) |
||
10699 | error->num_transcoders++; /* Account for eDP. */ |
||
10700 | |||
10701 | for (i = 0; i < error->num_transcoders; i++) { |
||
10702 | enum transcoder cpu_transcoder = transcoders[i]; |
||
10703 | |||
10704 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
||
10705 | |||
10706 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
||
10707 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
||
10708 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
||
10709 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
||
10710 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
||
10711 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
||
10712 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
||
10713 | } |
||
10714 | |||
10715 | /* In the code above we read the registers without checking if the power |
||
10716 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to |
||
10717 | * prevent the next I915_WRITE from detecting it and printing an error |
||
10718 | * message. */ |
||
10719 | intel_uncore_clear_errors(dev); |
||
10720 | |||
3031 | serge | 10721 | return error; |
2330 | Serge | 10722 | } |
2327 | Serge | 10723 | |
4104 | Serge | 10724 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
10725 | |||
3031 | serge | 10726 | void |
4104 | Serge | 10727 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
3031 | serge | 10728 | struct drm_device *dev, |
10729 | struct intel_display_error_state *error) |
||
2332 | Serge | 10730 | { |
3031 | serge | 10731 | int i; |
2330 | Serge | 10732 | |
4104 | Serge | 10733 | if (!error) |
10734 | return; |
||
10735 | |||
10736 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
||
10737 | if (HAS_POWER_WELL(dev)) |
||
10738 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
||
10739 | error->power_well_driver); |
||
3031 | serge | 10740 | for_each_pipe(i) { |
4104 | Serge | 10741 | err_printf(m, "Pipe [%d]:\n", i); |
10742 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
||
2332 | Serge | 10743 | |
4104 | Serge | 10744 | err_printf(m, "Plane [%d]:\n", i); |
10745 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
||
10746 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
||
3746 | Serge | 10747 | if (INTEL_INFO(dev)->gen <= 3) { |
4104 | Serge | 10748 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
10749 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
||
3746 | Serge | 10750 | } |
10751 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
||
4104 | Serge | 10752 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
3031 | serge | 10753 | if (INTEL_INFO(dev)->gen >= 4) { |
4104 | Serge | 10754 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
10755 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
||
3031 | serge | 10756 | } |
2332 | Serge | 10757 | |
4104 | Serge | 10758 | err_printf(m, "Cursor [%d]:\n", i); |
10759 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
||
10760 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
||
10761 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
||
3031 | serge | 10762 | } |
4104 | Serge | 10763 | |
10764 | for (i = 0; i < error->num_transcoders; i++) { |
||
10765 | err_printf(m, " CPU transcoder: %c\n", |
||
10766 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
||
10767 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
||
10768 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
||
10769 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
||
10770 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
||
10771 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
||
10772 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
||
10773 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
||
10774 | } |
||
2327 | Serge | 10775 | } |
3031 | serge | 10776 | #endif>=>=>>=>=>=>>>>>5,><5,>>>>><>><>>>>>>>>(intel_crtc)-><(intel_crtc)->>><>><>><>><>><>><>><>><>><>><>>>>>>=><=>>><>>>>><>><>><>><>>><>><>>>><>><>>>><>><>><>><>>>><>><>><>><>>><>><>><>><>>>>>>><>><>><>><>><>>>><>><>><>><>->>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>>><>>><>><>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>=>=>=>>>><>><>><>><>><>><>><>>>>>>>>>>>>><>><>><>><>>>>>>><>>>>>>=>=>>=>>>=>=>=>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |