WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
3746	Serge	27	//#include
2327	Serge	28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
3746	Serge	33	#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
3031	serge	40	#include
		41	#include
		42	//#include
2327	Serge	43
4104	Serge	44	#define MAX_ERRNO 4095
2327	Serge	45	phys_addr_t get_bus_addr(void);
		46
2342	Serge	47	bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
2327	Serge	48	static void intel_increase_pllclock(struct drm_crtc *crtc);
3243	Serge	49	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	50
4104	Serge	51	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		52	struct intel_crtc_config *pipe_config);
		53	static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
		54	struct intel_crtc_config *pipe_config);
2327	Serge	55
4104	Serge	56	static int intel_set_mode(struct drm_crtc crtc, struct drm_display_mode mode,
		57	int x, int y, struct drm_framebuffer *old_fb);
		58
		59
2327	Serge	60	typedef struct {
		61	int min, max;
		62	} intel_range_t;
		63
		64	typedef struct {
		65	int dot_limit;
		66	int p2_slow, p2_fast;
		67	} intel_p2_t;
		68
		69	typedef struct intel_limit intel_limit_t;
		70	struct intel_limit {
		71	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		72	intel_p2_t p2;
		73	};
		74
		75	/* FDI */
		76	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		77
3243	Serge	78	int
		79	intel_pch_rawclk(struct drm_device *dev)
		80	{
		81	struct drm_i915_private *dev_priv = dev->dev_private;
		82
		83	WARN_ON(!HAS_PCH_SPLIT(dev));
		84
		85	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
		86	}
		87
2327	Serge	88	static inline u32 /* units of 100MHz */
		89	intel_fdi_link_freq(struct drm_device *dev)
		90	{
		91	if (IS_GEN5(dev)) {
		92	struct drm_i915_private *dev_priv = dev->dev_private;
		93	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		94	} else
		95	return 27;
		96	}
		97
4104	Serge	98	static const intel_limit_t intel_limits_i8xx_dac = {
		99	.dot = { .min = 25000, .max = 350000 },
		100	.vco = { .min = 930000, .max = 1400000 },
		101	.n = { .min = 3, .max = 16 },
		102	.m = { .min = 96, .max = 140 },
		103	.m1 = { .min = 18, .max = 26 },
		104	.m2 = { .min = 6, .max = 16 },
		105	.p = { .min = 4, .max = 128 },
		106	.p1 = { .min = 2, .max = 33 },
		107	.p2 = { .dot_limit = 165000,
		108	.p2_slow = 4, .p2_fast = 2 },
		109	};
		110
2327	Serge	111	static const intel_limit_t intel_limits_i8xx_dvo = {
		112	.dot = { .min = 25000, .max = 350000 },
		113	.vco = { .min = 930000, .max = 1400000 },
		114	.n = { .min = 3, .max = 16 },
		115	.m = { .min = 96, .max = 140 },
		116	.m1 = { .min = 18, .max = 26 },
		117	.m2 = { .min = 6, .max = 16 },
		118	.p = { .min = 4, .max = 128 },
		119	.p1 = { .min = 2, .max = 33 },
		120	.p2 = { .dot_limit = 165000,
4104	Serge	121	.p2_slow = 4, .p2_fast = 4 },
2327	Serge	122	};
		123
		124	static const intel_limit_t intel_limits_i8xx_lvds = {
		125	.dot = { .min = 25000, .max = 350000 },
		126	.vco = { .min = 930000, .max = 1400000 },
		127	.n = { .min = 3, .max = 16 },
		128	.m = { .min = 96, .max = 140 },
		129	.m1 = { .min = 18, .max = 26 },
		130	.m2 = { .min = 6, .max = 16 },
		131	.p = { .min = 4, .max = 128 },
		132	.p1 = { .min = 1, .max = 6 },
		133	.p2 = { .dot_limit = 165000,
		134	.p2_slow = 14, .p2_fast = 7 },
		135	};
		136
		137	static const intel_limit_t intel_limits_i9xx_sdvo = {
		138	.dot = { .min = 20000, .max = 400000 },
		139	.vco = { .min = 1400000, .max = 2800000 },
		140	.n = { .min = 1, .max = 6 },
		141	.m = { .min = 70, .max = 120 },
3480	Serge	142	.m1 = { .min = 8, .max = 18 },
		143	.m2 = { .min = 3, .max = 7 },
2327	Serge	144	.p = { .min = 5, .max = 80 },
		145	.p1 = { .min = 1, .max = 8 },
		146	.p2 = { .dot_limit = 200000,
		147	.p2_slow = 10, .p2_fast = 5 },
		148	};
		149
		150	static const intel_limit_t intel_limits_i9xx_lvds = {
		151	.dot = { .min = 20000, .max = 400000 },
		152	.vco = { .min = 1400000, .max = 2800000 },
		153	.n = { .min = 1, .max = 6 },
		154	.m = { .min = 70, .max = 120 },
3480	Serge	155	.m1 = { .min = 8, .max = 18 },
		156	.m2 = { .min = 3, .max = 7 },
2327	Serge	157	.p = { .min = 7, .max = 98 },
		158	.p1 = { .min = 1, .max = 8 },
		159	.p2 = { .dot_limit = 112000,
		160	.p2_slow = 14, .p2_fast = 7 },
		161	};
		162
		163
		164	static const intel_limit_t intel_limits_g4x_sdvo = {
		165	.dot = { .min = 25000, .max = 270000 },
		166	.vco = { .min = 1750000, .max = 3500000},
		167	.n = { .min = 1, .max = 4 },
		168	.m = { .min = 104, .max = 138 },
		169	.m1 = { .min = 17, .max = 23 },
		170	.m2 = { .min = 5, .max = 11 },
		171	.p = { .min = 10, .max = 30 },
		172	.p1 = { .min = 1, .max = 3},
		173	.p2 = { .dot_limit = 270000,
		174	.p2_slow = 10,
		175	.p2_fast = 10
		176	},
		177	};
		178
		179	static const intel_limit_t intel_limits_g4x_hdmi = {
		180	.dot = { .min = 22000, .max = 400000 },
		181	.vco = { .min = 1750000, .max = 3500000},
		182	.n = { .min = 1, .max = 4 },
		183	.m = { .min = 104, .max = 138 },
		184	.m1 = { .min = 16, .max = 23 },
		185	.m2 = { .min = 5, .max = 11 },
		186	.p = { .min = 5, .max = 80 },
		187	.p1 = { .min = 1, .max = 8},
		188	.p2 = { .dot_limit = 165000,
		189	.p2_slow = 10, .p2_fast = 5 },
		190	};
		191
		192	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		193	.dot = { .min = 20000, .max = 115000 },
		194	.vco = { .min = 1750000, .max = 3500000 },
		195	.n = { .min = 1, .max = 3 },
		196	.m = { .min = 104, .max = 138 },
		197	.m1 = { .min = 17, .max = 23 },
		198	.m2 = { .min = 5, .max = 11 },
		199	.p = { .min = 28, .max = 112 },
		200	.p1 = { .min = 2, .max = 8 },
		201	.p2 = { .dot_limit = 0,
		202	.p2_slow = 14, .p2_fast = 14
		203	},
		204	};
		205
		206	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		207	.dot = { .min = 80000, .max = 224000 },
		208	.vco = { .min = 1750000, .max = 3500000 },
		209	.n = { .min = 1, .max = 3 },
		210	.m = { .min = 104, .max = 138 },
		211	.m1 = { .min = 17, .max = 23 },
		212	.m2 = { .min = 5, .max = 11 },
		213	.p = { .min = 14, .max = 42 },
		214	.p1 = { .min = 2, .max = 6 },
		215	.p2 = { .dot_limit = 0,
		216	.p2_slow = 7, .p2_fast = 7
		217	},
		218	};
		219
		220	static const intel_limit_t intel_limits_pineview_sdvo = {
		221	.dot = { .min = 20000, .max = 400000},
		222	.vco = { .min = 1700000, .max = 3500000 },
		223	/* Pineview's Ncounter is a ring counter */
		224	.n = { .min = 3, .max = 6 },
		225	.m = { .min = 2, .max = 256 },
		226	/* Pineview only has one combined m divider, which we treat as m2. */
		227	.m1 = { .min = 0, .max = 0 },
		228	.m2 = { .min = 0, .max = 254 },
		229	.p = { .min = 5, .max = 80 },
		230	.p1 = { .min = 1, .max = 8 },
		231	.p2 = { .dot_limit = 200000,
		232	.p2_slow = 10, .p2_fast = 5 },
		233	};
		234
		235	static const intel_limit_t intel_limits_pineview_lvds = {
		236	.dot = { .min = 20000, .max = 400000 },
		237	.vco = { .min = 1700000, .max = 3500000 },
		238	.n = { .min = 3, .max = 6 },
		239	.m = { .min = 2, .max = 256 },
		240	.m1 = { .min = 0, .max = 0 },
		241	.m2 = { .min = 0, .max = 254 },
		242	.p = { .min = 7, .max = 112 },
		243	.p1 = { .min = 1, .max = 8 },
		244	.p2 = { .dot_limit = 112000,
		245	.p2_slow = 14, .p2_fast = 14 },
		246	};
		247
		248	/* Ironlake / Sandybridge
		249	*
		250	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		251	* the range value for them is (actual_value - 2).
		252	*/
		253	static const intel_limit_t intel_limits_ironlake_dac = {
		254	.dot = { .min = 25000, .max = 350000 },
		255	.vco = { .min = 1760000, .max = 3510000 },
		256	.n = { .min = 1, .max = 5 },
		257	.m = { .min = 79, .max = 127 },
		258	.m1 = { .min = 12, .max = 22 },
		259	.m2 = { .min = 5, .max = 9 },
		260	.p = { .min = 5, .max = 80 },
		261	.p1 = { .min = 1, .max = 8 },
		262	.p2 = { .dot_limit = 225000,
		263	.p2_slow = 10, .p2_fast = 5 },
		264	};
		265
		266	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		267	.dot = { .min = 25000, .max = 350000 },
		268	.vco = { .min = 1760000, .max = 3510000 },
		269	.n = { .min = 1, .max = 3 },
		270	.m = { .min = 79, .max = 118 },
		271	.m1 = { .min = 12, .max = 22 },
		272	.m2 = { .min = 5, .max = 9 },
		273	.p = { .min = 28, .max = 112 },
		274	.p1 = { .min = 2, .max = 8 },
		275	.p2 = { .dot_limit = 225000,
		276	.p2_slow = 14, .p2_fast = 14 },
		277	};
		278
		279	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		280	.dot = { .min = 25000, .max = 350000 },
		281	.vco = { .min = 1760000, .max = 3510000 },
		282	.n = { .min = 1, .max = 3 },
		283	.m = { .min = 79, .max = 127 },
		284	.m1 = { .min = 12, .max = 22 },
		285	.m2 = { .min = 5, .max = 9 },
		286	.p = { .min = 14, .max = 56 },
		287	.p1 = { .min = 2, .max = 8 },
		288	.p2 = { .dot_limit = 225000,
		289	.p2_slow = 7, .p2_fast = 7 },
		290	};
		291
		292	/* LVDS 100mhz refclk limits. */
		293	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		294	.dot = { .min = 25000, .max = 350000 },
		295	.vco = { .min = 1760000, .max = 3510000 },
		296	.n = { .min = 1, .max = 2 },
		297	.m = { .min = 79, .max = 126 },
		298	.m1 = { .min = 12, .max = 22 },
		299	.m2 = { .min = 5, .max = 9 },
		300	.p = { .min = 28, .max = 112 },
2342	Serge	301	.p1 = { .min = 2, .max = 8 },
2327	Serge	302	.p2 = { .dot_limit = 225000,
		303	.p2_slow = 14, .p2_fast = 14 },
		304	};
		305
		306	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		307	.dot = { .min = 25000, .max = 350000 },
		308	.vco = { .min = 1760000, .max = 3510000 },
		309	.n = { .min = 1, .max = 3 },
		310	.m = { .min = 79, .max = 126 },
		311	.m1 = { .min = 12, .max = 22 },
		312	.m2 = { .min = 5, .max = 9 },
		313	.p = { .min = 14, .max = 42 },
2342	Serge	314	.p1 = { .min = 2, .max = 6 },
2327	Serge	315	.p2 = { .dot_limit = 225000,
		316	.p2_slow = 7, .p2_fast = 7 },
		317	};
		318
3031	serge	319	static const intel_limit_t intel_limits_vlv_dac = {
		320	.dot = { .min = 25000, .max = 270000 },
		321	.vco = { .min = 4000000, .max = 6000000 },
		322	.n = { .min = 1, .max = 7 },
		323	.m = { .min = 22, .max = 450 }, /* guess */
		324	.m1 = { .min = 2, .max = 3 },
		325	.m2 = { .min = 11, .max = 156 },
		326	.p = { .min = 10, .max = 30 },
4104	Serge	327	.p1 = { .min = 1, .max = 3 },
3031	serge	328	.p2 = { .dot_limit = 270000,
		329	.p2_slow = 2, .p2_fast = 20 },
		330	};
		331
		332	static const intel_limit_t intel_limits_vlv_hdmi = {
4104	Serge	333	.dot = { .min = 25000, .max = 270000 },
		334	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	335	.n = { .min = 1, .max = 7 },
		336	.m = { .min = 60, .max = 300 }, /* guess */
		337	.m1 = { .min = 2, .max = 3 },
		338	.m2 = { .min = 11, .max = 156 },
		339	.p = { .min = 10, .max = 30 },
		340	.p1 = { .min = 2, .max = 3 },
		341	.p2 = { .dot_limit = 270000,
		342	.p2_slow = 2, .p2_fast = 20 },
		343	};
		344
		345	static const intel_limit_t intel_limits_vlv_dp = {
3243	Serge	346	.dot = { .min = 25000, .max = 270000 },
		347	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	348	.n = { .min = 1, .max = 7 },
3243	Serge	349	.m = { .min = 22, .max = 450 },
3031	serge	350	.m1 = { .min = 2, .max = 3 },
		351	.m2 = { .min = 11, .max = 156 },
		352	.p = { .min = 10, .max = 30 },
4104	Serge	353	.p1 = { .min = 1, .max = 3 },
3031	serge	354	.p2 = { .dot_limit = 270000,
		355	.p2_slow = 2, .p2_fast = 20 },
		356	};
		357
2327	Serge	358	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		359	int refclk)
		360	{
		361	struct drm_device *dev = crtc->dev;
		362	const intel_limit_t *limit;
		363
		364	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	365	if (intel_is_dual_link_lvds(dev)) {
2327	Serge	366	if (refclk == 100000)
		367	limit = &intel_limits_ironlake_dual_lvds_100m;
		368	else
		369	limit = &intel_limits_ironlake_dual_lvds;
		370	} else {
		371	if (refclk == 100000)
		372	limit = &intel_limits_ironlake_single_lvds_100m;
		373	else
		374	limit = &intel_limits_ironlake_single_lvds;
		375	}
4104	Serge	376	} else
2327	Serge	377	limit = &intel_limits_ironlake_dac;
		378
		379	return limit;
		380	}
		381
		382	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		383	{
		384	struct drm_device *dev = crtc->dev;
		385	const intel_limit_t *limit;
		386
		387	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	388	if (intel_is_dual_link_lvds(dev))
2327	Serge	389	limit = &intel_limits_g4x_dual_channel_lvds;
		390	else
		391	limit = &intel_limits_g4x_single_channel_lvds;
		392	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		393	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		394	limit = &intel_limits_g4x_hdmi;
		395	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		396	limit = &intel_limits_g4x_sdvo;
		397	} else /* The option is for other outputs */
		398	limit = &intel_limits_i9xx_sdvo;
		399
		400	return limit;
		401	}
		402
		403	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		404	{
		405	struct drm_device *dev = crtc->dev;
		406	const intel_limit_t *limit;
		407
		408	if (HAS_PCH_SPLIT(dev))
		409	limit = intel_ironlake_limit(crtc, refclk);
		410	else if (IS_G4X(dev)) {
		411	limit = intel_g4x_limit(crtc);
		412	} else if (IS_PINEVIEW(dev)) {
		413	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		414	limit = &intel_limits_pineview_lvds;
		415	else
		416	limit = &intel_limits_pineview_sdvo;
3031	serge	417	} else if (IS_VALLEYVIEW(dev)) {
		418	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
		419	limit = &intel_limits_vlv_dac;
		420	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
		421	limit = &intel_limits_vlv_hdmi;
		422	else
		423	limit = &intel_limits_vlv_dp;
2327	Serge	424	} else if (!IS_GEN2(dev)) {
		425	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		426	limit = &intel_limits_i9xx_lvds;
		427	else
		428	limit = &intel_limits_i9xx_sdvo;
		429	} else {
		430	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		431	limit = &intel_limits_i8xx_lvds;
4104	Serge	432	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
		433	limit = &intel_limits_i8xx_dvo;
2327	Serge	434	else
4104	Serge	435	limit = &intel_limits_i8xx_dac;
2327	Serge	436	}
		437	return limit;
		438	}
		439
		440	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		441	static void pineview_clock(int refclk, intel_clock_t *clock)
		442	{
		443	clock->m = clock->m2 + 2;
		444	clock->p = clock->p1 * clock->p2;
		445	clock->vco = refclk * clock->m / clock->n;
		446	clock->dot = clock->vco / clock->p;
		447	}
		448
4104	Serge	449	static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
2327	Serge	450	{
4104	Serge	451	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
		452	}
		453
		454	static void i9xx_clock(int refclk, intel_clock_t *clock)
		455	{
		456	clock->m = i9xx_dpll_compute_m(clock);
2327	Serge	457	clock->p = clock->p1 * clock->p2;
		458	clock->vco = refclk * clock->m / (clock->n + 2);
		459	clock->dot = clock->vco / clock->p;
		460	}
		461
		462	/**
		463	* Returns whether any output on the specified pipe is of the specified type
		464	*/
		465	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		466	{
		467	struct drm_device *dev = crtc->dev;
		468	struct intel_encoder *encoder;
		469
3031	serge	470	for_each_encoder_on_crtc(dev, crtc, encoder)
		471	if (encoder->type == type)
2327	Serge	472	return true;
		473
		474	return false;
		475	}
		476
		477	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		478	/**
		479	* Returns whether the given set of divisors are valid for a given refclk with
		480	* the given connectors.
		481	*/
		482
		483	static bool intel_PLL_is_valid(struct drm_device *dev,
		484	const intel_limit_t *limit,
		485	const intel_clock_t *clock)
		486	{
		487	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	488	INTELPllInvalid("p1 out of range\n");
2327	Serge	489	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
2342	Serge	490	INTELPllInvalid("p out of range\n");
2327	Serge	491	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	492	INTELPllInvalid("m2 out of range\n");
2327	Serge	493	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	494	INTELPllInvalid("m1 out of range\n");
2327	Serge	495	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
2342	Serge	496	INTELPllInvalid("m1 <= m2\n");
2327	Serge	497	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
2342	Serge	498	INTELPllInvalid("m out of range\n");
2327	Serge	499	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
2342	Serge	500	INTELPllInvalid("n out of range\n");
2327	Serge	501	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	502	INTELPllInvalid("vco out of range\n");
2327	Serge	503	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		504	* connector, etc., rather than just a single range.
		505	*/
		506	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	507	INTELPllInvalid("dot out of range\n");
2327	Serge	508
		509	return true;
		510	}
		511
		512	static bool
4104	Serge	513	i9xx_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	514	int target, int refclk, intel_clock_t *match_clock,
		515	intel_clock_t *best_clock)
2327	Serge	516	{
		517	struct drm_device *dev = crtc->dev;
		518	intel_clock_t clock;
		519	int err = target;
		520
3480	Serge	521	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2327	Serge	522	/*
3480	Serge	523	* For LVDS just rely on its current settings for dual-channel.
		524	* We haven't figured out how to reliably set up different
		525	* single/dual channel state, if we even can.
2327	Serge	526	*/
3480	Serge	527	if (intel_is_dual_link_lvds(dev))
2327	Serge	528	clock.p2 = limit->p2.p2_fast;
		529	else
		530	clock.p2 = limit->p2.p2_slow;
		531	} else {
		532	if (target < limit->p2.dot_limit)
		533	clock.p2 = limit->p2.p2_slow;
		534	else
		535	clock.p2 = limit->p2.p2_fast;
		536	}
		537
2342	Serge	538	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	539
		540	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		541	clock.m1++) {
		542	for (clock.m2 = limit->m2.min;
		543	clock.m2 <= limit->m2.max; clock.m2++) {
4104	Serge	544	if (clock.m2 >= clock.m1)
2327	Serge	545	break;
		546	for (clock.n = limit->n.min;
		547	clock.n <= limit->n.max; clock.n++) {
		548	for (clock.p1 = limit->p1.min;
		549	clock.p1 <= limit->p1.max; clock.p1++) {
		550	int this_err;
		551
4104	Serge	552	i9xx_clock(refclk, &clock);
2327	Serge	553	if (!intel_PLL_is_valid(dev, limit,
		554	&clock))
		555	continue;
3031	serge	556	if (match_clock &&
		557	clock.p != match_clock->p)
		558	continue;
2327	Serge	559
		560	this_err = abs(clock.dot - target);
		561	if (this_err < err) {
		562	*best_clock = clock;
		563	err = this_err;
		564	}
		565	}
		566	}
		567	}
		568	}
		569
		570	return (err != target);
		571	}
		572
		573	static bool
4104	Serge	574	pnv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
		575	int target, int refclk, intel_clock_t *match_clock,
		576	intel_clock_t *best_clock)
		577	{
		578	struct drm_device *dev = crtc->dev;
		579	intel_clock_t clock;
		580	int err = target;
		581
		582	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		583	/*
		584	* For LVDS just rely on its current settings for dual-channel.
		585	* We haven't figured out how to reliably set up different
		586	* single/dual channel state, if we even can.
		587	*/
		588	if (intel_is_dual_link_lvds(dev))
		589	clock.p2 = limit->p2.p2_fast;
		590	else
		591	clock.p2 = limit->p2.p2_slow;
		592	} else {
		593	if (target < limit->p2.dot_limit)
		594	clock.p2 = limit->p2.p2_slow;
		595	else
		596	clock.p2 = limit->p2.p2_fast;
		597	}
		598
		599	memset(best_clock, 0, sizeof(*best_clock));
		600
		601	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		602	clock.m1++) {
		603	for (clock.m2 = limit->m2.min;
		604	clock.m2 <= limit->m2.max; clock.m2++) {
		605	for (clock.n = limit->n.min;
		606	clock.n <= limit->n.max; clock.n++) {
		607	for (clock.p1 = limit->p1.min;
		608	clock.p1 <= limit->p1.max; clock.p1++) {
		609	int this_err;
		610
		611	pineview_clock(refclk, &clock);
		612	if (!intel_PLL_is_valid(dev, limit,
		613	&clock))
		614	continue;
		615	if (match_clock &&
		616	clock.p != match_clock->p)
		617	continue;
		618
		619	this_err = abs(clock.dot - target);
		620	if (this_err < err) {
		621	*best_clock = clock;
		622	err = this_err;
		623	}
		624	}
		625	}
		626	}
		627	}
		628
		629	return (err != target);
		630	}
		631
		632	static bool
		633	g4x_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	634	int target, int refclk, intel_clock_t *match_clock,
		635	intel_clock_t *best_clock)
2327	Serge	636	{
		637	struct drm_device *dev = crtc->dev;
		638	intel_clock_t clock;
		639	int max_n;
		640	bool found;
		641	/* approximately equals target * 0.00585 */
		642	int err_most = (target >> 8) + (target >> 9);
		643	found = false;
		644
		645	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	646	if (intel_is_dual_link_lvds(dev))
2327	Serge	647	clock.p2 = limit->p2.p2_fast;
		648	else
		649	clock.p2 = limit->p2.p2_slow;
		650	} else {
		651	if (target < limit->p2.dot_limit)
		652	clock.p2 = limit->p2.p2_slow;
		653	else
		654	clock.p2 = limit->p2.p2_fast;
		655	}
		656
		657	memset(best_clock, 0, sizeof(*best_clock));
		658	max_n = limit->n.max;
		659	/* based on hardware requirement, prefer smaller n to precision */
		660	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		661	/* based on hardware requirement, prefere larger m1,m2 */
		662	for (clock.m1 = limit->m1.max;
		663	clock.m1 >= limit->m1.min; clock.m1--) {
		664	for (clock.m2 = limit->m2.max;
		665	clock.m2 >= limit->m2.min; clock.m2--) {
		666	for (clock.p1 = limit->p1.max;
		667	clock.p1 >= limit->p1.min; clock.p1--) {
		668	int this_err;
		669
4104	Serge	670	i9xx_clock(refclk, &clock);
2327	Serge	671	if (!intel_PLL_is_valid(dev, limit,
		672	&clock))
		673	continue;
		674
		675	this_err = abs(clock.dot - target);
		676	if (this_err < err_most) {
		677	*best_clock = clock;
		678	err_most = this_err;
		679	max_n = clock.n;
		680	found = true;
		681	}
		682	}
		683	}
		684	}
		685	}
		686	return found;
		687	}
		688
		689	static bool
4104	Serge	690	vlv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	691	int target, int refclk, intel_clock_t *match_clock,
		692	intel_clock_t *best_clock)
		693	{
		694	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
		695	u32 m, n, fastclk;
4104	Serge	696	u32 updrate, minupdate, p;
3031	serge	697	unsigned long bestppm, ppm, absppm;
		698	int dotclk, flag;
2327	Serge	699
3031	serge	700	flag = 0;
		701	dotclk = target * 1000;
		702	bestppm = 1000000;
		703	ppm = absppm = 0;
		704	fastclk = dotclk / (2*100);
		705	updrate = 0;
		706	minupdate = 19200;
		707	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
		708	bestm1 = bestm2 = bestp1 = bestp2 = 0;
		709
		710	/* based on hardware requirement, prefer smaller n to precision */
		711	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		712	updrate = refclk / n;
		713	for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
		714	for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
		715	if (p2 > 10)
		716	p2 = p2 - 1;
		717	p = p1 * p2;
		718	/* based on hardware requirement, prefer bigger m1,m2 values */
		719	for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
		720	m2 = (((2(fastclk p * n / m1 )) +
		721	refclk) / (2*refclk));
		722	m = m1 * m2;
		723	vco = updrate * m;
		724	if (vco >= limit->vco.min && vco < limit->vco.max) {
		725	ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
		726	absppm = (ppm > 0) ? ppm : (-ppm);
		727	if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
		728	bestppm = 0;
		729	flag = 1;
		730	}
		731	if (absppm < bestppm - 10) {
		732	bestppm = absppm;
		733	flag = 1;
		734	}
		735	if (flag) {
		736	bestn = n;
		737	bestm1 = m1;
		738	bestm2 = m2;
		739	bestp1 = p1;
		740	bestp2 = p2;
		741	flag = 0;
		742	}
		743	}
		744	}
		745	}
		746	}
		747	}
		748	best_clock->n = bestn;
		749	best_clock->m1 = bestm1;
		750	best_clock->m2 = bestm2;
		751	best_clock->p1 = bestp1;
		752	best_clock->p2 = bestp2;
		753
		754	return true;
		755	}
		756
3243	Serge	757	enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
		758	enum pipe pipe)
		759	{
		760	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		761	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		762
3746	Serge	763	return intel_crtc->config.cpu_transcoder;
3243	Serge	764	}
		765
3031	serge	766	static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
		767	{
		768	struct drm_i915_private *dev_priv = dev->dev_private;
		769	u32 frame, frame_reg = PIPEFRAME(pipe);
		770
		771	frame = I915_READ(frame_reg);
		772
		773	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		774	DRM_DEBUG_KMS("vblank wait timed out\n");
		775	}
		776
2327	Serge	777	/**
		778	* intel_wait_for_vblank - wait for vblank on a given pipe
		779	* @dev: drm device
		780	* @pipe: pipe to wait for
		781	*
		782	* Wait for vblank to occur on a given pipe. Needed for various bits of
		783	* mode setting code.
		784	*/
		785	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		786	{
		787	struct drm_i915_private *dev_priv = dev->dev_private;
		788	int pipestat_reg = PIPESTAT(pipe);
		789
3031	serge	790	if (INTEL_INFO(dev)->gen >= 5) {
		791	ironlake_wait_for_vblank(dev, pipe);
		792	return;
		793	}
		794
2327	Serge	795	/* Clear existing vblank status. Note this will clear any other
		796	* sticky status fields as well.
		797	*
		798	* This races with i915_driver_irq_handler() with the result
		799	* that either function could miss a vblank event. Here it is not
		800	* fatal, as we will either wait upon the next vblank interrupt or
		801	* timeout. Generally speaking intel_wait_for_vblank() is only
		802	* called during modeset at which time the GPU should be idle and
		803	* should not be performing page flips and thus not waiting on
		804	* vblanks...
		805	* Currently, the result of us stealing a vblank from the irq
		806	* handler is that a single frame will be skipped during swapbuffers.
		807	*/
		808	I915_WRITE(pipestat_reg,
		809	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		810
		811	/* Wait for vblank interrupt bit to set */
		812	if (wait_for(I915_READ(pipestat_reg) &
		813	PIPE_VBLANK_INTERRUPT_STATUS,
		814	50))
		815	DRM_DEBUG_KMS("vblank wait timed out\n");
		816	}
		817
		818	/*
		819	* intel_wait_for_pipe_off - wait for pipe to turn off
		820	* @dev: drm device
		821	* @pipe: pipe to wait for
		822	*
		823	* After disabling a pipe, we can't wait for vblank in the usual way,
		824	* spinning on the vblank interrupt status bit, since we won't actually
		825	* see an interrupt when the pipe is disabled.
		826	*
		827	* On Gen4 and above:
		828	* wait for the pipe register state bit to turn off
		829	*
		830	* Otherwise:
		831	* wait for the display line value to settle (it usually
		832	* ends up stopping at the start of the next frame).
		833	*
		834	*/
		835	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		836	{
		837	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	838	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		839	pipe);
2327	Serge	840
		841	if (INTEL_INFO(dev)->gen >= 4) {
3243	Serge	842	int reg = PIPECONF(cpu_transcoder);
2327	Serge	843
		844	/* Wait for the Pipe State to go off */
		845	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		846	100))
3031	serge	847	WARN(1, "pipe_off wait timed out\n");
2327	Serge	848	} else {
3031	serge	849	u32 last_line, line_mask;
2327	Serge	850	int reg = PIPEDSL(pipe);
4104	Serge	851	unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
2327	Serge	852
3031	serge	853	if (IS_GEN2(dev))
		854	line_mask = DSL_LINEMASK_GEN2;
		855	else
		856	line_mask = DSL_LINEMASK_GEN3;
		857
2327	Serge	858	/* Wait for the display line to settle */
		859	do {
3031	serge	860	last_line = I915_READ(reg) & line_mask;
2327	Serge	861	mdelay(5);
3031	serge	862	} while (((I915_READ(reg) & line_mask) != last_line) &&
		863	time_after(timeout, GetTimerTicks()));
		864	if (time_after(GetTimerTicks(), timeout))
		865	WARN(1, "pipe_off wait timed out\n");
2327	Serge	866	}
		867	}
		868
3480	Serge	869	/*
		870	* ibx_digital_port_connected - is the specified port connected?
		871	* @dev_priv: i915 private structure
		872	* @port: the port to test
		873	*
		874	* Returns true if @port is connected, false otherwise.
		875	*/
		876	bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
		877	struct intel_digital_port *port)
		878	{
		879	u32 bit;
		880
		881	if (HAS_PCH_IBX(dev_priv->dev)) {
		882	switch(port->port) {
		883	case PORT_B:
		884	bit = SDE_PORTB_HOTPLUG;
		885	break;
		886	case PORT_C:
		887	bit = SDE_PORTC_HOTPLUG;
		888	break;
		889	case PORT_D:
		890	bit = SDE_PORTD_HOTPLUG;
		891	break;
		892	default:
		893	return true;
		894	}
		895	} else {
		896	switch(port->port) {
		897	case PORT_B:
		898	bit = SDE_PORTB_HOTPLUG_CPT;
		899	break;
		900	case PORT_C:
		901	bit = SDE_PORTC_HOTPLUG_CPT;
		902	break;
		903	case PORT_D:
		904	bit = SDE_PORTD_HOTPLUG_CPT;
		905	break;
		906	default:
		907	return true;
		908	}
		909	}
		910
		911	return I915_READ(SDEISR) & bit;
		912	}
		913
2327	Serge	914	static const char *state_string(bool enabled)
		915	{
		916	return enabled ? "on" : "off";
		917	}
		918
		919	/* Only for pre-ILK configs */
4104	Serge	920	void assert_pll(struct drm_i915_private *dev_priv,
2327	Serge	921	enum pipe pipe, bool state)
		922	{
		923	int reg;
		924	u32 val;
		925	bool cur_state;
		926
		927	reg = DPLL(pipe);
		928	val = I915_READ(reg);
		929	cur_state = !!(val & DPLL_VCO_ENABLE);
		930	WARN(cur_state != state,
		931	"PLL state assertion failure (expected %s, current %s)\n",
		932	state_string(state), state_string(cur_state));
		933	}
		934
4104	Serge	935	struct intel_shared_dpll *
		936	intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
		937	{
		938	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		939
		940	if (crtc->config.shared_dpll < 0)
		941	return NULL;
		942
		943	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
		944	}
		945
2327	Serge	946	/* For ILK+ */
4104	Serge	947	void assert_shared_dpll(struct drm_i915_private *dev_priv,
		948	struct intel_shared_dpll *pll,
3031	serge	949	bool state)
2327	Serge	950	{
		951	bool cur_state;
4104	Serge	952	struct intel_dpll_hw_state hw_state;
2327	Serge	953
3031	serge	954	if (HAS_PCH_LPT(dev_priv->dev)) {
		955	DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		956	return;
		957	}
2342	Serge	958
3031	serge	959	if (WARN (!pll,
4104	Serge	960	"asserting DPLL %s with no DPLL\n", state_string(state)))
3031	serge	961	return;
2342	Serge	962
4104	Serge	963	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
3031	serge	964	WARN(cur_state != state,
4104	Serge	965	"%s assertion failure (expected %s, current %s)\n",
		966	pll->name, state_string(state), state_string(cur_state));
2327	Serge	967	}
		968
		969	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		970	enum pipe pipe, bool state)
		971	{
		972	int reg;
		973	u32 val;
		974	bool cur_state;
3243	Serge	975	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		976	pipe);
2327	Serge	977
3480	Serge	978	if (HAS_DDI(dev_priv->dev)) {
		979	/* DDI does not have a specific FDI_TX register */
3243	Serge	980	reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3031	serge	981	val = I915_READ(reg);
3243	Serge	982	cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
3031	serge	983	} else {
2327	Serge	984	reg = FDI_TX_CTL(pipe);
		985	val = I915_READ(reg);
		986	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	987	}
2327	Serge	988	WARN(cur_state != state,
		989	"FDI TX state assertion failure (expected %s, current %s)\n",
		990	state_string(state), state_string(cur_state));
		991	}
		992	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		993	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		994
		995	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		996	enum pipe pipe, bool state)
		997	{
		998	int reg;
		999	u32 val;
		1000	bool cur_state;
		1001
		1002	reg = FDI_RX_CTL(pipe);
		1003	val = I915_READ(reg);
		1004	cur_state = !!(val & FDI_RX_ENABLE);
		1005	WARN(cur_state != state,
		1006	"FDI RX state assertion failure (expected %s, current %s)\n",
		1007	state_string(state), state_string(cur_state));
		1008	}
		1009	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1010	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1011
		1012	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1013	enum pipe pipe)
		1014	{
		1015	int reg;
		1016	u32 val;
		1017
		1018	/* ILK FDI PLL is always enabled */
		1019	if (dev_priv->info->gen == 5)
		1020	return;
		1021
3031	serge	1022	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
3480	Serge	1023	if (HAS_DDI(dev_priv->dev))
3031	serge	1024	return;
		1025
2327	Serge	1026	reg = FDI_TX_CTL(pipe);
		1027	val = I915_READ(reg);
		1028	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		1029	}
		1030
4104	Serge	1031	void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		1032	enum pipe pipe, bool state)
2327	Serge	1033	{
		1034	int reg;
		1035	u32 val;
4104	Serge	1036	bool cur_state;
2327	Serge	1037
		1038	reg = FDI_RX_CTL(pipe);
		1039	val = I915_READ(reg);
4104	Serge	1040	cur_state = !!(val & FDI_RX_PLL_ENABLE);
		1041	WARN(cur_state != state,
		1042	"FDI RX PLL assertion failure (expected %s, current %s)\n",
		1043	state_string(state), state_string(cur_state));
2327	Serge	1044	}
		1045
		1046	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		1047	enum pipe pipe)
		1048	{
		1049	int pp_reg, lvds_reg;
		1050	u32 val;
		1051	enum pipe panel_pipe = PIPE_A;
		1052	bool locked = true;
		1053
		1054	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1055	pp_reg = PCH_PP_CONTROL;
		1056	lvds_reg = PCH_LVDS;
		1057	} else {
		1058	pp_reg = PP_CONTROL;
		1059	lvds_reg = LVDS;
		1060	}
		1061
		1062	val = I915_READ(pp_reg);
		1063	if (!(val & PANEL_POWER_ON) \|\|
		1064	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		1065	locked = false;
		1066
		1067	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		1068	panel_pipe = PIPE_B;
		1069
		1070	WARN(panel_pipe == pipe && locked,
		1071	"panel assertion failure, pipe %c regs locked\n",
		1072	pipe_name(pipe));
		1073	}
		1074
2342	Serge	1075	void assert_pipe(struct drm_i915_private *dev_priv,
2327	Serge	1076	enum pipe pipe, bool state)
		1077	{
		1078	int reg;
		1079	u32 val;
		1080	bool cur_state;
3243	Serge	1081	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1082	pipe);
2327	Serge	1083
3031	serge	1084	/* if we need the pipe A quirk it must be always on */
		1085	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		1086	state = true;
		1087
4104	Serge	1088	if (!intel_display_power_enabled(dev_priv->dev,
		1089	POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
3480	Serge	1090	cur_state = false;
		1091	} else {
3243	Serge	1092	reg = PIPECONF(cpu_transcoder);
2327	Serge	1093	val = I915_READ(reg);
		1094	cur_state = !!(val & PIPECONF_ENABLE);
3480	Serge	1095	}
		1096
2327	Serge	1097	WARN(cur_state != state,
		1098	"pipe %c assertion failure (expected %s, current %s)\n",
		1099	pipe_name(pipe), state_string(state), state_string(cur_state));
		1100	}
		1101
3031	serge	1102	static void assert_plane(struct drm_i915_private *dev_priv,
		1103	enum plane plane, bool state)
2327	Serge	1104	{
		1105	int reg;
		1106	u32 val;
3031	serge	1107	bool cur_state;
2327	Serge	1108
		1109	reg = DSPCNTR(plane);
		1110	val = I915_READ(reg);
3031	serge	1111	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
		1112	WARN(cur_state != state,
		1113	"plane %c assertion failure (expected %s, current %s)\n",
		1114	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1115	}
		1116
3031	serge	1117	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1118	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1119
2327	Serge	1120	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1121	enum pipe pipe)
		1122	{
4104	Serge	1123	struct drm_device *dev = dev_priv->dev;
2327	Serge	1124	int reg, i;
		1125	u32 val;
		1126	int cur_pipe;
		1127
4104	Serge	1128	/* Primary planes are fixed to pipes on gen4+ */
		1129	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	1130	reg = DSPCNTR(pipe);
		1131	val = I915_READ(reg);
		1132	WARN((val & DISPLAY_PLANE_ENABLE),
		1133	"plane %c assertion failure, should be disabled but not\n",
		1134	plane_name(pipe));
2327	Serge	1135	return;
3031	serge	1136	}
2327	Serge	1137
		1138	/* Need to check both planes against the pipe */
4104	Serge	1139	for_each_pipe(i) {
2327	Serge	1140	reg = DSPCNTR(i);
		1141	val = I915_READ(reg);
		1142	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		1143	DISPPLANE_SEL_PIPE_SHIFT;
		1144	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		1145	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1146	plane_name(i), pipe_name(pipe));
		1147	}
		1148	}
		1149
3746	Serge	1150	static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
		1151	enum pipe pipe)
		1152	{
4104	Serge	1153	struct drm_device *dev = dev_priv->dev;
3746	Serge	1154	int reg, i;
		1155	u32 val;
		1156
4104	Serge	1157	if (IS_VALLEYVIEW(dev)) {
3746	Serge	1158	for (i = 0; i < dev_priv->num_plane; i++) {
		1159	reg = SPCNTR(pipe, i);
		1160	val = I915_READ(reg);
		1161	WARN((val & SP_ENABLE),
4104	Serge	1162	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1163	sprite_name(pipe, i), pipe_name(pipe));
		1164	}
		1165	} else if (INTEL_INFO(dev)->gen >= 7) {
		1166	reg = SPRCTL(pipe);
		1167	val = I915_READ(reg);
		1168	WARN((val & SPRITE_ENABLE),
		1169	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1170	plane_name(pipe), pipe_name(pipe));
		1171	} else if (INTEL_INFO(dev)->gen >= 5) {
		1172	reg = DVSCNTR(pipe);
		1173	val = I915_READ(reg);
		1174	WARN((val & DVS_ENABLE),
		1175	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1176	plane_name(pipe), pipe_name(pipe));
3746	Serge	1177	}
		1178	}
		1179
2327	Serge	1180	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		1181	{
		1182	u32 val;
		1183	bool enabled;
		1184
3031	serge	1185	if (HAS_PCH_LPT(dev_priv->dev)) {
		1186	DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		1187	return;
		1188	}
		1189
2327	Serge	1190	val = I915_READ(PCH_DREF_CONTROL);
		1191	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1192	DREF_SUPERSPREAD_SOURCE_MASK));
		1193	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		1194	}
		1195
4104	Serge	1196	static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
2327	Serge	1197	enum pipe pipe)
		1198	{
		1199	int reg;
		1200	u32 val;
		1201	bool enabled;
		1202
4104	Serge	1203	reg = PCH_TRANSCONF(pipe);
2327	Serge	1204	val = I915_READ(reg);
		1205	enabled = !!(val & TRANS_ENABLE);
		1206	WARN(enabled,
		1207	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1208	pipe_name(pipe));
		1209	}
		1210
		1211	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1212	enum pipe pipe, u32 port_sel, u32 val)
		1213	{
		1214	if ((val & DP_PORT_EN) == 0)
		1215	return false;
		1216
		1217	if (HAS_PCH_CPT(dev_priv->dev)) {
		1218	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1219	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1220	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1221	return false;
		1222	} else {
		1223	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1224	return false;
		1225	}
		1226	return true;
		1227	}
		1228
		1229	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1230	enum pipe pipe, u32 val)
		1231	{
3746	Serge	1232	if ((val & SDVO_ENABLE) == 0)
2327	Serge	1233	return false;
		1234
		1235	if (HAS_PCH_CPT(dev_priv->dev)) {
3746	Serge	1236	if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
2327	Serge	1237	return false;
		1238	} else {
3746	Serge	1239	if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
2327	Serge	1240	return false;
		1241	}
		1242	return true;
		1243	}
		1244
		1245	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1246	enum pipe pipe, u32 val)
		1247	{
		1248	if ((val & LVDS_PORT_EN) == 0)
		1249	return false;
		1250
		1251	if (HAS_PCH_CPT(dev_priv->dev)) {
		1252	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1253	return false;
		1254	} else {
		1255	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1256	return false;
		1257	}
		1258	return true;
		1259	}
		1260
		1261	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1262	enum pipe pipe, u32 val)
		1263	{
		1264	if ((val & ADPA_DAC_ENABLE) == 0)
		1265	return false;
		1266	if (HAS_PCH_CPT(dev_priv->dev)) {
		1267	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1268	return false;
		1269	} else {
		1270	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1271	return false;
		1272	}
		1273	return true;
		1274	}
		1275
		1276	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1277	enum pipe pipe, int reg, u32 port_sel)
		1278	{
		1279	u32 val = I915_READ(reg);
		1280	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1281	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1282	reg, pipe_name(pipe));
3031	serge	1283
		1284	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
		1285	&& (val & DP_PIPEB_SELECT),
		1286	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1287	}
		1288
		1289	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1290	enum pipe pipe, int reg)
		1291	{
		1292	u32 val = I915_READ(reg);
3031	serge	1293	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
		1294	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1295	reg, pipe_name(pipe));
3031	serge	1296
3746	Serge	1297	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
3031	serge	1298	&& (val & SDVO_PIPE_B_SELECT),
		1299	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1300	}
		1301
		1302	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1303	enum pipe pipe)
		1304	{
		1305	int reg;
		1306	u32 val;
		1307
		1308	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1309	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1310	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1311
		1312	reg = PCH_ADPA;
		1313	val = I915_READ(reg);
3031	serge	1314	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1315	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1316	pipe_name(pipe));
		1317
		1318	reg = PCH_LVDS;
		1319	val = I915_READ(reg);
3031	serge	1320	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1321	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1322	pipe_name(pipe));
		1323
3746	Serge	1324	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
		1325	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
		1326	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
2327	Serge	1327	}
		1328
4104	Serge	1329	static void vlv_enable_pll(struct intel_crtc *crtc)
2327	Serge	1330	{
4104	Serge	1331	struct drm_device *dev = crtc->base.dev;
		1332	struct drm_i915_private *dev_priv = dev->dev_private;
		1333	int reg = DPLL(crtc->pipe);
		1334	u32 dpll = crtc->config.dpll_hw_state.dpll;
2327	Serge	1335
4104	Serge	1336	assert_pipe_disabled(dev_priv, crtc->pipe);
		1337
2327	Serge	1338	/* No really, not for ILK+ */
4104	Serge	1339	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
2327	Serge	1340
		1341	/* PLL is protected by panel, make sure we can write it */
		1342	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
4104	Serge	1343	assert_panel_unlocked(dev_priv, crtc->pipe);
2327	Serge	1344
4104	Serge	1345	I915_WRITE(reg, dpll);
		1346	POSTING_READ(reg);
		1347	udelay(150);
2327	Serge	1348
4104	Serge	1349	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		1350	DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
		1351
		1352	I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
		1353	POSTING_READ(DPLL_MD(crtc->pipe));
		1354
		1355	/* We do this three times for luck */
		1356	I915_WRITE(reg, dpll);
		1357	POSTING_READ(reg);
		1358	udelay(150); /* wait for warmup */
		1359	I915_WRITE(reg, dpll);
		1360	POSTING_READ(reg);
		1361	udelay(150); /* wait for warmup */
		1362	I915_WRITE(reg, dpll);
		1363	POSTING_READ(reg);
		1364	udelay(150); /* wait for warmup */
		1365	}
		1366
		1367	static void i9xx_enable_pll(struct intel_crtc *crtc)
		1368	{
		1369	struct drm_device *dev = crtc->base.dev;
		1370	struct drm_i915_private *dev_priv = dev->dev_private;
		1371	int reg = DPLL(crtc->pipe);
		1372	u32 dpll = crtc->config.dpll_hw_state.dpll;
		1373
		1374	assert_pipe_disabled(dev_priv, crtc->pipe);
		1375
		1376	/* No really, not for ILK+ */
		1377	BUG_ON(dev_priv->info->gen >= 5);
		1378
		1379	/* PLL is protected by panel, make sure we can write it */
		1380	if (IS_MOBILE(dev) && !IS_I830(dev))
		1381	assert_panel_unlocked(dev_priv, crtc->pipe);
		1382
		1383	I915_WRITE(reg, dpll);
		1384
		1385	/* Wait for the clocks to stabilize. */
		1386	POSTING_READ(reg);
		1387	udelay(150);
		1388
		1389	if (INTEL_INFO(dev)->gen >= 4) {
		1390	I915_WRITE(DPLL_MD(crtc->pipe),
		1391	crtc->config.dpll_hw_state.dpll_md);
		1392	} else {
		1393	/* The pixel multiplier can only be updated once the
		1394	* DPLL is enabled and the clocks are stable.
		1395	*
		1396	* So write it again.
		1397	*/
		1398	I915_WRITE(reg, dpll);
		1399	}
		1400
2327	Serge	1401	/* We do this three times for luck */
4104	Serge	1402	I915_WRITE(reg, dpll);
2327	Serge	1403	POSTING_READ(reg);
		1404	udelay(150); /* wait for warmup */
4104	Serge	1405	I915_WRITE(reg, dpll);
2327	Serge	1406	POSTING_READ(reg);
		1407	udelay(150); /* wait for warmup */
4104	Serge	1408	I915_WRITE(reg, dpll);
2327	Serge	1409	POSTING_READ(reg);
		1410	udelay(150); /* wait for warmup */
		1411	}
		1412
		1413	/**
4104	Serge	1414	* i9xx_disable_pll - disable a PLL
2327	Serge	1415	* @dev_priv: i915 private structure
		1416	* @pipe: pipe PLL to disable
		1417	*
		1418	* Disable the PLL for @pipe, making sure the pipe is off first.
		1419	*
		1420	* Note! This is for pre-ILK only.
		1421	*/
4104	Serge	1422	static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2327	Serge	1423	{
		1424	/* Don't disable pipe A or pipe A PLLs if needed */
		1425	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1426	return;
		1427
		1428	/* Make sure the pipe isn't still relying on us */
		1429	assert_pipe_disabled(dev_priv, pipe);
		1430
4104	Serge	1431	I915_WRITE(DPLL(pipe), 0);
		1432	POSTING_READ(DPLL(pipe));
2327	Serge	1433	}
		1434
4104	Serge	1435	void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
3031	serge	1436	{
4104	Serge	1437	u32 port_mask;
3031	serge	1438
4104	Serge	1439	if (!port)
		1440	port_mask = DPLL_PORTB_READY_MASK;
3243	Serge	1441	else
4104	Serge	1442	port_mask = DPLL_PORTC_READY_MASK;
3243	Serge	1443
4104	Serge	1444	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
		1445	WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
		1446	'B' + port, I915_READ(DPLL(0)));
3031	serge	1447	}
		1448
2327	Serge	1449	/**
4104	Serge	1450	* ironlake_enable_shared_dpll - enable PCH PLL
2327	Serge	1451	* @dev_priv: i915 private structure
		1452	* @pipe: pipe PLL to enable
		1453	*
		1454	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1455	* drives the transcoder clock.
		1456	*/
4104	Serge	1457	static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1458	{
4104	Serge	1459	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1460	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1461
3031	serge	1462	/* PCH PLLs only available on ILK, SNB and IVB */
		1463	BUG_ON(dev_priv->info->gen < 5);
4104	Serge	1464	if (WARN_ON(pll == NULL))
2342	Serge	1465	return;
		1466
3031	serge	1467	if (WARN_ON(pll->refcount == 0))
		1468	return;
2327	Serge	1469
4104	Serge	1470	DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
		1471	pll->name, pll->active, pll->on,
		1472	crtc->base.base.id);
3031	serge	1473
4104	Serge	1474	if (pll->active++) {
		1475	WARN_ON(!pll->on);
		1476	assert_shared_dpll_enabled(dev_priv, pll);
3031	serge	1477	return;
		1478	}
4104	Serge	1479	WARN_ON(pll->on);
3031	serge	1480
4104	Serge	1481	DRM_DEBUG_KMS("enabling %s\n", pll->name);
		1482	pll->enable(dev_priv, pll);
3031	serge	1483	pll->on = true;
2327	Serge	1484	}
		1485
4104	Serge	1486	static void intel_disable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1487	{
4104	Serge	1488	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1489	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1490
		1491	/* PCH only available on ILK+ */
		1492	BUG_ON(dev_priv->info->gen < 5);
4104	Serge	1493	if (WARN_ON(pll == NULL))
3031	serge	1494	return;
2327	Serge	1495
3031	serge	1496	if (WARN_ON(pll->refcount == 0))
		1497	return;
2327	Serge	1498
4104	Serge	1499	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
		1500	pll->name, pll->active, pll->on,
		1501	crtc->base.base.id);
2342	Serge	1502
3031	serge	1503	if (WARN_ON(pll->active == 0)) {
4104	Serge	1504	assert_shared_dpll_disabled(dev_priv, pll);
3031	serge	1505	return;
		1506	}
2342	Serge	1507
4104	Serge	1508	assert_shared_dpll_enabled(dev_priv, pll);
		1509	WARN_ON(!pll->on);
		1510	if (--pll->active)
2342	Serge	1511	return;
		1512
4104	Serge	1513	DRM_DEBUG_KMS("disabling %s\n", pll->name);
		1514	pll->disable(dev_priv, pll);
3031	serge	1515	pll->on = false;
2327	Serge	1516	}
		1517
3243	Serge	1518	static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1519	enum pipe pipe)
		1520	{
3243	Serge	1521	struct drm_device *dev = dev_priv->dev;
3031	serge	1522	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4104	Serge	1523	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	1524	uint32_t reg, val, pipeconf_val;
2327	Serge	1525
		1526	/* PCH only available on ILK+ */
		1527	BUG_ON(dev_priv->info->gen < 5);
		1528
		1529	/* Make sure PCH DPLL is enabled */
4104	Serge	1530	assert_shared_dpll_enabled(dev_priv,
		1531	intel_crtc_to_shared_dpll(intel_crtc));
2327	Serge	1532
		1533	/* FDI must be feeding us bits for PCH ports */
		1534	assert_fdi_tx_enabled(dev_priv, pipe);
		1535	assert_fdi_rx_enabled(dev_priv, pipe);
		1536
3243	Serge	1537	if (HAS_PCH_CPT(dev)) {
		1538	/* Workaround: Set the timing override bit before enabling the
		1539	* pch transcoder. */
		1540	reg = TRANS_CHICKEN2(pipe);
		1541	val = I915_READ(reg);
		1542	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1543	I915_WRITE(reg, val);
3031	serge	1544	}
3243	Serge	1545
4104	Serge	1546	reg = PCH_TRANSCONF(pipe);
2327	Serge	1547	val = I915_READ(reg);
3031	serge	1548	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1549
		1550	if (HAS_PCH_IBX(dev_priv->dev)) {
		1551	/*
		1552	* make the BPC in transcoder be consistent with
		1553	* that in pipeconf reg.
		1554	*/
3480	Serge	1555	val &= ~PIPECONF_BPC_MASK;
		1556	val \|= pipeconf_val & PIPECONF_BPC_MASK;
2327	Serge	1557	}
3031	serge	1558
		1559	val &= ~TRANS_INTERLACE_MASK;
		1560	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		1561	if (HAS_PCH_IBX(dev_priv->dev) &&
		1562	intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
		1563	val \|= TRANS_LEGACY_INTERLACED_ILK;
		1564	else
		1565	val \|= TRANS_INTERLACED;
		1566	else
		1567	val \|= TRANS_PROGRESSIVE;
		1568
2327	Serge	1569	I915_WRITE(reg, val \| TRANS_ENABLE);
		1570	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4104	Serge	1571	DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2327	Serge	1572	}
		1573
3243	Serge	1574	static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
		1575	enum transcoder cpu_transcoder)
		1576	{
		1577	u32 val, pipeconf_val;
		1578
		1579	/* PCH only available on ILK+ */
		1580	BUG_ON(dev_priv->info->gen < 5);
		1581
		1582	/* FDI must be feeding us bits for PCH ports */
3480	Serge	1583	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
3243	Serge	1584	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
		1585
		1586	/* Workaround: set timing override bit. */
		1587	val = I915_READ(_TRANSA_CHICKEN2);
		1588	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1589	I915_WRITE(_TRANSA_CHICKEN2, val);
		1590
		1591	val = TRANS_ENABLE;
		1592	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
		1593
		1594	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
		1595	PIPECONF_INTERLACED_ILK)
		1596	val \|= TRANS_INTERLACED;
		1597	else
		1598	val \|= TRANS_PROGRESSIVE;
		1599
4104	Serge	1600	I915_WRITE(LPT_TRANSCONF, val);
		1601	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
3243	Serge	1602	DRM_ERROR("Failed to enable PCH transcoder\n");
		1603	}
		1604
		1605	static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1606	enum pipe pipe)
		1607	{
3243	Serge	1608	struct drm_device *dev = dev_priv->dev;
		1609	uint32_t reg, val;
2327	Serge	1610
		1611	/* FDI relies on the transcoder */
		1612	assert_fdi_tx_disabled(dev_priv, pipe);
		1613	assert_fdi_rx_disabled(dev_priv, pipe);
		1614
		1615	/* Ports must be off as well */
		1616	assert_pch_ports_disabled(dev_priv, pipe);
		1617
4104	Serge	1618	reg = PCH_TRANSCONF(pipe);
2327	Serge	1619	val = I915_READ(reg);
		1620	val &= ~TRANS_ENABLE;
		1621	I915_WRITE(reg, val);
		1622	/* wait for PCH transcoder off, transcoder state */
		1623	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4104	Serge	1624	DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
3243	Serge	1625
		1626	if (!HAS_PCH_IBX(dev)) {
		1627	/* Workaround: Clear the timing override chicken bit again. */
		1628	reg = TRANS_CHICKEN2(pipe);
		1629	val = I915_READ(reg);
		1630	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1631	I915_WRITE(reg, val);
		1632	}
2327	Serge	1633	}
		1634
3243	Serge	1635	static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
		1636	{
		1637	u32 val;
		1638
4104	Serge	1639	val = I915_READ(LPT_TRANSCONF);
3243	Serge	1640	val &= ~TRANS_ENABLE;
4104	Serge	1641	I915_WRITE(LPT_TRANSCONF, val);
3243	Serge	1642	/* wait for PCH transcoder off, transcoder state */
4104	Serge	1643	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
3243	Serge	1644	DRM_ERROR("Failed to disable PCH transcoder\n");
		1645
		1646	/* Workaround: clear timing override bit. */
		1647	val = I915_READ(_TRANSA_CHICKEN2);
		1648	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1649	I915_WRITE(_TRANSA_CHICKEN2, val);
		1650	}
		1651
2327	Serge	1652	/**
		1653	* intel_enable_pipe - enable a pipe, asserting requirements
		1654	* @dev_priv: i915 private structure
		1655	* @pipe: pipe to enable
		1656	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1657	*
		1658	* Enable @pipe, making sure that various hardware specific requirements
		1659	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1660	*
		1661	* @pipe should be %PIPE_A or %PIPE_B.
		1662	*
		1663	* Will wait until the pipe is actually running (i.e. first vblank) before
		1664	* returning.
		1665	*/
		1666	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1667	bool pch_port)
		1668	{
3243	Serge	1669	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1670	pipe);
3480	Serge	1671	enum pipe pch_transcoder;
2327	Serge	1672	int reg;
		1673	u32 val;
		1674
4104	Serge	1675	assert_planes_disabled(dev_priv, pipe);
		1676	assert_sprites_disabled(dev_priv, pipe);
		1677
3480	Serge	1678	if (HAS_PCH_LPT(dev_priv->dev))
3243	Serge	1679	pch_transcoder = TRANSCODER_A;
		1680	else
		1681	pch_transcoder = pipe;
		1682
2327	Serge	1683	/*
		1684	* A pipe without a PLL won't actually be able to drive bits from
		1685	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1686	* need the check.
		1687	*/
		1688	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1689	assert_pll_enabled(dev_priv, pipe);
		1690	else {
		1691	if (pch_port) {
		1692	/* if driving the PCH, we need FDI enabled */
3243	Serge	1693	assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
3480	Serge	1694	assert_fdi_tx_pll_enabled(dev_priv,
		1695	(enum pipe) cpu_transcoder);
2327	Serge	1696	}
		1697	/* FIXME: assert CPU port conditions for SNB+ */
		1698	}
		1699
3243	Serge	1700	reg = PIPECONF(cpu_transcoder);
2327	Serge	1701	val = I915_READ(reg);
		1702	if (val & PIPECONF_ENABLE)
		1703	return;
		1704
		1705	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1706	intel_wait_for_vblank(dev_priv->dev, pipe);
		1707	}
		1708
		1709	/**
		1710	* intel_disable_pipe - disable a pipe, asserting requirements
		1711	* @dev_priv: i915 private structure
		1712	* @pipe: pipe to disable
		1713	*
		1714	* Disable @pipe, making sure that various hardware specific requirements
		1715	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1716	*
		1717	* @pipe should be %PIPE_A or %PIPE_B.
		1718	*
		1719	* Will wait until the pipe has shut down before returning.
		1720	*/
		1721	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1722	enum pipe pipe)
		1723	{
3243	Serge	1724	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1725	pipe);
2327	Serge	1726	int reg;
		1727	u32 val;
		1728
3031	serge	1729	/*
2327	Serge	1730	* Make sure planes won't keep trying to pump pixels to us,
		1731	* or we might hang the display.
		1732	*/
		1733	assert_planes_disabled(dev_priv, pipe);
3746	Serge	1734	assert_sprites_disabled(dev_priv, pipe);
2327	Serge	1735
		1736	/* Don't disable pipe A or pipe A PLLs if needed */
		1737	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1738	return;
		1739
3243	Serge	1740	reg = PIPECONF(cpu_transcoder);
2327	Serge	1741	val = I915_READ(reg);
		1742	if ((val & PIPECONF_ENABLE) == 0)
		1743	return;
		1744
		1745	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1746	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		1747	}
		1748
		1749	/*
		1750	* Plane regs are double buffered, going from enabled->disabled needs a
		1751	* trigger in order to latch. The display address reg provides this.
		1752	*/
3031	serge	1753	void intel_flush_display_plane(struct drm_i915_private *dev_priv,
2327	Serge	1754	enum plane plane)
		1755	{
3243	Serge	1756	if (dev_priv->info->gen >= 4)
		1757	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1758	else
2327	Serge	1759	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1760	}
		1761
		1762	/**
		1763	* intel_enable_plane - enable a display plane on a given pipe
		1764	* @dev_priv: i915 private structure
		1765	* @plane: plane to enable
		1766	* @pipe: pipe being fed
		1767	*
		1768	* Enable @plane on @pipe, making sure that @pipe is running first.
		1769	*/
		1770	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1771	enum plane plane, enum pipe pipe)
		1772	{
		1773	int reg;
		1774	u32 val;
		1775
		1776	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1777	assert_pipe_enabled(dev_priv, pipe);
		1778
		1779	reg = DSPCNTR(plane);
		1780	val = I915_READ(reg);
		1781	if (val & DISPLAY_PLANE_ENABLE)
		1782	return;
		1783
		1784	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1785	intel_flush_display_plane(dev_priv, plane);
		1786	intel_wait_for_vblank(dev_priv->dev, pipe);
		1787	}
		1788
		1789	/**
		1790	* intel_disable_plane - disable a display plane
		1791	* @dev_priv: i915 private structure
		1792	* @plane: plane to disable
		1793	* @pipe: pipe consuming the data
		1794	*
		1795	* Disable @plane; should be an independent operation.
		1796	*/
		1797	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1798	enum plane plane, enum pipe pipe)
		1799	{
		1800	int reg;
		1801	u32 val;
		1802
		1803	reg = DSPCNTR(plane);
		1804	val = I915_READ(reg);
		1805	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1806	return;
		1807
		1808	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1809	intel_flush_display_plane(dev_priv, plane);
3031	serge	1810	intel_wait_for_vblank(dev_priv->dev, pipe);
2327	Serge	1811	}
		1812
3746	Serge	1813	static bool need_vtd_wa(struct drm_device *dev)
		1814	{
		1815	#ifdef CONFIG_INTEL_IOMMU
		1816	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		1817	return true;
		1818	#endif
		1819	return false;
		1820	}
		1821
2335	Serge	1822	int
		1823	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1824	struct drm_i915_gem_object *obj,
		1825	struct intel_ring_buffer *pipelined)
		1826	{
		1827	struct drm_i915_private *dev_priv = dev->dev_private;
		1828	u32 alignment;
		1829	int ret;
2327	Serge	1830
2335	Serge	1831	switch (obj->tiling_mode) {
		1832	case I915_TILING_NONE:
		1833	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		1834	alignment = 128 * 1024;
		1835	else if (INTEL_INFO(dev)->gen >= 4)
		1836	alignment = 4 * 1024;
		1837	else
		1838	alignment = 64 * 1024;
		1839	break;
		1840	case I915_TILING_X:
		1841	/* pin() will align the object as required by fence */
		1842	alignment = 0;
		1843	break;
		1844	case I915_TILING_Y:
3746	Serge	1845	/* Despite that we check this in framebuffer_init userspace can
		1846	* screw us over and change the tiling after the fact. Only
		1847	* pinned buffers can't change their tiling. */
		1848	DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2335	Serge	1849	return -EINVAL;
		1850	default:
		1851	BUG();
		1852	}
2327	Serge	1853
3746	Serge	1854	/* Note that the w/a also requires 64 PTE of padding following the
		1855	* bo. We currently fill all unused PTE with the shadow page and so
		1856	* we should always have valid PTE following the scanout preventing
		1857	* the VT-d warning.
		1858	*/
		1859	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		1860	alignment = 256 * 1024;
		1861
2335	Serge	1862	dev_priv->mm.interruptible = false;
		1863	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		1864	if (ret)
		1865	goto err_interruptible;
2327	Serge	1866
2335	Serge	1867	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		1868	* fence, whereas 965+ only requires a fence if using
		1869	* framebuffer compression. For simplicity, we always install
		1870	* a fence as the cost is not that onerous.
		1871	*/
3480	Serge	1872	ret = i915_gem_object_get_fence(obj);
		1873	if (ret)
		1874	goto err_unpin;
2327	Serge	1875
3480	Serge	1876	i915_gem_object_pin_fence(obj);
		1877
2335	Serge	1878	dev_priv->mm.interruptible = true;
		1879	return 0;
2327	Serge	1880
2335	Serge	1881	err_unpin:
4104	Serge	1882	i915_gem_object_unpin_from_display_plane(obj);
2335	Serge	1883	err_interruptible:
		1884	dev_priv->mm.interruptible = true;
		1885	return ret;
		1886	}
2327	Serge	1887
3031	serge	1888	void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
		1889	{
		1890	// i915_gem_object_unpin_fence(obj);
		1891	// i915_gem_object_unpin(obj);
		1892	}
		1893
		1894	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		1895	* is assumed to be a power-of-two. */
3480	Serge	1896	unsigned long intel_gen4_compute_page_offset(int x, int y,
		1897	unsigned int tiling_mode,
		1898	unsigned int cpp,
3031	serge	1899	unsigned int pitch)
		1900	{
3480	Serge	1901	if (tiling_mode != I915_TILING_NONE) {
		1902	unsigned int tile_rows, tiles;
3031	serge	1903
		1904	tile_rows = *y / 8;
		1905	*y %= 8;
		1906
3480	Serge	1907	tiles = *x / (512/cpp);
		1908	*x %= 512/cpp;
		1909
3031	serge	1910	return tile_rows * pitch * 8 + tiles * 4096;
3480	Serge	1911	} else {
		1912	unsigned int offset;
		1913
		1914	offset = y pitch + x cpp;
		1915	*y = 0;
		1916	*x = (offset & 4095) / cpp;
		1917	return offset & -4096;
		1918	}
3031	serge	1919	}
		1920
2327	Serge	1921	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		1922	int x, int y)
		1923	{
		1924	struct drm_device *dev = crtc->dev;
		1925	struct drm_i915_private *dev_priv = dev->dev_private;
		1926	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1927	struct intel_framebuffer *intel_fb;
		1928	struct drm_i915_gem_object *obj;
		1929	int plane = intel_crtc->plane;
3031	serge	1930	unsigned long linear_offset;
2327	Serge	1931	u32 dspcntr;
		1932	u32 reg;
		1933
		1934	switch (plane) {
		1935	case 0:
		1936	case 1:
		1937	break;
		1938	default:
4104	Serge	1939	DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2327	Serge	1940	return -EINVAL;
		1941	}
		1942
		1943	intel_fb = to_intel_framebuffer(fb);
		1944	obj = intel_fb->obj;
		1945
		1946	reg = DSPCNTR(plane);
		1947	dspcntr = I915_READ(reg);
		1948	/* Mask out pixel format bits in case we change it */
		1949	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	1950	switch (fb->pixel_format) {
		1951	case DRM_FORMAT_C8:
2327	Serge	1952	dspcntr \|= DISPPLANE_8BPP;
		1953	break;
3243	Serge	1954	case DRM_FORMAT_XRGB1555:
		1955	case DRM_FORMAT_ARGB1555:
		1956	dspcntr \|= DISPPLANE_BGRX555;
		1957	break;
		1958	case DRM_FORMAT_RGB565:
		1959	dspcntr \|= DISPPLANE_BGRX565;
		1960	break;
		1961	case DRM_FORMAT_XRGB8888:
		1962	case DRM_FORMAT_ARGB8888:
		1963	dspcntr \|= DISPPLANE_BGRX888;
		1964	break;
		1965	case DRM_FORMAT_XBGR8888:
		1966	case DRM_FORMAT_ABGR8888:
		1967	dspcntr \|= DISPPLANE_RGBX888;
		1968	break;
		1969	case DRM_FORMAT_XRGB2101010:
		1970	case DRM_FORMAT_ARGB2101010:
		1971	dspcntr \|= DISPPLANE_BGRX101010;
2327	Serge	1972	break;
3243	Serge	1973	case DRM_FORMAT_XBGR2101010:
		1974	case DRM_FORMAT_ABGR2101010:
		1975	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	1976	break;
		1977	default:
3746	Serge	1978	BUG();
2327	Serge	1979	}
3243	Serge	1980
2327	Serge	1981	if (INTEL_INFO(dev)->gen >= 4) {
		1982	if (obj->tiling_mode != I915_TILING_NONE)
		1983	dspcntr \|= DISPPLANE_TILED;
		1984	else
		1985	dspcntr &= ~DISPPLANE_TILED;
		1986	}
		1987
4104	Serge	1988	if (IS_G4X(dev))
		1989	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		1990
2327	Serge	1991	I915_WRITE(reg, dspcntr);
		1992
3031	serge	1993	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327	Serge	1994
3031	serge	1995	if (INTEL_INFO(dev)->gen >= 4) {
		1996	intel_crtc->dspaddr_offset =
3480	Serge	1997	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	1998	fb->bits_per_pixel / 8,
		1999	fb->pitches[0]);
		2000	linear_offset -= intel_crtc->dspaddr_offset;
		2001	} else {
		2002	intel_crtc->dspaddr_offset = linear_offset;
		2003	}
		2004
4104	Serge	2005	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2006	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2007	fb->pitches[0]);
2342	Serge	2008	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327	Serge	2009	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	2010	I915_MODIFY_DISPBASE(DSPSURF(plane),
4104	Serge	2011	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	2012	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2013	I915_WRITE(DSPLINOFF(plane), linear_offset);
2327	Serge	2014	} else
4104	Serge	2015	I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2327	Serge	2016	POSTING_READ(reg);
		2017
		2018	return 0;
		2019	}
		2020
		2021	static int ironlake_update_plane(struct drm_crtc *crtc,
		2022	struct drm_framebuffer *fb, int x, int y)
		2023	{
		2024	struct drm_device *dev = crtc->dev;
		2025	struct drm_i915_private *dev_priv = dev->dev_private;
		2026	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2027	struct intel_framebuffer *intel_fb;
		2028	struct drm_i915_gem_object *obj;
		2029	int plane = intel_crtc->plane;
3031	serge	2030	unsigned long linear_offset;
2327	Serge	2031	u32 dspcntr;
		2032	u32 reg;
		2033
		2034	switch (plane) {
		2035	case 0:
		2036	case 1:
2342	Serge	2037	case 2:
2327	Serge	2038	break;
		2039	default:
4104	Serge	2040	DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2327	Serge	2041	return -EINVAL;
		2042	}
		2043
		2044	intel_fb = to_intel_framebuffer(fb);
		2045	obj = intel_fb->obj;
		2046
		2047	reg = DSPCNTR(plane);
		2048	dspcntr = I915_READ(reg);
		2049	/* Mask out pixel format bits in case we change it */
		2050	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	2051	switch (fb->pixel_format) {
		2052	case DRM_FORMAT_C8:
2327	Serge	2053	dspcntr \|= DISPPLANE_8BPP;
		2054	break;
3243	Serge	2055	case DRM_FORMAT_RGB565:
		2056	dspcntr \|= DISPPLANE_BGRX565;
2327	Serge	2057	break;
3243	Serge	2058	case DRM_FORMAT_XRGB8888:
		2059	case DRM_FORMAT_ARGB8888:
		2060	dspcntr \|= DISPPLANE_BGRX888;
		2061	break;
		2062	case DRM_FORMAT_XBGR8888:
		2063	case DRM_FORMAT_ABGR8888:
		2064	dspcntr \|= DISPPLANE_RGBX888;
		2065	break;
		2066	case DRM_FORMAT_XRGB2101010:
		2067	case DRM_FORMAT_ARGB2101010:
		2068	dspcntr \|= DISPPLANE_BGRX101010;
		2069	break;
		2070	case DRM_FORMAT_XBGR2101010:
		2071	case DRM_FORMAT_ABGR2101010:
		2072	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	2073	break;
		2074	default:
3746	Serge	2075	BUG();
2327	Serge	2076	}
		2077
3480	Serge	2078	if (obj->tiling_mode != I915_TILING_NONE)
		2079	dspcntr \|= DISPPLANE_TILED;
		2080	else
2327	Serge	2081	dspcntr &= ~DISPPLANE_TILED;
		2082
4104	Serge	2083	if (IS_HASWELL(dev))
		2084	dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
		2085	else
2327	Serge	2086	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2087
		2088	I915_WRITE(reg, dspcntr);
		2089
3031	serge	2090	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
		2091	intel_crtc->dspaddr_offset =
3480	Serge	2092	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2093	fb->bits_per_pixel / 8,
		2094	fb->pitches[0]);
		2095	linear_offset -= intel_crtc->dspaddr_offset;
2327	Serge	2096
4104	Serge	2097	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2098	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2099	fb->pitches[0]);
2342	Serge	2100	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3031	serge	2101	I915_MODIFY_DISPBASE(DSPSURF(plane),
4104	Serge	2102	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3243	Serge	2103	if (IS_HASWELL(dev)) {
		2104	I915_WRITE(DSPOFFSET(plane), (y << 16) \| x);
		2105	} else {
2330	Serge	2106	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2107	I915_WRITE(DSPLINOFF(plane), linear_offset);
3243	Serge	2108	}
2330	Serge	2109	POSTING_READ(reg);
2327	Serge	2110
		2111	return 0;
		2112	}
		2113
		2114	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2115	static int
		2116	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2117	int x, int y, enum mode_set_atomic state)
		2118	{
		2119	struct drm_device *dev = crtc->dev;
		2120	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2121
		2122	if (dev_priv->display.disable_fbc)
		2123	dev_priv->display.disable_fbc(dev);
		2124	intel_increase_pllclock(crtc);
		2125
		2126	return dev_priv->display.update_plane(crtc, fb, x, y);
		2127	}
		2128
		2129	#if 0
4104	Serge	2130	void intel_display_handle_reset(struct drm_device *dev)
		2131	{
		2132	struct drm_i915_private *dev_priv = dev->dev_private;
		2133	struct drm_crtc *crtc;
		2134
		2135	/*
		2136	* Flips in the rings have been nuked by the reset,
		2137	* so complete all pending flips so that user space
		2138	* will get its events and not get stuck.
		2139	*
		2140	* Also update the base address of all primary
		2141	* planes to the the last fb to make sure we're
		2142	* showing the correct fb after a reset.
		2143	*
		2144	* Need to make two loops over the crtcs so that we
		2145	* don't try to grab a crtc mutex before the
		2146	* pending_flip_queue really got woken up.
		2147	*/
		2148
		2149	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		2150	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2151	enum plane plane = intel_crtc->plane;
		2152
		2153	intel_prepare_page_flip(dev, plane);
		2154	intel_finish_page_flip_plane(dev, plane);
		2155	}
		2156
		2157	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		2158	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2159
		2160	mutex_lock(&crtc->mutex);
		2161	if (intel_crtc->active)
		2162	dev_priv->display.update_plane(crtc, crtc->fb,
		2163	crtc->x, crtc->y);
		2164	mutex_unlock(&crtc->mutex);
		2165	}
		2166	}
		2167
3031	serge	2168	static int
		2169	intel_finish_fb(struct drm_framebuffer *old_fb)
		2170	{
		2171	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
		2172	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		2173	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	2174	int ret;
		2175
3031	serge	2176	/* Big Hammer, we also need to ensure that any pending
		2177	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2178	* current scanout is retired before unpinning the old
		2179	* framebuffer.
		2180	*
		2181	* This should only fail upon a hung GPU, in which case we
		2182	* can safely continue.
		2183	*/
		2184	dev_priv->mm.interruptible = false;
		2185	ret = i915_gem_object_finish_gpu(obj);
		2186	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	2187
3031	serge	2188	return ret;
2327	Serge	2189	}
4104	Serge	2190
		2191	static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
		2192	{
		2193	struct drm_device *dev = crtc->dev;
		2194	struct drm_i915_master_private *master_priv;
		2195	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2196
		2197	if (!dev->primary->master)
		2198	return;
		2199
		2200	master_priv = dev->primary->master->driver_priv;
		2201	if (!master_priv->sarea_priv)
		2202	return;
		2203
		2204	switch (intel_crtc->pipe) {
		2205	case 0:
		2206	master_priv->sarea_priv->pipeA_x = x;
		2207	master_priv->sarea_priv->pipeA_y = y;
		2208	break;
		2209	case 1:
		2210	master_priv->sarea_priv->pipeB_x = x;
		2211	master_priv->sarea_priv->pipeB_y = y;
		2212	break;
		2213	default:
		2214	break;
		2215	}
		2216	}
3031	serge	2217	#endif
2327	Serge	2218
		2219	static int
		2220	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
3031	serge	2221	struct drm_framebuffer *fb)
2327	Serge	2222	{
		2223	struct drm_device *dev = crtc->dev;
3031	serge	2224	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2225	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2226	struct drm_framebuffer *old_fb;
2342	Serge	2227	int ret;
2327	Serge	2228
		2229	/* no fb bound */
3031	serge	2230	if (!fb) {
2327	Serge	2231	DRM_ERROR("No FB bound\n");
		2232	return 0;
		2233	}
		2234
3746	Serge	2235	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
4104	Serge	2236	DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
		2237	plane_name(intel_crtc->plane),
3746	Serge	2238	INTEL_INFO(dev)->num_pipes);
2327	Serge	2239	return -EINVAL;
		2240	}
		2241
		2242	mutex_lock(&dev->struct_mutex);
3031	serge	2243	// ret = intel_pin_and_fence_fb_obj(dev,
		2244	// to_intel_framebuffer(fb)->obj,
		2245	// NULL);
		2246	// if (ret != 0) {
		2247	// mutex_unlock(&dev->struct_mutex);
		2248	// DRM_ERROR("pin & fence failed\n");
		2249	// return ret;
		2250	// }
2327	Serge	2251
3031	serge	2252
		2253	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2327	Serge	2254	if (ret) {
3031	serge	2255	intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2327	Serge	2256	mutex_unlock(&dev->struct_mutex);
		2257	DRM_ERROR("failed to update base address\n");
3243	Serge	2258	return ret;
2327	Serge	2259	}
		2260
3031	serge	2261	old_fb = crtc->fb;
		2262	crtc->fb = fb;
		2263	crtc->x = x;
		2264	crtc->y = y;
		2265
		2266	if (old_fb) {
4104	Serge	2267	if (intel_crtc->active && old_fb != fb)
3031	serge	2268	intel_wait_for_vblank(dev, intel_crtc->pipe);
		2269	intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
		2270	}
		2271
		2272	intel_update_fbc(dev);
4104	Serge	2273	intel_edp_psr_update(dev);
2336	Serge	2274	mutex_unlock(&dev->struct_mutex);
2327	Serge	2275
2336	Serge	2276	return 0;
2327	Serge	2277	}
		2278
		2279	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2280	{
		2281	struct drm_device *dev = crtc->dev;
		2282	struct drm_i915_private *dev_priv = dev->dev_private;
		2283	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2284	int pipe = intel_crtc->pipe;
		2285	u32 reg, temp;
		2286
		2287	/* enable normal train */
		2288	reg = FDI_TX_CTL(pipe);
		2289	temp = I915_READ(reg);
		2290	if (IS_IVYBRIDGE(dev)) {
		2291	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2292	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2293	} else {
		2294	temp &= ~FDI_LINK_TRAIN_NONE;
		2295	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2296	}
		2297	I915_WRITE(reg, temp);
		2298
		2299	reg = FDI_RX_CTL(pipe);
		2300	temp = I915_READ(reg);
		2301	if (HAS_PCH_CPT(dev)) {
		2302	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2303	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2304	} else {
		2305	temp &= ~FDI_LINK_TRAIN_NONE;
		2306	temp \|= FDI_LINK_TRAIN_NONE;
		2307	}
		2308	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2309
		2310	/* wait one idle pattern time */
		2311	POSTING_READ(reg);
		2312	udelay(1000);
		2313
		2314	/* IVB wants error correction enabled */
		2315	if (IS_IVYBRIDGE(dev))
		2316	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2317	FDI_FE_ERRC_ENABLE);
		2318	}
		2319
4104	Serge	2320	static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
		2321	{
		2322	return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
		2323	}
		2324
3243	Serge	2325	static void ivb_modeset_global_resources(struct drm_device *dev)
2327	Serge	2326	{
		2327	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2328	struct intel_crtc *pipe_B_crtc =
		2329	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		2330	struct intel_crtc *pipe_C_crtc =
		2331	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
		2332	uint32_t temp;
2327	Serge	2333
4104	Serge	2334	/*
		2335	* When everything is off disable fdi C so that we could enable fdi B
		2336	* with all lanes. Note that we don't care about enabled pipes without
		2337	* an enabled pch encoder.
		2338	*/
		2339	if (!pipe_has_enabled_pch(pipe_B_crtc) &&
		2340	!pipe_has_enabled_pch(pipe_C_crtc)) {
3243	Serge	2341	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		2342	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		2343
		2344	temp = I915_READ(SOUTH_CHICKEN1);
		2345	temp &= ~FDI_BC_BIFURCATION_SELECT;
		2346	DRM_DEBUG_KMS("disabling fdi C rx\n");
		2347	I915_WRITE(SOUTH_CHICKEN1, temp);
		2348	}
2327	Serge	2349	}
		2350
		2351	/* The FDI link training functions for ILK/Ibexpeak. */
		2352	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2353	{
		2354	struct drm_device *dev = crtc->dev;
		2355	struct drm_i915_private *dev_priv = dev->dev_private;
		2356	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2357	int pipe = intel_crtc->pipe;
		2358	int plane = intel_crtc->plane;
		2359	u32 reg, temp, tries;
		2360
		2361	/* FDI needs bits from pipe & plane first */
		2362	assert_pipe_enabled(dev_priv, pipe);
		2363	assert_plane_enabled(dev_priv, plane);
		2364
		2365	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2366	for train result */
		2367	reg = FDI_RX_IMR(pipe);
		2368	temp = I915_READ(reg);
		2369	temp &= ~FDI_RX_SYMBOL_LOCK;
		2370	temp &= ~FDI_RX_BIT_LOCK;
		2371	I915_WRITE(reg, temp);
		2372	I915_READ(reg);
		2373	udelay(150);
		2374
		2375	/* enable CPU FDI TX and PCH FDI RX */
		2376	reg = FDI_TX_CTL(pipe);
		2377	temp = I915_READ(reg);
4104	Serge	2378	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2379	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2380	temp &= ~FDI_LINK_TRAIN_NONE;
		2381	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2382	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2383
		2384	reg = FDI_RX_CTL(pipe);
		2385	temp = I915_READ(reg);
		2386	temp &= ~FDI_LINK_TRAIN_NONE;
		2387	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2388	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2389
		2390	POSTING_READ(reg);
		2391	udelay(150);
		2392
		2393	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2394	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2395	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2396	FDI_RX_PHASE_SYNC_POINTER_EN);
		2397
		2398	reg = FDI_RX_IIR(pipe);
		2399	for (tries = 0; tries < 5; tries++) {
		2400	temp = I915_READ(reg);
		2401	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2402
		2403	if ((temp & FDI_RX_BIT_LOCK)) {
		2404	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2405	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2406	break;
		2407	}
		2408	}
		2409	if (tries == 5)
		2410	DRM_ERROR("FDI train 1 fail!\n");
		2411
		2412	/* Train 2 */
		2413	reg = FDI_TX_CTL(pipe);
		2414	temp = I915_READ(reg);
		2415	temp &= ~FDI_LINK_TRAIN_NONE;
		2416	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2417	I915_WRITE(reg, temp);
		2418
		2419	reg = FDI_RX_CTL(pipe);
		2420	temp = I915_READ(reg);
		2421	temp &= ~FDI_LINK_TRAIN_NONE;
		2422	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2423	I915_WRITE(reg, temp);
		2424
		2425	POSTING_READ(reg);
		2426	udelay(150);
		2427
		2428	reg = FDI_RX_IIR(pipe);
		2429	for (tries = 0; tries < 5; tries++) {
		2430	temp = I915_READ(reg);
		2431	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2432
		2433	if (temp & FDI_RX_SYMBOL_LOCK) {
		2434	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2435	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2436	break;
		2437	}
		2438	}
		2439	if (tries == 5)
		2440	DRM_ERROR("FDI train 2 fail!\n");
		2441
		2442	DRM_DEBUG_KMS("FDI train done\n");
		2443
		2444	}
		2445
2342	Serge	2446	static const int snb_b_fdi_train_param[] = {
2327	Serge	2447	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2448	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2449	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2450	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2451	};
		2452
		2453	/* The FDI link training functions for SNB/Cougarpoint. */
		2454	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2455	{
		2456	struct drm_device *dev = crtc->dev;
		2457	struct drm_i915_private *dev_priv = dev->dev_private;
		2458	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2459	int pipe = intel_crtc->pipe;
3031	serge	2460	u32 reg, temp, i, retry;
2327	Serge	2461
		2462	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2463	for train result */
		2464	reg = FDI_RX_IMR(pipe);
		2465	temp = I915_READ(reg);
		2466	temp &= ~FDI_RX_SYMBOL_LOCK;
		2467	temp &= ~FDI_RX_BIT_LOCK;
		2468	I915_WRITE(reg, temp);
		2469
		2470	POSTING_READ(reg);
		2471	udelay(150);
		2472
		2473	/* enable CPU FDI TX and PCH FDI RX */
		2474	reg = FDI_TX_CTL(pipe);
		2475	temp = I915_READ(reg);
4104	Serge	2476	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2477	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2478	temp &= ~FDI_LINK_TRAIN_NONE;
		2479	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2480	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2481	/* SNB-B */
		2482	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2483	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2484
3243	Serge	2485	I915_WRITE(FDI_RX_MISC(pipe),
		2486	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2487
2327	Serge	2488	reg = FDI_RX_CTL(pipe);
		2489	temp = I915_READ(reg);
		2490	if (HAS_PCH_CPT(dev)) {
		2491	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2492	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2493	} else {
		2494	temp &= ~FDI_LINK_TRAIN_NONE;
		2495	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2496	}
		2497	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2498
		2499	POSTING_READ(reg);
		2500	udelay(150);
		2501
2342	Serge	2502	for (i = 0; i < 4; i++) {
2327	Serge	2503	reg = FDI_TX_CTL(pipe);
		2504	temp = I915_READ(reg);
		2505	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2506	temp \|= snb_b_fdi_train_param[i];
		2507	I915_WRITE(reg, temp);
		2508
		2509	POSTING_READ(reg);
		2510	udelay(500);
		2511
3031	serge	2512	for (retry = 0; retry < 5; retry++) {
2327	Serge	2513	reg = FDI_RX_IIR(pipe);
		2514	temp = I915_READ(reg);
		2515	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2516	if (temp & FDI_RX_BIT_LOCK) {
		2517	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2518	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2519	break;
		2520	}
3031	serge	2521	udelay(50);
		2522	}
		2523	if (retry < 5)
		2524	break;
2327	Serge	2525	}
		2526	if (i == 4)
		2527	DRM_ERROR("FDI train 1 fail!\n");
		2528
		2529	/* Train 2 */
		2530	reg = FDI_TX_CTL(pipe);
		2531	temp = I915_READ(reg);
		2532	temp &= ~FDI_LINK_TRAIN_NONE;
		2533	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2534	if (IS_GEN6(dev)) {
		2535	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2536	/* SNB-B */
		2537	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2538	}
		2539	I915_WRITE(reg, temp);
		2540
		2541	reg = FDI_RX_CTL(pipe);
		2542	temp = I915_READ(reg);
		2543	if (HAS_PCH_CPT(dev)) {
		2544	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2545	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2546	} else {
		2547	temp &= ~FDI_LINK_TRAIN_NONE;
		2548	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2549	}
		2550	I915_WRITE(reg, temp);
		2551
		2552	POSTING_READ(reg);
		2553	udelay(150);
		2554
2342	Serge	2555	for (i = 0; i < 4; i++) {
2327	Serge	2556	reg = FDI_TX_CTL(pipe);
		2557	temp = I915_READ(reg);
		2558	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2559	temp \|= snb_b_fdi_train_param[i];
		2560	I915_WRITE(reg, temp);
		2561
		2562	POSTING_READ(reg);
		2563	udelay(500);
		2564
3031	serge	2565	for (retry = 0; retry < 5; retry++) {
2327	Serge	2566	reg = FDI_RX_IIR(pipe);
		2567	temp = I915_READ(reg);
		2568	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2569	if (temp & FDI_RX_SYMBOL_LOCK) {
		2570	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2571	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2572	break;
		2573	}
3031	serge	2574	udelay(50);
		2575	}
		2576	if (retry < 5)
		2577	break;
2327	Serge	2578	}
		2579	if (i == 4)
		2580	DRM_ERROR("FDI train 2 fail!\n");
		2581
		2582	DRM_DEBUG_KMS("FDI train done.\n");
		2583	}
		2584
		2585	/* Manual link training for Ivy Bridge A0 parts */
		2586	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2587	{
		2588	struct drm_device *dev = crtc->dev;
		2589	struct drm_i915_private *dev_priv = dev->dev_private;
		2590	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2591	int pipe = intel_crtc->pipe;
4104	Serge	2592	u32 reg, temp, i, j;
2327	Serge	2593
		2594	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2595	for train result */
		2596	reg = FDI_RX_IMR(pipe);
		2597	temp = I915_READ(reg);
		2598	temp &= ~FDI_RX_SYMBOL_LOCK;
		2599	temp &= ~FDI_RX_BIT_LOCK;
		2600	I915_WRITE(reg, temp);
		2601
		2602	POSTING_READ(reg);
		2603	udelay(150);
		2604
3243	Serge	2605	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		2606	I915_READ(FDI_RX_IIR(pipe)));
		2607
4104	Serge	2608	/* Try each vswing and preemphasis setting twice before moving on */
		2609	for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
		2610	/* disable first in case we need to retry */
		2611	reg = FDI_TX_CTL(pipe);
		2612	temp = I915_READ(reg);
		2613	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2614	temp &= ~FDI_TX_ENABLE;
		2615	I915_WRITE(reg, temp);
		2616
		2617	reg = FDI_RX_CTL(pipe);
		2618	temp = I915_READ(reg);
		2619	temp &= ~FDI_LINK_TRAIN_AUTO;
		2620	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2621	temp &= ~FDI_RX_ENABLE;
		2622	I915_WRITE(reg, temp);
		2623
2327	Serge	2624	/* enable CPU FDI TX and PCH FDI RX */
		2625	reg = FDI_TX_CTL(pipe);
		2626	temp = I915_READ(reg);
4104	Serge	2627	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2628	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2629	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2630	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4104	Serge	2631	temp \|= snb_b_fdi_train_param[j/2];
2342	Serge	2632	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2633	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2634
3243	Serge	2635	I915_WRITE(FDI_RX_MISC(pipe),
		2636	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2637
2327	Serge	2638	reg = FDI_RX_CTL(pipe);
		2639	temp = I915_READ(reg);
		2640	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342	Serge	2641	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2642	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2643
		2644	POSTING_READ(reg);
4104	Serge	2645	udelay(1); /* should be 0.5us */
2327	Serge	2646
2342	Serge	2647	for (i = 0; i < 4; i++) {
2327	Serge	2648	reg = FDI_RX_IIR(pipe);
		2649	temp = I915_READ(reg);
		2650	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2651
		2652	if (temp & FDI_RX_BIT_LOCK \|\|
		2653	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2654	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
4104	Serge	2655	DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
		2656	i);
2327	Serge	2657	break;
		2658	}
4104	Serge	2659	udelay(1); /* should be 0.5us */
		2660	}
		2661	if (i == 4) {
		2662	DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
		2663	continue;
2327	Serge	2664	}
		2665
		2666	/* Train 2 */
		2667	reg = FDI_TX_CTL(pipe);
		2668	temp = I915_READ(reg);
		2669	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2670	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2671	I915_WRITE(reg, temp);
		2672
		2673	reg = FDI_RX_CTL(pipe);
		2674	temp = I915_READ(reg);
		2675	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2676	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2677	I915_WRITE(reg, temp);
		2678
		2679	POSTING_READ(reg);
4104	Serge	2680	udelay(2); /* should be 1.5us */
2327	Serge	2681
2342	Serge	2682	for (i = 0; i < 4; i++) {
2327	Serge	2683	reg = FDI_RX_IIR(pipe);
		2684	temp = I915_READ(reg);
		2685	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2686
4104	Serge	2687	if (temp & FDI_RX_SYMBOL_LOCK \|\|
		2688	(I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2327	Serge	2689	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
4104	Serge	2690	DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
		2691	i);
		2692	goto train_done;
2327	Serge	2693	}
4104	Serge	2694	udelay(2); /* should be 1.5us */
2327	Serge	2695	}
		2696	if (i == 4)
4104	Serge	2697	DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
		2698	}
2327	Serge	2699
4104	Serge	2700	train_done:
2327	Serge	2701	DRM_DEBUG_KMS("FDI train done.\n");
		2702	}
		2703
3031	serge	2704	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	2705	{
3031	serge	2706	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	2707	struct drm_i915_private *dev_priv = dev->dev_private;
		2708	int pipe = intel_crtc->pipe;
		2709	u32 reg, temp;
		2710
		2711
		2712	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2713	reg = FDI_RX_CTL(pipe);
		2714	temp = I915_READ(reg);
4104	Serge	2715	temp &= ~(FDI_DP_PORT_WIDTH_MASK \| (0x7 << 16));
		2716	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3480	Serge	2717	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2718	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2719
		2720	POSTING_READ(reg);
		2721	udelay(200);
		2722
		2723	/* Switch from Rawclk to PCDclk */
		2724	temp = I915_READ(reg);
		2725	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2726
		2727	POSTING_READ(reg);
		2728	udelay(200);
		2729
		2730	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2731	reg = FDI_TX_CTL(pipe);
		2732	temp = I915_READ(reg);
		2733	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2734	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2735
		2736	POSTING_READ(reg);
		2737	udelay(100);
		2738	}
		2739	}
		2740
3031	serge	2741	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		2742	{
		2743	struct drm_device *dev = intel_crtc->base.dev;
		2744	struct drm_i915_private *dev_priv = dev->dev_private;
		2745	int pipe = intel_crtc->pipe;
		2746	u32 reg, temp;
		2747
		2748	/* Switch from PCDclk to Rawclk */
		2749	reg = FDI_RX_CTL(pipe);
		2750	temp = I915_READ(reg);
		2751	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		2752
		2753	/* Disable CPU FDI TX PLL */
		2754	reg = FDI_TX_CTL(pipe);
		2755	temp = I915_READ(reg);
		2756	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		2757
		2758	POSTING_READ(reg);
		2759	udelay(100);
		2760
		2761	reg = FDI_RX_CTL(pipe);
		2762	temp = I915_READ(reg);
		2763	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		2764
		2765	/* Wait for the clocks to turn off. */
		2766	POSTING_READ(reg);
		2767	udelay(100);
		2768	}
		2769
2327	Serge	2770	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2771	{
		2772	struct drm_device *dev = crtc->dev;
		2773	struct drm_i915_private *dev_priv = dev->dev_private;
		2774	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2775	int pipe = intel_crtc->pipe;
		2776	u32 reg, temp;
		2777
		2778	/* disable CPU FDI tx and PCH FDI rx */
		2779	reg = FDI_TX_CTL(pipe);
		2780	temp = I915_READ(reg);
		2781	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2782	POSTING_READ(reg);
		2783
		2784	reg = FDI_RX_CTL(pipe);
		2785	temp = I915_READ(reg);
		2786	temp &= ~(0x7 << 16);
3480	Serge	2787	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2788	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2789
		2790	POSTING_READ(reg);
		2791	udelay(100);
		2792
		2793	/* Ironlake workaround, disable clock pointer after downing FDI */
		2794	if (HAS_PCH_IBX(dev)) {
		2795	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2796	}
		2797
		2798	/* still set train pattern 1 */
		2799	reg = FDI_TX_CTL(pipe);
		2800	temp = I915_READ(reg);
		2801	temp &= ~FDI_LINK_TRAIN_NONE;
		2802	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2803	I915_WRITE(reg, temp);
		2804
		2805	reg = FDI_RX_CTL(pipe);
		2806	temp = I915_READ(reg);
		2807	if (HAS_PCH_CPT(dev)) {
		2808	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2809	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2810	} else {
		2811	temp &= ~FDI_LINK_TRAIN_NONE;
		2812	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2813	}
		2814	/* BPC in FDI rx is consistent with that in PIPECONF */
		2815	temp &= ~(0x07 << 16);
3480	Serge	2816	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2817	I915_WRITE(reg, temp);
		2818
		2819	POSTING_READ(reg);
		2820	udelay(100);
		2821	}
		2822
3031	serge	2823	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2327	Serge	2824	{
3031	serge	2825	struct drm_device *dev = crtc->dev;
2327	Serge	2826	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	2827	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2828	unsigned long flags;
		2829	bool pending;
2327	Serge	2830
3480	Serge	2831	if (i915_reset_in_progress(&dev_priv->gpu_error) \|\|
		2832	intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3031	serge	2833	return false;
2327	Serge	2834
3031	serge	2835	spin_lock_irqsave(&dev->event_lock, flags);
		2836	pending = to_intel_crtc(crtc)->unpin_work != NULL;
		2837	spin_unlock_irqrestore(&dev->event_lock, flags);
		2838
		2839	return pending;
2327	Serge	2840	}
		2841
3031	serge	2842	#if 0
2327	Serge	2843	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2844	{
3031	serge	2845	struct drm_device *dev = crtc->dev;
		2846	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2847
		2848	if (crtc->fb == NULL)
		2849	return;
		2850
3480	Serge	2851	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
		2852
2360	Serge	2853	wait_event(dev_priv->pending_flip_queue,
3031	serge	2854	!intel_crtc_has_pending_flip(crtc));
		2855
		2856	mutex_lock(&dev->struct_mutex);
		2857	intel_finish_fb(crtc->fb);
		2858	mutex_unlock(&dev->struct_mutex);
2327	Serge	2859	}
3031	serge	2860	#endif
2327	Serge	2861
3031	serge	2862	/* Program iCLKIP clock to the desired frequency */
		2863	static void lpt_program_iclkip(struct drm_crtc *crtc)
		2864	{
		2865	struct drm_device *dev = crtc->dev;
		2866	struct drm_i915_private *dev_priv = dev->dev_private;
		2867	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		2868	u32 temp;
		2869
3480	Serge	2870	mutex_lock(&dev_priv->dpio_lock);
		2871
3031	serge	2872	/* It is necessary to ungate the pixclk gate prior to programming
		2873	* the divisors, and gate it back when it is done.
		2874	*/
		2875	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		2876
		2877	/* Disable SSCCTL */
		2878	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3243	Serge	2879	intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) \|
		2880	SBI_SSCCTL_DISABLE,
		2881	SBI_ICLK);
3031	serge	2882
		2883	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
		2884	if (crtc->mode.clock == 20000) {
		2885	auxdiv = 1;
		2886	divsel = 0x41;
		2887	phaseinc = 0x20;
		2888	} else {
		2889	/* The iCLK virtual clock root frequency is in MHz,
		2890	* but the crtc->mode.clock in in KHz. To get the divisors,
		2891	* it is necessary to divide one by another, so we
		2892	* convert the virtual clock precision to KHz here for higher
		2893	* precision.
		2894	*/
		2895	u32 iclk_virtual_root_freq = 172800 * 1000;
		2896	u32 iclk_pi_range = 64;
		2897	u32 desired_divisor, msb_divisor_value, pi_value;
		2898
		2899	desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		2900	msb_divisor_value = desired_divisor / iclk_pi_range;
		2901	pi_value = desired_divisor % iclk_pi_range;
		2902
		2903	auxdiv = 0;
		2904	divsel = msb_divisor_value - 2;
		2905	phaseinc = pi_value;
		2906	}
		2907
		2908	/* This should not happen with any sane values */
		2909	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		2910	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		2911	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		2912	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		2913
		2914	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
		2915	crtc->mode.clock,
		2916	auxdiv,
		2917	divsel,
		2918	phasedir,
		2919	phaseinc);
		2920
		2921	/* Program SSCDIVINTPHASE6 */
3243	Serge	2922	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3031	serge	2923	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		2924	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		2925	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		2926	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		2927	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		2928	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
3243	Serge	2929	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031	serge	2930
		2931	/* Program SSCAUXDIV */
3243	Serge	2932	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3031	serge	2933	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		2934	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3243	Serge	2935	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3031	serge	2936
		2937	/* Enable modulator and associated divider */
3243	Serge	2938	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3031	serge	2939	temp &= ~SBI_SSCCTL_DISABLE;
3243	Serge	2940	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3031	serge	2941
		2942	/* Wait for initialization time */
		2943	udelay(24);
		2944
		2945	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3480	Serge	2946
		2947	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	2948	}
		2949
4104	Serge	2950	static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
		2951	enum pipe pch_transcoder)
		2952	{
		2953	struct drm_device *dev = crtc->base.dev;
		2954	struct drm_i915_private *dev_priv = dev->dev_private;
		2955	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
		2956
		2957	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
		2958	I915_READ(HTOTAL(cpu_transcoder)));
		2959	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
		2960	I915_READ(HBLANK(cpu_transcoder)));
		2961	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
		2962	I915_READ(HSYNC(cpu_transcoder)));
		2963
		2964	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
		2965	I915_READ(VTOTAL(cpu_transcoder)));
		2966	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
		2967	I915_READ(VBLANK(cpu_transcoder)));
		2968	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
		2969	I915_READ(VSYNC(cpu_transcoder)));
		2970	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
		2971	I915_READ(VSYNCSHIFT(cpu_transcoder)));
		2972	}
		2973
2327	Serge	2974	/*
		2975	* Enable PCH resources required for PCH ports:
		2976	* - PCH PLLs
		2977	* - FDI training & RX/TX
		2978	* - update transcoder timings
		2979	* - DP transcoding bits
		2980	* - transcoder
		2981	*/
		2982	static void ironlake_pch_enable(struct drm_crtc *crtc)
		2983	{
		2984	struct drm_device *dev = crtc->dev;
		2985	struct drm_i915_private *dev_priv = dev->dev_private;
		2986	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2987	int pipe = intel_crtc->pipe;
3031	serge	2988	u32 reg, temp;
2327	Serge	2989
4104	Serge	2990	assert_pch_transcoder_disabled(dev_priv, pipe);
3031	serge	2991
3243	Serge	2992	/* Write the TU size bits before fdi link training, so that error
		2993	* detection works. */
		2994	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		2995	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		2996
2327	Serge	2997	/* For PCH output, training FDI link */
		2998	dev_priv->display.fdi_link_train(crtc);
		2999
4104	Serge	3000	/* We need to program the right clock selection before writing the pixel
		3001	* mutliplier into the DPLL. */
3243	Serge	3002	if (HAS_PCH_CPT(dev)) {
3031	serge	3003	u32 sel;
2342	Serge	3004
2327	Serge	3005	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3006	temp \|= TRANS_DPLL_ENABLE(pipe);
		3007	sel = TRANS_DPLLB_SEL(pipe);
		3008	if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3031	serge	3009	temp \|= sel;
		3010	else
		3011	temp &= ~sel;
2327	Serge	3012	I915_WRITE(PCH_DPLL_SEL, temp);
		3013	}
		3014
4104	Serge	3015	/* XXX: pch pll's can be enabled any time before we enable the PCH
		3016	* transcoder, and we actually should do this to not upset any PCH
		3017	* transcoder that already use the clock when we share it.
		3018	*
		3019	* Note that enable_shared_dpll tries to do the right thing, but
		3020	* get_shared_dpll unconditionally resets the pll - we need that to have
		3021	* the right LVDS enable sequence. */
		3022	ironlake_enable_shared_dpll(intel_crtc);
		3023
2327	Serge	3024	/* set transcoder timing, panel must allow it */
		3025	assert_panel_unlocked(dev_priv, pipe);
4104	Serge	3026	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2327	Serge	3027
		3028	intel_fdi_normal_train(crtc);
		3029
		3030	/* For PCH DP, enable TRANS_DP_CTL */
		3031	if (HAS_PCH_CPT(dev) &&
2342	Serge	3032	(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		3033	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3480	Serge	3034	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2327	Serge	3035	reg = TRANS_DP_CTL(pipe);
		3036	temp = I915_READ(reg);
		3037	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		3038	TRANS_DP_SYNC_MASK \|
		3039	TRANS_DP_BPC_MASK);
		3040	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		3041	TRANS_DP_ENH_FRAMING);
		3042	temp \|= bpc << 9; /* same format but at 11:9 */
		3043
		3044	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		3045	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		3046	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		3047	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		3048
		3049	switch (intel_trans_dp_port_sel(crtc)) {
		3050	case PCH_DP_B:
		3051	temp \|= TRANS_DP_PORT_SEL_B;
		3052	break;
		3053	case PCH_DP_C:
		3054	temp \|= TRANS_DP_PORT_SEL_C;
		3055	break;
		3056	case PCH_DP_D:
		3057	temp \|= TRANS_DP_PORT_SEL_D;
		3058	break;
		3059	default:
3243	Serge	3060	BUG();
2327	Serge	3061	}
		3062
		3063	I915_WRITE(reg, temp);
		3064	}
		3065
3243	Serge	3066	ironlake_enable_pch_transcoder(dev_priv, pipe);
2327	Serge	3067	}
		3068
3243	Serge	3069	static void lpt_pch_enable(struct drm_crtc *crtc)
		3070	{
		3071	struct drm_device *dev = crtc->dev;
		3072	struct drm_i915_private *dev_priv = dev->dev_private;
		3073	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	3074	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3075
4104	Serge	3076	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3243	Serge	3077
		3078	lpt_program_iclkip(crtc);
		3079
		3080	/* Set transcoder timing. */
4104	Serge	3081	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3243	Serge	3082
		3083	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
		3084	}
		3085
4104	Serge	3086	static void intel_put_shared_dpll(struct intel_crtc *crtc)
3031	serge	3087	{
4104	Serge	3088	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3031	serge	3089
		3090	if (pll == NULL)
		3091	return;
		3092
		3093	if (pll->refcount == 0) {
4104	Serge	3094	WARN(1, "bad %s refcount\n", pll->name);
3031	serge	3095	return;
		3096	}
		3097
4104	Serge	3098	if (--pll->refcount == 0) {
		3099	WARN_ON(pll->on);
		3100	WARN_ON(pll->active);
		3101	}
		3102
		3103	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3031	serge	3104	}
		3105
4104	Serge	3106	static struct intel_shared_dpll intel_get_shared_dpll(struct intel_crtc crtc)
3031	serge	3107	{
4104	Serge	3108	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3109	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
		3110	enum intel_dpll_id i;
3031	serge	3111
		3112	if (pll) {
4104	Serge	3113	DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
		3114	crtc->base.base.id, pll->name);
		3115	intel_put_shared_dpll(crtc);
3031	serge	3116	}
		3117
		3118	if (HAS_PCH_IBX(dev_priv->dev)) {
		3119	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4104	Serge	3120	i = (enum intel_dpll_id) crtc->pipe;
		3121	pll = &dev_priv->shared_dplls[i];
3031	serge	3122
4104	Serge	3123	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
		3124	crtc->base.base.id, pll->name);
3031	serge	3125
		3126	goto found;
		3127	}
		3128
4104	Serge	3129	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3130	pll = &dev_priv->shared_dplls[i];
3031	serge	3131
		3132	/* Only want to check enabled timings first */
		3133	if (pll->refcount == 0)
		3134	continue;
		3135
4104	Serge	3136	if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
		3137	sizeof(pll->hw_state)) == 0) {
		3138	DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
		3139	crtc->base.base.id,
		3140	pll->name, pll->refcount, pll->active);
3031	serge	3141
		3142	goto found;
		3143	}
		3144	}
		3145
		3146	/* Ok no matching timings, maybe there's a free one? */
4104	Serge	3147	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3148	pll = &dev_priv->shared_dplls[i];
3031	serge	3149	if (pll->refcount == 0) {
4104	Serge	3150	DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
		3151	crtc->base.base.id, pll->name);
3031	serge	3152	goto found;
		3153	}
		3154	}
		3155
		3156	return NULL;
		3157
		3158	found:
4104	Serge	3159	crtc->config.shared_dpll = i;
		3160	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
		3161	pipe_name(crtc->pipe));
		3162
		3163	if (pll->active == 0) {
		3164	memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
		3165	sizeof(pll->hw_state));
		3166
		3167	DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
		3168	WARN_ON(pll->on);
		3169	assert_shared_dpll_disabled(dev_priv, pll);
		3170
		3171	pll->mode_set(dev_priv, pll);
		3172	}
3031	serge	3173	pll->refcount++;
		3174
		3175	return pll;
		3176	}
		3177
4104	Serge	3178	static void cpt_verify_modeset(struct drm_device *dev, int pipe)
2342	Serge	3179	{
		3180	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3181	int dslreg = PIPEDSL(pipe);
2342	Serge	3182	u32 temp;
		3183
		3184	temp = I915_READ(dslreg);
		3185	udelay(500);
		3186	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		3187	if (wait_for(I915_READ(dslreg) != temp, 5))
4104	Serge	3188	DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
2342	Serge	3189	}
		3190	}
		3191
4104	Serge	3192	static void ironlake_pfit_enable(struct intel_crtc *crtc)
		3193	{
		3194	struct drm_device *dev = crtc->base.dev;
		3195	struct drm_i915_private *dev_priv = dev->dev_private;
		3196	int pipe = crtc->pipe;
		3197
		3198	if (crtc->config.pch_pfit.enabled) {
		3199	/* Force use of hard-coded filter coefficients
		3200	* as some pre-programmed values are broken,
		3201	* e.g. x201.
		3202	*/
		3203	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		3204	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3 \|
		3205	PF_PIPE_SEL_IVB(pipe));
		3206	else
		3207	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		3208	I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
		3209	I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
		3210	}
		3211	}
		3212
		3213	static void intel_enable_planes(struct drm_crtc *crtc)
		3214	{
		3215	struct drm_device *dev = crtc->dev;
		3216	enum pipe pipe = to_intel_crtc(crtc)->pipe;
		3217	struct intel_plane *intel_plane;
		3218
		3219	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		3220	if (intel_plane->pipe == pipe)
		3221	intel_plane_restore(&intel_plane->base);
		3222	}
		3223
		3224	static void intel_disable_planes(struct drm_crtc *crtc)
		3225	{
		3226	struct drm_device *dev = crtc->dev;
		3227	enum pipe pipe = to_intel_crtc(crtc)->pipe;
		3228	struct intel_plane *intel_plane;
		3229
		3230	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		3231	if (intel_plane->pipe == pipe)
		3232	intel_plane_disable(&intel_plane->base);
		3233	}
		3234
2327	Serge	3235	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		3236	{
		3237	struct drm_device *dev = crtc->dev;
		3238	struct drm_i915_private *dev_priv = dev->dev_private;
		3239	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3240	struct intel_encoder *encoder;
2327	Serge	3241	int pipe = intel_crtc->pipe;
		3242	int plane = intel_crtc->plane;
		3243
3031	serge	3244	WARN_ON(!crtc->enabled);
		3245
2327	Serge	3246	if (intel_crtc->active)
		3247	return;
		3248
		3249	intel_crtc->active = true;
4104	Serge	3250
		3251	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3252	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
		3253
2327	Serge	3254	intel_update_watermarks(dev);
		3255
4104	Serge	3256	for_each_encoder_on_crtc(dev, crtc, encoder)
		3257	if (encoder->pre_enable)
		3258	encoder->pre_enable(encoder);
2327	Serge	3259
3746	Serge	3260	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3261	/* Note: FDI PLL enabling _must_ be done before we enable the
		3262	* cpu pipes, hence this is separate from all the other fdi/pch
		3263	* enabling. */
3031	serge	3264	ironlake_fdi_pll_enable(intel_crtc);
		3265	} else {
		3266	assert_fdi_tx_disabled(dev_priv, pipe);
		3267	assert_fdi_rx_disabled(dev_priv, pipe);
		3268	}
2327	Serge	3269
4104	Serge	3270	ironlake_pfit_enable(intel_crtc);
3031	serge	3271
2327	Serge	3272	/*
		3273	* On ILK+ LUT must be loaded before the pipe is running but with
		3274	* clocks enabled
		3275	*/
		3276	intel_crtc_load_lut(crtc);
		3277
3746	Serge	3278	intel_enable_pipe(dev_priv, pipe,
		3279	intel_crtc->config.has_pch_encoder);
2327	Serge	3280	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3281	intel_enable_planes(crtc);
		3282	// intel_crtc_update_cursor(crtc, true);
2327	Serge	3283
3746	Serge	3284	if (intel_crtc->config.has_pch_encoder)
2327	Serge	3285	ironlake_pch_enable(crtc);
		3286
		3287	mutex_lock(&dev->struct_mutex);
		3288	intel_update_fbc(dev);
		3289	mutex_unlock(&dev->struct_mutex);
		3290
3031	serge	3291	for_each_encoder_on_crtc(dev, crtc, encoder)
		3292	encoder->enable(encoder);
		3293
		3294	if (HAS_PCH_CPT(dev))
4104	Serge	3295	cpt_verify_modeset(dev, intel_crtc->pipe);
3031	serge	3296
		3297	/*
		3298	* There seems to be a race in PCH platform hw (at least on some
		3299	* outputs) where an enabled pipe still completes any pageflip right
		3300	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3301	* as the first vblank happend, everything works as expected. Hence just
		3302	* wait for one vblank before returning to avoid strange things
		3303	* happening.
		3304	*/
		3305	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	3306	}
		3307
4104	Serge	3308	/* IPS only exists on ULT machines and is tied to pipe A. */
		3309	static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
		3310	{
		3311	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
		3312	}
		3313
		3314	static void hsw_enable_ips(struct intel_crtc *crtc)
		3315	{
		3316	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3317
		3318	if (!crtc->config.ips_enabled)
		3319	return;
		3320
		3321	/* We can only enable IPS after we enable a plane and wait for a vblank.
		3322	* We guarantee that the plane is enabled by calling intel_enable_ips
		3323	* only after intel_enable_plane. And intel_enable_plane already waits
		3324	* for a vblank, so all we need to do here is to enable the IPS bit. */
		3325	assert_plane_enabled(dev_priv, crtc->plane);
		3326	I915_WRITE(IPS_CTL, IPS_ENABLE);
		3327	}
		3328
		3329	static void hsw_disable_ips(struct intel_crtc *crtc)
		3330	{
		3331	struct drm_device *dev = crtc->base.dev;
		3332	struct drm_i915_private *dev_priv = dev->dev_private;
		3333
		3334	if (!crtc->config.ips_enabled)
		3335	return;
		3336
		3337	assert_plane_enabled(dev_priv, crtc->plane);
		3338	I915_WRITE(IPS_CTL, 0);
		3339
		3340	/* We need to wait for a vblank before we can disable the plane. */
		3341	intel_wait_for_vblank(dev, crtc->pipe);
		3342	}
		3343
3243	Serge	3344	static void haswell_crtc_enable(struct drm_crtc *crtc)
		3345	{
		3346	struct drm_device *dev = crtc->dev;
		3347	struct drm_i915_private *dev_priv = dev->dev_private;
		3348	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3349	struct intel_encoder *encoder;
		3350	int pipe = intel_crtc->pipe;
		3351	int plane = intel_crtc->plane;
		3352
		3353	WARN_ON(!crtc->enabled);
		3354
		3355	if (intel_crtc->active)
		3356	return;
		3357
		3358	intel_crtc->active = true;
4104	Serge	3359
		3360	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3361	if (intel_crtc->config.has_pch_encoder)
		3362	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
		3363
3243	Serge	3364	intel_update_watermarks(dev);
		3365
3746	Serge	3366	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3367	dev_priv->display.fdi_link_train(crtc);
		3368
		3369	for_each_encoder_on_crtc(dev, crtc, encoder)
		3370	if (encoder->pre_enable)
		3371	encoder->pre_enable(encoder);
		3372
		3373	intel_ddi_enable_pipe_clock(intel_crtc);
		3374
4104	Serge	3375	ironlake_pfit_enable(intel_crtc);
3243	Serge	3376
		3377	/*
		3378	* On ILK+ LUT must be loaded before the pipe is running but with
		3379	* clocks enabled
		3380	*/
		3381	intel_crtc_load_lut(crtc);
		3382
		3383	intel_ddi_set_pipe_settings(crtc);
3746	Serge	3384	intel_ddi_enable_transcoder_func(crtc);
3243	Serge	3385
3746	Serge	3386	intel_enable_pipe(dev_priv, pipe,
		3387	intel_crtc->config.has_pch_encoder);
3243	Serge	3388	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3389	intel_enable_planes(crtc);
		3390	// intel_crtc_update_cursor(crtc, true);
3243	Serge	3391
4104	Serge	3392	hsw_enable_ips(intel_crtc);
		3393
3746	Serge	3394	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3395	lpt_pch_enable(crtc);
		3396
		3397	mutex_lock(&dev->struct_mutex);
		3398	intel_update_fbc(dev);
		3399	mutex_unlock(&dev->struct_mutex);
		3400
		3401	for_each_encoder_on_crtc(dev, crtc, encoder)
		3402	encoder->enable(encoder);
		3403
		3404	/*
		3405	* There seems to be a race in PCH platform hw (at least on some
		3406	* outputs) where an enabled pipe still completes any pageflip right
		3407	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3408	* as the first vblank happend, everything works as expected. Hence just
		3409	* wait for one vblank before returning to avoid strange things
		3410	* happening.
		3411	*/
		3412	intel_wait_for_vblank(dev, intel_crtc->pipe);
		3413	}
		3414
4104	Serge	3415	static void ironlake_pfit_disable(struct intel_crtc *crtc)
		3416	{
		3417	struct drm_device *dev = crtc->base.dev;
		3418	struct drm_i915_private *dev_priv = dev->dev_private;
		3419	int pipe = crtc->pipe;
		3420
		3421	/* To avoid upsetting the power well on haswell only disable the pfit if
		3422	* it's in use. The hw state code will make sure we get this right. */
		3423	if (crtc->config.pch_pfit.enabled) {
		3424	I915_WRITE(PF_CTL(pipe), 0);
		3425	I915_WRITE(PF_WIN_POS(pipe), 0);
		3426	I915_WRITE(PF_WIN_SZ(pipe), 0);
		3427	}
		3428	}
		3429
2327	Serge	3430	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		3431	{
		3432	struct drm_device *dev = crtc->dev;
		3433	struct drm_i915_private *dev_priv = dev->dev_private;
		3434	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3435	struct intel_encoder *encoder;
2327	Serge	3436	int pipe = intel_crtc->pipe;
		3437	int plane = intel_crtc->plane;
		3438	u32 reg, temp;
		3439
3031	serge	3440
2327	Serge	3441	if (!intel_crtc->active)
		3442	return;
		3443
3031	serge	3444	for_each_encoder_on_crtc(dev, crtc, encoder)
		3445	encoder->disable(encoder);
2336	Serge	3446
3031	serge	3447	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3448	// drm_vblank_off(dev, pipe);
		3449
4104	Serge	3450	if (dev_priv->fbc.plane == plane)
		3451	intel_disable_fbc(dev);
		3452
		3453	// intel_crtc_update_cursor(crtc, false);
		3454	intel_disable_planes(crtc);
2327	Serge	3455	intel_disable_plane(dev_priv, plane, pipe);
		3456
4104	Serge	3457	if (intel_crtc->config.has_pch_encoder)
		3458	intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
2327	Serge	3459
		3460	intel_disable_pipe(dev_priv, pipe);
		3461
4104	Serge	3462	ironlake_pfit_disable(intel_crtc);
2327	Serge	3463
3031	serge	3464	for_each_encoder_on_crtc(dev, crtc, encoder)
		3465	if (encoder->post_disable)
		3466	encoder->post_disable(encoder);
		3467
4104	Serge	3468	if (intel_crtc->config.has_pch_encoder) {
2327	Serge	3469	ironlake_fdi_disable(crtc);
		3470
3243	Serge	3471	ironlake_disable_pch_transcoder(dev_priv, pipe);
4104	Serge	3472	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
2327	Serge	3473
		3474	if (HAS_PCH_CPT(dev)) {
		3475	/* disable TRANS_DP_CTL */
		3476	reg = TRANS_DP_CTL(pipe);
		3477	temp = I915_READ(reg);
4104	Serge	3478	temp &= ~(TRANS_DP_OUTPUT_ENABLE \|
		3479	TRANS_DP_PORT_SEL_MASK);
2327	Serge	3480	temp \|= TRANS_DP_PORT_SEL_NONE;
		3481	I915_WRITE(reg, temp);
		3482
		3483	/* disable DPLL_SEL */
		3484	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3485	temp &= ~(TRANS_DPLL_ENABLE(pipe) \| TRANS_DPLLB_SEL(pipe));
2327	Serge	3486	I915_WRITE(PCH_DPLL_SEL, temp);
		3487	}
		3488
		3489	/* disable PCH DPLL */
4104	Serge	3490	intel_disable_shared_dpll(intel_crtc);
2327	Serge	3491
3031	serge	3492	ironlake_fdi_pll_disable(intel_crtc);
4104	Serge	3493	}
2327	Serge	3494
		3495	intel_crtc->active = false;
		3496	intel_update_watermarks(dev);
		3497
		3498	mutex_lock(&dev->struct_mutex);
		3499	intel_update_fbc(dev);
		3500	mutex_unlock(&dev->struct_mutex);
		3501	}
		3502
3243	Serge	3503	static void haswell_crtc_disable(struct drm_crtc *crtc)
		3504	{
		3505	struct drm_device *dev = crtc->dev;
		3506	struct drm_i915_private *dev_priv = dev->dev_private;
		3507	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3508	struct intel_encoder *encoder;
		3509	int pipe = intel_crtc->pipe;
		3510	int plane = intel_crtc->plane;
3746	Serge	3511	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3512
		3513	if (!intel_crtc->active)
		3514	return;
		3515
		3516	for_each_encoder_on_crtc(dev, crtc, encoder)
		3517	encoder->disable(encoder);
		3518
		3519
4104	Serge	3520	/* FBC must be disabled before disabling the plane on HSW. */
		3521	if (dev_priv->fbc.plane == plane)
		3522	intel_disable_fbc(dev);
		3523
		3524	hsw_disable_ips(intel_crtc);
		3525
		3526	// intel_crtc_update_cursor(crtc, false);
		3527	intel_disable_planes(crtc);
3243	Serge	3528	intel_disable_plane(dev_priv, plane, pipe);
		3529
4104	Serge	3530	if (intel_crtc->config.has_pch_encoder)
		3531	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3243	Serge	3532	intel_disable_pipe(dev_priv, pipe);
		3533
		3534	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
		3535
4104	Serge	3536	ironlake_pfit_disable(intel_crtc);
3243	Serge	3537
		3538	intel_ddi_disable_pipe_clock(intel_crtc);
		3539
		3540	for_each_encoder_on_crtc(dev, crtc, encoder)
		3541	if (encoder->post_disable)
		3542	encoder->post_disable(encoder);
		3543
3746	Serge	3544	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3545	lpt_disable_pch_transcoder(dev_priv);
4104	Serge	3546	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3243	Serge	3547	intel_ddi_fdi_disable(crtc);
		3548	}
		3549
		3550	intel_crtc->active = false;
		3551	intel_update_watermarks(dev);
		3552
		3553	mutex_lock(&dev->struct_mutex);
		3554	intel_update_fbc(dev);
		3555	mutex_unlock(&dev->struct_mutex);
		3556	}
		3557
3031	serge	3558	static void ironlake_crtc_off(struct drm_crtc *crtc)
2327	Serge	3559	{
		3560	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	3561	intel_put_shared_dpll(intel_crtc);
2327	Serge	3562	}
		3563
3243	Serge	3564	static void haswell_crtc_off(struct drm_crtc *crtc)
		3565	{
		3566	intel_ddi_put_crtc_pll(crtc);
		3567	}
		3568
2327	Serge	3569	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3570	{
		3571	if (!enable && intel_crtc->overlay) {
		3572	struct drm_device *dev = intel_crtc->base.dev;
		3573	struct drm_i915_private *dev_priv = dev->dev_private;
		3574
		3575	mutex_lock(&dev->struct_mutex);
		3576	dev_priv->mm.interruptible = false;
		3577	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3578	dev_priv->mm.interruptible = true;
		3579	mutex_unlock(&dev->struct_mutex);
		3580	}
		3581
		3582	/* Let userspace switch the overlay on again. In most cases userspace
		3583	* has to recompute where to put it anyway.
		3584	*/
		3585	}
		3586
3480	Serge	3587	/**
		3588	* i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
		3589	* cursor plane briefly if not already running after enabling the display
		3590	* plane.
		3591	* This workaround avoids occasional blank screens when self refresh is
		3592	* enabled.
		3593	*/
		3594	static void
		3595	g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
		3596	{
		3597	u32 cntl = I915_READ(CURCNTR(pipe));
		3598
		3599	if ((cntl & CURSOR_MODE) == 0) {
		3600	u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
		3601
		3602	I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
		3603	I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
		3604	intel_wait_for_vblank(dev_priv->dev, pipe);
		3605	I915_WRITE(CURCNTR(pipe), cntl);
		3606	I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
		3607	I915_WRITE(FW_BLC_SELF, fw_bcl_self);
		3608	}
		3609	}
		3610
4104	Serge	3611	static void i9xx_pfit_enable(struct intel_crtc *crtc)
		3612	{
		3613	struct drm_device *dev = crtc->base.dev;
		3614	struct drm_i915_private *dev_priv = dev->dev_private;
		3615	struct intel_crtc_config *pipe_config = &crtc->config;
		3616
		3617	if (!crtc->config.gmch_pfit.control)
		3618	return;
		3619
		3620	/*
		3621	* The panel fitter should only be adjusted whilst the pipe is disabled,
		3622	* according to register description and PRM.
		3623	*/
		3624	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
		3625	assert_pipe_disabled(dev_priv, crtc->pipe);
		3626
		3627	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
		3628	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
		3629
		3630	/* Border color in case we don't scale up to the full screen. Black by
		3631	* default, change to something else for debugging. */
		3632	I915_WRITE(BCLRPAT(crtc->pipe), 0);
		3633	}
		3634
		3635	static void valleyview_crtc_enable(struct drm_crtc *crtc)
		3636	{
		3637	struct drm_device *dev = crtc->dev;
		3638	struct drm_i915_private *dev_priv = dev->dev_private;
		3639	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3640	struct intel_encoder *encoder;
		3641	int pipe = intel_crtc->pipe;
		3642	int plane = intel_crtc->plane;
		3643
		3644	WARN_ON(!crtc->enabled);
		3645
		3646	if (intel_crtc->active)
		3647	return;
		3648
		3649	intel_crtc->active = true;
		3650	intel_update_watermarks(dev);
		3651
		3652	for_each_encoder_on_crtc(dev, crtc, encoder)
		3653	if (encoder->pre_pll_enable)
		3654	encoder->pre_pll_enable(encoder);
		3655
		3656	vlv_enable_pll(intel_crtc);
		3657
		3658	for_each_encoder_on_crtc(dev, crtc, encoder)
		3659	if (encoder->pre_enable)
		3660	encoder->pre_enable(encoder);
		3661
		3662	i9xx_pfit_enable(intel_crtc);
		3663
		3664	intel_crtc_load_lut(crtc);
		3665
		3666	intel_enable_pipe(dev_priv, pipe, false);
		3667	intel_enable_plane(dev_priv, plane, pipe);
		3668	intel_enable_planes(crtc);
		3669	// intel_crtc_update_cursor(crtc, true);
		3670
		3671	intel_update_fbc(dev);
		3672
		3673	for_each_encoder_on_crtc(dev, crtc, encoder)
		3674	encoder->enable(encoder);
		3675	}
		3676
2327	Serge	3677	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3678	{
		3679	struct drm_device *dev = crtc->dev;
		3680	struct drm_i915_private *dev_priv = dev->dev_private;
		3681	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3682	struct intel_encoder *encoder;
2327	Serge	3683	int pipe = intel_crtc->pipe;
		3684	int plane = intel_crtc->plane;
		3685
3031	serge	3686	WARN_ON(!crtc->enabled);
		3687
2327	Serge	3688	if (intel_crtc->active)
		3689	return;
		3690
		3691	intel_crtc->active = true;
		3692	intel_update_watermarks(dev);
		3693
3480	Serge	3694	for_each_encoder_on_crtc(dev, crtc, encoder)
		3695	if (encoder->pre_enable)
		3696	encoder->pre_enable(encoder);
		3697
4104	Serge	3698	i9xx_enable_pll(intel_crtc);
		3699
		3700	i9xx_pfit_enable(intel_crtc);
		3701
		3702	intel_crtc_load_lut(crtc);
		3703
2327	Serge	3704	intel_enable_pipe(dev_priv, pipe, false);
		3705	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3706	intel_enable_planes(crtc);
		3707	/* The fixup needs to happen before cursor is enabled */
3480	Serge	3708	if (IS_G4X(dev))
		3709	g4x_fixup_plane(dev_priv, pipe);
4104	Serge	3710	// intel_crtc_update_cursor(crtc, true);
2327	Serge	3711
		3712	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3713	intel_crtc_dpms_overlay(intel_crtc, true);
3031	serge	3714
4104	Serge	3715	intel_update_fbc(dev);
		3716
3031	serge	3717	for_each_encoder_on_crtc(dev, crtc, encoder)
		3718	encoder->enable(encoder);
2327	Serge	3719	}
		3720
3746	Serge	3721	static void i9xx_pfit_disable(struct intel_crtc *crtc)
		3722	{
		3723	struct drm_device *dev = crtc->base.dev;
		3724	struct drm_i915_private *dev_priv = dev->dev_private;
		3725
4104	Serge	3726	if (!crtc->config.gmch_pfit.control)
		3727	return;
		3728
3746	Serge	3729	assert_pipe_disabled(dev_priv, crtc->pipe);
		3730
4104	Serge	3731	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
		3732	I915_READ(PFIT_CONTROL));
3746	Serge	3733	I915_WRITE(PFIT_CONTROL, 0);
		3734	}
		3735
2327	Serge	3736	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3737	{
		3738	struct drm_device *dev = crtc->dev;
		3739	struct drm_i915_private *dev_priv = dev->dev_private;
		3740	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3741	struct intel_encoder *encoder;
2327	Serge	3742	int pipe = intel_crtc->pipe;
		3743	int plane = intel_crtc->plane;
		3744
		3745	if (!intel_crtc->active)
		3746	return;
		3747
3031	serge	3748	for_each_encoder_on_crtc(dev, crtc, encoder)
		3749	encoder->disable(encoder);
		3750
2327	Serge	3751	/* Give the overlay scaler a chance to disable if it's on this pipe */
3031	serge	3752	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3753	// drm_vblank_off(dev, pipe);
		3754
4104	Serge	3755	if (dev_priv->fbc.plane == plane)
2327	Serge	3756	intel_disable_fbc(dev);
		3757
4104	Serge	3758	intel_crtc_dpms_overlay(intel_crtc, false);
		3759	// intel_crtc_update_cursor(crtc, false);
		3760	intel_disable_planes(crtc);
2327	Serge	3761	intel_disable_plane(dev_priv, plane, pipe);
4104	Serge	3762
2327	Serge	3763	intel_disable_pipe(dev_priv, pipe);
3480	Serge	3764
3746	Serge	3765	i9xx_pfit_disable(intel_crtc);
3480	Serge	3766
4104	Serge	3767	for_each_encoder_on_crtc(dev, crtc, encoder)
		3768	if (encoder->post_disable)
		3769	encoder->post_disable(encoder);
2327	Serge	3770
4104	Serge	3771	i9xx_disable_pll(dev_priv, pipe);
		3772
2327	Serge	3773	intel_crtc->active = false;
		3774	intel_update_fbc(dev);
		3775	intel_update_watermarks(dev);
		3776	}
		3777
3031	serge	3778	static void i9xx_crtc_off(struct drm_crtc *crtc)
2327	Serge	3779	{
		3780	}
		3781
3031	serge	3782	static void intel_crtc_update_sarea(struct drm_crtc *crtc,
		3783	bool enabled)
2330	Serge	3784	{
		3785	struct drm_device *dev = crtc->dev;
		3786	struct drm_i915_master_private *master_priv;
		3787	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3788	int pipe = intel_crtc->pipe;
2327	Serge	3789
		3790
2340	Serge	3791	#if 0
2330	Serge	3792	if (!dev->primary->master)
		3793	return;
2327	Serge	3794
2330	Serge	3795	master_priv = dev->primary->master->driver_priv;
		3796	if (!master_priv->sarea_priv)
		3797	return;
2327	Serge	3798
2330	Serge	3799	switch (pipe) {
		3800	case 0:
		3801	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3802	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3803	break;
		3804	case 1:
		3805	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3806	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3807	break;
		3808	default:
		3809	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3810	break;
		3811	}
2340	Serge	3812	#endif
		3813
2330	Serge	3814	}
2327	Serge	3815
3031	serge	3816	/**
		3817	* Sets the power management mode of the pipe and plane.
		3818	*/
		3819	void intel_crtc_update_dpms(struct drm_crtc *crtc)
		3820	{
		3821	struct drm_device *dev = crtc->dev;
		3822	struct drm_i915_private *dev_priv = dev->dev_private;
		3823	struct intel_encoder *intel_encoder;
		3824	bool enable = false;
		3825
		3826	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		3827	enable \|= intel_encoder->connectors_active;
		3828
		3829	if (enable)
		3830	dev_priv->display.crtc_enable(crtc);
		3831	else
		3832	dev_priv->display.crtc_disable(crtc);
		3833
		3834	intel_crtc_update_sarea(crtc, enable);
		3835	}
		3836
2330	Serge	3837	static void intel_crtc_disable(struct drm_crtc *crtc)
		3838	{
		3839	struct drm_device *dev = crtc->dev;
3031	serge	3840	struct drm_connector *connector;
		3841	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	3842	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	3843
3031	serge	3844	/* crtc should still be enabled when we disable it. */
		3845	WARN_ON(!crtc->enabled);
2327	Serge	3846
4104	Serge	3847	dev_priv->display.crtc_disable(crtc);
3480	Serge	3848	intel_crtc->eld_vld = false;
3031	serge	3849	intel_crtc_update_sarea(crtc, false);
		3850	dev_priv->display.off(crtc);
		3851
		3852	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
		3853	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
		3854
		3855	// if (crtc->fb) {
		3856	// mutex_lock(&dev->struct_mutex);
		3857	// intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
		3858	// mutex_unlock(&dev->struct_mutex);
		3859	// crtc->fb = NULL;
		3860	// }
		3861
		3862	/* Update computed state. */
		3863	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		3864	if (!connector->encoder \|\| !connector->encoder->crtc)
		3865	continue;
		3866
		3867	if (connector->encoder->crtc != crtc)
		3868	continue;
		3869
		3870	connector->dpms = DRM_MODE_DPMS_OFF;
		3871	to_intel_encoder(connector->encoder)->connectors_active = false;
2330	Serge	3872	}
		3873	}
2327	Serge	3874
3031	serge	3875	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3876	{
3031	serge	3877	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3878
		3879	drm_encoder_cleanup(encoder);
		3880	kfree(intel_encoder);
2330	Serge	3881	}
2327	Serge	3882
4104	Serge	3883	/* Simple dpms helper for encoders with just one connector, no cloning and only
3031	serge	3884	* one kind of off state. It clamps all !ON modes to fully OFF and changes the
		3885	* state of the entire output pipe. */
4104	Serge	3886	static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
2330	Serge	3887	{
3031	serge	3888	if (mode == DRM_MODE_DPMS_ON) {
		3889	encoder->connectors_active = true;
		3890
		3891	intel_crtc_update_dpms(encoder->base.crtc);
		3892	} else {
		3893	encoder->connectors_active = false;
		3894
		3895	intel_crtc_update_dpms(encoder->base.crtc);
		3896	}
2330	Serge	3897	}
2327	Serge	3898
3031	serge	3899	/* Cross check the actual hw state with our own modeset state tracking (and it's
		3900	* internal consistency). */
		3901	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	3902	{
3031	serge	3903	if (connector->get_hw_state(connector)) {
		3904	struct intel_encoder *encoder = connector->encoder;
		3905	struct drm_crtc *crtc;
		3906	bool encoder_enabled;
		3907	enum pipe pipe;
		3908
		3909	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		3910	connector->base.base.id,
		3911	drm_get_connector_name(&connector->base));
		3912
		3913	WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		3914	"wrong connector dpms state\n");
		3915	WARN(connector->base.encoder != &encoder->base,
		3916	"active connector not linked to encoder\n");
		3917	WARN(!encoder->connectors_active,
		3918	"encoder->connectors_active not set\n");
		3919
		3920	encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		3921	WARN(!encoder_enabled, "encoder not enabled\n");
		3922	if (WARN_ON(!encoder->base.crtc))
		3923	return;
		3924
		3925	crtc = encoder->base.crtc;
		3926
		3927	WARN(!crtc->enabled, "crtc not enabled\n");
		3928	WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		3929	WARN(pipe != to_intel_crtc(crtc)->pipe,
		3930	"encoder active on the wrong pipe\n");
		3931	}
2330	Serge	3932	}
2327	Serge	3933
3031	serge	3934	/* Even simpler default implementation, if there's really no special case to
		3935	* consider. */
		3936	void intel_connector_dpms(struct drm_connector *connector, int mode)
2330	Serge	3937	{
3031	serge	3938	/* All the simple cases only support two dpms states. */
		3939	if (mode != DRM_MODE_DPMS_ON)
		3940	mode = DRM_MODE_DPMS_OFF;
2342	Serge	3941
3031	serge	3942	if (mode == connector->dpms)
		3943	return;
		3944
		3945	connector->dpms = mode;
		3946
		3947	/* Only need to change hw state when actually enabled */
4104	Serge	3948	if (connector->encoder)
		3949	intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
3031	serge	3950
		3951	intel_modeset_check_state(connector->dev);
2330	Serge	3952	}
2327	Serge	3953
3031	serge	3954	/* Simple connector->get_hw_state implementation for encoders that support only
		3955	* one connector and no cloning and hence the encoder state determines the state
		3956	* of the connector. */
		3957	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	3958	{
3031	serge	3959	enum pipe pipe = 0;
		3960	struct intel_encoder *encoder = connector->encoder;
2330	Serge	3961
3031	serge	3962	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	3963	}
		3964
4104	Serge	3965	static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
		3966	struct intel_crtc_config *pipe_config)
		3967	{
		3968	struct drm_i915_private *dev_priv = dev->dev_private;
		3969	struct intel_crtc *pipe_B_crtc =
		3970	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		3971
		3972	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
		3973	pipe_name(pipe), pipe_config->fdi_lanes);
		3974	if (pipe_config->fdi_lanes > 4) {
		3975	DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
		3976	pipe_name(pipe), pipe_config->fdi_lanes);
		3977	return false;
		3978	}
		3979
		3980	if (IS_HASWELL(dev)) {
		3981	if (pipe_config->fdi_lanes > 2) {
		3982	DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
		3983	pipe_config->fdi_lanes);
		3984	return false;
		3985	} else {
		3986	return true;
		3987	}
		3988	}
		3989
		3990	if (INTEL_INFO(dev)->num_pipes == 2)
		3991	return true;
		3992
		3993	/* Ivybridge 3 pipe is really complicated */
		3994	switch (pipe) {
		3995	case PIPE_A:
		3996	return true;
		3997	case PIPE_B:
		3998	if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		3999	pipe_config->fdi_lanes > 2) {
		4000	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		4001	pipe_name(pipe), pipe_config->fdi_lanes);
		4002	return false;
		4003	}
		4004	return true;
		4005	case PIPE_C:
		4006	if (!pipe_has_enabled_pch(pipe_B_crtc) \|\|
		4007	pipe_B_crtc->config.fdi_lanes <= 2) {
		4008	if (pipe_config->fdi_lanes > 2) {
		4009	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		4010	pipe_name(pipe), pipe_config->fdi_lanes);
		4011	return false;
		4012	}
		4013	} else {
		4014	DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
		4015	return false;
		4016	}
		4017	return true;
		4018	default:
		4019	BUG();
		4020	}
		4021	}
		4022
		4023	#define RETRY 1
		4024	static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3746	Serge	4025	struct intel_crtc_config *pipe_config)
2330	Serge	4026	{
4104	Serge	4027	struct drm_device *dev = intel_crtc->base.dev;
3746	Serge	4028	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4104	Serge	4029	int lane, link_bw, fdi_dotclock;
		4030	bool setup_ok, needs_recompute = false;
2330	Serge	4031
4104	Serge	4032	retry:
		4033	/* FDI is a binary signal running at ~2.7GHz, encoding
		4034	* each output octet as 10 bits. The actual frequency
		4035	* is stored as a divider into a 100MHz clock, and the
		4036	* mode pixel clock is stored in units of 1KHz.
		4037	* Hence the bw of each lane in terms of the mode signal
		4038	* is:
		4039	*/
		4040	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		4041
		4042	fdi_dotclock = adjusted_mode->clock;
		4043	fdi_dotclock /= pipe_config->pixel_multiplier;
		4044
		4045	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
		4046	pipe_config->pipe_bpp);
		4047
		4048	pipe_config->fdi_lanes = lane;
		4049
		4050	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
		4051	link_bw, &pipe_config->fdi_m_n);
		4052
		4053	setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
		4054	intel_crtc->pipe, pipe_config);
		4055	if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
		4056	pipe_config->pipe_bpp -= 2*3;
		4057	DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
		4058	pipe_config->pipe_bpp);
		4059	needs_recompute = true;
		4060	pipe_config->bw_constrained = true;
		4061
		4062	goto retry;
		4063	}
		4064
		4065	if (needs_recompute)
		4066	return RETRY;
		4067
		4068	return setup_ok ? 0 : -EINVAL;
		4069	}
		4070
		4071	static void hsw_compute_ips_config(struct intel_crtc *crtc,
		4072	struct intel_crtc_config *pipe_config)
		4073	{
		4074	pipe_config->ips_enabled = i915_enable_ips &&
		4075	hsw_crtc_supports_ips(crtc) &&
		4076	pipe_config->pipe_bpp <= 24;
		4077	}
		4078
		4079	static int intel_crtc_compute_config(struct intel_crtc *crtc,
		4080	struct intel_crtc_config *pipe_config)
		4081	{
		4082	struct drm_device *dev = crtc->base.dev;
		4083	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
		4084
2330	Serge	4085	if (HAS_PCH_SPLIT(dev)) {
		4086	/* FDI link clock is fixed at 2.7G */
3746	Serge	4087	if (pipe_config->requested_mode.clock * 3
		4088	> IRONLAKE_FDI_FREQ * 4)
4104	Serge	4089	return -EINVAL;
2330	Serge	4090	}
		4091
4104	Serge	4092	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
		4093	* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
3031	serge	4094	*/
		4095	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
		4096	adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4104	Serge	4097	return -EINVAL;
3031	serge	4098
3746	Serge	4099	if ((IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
		4100	pipe_config->pipe_bpp = 103; / 12bpc is gen5+ */
		4101	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
		4102	/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		4103	* for lvds. */
		4104	pipe_config->pipe_bpp = 8*3;
		4105	}
		4106
4104	Serge	4107	if (HAS_IPS(dev))
		4108	hsw_compute_ips_config(crtc, pipe_config);
		4109
		4110	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
		4111	* clock survives for now. */
		4112	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		4113	pipe_config->shared_dpll = crtc->config.shared_dpll;
		4114
		4115	if (pipe_config->has_pch_encoder)
		4116	return ironlake_fdi_compute_config(crtc, pipe_config);
		4117
		4118	return 0;
2330	Serge	4119	}
		4120
3031	serge	4121	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		4122	{
		4123	return 400000; /* FIXME */
		4124	}
		4125
2327	Serge	4126	static int i945_get_display_clock_speed(struct drm_device *dev)
		4127	{
		4128	return 400000;
		4129	}
		4130
		4131	static int i915_get_display_clock_speed(struct drm_device *dev)
		4132	{
		4133	return 333000;
		4134	}
		4135
		4136	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		4137	{
		4138	return 200000;
		4139	}
		4140
4104	Serge	4141	static int pnv_get_display_clock_speed(struct drm_device *dev)
		4142	{
		4143	u16 gcfgc = 0;
		4144
		4145	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		4146
		4147	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		4148	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
		4149	return 267000;
		4150	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
		4151	return 333000;
		4152	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
		4153	return 444000;
		4154	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
		4155	return 200000;
		4156	default:
		4157	DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
		4158	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
		4159	return 133000;
		4160	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
		4161	return 167000;
		4162	}
		4163	}
		4164
2327	Serge	4165	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		4166	{
		4167	u16 gcfgc = 0;
		4168
		4169	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		4170
		4171	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		4172	return 133000;
		4173	else {
		4174	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		4175	case GC_DISPLAY_CLOCK_333_MHZ:
		4176	return 333000;
		4177	default:
		4178	case GC_DISPLAY_CLOCK_190_200_MHZ:
		4179	return 190000;
		4180	}
		4181	}
		4182	}
		4183
		4184	static int i865_get_display_clock_speed(struct drm_device *dev)
		4185	{
		4186	return 266000;
		4187	}
		4188
		4189	static int i855_get_display_clock_speed(struct drm_device *dev)
		4190	{
		4191	u16 hpllcc = 0;
		4192	/* Assume that the hardware is in the high speed state. This
		4193	* should be the default.
		4194	*/
		4195	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		4196	case GC_CLOCK_133_200:
		4197	case GC_CLOCK_100_200:
		4198	return 200000;
		4199	case GC_CLOCK_166_250:
		4200	return 250000;
		4201	case GC_CLOCK_100_133:
		4202	return 133000;
		4203	}
		4204
		4205	/* Shouldn't happen */
		4206	return 0;
		4207	}
		4208
		4209	static int i830_get_display_clock_speed(struct drm_device *dev)
		4210	{
		4211	return 133000;
		4212	}
		4213
		4214	static void
3746	Serge	4215	intel_reduce_m_n_ratio(uint32_t num, uint32_t den)
2327	Serge	4216	{
3746	Serge	4217	while (*num > DATA_LINK_M_N_MASK \|\|
		4218	*den > DATA_LINK_M_N_MASK) {
2327	Serge	4219	*num >>= 1;
		4220	*den >>= 1;
		4221	}
		4222	}
		4223
3746	Serge	4224	static void compute_m_n(unsigned int m, unsigned int n,
		4225	uint32_t ret_m, uint32_t ret_n)
		4226	{
		4227	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
		4228	ret_m = div_u64((uint64_t) m *ret_n, n);
		4229	intel_reduce_m_n_ratio(ret_m, ret_n);
		4230	}
		4231
3480	Serge	4232	void
		4233	intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		4234	int pixel_clock, int link_clock,
		4235	struct intel_link_m_n *m_n)
2327	Serge	4236	{
3480	Serge	4237	m_n->tu = 64;
3746	Serge	4238
		4239	compute_m_n(bits_per_pixel * pixel_clock,
		4240	link_clock * nlanes * 8,
		4241	&m_n->gmch_m, &m_n->gmch_n);
		4242
		4243	compute_m_n(pixel_clock, link_clock,
		4244	&m_n->link_m, &m_n->link_n);
2327	Serge	4245	}
		4246
		4247	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		4248	{
2342	Serge	4249	if (i915_panel_use_ssc >= 0)
		4250	return i915_panel_use_ssc != 0;
4104	Serge	4251	return dev_priv->vbt.lvds_use_ssc
2327	Serge	4252	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		4253	}
		4254
3031	serge	4255	static int vlv_get_refclk(struct drm_crtc *crtc)
2327	Serge	4256	{
3031	serge	4257	struct drm_device *dev = crtc->dev;
		4258	struct drm_i915_private *dev_priv = dev->dev_private;
		4259	int refclk = 27000; /* for DP & HDMI */
2327	Serge	4260
3031	serge	4261	return 100000; /* only one validated so far */
2327	Serge	4262
3031	serge	4263	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		4264	refclk = 96000;
		4265	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		4266	if (intel_panel_use_ssc(dev_priv))
		4267	refclk = 100000;
		4268	else
		4269	refclk = 96000;
		4270	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		4271	refclk = 100000;
		4272	}
2327	Serge	4273
3031	serge	4274	return refclk;
		4275	}
2327	Serge	4276
3031	serge	4277	static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
		4278	{
		4279	struct drm_device *dev = crtc->dev;
		4280	struct drm_i915_private *dev_priv = dev->dev_private;
		4281	int refclk;
2327	Serge	4282
3031	serge	4283	if (IS_VALLEYVIEW(dev)) {
		4284	refclk = vlv_get_refclk(crtc);
		4285	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4286	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4104	Serge	4287	refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
3031	serge	4288	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4289	refclk / 1000);
		4290	} else if (!IS_GEN2(dev)) {
		4291	refclk = 96000;
		4292	} else {
		4293	refclk = 48000;
		4294	}
2327	Serge	4295
3031	serge	4296	return refclk;
		4297	}
2327	Serge	4298
4104	Serge	4299	static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
3031	serge	4300	{
4104	Serge	4301	return (1 << dpll->n) << 16 \| dpll->m2;
		4302	}
3746	Serge	4303
4104	Serge	4304	static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
		4305	{
		4306	return dpll->n << 16 \| dpll->m1 << 8 \| dpll->m2;
3031	serge	4307	}
2327	Serge	4308
3746	Serge	4309	static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
3031	serge	4310	intel_clock_t *reduced_clock)
		4311	{
3746	Serge	4312	struct drm_device *dev = crtc->base.dev;
3031	serge	4313	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4314	int pipe = crtc->pipe;
3031	serge	4315	u32 fp, fp2 = 0;
2327	Serge	4316
3031	serge	4317	if (IS_PINEVIEW(dev)) {
4104	Serge	4318	fp = pnv_dpll_compute_fp(&crtc->config.dpll);
3031	serge	4319	if (reduced_clock)
4104	Serge	4320	fp2 = pnv_dpll_compute_fp(reduced_clock);
3031	serge	4321	} else {
4104	Serge	4322	fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
3031	serge	4323	if (reduced_clock)
4104	Serge	4324	fp2 = i9xx_dpll_compute_fp(reduced_clock);
3031	serge	4325	}
2327	Serge	4326
3031	serge	4327	I915_WRITE(FP0(pipe), fp);
4104	Serge	4328	crtc->config.dpll_hw_state.fp0 = fp;
2327	Serge	4329
3746	Serge	4330	crtc->lowfreq_avail = false;
		4331	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4332	reduced_clock && i915_powersave) {
		4333	I915_WRITE(FP1(pipe), fp2);
4104	Serge	4334	crtc->config.dpll_hw_state.fp1 = fp2;
3746	Serge	4335	crtc->lowfreq_avail = true;
3031	serge	4336	} else {
		4337	I915_WRITE(FP1(pipe), fp);
4104	Serge	4338	crtc->config.dpll_hw_state.fp1 = fp;
3031	serge	4339	}
		4340	}
2327	Serge	4341
4104	Serge	4342	static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
		4343	{
		4344	u32 reg_val;
		4345
		4346	/*
		4347	* PLLB opamp always calibrates to max value of 0x3f, force enable it
		4348	* and set it to a reasonable value instead.
		4349	*/
		4350	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
		4351	reg_val &= 0xffffff00;
		4352	reg_val \|= 0x00000030;
		4353	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
		4354
		4355	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
		4356	reg_val &= 0x8cffffff;
		4357	reg_val = 0x8c000000;
		4358	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
		4359
		4360	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
		4361	reg_val &= 0xffffff00;
		4362	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
		4363
		4364	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
		4365	reg_val &= 0x00ffffff;
		4366	reg_val \|= 0xb0000000;
		4367	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
		4368	}
		4369
		4370	static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
		4371	struct intel_link_m_n *m_n)
		4372	{
		4373	struct drm_device *dev = crtc->base.dev;
		4374	struct drm_i915_private *dev_priv = dev->dev_private;
		4375	int pipe = crtc->pipe;
		4376
		4377	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4378	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
		4379	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
		4380	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
		4381	}
		4382
		4383	static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
		4384	struct intel_link_m_n *m_n)
		4385	{
		4386	struct drm_device *dev = crtc->base.dev;
		4387	struct drm_i915_private *dev_priv = dev->dev_private;
		4388	int pipe = crtc->pipe;
		4389	enum transcoder transcoder = crtc->config.cpu_transcoder;
		4390
		4391	if (INTEL_INFO(dev)->gen >= 5) {
		4392	I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4393	I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		4394	I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		4395	I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
		4396	} else {
		4397	I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4398	I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
		4399	I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
		4400	I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
		4401	}
		4402	}
		4403
3746	Serge	4404	static void intel_dp_set_m_n(struct intel_crtc *crtc)
3031	serge	4405	{
3746	Serge	4406	if (crtc->config.has_pch_encoder)
		4407	intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4408	else
		4409	intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4410	}
		4411
		4412	static void vlv_update_pll(struct intel_crtc *crtc)
		4413	{
		4414	struct drm_device *dev = crtc->base.dev;
3031	serge	4415	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4416	int pipe = crtc->pipe;
4104	Serge	4417	u32 dpll, mdiv;
3031	serge	4418	u32 bestn, bestm1, bestm2, bestp1, bestp2;
4104	Serge	4419	u32 coreclk, reg_val, dpll_md;
2327	Serge	4420
3480	Serge	4421	mutex_lock(&dev_priv->dpio_lock);
		4422
3746	Serge	4423	bestn = crtc->config.dpll.n;
		4424	bestm1 = crtc->config.dpll.m1;
		4425	bestm2 = crtc->config.dpll.m2;
		4426	bestp1 = crtc->config.dpll.p1;
		4427	bestp2 = crtc->config.dpll.p2;
3031	serge	4428
4104	Serge	4429	/* See eDP HDMI DPIO driver vbios notes doc */
		4430
		4431	/* PLL B needs special handling */
		4432	if (pipe)
		4433	vlv_pllb_recal_opamp(dev_priv);
		4434
		4435	/* Set up Tx target for periodic Rcomp update */
		4436	vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
		4437
		4438	/* Disable target IRef on PLL */
		4439	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
		4440	reg_val &= 0x00ffffff;
		4441	vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
		4442
		4443	/* Disable fast lock */
		4444	vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
		4445
		4446	/* Set idtafcrecal before PLL is enabled */
3031	serge	4447	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		4448	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		4449	mdiv \|= ((bestn << DPIO_N_SHIFT));
		4450	mdiv \|= (1 << DPIO_K_SHIFT);
4104	Serge	4451
		4452	/*
		4453	* Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
		4454	* but we don't support that).
		4455	* Note: don't use the DAC post divider as it seems unstable.
		4456	*/
		4457	mdiv \|= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
		4458	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
		4459
3031	serge	4460	mdiv \|= DPIO_ENABLE_CALIBRATION;
4104	Serge	4461	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
3031	serge	4462
4104	Serge	4463	/* Set HBR and RBR LPF coefficients */
		4464	if (crtc->config.port_clock == 162000 \|\|
		4465	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) \|\|
		4466	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
		4467	vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
		4468	0x009f0003);
		4469	else
		4470	vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
		4471	0x00d0000f);
3031	serge	4472
4104	Serge	4473	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) \|\|
		4474	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
		4475	/* Use SSC source */
		4476	if (!pipe)
		4477	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4478	0x0df40000);
		4479	else
		4480	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4481	0x0df70000);
		4482	} else { /* HDMI or VGA */
		4483	/* Use bend source */
		4484	if (!pipe)
		4485	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4486	0x0df70000);
		4487	else
		4488	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4489	0x0df40000);
		4490	}
3031	serge	4491
4104	Serge	4492	coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
		4493	coreclk = (coreclk & 0x0000ff00) \| 0x01c00000;
		4494	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) \|\|
		4495	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
		4496	coreclk \|= 0x01000000;
		4497	vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
3031	serge	4498
4104	Serge	4499	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
		4500
		4501	/* Enable DPIO clock input */
		4502	dpll = DPLL_EXT_BUFFER_ENABLE_VLV \| DPLL_REFA_CLK_ENABLE_VLV \|
		4503	DPLL_VGA_MODE_DIS \| DPLL_INTEGRATED_CLOCK_VLV;
		4504	if (pipe)
		4505	dpll \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		4506
3031	serge	4507	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4508	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	4509
4104	Serge	4510	dpll_md = (crtc->config.pixel_multiplier - 1)
		4511	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4512	crtc->config.dpll_hw_state.dpll_md = dpll_md;
3031	serge	4513
3746	Serge	4514	if (crtc->config.has_dp_encoder)
		4515	intel_dp_set_m_n(crtc);
3243	Serge	4516
3480	Serge	4517	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	4518	}
		4519
3746	Serge	4520	static void i9xx_update_pll(struct intel_crtc *crtc,
		4521	intel_clock_t *reduced_clock,
3031	serge	4522	int num_connectors)
		4523	{
3746	Serge	4524	struct drm_device *dev = crtc->base.dev;
3031	serge	4525	struct drm_i915_private *dev_priv = dev->dev_private;
		4526	u32 dpll;
		4527	bool is_sdvo;
3746	Serge	4528	struct dpll *clock = &crtc->config.dpll;
3031	serge	4529
3746	Serge	4530	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4531
3746	Serge	4532	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) \|\|
		4533	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
3031	serge	4534
		4535	dpll = DPLL_VGA_MODE_DIS;
		4536
3746	Serge	4537	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
3031	serge	4538	dpll \|= DPLLB_MODE_LVDS;
		4539	else
		4540	dpll \|= DPLLB_MODE_DAC_SERIAL;
3746	Serge	4541
4104	Serge	4542	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
3746	Serge	4543	dpll \|= (crtc->config.pixel_multiplier - 1)
		4544	<< SDVO_MULTIPLIER_SHIFT_HIRES;
2342	Serge	4545	}
4104	Serge	4546
		4547	if (is_sdvo)
		4548	dpll \|= DPLL_SDVO_HIGH_SPEED;
		4549
3746	Serge	4550	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4104	Serge	4551	dpll \|= DPLL_SDVO_HIGH_SPEED;
2342	Serge	4552
3031	serge	4553	/* compute bitmask from p1 value */
		4554	if (IS_PINEVIEW(dev))
		4555	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4556	else {
		4557	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4558	if (IS_G4X(dev) && reduced_clock)
		4559	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4560	}
		4561	switch (clock->p2) {
		4562	case 5:
		4563	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4564	break;
		4565	case 7:
		4566	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4567	break;
		4568	case 10:
		4569	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4570	break;
		4571	case 14:
		4572	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4573	break;
		4574	}
		4575	if (INTEL_INFO(dev)->gen >= 4)
		4576	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	4577
4104	Serge	4578	if (crtc->config.sdvo_tv_clock)
3031	serge	4579	dpll \|= PLL_REF_INPUT_TVCLKINBC;
3746	Serge	4580	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4581	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4582	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4583	else
		4584	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	4585
3031	serge	4586	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4587	crtc->config.dpll_hw_state.dpll = dpll;
2327	Serge	4588
4104	Serge	4589	if (INTEL_INFO(dev)->gen >= 4) {
		4590	u32 dpll_md = (crtc->config.pixel_multiplier - 1)
		4591	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4592	crtc->config.dpll_hw_state.dpll_md = dpll_md;
		4593	}
2327	Serge	4594
3746	Serge	4595	if (crtc->config.has_dp_encoder)
		4596	intel_dp_set_m_n(crtc);
3031	serge	4597	}
2327	Serge	4598
3746	Serge	4599	static void i8xx_update_pll(struct intel_crtc *crtc,
		4600	intel_clock_t *reduced_clock,
3031	serge	4601	int num_connectors)
		4602	{
3746	Serge	4603	struct drm_device *dev = crtc->base.dev;
3031	serge	4604	struct drm_i915_private *dev_priv = dev->dev_private;
		4605	u32 dpll;
3746	Serge	4606	struct dpll *clock = &crtc->config.dpll;
2327	Serge	4607
3746	Serge	4608	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4609
3031	serge	4610	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	4611
3746	Serge	4612	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
3031	serge	4613	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4614	} else {
		4615	if (clock->p1 == 2)
		4616	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4617	else
		4618	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4619	if (clock->p2 == 4)
		4620	dpll \|= PLL_P2_DIVIDE_BY_4;
		4621	}
2327	Serge	4622
4104	Serge	4623	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
		4624	dpll \|= DPLL_DVO_2X_MODE;
		4625
3746	Serge	4626	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4627	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4628	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4629	else
		4630	dpll \|= PLL_REF_INPUT_DREFCLK;
		4631
		4632	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4633	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	4634	}
		4635
4104	Serge	4636	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
3243	Serge	4637	{
		4638	struct drm_device *dev = intel_crtc->base.dev;
		4639	struct drm_i915_private *dev_priv = dev->dev_private;
		4640	enum pipe pipe = intel_crtc->pipe;
3746	Serge	4641	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4104	Serge	4642	struct drm_display_mode *adjusted_mode =
		4643	&intel_crtc->config.adjusted_mode;
		4644	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
		4645	uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
3243	Serge	4646
4104	Serge	4647	/* We need to be careful not to changed the adjusted mode, for otherwise
		4648	* the hw state checker will get angry at the mismatch. */
		4649	crtc_vtotal = adjusted_mode->crtc_vtotal;
		4650	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
		4651
3243	Serge	4652	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		4653	/* the chip adds 2 halflines automatically */
4104	Serge	4654	crtc_vtotal -= 1;
		4655	crtc_vblank_end -= 1;
3243	Serge	4656	vsyncshift = adjusted_mode->crtc_hsync_start
		4657	- adjusted_mode->crtc_htotal / 2;
		4658	} else {
		4659	vsyncshift = 0;
		4660	}
		4661
		4662	if (INTEL_INFO(dev)->gen > 3)
		4663	I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
		4664
		4665	I915_WRITE(HTOTAL(cpu_transcoder),
		4666	(adjusted_mode->crtc_hdisplay - 1) \|
		4667	((adjusted_mode->crtc_htotal - 1) << 16));
		4668	I915_WRITE(HBLANK(cpu_transcoder),
		4669	(adjusted_mode->crtc_hblank_start - 1) \|
		4670	((adjusted_mode->crtc_hblank_end - 1) << 16));
		4671	I915_WRITE(HSYNC(cpu_transcoder),
		4672	(adjusted_mode->crtc_hsync_start - 1) \|
		4673	((adjusted_mode->crtc_hsync_end - 1) << 16));
		4674
		4675	I915_WRITE(VTOTAL(cpu_transcoder),
		4676	(adjusted_mode->crtc_vdisplay - 1) \|
4104	Serge	4677	((crtc_vtotal - 1) << 16));
3243	Serge	4678	I915_WRITE(VBLANK(cpu_transcoder),
		4679	(adjusted_mode->crtc_vblank_start - 1) \|
4104	Serge	4680	((crtc_vblank_end - 1) << 16));
3243	Serge	4681	I915_WRITE(VSYNC(cpu_transcoder),
		4682	(adjusted_mode->crtc_vsync_start - 1) \|
		4683	((adjusted_mode->crtc_vsync_end - 1) << 16));
		4684
		4685	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
		4686	* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
		4687	* documented on the DDI_FUNC_CTL register description, EDP Input Select
		4688	* bits. */
		4689	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
		4690	(pipe == PIPE_B \|\| pipe == PIPE_C))
		4691	I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
		4692
		4693	/* pipesrc controls the size that is scaled from, which should
		4694	* always be the user's requested size.
		4695	*/
		4696	I915_WRITE(PIPESRC(pipe),
		4697	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		4698	}
		4699
4104	Serge	4700	static void intel_get_pipe_timings(struct intel_crtc *crtc,
		4701	struct intel_crtc_config *pipe_config)
		4702	{
		4703	struct drm_device *dev = crtc->base.dev;
		4704	struct drm_i915_private *dev_priv = dev->dev_private;
		4705	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		4706	uint32_t tmp;
		4707
		4708	tmp = I915_READ(HTOTAL(cpu_transcoder));
		4709	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
		4710	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
		4711	tmp = I915_READ(HBLANK(cpu_transcoder));
		4712	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
		4713	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
		4714	tmp = I915_READ(HSYNC(cpu_transcoder));
		4715	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
		4716	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
		4717
		4718	tmp = I915_READ(VTOTAL(cpu_transcoder));
		4719	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
		4720	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
		4721	tmp = I915_READ(VBLANK(cpu_transcoder));
		4722	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
		4723	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
		4724	tmp = I915_READ(VSYNC(cpu_transcoder));
		4725	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
		4726	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
		4727
		4728	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
		4729	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		4730	pipe_config->adjusted_mode.crtc_vtotal += 1;
		4731	pipe_config->adjusted_mode.crtc_vblank_end += 1;
		4732	}
		4733
		4734	tmp = I915_READ(PIPESRC(crtc->pipe));
		4735	pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
		4736	pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
		4737	}
		4738
		4739	static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
		4740	struct intel_crtc_config *pipe_config)
		4741	{
		4742	struct drm_crtc *crtc = &intel_crtc->base;
		4743
		4744	crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
		4745	crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
		4746	crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
		4747	crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
		4748
		4749	crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
		4750	crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
		4751	crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
		4752	crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
		4753
		4754	crtc->mode.flags = pipe_config->adjusted_mode.flags;
		4755
		4756	crtc->mode.clock = pipe_config->adjusted_mode.clock;
		4757	crtc->mode.flags \|= pipe_config->adjusted_mode.flags;
		4758	}
		4759
3746	Serge	4760	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
		4761	{
		4762	struct drm_device *dev = intel_crtc->base.dev;
		4763	struct drm_i915_private *dev_priv = dev->dev_private;
		4764	uint32_t pipeconf;
		4765
4104	Serge	4766	pipeconf = 0;
3746	Serge	4767
4104	Serge	4768	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		4769	I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
		4770	pipeconf \|= PIPECONF_ENABLE;
		4771
3746	Serge	4772	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4773	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4774	* core speed.
		4775	*
		4776	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4777	* pipe == 0 check?
		4778	*/
		4779	if (intel_crtc->config.requested_mode.clock >
		4780	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4781	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4782	}
		4783
4104	Serge	4784	/* only g4x and later have fancy bpc/dither controls */
		4785	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		4786	/* Bspec claims that we can't use dithering for 30bpp pipes. */
		4787	if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
		4788	pipeconf \|= PIPECONF_DITHER_EN \|
3746	Serge	4789	PIPECONF_DITHER_TYPE_SP;
		4790
4104	Serge	4791	switch (intel_crtc->config.pipe_bpp) {
		4792	case 18:
		4793	pipeconf \|= PIPECONF_6BPC;
		4794	break;
		4795	case 24:
		4796	pipeconf \|= PIPECONF_8BPC;
		4797	break;
		4798	case 30:
		4799	pipeconf \|= PIPECONF_10BPC;
		4800	break;
		4801	default:
		4802	/* Case prevented by intel_choose_pipe_bpp_dither. */
		4803	BUG();
3746	Serge	4804	}
		4805	}
		4806
		4807	if (HAS_PIPE_CXSR(dev)) {
		4808	if (intel_crtc->lowfreq_avail) {
		4809	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		4810	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		4811	} else {
		4812	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		4813	}
		4814	}
		4815
		4816	if (!IS_GEN2(dev) &&
		4817	intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
		4818	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		4819	else
		4820	pipeconf \|= PIPECONF_PROGRESSIVE;
		4821
4104	Serge	4822	if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
3746	Serge	4823	pipeconf \|= PIPECONF_COLOR_RANGE_SELECT;
		4824
		4825	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
		4826	POSTING_READ(PIPECONF(intel_crtc->pipe));
		4827	}
		4828
3031	serge	4829	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4830	int x, int y,
		4831	struct drm_framebuffer *fb)
		4832	{
		4833	struct drm_device *dev = crtc->dev;
		4834	struct drm_i915_private *dev_priv = dev->dev_private;
		4835	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	4836	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
3031	serge	4837	int pipe = intel_crtc->pipe;
		4838	int plane = intel_crtc->plane;
		4839	int refclk, num_connectors = 0;
		4840	intel_clock_t clock, reduced_clock;
3746	Serge	4841	u32 dspcntr;
4104	Serge	4842	bool ok, has_reduced_clock = false;
		4843	bool is_lvds = false;
3031	serge	4844	struct intel_encoder *encoder;
		4845	const intel_limit_t *limit;
		4846	int ret;
		4847
		4848	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4849	switch (encoder->type) {
		4850	case INTEL_OUTPUT_LVDS:
		4851	is_lvds = true;
		4852	break;
		4853	}
		4854
		4855	num_connectors++;
		4856	}
		4857
		4858	refclk = i9xx_get_refclk(crtc, num_connectors);
		4859
		4860	/*
		4861	* Returns a set of divisors for the desired target clock with the given
		4862	* refclk, or FALSE. The returned values represent the clock equation:
		4863	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4864	*/
		4865	limit = intel_limit(crtc, refclk);
4104	Serge	4866	ok = dev_priv->display.find_dpll(limit, crtc,
		4867	intel_crtc->config.port_clock,
		4868	refclk, NULL, &clock);
		4869	if (!ok && !intel_crtc->config.clock_set) {
3031	serge	4870	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4871	return -EINVAL;
		4872	}
		4873
		4874	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4875	/*
		4876	* Ensure we match the reduced clock's P to the target clock.
		4877	* If the clocks don't match, we can't switch the display clock
		4878	* by using the FP0/FP1. In such case we will disable the LVDS
		4879	* downclock feature.
		4880	*/
4104	Serge	4881	has_reduced_clock =
		4882	dev_priv->display.find_dpll(limit, crtc,
3031	serge	4883	dev_priv->lvds_downclock,
4104	Serge	4884	refclk, &clock,
3031	serge	4885	&reduced_clock);
		4886	}
3746	Serge	4887	/* Compat-code for transition, will disappear. */
		4888	if (!intel_crtc->config.clock_set) {
		4889	intel_crtc->config.dpll.n = clock.n;
		4890	intel_crtc->config.dpll.m1 = clock.m1;
		4891	intel_crtc->config.dpll.m2 = clock.m2;
		4892	intel_crtc->config.dpll.p1 = clock.p1;
		4893	intel_crtc->config.dpll.p2 = clock.p2;
		4894	}
3031	serge	4895
		4896	if (IS_GEN2(dev))
4104	Serge	4897	i8xx_update_pll(intel_crtc,
3243	Serge	4898	has_reduced_clock ? &reduced_clock : NULL,
		4899	num_connectors);
3031	serge	4900	else if (IS_VALLEYVIEW(dev))
3746	Serge	4901	vlv_update_pll(intel_crtc);
3031	serge	4902	else
3746	Serge	4903	i9xx_update_pll(intel_crtc,
3031	serge	4904	has_reduced_clock ? &reduced_clock : NULL,
		4905	num_connectors);
		4906
		4907	/* Set up the display plane register */
		4908	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4909
3746	Serge	4910	if (!IS_VALLEYVIEW(dev)) {
3031	serge	4911	if (pipe == 0)
		4912	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4913	else
		4914	dspcntr \|= DISPPLANE_SEL_PIPE_B;
3243	Serge	4915	}
		4916
4104	Serge	4917	intel_set_pipe_timings(intel_crtc);
3031	serge	4918
		4919	/* pipesrc and dspsize control the size that is scaled from,
		4920	* which should always be the user's requested size.
		4921	*/
		4922	I915_WRITE(DSPSIZE(plane),
		4923	((mode->vdisplay - 1) << 16) \|
		4924	(mode->hdisplay - 1));
		4925	I915_WRITE(DSPPOS(plane), 0);
2327	Serge	4926
3746	Serge	4927	i9xx_set_pipeconf(intel_crtc);
		4928
3031	serge	4929	I915_WRITE(DSPCNTR(plane), dspcntr);
		4930	POSTING_READ(DSPCNTR(plane));
2327	Serge	4931
3031	serge	4932	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	4933
3031	serge	4934	intel_update_watermarks(dev);
		4935
2327	Serge	4936	return ret;
		4937	}
		4938
4104	Serge	4939	static void i9xx_get_pfit_config(struct intel_crtc *crtc,
		4940	struct intel_crtc_config *pipe_config)
		4941	{
		4942	struct drm_device *dev = crtc->base.dev;
		4943	struct drm_i915_private *dev_priv = dev->dev_private;
		4944	uint32_t tmp;
		4945
		4946	tmp = I915_READ(PFIT_CONTROL);
		4947	if (!(tmp & PFIT_ENABLE))
		4948	return;
		4949
		4950	/* Check whether the pfit is attached to our pipe. */
		4951	if (INTEL_INFO(dev)->gen < 4) {
		4952	if (crtc->pipe != PIPE_B)
		4953	return;
		4954	} else {
		4955	if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
		4956	return;
		4957	}
		4958
		4959	pipe_config->gmch_pfit.control = tmp;
		4960	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
		4961	if (INTEL_INFO(dev)->gen < 5)
		4962	pipe_config->gmch_pfit.lvds_border_bits =
		4963	I915_READ(LVDS) & LVDS_BORDER_ENABLE;
		4964	}
		4965
3746	Serge	4966	static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
		4967	struct intel_crtc_config *pipe_config)
		4968	{
		4969	struct drm_device *dev = crtc->base.dev;
		4970	struct drm_i915_private *dev_priv = dev->dev_private;
		4971	uint32_t tmp;
		4972
4104	Serge	4973	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		4974	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		4975
3746	Serge	4976	tmp = I915_READ(PIPECONF(crtc->pipe));
		4977	if (!(tmp & PIPECONF_ENABLE))
		4978	return false;
		4979
4104	Serge	4980	intel_get_pipe_timings(crtc, pipe_config);
		4981
		4982	i9xx_get_pfit_config(crtc, pipe_config);
		4983
		4984	if (INTEL_INFO(dev)->gen >= 4) {
		4985	tmp = I915_READ(DPLL_MD(crtc->pipe));
		4986	pipe_config->pixel_multiplier =
		4987	((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
		4988	>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
		4989	pipe_config->dpll_hw_state.dpll_md = tmp;
		4990	} else if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
		4991	tmp = I915_READ(DPLL(crtc->pipe));
		4992	pipe_config->pixel_multiplier =
		4993	((tmp & SDVO_MULTIPLIER_MASK)
		4994	>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
		4995	} else {
		4996	/* Note that on i915G/GM the pixel multiplier is in the sdvo
		4997	* port and will be fixed up in the encoder->get_config
		4998	* function. */
		4999	pipe_config->pixel_multiplier = 1;
		5000	}
		5001	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
		5002	if (!IS_VALLEYVIEW(dev)) {
		5003	pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
		5004	pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
		5005	} else {
		5006	/* Mask out read-only status bits. */
		5007	pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV \|
		5008	DPLL_PORTC_READY_MASK \|
		5009	DPLL_PORTB_READY_MASK);
		5010	}
		5011
3746	Serge	5012	return true;
		5013	}
		5014
3243	Serge	5015	static void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	5016	{
		5017	struct drm_i915_private *dev_priv = dev->dev_private;
		5018	struct drm_mode_config *mode_config = &dev->mode_config;
		5019	struct intel_encoder *encoder;
3746	Serge	5020	u32 val, final;
2327	Serge	5021	bool has_lvds = false;
2342	Serge	5022	bool has_cpu_edp = false;
		5023	bool has_panel = false;
		5024	bool has_ck505 = false;
		5025	bool can_ssc = false;
2327	Serge	5026
		5027	/* We need to take the global config into account */
		5028	list_for_each_entry(encoder, &mode_config->encoder_list,
		5029	base.head) {
		5030	switch (encoder->type) {
		5031	case INTEL_OUTPUT_LVDS:
2342	Serge	5032	has_panel = true;
2327	Serge	5033	has_lvds = true;
2342	Serge	5034	break;
2327	Serge	5035	case INTEL_OUTPUT_EDP:
2342	Serge	5036	has_panel = true;
4104	Serge	5037	if (enc_to_dig_port(&encoder->base)->port == PORT_A)
2342	Serge	5038	has_cpu_edp = true;
2327	Serge	5039	break;
		5040	}
		5041	}
2342	Serge	5042
		5043	if (HAS_PCH_IBX(dev)) {
4104	Serge	5044	has_ck505 = dev_priv->vbt.display_clock_mode;
2342	Serge	5045	can_ssc = has_ck505;
		5046	} else {
		5047	has_ck505 = false;
		5048	can_ssc = true;
2327	Serge	5049	}
		5050
4104	Serge	5051	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
		5052	has_panel, has_lvds, has_ck505);
2342	Serge	5053
2327	Serge	5054	/* Ironlake: try to setup display ref clock before DPLL
		5055	* enabling. This is only under driver's control after
		5056	* PCH B stepping, previous chipset stepping should be
		5057	* ignoring this setting.
		5058	*/
3746	Serge	5059	val = I915_READ(PCH_DREF_CONTROL);
		5060
		5061	/* As we must carefully and slowly disable/enable each source in turn,
		5062	* compute the final state we want first and check if we need to
		5063	* make any changes at all.
		5064	*/
		5065	final = val;
		5066	final &= ~DREF_NONSPREAD_SOURCE_MASK;
		5067	if (has_ck505)
		5068	final \|= DREF_NONSPREAD_CK505_ENABLE;
		5069	else
		5070	final \|= DREF_NONSPREAD_SOURCE_ENABLE;
		5071
		5072	final &= ~DREF_SSC_SOURCE_MASK;
		5073	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		5074	final &= ~DREF_SSC1_ENABLE;
		5075
		5076	if (has_panel) {
		5077	final \|= DREF_SSC_SOURCE_ENABLE;
		5078
		5079	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		5080	final \|= DREF_SSC1_ENABLE;
		5081
		5082	if (has_cpu_edp) {
		5083	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		5084	final \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		5085	else
		5086	final \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		5087	} else
		5088	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		5089	} else {
		5090	final \|= DREF_SSC_SOURCE_DISABLE;
		5091	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		5092	}
		5093
		5094	if (final == val)
		5095	return;
		5096
2327	Serge	5097	/* Always enable nonspread source */
3746	Serge	5098	val &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	5099
		5100	if (has_ck505)
3746	Serge	5101	val \|= DREF_NONSPREAD_CK505_ENABLE;
2342	Serge	5102	else
3746	Serge	5103	val \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	5104
		5105	if (has_panel) {
3746	Serge	5106	val &= ~DREF_SSC_SOURCE_MASK;
		5107	val \|= DREF_SSC_SOURCE_ENABLE;
2327	Serge	5108
2342	Serge	5109	/* SSC must be turned on before enabling the CPU output */
		5110	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		5111	DRM_DEBUG_KMS("Using SSC on panel\n");
3746	Serge	5112	val \|= DREF_SSC1_ENABLE;
3031	serge	5113	} else
3746	Serge	5114	val &= ~DREF_SSC1_ENABLE;
2327	Serge	5115
2342	Serge	5116	/* Get SSC going before enabling the outputs */
3746	Serge	5117	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	5118	POSTING_READ(PCH_DREF_CONTROL);
		5119	udelay(200);
2342	Serge	5120
3746	Serge	5121	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2327	Serge	5122
		5123	/* Enable CPU source on CPU attached eDP */
2342	Serge	5124	if (has_cpu_edp) {
		5125	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		5126	DRM_DEBUG_KMS("Using SSC on eDP\n");
3746	Serge	5127	val \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2342	Serge	5128	}
2327	Serge	5129	else
3746	Serge	5130	val \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	5131	} else
3746	Serge	5132	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	5133
3746	Serge	5134	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	5135	POSTING_READ(PCH_DREF_CONTROL);
		5136	udelay(200);
2327	Serge	5137	} else {
2342	Serge	5138	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		5139
3746	Serge	5140	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2342	Serge	5141
		5142	/* Turn off CPU output */
3746	Serge	5143	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	5144
3746	Serge	5145	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	5146	POSTING_READ(PCH_DREF_CONTROL);
		5147	udelay(200);
2342	Serge	5148
		5149	/* Turn off the SSC source */
3746	Serge	5150	val &= ~DREF_SSC_SOURCE_MASK;
		5151	val \|= DREF_SSC_SOURCE_DISABLE;
2342	Serge	5152
		5153	/* Turn off SSC1 */
3746	Serge	5154	val &= ~DREF_SSC1_ENABLE;
2342	Serge	5155
3746	Serge	5156	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	5157	POSTING_READ(PCH_DREF_CONTROL);
		5158	udelay(200);
2327	Serge	5159	}
3746	Serge	5160
		5161	BUG_ON(val != final);
2327	Serge	5162	}
		5163
4104	Serge	5164	static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
3243	Serge	5165	{
4104	Serge	5166	uint32_t tmp;
3243	Serge	5167
		5168	tmp = I915_READ(SOUTH_CHICKEN2);
		5169	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;
		5170	I915_WRITE(SOUTH_CHICKEN2, tmp);
		5171
		5172	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
		5173	FDI_MPHY_IOSFSB_RESET_STATUS, 100))
		5174	DRM_ERROR("FDI mPHY reset assert timeout\n");
		5175
		5176	tmp = I915_READ(SOUTH_CHICKEN2);
		5177	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		5178	I915_WRITE(SOUTH_CHICKEN2, tmp);
		5179
		5180	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4104	Serge	5181	FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
3243	Serge	5182	DRM_ERROR("FDI mPHY reset de-assert timeout\n");
		5183	}
		5184
4104	Serge	5185	/* WaMPhyProgramming:hsw */
		5186	static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
		5187	{
		5188	uint32_t tmp;
		5189
3243	Serge	5190	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
		5191	tmp &= ~(0xFF << 24);
		5192	tmp \|= (0x12 << 24);
		5193	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
		5194
		5195	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
		5196	tmp \|= (1 << 11);
		5197	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
		5198
		5199	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
		5200	tmp \|= (1 << 11);
		5201	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
		5202
		5203	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
		5204	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		5205	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
		5206
		5207	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
		5208	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		5209	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
		5210
		5211	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		5212	tmp &= ~(7 << 13);
		5213	tmp \|= (5 << 13);
		5214	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
		5215
		5216	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		5217	tmp &= ~(7 << 13);
		5218	tmp \|= (5 << 13);
		5219	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
		5220
		5221	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
		5222	tmp &= ~0xFF;
		5223	tmp \|= 0x1C;
		5224	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
		5225
		5226	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
		5227	tmp &= ~0xFF;
		5228	tmp \|= 0x1C;
		5229	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
		5230
		5231	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
		5232	tmp &= ~(0xFF << 16);
		5233	tmp \|= (0x1C << 16);
		5234	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
		5235
		5236	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
		5237	tmp &= ~(0xFF << 16);
		5238	tmp \|= (0x1C << 16);
		5239	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
		5240
		5241	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		5242	tmp \|= (1 << 27);
		5243	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
		5244
		5245	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		5246	tmp \|= (1 << 27);
		5247	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
		5248
		5249	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		5250	tmp &= ~(0xF << 28);
		5251	tmp \|= (4 << 28);
		5252	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
		5253
		5254	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		5255	tmp &= ~(0xF << 28);
		5256	tmp \|= (4 << 28);
		5257	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
		5258	}
		5259
4104	Serge	5260	/* Implements 3 different sequences from BSpec chapter "Display iCLK
		5261	* Programming" based on the parameters passed:
		5262	* - Sequence to enable CLKOUT_DP
		5263	* - Sequence to enable CLKOUT_DP without spread
		5264	* - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
		5265	*/
		5266	static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
		5267	bool with_fdi)
		5268	{
		5269	struct drm_i915_private *dev_priv = dev->dev_private;
		5270	uint32_t reg, tmp;
3480	Serge	5271
4104	Serge	5272	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
		5273	with_spread = true;
		5274	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
		5275	with_fdi, "LP PCH doesn't have FDI\n"))
		5276	with_fdi = false;
		5277
		5278	mutex_lock(&dev_priv->dpio_lock);
		5279
		5280	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5281	tmp &= ~SBI_SSCCTL_DISABLE;
		5282	tmp \|= SBI_SSCCTL_PATHALT;
		5283	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5284
		5285	udelay(24);
		5286
		5287	if (with_spread) {
		5288	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5289	tmp &= ~SBI_SSCCTL_PATHALT;
		5290	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5291
		5292	if (with_fdi) {
		5293	lpt_reset_fdi_mphy(dev_priv);
		5294	lpt_program_fdi_mphy(dev_priv);
		5295	}
		5296	}
		5297
		5298	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		5299	SBI_GEN0 : SBI_DBUFF0;
		5300	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		5301	tmp \|= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		5302	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		5303
3480	Serge	5304	mutex_unlock(&dev_priv->dpio_lock);
3243	Serge	5305	}
		5306
4104	Serge	5307	/* Sequence to disable CLKOUT_DP */
		5308	static void lpt_disable_clkout_dp(struct drm_device *dev)
		5309	{
		5310	struct drm_i915_private *dev_priv = dev->dev_private;
		5311	uint32_t reg, tmp;
		5312
		5313	mutex_lock(&dev_priv->dpio_lock);
		5314
		5315	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		5316	SBI_GEN0 : SBI_DBUFF0;
		5317	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		5318	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		5319	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		5320
		5321	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5322	if (!(tmp & SBI_SSCCTL_DISABLE)) {
		5323	if (!(tmp & SBI_SSCCTL_PATHALT)) {
		5324	tmp \|= SBI_SSCCTL_PATHALT;
		5325	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5326	udelay(32);
		5327	}
		5328	tmp \|= SBI_SSCCTL_DISABLE;
		5329	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5330	}
		5331
		5332	mutex_unlock(&dev_priv->dpio_lock);
		5333	}
		5334
		5335	static void lpt_init_pch_refclk(struct drm_device *dev)
		5336	{
		5337	struct drm_mode_config *mode_config = &dev->mode_config;
		5338	struct intel_encoder *encoder;
		5339	bool has_vga = false;
		5340
		5341	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		5342	switch (encoder->type) {
		5343	case INTEL_OUTPUT_ANALOG:
		5344	has_vga = true;
		5345	break;
		5346	}
		5347	}
		5348
		5349	if (has_vga)
		5350	lpt_enable_clkout_dp(dev, true, true);
		5351	else
		5352	lpt_disable_clkout_dp(dev);
		5353	}
		5354
3243	Serge	5355	/*
		5356	* Initialize reference clocks when the driver loads
		5357	*/
		5358	void intel_init_pch_refclk(struct drm_device *dev)
		5359	{
		5360	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		5361	ironlake_init_pch_refclk(dev);
		5362	else if (HAS_PCH_LPT(dev))
		5363	lpt_init_pch_refclk(dev);
		5364	}
		5365
2342	Serge	5366	static int ironlake_get_refclk(struct drm_crtc *crtc)
		5367	{
		5368	struct drm_device *dev = crtc->dev;
		5369	struct drm_i915_private *dev_priv = dev->dev_private;
		5370	struct intel_encoder *encoder;
		5371	int num_connectors = 0;
		5372	bool is_lvds = false;
		5373
3031	serge	5374	for_each_encoder_on_crtc(dev, crtc, encoder) {
2342	Serge	5375	switch (encoder->type) {
		5376	case INTEL_OUTPUT_LVDS:
		5377	is_lvds = true;
		5378	break;
		5379	}
		5380	num_connectors++;
		5381	}
		5382
		5383	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		5384	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4104	Serge	5385	dev_priv->vbt.lvds_ssc_freq);
		5386	return dev_priv->vbt.lvds_ssc_freq * 1000;
2342	Serge	5387	}
		5388
		5389	return 120000;
		5390	}
		5391
4104	Serge	5392	static void ironlake_set_pipeconf(struct drm_crtc *crtc)
3031	serge	5393	{
		5394	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5395	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5396	int pipe = intel_crtc->pipe;
		5397	uint32_t val;
		5398
4104	Serge	5399	val = 0;
3031	serge	5400
3746	Serge	5401	switch (intel_crtc->config.pipe_bpp) {
3031	serge	5402	case 18:
3480	Serge	5403	val \|= PIPECONF_6BPC;
3031	serge	5404	break;
		5405	case 24:
3480	Serge	5406	val \|= PIPECONF_8BPC;
3031	serge	5407	break;
		5408	case 30:
3480	Serge	5409	val \|= PIPECONF_10BPC;
3031	serge	5410	break;
		5411	case 36:
3480	Serge	5412	val \|= PIPECONF_12BPC;
3031	serge	5413	break;
		5414	default:
3243	Serge	5415	/* Case prevented by intel_choose_pipe_bpp_dither. */
		5416	BUG();
3031	serge	5417	}
		5418
4104	Serge	5419	if (intel_crtc->config.dither)
3031	serge	5420	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5421
4104	Serge	5422	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3031	serge	5423	val \|= PIPECONF_INTERLACED_ILK;
		5424	else
		5425	val \|= PIPECONF_PROGRESSIVE;
		5426
3746	Serge	5427	if (intel_crtc->config.limited_color_range)
3480	Serge	5428	val \|= PIPECONF_COLOR_RANGE_SELECT;
		5429
3031	serge	5430	I915_WRITE(PIPECONF(pipe), val);
		5431	POSTING_READ(PIPECONF(pipe));
		5432	}
		5433
3480	Serge	5434	/*
		5435	* Set up the pipe CSC unit.
		5436	*
		5437	* Currently only full range RGB to limited range RGB conversion
		5438	* is supported, but eventually this should handle various
		5439	* RGB<->YCbCr scenarios as well.
		5440	*/
3746	Serge	5441	static void intel_set_pipe_csc(struct drm_crtc *crtc)
3480	Serge	5442	{
		5443	struct drm_device *dev = crtc->dev;
		5444	struct drm_i915_private *dev_priv = dev->dev_private;
		5445	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5446	int pipe = intel_crtc->pipe;
		5447	uint16_t coeff = 0x7800; /* 1.0 */
		5448
		5449	/*
		5450	* TODO: Check what kind of values actually come out of the pipe
		5451	* with these coeff/postoff values and adjust to get the best
		5452	* accuracy. Perhaps we even need to take the bpc value into
		5453	* consideration.
		5454	*/
		5455
3746	Serge	5456	if (intel_crtc->config.limited_color_range)
3480	Serge	5457	coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
		5458
		5459	/*
		5460	* GY/GU and RY/RU should be the other way around according
		5461	* to BSpec, but reality doesn't agree. Just set them up in
		5462	* a way that results in the correct picture.
		5463	*/
		5464	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
		5465	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
		5466
		5467	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
		5468	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
		5469
		5470	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
		5471	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
		5472
		5473	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
		5474	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
		5475	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
		5476
		5477	if (INTEL_INFO(dev)->gen > 6) {
		5478	uint16_t postoff = 0;
		5479
3746	Serge	5480	if (intel_crtc->config.limited_color_range)
3480	Serge	5481	postoff = (16 * (1 << 13) / 255) & 0x1fff;
		5482
		5483	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		5484	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		5485	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
		5486
		5487	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
		5488	} else {
		5489	uint32_t mode = CSC_MODE_YUV_TO_RGB;
		5490
3746	Serge	5491	if (intel_crtc->config.limited_color_range)
3480	Serge	5492	mode \|= CSC_BLACK_SCREEN_OFFSET;
		5493
		5494	I915_WRITE(PIPE_CSC_MODE(pipe), mode);
		5495	}
		5496	}
		5497
4104	Serge	5498	static void haswell_set_pipeconf(struct drm_crtc *crtc)
3243	Serge	5499	{
		5500	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5501	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5502	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	5503	uint32_t val;
		5504
4104	Serge	5505	val = 0;
3243	Serge	5506
4104	Serge	5507	if (intel_crtc->config.dither)
3243	Serge	5508	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5509
4104	Serge	5510	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3243	Serge	5511	val \|= PIPECONF_INTERLACED_ILK;
		5512	else
		5513	val \|= PIPECONF_PROGRESSIVE;
		5514
		5515	I915_WRITE(PIPECONF(cpu_transcoder), val);
		5516	POSTING_READ(PIPECONF(cpu_transcoder));
4104	Serge	5517
		5518	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
		5519	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
3243	Serge	5520	}
		5521
3031	serge	5522	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
		5523	intel_clock_t *clock,
		5524	bool *has_reduced_clock,
		5525	intel_clock_t *reduced_clock)
		5526	{
		5527	struct drm_device *dev = crtc->dev;
		5528	struct drm_i915_private *dev_priv = dev->dev_private;
		5529	struct intel_encoder *intel_encoder;
		5530	int refclk;
		5531	const intel_limit_t *limit;
4104	Serge	5532	bool ret, is_lvds = false;
3031	serge	5533
		5534	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5535	switch (intel_encoder->type) {
		5536	case INTEL_OUTPUT_LVDS:
		5537	is_lvds = true;
		5538	break;
		5539	}
		5540	}
		5541
		5542	refclk = ironlake_get_refclk(crtc);
		5543
		5544	/*
		5545	* Returns a set of divisors for the desired target clock with the given
		5546	* refclk, or FALSE. The returned values represent the clock equation:
		5547	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		5548	*/
		5549	limit = intel_limit(crtc, refclk);
4104	Serge	5550	ret = dev_priv->display.find_dpll(limit, crtc,
		5551	to_intel_crtc(crtc)->config.port_clock,
		5552	refclk, NULL, clock);
3031	serge	5553	if (!ret)
		5554	return false;
		5555
		5556	if (is_lvds && dev_priv->lvds_downclock_avail) {
		5557	/*
		5558	* Ensure we match the reduced clock's P to the target clock.
		5559	* If the clocks don't match, we can't switch the display clock
		5560	* by using the FP0/FP1. In such case we will disable the LVDS
		5561	* downclock feature.
		5562	*/
4104	Serge	5563	*has_reduced_clock =
		5564	dev_priv->display.find_dpll(limit, crtc,
3031	serge	5565	dev_priv->lvds_downclock,
4104	Serge	5566	refclk, clock,
3031	serge	5567	reduced_clock);
		5568	}
		5569
		5570	return true;
		5571	}
		5572
3243	Serge	5573	static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
		5574	{
		5575	struct drm_i915_private *dev_priv = dev->dev_private;
		5576	uint32_t temp;
		5577
		5578	temp = I915_READ(SOUTH_CHICKEN1);
		5579	if (temp & FDI_BC_BIFURCATION_SELECT)
		5580	return;
		5581
		5582	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		5583	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		5584
		5585	temp \|= FDI_BC_BIFURCATION_SELECT;
		5586	DRM_DEBUG_KMS("enabling fdi C rx\n");
		5587	I915_WRITE(SOUTH_CHICKEN1, temp);
		5588	POSTING_READ(SOUTH_CHICKEN1);
		5589	}
		5590
4104	Serge	5591	static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3243	Serge	5592	{
		5593	struct drm_device *dev = intel_crtc->base.dev;
		5594	struct drm_i915_private *dev_priv = dev->dev_private;
		5595
		5596	switch (intel_crtc->pipe) {
		5597	case PIPE_A:
4104	Serge	5598	break;
3243	Serge	5599	case PIPE_B:
4104	Serge	5600	if (intel_crtc->config.fdi_lanes > 2)
3243	Serge	5601	WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		5602	else
		5603	cpt_enable_fdi_bc_bifurcation(dev);
		5604
4104	Serge	5605	break;
3243	Serge	5606	case PIPE_C:
		5607	cpt_enable_fdi_bc_bifurcation(dev);
		5608
4104	Serge	5609	break;
3243	Serge	5610	default:
		5611	BUG();
		5612	}
		5613	}
		5614
		5615	int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
		5616	{
		5617	/*
		5618	* Account for spread spectrum to avoid
		5619	* oversubscribing the link. Max center spread
		5620	* is 2.5%; use 5% for safety's sake.
		5621	*/
		5622	u32 bps = target_clock * bpp * 21 / 20;
		5623	return bps / (link_bw * 8) + 1;
		5624	}
		5625
4104	Serge	5626	static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
2327	Serge	5627	{
4104	Serge	5628	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
3746	Serge	5629	}
		5630
3243	Serge	5631	static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4104	Serge	5632	u32 *fp,
3746	Serge	5633	intel_clock_t reduced_clock, u32 fp2)
3243	Serge	5634	{
		5635	struct drm_crtc *crtc = &intel_crtc->base;
		5636	struct drm_device *dev = crtc->dev;
		5637	struct drm_i915_private *dev_priv = dev->dev_private;
		5638	struct intel_encoder *intel_encoder;
		5639	uint32_t dpll;
3746	Serge	5640	int factor, num_connectors = 0;
4104	Serge	5641	bool is_lvds = false, is_sdvo = false;
3243	Serge	5642
		5643	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5644	switch (intel_encoder->type) {
		5645	case INTEL_OUTPUT_LVDS:
		5646	is_lvds = true;
		5647	break;
		5648	case INTEL_OUTPUT_SDVO:
		5649	case INTEL_OUTPUT_HDMI:
		5650	is_sdvo = true;
		5651	break;
		5652	}
		5653
		5654	num_connectors++;
		5655	}
		5656
2327	Serge	5657	/* Enable autotuning of the PLL clock (if permissible) */
		5658	factor = 21;
		5659	if (is_lvds) {
		5660	if ((intel_panel_use_ssc(dev_priv) &&
4104	Serge	5661	dev_priv->vbt.lvds_ssc_freq == 100) \|\|
3746	Serge	5662	(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
2327	Serge	5663	factor = 25;
4104	Serge	5664	} else if (intel_crtc->config.sdvo_tv_clock)
2327	Serge	5665	factor = 20;
		5666
4104	Serge	5667	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
3746	Serge	5668	*fp \|= FP_CB_TUNE;
2327	Serge	5669
3746	Serge	5670	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		5671	*fp2 \|= FP_CB_TUNE;
		5672
2327	Serge	5673	dpll = 0;
		5674
		5675	if (is_lvds)
		5676	dpll \|= DPLLB_MODE_LVDS;
		5677	else
		5678	dpll \|= DPLLB_MODE_DAC_SERIAL;
4104	Serge	5679
3746	Serge	5680	dpll \|= (intel_crtc->config.pixel_multiplier - 1)
		5681	<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2327	Serge	5682
4104	Serge	5683	if (is_sdvo)
		5684	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5685	if (intel_crtc->config.has_dp_encoder)
		5686	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5687
2327	Serge	5688	/* compute bitmask from p1 value */
4104	Serge	5689	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2327	Serge	5690	/* also FPA1 */
4104	Serge	5691	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2327	Serge	5692
4104	Serge	5693	switch (intel_crtc->config.dpll.p2) {
2327	Serge	5694	case 5:
		5695	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		5696	break;
		5697	case 7:
		5698	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		5699	break;
		5700	case 10:
		5701	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		5702	break;
		5703	case 14:
		5704	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		5705	break;
		5706	}
		5707
4104	Serge	5708	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
2327	Serge	5709	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5710	else
		5711	dpll \|= PLL_REF_INPUT_DREFCLK;
		5712
4104	Serge	5713	return dpll \| DPLL_VCO_ENABLE;
3243	Serge	5714	}
		5715
		5716	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		5717	int x, int y,
		5718	struct drm_framebuffer *fb)
		5719	{
		5720	struct drm_device *dev = crtc->dev;
		5721	struct drm_i915_private *dev_priv = dev->dev_private;
		5722	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5723	int pipe = intel_crtc->pipe;
		5724	int plane = intel_crtc->plane;
		5725	int num_connectors = 0;
		5726	intel_clock_t clock, reduced_clock;
4104	Serge	5727	u32 dpll = 0, fp = 0, fp2 = 0;
3243	Serge	5728	bool ok, has_reduced_clock = false;
3746	Serge	5729	bool is_lvds = false;
3243	Serge	5730	struct intel_encoder *encoder;
4104	Serge	5731	struct intel_shared_dpll *pll;
3243	Serge	5732	int ret;
		5733
		5734	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5735	switch (encoder->type) {
		5736	case INTEL_OUTPUT_LVDS:
		5737	is_lvds = true;
		5738	break;
		5739	}
		5740
		5741	num_connectors++;
		5742	}
		5743
		5744	WARN(!(HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)),
		5745	"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
		5746
4104	Serge	5747	ok = ironlake_compute_clocks(crtc, &clock,
3243	Serge	5748	&has_reduced_clock, &reduced_clock);
4104	Serge	5749	if (!ok && !intel_crtc->config.clock_set) {
3243	Serge	5750	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		5751	return -EINVAL;
		5752	}
3746	Serge	5753	/* Compat-code for transition, will disappear. */
		5754	if (!intel_crtc->config.clock_set) {
		5755	intel_crtc->config.dpll.n = clock.n;
		5756	intel_crtc->config.dpll.m1 = clock.m1;
		5757	intel_crtc->config.dpll.m2 = clock.m2;
		5758	intel_crtc->config.dpll.p1 = clock.p1;
		5759	intel_crtc->config.dpll.p2 = clock.p2;
		5760	}
3243	Serge	5761
4104	Serge	5762	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
		5763	if (intel_crtc->config.has_pch_encoder) {
		5764	fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
3243	Serge	5765	if (has_reduced_clock)
4104	Serge	5766	fp2 = i9xx_dpll_compute_fp(&reduced_clock);
3243	Serge	5767
4104	Serge	5768	dpll = ironlake_compute_dpll(intel_crtc,
		5769	&fp, &reduced_clock,
3746	Serge	5770	has_reduced_clock ? &fp2 : NULL);
3243	Serge	5771
4104	Serge	5772	intel_crtc->config.dpll_hw_state.dpll = dpll;
		5773	intel_crtc->config.dpll_hw_state.fp0 = fp;
		5774	if (has_reduced_clock)
		5775	intel_crtc->config.dpll_hw_state.fp1 = fp2;
		5776	else
		5777	intel_crtc->config.dpll_hw_state.fp1 = fp;
2327	Serge	5778
4104	Serge	5779	pll = intel_get_shared_dpll(intel_crtc);
3031	serge	5780	if (pll == NULL) {
4104	Serge	5781	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		5782	pipe_name(pipe));
2342	Serge	5783	return -EINVAL;
2327	Serge	5784	}
3031	serge	5785	} else
4104	Serge	5786	intel_put_shared_dpll(intel_crtc);
2327	Serge	5787
3746	Serge	5788	if (intel_crtc->config.has_dp_encoder)
		5789	intel_dp_set_m_n(intel_crtc);
2342	Serge	5790
4104	Serge	5791	if (is_lvds && has_reduced_clock && i915_powersave)
		5792	intel_crtc->lowfreq_avail = true;
		5793	else
		5794	intel_crtc->lowfreq_avail = false;
2327	Serge	5795
4104	Serge	5796	if (intel_crtc->config.has_pch_encoder) {
		5797	pll = intel_crtc_to_shared_dpll(intel_crtc);
2327	Serge	5798
4104	Serge	5799	}
2327	Serge	5800
4104	Serge	5801	intel_set_pipe_timings(intel_crtc);
2327	Serge	5802
4104	Serge	5803	if (intel_crtc->config.has_pch_encoder) {
		5804	intel_cpu_transcoder_set_m_n(intel_crtc,
		5805	&intel_crtc->config.fdi_m_n);
2342	Serge	5806	}
2327	Serge	5807
4104	Serge	5808	if (IS_IVYBRIDGE(dev))
		5809	ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3243	Serge	5810
4104	Serge	5811	ironlake_set_pipeconf(crtc);
3243	Serge	5812
		5813	/* Set up the display plane register */
		5814	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
		5815	POSTING_READ(DSPCNTR(plane));
		5816
		5817	ret = intel_pipe_set_base(crtc, x, y, fb);
		5818
		5819	intel_update_watermarks(dev);
		5820
4104	Serge	5821	return ret;
		5822	}
3243	Serge	5823
4104	Serge	5824	static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
		5825	struct intel_crtc_config *pipe_config)
		5826	{
		5827	struct drm_device *dev = crtc->base.dev;
		5828	struct drm_i915_private *dev_priv = dev->dev_private;
		5829	enum transcoder transcoder = pipe_config->cpu_transcoder;
		5830
		5831	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
		5832	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
		5833	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
		5834	& ~TU_SIZE_MASK;
		5835	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
		5836	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
		5837	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
3243	Serge	5838	}
		5839
4104	Serge	5840	static void ironlake_get_pfit_config(struct intel_crtc *crtc,
		5841	struct intel_crtc_config *pipe_config)
		5842	{
		5843	struct drm_device *dev = crtc->base.dev;
		5844	struct drm_i915_private *dev_priv = dev->dev_private;
		5845	uint32_t tmp;
		5846
		5847	tmp = I915_READ(PF_CTL(crtc->pipe));
		5848
		5849	if (tmp & PF_ENABLE) {
		5850	pipe_config->pch_pfit.enabled = true;
		5851	pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
		5852	pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
		5853
		5854	/* We currently do not free assignements of panel fitters on
		5855	* ivb/hsw (since we don't use the higher upscaling modes which
		5856	* differentiates them) so just WARN about this case for now. */
		5857	if (IS_GEN7(dev)) {
		5858	WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
		5859	PF_PIPE_SEL_IVB(crtc->pipe));
		5860	}
		5861	}
		5862	}
		5863
3746	Serge	5864	static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
		5865	struct intel_crtc_config *pipe_config)
		5866	{
		5867	struct drm_device *dev = crtc->base.dev;
		5868	struct drm_i915_private *dev_priv = dev->dev_private;
		5869	uint32_t tmp;
		5870
4104	Serge	5871	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		5872	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		5873
3746	Serge	5874	tmp = I915_READ(PIPECONF(crtc->pipe));
		5875	if (!(tmp & PIPECONF_ENABLE))
		5876	return false;
		5877
4104	Serge	5878	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
		5879	struct intel_shared_dpll *pll;
		5880
3746	Serge	5881	pipe_config->has_pch_encoder = true;
		5882
4104	Serge	5883	tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
		5884	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		5885	FDI_DP_PORT_WIDTH_SHIFT) + 1;
		5886
		5887	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		5888
		5889	if (HAS_PCH_IBX(dev_priv->dev)) {
		5890	pipe_config->shared_dpll =
		5891	(enum intel_dpll_id) crtc->pipe;
		5892	} else {
		5893	tmp = I915_READ(PCH_DPLL_SEL);
		5894	if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
		5895	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
		5896	else
		5897	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
		5898	}
		5899
		5900	pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
		5901
		5902	WARN_ON(!pll->get_hw_state(dev_priv, pll,
		5903	&pipe_config->dpll_hw_state));
		5904
		5905	tmp = pipe_config->dpll_hw_state.dpll;
		5906	pipe_config->pixel_multiplier =
		5907	((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
		5908	>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
		5909	} else {
		5910	pipe_config->pixel_multiplier = 1;
		5911	}
		5912
		5913	intel_get_pipe_timings(crtc, pipe_config);
		5914
		5915	ironlake_get_pfit_config(crtc, pipe_config);
		5916
3746	Serge	5917	return true;
		5918	}
		5919
4104	Serge	5920	static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
		5921	{
		5922	struct drm_device *dev = dev_priv->dev;
		5923	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
		5924	struct intel_crtc *crtc;
		5925	unsigned long irqflags;
		5926	uint32_t val;
		5927
		5928	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		5929	WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
		5930	pipe_name(crtc->pipe));
		5931
		5932	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
		5933	WARN(plls->spll_refcount, "SPLL enabled\n");
		5934	WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
		5935	WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
		5936	WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
		5937	WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
		5938	"CPU PWM1 enabled\n");
		5939	WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
		5940	"CPU PWM2 enabled\n");
		5941	WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
		5942	"PCH PWM1 enabled\n");
		5943	WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
		5944	"Utility pin enabled\n");
		5945	WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
		5946
		5947	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		5948	val = I915_READ(DEIMR);
		5949	WARN((val & ~DE_PCH_EVENT_IVB) != val,
		5950	"Unexpected DEIMR bits enabled: 0x%x\n", val);
		5951	val = I915_READ(SDEIMR);
		5952	WARN((val \| SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
		5953	"Unexpected SDEIMR bits enabled: 0x%x\n", val);
		5954	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
		5955	}
		5956
		5957	/*
		5958	* This function implements pieces of two sequences from BSpec:
		5959	* - Sequence for display software to disable LCPLL
		5960	* - Sequence for display software to allow package C8+
		5961	* The steps implemented here are just the steps that actually touch the LCPLL
		5962	* register. Callers should take care of disabling all the display engine
		5963	* functions, doing the mode unset, fixing interrupts, etc.
		5964	*/
		5965	void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
		5966	bool switch_to_fclk, bool allow_power_down)
		5967	{
		5968	uint32_t val;
		5969
		5970	assert_can_disable_lcpll(dev_priv);
		5971
		5972	val = I915_READ(LCPLL_CTL);
		5973
		5974	if (switch_to_fclk) {
		5975	val \|= LCPLL_CD_SOURCE_FCLK;
		5976	I915_WRITE(LCPLL_CTL, val);
		5977
		5978	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
		5979	LCPLL_CD_SOURCE_FCLK_DONE, 1))
		5980	DRM_ERROR("Switching to FCLK failed\n");
		5981
		5982	val = I915_READ(LCPLL_CTL);
		5983	}
		5984
		5985	val \|= LCPLL_PLL_DISABLE;
		5986	I915_WRITE(LCPLL_CTL, val);
		5987	POSTING_READ(LCPLL_CTL);
		5988
		5989	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
		5990	DRM_ERROR("LCPLL still locked\n");
		5991
		5992	val = I915_READ(D_COMP);
		5993	val \|= D_COMP_COMP_DISABLE;
		5994	I915_WRITE(D_COMP, val);
		5995	POSTING_READ(D_COMP);
		5996	udelay(100);
		5997
		5998	if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
		5999	DRM_ERROR("D_COMP RCOMP still in progress\n");
		6000
		6001	if (allow_power_down) {
		6002	val = I915_READ(LCPLL_CTL);
		6003	val \|= LCPLL_POWER_DOWN_ALLOW;
		6004	I915_WRITE(LCPLL_CTL, val);
		6005	POSTING_READ(LCPLL_CTL);
		6006	}
		6007	}
		6008
		6009	/*
		6010	* Fully restores LCPLL, disallowing power down and switching back to LCPLL
		6011	* source.
		6012	*/
		6013	void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
		6014	{
		6015	uint32_t val;
		6016
		6017	val = I915_READ(LCPLL_CTL);
		6018
		6019	if ((val & (LCPLL_PLL_LOCK \| LCPLL_PLL_DISABLE \| LCPLL_CD_SOURCE_FCLK \|
		6020	LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
		6021	return;
		6022
		6023	/* Make sure we're not on PC8 state before disabling PC8, otherwise
		6024	* we'll hang the machine! */
		6025	dev_priv->uncore.funcs.force_wake_get(dev_priv);
		6026
		6027	if (val & LCPLL_POWER_DOWN_ALLOW) {
		6028	val &= ~LCPLL_POWER_DOWN_ALLOW;
		6029	I915_WRITE(LCPLL_CTL, val);
		6030	POSTING_READ(LCPLL_CTL);
		6031	}
		6032
		6033	val = I915_READ(D_COMP);
		6034	val \|= D_COMP_COMP_FORCE;
		6035	val &= ~D_COMP_COMP_DISABLE;
		6036	I915_WRITE(D_COMP, val);
		6037	POSTING_READ(D_COMP);
		6038
		6039	val = I915_READ(LCPLL_CTL);
		6040	val &= ~LCPLL_PLL_DISABLE;
		6041	I915_WRITE(LCPLL_CTL, val);
		6042
		6043	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
		6044	DRM_ERROR("LCPLL not locked yet\n");
		6045
		6046	if (val & LCPLL_CD_SOURCE_FCLK) {
		6047	val = I915_READ(LCPLL_CTL);
		6048	val &= ~LCPLL_CD_SOURCE_FCLK;
		6049	I915_WRITE(LCPLL_CTL, val);
		6050
		6051	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
		6052	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
		6053	DRM_ERROR("Switching back to LCPLL failed\n");
		6054	}
		6055
		6056	dev_priv->uncore.funcs.force_wake_put(dev_priv);
		6057	}
		6058
		6059	void hsw_enable_pc8_work(struct work_struct *__work)
		6060	{
		6061	struct drm_i915_private *dev_priv =
		6062	container_of(to_delayed_work(__work), struct drm_i915_private,
		6063	pc8.enable_work);
		6064	struct drm_device *dev = dev_priv->dev;
		6065	uint32_t val;
		6066
		6067	if (dev_priv->pc8.enabled)
		6068	return;
		6069
		6070	DRM_DEBUG_KMS("Enabling package C8+\n");
		6071
		6072	dev_priv->pc8.enabled = true;
		6073
		6074	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		6075	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		6076	val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
		6077	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		6078	}
		6079
		6080	lpt_disable_clkout_dp(dev);
		6081	hsw_pc8_disable_interrupts(dev);
		6082	hsw_disable_lcpll(dev_priv, true, true);
		6083	}
		6084
		6085	static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
		6086	{
		6087	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
		6088	WARN(dev_priv->pc8.disable_count < 1,
		6089	"pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
		6090
		6091	dev_priv->pc8.disable_count--;
		6092	if (dev_priv->pc8.disable_count != 0)
		6093	return;
		6094
		6095	schedule_delayed_work(&dev_priv->pc8.enable_work,
		6096	msecs_to_jiffies(i915_pc8_timeout));
		6097	}
		6098
		6099	static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
		6100	{
		6101	struct drm_device *dev = dev_priv->dev;
		6102	uint32_t val;
		6103
		6104	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
		6105	WARN(dev_priv->pc8.disable_count < 0,
		6106	"pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
		6107
		6108	dev_priv->pc8.disable_count++;
		6109	if (dev_priv->pc8.disable_count != 1)
		6110	return;
		6111
		6112	// cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
		6113	if (!dev_priv->pc8.enabled)
		6114	return;
		6115
		6116	DRM_DEBUG_KMS("Disabling package C8+\n");
		6117
		6118	hsw_restore_lcpll(dev_priv);
		6119	hsw_pc8_restore_interrupts(dev);
		6120	lpt_init_pch_refclk(dev);
		6121
		6122	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		6123	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		6124	val \|= PCH_LP_PARTITION_LEVEL_DISABLE;
		6125	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		6126	}
		6127
		6128	intel_prepare_ddi(dev);
		6129	i915_gem_init_swizzling(dev);
		6130	mutex_lock(&dev_priv->rps.hw_lock);
		6131	gen6_update_ring_freq(dev);
		6132	mutex_unlock(&dev_priv->rps.hw_lock);
		6133	dev_priv->pc8.enabled = false;
		6134	}
		6135
		6136	void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
		6137	{
		6138	mutex_lock(&dev_priv->pc8.lock);
		6139	__hsw_enable_package_c8(dev_priv);
		6140	mutex_unlock(&dev_priv->pc8.lock);
		6141	}
		6142
		6143	void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
		6144	{
		6145	mutex_lock(&dev_priv->pc8.lock);
		6146	__hsw_disable_package_c8(dev_priv);
		6147	mutex_unlock(&dev_priv->pc8.lock);
		6148	}
		6149
		6150	static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
		6151	{
		6152	struct drm_device *dev = dev_priv->dev;
		6153	struct intel_crtc *crtc;
		6154	uint32_t val;
		6155
		6156	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		6157	if (crtc->base.enabled)
		6158	return false;
		6159
		6160	/* This case is still possible since we have the i915.disable_power_well
		6161	* parameter and also the KVMr or something else might be requesting the
		6162	* power well. */
		6163	val = I915_READ(HSW_PWR_WELL_DRIVER);
		6164	if (val != 0) {
		6165	DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
		6166	return false;
		6167	}
		6168
		6169	return true;
		6170	}
		6171
		6172	/* Since we're called from modeset_global_resources there's no way to
		6173	* symmetrically increase and decrease the refcount, so we use
		6174	* dev_priv->pc8.requirements_met to track whether we already have the refcount
		6175	* or not.
		6176	*/
		6177	static void hsw_update_package_c8(struct drm_device *dev)
		6178	{
		6179	struct drm_i915_private *dev_priv = dev->dev_private;
		6180	bool allow;
		6181
		6182	if (!i915_enable_pc8)
		6183	return;
		6184
		6185	mutex_lock(&dev_priv->pc8.lock);
		6186
		6187	allow = hsw_can_enable_package_c8(dev_priv);
		6188
		6189	if (allow == dev_priv->pc8.requirements_met)
		6190	goto done;
		6191
		6192	dev_priv->pc8.requirements_met = allow;
		6193
		6194	if (allow)
		6195	__hsw_enable_package_c8(dev_priv);
		6196	else
		6197	__hsw_disable_package_c8(dev_priv);
		6198
		6199	done:
		6200	mutex_unlock(&dev_priv->pc8.lock);
		6201	}
		6202
		6203	static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
		6204	{
		6205	if (!dev_priv->pc8.gpu_idle) {
		6206	dev_priv->pc8.gpu_idle = true;
		6207	hsw_enable_package_c8(dev_priv);
		6208	}
		6209	}
		6210
		6211	static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
		6212	{
		6213	if (dev_priv->pc8.gpu_idle) {
		6214	dev_priv->pc8.gpu_idle = false;
		6215	hsw_disable_package_c8(dev_priv);
		6216	}
		6217	}
		6218
3480	Serge	6219	static void haswell_modeset_global_resources(struct drm_device *dev)
		6220	{
		6221	bool enable = false;
		6222	struct intel_crtc *crtc;
		6223
		6224	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4104	Serge	6225	if (!crtc->base.enabled)
		6226	continue;
3480	Serge	6227
4104	Serge	6228	if (crtc->pipe != PIPE_A \|\| crtc->config.pch_pfit.enabled \|\|
		6229	crtc->config.cpu_transcoder != TRANSCODER_EDP)
3480	Serge	6230	enable = true;
		6231	}
		6232
4104	Serge	6233	intel_set_power_well(dev, enable);
3480	Serge	6234
4104	Serge	6235	hsw_update_package_c8(dev);
3480	Serge	6236	}
		6237
3243	Serge	6238	static int haswell_crtc_mode_set(struct drm_crtc *crtc,
		6239	int x, int y,
		6240	struct drm_framebuffer *fb)
		6241	{
		6242	struct drm_device *dev = crtc->dev;
		6243	struct drm_i915_private *dev_priv = dev->dev_private;
		6244	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6245	int plane = intel_crtc->plane;
		6246	int ret;
		6247
4104	Serge	6248	if (!intel_ddi_pll_mode_set(crtc))
3243	Serge	6249	return -EINVAL;
		6250
3746	Serge	6251	if (intel_crtc->config.has_dp_encoder)
		6252	intel_dp_set_m_n(intel_crtc);
2327	Serge	6253
3243	Serge	6254	intel_crtc->lowfreq_avail = false;
2327	Serge	6255
4104	Serge	6256	intel_set_pipe_timings(intel_crtc);
3243	Serge	6257
4104	Serge	6258	if (intel_crtc->config.has_pch_encoder) {
		6259	intel_cpu_transcoder_set_m_n(intel_crtc,
		6260	&intel_crtc->config.fdi_m_n);
		6261	}
3243	Serge	6262
4104	Serge	6263	haswell_set_pipeconf(crtc);
2327	Serge	6264
3746	Serge	6265	intel_set_pipe_csc(crtc);
3480	Serge	6266
3031	serge	6267	/* Set up the display plane register */
3480	Serge	6268	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE \| DISPPLANE_PIPE_CSC_ENABLE);
2327	Serge	6269	POSTING_READ(DSPCNTR(plane));
		6270
3031	serge	6271	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	6272
		6273	intel_update_watermarks(dev);
		6274
		6275	return ret;
		6276	}
		6277
3746	Serge	6278	static bool haswell_get_pipe_config(struct intel_crtc *crtc,
		6279	struct intel_crtc_config *pipe_config)
		6280	{
		6281	struct drm_device *dev = crtc->base.dev;
		6282	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	6283	enum intel_display_power_domain pfit_domain;
3746	Serge	6284	uint32_t tmp;
		6285
4104	Serge	6286	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		6287	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		6288
		6289	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
		6290	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		6291	enum pipe trans_edp_pipe;
		6292	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		6293	default:
		6294	WARN(1, "unknown pipe linked to edp transcoder\n");
		6295	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		6296	case TRANS_DDI_EDP_INPUT_A_ON:
		6297	trans_edp_pipe = PIPE_A;
		6298	break;
		6299	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		6300	trans_edp_pipe = PIPE_B;
		6301	break;
		6302	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		6303	trans_edp_pipe = PIPE_C;
		6304	break;
		6305	}
		6306
		6307	if (trans_edp_pipe == crtc->pipe)
		6308	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		6309	}
		6310
		6311	if (!intel_display_power_enabled(dev,
		6312	POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
		6313	return false;
		6314
		6315	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
3746	Serge	6316	if (!(tmp & PIPECONF_ENABLE))
		6317	return false;
		6318
		6319	/*
4104	Serge	6320	* Haswell has only FDI/PCH transcoder A. It is which is connected to
3746	Serge	6321	* DDI E. So just check whether this pipe is wired to DDI E and whether
		6322	* the PCH transcoder is on.
		6323	*/
4104	Serge	6324	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3746	Serge	6325	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
4104	Serge	6326	I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
3746	Serge	6327	pipe_config->has_pch_encoder = true;
		6328
4104	Serge	6329	tmp = I915_READ(FDI_RX_CTL(PIPE_A));
		6330	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		6331	FDI_DP_PORT_WIDTH_SHIFT) + 1;
3746	Serge	6332
4104	Serge	6333	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		6334	}
		6335
		6336	intel_get_pipe_timings(crtc, pipe_config);
		6337
		6338	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
		6339	if (intel_display_power_enabled(dev, pfit_domain))
		6340	ironlake_get_pfit_config(crtc, pipe_config);
		6341
		6342	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
		6343	(I915_READ(IPS_CTL) & IPS_ENABLE);
		6344
		6345	pipe_config->pixel_multiplier = 1;
		6346
3746	Serge	6347	return true;
		6348	}
		6349
2330	Serge	6350	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		6351	int x, int y,
3031	serge	6352	struct drm_framebuffer *fb)
2330	Serge	6353	{
		6354	struct drm_device *dev = crtc->dev;
		6355	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	6356	struct intel_encoder *encoder;
2330	Serge	6357	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	6358	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
2330	Serge	6359	int pipe = intel_crtc->pipe;
		6360	int ret;
2327	Serge	6361
3031	serge	6362	drm_vblank_pre_modeset(dev, pipe);
2327	Serge	6363
3746	Serge	6364	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
		6365
3031	serge	6366	drm_vblank_post_modeset(dev, pipe);
2327	Serge	6367
3243	Serge	6368	if (ret != 0)
2330	Serge	6369	return ret;
3243	Serge	6370
		6371	for_each_encoder_on_crtc(dev, crtc, encoder) {
		6372	DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
		6373	encoder->base.base.id,
		6374	drm_get_encoder_name(&encoder->base),
		6375	mode->base.id, mode->name);
3746	Serge	6376	encoder->mode_set(encoder);
3243	Serge	6377	}
		6378
		6379	return 0;
2330	Serge	6380	}
2327	Serge	6381
2342	Serge	6382	static bool intel_eld_uptodate(struct drm_connector *connector,
		6383	int reg_eldv, uint32_t bits_eldv,
		6384	int reg_elda, uint32_t bits_elda,
		6385	int reg_edid)
		6386	{
		6387	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6388	uint8_t *eld = connector->eld;
		6389	uint32_t i;
		6390
		6391	i = I915_READ(reg_eldv);
		6392	i &= bits_eldv;
		6393
		6394	if (!eld[0])
		6395	return !i;
		6396
		6397	if (!i)
		6398	return false;
		6399
		6400	i = I915_READ(reg_elda);
		6401	i &= ~bits_elda;
		6402	I915_WRITE(reg_elda, i);
		6403
		6404	for (i = 0; i < eld[2]; i++)
		6405	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
		6406	return false;
		6407
		6408	return true;
		6409	}
		6410
		6411	static void g4x_write_eld(struct drm_connector *connector,
		6412	struct drm_crtc *crtc)
		6413	{
		6414	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6415	uint8_t *eld = connector->eld;
		6416	uint32_t eldv;
		6417	uint32_t len;
		6418	uint32_t i;
		6419
		6420	i = I915_READ(G4X_AUD_VID_DID);
		6421
		6422	if (i == INTEL_AUDIO_DEVBLC \|\| i == INTEL_AUDIO_DEVCL)
		6423	eldv = G4X_ELDV_DEVCL_DEVBLC;
		6424	else
		6425	eldv = G4X_ELDV_DEVCTG;
		6426
		6427	if (intel_eld_uptodate(connector,
		6428	G4X_AUD_CNTL_ST, eldv,
		6429	G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
		6430	G4X_HDMIW_HDMIEDID))
		6431	return;
		6432
		6433	i = I915_READ(G4X_AUD_CNTL_ST);
		6434	i &= ~(eldv \| G4X_ELD_ADDR);
		6435	len = (i >> 9) & 0x1f; /* ELD buffer size */
		6436	I915_WRITE(G4X_AUD_CNTL_ST, i);
		6437
		6438	if (!eld[0])
		6439	return;
		6440
		6441	len = min_t(uint8_t, eld[2], len);
		6442	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6443	for (i = 0; i < len; i++)
		6444	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
		6445
		6446	i = I915_READ(G4X_AUD_CNTL_ST);
		6447	i \|= eldv;
		6448	I915_WRITE(G4X_AUD_CNTL_ST, i);
		6449	}
		6450
3031	serge	6451	static void haswell_write_eld(struct drm_connector *connector,
		6452	struct drm_crtc *crtc)
		6453	{
		6454	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6455	uint8_t *eld = connector->eld;
		6456	struct drm_device *dev = crtc->dev;
3480	Serge	6457	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	6458	uint32_t eldv;
		6459	uint32_t i;
		6460	int len;
		6461	int pipe = to_intel_crtc(crtc)->pipe;
		6462	int tmp;
		6463
		6464	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
		6465	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
		6466	int aud_config = HSW_AUD_CFG(pipe);
		6467	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
		6468
		6469
		6470	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
		6471
		6472	/* Audio output enable */
		6473	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
		6474	tmp = I915_READ(aud_cntrl_st2);
		6475	tmp \|= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
		6476	I915_WRITE(aud_cntrl_st2, tmp);
		6477
		6478	/* Wait for 1 vertical blank */
		6479	intel_wait_for_vblank(dev, pipe);
		6480
		6481	/* Set ELD valid state */
		6482	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	6483	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
3031	serge	6484	tmp \|= (AUDIO_ELD_VALID_A << (pipe * 4));
		6485	I915_WRITE(aud_cntrl_st2, tmp);
		6486	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	6487	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
3031	serge	6488
		6489	/* Enable HDMI mode */
		6490	tmp = I915_READ(aud_config);
4104	Serge	6491	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
3031	serge	6492	/* clear N_programing_enable and N_value_index */
		6493	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX \| AUD_CONFIG_N_PROG_ENABLE);
		6494	I915_WRITE(aud_config, tmp);
		6495
		6496	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
		6497
		6498	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
3480	Serge	6499	intel_crtc->eld_vld = true;
3031	serge	6500
		6501	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6502	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6503	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
		6504	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6505	} else
		6506	I915_WRITE(aud_config, 0);
		6507
		6508	if (intel_eld_uptodate(connector,
		6509	aud_cntrl_st2, eldv,
		6510	aud_cntl_st, IBX_ELD_ADDRESS,
		6511	hdmiw_hdmiedid))
		6512	return;
		6513
		6514	i = I915_READ(aud_cntrl_st2);
		6515	i &= ~eldv;
		6516	I915_WRITE(aud_cntrl_st2, i);
		6517
		6518	if (!eld[0])
		6519	return;
		6520
		6521	i = I915_READ(aud_cntl_st);
		6522	i &= ~IBX_ELD_ADDRESS;
		6523	I915_WRITE(aud_cntl_st, i);
		6524	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
		6525	DRM_DEBUG_DRIVER("port num:%d\n", i);
		6526
		6527	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6528	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6529	for (i = 0; i < len; i++)
		6530	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6531
		6532	i = I915_READ(aud_cntrl_st2);
		6533	i \|= eldv;
		6534	I915_WRITE(aud_cntrl_st2, i);
		6535
		6536	}
		6537
2342	Serge	6538	static void ironlake_write_eld(struct drm_connector *connector,
		6539	struct drm_crtc *crtc)
		6540	{
		6541	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6542	uint8_t *eld = connector->eld;
		6543	uint32_t eldv;
		6544	uint32_t i;
		6545	int len;
		6546	int hdmiw_hdmiedid;
3031	serge	6547	int aud_config;
2342	Serge	6548	int aud_cntl_st;
		6549	int aud_cntrl_st2;
3031	serge	6550	int pipe = to_intel_crtc(crtc)->pipe;
2342	Serge	6551
		6552	if (HAS_PCH_IBX(connector->dev)) {
3031	serge	6553	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		6554	aud_config = IBX_AUD_CFG(pipe);
		6555	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
2342	Serge	6556	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
		6557	} else {
3031	serge	6558	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		6559	aud_config = CPT_AUD_CFG(pipe);
		6560	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
2342	Serge	6561	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
		6562	}
		6563
3031	serge	6564	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
2342	Serge	6565
		6566	i = I915_READ(aud_cntl_st);
3031	serge	6567	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
2342	Serge	6568	if (!i) {
		6569	DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		6570	/* operate blindly on all ports */
		6571	eldv = IBX_ELD_VALIDB;
		6572	eldv \|= IBX_ELD_VALIDB << 4;
		6573	eldv \|= IBX_ELD_VALIDB << 8;
		6574	} else {
4104	Serge	6575	DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
2342	Serge	6576	eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
		6577	}
		6578
		6579	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6580	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6581	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
3031	serge	6582	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6583	} else
		6584	I915_WRITE(aud_config, 0);
2342	Serge	6585
		6586	if (intel_eld_uptodate(connector,
		6587	aud_cntrl_st2, eldv,
		6588	aud_cntl_st, IBX_ELD_ADDRESS,
		6589	hdmiw_hdmiedid))
		6590	return;
		6591
		6592	i = I915_READ(aud_cntrl_st2);
		6593	i &= ~eldv;
		6594	I915_WRITE(aud_cntrl_st2, i);
		6595
		6596	if (!eld[0])
		6597	return;
		6598
		6599	i = I915_READ(aud_cntl_st);
		6600	i &= ~IBX_ELD_ADDRESS;
		6601	I915_WRITE(aud_cntl_st, i);
		6602
		6603	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6604	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6605	for (i = 0; i < len; i++)
		6606	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6607
		6608	i = I915_READ(aud_cntrl_st2);
		6609	i \|= eldv;
		6610	I915_WRITE(aud_cntrl_st2, i);
		6611	}
		6612
		6613	void intel_write_eld(struct drm_encoder *encoder,
		6614	struct drm_display_mode *mode)
		6615	{
		6616	struct drm_crtc *crtc = encoder->crtc;
		6617	struct drm_connector *connector;
		6618	struct drm_device *dev = encoder->dev;
		6619	struct drm_i915_private *dev_priv = dev->dev_private;
		6620
		6621	connector = drm_select_eld(encoder, mode);
		6622	if (!connector)
		6623	return;
		6624
		6625	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		6626	connector->base.id,
		6627	drm_get_connector_name(connector),
		6628	connector->encoder->base.id,
		6629	drm_get_encoder_name(connector->encoder));
		6630
		6631	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
		6632
		6633	if (dev_priv->display.write_eld)
		6634	dev_priv->display.write_eld(connector, crtc);
		6635	}
		6636
2327	Serge	6637	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		6638	void intel_crtc_load_lut(struct drm_crtc *crtc)
		6639	{
		6640	struct drm_device *dev = crtc->dev;
		6641	struct drm_i915_private *dev_priv = dev->dev_private;
		6642	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	6643	enum pipe pipe = intel_crtc->pipe;
		6644	int palreg = PALETTE(pipe);
2327	Serge	6645	int i;
4104	Serge	6646	bool reenable_ips = false;
2327	Serge	6647
		6648	/* The clocks have to be on to load the palette. */
3031	serge	6649	if (!crtc->enabled \|\| !intel_crtc->active)
2327	Serge	6650	return;
		6651
4104	Serge	6652	if (!HAS_PCH_SPLIT(dev_priv->dev))
		6653	assert_pll_enabled(dev_priv, pipe);
		6654
2327	Serge	6655	/* use legacy palette for Ironlake */
		6656	if (HAS_PCH_SPLIT(dev))
4104	Serge	6657	palreg = LGC_PALETTE(pipe);
2327	Serge	6658
4104	Serge	6659	/* Workaround : Do not read or write the pipe palette/gamma data while
		6660	* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
		6661	*/
		6662	if (intel_crtc->config.ips_enabled &&
		6663	((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
		6664	GAMMA_MODE_MODE_SPLIT)) {
		6665	hsw_disable_ips(intel_crtc);
		6666	reenable_ips = true;
		6667	}
		6668
2327	Serge	6669	for (i = 0; i < 256; i++) {
		6670	I915_WRITE(palreg + 4 * i,
		6671	(intel_crtc->lut_r[i] << 16) \|
		6672	(intel_crtc->lut_g[i] << 8) \|
		6673	intel_crtc->lut_b[i]);
		6674	}
4104	Serge	6675
		6676	if (reenable_ips)
		6677	hsw_enable_ips(intel_crtc);
2327	Serge	6678	}
		6679
3031	serge	6680	#if 0
		6681	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
		6682	{
		6683	struct drm_device *dev = crtc->dev;
		6684	struct drm_i915_private *dev_priv = dev->dev_private;
		6685	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6686	bool visible = base != 0;
		6687	u32 cntl;
2327	Serge	6688
3031	serge	6689	if (intel_crtc->cursor_visible == visible)
		6690	return;
2327	Serge	6691
3031	serge	6692	cntl = I915_READ(_CURACNTR);
		6693	if (visible) {
		6694	/* On these chipsets we can only modify the base whilst
		6695	* the cursor is disabled.
		6696	*/
		6697	I915_WRITE(_CURABASE, base);
2327	Serge	6698
3031	serge	6699	cntl &= ~(CURSOR_FORMAT_MASK);
		6700	/* XXX width must be 64, stride 256 => 0x00 << 28 */
		6701	cntl \|= CURSOR_ENABLE \|
		6702	CURSOR_GAMMA_ENABLE \|
		6703	CURSOR_FORMAT_ARGB;
		6704	} else
		6705	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);
		6706	I915_WRITE(_CURACNTR, cntl);
2327	Serge	6707
3031	serge	6708	intel_crtc->cursor_visible = visible;
		6709	}
2327	Serge	6710
3031	serge	6711	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
		6712	{
		6713	struct drm_device *dev = crtc->dev;
		6714	struct drm_i915_private *dev_priv = dev->dev_private;
		6715	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6716	int pipe = intel_crtc->pipe;
		6717	bool visible = base != 0;
2327	Serge	6718
3031	serge	6719	if (intel_crtc->cursor_visible != visible) {
		6720	uint32_t cntl = I915_READ(CURCNTR(pipe));
		6721	if (base) {
		6722	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);
		6723	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6724	cntl \|= pipe << 28; /* Connect to correct pipe */
		6725	} else {
		6726	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6727	cntl \|= CURSOR_MODE_DISABLE;
		6728	}
		6729	I915_WRITE(CURCNTR(pipe), cntl);
2327	Serge	6730
3031	serge	6731	intel_crtc->cursor_visible = visible;
		6732	}
		6733	/* and commit changes on next vblank */
		6734	I915_WRITE(CURBASE(pipe), base);
		6735	}
2327	Serge	6736
3031	serge	6737	static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
		6738	{
		6739	struct drm_device *dev = crtc->dev;
		6740	struct drm_i915_private *dev_priv = dev->dev_private;
		6741	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6742	int pipe = intel_crtc->pipe;
		6743	bool visible = base != 0;
2327	Serge	6744
3031	serge	6745	if (intel_crtc->cursor_visible != visible) {
		6746	uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		6747	if (base) {
		6748	cntl &= ~CURSOR_MODE;
		6749	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6750	} else {
		6751	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6752	cntl \|= CURSOR_MODE_DISABLE;
		6753	}
4104	Serge	6754	if (IS_HASWELL(dev)) {
3480	Serge	6755	cntl \|= CURSOR_PIPE_CSC_ENABLE;
4104	Serge	6756	cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
		6757	}
3031	serge	6758	I915_WRITE(CURCNTR_IVB(pipe), cntl);
2327	Serge	6759
3031	serge	6760	intel_crtc->cursor_visible = visible;
		6761	}
		6762	/* and commit changes on next vblank */
		6763	I915_WRITE(CURBASE_IVB(pipe), base);
		6764	}
2327	Serge	6765
3031	serge	6766	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
		6767	static void intel_crtc_update_cursor(struct drm_crtc *crtc,
		6768	bool on)
		6769	{
		6770	struct drm_device *dev = crtc->dev;
		6771	struct drm_i915_private *dev_priv = dev->dev_private;
		6772	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6773	int pipe = intel_crtc->pipe;
		6774	int x = intel_crtc->cursor_x;
		6775	int y = intel_crtc->cursor_y;
		6776	u32 base, pos;
		6777	bool visible;
2327	Serge	6778
3031	serge	6779	pos = 0;
2327	Serge	6780
3031	serge	6781	if (on && crtc->enabled && crtc->fb) {
		6782	base = intel_crtc->cursor_addr;
		6783	if (x > (int) crtc->fb->width)
		6784	base = 0;
2327	Serge	6785
3031	serge	6786	if (y > (int) crtc->fb->height)
		6787	base = 0;
		6788	} else
		6789	base = 0;
2327	Serge	6790
3031	serge	6791	if (x < 0) {
		6792	if (x + intel_crtc->cursor_width < 0)
		6793	base = 0;
2327	Serge	6794
3031	serge	6795	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		6796	x = -x;
		6797	}
		6798	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	6799
3031	serge	6800	if (y < 0) {
		6801	if (y + intel_crtc->cursor_height < 0)
		6802	base = 0;
2327	Serge	6803
3031	serge	6804	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		6805	y = -y;
		6806	}
		6807	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	6808
3031	serge	6809	visible = base != 0;
		6810	if (!visible && !intel_crtc->cursor_visible)
		6811	return;
2327	Serge	6812
3031	serge	6813	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev)) {
		6814	I915_WRITE(CURPOS_IVB(pipe), pos);
		6815	ivb_update_cursor(crtc, base);
		6816	} else {
		6817	I915_WRITE(CURPOS(pipe), pos);
		6818	if (IS_845G(dev) \|\| IS_I865G(dev))
		6819	i845_update_cursor(crtc, base);
		6820	else
		6821	i9xx_update_cursor(crtc, base);
		6822	}
		6823	}
2327	Serge	6824
3031	serge	6825	static int intel_crtc_cursor_set(struct drm_crtc *crtc,
		6826	struct drm_file *file,
		6827	uint32_t handle,
		6828	uint32_t width, uint32_t height)
		6829	{
		6830	struct drm_device *dev = crtc->dev;
		6831	struct drm_i915_private *dev_priv = dev->dev_private;
		6832	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6833	struct drm_i915_gem_object *obj;
		6834	uint32_t addr;
		6835	int ret;
2327	Serge	6836
3031	serge	6837	/* if we want to turn off the cursor ignore width and height */
		6838	if (!handle) {
		6839	DRM_DEBUG_KMS("cursor off\n");
		6840	addr = 0;
		6841	obj = NULL;
		6842	mutex_lock(&dev->struct_mutex);
		6843	goto finish;
		6844	}
2327	Serge	6845
3031	serge	6846	/* Currently we only support 64x64 cursors */
		6847	if (width != 64 \|\| height != 64) {
		6848	DRM_ERROR("we currently only support 64x64 cursors\n");
		6849	return -EINVAL;
		6850	}
2327	Serge	6851
3031	serge	6852	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
		6853	if (&obj->base == NULL)
		6854	return -ENOENT;
2327	Serge	6855
3031	serge	6856	if (obj->base.size < width * height * 4) {
		6857	DRM_ERROR("buffer is to small\n");
		6858	ret = -ENOMEM;
		6859	goto fail;
		6860	}
2327	Serge	6861
3031	serge	6862	/* we only need to pin inside GTT if cursor is non-phy */
		6863	mutex_lock(&dev->struct_mutex);
		6864	if (!dev_priv->info->cursor_needs_physical) {
3746	Serge	6865	unsigned alignment;
		6866
3031	serge	6867	if (obj->tiling_mode) {
		6868	DRM_ERROR("cursor cannot be tiled\n");
		6869	ret = -EINVAL;
		6870	goto fail_locked;
		6871	}
2327	Serge	6872
3746	Serge	6873	/* Note that the w/a also requires 2 PTE of padding following
		6874	* the bo. We currently fill all unused PTE with the shadow
		6875	* page and so we should always have valid PTE following the
		6876	* cursor preventing the VT-d warning.
		6877	*/
		6878	alignment = 0;
		6879	if (need_vtd_wa(dev))
		6880	alignment = 64*1024;
		6881
		6882	ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
3031	serge	6883	if (ret) {
		6884	DRM_ERROR("failed to move cursor bo into the GTT\n");
		6885	goto fail_locked;
		6886	}
2327	Serge	6887
3031	serge	6888	ret = i915_gem_object_put_fence(obj);
		6889	if (ret) {
		6890	DRM_ERROR("failed to release fence for cursor");
		6891	goto fail_unpin;
		6892	}
2327	Serge	6893
4104	Serge	6894	addr = i915_gem_obj_ggtt_offset(obj);
3031	serge	6895	} else {
		6896	int align = IS_I830(dev) ? 16 * 1024 : 256;
		6897	ret = i915_gem_attach_phys_object(dev, obj,
		6898	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
		6899	align);
		6900	if (ret) {
		6901	DRM_ERROR("failed to attach phys object\n");
		6902	goto fail_locked;
		6903	}
		6904	addr = obj->phys_obj->handle->busaddr;
		6905	}
2327	Serge	6906
3031	serge	6907	if (IS_GEN2(dev))
		6908	I915_WRITE(CURSIZE, (height << 12) \| width);
2327	Serge	6909
3031	serge	6910	finish:
		6911	if (intel_crtc->cursor_bo) {
		6912	if (dev_priv->info->cursor_needs_physical) {
		6913	if (intel_crtc->cursor_bo != obj)
		6914	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		6915	} else
4104	Serge	6916	i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
3031	serge	6917	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
		6918	}
2327	Serge	6919
3031	serge	6920	mutex_unlock(&dev->struct_mutex);
2327	Serge	6921
3031	serge	6922	intel_crtc->cursor_addr = addr;
		6923	intel_crtc->cursor_bo = obj;
		6924	intel_crtc->cursor_width = width;
		6925	intel_crtc->cursor_height = height;
2327	Serge	6926
4104	Serge	6927	if (intel_crtc->active)
		6928	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
2327	Serge	6929
3031	serge	6930	return 0;
		6931	fail_unpin:
4104	Serge	6932	i915_gem_object_unpin_from_display_plane(obj);
3031	serge	6933	fail_locked:
		6934	mutex_unlock(&dev->struct_mutex);
		6935	fail:
		6936	drm_gem_object_unreference_unlocked(&obj->base);
		6937	return ret;
		6938	}
2327	Serge	6939
3031	serge	6940	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
		6941	{
		6942	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6943
		6944	intel_crtc->cursor_x = x;
		6945	intel_crtc->cursor_y = y;
		6946
4104	Serge	6947	if (intel_crtc->active)
		6948	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3031	serge	6949
		6950	return 0;
		6951	}
		6952	#endif
		6953
2332	Serge	6954	/** Sets the color ramps on behalf of RandR */
		6955	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		6956	u16 blue, int regno)
		6957	{
		6958	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6959
2332	Serge	6960	intel_crtc->lut_r[regno] = red >> 8;
		6961	intel_crtc->lut_g[regno] = green >> 8;
		6962	intel_crtc->lut_b[regno] = blue >> 8;
		6963	}
2327	Serge	6964
2332	Serge	6965	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		6966	u16 *blue, int regno)
		6967	{
		6968	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6969
2332	Serge	6970	*red = intel_crtc->lut_r[regno] << 8;
		6971	*green = intel_crtc->lut_g[regno] << 8;
		6972	*blue = intel_crtc->lut_b[regno] << 8;
		6973	}
2327	Serge	6974
2330	Serge	6975	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		6976	u16 *blue, uint32_t start, uint32_t size)
		6977	{
		6978	int end = (start + size > 256) ? 256 : start + size, i;
		6979	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6980
2330	Serge	6981	for (i = start; i < end; i++) {
		6982	intel_crtc->lut_r[i] = red[i] >> 8;
		6983	intel_crtc->lut_g[i] = green[i] >> 8;
		6984	intel_crtc->lut_b[i] = blue[i] >> 8;
		6985	}
2327	Serge	6986
2330	Serge	6987	intel_crtc_load_lut(crtc);
		6988	}
2327	Serge	6989
2330	Serge	6990	/* VESA 640x480x72Hz mode to set on the pipe */
		6991	static struct drm_display_mode load_detect_mode = {
		6992	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		6993	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		6994	};
2327	Serge	6995
3031	serge	6996	static struct drm_framebuffer *
		6997	intel_framebuffer_create(struct drm_device *dev,
		6998	struct drm_mode_fb_cmd2 *mode_cmd,
		6999	struct drm_i915_gem_object *obj)
		7000	{
		7001	struct intel_framebuffer *intel_fb;
		7002	int ret;
2327	Serge	7003
3031	serge	7004	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		7005	if (!intel_fb) {
		7006	drm_gem_object_unreference_unlocked(&obj->base);
		7007	return ERR_PTR(-ENOMEM);
		7008	}
2327	Serge	7009
3031	serge	7010	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
		7011	if (ret) {
		7012	drm_gem_object_unreference_unlocked(&obj->base);
		7013	kfree(intel_fb);
		7014	return ERR_PTR(ret);
		7015	}
2327	Serge	7016
3031	serge	7017	return &intel_fb->base;
		7018	}
2327	Serge	7019
2330	Serge	7020	static u32
		7021	intel_framebuffer_pitch_for_width(int width, int bpp)
		7022	{
		7023	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		7024	return ALIGN(pitch, 64);
		7025	}
2327	Serge	7026
2330	Serge	7027	static u32
		7028	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		7029	{
		7030	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		7031	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		7032	}
2327	Serge	7033
2330	Serge	7034	static struct drm_framebuffer *
		7035	intel_framebuffer_create_for_mode(struct drm_device *dev,
		7036	struct drm_display_mode *mode,
		7037	int depth, int bpp)
		7038	{
		7039	struct drm_i915_gem_object *obj;
3243	Serge	7040	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327	Serge	7041
4104	Serge	7042	return NULL;
2330	Serge	7043	}
2327	Serge	7044
2330	Serge	7045	static struct drm_framebuffer *
		7046	mode_fits_in_fbdev(struct drm_device *dev,
		7047	struct drm_display_mode *mode)
		7048	{
		7049	struct drm_i915_private *dev_priv = dev->dev_private;
		7050	struct drm_i915_gem_object *obj;
		7051	struct drm_framebuffer *fb;
2327	Serge	7052
2330	Serge	7053	// if (dev_priv->fbdev == NULL)
		7054	// return NULL;
2327	Serge	7055
2330	Serge	7056	// obj = dev_priv->fbdev->ifb.obj;
		7057	// if (obj == NULL)
		7058	return NULL;
2327	Serge	7059
2330	Serge	7060	// if (obj->base.size < mode->vdisplay * fb->pitch)
3031	serge	7061	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		7062	fb->bits_per_pixel))
2330	Serge	7063	// return NULL;
2327	Serge	7064
3031	serge	7065	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		7066	return NULL;
		7067
2330	Serge	7068	// return fb;
		7069	}
2327	Serge	7070
3031	serge	7071	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	7072	struct drm_display_mode *mode,
		7073	struct intel_load_detect_pipe *old)
		7074	{
		7075	struct intel_crtc *intel_crtc;
3031	serge	7076	struct intel_encoder *intel_encoder =
		7077	intel_attached_encoder(connector);
2330	Serge	7078	struct drm_crtc *possible_crtc;
		7079	struct drm_encoder *encoder = &intel_encoder->base;
		7080	struct drm_crtc *crtc = NULL;
		7081	struct drm_device *dev = encoder->dev;
3031	serge	7082	struct drm_framebuffer *fb;
2330	Serge	7083	int i = -1;
2327	Serge	7084
2330	Serge	7085	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		7086	connector->base.id, drm_get_connector_name(connector),
		7087	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	7088
2330	Serge	7089	/*
		7090	* Algorithm gets a little messy:
		7091	*
		7092	* - if the connector already has an assigned crtc, use it (but make
		7093	* sure it's on first)
		7094	*
		7095	* - try to find the first unused crtc that can drive this connector,
		7096	* and use that if we find one
		7097	*/
2327	Serge	7098
2330	Serge	7099	/* See if we already have a CRTC for this connector */
		7100	if (encoder->crtc) {
		7101	crtc = encoder->crtc;
2327	Serge	7102
3480	Serge	7103	mutex_lock(&crtc->mutex);
		7104
3031	serge	7105	old->dpms_mode = connector->dpms;
2330	Serge	7106	old->load_detect_temp = false;
2327	Serge	7107
2330	Serge	7108	/* Make sure the crtc and connector are running */
3031	serge	7109	if (connector->dpms != DRM_MODE_DPMS_ON)
		7110	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	7111
2330	Serge	7112	return true;
		7113	}
2327	Serge	7114
2330	Serge	7115	/* Find an unused one (if possible) */
		7116	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		7117	i++;
		7118	if (!(encoder->possible_crtcs & (1 << i)))
		7119	continue;
		7120	if (!possible_crtc->enabled) {
		7121	crtc = possible_crtc;
		7122	break;
		7123	}
		7124	}
2327	Serge	7125
2330	Serge	7126	/*
		7127	* If we didn't find an unused CRTC, don't use any.
		7128	*/
		7129	if (!crtc) {
		7130	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		7131	return false;
		7132	}
2327	Serge	7133
3480	Serge	7134	mutex_lock(&crtc->mutex);
3031	serge	7135	intel_encoder->new_crtc = to_intel_crtc(crtc);
		7136	to_intel_connector(connector)->new_encoder = intel_encoder;
2327	Serge	7137
2330	Serge	7138	intel_crtc = to_intel_crtc(crtc);
3031	serge	7139	old->dpms_mode = connector->dpms;
2330	Serge	7140	old->load_detect_temp = true;
		7141	old->release_fb = NULL;
2327	Serge	7142
2330	Serge	7143	if (!mode)
		7144	mode = &load_detect_mode;
2327	Serge	7145
2330	Serge	7146	/* We need a framebuffer large enough to accommodate all accesses
		7147	* that the plane may generate whilst we perform load detection.
		7148	* We can not rely on the fbcon either being present (we get called
		7149	* during its initialisation to detect all boot displays, or it may
		7150	* not even exist) or that it is large enough to satisfy the
		7151	* requested mode.
		7152	*/
3031	serge	7153	fb = mode_fits_in_fbdev(dev, mode);
		7154	if (fb == NULL) {
2330	Serge	7155	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	7156	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		7157	old->release_fb = fb;
2330	Serge	7158	} else
		7159	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	7160	if (IS_ERR(fb)) {
2330	Serge	7161	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
3480	Serge	7162	mutex_unlock(&crtc->mutex);
3243	Serge	7163	return false;
2330	Serge	7164	}
2327	Serge	7165
3480	Serge	7166	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
2330	Serge	7167	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		7168	if (old->release_fb)
		7169	old->release_fb->funcs->destroy(old->release_fb);
3480	Serge	7170	mutex_unlock(&crtc->mutex);
3243	Serge	7171	return false;
2330	Serge	7172	}
2327	Serge	7173
2330	Serge	7174	/* let the connector get through one full cycle before testing */
		7175	intel_wait_for_vblank(dev, intel_crtc->pipe);
		7176	return true;
		7177	}
2327	Serge	7178
3031	serge	7179	void intel_release_load_detect_pipe(struct drm_connector *connector,
2330	Serge	7180	struct intel_load_detect_pipe *old)
		7181	{
3031	serge	7182	struct intel_encoder *intel_encoder =
		7183	intel_attached_encoder(connector);
2330	Serge	7184	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	7185	struct drm_crtc *crtc = encoder->crtc;
2327	Serge	7186
2330	Serge	7187	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		7188	connector->base.id, drm_get_connector_name(connector),
		7189	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	7190
2330	Serge	7191	if (old->load_detect_temp) {
3031	serge	7192	to_intel_connector(connector)->new_encoder = NULL;
		7193	intel_encoder->new_crtc = NULL;
		7194	intel_set_mode(crtc, NULL, 0, 0, NULL);
		7195
3480	Serge	7196	if (old->release_fb) {
		7197	drm_framebuffer_unregister_private(old->release_fb);
		7198	drm_framebuffer_unreference(old->release_fb);
		7199	}
2327	Serge	7200
3480	Serge	7201	mutex_unlock(&crtc->mutex);
2330	Serge	7202	return;
		7203	}
2327	Serge	7204
2330	Serge	7205	/* Switch crtc and encoder back off if necessary */
3031	serge	7206	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		7207	connector->funcs->dpms(connector, old->dpms_mode);
3480	Serge	7208
		7209	mutex_unlock(&crtc->mutex);
2330	Serge	7210	}
2327	Serge	7211
2330	Serge	7212	/* Returns the clock of the currently programmed mode of the given pipe. */
4104	Serge	7213	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		7214	struct intel_crtc_config *pipe_config)
2330	Serge	7215	{
4104	Serge	7216	struct drm_device *dev = crtc->base.dev;
2330	Serge	7217	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	7218	int pipe = pipe_config->cpu_transcoder;
2330	Serge	7219	u32 dpll = I915_READ(DPLL(pipe));
		7220	u32 fp;
		7221	intel_clock_t clock;
2327	Serge	7222
2330	Serge	7223	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		7224	fp = I915_READ(FP0(pipe));
		7225	else
		7226	fp = I915_READ(FP1(pipe));
2327	Serge	7227
2330	Serge	7228	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		7229	if (IS_PINEVIEW(dev)) {
		7230	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		7231	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		7232	} else {
		7233	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		7234	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		7235	}
2327	Serge	7236
2330	Serge	7237	if (!IS_GEN2(dev)) {
		7238	if (IS_PINEVIEW(dev))
		7239	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		7240	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		7241	else
		7242	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		7243	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	7244
2330	Serge	7245	switch (dpll & DPLL_MODE_MASK) {
		7246	case DPLLB_MODE_DAC_SERIAL:
		7247	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		7248	5 : 10;
		7249	break;
		7250	case DPLLB_MODE_LVDS:
		7251	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		7252	7 : 14;
		7253	break;
		7254	default:
		7255	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		7256	"mode\n", (int)(dpll & DPLL_MODE_MASK));
4104	Serge	7257	pipe_config->adjusted_mode.clock = 0;
		7258	return;
2330	Serge	7259	}
2327	Serge	7260
4104	Serge	7261	if (IS_PINEVIEW(dev))
		7262	pineview_clock(96000, &clock);
		7263	else
		7264	i9xx_clock(96000, &clock);
2330	Serge	7265	} else {
		7266	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	7267
2330	Serge	7268	if (is_lvds) {
		7269	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		7270	DPLL_FPA01_P1_POST_DIV_SHIFT);
		7271	clock.p2 = 14;
2327	Serge	7272
2330	Serge	7273	if ((dpll & PLL_REF_INPUT_MASK) ==
		7274	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		7275	/* XXX: might not be 66MHz */
4104	Serge	7276	i9xx_clock(66000, &clock);
2330	Serge	7277	} else
4104	Serge	7278	i9xx_clock(48000, &clock);
2330	Serge	7279	} else {
		7280	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		7281	clock.p1 = 2;
		7282	else {
		7283	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		7284	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		7285	}
		7286	if (dpll & PLL_P2_DIVIDE_BY_4)
		7287	clock.p2 = 4;
		7288	else
		7289	clock.p2 = 2;
2327	Serge	7290
4104	Serge	7291	i9xx_clock(48000, &clock);
2330	Serge	7292	}
		7293	}
2327	Serge	7294
4104	Serge	7295	pipe_config->adjusted_mode.clock = clock.dot;
		7296	}
		7297
		7298	static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
		7299	struct intel_crtc_config *pipe_config)
		7300	{
		7301	struct drm_device *dev = crtc->base.dev;
		7302	struct drm_i915_private *dev_priv = dev->dev_private;
		7303	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		7304	int link_freq, repeat;
		7305	u64 clock;
		7306	u32 link_m, link_n;
		7307
		7308	repeat = pipe_config->pixel_multiplier;
		7309
		7310	/*
		7311	* The calculation for the data clock is:
		7312	* pixel_clock = ((m/n)(link_clock nr_lanes * repeat))/bpp
		7313	* But we want to avoid losing precison if possible, so:
		7314	* pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
		7315	*
		7316	* and the link clock is simpler:
		7317	* link_clock = (m * link_clock * repeat) / n
2330	Serge	7318	*/
2327	Serge	7319
4104	Serge	7320	/*
		7321	* We need to get the FDI or DP link clock here to derive
		7322	* the M/N dividers.
		7323	*
		7324	* For FDI, we read it from the BIOS or use a fixed 2.7GHz.
		7325	* For DP, it's either 1.62GHz or 2.7GHz.
		7326	* We do our calculations in 10*MHz since we don't need much precison.
		7327	*/
		7328	if (pipe_config->has_pch_encoder)
		7329	link_freq = intel_fdi_link_freq(dev) * 10000;
		7330	else
		7331	link_freq = pipe_config->port_clock;
		7332
		7333	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
		7334	link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
		7335
		7336	if (!link_m \|\| !link_n)
		7337	return;
		7338
		7339	clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
		7340	do_div(clock, link_n);
		7341
		7342	pipe_config->adjusted_mode.clock = clock;
2330	Serge	7343	}
2327	Serge	7344
2330	Serge	7345	/** Returns the currently programmed mode of the given pipe. */
		7346	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		7347	struct drm_crtc *crtc)
		7348	{
		7349	struct drm_i915_private *dev_priv = dev->dev_private;
		7350	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	7351	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
2330	Serge	7352	struct drm_display_mode *mode;
4104	Serge	7353	struct intel_crtc_config pipe_config;
3243	Serge	7354	int htot = I915_READ(HTOTAL(cpu_transcoder));
		7355	int hsync = I915_READ(HSYNC(cpu_transcoder));
		7356	int vtot = I915_READ(VTOTAL(cpu_transcoder));
		7357	int vsync = I915_READ(VSYNC(cpu_transcoder));
2327	Serge	7358
2330	Serge	7359	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		7360	if (!mode)
		7361	return NULL;
		7362
4104	Serge	7363	/*
		7364	* Construct a pipe_config sufficient for getting the clock info
		7365	* back out of crtc_clock_get.
		7366	*
		7367	* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
		7368	* to use a real value here instead.
		7369	*/
		7370	pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
		7371	pipe_config.pixel_multiplier = 1;
		7372	i9xx_crtc_clock_get(intel_crtc, &pipe_config);
		7373
		7374	mode->clock = pipe_config.adjusted_mode.clock;
2330	Serge	7375	mode->hdisplay = (htot & 0xffff) + 1;
		7376	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		7377	mode->hsync_start = (hsync & 0xffff) + 1;
		7378	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		7379	mode->vdisplay = (vtot & 0xffff) + 1;
		7380	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		7381	mode->vsync_start = (vsync & 0xffff) + 1;
		7382	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		7383
		7384	drm_mode_set_name(mode);
		7385
		7386	return mode;
		7387	}
		7388
2327	Serge	7389	static void intel_increase_pllclock(struct drm_crtc *crtc)
		7390	{
		7391	struct drm_device *dev = crtc->dev;
		7392	drm_i915_private_t *dev_priv = dev->dev_private;
		7393	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7394	int pipe = intel_crtc->pipe;
		7395	int dpll_reg = DPLL(pipe);
		7396	int dpll;
		7397
		7398	if (HAS_PCH_SPLIT(dev))
		7399	return;
		7400
		7401	if (!dev_priv->lvds_downclock_avail)
		7402	return;
		7403
		7404	dpll = I915_READ(dpll_reg);
		7405	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		7406	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		7407
3031	serge	7408	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	7409
		7410	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		7411	I915_WRITE(dpll_reg, dpll);
		7412	intel_wait_for_vblank(dev, pipe);
		7413
		7414	dpll = I915_READ(dpll_reg);
		7415	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		7416	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		7417	}
		7418	}
		7419
3031	serge	7420	static void intel_decrease_pllclock(struct drm_crtc *crtc)
		7421	{
		7422	struct drm_device *dev = crtc->dev;
		7423	drm_i915_private_t *dev_priv = dev->dev_private;
		7424	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7425
3031	serge	7426	if (HAS_PCH_SPLIT(dev))
		7427	return;
2327	Serge	7428
3031	serge	7429	if (!dev_priv->lvds_downclock_avail)
		7430	return;
2327	Serge	7431
3031	serge	7432	/*
		7433	* Since this is called by a timer, we should never get here in
		7434	* the manual case.
		7435	*/
		7436	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		7437	int pipe = intel_crtc->pipe;
		7438	int dpll_reg = DPLL(pipe);
		7439	int dpll;
2327	Serge	7440
3031	serge	7441	DRM_DEBUG_DRIVER("downclocking LVDS\n");
2327	Serge	7442
3031	serge	7443	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	7444
3031	serge	7445	dpll = I915_READ(dpll_reg);
		7446	dpll \|= DISPLAY_RATE_SELECT_FPA1;
		7447	I915_WRITE(dpll_reg, dpll);
		7448	intel_wait_for_vblank(dev, pipe);
		7449	dpll = I915_READ(dpll_reg);
		7450	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
		7451	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
		7452	}
2327	Serge	7453
3031	serge	7454	}
2327	Serge	7455
3031	serge	7456	void intel_mark_busy(struct drm_device *dev)
		7457	{
4104	Serge	7458	struct drm_i915_private *dev_priv = dev->dev_private;
		7459
		7460	hsw_package_c8_gpu_busy(dev_priv);
		7461	i915_update_gfx_val(dev_priv);
3031	serge	7462	}
2327	Serge	7463
3031	serge	7464	void intel_mark_idle(struct drm_device *dev)
		7465	{
4104	Serge	7466	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	7467	struct drm_crtc *crtc;
2327	Serge	7468
4104	Serge	7469	hsw_package_c8_gpu_idle(dev_priv);
		7470
3031	serge	7471	if (!i915_powersave)
		7472	return;
2327	Serge	7473
3031	serge	7474	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		7475	if (!crtc->fb)
		7476	continue;
2327	Serge	7477
3480	Serge	7478	intel_decrease_pllclock(crtc);
3031	serge	7479	}
		7480	}
2327	Serge	7481
4104	Serge	7482	void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
		7483	struct intel_ring_buffer *ring)
3031	serge	7484	{
		7485	struct drm_device *dev = obj->base.dev;
		7486	struct drm_crtc *crtc;
2327	Serge	7487
3031	serge	7488	if (!i915_powersave)
		7489	return;
2327	Serge	7490
3031	serge	7491	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		7492	if (!crtc->fb)
		7493	continue;
2327	Serge	7494
4104	Serge	7495	if (to_intel_framebuffer(crtc->fb)->obj != obj)
		7496	continue;
		7497
3480	Serge	7498	intel_increase_pllclock(crtc);
4104	Serge	7499	if (ring && intel_fbc_enabled(dev))
		7500	ring->fbc_dirty = true;
3031	serge	7501	}
		7502	}
2327	Serge	7503
2330	Serge	7504	static void intel_crtc_destroy(struct drm_crtc *crtc)
		7505	{
		7506	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7507	struct drm_device *dev = crtc->dev;
		7508	struct intel_unpin_work *work;
		7509	unsigned long flags;
2327	Serge	7510
2330	Serge	7511	spin_lock_irqsave(&dev->event_lock, flags);
		7512	work = intel_crtc->unpin_work;
		7513	intel_crtc->unpin_work = NULL;
		7514	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7515
2330	Serge	7516	if (work) {
		7517	// cancel_work_sync(&work->work);
		7518	kfree(work);
		7519	}
2327	Serge	7520
2330	Serge	7521	drm_crtc_cleanup(crtc);
2327	Serge	7522
2330	Serge	7523	kfree(intel_crtc);
		7524	}
2327	Serge	7525
3031	serge	7526	#if 0
		7527	static void intel_unpin_work_fn(struct work_struct *__work)
		7528	{
		7529	struct intel_unpin_work *work =
		7530	container_of(__work, struct intel_unpin_work, work);
3243	Serge	7531	struct drm_device *dev = work->crtc->dev;
2327	Serge	7532
3243	Serge	7533	mutex_lock(&dev->struct_mutex);
3031	serge	7534	intel_unpin_fb_obj(work->old_fb_obj);
		7535	drm_gem_object_unreference(&work->pending_flip_obj->base);
		7536	drm_gem_object_unreference(&work->old_fb_obj->base);
2327	Serge	7537
3243	Serge	7538	intel_update_fbc(dev);
		7539	mutex_unlock(&dev->struct_mutex);
		7540
		7541	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
		7542	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
		7543
3031	serge	7544	kfree(work);
		7545	}
2327	Serge	7546
3031	serge	7547	static void do_intel_finish_page_flip(struct drm_device *dev,
		7548	struct drm_crtc *crtc)
		7549	{
		7550	drm_i915_private_t *dev_priv = dev->dev_private;
		7551	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7552	struct intel_unpin_work *work;
		7553	unsigned long flags;
2327	Serge	7554
3031	serge	7555	/* Ignore early vblank irqs */
		7556	if (intel_crtc == NULL)
		7557	return;
2327	Serge	7558
3031	serge	7559	spin_lock_irqsave(&dev->event_lock, flags);
		7560	work = intel_crtc->unpin_work;
3243	Serge	7561
		7562	/* Ensure we don't miss a work->pending update ... */
		7563	smp_rmb();
		7564
		7565	if (work == NULL \|\| atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
3031	serge	7566	spin_unlock_irqrestore(&dev->event_lock, flags);
		7567	return;
		7568	}
2327	Serge	7569
3243	Serge	7570	/* and that the unpin work is consistent wrt ->pending. */
		7571	smp_rmb();
		7572
3031	serge	7573	intel_crtc->unpin_work = NULL;
2327	Serge	7574
3243	Serge	7575	if (work->event)
		7576	drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
2327	Serge	7577
3031	serge	7578	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	7579
3031	serge	7580	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7581
3480	Serge	7582	wake_up_all(&dev_priv->pending_flip_queue);
2327	Serge	7583
3243	Serge	7584	queue_work(dev_priv->wq, &work->work);
		7585
3031	serge	7586	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
		7587	}
2327	Serge	7588
3031	serge	7589	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		7590	{
		7591	drm_i915_private_t *dev_priv = dev->dev_private;
		7592	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	7593
3031	serge	7594	do_intel_finish_page_flip(dev, crtc);
		7595	}
2327	Serge	7596
3031	serge	7597	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		7598	{
		7599	drm_i915_private_t *dev_priv = dev->dev_private;
		7600	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	7601
3031	serge	7602	do_intel_finish_page_flip(dev, crtc);
		7603	}
2327	Serge	7604
3031	serge	7605	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		7606	{
		7607	drm_i915_private_t *dev_priv = dev->dev_private;
		7608	struct intel_crtc *intel_crtc =
		7609	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		7610	unsigned long flags;
2327	Serge	7611
3243	Serge	7612	/* NB: An MMIO update of the plane base pointer will also
		7613	* generate a page-flip completion irq, i.e. every modeset
		7614	* is also accompanied by a spurious intel_prepare_page_flip().
		7615	*/
3031	serge	7616	spin_lock_irqsave(&dev->event_lock, flags);
3243	Serge	7617	if (intel_crtc->unpin_work)
		7618	atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
3031	serge	7619	spin_unlock_irqrestore(&dev->event_lock, flags);
		7620	}
2327	Serge	7621
3243	Serge	7622	inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
		7623	{
		7624	/* Ensure that the work item is consistent when activating it ... */
		7625	smp_wmb();
		7626	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
		7627	/* and that it is marked active as soon as the irq could fire. */
		7628	smp_wmb();
		7629	}
		7630
3031	serge	7631	static int intel_gen2_queue_flip(struct drm_device *dev,
		7632	struct drm_crtc *crtc,
		7633	struct drm_framebuffer *fb,
4104	Serge	7634	struct drm_i915_gem_object *obj,
		7635	uint32_t flags)
3031	serge	7636	{
		7637	struct drm_i915_private *dev_priv = dev->dev_private;
		7638	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7639	u32 flip_mask;
		7640	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7641	int ret;
2327	Serge	7642
3031	serge	7643	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7644	if (ret)
		7645	goto err;
2327	Serge	7646
3031	serge	7647	ret = intel_ring_begin(ring, 6);
		7648	if (ret)
		7649	goto err_unpin;
2327	Serge	7650
3031	serge	7651	/* Can't queue multiple flips, so wait for the previous
		7652	* one to finish before executing the next.
		7653	*/
		7654	if (intel_crtc->plane)
		7655	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7656	else
		7657	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7658	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7659	intel_ring_emit(ring, MI_NOOP);
		7660	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7661	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7662	intel_ring_emit(ring, fb->pitches[0]);
4104	Serge	7663	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7664	intel_ring_emit(ring, 0); /* aux display base address, unused */
3243	Serge	7665
		7666	intel_mark_page_flip_active(intel_crtc);
3031	serge	7667	intel_ring_advance(ring);
		7668	return 0;
2327	Serge	7669
3031	serge	7670	err_unpin:
		7671	intel_unpin_fb_obj(obj);
		7672	err:
		7673	return ret;
		7674	}
2327	Serge	7675
3031	serge	7676	static int intel_gen3_queue_flip(struct drm_device *dev,
		7677	struct drm_crtc *crtc,
		7678	struct drm_framebuffer *fb,
4104	Serge	7679	struct drm_i915_gem_object *obj,
		7680	uint32_t flags)
3031	serge	7681	{
		7682	struct drm_i915_private *dev_priv = dev->dev_private;
		7683	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7684	u32 flip_mask;
		7685	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7686	int ret;
2327	Serge	7687
3031	serge	7688	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7689	if (ret)
		7690	goto err;
2327	Serge	7691
3031	serge	7692	ret = intel_ring_begin(ring, 6);
		7693	if (ret)
		7694	goto err_unpin;
2327	Serge	7695
3031	serge	7696	if (intel_crtc->plane)
		7697	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7698	else
		7699	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7700	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7701	intel_ring_emit(ring, MI_NOOP);
		7702	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		7703	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7704	intel_ring_emit(ring, fb->pitches[0]);
4104	Serge	7705	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7706	intel_ring_emit(ring, MI_NOOP);
2327	Serge	7707
3243	Serge	7708	intel_mark_page_flip_active(intel_crtc);
3031	serge	7709	intel_ring_advance(ring);
		7710	return 0;
2327	Serge	7711
3031	serge	7712	err_unpin:
		7713	intel_unpin_fb_obj(obj);
		7714	err:
		7715	return ret;
		7716	}
2327	Serge	7717
3031	serge	7718	static int intel_gen4_queue_flip(struct drm_device *dev,
		7719	struct drm_crtc *crtc,
		7720	struct drm_framebuffer *fb,
4104	Serge	7721	struct drm_i915_gem_object *obj,
		7722	uint32_t flags)
3031	serge	7723	{
		7724	struct drm_i915_private *dev_priv = dev->dev_private;
		7725	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7726	uint32_t pf, pipesrc;
		7727	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7728	int ret;
2327	Serge	7729
3031	serge	7730	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7731	if (ret)
		7732	goto err;
2327	Serge	7733
3031	serge	7734	ret = intel_ring_begin(ring, 4);
		7735	if (ret)
		7736	goto err_unpin;
2327	Serge	7737
3031	serge	7738	/* i965+ uses the linear or tiled offsets from the
		7739	* Display Registers (which do not change across a page-flip)
		7740	* so we need only reprogram the base address.
		7741	*/
		7742	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7743	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7744	intel_ring_emit(ring, fb->pitches[0]);
		7745	intel_ring_emit(ring,
4104	Serge	7746	(i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) \|
3031	serge	7747	obj->tiling_mode);
2327	Serge	7748
3031	serge	7749	/* XXX Enabling the panel-fitter across page-flip is so far
		7750	* untested on non-native modes, so ignore it for now.
		7751	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		7752	*/
		7753	pf = 0;
		7754	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7755	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7756
		7757	intel_mark_page_flip_active(intel_crtc);
3031	serge	7758	intel_ring_advance(ring);
		7759	return 0;
2327	Serge	7760
3031	serge	7761	err_unpin:
		7762	intel_unpin_fb_obj(obj);
		7763	err:
		7764	return ret;
		7765	}
2327	Serge	7766
3031	serge	7767	static int intel_gen6_queue_flip(struct drm_device *dev,
		7768	struct drm_crtc *crtc,
		7769	struct drm_framebuffer *fb,
4104	Serge	7770	struct drm_i915_gem_object *obj,
		7771	uint32_t flags)
3031	serge	7772	{
		7773	struct drm_i915_private *dev_priv = dev->dev_private;
		7774	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7775	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7776	uint32_t pf, pipesrc;
		7777	int ret;
2327	Serge	7778
3031	serge	7779	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7780	if (ret)
		7781	goto err;
2327	Serge	7782
3031	serge	7783	ret = intel_ring_begin(ring, 4);
		7784	if (ret)
		7785	goto err_unpin;
2327	Serge	7786
3031	serge	7787	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7788	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7789	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
4104	Serge	7790	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	7791
3031	serge	7792	/* Contrary to the suggestions in the documentation,
		7793	* "Enable Panel Fitter" does not seem to be required when page
		7794	* flipping with a non-native mode, and worse causes a normal
		7795	* modeset to fail.
		7796	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		7797	*/
		7798	pf = 0;
		7799	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7800	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7801
		7802	intel_mark_page_flip_active(intel_crtc);
3031	serge	7803	intel_ring_advance(ring);
		7804	return 0;
2327	Serge	7805
3031	serge	7806	err_unpin:
		7807	intel_unpin_fb_obj(obj);
		7808	err:
		7809	return ret;
		7810	}
2327	Serge	7811
3031	serge	7812	static int intel_gen7_queue_flip(struct drm_device *dev,
		7813	struct drm_crtc *crtc,
		7814	struct drm_framebuffer *fb,
4104	Serge	7815	struct drm_i915_gem_object *obj,
		7816	uint32_t flags)
3031	serge	7817	{
		7818	struct drm_i915_private *dev_priv = dev->dev_private;
		7819	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	7820	struct intel_ring_buffer *ring;
3031	serge	7821	uint32_t plane_bit = 0;
4104	Serge	7822	int len, ret;
2327	Serge	7823
4104	Serge	7824	ring = obj->ring;
		7825	if (IS_VALLEYVIEW(dev) \|\| ring == NULL \|\| ring->id != RCS)
		7826	ring = &dev_priv->ring[BCS];
		7827
3031	serge	7828	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7829	if (ret)
		7830	goto err;
2327	Serge	7831
3031	serge	7832	switch(intel_crtc->plane) {
		7833	case PLANE_A:
		7834	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		7835	break;
		7836	case PLANE_B:
		7837	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		7838	break;
		7839	case PLANE_C:
		7840	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		7841	break;
		7842	default:
		7843	WARN_ONCE(1, "unknown plane in flip command\n");
		7844	ret = -ENODEV;
		7845	goto err_unpin;
		7846	}
2327	Serge	7847
4104	Serge	7848	len = 4;
		7849	if (ring->id == RCS)
		7850	len += 6;
		7851
		7852	ret = intel_ring_begin(ring, len);
3031	serge	7853	if (ret)
		7854	goto err_unpin;
2327	Serge	7855
4104	Serge	7856	/* Unmask the flip-done completion message. Note that the bspec says that
		7857	* we should do this for both the BCS and RCS, and that we must not unmask
		7858	* more than one flip event at any time (or ensure that one flip message
		7859	* can be sent by waiting for flip-done prior to queueing new flips).
		7860	* Experimentation says that BCS works despite DERRMR masking all
		7861	* flip-done completion events and that unmasking all planes at once
		7862	* for the RCS also doesn't appear to drop events. Setting the DERRMR
		7863	* to zero does lead to lockups within MI_DISPLAY_FLIP.
		7864	*/
		7865	if (ring->id == RCS) {
		7866	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		7867	intel_ring_emit(ring, DERRMR);
		7868	intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE \|
		7869	DERRMR_PIPEB_PRI_FLIP_DONE \|
		7870	DERRMR_PIPEC_PRI_FLIP_DONE));
		7871	intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
		7872	intel_ring_emit(ring, DERRMR);
		7873	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
		7874	}
		7875
3031	serge	7876	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		7877	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
4104	Serge	7878	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7879	intel_ring_emit(ring, (MI_NOOP));
3243	Serge	7880
		7881	intel_mark_page_flip_active(intel_crtc);
3031	serge	7882	intel_ring_advance(ring);
		7883	return 0;
2327	Serge	7884
3031	serge	7885	err_unpin:
		7886	intel_unpin_fb_obj(obj);
		7887	err:
		7888	return ret;
		7889	}
2327	Serge	7890
3031	serge	7891	static int intel_default_queue_flip(struct drm_device *dev,
		7892	struct drm_crtc *crtc,
		7893	struct drm_framebuffer *fb,
4104	Serge	7894	struct drm_i915_gem_object *obj,
		7895	uint32_t flags)
3031	serge	7896	{
		7897	return -ENODEV;
		7898	}
2327	Serge	7899
3031	serge	7900	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		7901	struct drm_framebuffer *fb,
4104	Serge	7902	struct drm_pending_vblank_event *event,
		7903	uint32_t page_flip_flags)
3031	serge	7904	{
		7905	struct drm_device *dev = crtc->dev;
		7906	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	7907	struct drm_framebuffer *old_fb = crtc->fb;
		7908	struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
3031	serge	7909	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7910	struct intel_unpin_work *work;
		7911	unsigned long flags;
		7912	int ret;
2327	Serge	7913
3031	serge	7914	/* Can't change pixel format via MI display flips. */
		7915	if (fb->pixel_format != crtc->fb->pixel_format)
		7916	return -EINVAL;
2327	Serge	7917
3031	serge	7918	/*
		7919	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		7920	* Note that pitch changes could also affect these register.
		7921	*/
		7922	if (INTEL_INFO(dev)->gen > 3 &&
		7923	(fb->offsets[0] != crtc->fb->offsets[0] \|\|
		7924	fb->pitches[0] != crtc->fb->pitches[0]))
		7925	return -EINVAL;
2327	Serge	7926
3031	serge	7927	work = kzalloc(sizeof *work, GFP_KERNEL);
		7928	if (work == NULL)
		7929	return -ENOMEM;
2327	Serge	7930
3031	serge	7931	work->event = event;
3243	Serge	7932	work->crtc = crtc;
3480	Serge	7933	work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
3031	serge	7934	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	7935
3031	serge	7936	ret = drm_vblank_get(dev, intel_crtc->pipe);
		7937	if (ret)
		7938	goto free_work;
2327	Serge	7939
3031	serge	7940	/* We borrow the event spin lock for protecting unpin_work */
		7941	spin_lock_irqsave(&dev->event_lock, flags);
		7942	if (intel_crtc->unpin_work) {
		7943	spin_unlock_irqrestore(&dev->event_lock, flags);
		7944	kfree(work);
		7945	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	7946
3031	serge	7947	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		7948	return -EBUSY;
		7949	}
		7950	intel_crtc->unpin_work = work;
		7951	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7952
3243	Serge	7953	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		7954	flush_workqueue(dev_priv->wq);
		7955
3031	serge	7956	ret = i915_mutex_lock_interruptible(dev);
		7957	if (ret)
		7958	goto cleanup;
2327	Serge	7959
3031	serge	7960	/* Reference the objects for the scheduled work. */
		7961	drm_gem_object_reference(&work->old_fb_obj->base);
		7962	drm_gem_object_reference(&obj->base);
2327	Serge	7963
3031	serge	7964	crtc->fb = fb;
2327	Serge	7965
3031	serge	7966	work->pending_flip_obj = obj;
2327	Serge	7967
3031	serge	7968	work->enable_stall_check = true;
		7969
3243	Serge	7970	atomic_inc(&intel_crtc->unpin_work_count);
3480	Serge	7971	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3031	serge	7972
4104	Serge	7973	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
3031	serge	7974	if (ret)
		7975	goto cleanup_pending;
		7976
		7977	intel_disable_fbc(dev);
4104	Serge	7978	intel_mark_fb_busy(obj, NULL);
3031	serge	7979	mutex_unlock(&dev->struct_mutex);
		7980
		7981	trace_i915_flip_request(intel_crtc->plane, obj);
		7982
		7983	return 0;
		7984
		7985	cleanup_pending:
3243	Serge	7986	atomic_dec(&intel_crtc->unpin_work_count);
3480	Serge	7987	crtc->fb = old_fb;
3031	serge	7988	drm_gem_object_unreference(&work->old_fb_obj->base);
		7989	drm_gem_object_unreference(&obj->base);
		7990	mutex_unlock(&dev->struct_mutex);
		7991
		7992	cleanup:
		7993	spin_lock_irqsave(&dev->event_lock, flags);
		7994	intel_crtc->unpin_work = NULL;
		7995	spin_unlock_irqrestore(&dev->event_lock, flags);
		7996
		7997	drm_vblank_put(dev, intel_crtc->pipe);
		7998	free_work:
		7999	kfree(work);
		8000
		8001	return ret;
		8002	}
		8003	#endif
		8004
		8005	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		8006	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		8007	.load_lut = intel_crtc_load_lut,
		8008	};
		8009
		8010	static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
		8011	struct drm_crtc *crtc)
		8012	{
		8013	struct drm_device *dev;
		8014	struct drm_crtc *tmp;
		8015	int crtc_mask = 1;
		8016
		8017	WARN(!crtc, "checking null crtc?\n");
		8018
		8019	dev = crtc->dev;
		8020
		8021	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		8022	if (tmp == crtc)
		8023	break;
		8024	crtc_mask <<= 1;
		8025	}
		8026
		8027	if (encoder->possible_crtcs & crtc_mask)
		8028	return true;
		8029	return false;
		8030	}
		8031
		8032	/**
		8033	* intel_modeset_update_staged_output_state
		8034	*
		8035	* Updates the staged output configuration state, e.g. after we've read out the
		8036	* current hw state.
		8037	*/
		8038	static void intel_modeset_update_staged_output_state(struct drm_device *dev)
		8039	{
		8040	struct intel_encoder *encoder;
		8041	struct intel_connector *connector;
		8042
		8043	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8044	base.head) {
		8045	connector->new_encoder =
		8046	to_intel_encoder(connector->base.encoder);
		8047	}
		8048
		8049	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8050	base.head) {
		8051	encoder->new_crtc =
		8052	to_intel_crtc(encoder->base.crtc);
		8053	}
		8054	}
		8055
		8056	/**
		8057	* intel_modeset_commit_output_state
		8058	*
		8059	* This function copies the stage display pipe configuration to the real one.
		8060	*/
		8061	static void intel_modeset_commit_output_state(struct drm_device *dev)
		8062	{
		8063	struct intel_encoder *encoder;
		8064	struct intel_connector *connector;
		8065
		8066	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8067	base.head) {
		8068	connector->base.encoder = &connector->new_encoder->base;
		8069	}
		8070
		8071	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8072	base.head) {
		8073	encoder->base.crtc = &encoder->new_crtc->base;
		8074	}
		8075	}
		8076
4104	Serge	8077	static void
		8078	connected_sink_compute_bpp(struct intel_connector * connector,
		8079	struct intel_crtc_config *pipe_config)
		8080	{
		8081	int bpp = pipe_config->pipe_bpp;
		8082
		8083	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
		8084	connector->base.base.id,
		8085	drm_get_connector_name(&connector->base));
		8086
		8087	/* Don't use an invalid EDID bpc value */
		8088	if (connector->base.display_info.bpc &&
		8089	connector->base.display_info.bpc * 3 < bpp) {
		8090	DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
		8091	bpp, connector->base.display_info.bpc*3);
		8092	pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
		8093	}
		8094
		8095	/* Clamp bpp to 8 on screens without EDID 1.4 */
		8096	if (connector->base.display_info.bpc == 0 && bpp > 24) {
		8097	DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
		8098	bpp);
		8099	pipe_config->pipe_bpp = 24;
		8100	}
		8101	}
		8102
3746	Serge	8103	static int
4104	Serge	8104	compute_baseline_pipe_bpp(struct intel_crtc *crtc,
3746	Serge	8105	struct drm_framebuffer *fb,
		8106	struct intel_crtc_config *pipe_config)
		8107	{
4104	Serge	8108	struct drm_device *dev = crtc->base.dev;
		8109	struct intel_connector *connector;
3746	Serge	8110	int bpp;
		8111
		8112	switch (fb->pixel_format) {
		8113	case DRM_FORMAT_C8:
		8114	bpp = 83; / since we go through a colormap */
		8115	break;
		8116	case DRM_FORMAT_XRGB1555:
		8117	case DRM_FORMAT_ARGB1555:
		8118	/* checked in intel_framebuffer_init already */
		8119	if (WARN_ON(INTEL_INFO(dev)->gen > 3))
		8120	return -EINVAL;
		8121	case DRM_FORMAT_RGB565:
		8122	bpp = 63; / min is 18bpp */
		8123	break;
		8124	case DRM_FORMAT_XBGR8888:
		8125	case DRM_FORMAT_ABGR8888:
		8126	/* checked in intel_framebuffer_init already */
		8127	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		8128	return -EINVAL;
		8129	case DRM_FORMAT_XRGB8888:
		8130	case DRM_FORMAT_ARGB8888:
		8131	bpp = 8*3;
		8132	break;
		8133	case DRM_FORMAT_XRGB2101010:
		8134	case DRM_FORMAT_ARGB2101010:
		8135	case DRM_FORMAT_XBGR2101010:
		8136	case DRM_FORMAT_ABGR2101010:
		8137	/* checked in intel_framebuffer_init already */
		8138	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		8139	return -EINVAL;
		8140	bpp = 10*3;
		8141	break;
		8142	/* TODO: gen4+ supports 16 bpc floating point, too. */
		8143	default:
		8144	DRM_DEBUG_KMS("unsupported depth\n");
		8145	return -EINVAL;
		8146	}
		8147
		8148	pipe_config->pipe_bpp = bpp;
		8149
		8150	/* Clamp display bpp to EDID value */
		8151	list_for_each_entry(connector, &dev->mode_config.connector_list,
4104	Serge	8152	base.head) {
		8153	if (!connector->new_encoder \|\|
		8154	connector->new_encoder->new_crtc != crtc)
3746	Serge	8155	continue;
		8156
4104	Serge	8157	connected_sink_compute_bpp(connector, pipe_config);
3746	Serge	8158	}
		8159
		8160	return bpp;
		8161	}
		8162
4104	Serge	8163	static void intel_dump_pipe_config(struct intel_crtc *crtc,
		8164	struct intel_crtc_config *pipe_config,
		8165	const char *context)
		8166	{
		8167	DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
		8168	context, pipe_name(crtc->pipe));
		8169
		8170	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
		8171	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
		8172	pipe_config->pipe_bpp, pipe_config->dither);
		8173	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		8174	pipe_config->has_pch_encoder,
		8175	pipe_config->fdi_lanes,
		8176	pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
		8177	pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
		8178	pipe_config->fdi_m_n.tu);
		8179	DRM_DEBUG_KMS("requested mode:\n");
		8180	drm_mode_debug_printmodeline(&pipe_config->requested_mode);
		8181	DRM_DEBUG_KMS("adjusted mode:\n");
		8182	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
		8183	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
		8184	pipe_config->gmch_pfit.control,
		8185	pipe_config->gmch_pfit.pgm_ratios,
		8186	pipe_config->gmch_pfit.lvds_border_bits);
		8187	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
		8188	pipe_config->pch_pfit.pos,
		8189	pipe_config->pch_pfit.size,
		8190	pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
		8191	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
		8192	}
		8193
		8194	static bool check_encoder_cloning(struct drm_crtc *crtc)
		8195	{
		8196	int num_encoders = 0;
		8197	bool uncloneable_encoders = false;
		8198	struct intel_encoder *encoder;
		8199
		8200	list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
		8201	base.head) {
		8202	if (&encoder->new_crtc->base != crtc)
		8203	continue;
		8204
		8205	num_encoders++;
		8206	if (!encoder->cloneable)
		8207	uncloneable_encoders = true;
		8208	}
		8209
		8210	return !(num_encoders > 1 && uncloneable_encoders);
		8211	}
		8212
3746	Serge	8213	static struct intel_crtc_config *
		8214	intel_modeset_pipe_config(struct drm_crtc *crtc,
		8215	struct drm_framebuffer *fb,
3031	serge	8216	struct drm_display_mode *mode)
		8217	{
		8218	struct drm_device *dev = crtc->dev;
		8219	struct intel_encoder *encoder;
3746	Serge	8220	struct intel_crtc_config *pipe_config;
4104	Serge	8221	int plane_bpp, ret = -EINVAL;
		8222	bool retry = true;
3031	serge	8223
4104	Serge	8224	if (!check_encoder_cloning(crtc)) {
		8225	DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
		8226	return ERR_PTR(-EINVAL);
		8227	}
		8228
3746	Serge	8229	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
		8230	if (!pipe_config)
3031	serge	8231	return ERR_PTR(-ENOMEM);
		8232
3746	Serge	8233	drm_mode_copy(&pipe_config->adjusted_mode, mode);
		8234	drm_mode_copy(&pipe_config->requested_mode, mode);
4104	Serge	8235	pipe_config->cpu_transcoder =
		8236	(enum transcoder) to_intel_crtc(crtc)->pipe;
		8237	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
3746	Serge	8238
4104	Serge	8239	/*
		8240	* Sanitize sync polarity flags based on requested ones. If neither
		8241	* positive or negative polarity is requested, treat this as meaning
		8242	* negative polarity.
		8243	*/
		8244	if (!(pipe_config->adjusted_mode.flags &
		8245	(DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NHSYNC)))
		8246	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		8247
		8248	if (!(pipe_config->adjusted_mode.flags &
		8249	(DRM_MODE_FLAG_PVSYNC \| DRM_MODE_FLAG_NVSYNC)))
		8250	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		8251
		8252	/* Compute a starting value for pipe_config->pipe_bpp taking the source
		8253	* plane pixel format and any sink constraints into account. Returns the
		8254	* source plane bpp so that dithering can be selected on mismatches
		8255	* after encoders and crtc also have had their say. */
		8256	plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
		8257	fb, pipe_config);
3746	Serge	8258	if (plane_bpp < 0)
		8259	goto fail;
		8260
4104	Serge	8261	encoder_retry:
		8262	/* Ensure the port clock defaults are reset when retrying. */
		8263	pipe_config->port_clock = 0;
		8264	pipe_config->pixel_multiplier = 1;
		8265
		8266	/* Fill in default crtc timings, allow encoders to overwrite them. */
		8267	drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
		8268
3031	serge	8269	/* Pass our mode to the connectors and the CRTC to give them a chance to
		8270	* adjust it according to limitations or connector properties, and also
		8271	* a chance to reject the mode entirely.
2330	Serge	8272	*/
3031	serge	8273	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8274	base.head) {
2327	Serge	8275
3031	serge	8276	if (&encoder->new_crtc->base != crtc)
		8277	continue;
3746	Serge	8278
		8279	if (!(encoder->compute_config(encoder, pipe_config))) {
		8280	DRM_DEBUG_KMS("Encoder config failure\n");
		8281	goto fail;
		8282	}
		8283	}
		8284
4104	Serge	8285	/* Set default port clock if not overwritten by the encoder. Needs to be
		8286	* done afterwards in case the encoder adjusts the mode. */
		8287	if (!pipe_config->port_clock)
		8288	pipe_config->port_clock = pipe_config->adjusted_mode.clock;
2327	Serge	8289
4104	Serge	8290	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
		8291	if (ret < 0) {
3031	serge	8292	DRM_DEBUG_KMS("CRTC fixup failed\n");
		8293	goto fail;
		8294	}
2327	Serge	8295
4104	Serge	8296	if (ret == RETRY) {
		8297	if (WARN(!retry, "loop in pipe configuration computation\n")) {
		8298	ret = -EINVAL;
		8299	goto fail;
		8300	}
		8301
		8302	DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
		8303	retry = false;
		8304	goto encoder_retry;
		8305	}
		8306
3746	Serge	8307	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
		8308	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		8309	plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
		8310
		8311	return pipe_config;
3031	serge	8312	fail:
3746	Serge	8313	kfree(pipe_config);
4104	Serge	8314	return ERR_PTR(ret);
3031	serge	8315	}
2327	Serge	8316
3031	serge	8317	/* Computes which crtcs are affected and sets the relevant bits in the mask. For
		8318	* simplicity we use the crtc's pipe number (because it's easier to obtain). */
		8319	static void
		8320	intel_modeset_affected_pipes(struct drm_crtc crtc, unsigned modeset_pipes,
		8321	unsigned prepare_pipes, unsigned disable_pipes)
		8322	{
		8323	struct intel_crtc *intel_crtc;
		8324	struct drm_device *dev = crtc->dev;
		8325	struct intel_encoder *encoder;
		8326	struct intel_connector *connector;
		8327	struct drm_crtc *tmp_crtc;
		8328
		8329	disable_pipes = modeset_pipes = *prepare_pipes = 0;
		8330
		8331	/* Check which crtcs have changed outputs connected to them, these need
		8332	* to be part of the prepare_pipes mask. We don't (yet) support global
		8333	* modeset across multiple crtcs, so modeset_pipes will only have one
		8334	* bit set at most. */
		8335	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8336	base.head) {
		8337	if (connector->base.encoder == &connector->new_encoder->base)
		8338	continue;
		8339
		8340	if (connector->base.encoder) {
		8341	tmp_crtc = connector->base.encoder->crtc;
		8342
		8343	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		8344	}
		8345
		8346	if (connector->new_encoder)
		8347	*prepare_pipes \|=
		8348	1 << connector->new_encoder->new_crtc->pipe;
		8349	}
		8350
		8351	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8352	base.head) {
		8353	if (encoder->base.crtc == &encoder->new_crtc->base)
		8354	continue;
		8355
		8356	if (encoder->base.crtc) {
		8357	tmp_crtc = encoder->base.crtc;
		8358
		8359	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		8360	}
		8361
		8362	if (encoder->new_crtc)
		8363	*prepare_pipes \|= 1 << encoder->new_crtc->pipe;
		8364	}
		8365
		8366	/* Check for any pipes that will be fully disabled ... */
		8367	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		8368	base.head) {
		8369	bool used = false;
		8370
		8371	/* Don't try to disable disabled crtcs. */
		8372	if (!intel_crtc->base.enabled)
		8373	continue;
		8374
		8375	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8376	base.head) {
		8377	if (encoder->new_crtc == intel_crtc)
		8378	used = true;
		8379	}
		8380
		8381	if (!used)
		8382	*disable_pipes \|= 1 << intel_crtc->pipe;
		8383	}
		8384
		8385
		8386	/* set_mode is also used to update properties on life display pipes. */
		8387	intel_crtc = to_intel_crtc(crtc);
		8388	if (crtc->enabled)
		8389	*prepare_pipes \|= 1 << intel_crtc->pipe;
		8390
3746	Serge	8391	/*
		8392	* For simplicity do a full modeset on any pipe where the output routing
		8393	* changed. We could be more clever, but that would require us to be
		8394	* more careful with calling the relevant encoder->mode_set functions.
		8395	*/
3031	serge	8396	if (*prepare_pipes)
		8397	modeset_pipes = prepare_pipes;
		8398
		8399	/* ... and mask these out. */
		8400	modeset_pipes &= ~(disable_pipes);
		8401	prepare_pipes &= ~(disable_pipes);
3746	Serge	8402
		8403	/*
		8404	* HACK: We don't (yet) fully support global modesets. intel_set_config
		8405	* obies this rule, but the modeset restore mode of
		8406	* intel_modeset_setup_hw_state does not.
		8407	*/
		8408	*modeset_pipes &= 1 << intel_crtc->pipe;
		8409	*prepare_pipes &= 1 << intel_crtc->pipe;
4104	Serge	8410
		8411	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		8412	modeset_pipes, prepare_pipes, *disable_pipes);
2330	Serge	8413	}
2327	Serge	8414
3031	serge	8415	static bool intel_crtc_in_use(struct drm_crtc *crtc)
2330	Serge	8416	{
3031	serge	8417	struct drm_encoder *encoder;
2330	Serge	8418	struct drm_device *dev = crtc->dev;
2327	Serge	8419
3031	serge	8420	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		8421	if (encoder->crtc == crtc)
		8422	return true;
		8423
		8424	return false;
		8425	}
		8426
		8427	static void
		8428	intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
		8429	{
		8430	struct intel_encoder *intel_encoder;
		8431	struct intel_crtc *intel_crtc;
		8432	struct drm_connector *connector;
		8433
		8434	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
		8435	base.head) {
		8436	if (!intel_encoder->base.crtc)
		8437	continue;
		8438
		8439	intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
		8440
		8441	if (prepare_pipes & (1 << intel_crtc->pipe))
		8442	intel_encoder->connectors_active = false;
		8443	}
		8444
		8445	intel_modeset_commit_output_state(dev);
		8446
		8447	/* Update computed state. */
		8448	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		8449	base.head) {
		8450	intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
		8451	}
		8452
		8453	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		8454	if (!connector->encoder \|\| !connector->encoder->crtc)
		8455	continue;
		8456
		8457	intel_crtc = to_intel_crtc(connector->encoder->crtc);
		8458
		8459	if (prepare_pipes & (1 << intel_crtc->pipe)) {
		8460	struct drm_property *dpms_property =
		8461	dev->mode_config.dpms_property;
		8462
		8463	connector->dpms = DRM_MODE_DPMS_ON;
3243	Serge	8464	drm_object_property_set_value(&connector->base,
3031	serge	8465	dpms_property,
		8466	DRM_MODE_DPMS_ON);
		8467
		8468	intel_encoder = to_intel_encoder(connector->encoder);
		8469	intel_encoder->connectors_active = true;
		8470	}
		8471	}
		8472
		8473	}
		8474
4104	Serge	8475	static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
		8476	struct intel_crtc_config *new)
		8477	{
		8478	int clock1, clock2, diff;
		8479
		8480	clock1 = cur->adjusted_mode.clock;
		8481	clock2 = new->adjusted_mode.clock;
		8482
		8483	if (clock1 == clock2)
		8484	return true;
		8485
		8486	if (!clock1 \|\| !clock2)
		8487	return false;
		8488
		8489	diff = abs(clock1 - clock2);
		8490
		8491	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
		8492	return true;
		8493
		8494	return false;
		8495	}
		8496
3031	serge	8497	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		8498	list_for_each_entry((intel_crtc), \
		8499	&(dev)->mode_config.crtc_list, \
		8500	base.head) \
4104	Serge	8501	if (mask & (1 <<(intel_crtc)->pipe))
3031	serge	8502
3746	Serge	8503	static bool
4104	Serge	8504	intel_pipe_config_compare(struct drm_device *dev,
		8505	struct intel_crtc_config *current_config,
3746	Serge	8506	struct intel_crtc_config *pipe_config)
		8507	{
4104	Serge	8508	#define PIPE_CONF_CHECK_X(name) \
		8509	if (current_config->name != pipe_config->name) { \
		8510	DRM_ERROR("mismatch in " #name " " \
		8511	"(expected 0x%08x, found 0x%08x)\n", \
		8512	current_config->name, \
		8513	pipe_config->name); \
		8514	return false; \
3746	Serge	8515	}
		8516
4104	Serge	8517	#define PIPE_CONF_CHECK_I(name) \
		8518	if (current_config->name != pipe_config->name) { \
		8519	DRM_ERROR("mismatch in " #name " " \
		8520	"(expected %i, found %i)\n", \
		8521	current_config->name, \
		8522	pipe_config->name); \
		8523	return false; \
		8524	}
		8525
		8526	#define PIPE_CONF_CHECK_FLAGS(name, mask) \
		8527	if ((current_config->name ^ pipe_config->name) & (mask)) { \
		8528	DRM_ERROR("mismatch in " #name "(" #mask ") " \
		8529	"(expected %i, found %i)\n", \
		8530	current_config->name & (mask), \
		8531	pipe_config->name & (mask)); \
		8532	return false; \
		8533	}
		8534
		8535	#define PIPE_CONF_QUIRK(quirk) \
		8536	((current_config->quirks \| pipe_config->quirks) & (quirk))
		8537
		8538	PIPE_CONF_CHECK_I(cpu_transcoder);
		8539
		8540	PIPE_CONF_CHECK_I(has_pch_encoder);
		8541	PIPE_CONF_CHECK_I(fdi_lanes);
		8542	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
		8543	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
		8544	PIPE_CONF_CHECK_I(fdi_m_n.link_m);
		8545	PIPE_CONF_CHECK_I(fdi_m_n.link_n);
		8546	PIPE_CONF_CHECK_I(fdi_m_n.tu);
		8547
		8548	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
		8549	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
		8550	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
		8551	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
		8552	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
		8553	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
		8554
		8555	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
		8556	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
		8557	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
		8558	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
		8559	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
		8560	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
		8561
		8562	PIPE_CONF_CHECK_I(pixel_multiplier);
		8563
		8564	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8565	DRM_MODE_FLAG_INTERLACE);
		8566
		8567	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
		8568	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8569	DRM_MODE_FLAG_PHSYNC);
		8570	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8571	DRM_MODE_FLAG_NHSYNC);
		8572	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8573	DRM_MODE_FLAG_PVSYNC);
		8574	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8575	DRM_MODE_FLAG_NVSYNC);
		8576	}
		8577
		8578	PIPE_CONF_CHECK_I(requested_mode.hdisplay);
		8579	PIPE_CONF_CHECK_I(requested_mode.vdisplay);
		8580
		8581	PIPE_CONF_CHECK_I(gmch_pfit.control);
		8582	/* pfit ratios are autocomputed by the hw on gen4+ */
		8583	if (INTEL_INFO(dev)->gen < 4)
		8584	PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
		8585	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
		8586	PIPE_CONF_CHECK_I(pch_pfit.enabled);
		8587	if (current_config->pch_pfit.enabled) {
		8588	PIPE_CONF_CHECK_I(pch_pfit.pos);
		8589	PIPE_CONF_CHECK_I(pch_pfit.size);
		8590	}
		8591
		8592	PIPE_CONF_CHECK_I(ips_enabled);
		8593
		8594	PIPE_CONF_CHECK_I(shared_dpll);
		8595	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
		8596	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
		8597	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
		8598	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
		8599
		8600	#undef PIPE_CONF_CHECK_X
		8601	#undef PIPE_CONF_CHECK_I
		8602	#undef PIPE_CONF_CHECK_FLAGS
		8603	#undef PIPE_CONF_QUIRK
		8604
		8605	if (!IS_HASWELL(dev)) {
		8606	if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
		8607	DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
		8608	current_config->adjusted_mode.clock,
		8609	pipe_config->adjusted_mode.clock);
		8610	return false;
		8611	}
		8612	}
		8613
3746	Serge	8614	return true;
		8615	}
		8616
4104	Serge	8617	static void
		8618	check_connector_state(struct drm_device *dev)
3031	serge	8619	{
		8620	struct intel_connector *connector;
		8621
		8622	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8623	base.head) {
		8624	/* This also checks the encoder/connector hw state with the
		8625	* ->get_hw_state callbacks. */
		8626	intel_connector_check_state(connector);
		8627
		8628	WARN(&connector->new_encoder->base != connector->base.encoder,
		8629	"connector's staged encoder doesn't match current encoder\n");
		8630	}
4104	Serge	8631	}
3031	serge	8632
4104	Serge	8633	static void
		8634	check_encoder_state(struct drm_device *dev)
		8635	{
		8636	struct intel_encoder *encoder;
		8637	struct intel_connector *connector;
		8638
3031	serge	8639	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8640	base.head) {
		8641	bool enabled = false;
		8642	bool active = false;
		8643	enum pipe pipe, tracked_pipe;
		8644
		8645	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		8646	encoder->base.base.id,
		8647	drm_get_encoder_name(&encoder->base));
		8648
		8649	WARN(&encoder->new_crtc->base != encoder->base.crtc,
		8650	"encoder's stage crtc doesn't match current crtc\n");
		8651	WARN(encoder->connectors_active && !encoder->base.crtc,
		8652	"encoder's active_connectors set, but no crtc\n");
		8653
		8654	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8655	base.head) {
		8656	if (connector->base.encoder != &encoder->base)
		8657	continue;
		8658	enabled = true;
		8659	if (connector->base.dpms != DRM_MODE_DPMS_OFF)
		8660	active = true;
		8661	}
		8662	WARN(!!encoder->base.crtc != enabled,
		8663	"encoder's enabled state mismatch "
		8664	"(expected %i, found %i)\n",
		8665	!!encoder->base.crtc, enabled);
		8666	WARN(active && !encoder->base.crtc,
		8667	"active encoder with no crtc\n");
		8668
		8669	WARN(encoder->connectors_active != active,
		8670	"encoder's computed active state doesn't match tracked active state "
		8671	"(expected %i, found %i)\n", active, encoder->connectors_active);
		8672
		8673	active = encoder->get_hw_state(encoder, &pipe);
		8674	WARN(active != encoder->connectors_active,
		8675	"encoder's hw state doesn't match sw tracking "
		8676	"(expected %i, found %i)\n",
		8677	encoder->connectors_active, active);
		8678
		8679	if (!encoder->base.crtc)
		8680	continue;
		8681
		8682	tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		8683	WARN(active && pipe != tracked_pipe,
		8684	"active encoder's pipe doesn't match"
		8685	"(expected %i, found %i)\n",
		8686	tracked_pipe, pipe);
		8687
		8688	}
4104	Serge	8689	}
3031	serge	8690
4104	Serge	8691	static void
		8692	check_crtc_state(struct drm_device *dev)
		8693	{
		8694	drm_i915_private_t *dev_priv = dev->dev_private;
		8695	struct intel_crtc *crtc;
		8696	struct intel_encoder *encoder;
		8697	struct intel_crtc_config pipe_config;
		8698
3031	serge	8699	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		8700	base.head) {
		8701	bool enabled = false;
		8702	bool active = false;
		8703
4104	Serge	8704	memset(&pipe_config, 0, sizeof(pipe_config));
		8705
3031	serge	8706	DRM_DEBUG_KMS("[CRTC:%d]\n",
		8707	crtc->base.base.id);
		8708
		8709	WARN(crtc->active && !crtc->base.enabled,
		8710	"active crtc, but not enabled in sw tracking\n");
		8711
		8712	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8713	base.head) {
		8714	if (encoder->base.crtc != &crtc->base)
		8715	continue;
		8716	enabled = true;
		8717	if (encoder->connectors_active)
		8718	active = true;
		8719	}
4104	Serge	8720
3031	serge	8721	WARN(active != crtc->active,
		8722	"crtc's computed active state doesn't match tracked active state "
		8723	"(expected %i, found %i)\n", active, crtc->active);
		8724	WARN(enabled != crtc->base.enabled,
		8725	"crtc's computed enabled state doesn't match tracked enabled state "
		8726	"(expected %i, found %i)\n", enabled, crtc->base.enabled);
		8727
3746	Serge	8728	active = dev_priv->display.get_pipe_config(crtc,
		8729	&pipe_config);
		8730
		8731	/* hw state is inconsistent with the pipe A quirk */
		8732	if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		8733	active = crtc->active;
		8734
4104	Serge	8735	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8736	base.head) {
		8737	enum pipe pipe;
		8738	if (encoder->base.crtc != &crtc->base)
		8739	continue;
		8740	if (encoder->get_config &&
		8741	encoder->get_hw_state(encoder, &pipe))
		8742	encoder->get_config(encoder, &pipe_config);
		8743	}
		8744
		8745	if (dev_priv->display.get_clock)
		8746	dev_priv->display.get_clock(crtc, &pipe_config);
		8747
3746	Serge	8748	WARN(crtc->active != active,
		8749	"crtc active state doesn't match with hw state "
		8750	"(expected %i, found %i)\n", crtc->active, active);
		8751
4104	Serge	8752	if (active &&
		8753	!intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
		8754	WARN(1, "pipe state doesn't match!\n");
		8755	intel_dump_pipe_config(crtc, &pipe_config,
		8756	"[hw state]");
		8757	intel_dump_pipe_config(crtc, &crtc->config,
		8758	"[sw state]");
		8759	}
3031	serge	8760	}
		8761	}
		8762
4104	Serge	8763	static void
		8764	check_shared_dpll_state(struct drm_device *dev)
		8765	{
		8766	drm_i915_private_t *dev_priv = dev->dev_private;
		8767	struct intel_crtc *crtc;
		8768	struct intel_dpll_hw_state dpll_hw_state;
		8769	int i;
		8770
		8771	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		8772	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		8773	int enabled_crtcs = 0, active_crtcs = 0;
		8774	bool active;
		8775
		8776	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
		8777
		8778	DRM_DEBUG_KMS("%s\n", pll->name);
		8779
		8780	active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
		8781
		8782	WARN(pll->active > pll->refcount,
		8783	"more active pll users than references: %i vs %i\n",
		8784	pll->active, pll->refcount);
		8785	WARN(pll->active && !pll->on,
		8786	"pll in active use but not on in sw tracking\n");
		8787	WARN(pll->on && !pll->active,
		8788	"pll in on but not on in use in sw tracking\n");
		8789	WARN(pll->on != active,
		8790	"pll on state mismatch (expected %i, found %i)\n",
		8791	pll->on, active);
		8792
		8793	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		8794	base.head) {
		8795	if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
		8796	enabled_crtcs++;
		8797	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		8798	active_crtcs++;
		8799	}
		8800	WARN(pll->active != active_crtcs,
		8801	"pll active crtcs mismatch (expected %i, found %i)\n",
		8802	pll->active, active_crtcs);
		8803	WARN(pll->refcount != enabled_crtcs,
		8804	"pll enabled crtcs mismatch (expected %i, found %i)\n",
		8805	pll->refcount, enabled_crtcs);
		8806
		8807	WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
		8808	sizeof(dpll_hw_state)),
		8809	"pll hw state mismatch\n");
		8810	}
		8811	}
		8812
		8813	void
		8814	intel_modeset_check_state(struct drm_device *dev)
		8815	{
		8816	check_connector_state(dev);
		8817	check_encoder_state(dev);
		8818	check_crtc_state(dev);
		8819	check_shared_dpll_state(dev);
		8820	}
		8821
3746	Serge	8822	static int __intel_set_mode(struct drm_crtc *crtc,
3031	serge	8823	struct drm_display_mode *mode,
		8824	int x, int y, struct drm_framebuffer *fb)
		8825	{
		8826	struct drm_device *dev = crtc->dev;
		8827	drm_i915_private_t *dev_priv = dev->dev_private;
3746	Serge	8828	struct drm_display_mode saved_mode, saved_hwmode;
		8829	struct intel_crtc_config *pipe_config = NULL;
3031	serge	8830	struct intel_crtc *intel_crtc;
		8831	unsigned disable_pipes, prepare_pipes, modeset_pipes;
3480	Serge	8832	int ret = 0;
3031	serge	8833
3480	Serge	8834	saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
		8835	if (!saved_mode)
		8836	return -ENOMEM;
		8837	saved_hwmode = saved_mode + 1;
		8838
3031	serge	8839	intel_modeset_affected_pipes(crtc, &modeset_pipes,
		8840	&prepare_pipes, &disable_pipes);
		8841
3480	Serge	8842	*saved_hwmode = crtc->hwmode;
		8843	*saved_mode = crtc->mode;
3031	serge	8844
		8845	/* Hack: Because we don't (yet) support global modeset on multiple
		8846	* crtcs, we don't keep track of the new mode for more than one crtc.
		8847	* Hence simply check whether any bit is set in modeset_pipes in all the
		8848	* pieces of code that are not yet converted to deal with mutliple crtcs
		8849	* changing their mode at the same time. */
		8850	if (modeset_pipes) {
3746	Serge	8851	pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
		8852	if (IS_ERR(pipe_config)) {
		8853	ret = PTR_ERR(pipe_config);
		8854	pipe_config = NULL;
		8855
3480	Serge	8856	goto out;
3031	serge	8857	}
4104	Serge	8858	intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
		8859	"[modeset]");
3031	serge	8860	}
		8861
3746	Serge	8862	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		8863	intel_crtc_disable(&intel_crtc->base);
		8864
3031	serge	8865	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		8866	if (intel_crtc->base.enabled)
		8867	dev_priv->display.crtc_disable(&intel_crtc->base);
		8868	}
		8869
		8870	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
		8871	* to set it here already despite that we pass it down the callchain.
2330	Serge	8872	*/
3746	Serge	8873	if (modeset_pipes) {
3031	serge	8874	crtc->mode = *mode;
3746	Serge	8875	/* mode_set/enable/disable functions rely on a correct pipe
		8876	* config. */
		8877	to_intel_crtc(crtc)->config = *pipe_config;
		8878	}
2327	Serge	8879
3031	serge	8880	/* Only after disabling all output pipelines that will be changed can we
		8881	* update the the output configuration. */
		8882	intel_modeset_update_state(dev, prepare_pipes);
		8883
3243	Serge	8884	if (dev_priv->display.modeset_global_resources)
		8885	dev_priv->display.modeset_global_resources(dev);
		8886
3031	serge	8887	/* Set up the DPLL and any encoders state that needs to adjust or depend
		8888	* on the DPLL.
2330	Serge	8889	*/
3031	serge	8890	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
3480	Serge	8891	ret = intel_crtc_mode_set(&intel_crtc->base,
3031	serge	8892	x, y, fb);
3480	Serge	8893	if (ret)
3031	serge	8894	goto done;
		8895	}
		8896
		8897	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
		8898	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		8899	dev_priv->display.crtc_enable(&intel_crtc->base);
		8900
		8901	if (modeset_pipes) {
		8902	/* Store real post-adjustment hardware mode. */
3746	Serge	8903	crtc->hwmode = pipe_config->adjusted_mode;
3031	serge	8904
		8905	/* Calculate and store various constants which
		8906	* are later needed by vblank and swap-completion
		8907	* timestamping. They are derived from true hwmode.
		8908	*/
		8909	drm_calc_timestamping_constants(crtc);
		8910	}
		8911
		8912	/* FIXME: add subpixel order */
		8913	done:
3480	Serge	8914	if (ret && crtc->enabled) {
		8915	crtc->hwmode = *saved_hwmode;
		8916	crtc->mode = *saved_mode;
3031	serge	8917	}
		8918
3480	Serge	8919	out:
3746	Serge	8920	kfree(pipe_config);
3480	Serge	8921	kfree(saved_mode);
3031	serge	8922	return ret;
2330	Serge	8923	}
2327	Serge	8924
4104	Serge	8925	static int intel_set_mode(struct drm_crtc *crtc,
3746	Serge	8926	struct drm_display_mode *mode,
		8927	int x, int y, struct drm_framebuffer *fb)
		8928	{
		8929	int ret;
		8930
		8931	ret = __intel_set_mode(crtc, mode, x, y, fb);
		8932
		8933	if (ret == 0)
		8934	intel_modeset_check_state(crtc->dev);
		8935
		8936	return ret;
		8937	}
		8938
3480	Serge	8939	void intel_crtc_restore_mode(struct drm_crtc *crtc)
		8940	{
		8941	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
		8942	}
		8943
3031	serge	8944	#undef for_each_intel_crtc_masked
2327	Serge	8945
3031	serge	8946	static void intel_set_config_free(struct intel_set_config *config)
		8947	{
		8948	if (!config)
		8949	return;
		8950
		8951	kfree(config->save_connector_encoders);
		8952	kfree(config->save_encoder_crtcs);
		8953	kfree(config);
		8954	}
		8955
		8956	static int intel_set_config_save_state(struct drm_device *dev,
		8957	struct intel_set_config *config)
		8958	{
		8959	struct drm_encoder *encoder;
		8960	struct drm_connector *connector;
		8961	int count;
		8962
		8963	config->save_encoder_crtcs =
		8964	kcalloc(dev->mode_config.num_encoder,
		8965	sizeof(struct drm_crtc *), GFP_KERNEL);
		8966	if (!config->save_encoder_crtcs)
		8967	return -ENOMEM;
		8968
		8969	config->save_connector_encoders =
		8970	kcalloc(dev->mode_config.num_connector,
		8971	sizeof(struct drm_encoder *), GFP_KERNEL);
		8972	if (!config->save_connector_encoders)
		8973	return -ENOMEM;
		8974
		8975	/* Copy data. Note that driver private data is not affected.
		8976	* Should anything bad happen only the expected state is
		8977	* restored, not the drivers personal bookkeeping.
		8978	*/
		8979	count = 0;
		8980	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		8981	config->save_encoder_crtcs[count++] = encoder->crtc;
		8982	}
		8983
		8984	count = 0;
		8985	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		8986	config->save_connector_encoders[count++] = connector->encoder;
		8987	}
		8988
		8989	return 0;
		8990	}
		8991
		8992	static void intel_set_config_restore_state(struct drm_device *dev,
		8993	struct intel_set_config *config)
		8994	{
		8995	struct intel_encoder *encoder;
		8996	struct intel_connector *connector;
		8997	int count;
		8998
		8999	count = 0;
		9000	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		9001	encoder->new_crtc =
		9002	to_intel_crtc(config->save_encoder_crtcs[count++]);
		9003	}
		9004
		9005	count = 0;
		9006	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		9007	connector->new_encoder =
		9008	to_intel_encoder(config->save_connector_encoders[count++]);
		9009	}
		9010	}
		9011
3746	Serge	9012	static bool
4104	Serge	9013	is_crtc_connector_off(struct drm_mode_set *set)
3746	Serge	9014	{
		9015	int i;
		9016
4104	Serge	9017	if (set->num_connectors == 0)
		9018	return false;
		9019
		9020	if (WARN_ON(set->connectors == NULL))
		9021	return false;
		9022
		9023	for (i = 0; i < set->num_connectors; i++)
		9024	if (set->connectors[i]->encoder &&
		9025	set->connectors[i]->encoder->crtc == set->crtc &&
		9026	set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
3746	Serge	9027	return true;
		9028
		9029	return false;
		9030	}
		9031
3031	serge	9032	static void
		9033	intel_set_config_compute_mode_changes(struct drm_mode_set *set,
		9034	struct intel_set_config *config)
		9035	{
		9036
		9037	/* We should be able to check here if the fb has the same properties
		9038	* and then just flip_or_move it */
4104	Serge	9039	if (is_crtc_connector_off(set)) {
3746	Serge	9040	config->mode_changed = true;
		9041	} else if (set->crtc->fb != set->fb) {
3031	serge	9042	/* If we have no fb then treat it as a full mode set */
		9043	if (set->crtc->fb == NULL) {
4104	Serge	9044	struct intel_crtc *intel_crtc =
		9045	to_intel_crtc(set->crtc);
		9046
		9047	if (intel_crtc->active && i915_fastboot) {
		9048	DRM_DEBUG_KMS("crtc has no fb, will flip\n");
		9049	config->fb_changed = true;
		9050	} else {
		9051	DRM_DEBUG_KMS("inactive crtc, full mode set\n");
3031	serge	9052	config->mode_changed = true;
4104	Serge	9053	}
3031	serge	9054	} else if (set->fb == NULL) {
		9055	config->mode_changed = true;
3746	Serge	9056	} else if (set->fb->pixel_format !=
		9057	set->crtc->fb->pixel_format) {
3031	serge	9058	config->mode_changed = true;
3746	Serge	9059	} else {
3031	serge	9060	config->fb_changed = true;
		9061	}
3746	Serge	9062	}
3031	serge	9063
		9064	if (set->fb && (set->x != set->crtc->x \|\| set->y != set->crtc->y))
		9065	config->fb_changed = true;
		9066
		9067	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		9068	DRM_DEBUG_KMS("modes are different, full mode set\n");
		9069	drm_mode_debug_printmodeline(&set->crtc->mode);
		9070	drm_mode_debug_printmodeline(set->mode);
		9071	config->mode_changed = true;
		9072	}
4104	Serge	9073
		9074	DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
		9075	set->crtc->base.id, config->mode_changed, config->fb_changed);
3031	serge	9076	}
		9077
		9078	static int
		9079	intel_modeset_stage_output_state(struct drm_device *dev,
		9080	struct drm_mode_set *set,
		9081	struct intel_set_config *config)
		9082	{
		9083	struct drm_crtc *new_crtc;
		9084	struct intel_connector *connector;
		9085	struct intel_encoder *encoder;
4104	Serge	9086	int ro;
3031	serge	9087
3480	Serge	9088	/* The upper layers ensure that we either disable a crtc or have a list
3031	serge	9089	* of connectors. For paranoia, double-check this. */
		9090	WARN_ON(!set->fb && (set->num_connectors != 0));
		9091	WARN_ON(set->fb && (set->num_connectors == 0));
		9092
		9093	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9094	base.head) {
		9095	/* Otherwise traverse passed in connector list and get encoders
		9096	* for them. */
		9097	for (ro = 0; ro < set->num_connectors; ro++) {
		9098	if (set->connectors[ro] == &connector->base) {
		9099	connector->new_encoder = connector->encoder;
		9100	break;
		9101	}
		9102	}
		9103
		9104	/* If we disable the crtc, disable all its connectors. Also, if
		9105	* the connector is on the changing crtc but not on the new
		9106	* connector list, disable it. */
		9107	if ((!set->fb \|\| ro == set->num_connectors) &&
		9108	connector->base.encoder &&
		9109	connector->base.encoder->crtc == set->crtc) {
		9110	connector->new_encoder = NULL;
		9111
		9112	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
		9113	connector->base.base.id,
		9114	drm_get_connector_name(&connector->base));
		9115	}
		9116
		9117
		9118	if (&connector->new_encoder->base != connector->base.encoder) {
		9119	DRM_DEBUG_KMS("encoder changed, full mode switch\n");
		9120	config->mode_changed = true;
		9121	}
		9122	}
		9123	/* connector->new_encoder is now updated for all connectors. */
		9124
		9125	/* Update crtc of enabled connectors. */
		9126	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9127	base.head) {
		9128	if (!connector->new_encoder)
		9129	continue;
		9130
		9131	new_crtc = connector->new_encoder->base.crtc;
		9132
		9133	for (ro = 0; ro < set->num_connectors; ro++) {
		9134	if (set->connectors[ro] == &connector->base)
		9135	new_crtc = set->crtc;
		9136	}
		9137
		9138	/* Make sure the new CRTC will work with the encoder */
		9139	if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
		9140	new_crtc)) {
		9141	return -EINVAL;
		9142	}
		9143	connector->encoder->new_crtc = to_intel_crtc(new_crtc);
		9144
		9145	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
		9146	connector->base.base.id,
		9147	drm_get_connector_name(&connector->base),
		9148	new_crtc->base.id);
		9149	}
		9150
		9151	/* Check for any encoders that needs to be disabled. */
		9152	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9153	base.head) {
		9154	list_for_each_entry(connector,
		9155	&dev->mode_config.connector_list,
		9156	base.head) {
		9157	if (connector->new_encoder == encoder) {
		9158	WARN_ON(!connector->new_encoder->new_crtc);
		9159
		9160	goto next_encoder;
		9161	}
		9162	}
		9163	encoder->new_crtc = NULL;
		9164	next_encoder:
		9165	/* Only now check for crtc changes so we don't miss encoders
		9166	* that will be disabled. */
		9167	if (&encoder->new_crtc->base != encoder->base.crtc) {
		9168	DRM_DEBUG_KMS("crtc changed, full mode switch\n");
		9169	config->mode_changed = true;
		9170	}
		9171	}
		9172	/* Now we've also updated encoder->new_crtc for all encoders. */
		9173
		9174	return 0;
		9175	}
		9176
		9177	static int intel_crtc_set_config(struct drm_mode_set *set)
		9178	{
		9179	struct drm_device *dev;
		9180	struct drm_mode_set save_set;
		9181	struct intel_set_config *config;
		9182	int ret;
		9183
		9184	BUG_ON(!set);
		9185	BUG_ON(!set->crtc);
		9186	BUG_ON(!set->crtc->helper_private);
		9187
3480	Serge	9188	/* Enforce sane interface api - has been abused by the fb helper. */
		9189	BUG_ON(!set->mode && set->fb);
		9190	BUG_ON(set->fb && set->num_connectors == 0);
3031	serge	9191
		9192	if (set->fb) {
		9193	DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
		9194	set->crtc->base.id, set->fb->base.id,
		9195	(int)set->num_connectors, set->x, set->y);
		9196	} else {
		9197	DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
		9198	}
		9199
		9200	dev = set->crtc->dev;
		9201
		9202	ret = -ENOMEM;
		9203	config = kzalloc(sizeof(*config), GFP_KERNEL);
		9204	if (!config)
		9205	goto out_config;
		9206
		9207	ret = intel_set_config_save_state(dev, config);
		9208	if (ret)
		9209	goto out_config;
		9210
		9211	save_set.crtc = set->crtc;
		9212	save_set.mode = &set->crtc->mode;
		9213	save_set.x = set->crtc->x;
		9214	save_set.y = set->crtc->y;
		9215	save_set.fb = set->crtc->fb;
		9216
		9217	/* Compute whether we need a full modeset, only an fb base update or no
		9218	* change at all. In the future we might also check whether only the
		9219	* mode changed, e.g. for LVDS where we only change the panel fitter in
		9220	* such cases. */
		9221	intel_set_config_compute_mode_changes(set, config);
		9222
		9223	ret = intel_modeset_stage_output_state(dev, set, config);
		9224	if (ret)
		9225	goto fail;
		9226
		9227	if (config->mode_changed) {
3480	Serge	9228	ret = intel_set_mode(set->crtc, set->mode,
		9229	set->x, set->y, set->fb);
3031	serge	9230	} else if (config->fb_changed) {
3746	Serge	9231	// intel_crtc_wait_for_pending_flips(set->crtc);
		9232
3031	serge	9233	ret = intel_pipe_set_base(set->crtc,
		9234	set->x, set->y, set->fb);
		9235	}
		9236
3746	Serge	9237	if (ret) {
4104	Serge	9238	DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
3746	Serge	9239	set->crtc->base.id, ret);
3031	serge	9240	fail:
		9241	intel_set_config_restore_state(dev, config);
		9242
		9243	/* Try to restore the config */
		9244	if (config->mode_changed &&
3480	Serge	9245	intel_set_mode(save_set.crtc, save_set.mode,
3031	serge	9246	save_set.x, save_set.y, save_set.fb))
		9247	DRM_ERROR("failed to restore config after modeset failure\n");
3746	Serge	9248	}
3031	serge	9249
		9250	out_config:
		9251	intel_set_config_free(config);
		9252	return ret;
		9253	}
		9254
2330	Serge	9255	static const struct drm_crtc_funcs intel_crtc_funcs = {
		9256	// .cursor_set = intel_crtc_cursor_set,
		9257	// .cursor_move = intel_crtc_cursor_move,
		9258	.gamma_set = intel_crtc_gamma_set,
3031	serge	9259	.set_config = intel_crtc_set_config,
2330	Serge	9260	.destroy = intel_crtc_destroy,
		9261	// .page_flip = intel_crtc_page_flip,
		9262	};
2327	Serge	9263
3243	Serge	9264	static void intel_cpu_pll_init(struct drm_device *dev)
		9265	{
3480	Serge	9266	if (HAS_DDI(dev))
3243	Serge	9267	intel_ddi_pll_init(dev);
		9268	}
		9269
4104	Serge	9270	static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
		9271	struct intel_shared_dpll *pll,
		9272	struct intel_dpll_hw_state *hw_state)
3031	serge	9273	{
4104	Serge	9274	uint32_t val;
3031	serge	9275
4104	Serge	9276	val = I915_READ(PCH_DPLL(pll->id));
		9277	hw_state->dpll = val;
		9278	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
		9279	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
		9280
		9281	return val & DPLL_VCO_ENABLE;
		9282	}
		9283
		9284	static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
		9285	struct intel_shared_dpll *pll)
		9286	{
		9287	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
		9288	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
		9289	}
		9290
		9291	static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
		9292	struct intel_shared_dpll *pll)
		9293	{
		9294	/* PCH refclock must be enabled first */
		9295	assert_pch_refclk_enabled(dev_priv);
		9296
		9297	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		9298
		9299	/* Wait for the clocks to stabilize. */
		9300	POSTING_READ(PCH_DPLL(pll->id));
		9301	udelay(150);
		9302
		9303	/* The pixel multiplier can only be updated once the
		9304	* DPLL is enabled and the clocks are stable.
		9305	*
		9306	* So write it again.
		9307	*/
		9308	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		9309	POSTING_READ(PCH_DPLL(pll->id));
		9310	udelay(200);
		9311	}
		9312
		9313	static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
		9314	struct intel_shared_dpll *pll)
		9315	{
		9316	struct drm_device *dev = dev_priv->dev;
		9317	struct intel_crtc *crtc;
		9318
		9319	/* Make sure no transcoder isn't still depending on us. */
		9320	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
		9321	if (intel_crtc_to_shared_dpll(crtc) == pll)
		9322	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
3031	serge	9323	}
		9324
4104	Serge	9325	I915_WRITE(PCH_DPLL(pll->id), 0);
		9326	POSTING_READ(PCH_DPLL(pll->id));
		9327	udelay(200);
		9328	}
		9329
		9330	static char *ibx_pch_dpll_names[] = {
		9331	"PCH DPLL A",
		9332	"PCH DPLL B",
		9333	};
		9334
		9335	static void ibx_pch_dpll_init(struct drm_device *dev)
		9336	{
		9337	struct drm_i915_private *dev_priv = dev->dev_private;
		9338	int i;
		9339
		9340	dev_priv->num_shared_dpll = 2;
		9341
		9342	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		9343	dev_priv->shared_dplls[i].id = i;
		9344	dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
		9345	dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
		9346	dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
		9347	dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
		9348	dev_priv->shared_dplls[i].get_hw_state =
		9349	ibx_pch_dpll_get_hw_state;
3031	serge	9350	}
		9351	}
		9352
4104	Serge	9353	static void intel_shared_dpll_init(struct drm_device *dev)
		9354	{
		9355	struct drm_i915_private *dev_priv = dev->dev_private;
		9356
		9357	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		9358	ibx_pch_dpll_init(dev);
		9359	else
		9360	dev_priv->num_shared_dpll = 0;
		9361
		9362	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
		9363	DRM_DEBUG_KMS("%i shared PLLs initialized\n",
		9364	dev_priv->num_shared_dpll);
		9365	}
		9366
2330	Serge	9367	static void intel_crtc_init(struct drm_device *dev, int pipe)
		9368	{
		9369	drm_i915_private_t *dev_priv = dev->dev_private;
		9370	struct intel_crtc *intel_crtc;
		9371	int i;
2327	Serge	9372
2330	Serge	9373	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		9374	if (intel_crtc == NULL)
		9375	return;
2327	Serge	9376
2330	Serge	9377	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	9378
2330	Serge	9379	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		9380	for (i = 0; i < 256; i++) {
		9381	intel_crtc->lut_r[i] = i;
		9382	intel_crtc->lut_g[i] = i;
		9383	intel_crtc->lut_b[i] = i;
		9384	}
2327	Serge	9385
2330	Serge	9386	/* Swap pipes & planes for FBC on pre-965 */
		9387	intel_crtc->pipe = pipe;
		9388	intel_crtc->plane = pipe;
		9389	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		9390	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		9391	intel_crtc->plane = !pipe;
		9392	}
2327	Serge	9393
2330	Serge	9394	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		9395	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		9396	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		9397	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	9398
2330	Serge	9399	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
		9400	}
2327	Serge	9401
3031	serge	9402	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		9403	struct drm_file *file)
		9404	{
		9405	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
		9406	struct drm_mode_object *drmmode_obj;
		9407	struct intel_crtc *crtc;
2327	Serge	9408
3482	Serge	9409	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		9410	return -ENODEV;
		9411
3031	serge	9412	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
		9413	DRM_MODE_OBJECT_CRTC);
2327	Serge	9414
3031	serge	9415	if (!drmmode_obj) {
		9416	DRM_ERROR("no such CRTC id\n");
		9417	return -EINVAL;
		9418	}
2327	Serge	9419
3031	serge	9420	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
		9421	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	9422
3031	serge	9423	return 0;
		9424	}
2327	Serge	9425
3031	serge	9426	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	9427	{
3031	serge	9428	struct drm_device *dev = encoder->base.dev;
		9429	struct intel_encoder *source_encoder;
2330	Serge	9430	int index_mask = 0;
		9431	int entry = 0;
2327	Serge	9432
3031	serge	9433	list_for_each_entry(source_encoder,
		9434	&dev->mode_config.encoder_list, base.head) {
		9435
		9436	if (encoder == source_encoder)
2330	Serge	9437	index_mask \|= (1 << entry);
3031	serge	9438
		9439	/* Intel hw has only one MUX where enocoders could be cloned. */
		9440	if (encoder->cloneable && source_encoder->cloneable)
		9441	index_mask \|= (1 << entry);
		9442
2330	Serge	9443	entry++;
		9444	}
2327	Serge	9445
2330	Serge	9446	return index_mask;
		9447	}
2327	Serge	9448
2330	Serge	9449	static bool has_edp_a(struct drm_device *dev)
		9450	{
		9451	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9452
2330	Serge	9453	if (!IS_MOBILE(dev))
		9454	return false;
2327	Serge	9455
2330	Serge	9456	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		9457	return false;
2327	Serge	9458
2330	Serge	9459	if (IS_GEN5(dev) &&
		9460	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		9461	return false;
2327	Serge	9462
2330	Serge	9463	return true;
		9464	}
2327	Serge	9465
2330	Serge	9466	static void intel_setup_outputs(struct drm_device *dev)
		9467	{
		9468	struct drm_i915_private *dev_priv = dev->dev_private;
		9469	struct intel_encoder *encoder;
		9470	bool dpd_is_edp = false;
2327	Serge	9471
4104	Serge	9472	intel_lvds_init(dev);
2327	Serge	9473
3746	Serge	9474	if (!IS_ULT(dev))
2330	Serge	9475	intel_crt_init(dev);
2327	Serge	9476
3480	Serge	9477	if (HAS_DDI(dev)) {
2330	Serge	9478	int found;
2327	Serge	9479
3031	serge	9480	/* Haswell uses DDI functions to detect digital outputs */
		9481	found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		9482	/* DDI A only supports eDP */
		9483	if (found)
		9484	intel_ddi_init(dev, PORT_A);
		9485
		9486	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		9487	* register */
		9488	found = I915_READ(SFUSE_STRAP);
		9489
		9490	if (found & SFUSE_STRAP_DDIB_DETECTED)
		9491	intel_ddi_init(dev, PORT_B);
		9492	if (found & SFUSE_STRAP_DDIC_DETECTED)
		9493	intel_ddi_init(dev, PORT_C);
		9494	if (found & SFUSE_STRAP_DDID_DETECTED)
		9495	intel_ddi_init(dev, PORT_D);
		9496	} else if (HAS_PCH_SPLIT(dev)) {
		9497	int found;
3243	Serge	9498	dpd_is_edp = intel_dpd_is_edp(dev);
3031	serge	9499
3243	Serge	9500	if (has_edp_a(dev))
		9501	intel_dp_init(dev, DP_A, PORT_A);
		9502
3746	Serge	9503	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
2330	Serge	9504	/* PCH SDVOB multiplex with HDMIB */
3031	serge	9505	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	9506	if (!found)
3746	Serge	9507	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
2330	Serge	9508	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	9509	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	9510	}
2327	Serge	9511
3746	Serge	9512	if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
		9513	intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
2327	Serge	9514
3746	Serge	9515	if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
		9516	intel_hdmi_init(dev, PCH_HDMID, PORT_D);
2327	Serge	9517
2330	Serge	9518	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	9519	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	9520
3243	Serge	9521	if (I915_READ(PCH_DP_D) & DP_DETECTED)
3031	serge	9522	intel_dp_init(dev, PCH_DP_D, PORT_D);
		9523	} else if (IS_VALLEYVIEW(dev)) {
3243	Serge	9524	/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
4104	Serge	9525	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
		9526	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
		9527	PORT_C);
3480	Serge	9528	if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
4104	Serge	9529	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
		9530	PORT_C);
		9531	}
3243	Serge	9532
3746	Serge	9533	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
		9534	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
		9535	PORT_B);
3480	Serge	9536	if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
		9537	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
3031	serge	9538	}
2330	Serge	9539	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		9540	bool found = false;
2327	Serge	9541
3746	Serge	9542	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	9543	DRM_DEBUG_KMS("probing SDVOB\n");
3746	Serge	9544	found = intel_sdvo_init(dev, GEN3_SDVOB, true);
2330	Serge	9545	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		9546	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3746	Serge	9547	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
2330	Serge	9548	}
2327	Serge	9549
4104	Serge	9550	if (!found && SUPPORTS_INTEGRATED_DP(dev))
3031	serge	9551	intel_dp_init(dev, DP_B, PORT_B);
2330	Serge	9552	}
2327	Serge	9553
2330	Serge	9554	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	9555
3746	Serge	9556	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	9557	DRM_DEBUG_KMS("probing SDVOC\n");
3746	Serge	9558	found = intel_sdvo_init(dev, GEN3_SDVOC, false);
2330	Serge	9559	}
2327	Serge	9560
3746	Serge	9561	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
2327	Serge	9562
2330	Serge	9563	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		9564	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3746	Serge	9565	intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
2330	Serge	9566	}
4104	Serge	9567	if (SUPPORTS_INTEGRATED_DP(dev))
3031	serge	9568	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	9569	}
2327	Serge	9570
2330	Serge	9571	if (SUPPORTS_INTEGRATED_DP(dev) &&
4104	Serge	9572	(I915_READ(DP_D) & DP_DETECTED))
3031	serge	9573	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	9574	} else if (IS_GEN2(dev))
		9575	intel_dvo_init(dev);
2327	Serge	9576
2330	Serge	9577	// if (SUPPORTS_TV(dev))
		9578	// intel_tv_init(dev);
2327	Serge	9579
2330	Serge	9580	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		9581	encoder->base.possible_crtcs = encoder->crtc_mask;
		9582	encoder->base.possible_clones =
3031	serge	9583	intel_encoder_clones(encoder);
2330	Serge	9584	}
2327	Serge	9585
3243	Serge	9586	intel_init_pch_refclk(dev);
		9587
		9588	drm_helper_move_panel_connectors_to_head(dev);
2330	Serge	9589	}
		9590
		9591
		9592
2335	Serge	9593	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		9594	// .destroy = intel_user_framebuffer_destroy,
		9595	// .create_handle = intel_user_framebuffer_create_handle,
		9596	};
2327	Serge	9597
2335	Serge	9598	int intel_framebuffer_init(struct drm_device *dev,
		9599	struct intel_framebuffer *intel_fb,
2342	Serge	9600	struct drm_mode_fb_cmd2 *mode_cmd,
2335	Serge	9601	struct drm_i915_gem_object *obj)
		9602	{
4104	Serge	9603	int pitch_limit;
2335	Serge	9604	int ret;
2327	Serge	9605
3243	Serge	9606	if (obj->tiling_mode == I915_TILING_Y) {
		9607	DRM_DEBUG("hardware does not support tiling Y\n");
2335	Serge	9608	return -EINVAL;
3243	Serge	9609	}
2327	Serge	9610
3243	Serge	9611	if (mode_cmd->pitches[0] & 63) {
		9612	DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
		9613	mode_cmd->pitches[0]);
		9614	return -EINVAL;
		9615	}
		9616
4104	Serge	9617	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
		9618	pitch_limit = 32*1024;
		9619	} else if (INTEL_INFO(dev)->gen >= 4) {
		9620	if (obj->tiling_mode)
		9621	pitch_limit = 16*1024;
		9622	else
		9623	pitch_limit = 32*1024;
		9624	} else if (INTEL_INFO(dev)->gen >= 3) {
		9625	if (obj->tiling_mode)
		9626	pitch_limit = 8*1024;
		9627	else
		9628	pitch_limit = 16*1024;
		9629	} else
		9630	/* XXX DSPC is limited to 4k tiled */
		9631	pitch_limit = 8*1024;
		9632
		9633	if (mode_cmd->pitches[0] > pitch_limit) {
		9634	DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
		9635	obj->tiling_mode ? "tiled" : "linear",
		9636	mode_cmd->pitches[0], pitch_limit);
3243	Serge	9637	return -EINVAL;
		9638	}
		9639
		9640	if (obj->tiling_mode != I915_TILING_NONE &&
		9641	mode_cmd->pitches[0] != obj->stride) {
		9642	DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
		9643	mode_cmd->pitches[0], obj->stride);
2335	Serge	9644	return -EINVAL;
3243	Serge	9645	}
2327	Serge	9646
3243	Serge	9647	/* Reject formats not supported by any plane early. */
2342	Serge	9648	switch (mode_cmd->pixel_format) {
3243	Serge	9649	case DRM_FORMAT_C8:
2342	Serge	9650	case DRM_FORMAT_RGB565:
		9651	case DRM_FORMAT_XRGB8888:
3243	Serge	9652	case DRM_FORMAT_ARGB8888:
		9653	break;
		9654	case DRM_FORMAT_XRGB1555:
		9655	case DRM_FORMAT_ARGB1555:
		9656	if (INTEL_INFO(dev)->gen > 3) {
4104	Serge	9657	DRM_DEBUG("unsupported pixel format: %s\n",
		9658	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9659	return -EINVAL;
		9660	}
		9661	break;
3031	serge	9662	case DRM_FORMAT_XBGR8888:
3243	Serge	9663	case DRM_FORMAT_ABGR8888:
2342	Serge	9664	case DRM_FORMAT_XRGB2101010:
		9665	case DRM_FORMAT_ARGB2101010:
3243	Serge	9666	case DRM_FORMAT_XBGR2101010:
		9667	case DRM_FORMAT_ABGR2101010:
		9668	if (INTEL_INFO(dev)->gen < 4) {
4104	Serge	9669	DRM_DEBUG("unsupported pixel format: %s\n",
		9670	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9671	return -EINVAL;
		9672	}
2335	Serge	9673	break;
2342	Serge	9674	case DRM_FORMAT_YUYV:
		9675	case DRM_FORMAT_UYVY:
		9676	case DRM_FORMAT_YVYU:
		9677	case DRM_FORMAT_VYUY:
3243	Serge	9678	if (INTEL_INFO(dev)->gen < 5) {
4104	Serge	9679	DRM_DEBUG("unsupported pixel format: %s\n",
		9680	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9681	return -EINVAL;
		9682	}
2342	Serge	9683	break;
2335	Serge	9684	default:
4104	Serge	9685	DRM_DEBUG("unsupported pixel format: %s\n",
		9686	drm_get_format_name(mode_cmd->pixel_format));
2335	Serge	9687	return -EINVAL;
		9688	}
2327	Serge	9689
3243	Serge	9690	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
		9691	if (mode_cmd->offsets[0] != 0)
		9692	return -EINVAL;
		9693
3480	Serge	9694	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		9695	intel_fb->obj = obj;
		9696
2335	Serge	9697	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		9698	if (ret) {
		9699	DRM_ERROR("framebuffer init failed %d\n", ret);
		9700	return ret;
		9701	}
2327	Serge	9702
2335	Serge	9703	return 0;
		9704	}
2327	Serge	9705
		9706
2360	Serge	9707	static const struct drm_mode_config_funcs intel_mode_funcs = {
		9708	.fb_create = NULL /intel_user_framebuffer_create/,
3480	Serge	9709	.output_poll_changed = intel_fb_output_poll_changed,
2360	Serge	9710	};
2327	Serge	9711
3031	serge	9712	/* Set up chip specific display functions */
		9713	static void intel_init_display(struct drm_device *dev)
		9714	{
		9715	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9716
4104	Serge	9717	if (HAS_PCH_SPLIT(dev) \|\| IS_G4X(dev))
		9718	dev_priv->display.find_dpll = g4x_find_best_dpll;
		9719	else if (IS_VALLEYVIEW(dev))
		9720	dev_priv->display.find_dpll = vlv_find_best_dpll;
		9721	else if (IS_PINEVIEW(dev))
		9722	dev_priv->display.find_dpll = pnv_find_best_dpll;
		9723	else
		9724	dev_priv->display.find_dpll = i9xx_find_best_dpll;
		9725
3480	Serge	9726	if (HAS_DDI(dev)) {
3746	Serge	9727	dev_priv->display.get_pipe_config = haswell_get_pipe_config;
3243	Serge	9728	dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
		9729	dev_priv->display.crtc_enable = haswell_crtc_enable;
		9730	dev_priv->display.crtc_disable = haswell_crtc_disable;
		9731	dev_priv->display.off = haswell_crtc_off;
		9732	dev_priv->display.update_plane = ironlake_update_plane;
		9733	} else if (HAS_PCH_SPLIT(dev)) {
3746	Serge	9734	dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
4104	Serge	9735	dev_priv->display.get_clock = ironlake_crtc_clock_get;
3031	serge	9736	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		9737	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		9738	dev_priv->display.crtc_disable = ironlake_crtc_disable;
		9739	dev_priv->display.off = ironlake_crtc_off;
		9740	dev_priv->display.update_plane = ironlake_update_plane;
4104	Serge	9741	} else if (IS_VALLEYVIEW(dev)) {
		9742	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
		9743	dev_priv->display.get_clock = i9xx_crtc_clock_get;
		9744	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		9745	dev_priv->display.crtc_enable = valleyview_crtc_enable;
		9746	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		9747	dev_priv->display.off = i9xx_crtc_off;
		9748	dev_priv->display.update_plane = i9xx_update_plane;
3031	serge	9749	} else {
3746	Serge	9750	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
4104	Serge	9751	dev_priv->display.get_clock = i9xx_crtc_clock_get;
3031	serge	9752	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		9753	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		9754	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		9755	dev_priv->display.off = i9xx_crtc_off;
		9756	dev_priv->display.update_plane = i9xx_update_plane;
		9757	}
2327	Serge	9758
3031	serge	9759	/* Returns the core display clock speed */
		9760	if (IS_VALLEYVIEW(dev))
		9761	dev_priv->display.get_display_clock_speed =
		9762	valleyview_get_display_clock_speed;
		9763	else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		9764	dev_priv->display.get_display_clock_speed =
		9765	i945_get_display_clock_speed;
		9766	else if (IS_I915G(dev))
		9767	dev_priv->display.get_display_clock_speed =
		9768	i915_get_display_clock_speed;
4104	Serge	9769	else if (IS_I945GM(dev) \|\| IS_845G(dev))
3031	serge	9770	dev_priv->display.get_display_clock_speed =
		9771	i9xx_misc_get_display_clock_speed;
4104	Serge	9772	else if (IS_PINEVIEW(dev))
		9773	dev_priv->display.get_display_clock_speed =
		9774	pnv_get_display_clock_speed;
3031	serge	9775	else if (IS_I915GM(dev))
		9776	dev_priv->display.get_display_clock_speed =
		9777	i915gm_get_display_clock_speed;
		9778	else if (IS_I865G(dev))
		9779	dev_priv->display.get_display_clock_speed =
		9780	i865_get_display_clock_speed;
		9781	else if (IS_I85X(dev))
		9782	dev_priv->display.get_display_clock_speed =
		9783	i855_get_display_clock_speed;
		9784	else /* 852, 830 */
		9785	dev_priv->display.get_display_clock_speed =
		9786	i830_get_display_clock_speed;
2327	Serge	9787
3031	serge	9788	if (HAS_PCH_SPLIT(dev)) {
		9789	if (IS_GEN5(dev)) {
		9790	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		9791	dev_priv->display.write_eld = ironlake_write_eld;
		9792	} else if (IS_GEN6(dev)) {
		9793	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		9794	dev_priv->display.write_eld = ironlake_write_eld;
		9795	} else if (IS_IVYBRIDGE(dev)) {
		9796	/* FIXME: detect B0+ stepping and use auto training */
		9797	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		9798	dev_priv->display.write_eld = ironlake_write_eld;
3243	Serge	9799	dev_priv->display.modeset_global_resources =
		9800	ivb_modeset_global_resources;
3031	serge	9801	} else if (IS_HASWELL(dev)) {
		9802	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		9803	dev_priv->display.write_eld = haswell_write_eld;
3480	Serge	9804	dev_priv->display.modeset_global_resources =
		9805	haswell_modeset_global_resources;
		9806	}
3031	serge	9807	} else if (IS_G4X(dev)) {
		9808	dev_priv->display.write_eld = g4x_write_eld;
		9809	}
2327	Serge	9810
3031	serge	9811	/* Default just returns -ENODEV to indicate unsupported */
		9812	// dev_priv->display.queue_flip = intel_default_queue_flip;
2327	Serge	9813
		9814
		9815
		9816
3031	serge	9817	}
		9818
		9819	/*
		9820	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		9821	* resume, or other times. This quirk makes sure that's the case for
		9822	* affected systems.
		9823	*/
		9824	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	9825	{
		9826	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9827
3031	serge	9828	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		9829	DRM_INFO("applying pipe a force quirk\n");
		9830	}
2327	Serge	9831
3031	serge	9832	/*
		9833	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		9834	*/
		9835	static void quirk_ssc_force_disable(struct drm_device *dev)
		9836	{
		9837	struct drm_i915_private *dev_priv = dev->dev_private;
		9838	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		9839	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	9840	}
2327	Serge	9841
3031	serge	9842	/*
		9843	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		9844	* brightness value
		9845	*/
		9846	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	9847	{
		9848	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9849	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		9850	DRM_INFO("applying inverted panel brightness quirk\n");
		9851	}
2327	Serge	9852
4104	Serge	9853	/*
		9854	* Some machines (Dell XPS13) suffer broken backlight controls if
		9855	* BLM_PCH_PWM_ENABLE is set.
		9856	*/
		9857	static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
		9858	{
		9859	struct drm_i915_private *dev_priv = dev->dev_private;
		9860	dev_priv->quirks \|= QUIRK_NO_PCH_PWM_ENABLE;
		9861	DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
		9862	}
		9863
3031	serge	9864	struct intel_quirk {
		9865	int device;
		9866	int subsystem_vendor;
		9867	int subsystem_device;
		9868	void (hook)(struct drm_device dev);
		9869	};
2327	Serge	9870
3031	serge	9871	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		9872	struct intel_dmi_quirk {
		9873	void (hook)(struct drm_device dev);
		9874	const struct dmi_system_id (*dmi_id_list)[];
		9875	};
2327	Serge	9876
3031	serge	9877	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		9878	{
		9879	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		9880	return 1;
2330	Serge	9881	}
2327	Serge	9882
3031	serge	9883	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		9884	{
		9885	.dmi_id_list = &(const struct dmi_system_id[]) {
		9886	{
		9887	.callback = intel_dmi_reverse_brightness,
		9888	.ident = "NCR Corporation",
		9889	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		9890	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		9891	},
		9892	},
		9893	{ } /* terminating entry */
		9894	},
		9895	.hook = quirk_invert_brightness,
		9896	},
		9897	};
2327	Serge	9898
3031	serge	9899	static struct intel_quirk intel_quirks[] = {
		9900	/* HP Mini needs pipe A force quirk (LP: #322104) */
		9901	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327	Serge	9902
3031	serge	9903	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		9904	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	9905
3031	serge	9906	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		9907	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	9908
3031	serge	9909	/* 830/845 need to leave pipe A & dpll A up */
		9910	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		9911	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
2327	Serge	9912
3031	serge	9913	/* Lenovo U160 cannot use SSC on LVDS */
		9914	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	9915
3031	serge	9916	/* Sony Vaio Y cannot use SSC on LVDS */
		9917	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	9918
3031	serge	9919	/* Acer Aspire 5734Z must invert backlight brightness */
		9920	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
3480	Serge	9921
		9922	/* Acer/eMachines G725 */
		9923	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
		9924
		9925	/* Acer/eMachines e725 */
		9926	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
		9927
		9928	/* Acer/Packard Bell NCL20 */
		9929	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
		9930
		9931	/* Acer Aspire 4736Z */
		9932	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
4104	Serge	9933
		9934	/* Dell XPS13 HD Sandy Bridge */
		9935	{ 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
		9936	/* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
		9937	{ 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
3031	serge	9938	};
2327	Serge	9939
3031	serge	9940	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	9941	{
3031	serge	9942	struct pci_dev *d = dev->pdev;
		9943	int i;
2327	Serge	9944
3031	serge	9945	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		9946	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	9947
3031	serge	9948	if (d->device == q->device &&
		9949	(d->subsystem_vendor == q->subsystem_vendor \|\|
		9950	q->subsystem_vendor == PCI_ANY_ID) &&
		9951	(d->subsystem_device == q->subsystem_device \|\|
		9952	q->subsystem_device == PCI_ANY_ID))
		9953	q->hook(dev);
		9954	}
		9955	// for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
		9956	// if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
		9957	// intel_dmi_quirks[i].hook(dev);
		9958	// }
2330	Serge	9959	}
2327	Serge	9960
3031	serge	9961	/* Disable the VGA plane that we never use */
		9962	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	9963	{
		9964	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9965	u8 sr1;
3480	Serge	9966	u32 vga_reg = i915_vgacntrl_reg(dev);
2327	Serge	9967
3031	serge	9968	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		9969	out8(SR01, VGA_SR_INDEX);
		9970	sr1 = in8(VGA_SR_DATA);
		9971	out8(sr1 \| 1<<5, VGA_SR_DATA);
		9972	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		9973	udelay(300);
2327	Serge	9974
3031	serge	9975	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		9976	POSTING_READ(vga_reg);
2330	Serge	9977	}
		9978
3031	serge	9979	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	9980	{
3480	Serge	9981	intel_init_power_well(dev);
2342	Serge	9982
3031	serge	9983	intel_prepare_ddi(dev);
2342	Serge	9984
3031	serge	9985	intel_init_clock_gating(dev);
		9986
3482	Serge	9987	mutex_lock(&dev->struct_mutex);
		9988	intel_enable_gt_powersave(dev);
		9989	mutex_unlock(&dev->struct_mutex);
2342	Serge	9990	}
		9991
3031	serge	9992	void intel_modeset_init(struct drm_device *dev)
2330	Serge	9993	{
3031	serge	9994	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	9995	int i, j, ret;
2330	Serge	9996
3031	serge	9997	drm_mode_config_init(dev);
2330	Serge	9998
3031	serge	9999	dev->mode_config.min_width = 0;
		10000	dev->mode_config.min_height = 0;
2330	Serge	10001
3031	serge	10002	dev->mode_config.preferred_depth = 24;
		10003	dev->mode_config.prefer_shadow = 1;
2330	Serge	10004
3031	serge	10005	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	10006
3031	serge	10007	intel_init_quirks(dev);
2330	Serge	10008
3031	serge	10009	intel_init_pm(dev);
2330	Serge	10010
3746	Serge	10011	if (INTEL_INFO(dev)->num_pipes == 0)
		10012	return;
		10013
3031	serge	10014	intel_init_display(dev);
2330	Serge	10015
3031	serge	10016	if (IS_GEN2(dev)) {
		10017	dev->mode_config.max_width = 2048;
		10018	dev->mode_config.max_height = 2048;
		10019	} else if (IS_GEN3(dev)) {
		10020	dev->mode_config.max_width = 4096;
		10021	dev->mode_config.max_height = 4096;
		10022	} else {
		10023	dev->mode_config.max_width = 8192;
		10024	dev->mode_config.max_height = 8192;
		10025	}
3480	Serge	10026	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
2330	Serge	10027
3031	serge	10028	DRM_DEBUG_KMS("%d display pipe%s available.\n",
3746	Serge	10029	INTEL_INFO(dev)->num_pipes,
		10030	INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
2330	Serge	10031
4104	Serge	10032	for_each_pipe(i) {
3031	serge	10033	intel_crtc_init(dev, i);
3746	Serge	10034	for (j = 0; j < dev_priv->num_plane; j++) {
		10035	ret = intel_plane_init(dev, i, j);
3031	serge	10036	if (ret)
4104	Serge	10037	DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
		10038	pipe_name(i), sprite_name(i, j), ret);
3746	Serge	10039	}
2330	Serge	10040	}
		10041
3243	Serge	10042	intel_cpu_pll_init(dev);
4104	Serge	10043	intel_shared_dpll_init(dev);
2330	Serge	10044
3031	serge	10045	/* Just disable it once at startup */
		10046	i915_disable_vga(dev);
		10047	intel_setup_outputs(dev);
3480	Serge	10048
		10049	/* Just in case the BIOS is doing something questionable. */
		10050	intel_disable_fbc(dev);
3031	serge	10051	}
2330	Serge	10052
3031	serge	10053	static void
		10054	intel_connector_break_all_links(struct intel_connector *connector)
		10055	{
		10056	connector->base.dpms = DRM_MODE_DPMS_OFF;
		10057	connector->base.encoder = NULL;
		10058	connector->encoder->connectors_active = false;
		10059	connector->encoder->base.crtc = NULL;
2330	Serge	10060	}
		10061
3031	serge	10062	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	10063	{
3031	serge	10064	struct intel_connector *connector;
		10065	struct drm_connector *crt = NULL;
		10066	struct intel_load_detect_pipe load_detect_temp;
2330	Serge	10067
3031	serge	10068	/* We can't just switch on the pipe A, we need to set things up with a
		10069	* proper mode and output configuration. As a gross hack, enable pipe A
		10070	* by enabling the load detect pipe once. */
		10071	list_for_each_entry(connector,
		10072	&dev->mode_config.connector_list,
		10073	base.head) {
		10074	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		10075	crt = &connector->base;
		10076	break;
2330	Serge	10077	}
		10078	}
		10079
3031	serge	10080	if (!crt)
		10081	return;
2330	Serge	10082
3031	serge	10083	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		10084	intel_release_load_detect_pipe(crt, &load_detect_temp);
2327	Serge	10085
		10086
		10087	}
		10088
3031	serge	10089	static bool
		10090	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	10091	{
3746	Serge	10092	struct drm_device *dev = crtc->base.dev;
		10093	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10094	u32 reg, val;
2327	Serge	10095
3746	Serge	10096	if (INTEL_INFO(dev)->num_pipes == 1)
3031	serge	10097	return true;
2327	Serge	10098
3031	serge	10099	reg = DSPCNTR(!crtc->plane);
		10100	val = I915_READ(reg);
2327	Serge	10101
3031	serge	10102	if ((val & DISPLAY_PLANE_ENABLE) &&
		10103	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		10104	return false;
2327	Serge	10105
3031	serge	10106	return true;
2327	Serge	10107	}
		10108
3031	serge	10109	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	10110	{
3031	serge	10111	struct drm_device *dev = crtc->base.dev;
2327	Serge	10112	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10113	u32 reg;
2327	Serge	10114
3031	serge	10115	/* Clear any frame start delays used for debugging left by the BIOS */
3746	Serge	10116	reg = PIPECONF(crtc->config.cpu_transcoder);
3031	serge	10117	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	10118
3031	serge	10119	/* We need to sanitize the plane -> pipe mapping first because this will
		10120	* disable the crtc (and hence change the state) if it is wrong. Note
		10121	* that gen4+ has a fixed plane -> pipe mapping. */
		10122	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		10123	struct intel_connector *connector;
		10124	bool plane;
2327	Serge	10125
3031	serge	10126	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		10127	crtc->base.base.id);
2327	Serge	10128
3031	serge	10129	/* Pipe has the wrong plane attached and the plane is active.
		10130	* Temporarily change the plane mapping and disable everything
		10131	* ... */
		10132	plane = crtc->plane;
		10133	crtc->plane = !plane;
		10134	dev_priv->display.crtc_disable(&crtc->base);
		10135	crtc->plane = plane;
2342	Serge	10136
3031	serge	10137	/* ... and break all links. */
		10138	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10139	base.head) {
		10140	if (connector->encoder->base.crtc != &crtc->base)
		10141	continue;
2327	Serge	10142
3031	serge	10143	intel_connector_break_all_links(connector);
		10144	}
2327	Serge	10145
3031	serge	10146	WARN_ON(crtc->active);
		10147	crtc->base.enabled = false;
		10148	}
2327	Serge	10149
3031	serge	10150	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		10151	crtc->pipe == PIPE_A && !crtc->active) {
		10152	/* BIOS forgot to enable pipe A, this mostly happens after
		10153	* resume. Force-enable the pipe to fix this, the update_dpms
		10154	* call below we restore the pipe to the right state, but leave
		10155	* the required bits on. */
		10156	intel_enable_pipe_a(dev);
		10157	}
2327	Serge	10158
3031	serge	10159	/* Adjust the state of the output pipe according to whether we
		10160	* have active connectors/encoders. */
		10161	intel_crtc_update_dpms(&crtc->base);
2327	Serge	10162
3031	serge	10163	if (crtc->active != crtc->base.enabled) {
		10164	struct intel_encoder *encoder;
2327	Serge	10165
3031	serge	10166	/* This can happen either due to bugs in the get_hw_state
		10167	* functions or because the pipe is force-enabled due to the
		10168	* pipe A quirk. */
		10169	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		10170	crtc->base.base.id,
		10171	crtc->base.enabled ? "enabled" : "disabled",
		10172	crtc->active ? "enabled" : "disabled");
2327	Serge	10173
3031	serge	10174	crtc->base.enabled = crtc->active;
2327	Serge	10175
3031	serge	10176	/* Because we only establish the connector -> encoder ->
		10177	* crtc links if something is active, this means the
		10178	* crtc is now deactivated. Break the links. connector
		10179	* -> encoder links are only establish when things are
		10180	* actually up, hence no need to break them. */
		10181	WARN_ON(crtc->active);
2327	Serge	10182
3031	serge	10183	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		10184	WARN_ON(encoder->connectors_active);
		10185	encoder->base.crtc = NULL;
		10186	}
		10187	}
2327	Serge	10188	}
		10189
3031	serge	10190	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	10191	{
3031	serge	10192	struct intel_connector *connector;
		10193	struct drm_device *dev = encoder->base.dev;
2327	Serge	10194
3031	serge	10195	/* We need to check both for a crtc link (meaning that the
		10196	* encoder is active and trying to read from a pipe) and the
		10197	* pipe itself being active. */
		10198	bool has_active_crtc = encoder->base.crtc &&
		10199	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	10200
3031	serge	10201	if (encoder->connectors_active && !has_active_crtc) {
		10202	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		10203	encoder->base.base.id,
		10204	drm_get_encoder_name(&encoder->base));
2327	Serge	10205
3031	serge	10206	/* Connector is active, but has no active pipe. This is
		10207	* fallout from our resume register restoring. Disable
		10208	* the encoder manually again. */
		10209	if (encoder->base.crtc) {
		10210	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		10211	encoder->base.base.id,
		10212	drm_get_encoder_name(&encoder->base));
		10213	encoder->disable(encoder);
		10214	}
2327	Serge	10215
3031	serge	10216	/* Inconsistent output/port/pipe state happens presumably due to
		10217	* a bug in one of the get_hw_state functions. Or someplace else
		10218	* in our code, like the register restore mess on resume. Clamp
		10219	* things to off as a safer default. */
		10220	list_for_each_entry(connector,
		10221	&dev->mode_config.connector_list,
		10222	base.head) {
		10223	if (connector->encoder != encoder)
		10224	continue;
2327	Serge	10225
3031	serge	10226	intel_connector_break_all_links(connector);
		10227	}
		10228	}
		10229	/* Enabled encoders without active connectors will be fixed in
		10230	* the crtc fixup. */
2327	Serge	10231	}
		10232
3746	Serge	10233	void i915_redisable_vga(struct drm_device *dev)
		10234	{
		10235	struct drm_i915_private *dev_priv = dev->dev_private;
		10236	u32 vga_reg = i915_vgacntrl_reg(dev);
		10237
4104	Serge	10238	/* This function can be called both from intel_modeset_setup_hw_state or
		10239	* at a very early point in our resume sequence, where the power well
		10240	* structures are not yet restored. Since this function is at a very
		10241	* paranoid "someone might have enabled VGA while we were not looking"
		10242	* level, just check if the power well is enabled instead of trying to
		10243	* follow the "don't touch the power well if we don't need it" policy
		10244	* the rest of the driver uses. */
		10245	if (HAS_POWER_WELL(dev) &&
		10246	(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
		10247	return;
		10248
3746	Serge	10249	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
		10250	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
		10251	i915_disable_vga(dev);
		10252	}
		10253	}
		10254
4104	Serge	10255	static void intel_modeset_readout_hw_state(struct drm_device *dev)
2332	Serge	10256	{
		10257	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10258	enum pipe pipe;
		10259	struct intel_crtc *crtc;
		10260	struct intel_encoder *encoder;
		10261	struct intel_connector *connector;
4104	Serge	10262	int i;
2327	Serge	10263
3746	Serge	10264	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10265	base.head) {
		10266	memset(&crtc->config, 0, sizeof(crtc->config));
2327	Serge	10267
3746	Serge	10268	crtc->active = dev_priv->display.get_pipe_config(crtc,
		10269	&crtc->config);
2327	Serge	10270
3031	serge	10271	crtc->base.enabled = crtc->active;
2330	Serge	10272
3031	serge	10273	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		10274	crtc->base.base.id,
		10275	crtc->active ? "enabled" : "disabled");
2339	Serge	10276	}
2332	Serge	10277
4104	Serge	10278	/* FIXME: Smash this into the new shared dpll infrastructure. */
3480	Serge	10279	if (HAS_DDI(dev))
3243	Serge	10280	intel_ddi_setup_hw_pll_state(dev);
		10281
4104	Serge	10282	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10283	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10284
		10285	pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
		10286	pll->active = 0;
		10287	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10288	base.head) {
		10289	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		10290	pll->active++;
		10291	}
		10292	pll->refcount = pll->active;
		10293
		10294	DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
		10295	pll->name, pll->refcount, pll->on);
		10296	}
		10297
3031	serge	10298	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10299	base.head) {
		10300	pipe = 0;
2332	Serge	10301
3031	serge	10302	if (encoder->get_hw_state(encoder, &pipe)) {
4104	Serge	10303	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		10304	encoder->base.crtc = &crtc->base;
		10305	if (encoder->get_config)
		10306	encoder->get_config(encoder, &crtc->config);
3031	serge	10307	} else {
		10308	encoder->base.crtc = NULL;
		10309	}
2332	Serge	10310
3031	serge	10311	encoder->connectors_active = false;
		10312	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
		10313	encoder->base.base.id,
		10314	drm_get_encoder_name(&encoder->base),
		10315	encoder->base.crtc ? "enabled" : "disabled",
		10316	pipe);
		10317	}
2332	Serge	10318
4104	Serge	10319	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10320	base.head) {
		10321	if (!crtc->active)
		10322	continue;
		10323	if (dev_priv->display.get_clock)
		10324	dev_priv->display.get_clock(crtc,
		10325	&crtc->config);
		10326	}
		10327
3031	serge	10328	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10329	base.head) {
		10330	if (connector->get_hw_state(connector)) {
		10331	connector->base.dpms = DRM_MODE_DPMS_ON;
		10332	connector->encoder->connectors_active = true;
		10333	connector->base.encoder = &connector->encoder->base;
		10334	} else {
		10335	connector->base.dpms = DRM_MODE_DPMS_OFF;
		10336	connector->base.encoder = NULL;
		10337	}
		10338	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		10339	connector->base.base.id,
		10340	drm_get_connector_name(&connector->base),
		10341	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	10342	}
4104	Serge	10343	}
2332	Serge	10344
4104	Serge	10345	/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
		10346	* and i915 state tracking structures. */
		10347	void intel_modeset_setup_hw_state(struct drm_device *dev,
		10348	bool force_restore)
		10349	{
		10350	struct drm_i915_private *dev_priv = dev->dev_private;
		10351	enum pipe pipe;
		10352	struct drm_plane *plane;
		10353	struct intel_crtc *crtc;
		10354	struct intel_encoder *encoder;
		10355	int i;
		10356
		10357	intel_modeset_readout_hw_state(dev);
		10358
		10359	/*
		10360	* Now that we have the config, copy it to each CRTC struct
		10361	* Note that this could go away if we move to using crtc_config
		10362	* checking everywhere.
		10363	*/
		10364	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10365	base.head) {
		10366	if (crtc->active && i915_fastboot) {
		10367	intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
		10368
		10369	DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
		10370	crtc->base.base.id);
		10371	drm_mode_debug_printmodeline(&crtc->base.mode);
		10372	}
		10373	}
		10374
3031	serge	10375	/* HW state is read out, now we need to sanitize this mess. */
		10376	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10377	base.head) {
		10378	intel_sanitize_encoder(encoder);
2332	Serge	10379	}
		10380
3031	serge	10381	for_each_pipe(pipe) {
		10382	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		10383	intel_sanitize_crtc(crtc);
4104	Serge	10384	intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
2332	Serge	10385	}
		10386
4104	Serge	10387	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10388	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10389
		10390	if (!pll->on \|\| pll->active)
		10391	continue;
		10392
		10393	DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
		10394
		10395	pll->disable(dev_priv, pll);
		10396	pll->on = false;
		10397	}
		10398
3243	Serge	10399	if (force_restore) {
3746	Serge	10400	/*
		10401	* We need to use raw interfaces for restoring state to avoid
		10402	* checking (bogus) intermediate states.
		10403	*/
3243	Serge	10404	for_each_pipe(pipe) {
3746	Serge	10405	struct drm_crtc *crtc =
		10406	dev_priv->pipe_to_crtc_mapping[pipe];
		10407
		10408	__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
		10409	crtc->fb);
3243	Serge	10410	}
3746	Serge	10411	list_for_each_entry(plane, &dev->mode_config.plane_list, head)
		10412	intel_plane_restore(plane);
3243	Serge	10413
3746	Serge	10414	i915_redisable_vga(dev);
3243	Serge	10415	} else {
3031	serge	10416	intel_modeset_update_staged_output_state(dev);
3243	Serge	10417	}
2332	Serge	10418
3031	serge	10419	intel_modeset_check_state(dev);
3243	Serge	10420
		10421	drm_mode_config_reset(dev);
2332	Serge	10422	}
		10423
3031	serge	10424	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	10425	{
3031	serge	10426	intel_modeset_init_hw(dev);
2330	Serge	10427
3031	serge	10428	// intel_setup_overlay(dev);
2330	Serge	10429
3243	Serge	10430	intel_modeset_setup_hw_state(dev, false);
2330	Serge	10431	}
		10432
3031	serge	10433	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	10434	{
3031	serge	10435	#if 0
		10436	struct drm_i915_private *dev_priv = dev->dev_private;
		10437	struct drm_crtc *crtc;
2327	Serge	10438
4104	Serge	10439	/*
		10440	* Interrupts and polling as the first thing to avoid creating havoc.
		10441	* Too much stuff here (turning of rps, connectors, ...) would
		10442	* experience fancy races otherwise.
		10443	*/
		10444	drm_irq_uninstall(dev);
		10445	cancel_work_sync(&dev_priv->hotplug_work);
		10446	/*
		10447	* Due to the hpd irq storm handling the hotplug work can re-arm the
		10448	* poll handlers. Hence disable polling after hpd handling is shut down.
		10449	*/
3031	serge	10450	// drm_kms_helper_poll_fini(dev);
4104	Serge	10451
3031	serge	10452	mutex_lock(&dev->struct_mutex);
2327	Serge	10453
3031	serge	10454	// intel_unregister_dsm_handler();
2327	Serge	10455
3031	serge	10456	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		10457	/* Skip inactive CRTCs */
		10458	if (!crtc->fb)
		10459	continue;
2342	Serge	10460
3031	serge	10461	intel_increase_pllclock(crtc);
		10462	}
2342	Serge	10463
3031	serge	10464	intel_disable_fbc(dev);
2342	Serge	10465
3031	serge	10466	intel_disable_gt_powersave(dev);
2342	Serge	10467
3031	serge	10468	ironlake_teardown_rc6(dev);
2327	Serge	10469
3031	serge	10470	mutex_unlock(&dev->struct_mutex);
2327	Serge	10471
4104	Serge	10472	/* flush any delayed tasks or pending work */
		10473	flush_scheduled_work();
3031	serge	10474	// cancel_work_sync(&dev_priv->hotplug_work);
		10475	// cancel_work_sync(&dev_priv->rps.work);
2327	Serge	10476
3031	serge	10477	/* flush any delayed tasks or pending work */
		10478	// flush_scheduled_work();
2327	Serge	10479
3031	serge	10480	drm_mode_config_cleanup(dev);
2327	Serge	10481	#endif
		10482	}
		10483
		10484	/*
3031	serge	10485	* Return which encoder is currently attached for connector.
2327	Serge	10486	*/
3031	serge	10487	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	10488	{
3031	serge	10489	return &intel_attached_encoder(connector)->base;
		10490	}
2327	Serge	10491
3031	serge	10492	void intel_connector_attach_encoder(struct intel_connector *connector,
		10493	struct intel_encoder *encoder)
		10494	{
		10495	connector->encoder = encoder;
		10496	drm_mode_connector_attach_encoder(&connector->base,
		10497	&encoder->base);
2327	Serge	10498	}
		10499
		10500	/*
3031	serge	10501	* set vga decode state - true == enable VGA decode
2327	Serge	10502	*/
3031	serge	10503	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	10504	{
2330	Serge	10505	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10506	u16 gmch_ctrl;
2327	Serge	10507
3031	serge	10508	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
		10509	if (state)
		10510	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	10511	else
3031	serge	10512	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
		10513	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
		10514	return 0;
2330	Serge	10515	}
		10516
3031	serge	10517	#ifdef CONFIG_DEBUG_FS
		10518	#include
2327	Serge	10519
3031	serge	10520	struct intel_display_error_state {
4104	Serge	10521
		10522	u32 power_well_driver;
		10523
		10524	int num_transcoders;
		10525
3031	serge	10526	struct intel_cursor_error_state {
		10527	u32 control;
		10528	u32 position;
		10529	u32 base;
		10530	u32 size;
		10531	} cursor[I915_MAX_PIPES];
2327	Serge	10532
3031	serge	10533	struct intel_pipe_error_state {
		10534	u32 source;
		10535	} pipe[I915_MAX_PIPES];
2327	Serge	10536
3031	serge	10537	struct intel_plane_error_state {
		10538	u32 control;
		10539	u32 stride;
		10540	u32 size;
		10541	u32 pos;
		10542	u32 addr;
		10543	u32 surface;
		10544	u32 tile_offset;
		10545	} plane[I915_MAX_PIPES];
4104	Serge	10546
		10547	struct intel_transcoder_error_state {
		10548	enum transcoder cpu_transcoder;
		10549
		10550	u32 conf;
		10551
		10552	u32 htotal;
		10553	u32 hblank;
		10554	u32 hsync;
		10555	u32 vtotal;
		10556	u32 vblank;
		10557	u32 vsync;
		10558	} transcoder[4];
3031	serge	10559	};
2327	Serge	10560
3031	serge	10561	struct intel_display_error_state *
		10562	intel_display_capture_error_state(struct drm_device *dev)
		10563	{
		10564	drm_i915_private_t *dev_priv = dev->dev_private;
		10565	struct intel_display_error_state *error;
4104	Serge	10566	int transcoders[] = {
		10567	TRANSCODER_A,
		10568	TRANSCODER_B,
		10569	TRANSCODER_C,
		10570	TRANSCODER_EDP,
		10571	};
3031	serge	10572	int i;
2327	Serge	10573
4104	Serge	10574	if (INTEL_INFO(dev)->num_pipes == 0)
		10575	return NULL;
		10576
3031	serge	10577	error = kmalloc(sizeof(*error), GFP_ATOMIC);
		10578	if (error == NULL)
		10579	return NULL;
2327	Serge	10580
4104	Serge	10581	if (HAS_POWER_WELL(dev))
		10582	error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
		10583
3031	serge	10584	for_each_pipe(i) {
3746	Serge	10585	if (INTEL_INFO(dev)->gen <= 6 \|\| IS_VALLEYVIEW(dev)) {
3031	serge	10586	error->cursor[i].control = I915_READ(CURCNTR(i));
		10587	error->cursor[i].position = I915_READ(CURPOS(i));
		10588	error->cursor[i].base = I915_READ(CURBASE(i));
3746	Serge	10589	} else {
		10590	error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
		10591	error->cursor[i].position = I915_READ(CURPOS_IVB(i));
		10592	error->cursor[i].base = I915_READ(CURBASE_IVB(i));
		10593	}
2327	Serge	10594
3031	serge	10595	error->plane[i].control = I915_READ(DSPCNTR(i));
		10596	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
3746	Serge	10597	if (INTEL_INFO(dev)->gen <= 3) {
3031	serge	10598	error->plane[i].size = I915_READ(DSPSIZE(i));
		10599	error->plane[i].pos = I915_READ(DSPPOS(i));
3746	Serge	10600	}
		10601	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3031	serge	10602	error->plane[i].addr = I915_READ(DSPADDR(i));
		10603	if (INTEL_INFO(dev)->gen >= 4) {
		10604	error->plane[i].surface = I915_READ(DSPSURF(i));
		10605	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		10606	}
2327	Serge	10607
3031	serge	10608	error->pipe[i].source = I915_READ(PIPESRC(i));
		10609	}
2327	Serge	10610
4104	Serge	10611	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
		10612	if (HAS_DDI(dev_priv->dev))
		10613	error->num_transcoders++; /* Account for eDP. */
		10614
		10615	for (i = 0; i < error->num_transcoders; i++) {
		10616	enum transcoder cpu_transcoder = transcoders[i];
		10617
		10618	error->transcoder[i].cpu_transcoder = cpu_transcoder;
		10619
		10620	error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
		10621	error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		10622	error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		10623	error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		10624	error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		10625	error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		10626	error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
		10627	}
		10628
		10629	/* In the code above we read the registers without checking if the power
		10630	* well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
		10631	* prevent the next I915_WRITE from detecting it and printing an error
		10632	* message. */
		10633	intel_uncore_clear_errors(dev);
		10634
3031	serge	10635	return error;
2330	Serge	10636	}
2327	Serge	10637
4104	Serge	10638	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		10639
3031	serge	10640	void
4104	Serge	10641	intel_display_print_error_state(struct drm_i915_error_state_buf *m,
3031	serge	10642	struct drm_device *dev,
		10643	struct intel_display_error_state *error)
2332	Serge	10644	{
3031	serge	10645	int i;
2330	Serge	10646
4104	Serge	10647	if (!error)
		10648	return;
		10649
		10650	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
		10651	if (HAS_POWER_WELL(dev))
		10652	err_printf(m, "PWR_WELL_CTL2: %08x\n",
		10653	error->power_well_driver);
3031	serge	10654	for_each_pipe(i) {
4104	Serge	10655	err_printf(m, "Pipe [%d]:\n", i);
		10656	err_printf(m, " SRC: %08x\n", error->pipe[i].source);
2332	Serge	10657
4104	Serge	10658	err_printf(m, "Plane [%d]:\n", i);
		10659	err_printf(m, " CNTR: %08x\n", error->plane[i].control);
		10660	err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
3746	Serge	10661	if (INTEL_INFO(dev)->gen <= 3) {
4104	Serge	10662	err_printf(m, " SIZE: %08x\n", error->plane[i].size);
		10663	err_printf(m, " POS: %08x\n", error->plane[i].pos);
3746	Serge	10664	}
		10665	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
4104	Serge	10666	err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
3031	serge	10667	if (INTEL_INFO(dev)->gen >= 4) {
4104	Serge	10668	err_printf(m, " SURF: %08x\n", error->plane[i].surface);
		10669	err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
3031	serge	10670	}
2332	Serge	10671
4104	Serge	10672	err_printf(m, "Cursor [%d]:\n", i);
		10673	err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		10674	err_printf(m, " POS: %08x\n", error->cursor[i].position);
		10675	err_printf(m, " BASE: %08x\n", error->cursor[i].base);
3031	serge	10676	}
4104	Serge	10677
		10678	for (i = 0; i < error->num_transcoders; i++) {
		10679	err_printf(m, " CPU transcoder: %c\n",
		10680	transcoder_name(error->transcoder[i].cpu_transcoder));
		10681	err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
		10682	err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
		10683	err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
		10684	err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
		10685	err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
		10686	err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
		10687	err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
		10688	}
2327	Serge	10689	}
3031	serge	10690	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c @ 5097 – Rev 4104