WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
3746	Serge	27	//#include
2327	Serge	28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
3746	Serge	33	#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
3031	serge	40	#include
		41	#include
		42	//#include
2327	Serge	43
		44	phys_addr_t get_bus_addr(void);
		45
		46
2330	Serge	47	#define MAX_ERRNO 4095
		48
		49
		50
2342	Serge	51	bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
2327	Serge	52	static void intel_increase_pllclock(struct drm_crtc *crtc);
3243	Serge	53	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	54
		55	typedef struct {
		56	/* given values */
		57	int n;
		58	int m1, m2;
		59	int p1, p2;
		60	/* derived values */
		61	int dot;
		62	int vco;
		63	int m;
		64	int p;
		65	} intel_clock_t;
		66
		67	typedef struct {
		68	int min, max;
		69	} intel_range_t;
		70
		71	typedef struct {
		72	int dot_limit;
		73	int p2_slow, p2_fast;
		74	} intel_p2_t;
		75
		76	#define INTEL_P2_NUM 2
		77	typedef struct intel_limit intel_limit_t;
		78	struct intel_limit {
		79	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		80	intel_p2_t p2;
3746	Serge	81	/**
		82	* find_pll() - Find the best values for the PLL
		83	* @limit: limits for the PLL
		84	* @crtc: current CRTC
		85	* @target: target frequency in kHz
		86	* @refclk: reference clock frequency in kHz
		87	* @match_clock: if provided, @best_clock P divider must
		88	* match the P divider from @match_clock
		89	* used for LVDS downclocking
		90	* @best_clock: best PLL values found
		91	*
		92	* Returns true on success, false on failure.
		93	*/
		94	bool (find_pll)(const intel_limit_t limit,
		95	struct drm_crtc *crtc,
		96	int target, int refclk,
		97	intel_clock_t *match_clock,
		98	intel_clock_t *best_clock);
2327	Serge	99	};
		100
		101	/* FDI */
		102	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		103
3243	Serge	104	int
		105	intel_pch_rawclk(struct drm_device *dev)
		106	{
		107	struct drm_i915_private *dev_priv = dev->dev_private;
		108
		109	WARN_ON(!HAS_PCH_SPLIT(dev));
		110
		111	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
		112	}
		113
2327	Serge	114	static bool
		115	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	116	int target, int refclk, intel_clock_t *match_clock,
		117	intel_clock_t *best_clock);
2327	Serge	118	static bool
		119	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	120	int target, int refclk, intel_clock_t *match_clock,
		121	intel_clock_t *best_clock);
2327	Serge	122
		123	static bool
		124	intel_find_pll_g4x_dp(const intel_limit_t , struct drm_crtc crtc,
3031	serge	125	int target, int refclk, intel_clock_t *match_clock,
		126	intel_clock_t *best_clock);
2327	Serge	127	static bool
		128	intel_find_pll_ironlake_dp(const intel_limit_t , struct drm_crtc crtc,
3031	serge	129	int target, int refclk, intel_clock_t *match_clock,
		130	intel_clock_t *best_clock);
2327	Serge	131
3031	serge	132	static bool
		133	intel_vlv_find_best_pll(const intel_limit_t limit, struct drm_crtc crtc,
		134	int target, int refclk, intel_clock_t *match_clock,
		135	intel_clock_t *best_clock);
		136
2327	Serge	137	static inline u32 /* units of 100MHz */
		138	intel_fdi_link_freq(struct drm_device *dev)
		139	{
		140	if (IS_GEN5(dev)) {
		141	struct drm_i915_private *dev_priv = dev->dev_private;
		142	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		143	} else
		144	return 27;
		145	}
		146
		147	static const intel_limit_t intel_limits_i8xx_dvo = {
		148	.dot = { .min = 25000, .max = 350000 },
		149	.vco = { .min = 930000, .max = 1400000 },
		150	.n = { .min = 3, .max = 16 },
		151	.m = { .min = 96, .max = 140 },
		152	.m1 = { .min = 18, .max = 26 },
		153	.m2 = { .min = 6, .max = 16 },
		154	.p = { .min = 4, .max = 128 },
		155	.p1 = { .min = 2, .max = 33 },
		156	.p2 = { .dot_limit = 165000,
		157	.p2_slow = 4, .p2_fast = 2 },
		158	.find_pll = intel_find_best_PLL,
		159	};
		160
		161	static const intel_limit_t intel_limits_i8xx_lvds = {
		162	.dot = { .min = 25000, .max = 350000 },
		163	.vco = { .min = 930000, .max = 1400000 },
		164	.n = { .min = 3, .max = 16 },
		165	.m = { .min = 96, .max = 140 },
		166	.m1 = { .min = 18, .max = 26 },
		167	.m2 = { .min = 6, .max = 16 },
		168	.p = { .min = 4, .max = 128 },
		169	.p1 = { .min = 1, .max = 6 },
		170	.p2 = { .dot_limit = 165000,
		171	.p2_slow = 14, .p2_fast = 7 },
		172	.find_pll = intel_find_best_PLL,
		173	};
		174
		175	static const intel_limit_t intel_limits_i9xx_sdvo = {
		176	.dot = { .min = 20000, .max = 400000 },
		177	.vco = { .min = 1400000, .max = 2800000 },
		178	.n = { .min = 1, .max = 6 },
		179	.m = { .min = 70, .max = 120 },
3480	Serge	180	.m1 = { .min = 8, .max = 18 },
		181	.m2 = { .min = 3, .max = 7 },
2327	Serge	182	.p = { .min = 5, .max = 80 },
		183	.p1 = { .min = 1, .max = 8 },
		184	.p2 = { .dot_limit = 200000,
		185	.p2_slow = 10, .p2_fast = 5 },
		186	.find_pll = intel_find_best_PLL,
		187	};
		188
		189	static const intel_limit_t intel_limits_i9xx_lvds = {
		190	.dot = { .min = 20000, .max = 400000 },
		191	.vco = { .min = 1400000, .max = 2800000 },
		192	.n = { .min = 1, .max = 6 },
		193	.m = { .min = 70, .max = 120 },
3480	Serge	194	.m1 = { .min = 8, .max = 18 },
		195	.m2 = { .min = 3, .max = 7 },
2327	Serge	196	.p = { .min = 7, .max = 98 },
		197	.p1 = { .min = 1, .max = 8 },
		198	.p2 = { .dot_limit = 112000,
		199	.p2_slow = 14, .p2_fast = 7 },
		200	.find_pll = intel_find_best_PLL,
		201	};
		202
		203
		204	static const intel_limit_t intel_limits_g4x_sdvo = {
		205	.dot = { .min = 25000, .max = 270000 },
		206	.vco = { .min = 1750000, .max = 3500000},
		207	.n = { .min = 1, .max = 4 },
		208	.m = { .min = 104, .max = 138 },
		209	.m1 = { .min = 17, .max = 23 },
		210	.m2 = { .min = 5, .max = 11 },
		211	.p = { .min = 10, .max = 30 },
		212	.p1 = { .min = 1, .max = 3},
		213	.p2 = { .dot_limit = 270000,
		214	.p2_slow = 10,
		215	.p2_fast = 10
		216	},
		217	.find_pll = intel_g4x_find_best_PLL,
		218	};
		219
		220	static const intel_limit_t intel_limits_g4x_hdmi = {
		221	.dot = { .min = 22000, .max = 400000 },
		222	.vco = { .min = 1750000, .max = 3500000},
		223	.n = { .min = 1, .max = 4 },
		224	.m = { .min = 104, .max = 138 },
		225	.m1 = { .min = 16, .max = 23 },
		226	.m2 = { .min = 5, .max = 11 },
		227	.p = { .min = 5, .max = 80 },
		228	.p1 = { .min = 1, .max = 8},
		229	.p2 = { .dot_limit = 165000,
		230	.p2_slow = 10, .p2_fast = 5 },
		231	.find_pll = intel_g4x_find_best_PLL,
		232	};
		233
		234	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		235	.dot = { .min = 20000, .max = 115000 },
		236	.vco = { .min = 1750000, .max = 3500000 },
		237	.n = { .min = 1, .max = 3 },
		238	.m = { .min = 104, .max = 138 },
		239	.m1 = { .min = 17, .max = 23 },
		240	.m2 = { .min = 5, .max = 11 },
		241	.p = { .min = 28, .max = 112 },
		242	.p1 = { .min = 2, .max = 8 },
		243	.p2 = { .dot_limit = 0,
		244	.p2_slow = 14, .p2_fast = 14
		245	},
		246	.find_pll = intel_g4x_find_best_PLL,
		247	};
		248
		249	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		250	.dot = { .min = 80000, .max = 224000 },
		251	.vco = { .min = 1750000, .max = 3500000 },
		252	.n = { .min = 1, .max = 3 },
		253	.m = { .min = 104, .max = 138 },
		254	.m1 = { .min = 17, .max = 23 },
		255	.m2 = { .min = 5, .max = 11 },
		256	.p = { .min = 14, .max = 42 },
		257	.p1 = { .min = 2, .max = 6 },
		258	.p2 = { .dot_limit = 0,
		259	.p2_slow = 7, .p2_fast = 7
		260	},
		261	.find_pll = intel_g4x_find_best_PLL,
		262	};
		263
		264	static const intel_limit_t intel_limits_g4x_display_port = {
		265	.dot = { .min = 161670, .max = 227000 },
		266	.vco = { .min = 1750000, .max = 3500000},
		267	.n = { .min = 1, .max = 2 },
		268	.m = { .min = 97, .max = 108 },
		269	.m1 = { .min = 0x10, .max = 0x12 },
		270	.m2 = { .min = 0x05, .max = 0x06 },
		271	.p = { .min = 10, .max = 20 },
		272	.p1 = { .min = 1, .max = 2},
		273	.p2 = { .dot_limit = 0,
		274	.p2_slow = 10, .p2_fast = 10 },
		275	.find_pll = intel_find_pll_g4x_dp,
		276	};
		277
		278	static const intel_limit_t intel_limits_pineview_sdvo = {
		279	.dot = { .min = 20000, .max = 400000},
		280	.vco = { .min = 1700000, .max = 3500000 },
		281	/* Pineview's Ncounter is a ring counter */
		282	.n = { .min = 3, .max = 6 },
		283	.m = { .min = 2, .max = 256 },
		284	/* Pineview only has one combined m divider, which we treat as m2. */
		285	.m1 = { .min = 0, .max = 0 },
		286	.m2 = { .min = 0, .max = 254 },
		287	.p = { .min = 5, .max = 80 },
		288	.p1 = { .min = 1, .max = 8 },
		289	.p2 = { .dot_limit = 200000,
		290	.p2_slow = 10, .p2_fast = 5 },
		291	.find_pll = intel_find_best_PLL,
		292	};
		293
		294	static const intel_limit_t intel_limits_pineview_lvds = {
		295	.dot = { .min = 20000, .max = 400000 },
		296	.vco = { .min = 1700000, .max = 3500000 },
		297	.n = { .min = 3, .max = 6 },
		298	.m = { .min = 2, .max = 256 },
		299	.m1 = { .min = 0, .max = 0 },
		300	.m2 = { .min = 0, .max = 254 },
		301	.p = { .min = 7, .max = 112 },
		302	.p1 = { .min = 1, .max = 8 },
		303	.p2 = { .dot_limit = 112000,
		304	.p2_slow = 14, .p2_fast = 14 },
		305	.find_pll = intel_find_best_PLL,
		306	};
		307
		308	/* Ironlake / Sandybridge
		309	*
		310	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		311	* the range value for them is (actual_value - 2).
		312	*/
		313	static const intel_limit_t intel_limits_ironlake_dac = {
		314	.dot = { .min = 25000, .max = 350000 },
		315	.vco = { .min = 1760000, .max = 3510000 },
		316	.n = { .min = 1, .max = 5 },
		317	.m = { .min = 79, .max = 127 },
		318	.m1 = { .min = 12, .max = 22 },
		319	.m2 = { .min = 5, .max = 9 },
		320	.p = { .min = 5, .max = 80 },
		321	.p1 = { .min = 1, .max = 8 },
		322	.p2 = { .dot_limit = 225000,
		323	.p2_slow = 10, .p2_fast = 5 },
		324	.find_pll = intel_g4x_find_best_PLL,
		325	};
		326
		327	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		328	.dot = { .min = 25000, .max = 350000 },
		329	.vco = { .min = 1760000, .max = 3510000 },
		330	.n = { .min = 1, .max = 3 },
		331	.m = { .min = 79, .max = 118 },
		332	.m1 = { .min = 12, .max = 22 },
		333	.m2 = { .min = 5, .max = 9 },
		334	.p = { .min = 28, .max = 112 },
		335	.p1 = { .min = 2, .max = 8 },
		336	.p2 = { .dot_limit = 225000,
		337	.p2_slow = 14, .p2_fast = 14 },
		338	.find_pll = intel_g4x_find_best_PLL,
		339	};
		340
		341	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		342	.dot = { .min = 25000, .max = 350000 },
		343	.vco = { .min = 1760000, .max = 3510000 },
		344	.n = { .min = 1, .max = 3 },
		345	.m = { .min = 79, .max = 127 },
		346	.m1 = { .min = 12, .max = 22 },
		347	.m2 = { .min = 5, .max = 9 },
		348	.p = { .min = 14, .max = 56 },
		349	.p1 = { .min = 2, .max = 8 },
		350	.p2 = { .dot_limit = 225000,
		351	.p2_slow = 7, .p2_fast = 7 },
		352	.find_pll = intel_g4x_find_best_PLL,
		353	};
		354
		355	/* LVDS 100mhz refclk limits. */
		356	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		357	.dot = { .min = 25000, .max = 350000 },
		358	.vco = { .min = 1760000, .max = 3510000 },
		359	.n = { .min = 1, .max = 2 },
		360	.m = { .min = 79, .max = 126 },
		361	.m1 = { .min = 12, .max = 22 },
		362	.m2 = { .min = 5, .max = 9 },
		363	.p = { .min = 28, .max = 112 },
2342	Serge	364	.p1 = { .min = 2, .max = 8 },
2327	Serge	365	.p2 = { .dot_limit = 225000,
		366	.p2_slow = 14, .p2_fast = 14 },
		367	.find_pll = intel_g4x_find_best_PLL,
		368	};
		369
		370	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		371	.dot = { .min = 25000, .max = 350000 },
		372	.vco = { .min = 1760000, .max = 3510000 },
		373	.n = { .min = 1, .max = 3 },
		374	.m = { .min = 79, .max = 126 },
		375	.m1 = { .min = 12, .max = 22 },
		376	.m2 = { .min = 5, .max = 9 },
		377	.p = { .min = 14, .max = 42 },
2342	Serge	378	.p1 = { .min = 2, .max = 6 },
2327	Serge	379	.p2 = { .dot_limit = 225000,
		380	.p2_slow = 7, .p2_fast = 7 },
		381	.find_pll = intel_g4x_find_best_PLL,
		382	};
		383
		384	static const intel_limit_t intel_limits_ironlake_display_port = {
		385	.dot = { .min = 25000, .max = 350000 },
		386	.vco = { .min = 1760000, .max = 3510000},
		387	.n = { .min = 1, .max = 2 },
		388	.m = { .min = 81, .max = 90 },
		389	.m1 = { .min = 12, .max = 22 },
		390	.m2 = { .min = 5, .max = 9 },
		391	.p = { .min = 10, .max = 20 },
		392	.p1 = { .min = 1, .max = 2},
		393	.p2 = { .dot_limit = 0,
		394	.p2_slow = 10, .p2_fast = 10 },
		395	.find_pll = intel_find_pll_ironlake_dp,
		396	};
		397
3031	serge	398	static const intel_limit_t intel_limits_vlv_dac = {
		399	.dot = { .min = 25000, .max = 270000 },
		400	.vco = { .min = 4000000, .max = 6000000 },
		401	.n = { .min = 1, .max = 7 },
		402	.m = { .min = 22, .max = 450 }, /* guess */
		403	.m1 = { .min = 2, .max = 3 },
		404	.m2 = { .min = 11, .max = 156 },
		405	.p = { .min = 10, .max = 30 },
		406	.p1 = { .min = 2, .max = 3 },
		407	.p2 = { .dot_limit = 270000,
		408	.p2_slow = 2, .p2_fast = 20 },
		409	.find_pll = intel_vlv_find_best_pll,
		410	};
		411
		412	static const intel_limit_t intel_limits_vlv_hdmi = {
		413	.dot = { .min = 20000, .max = 165000 },
3243	Serge	414	.vco = { .min = 4000000, .max = 5994000},
3031	serge	415	.n = { .min = 1, .max = 7 },
		416	.m = { .min = 60, .max = 300 }, /* guess */
		417	.m1 = { .min = 2, .max = 3 },
		418	.m2 = { .min = 11, .max = 156 },
		419	.p = { .min = 10, .max = 30 },
		420	.p1 = { .min = 2, .max = 3 },
		421	.p2 = { .dot_limit = 270000,
		422	.p2_slow = 2, .p2_fast = 20 },
		423	.find_pll = intel_vlv_find_best_pll,
		424	};
		425
		426	static const intel_limit_t intel_limits_vlv_dp = {
3243	Serge	427	.dot = { .min = 25000, .max = 270000 },
		428	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	429	.n = { .min = 1, .max = 7 },
3243	Serge	430	.m = { .min = 22, .max = 450 },
3031	serge	431	.m1 = { .min = 2, .max = 3 },
		432	.m2 = { .min = 11, .max = 156 },
		433	.p = { .min = 10, .max = 30 },
		434	.p1 = { .min = 2, .max = 3 },
		435	.p2 = { .dot_limit = 270000,
		436	.p2_slow = 2, .p2_fast = 20 },
		437	.find_pll = intel_vlv_find_best_pll,
		438	};
		439
		440	u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
		441	{
3480	Serge	442	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
3031	serge	443
		444	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		445	DRM_ERROR("DPIO idle wait timed out\n");
3480	Serge	446	return 0;
3031	serge	447	}
		448
		449	I915_WRITE(DPIO_REG, reg);
		450	I915_WRITE(DPIO_PKT, DPIO_RID \| DPIO_OP_READ \| DPIO_PORTID \|
		451	DPIO_BYTE);
		452	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		453	DRM_ERROR("DPIO read wait timed out\n");
3480	Serge	454	return 0;
3031	serge	455	}
		456
3480	Serge	457	return I915_READ(DPIO_DATA);
3031	serge	458	}
		459
		460	static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
		461	u32 val)
		462	{
3480	Serge	463	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
3031	serge	464
		465	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		466	DRM_ERROR("DPIO idle wait timed out\n");
3480	Serge	467	return;
3031	serge	468	}
		469
		470	I915_WRITE(DPIO_DATA, val);
		471	I915_WRITE(DPIO_REG, reg);
		472	I915_WRITE(DPIO_PKT, DPIO_RID \| DPIO_OP_WRITE \| DPIO_PORTID \|
		473	DPIO_BYTE);
		474	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
		475	DRM_ERROR("DPIO write wait timed out\n");
		476	}
		477
		478	static void vlv_init_dpio(struct drm_device *dev)
		479	{
		480	struct drm_i915_private *dev_priv = dev->dev_private;
		481
		482	/* Reset the DPIO config */
		483	I915_WRITE(DPIO_CTL, 0);
		484	POSTING_READ(DPIO_CTL);
		485	I915_WRITE(DPIO_CTL, 1);
		486	POSTING_READ(DPIO_CTL);
		487	}
		488
2327	Serge	489	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		490	int refclk)
		491	{
		492	struct drm_device *dev = crtc->dev;
		493	const intel_limit_t *limit;
		494
		495	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	496	if (intel_is_dual_link_lvds(dev)) {
2327	Serge	497	if (refclk == 100000)
		498	limit = &intel_limits_ironlake_dual_lvds_100m;
		499	else
		500	limit = &intel_limits_ironlake_dual_lvds;
		501	} else {
		502	if (refclk == 100000)
		503	limit = &intel_limits_ironlake_single_lvds_100m;
		504	else
		505	limit = &intel_limits_ironlake_single_lvds;
		506	}
		507	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
3243	Serge	508	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
2327	Serge	509	limit = &intel_limits_ironlake_display_port;
		510	else
		511	limit = &intel_limits_ironlake_dac;
		512
		513	return limit;
		514	}
		515
		516	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		517	{
		518	struct drm_device *dev = crtc->dev;
		519	const intel_limit_t *limit;
		520
		521	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	522	if (intel_is_dual_link_lvds(dev))
2327	Serge	523	limit = &intel_limits_g4x_dual_channel_lvds;
		524	else
		525	limit = &intel_limits_g4x_single_channel_lvds;
		526	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		527	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		528	limit = &intel_limits_g4x_hdmi;
		529	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		530	limit = &intel_limits_g4x_sdvo;
2342	Serge	531	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2327	Serge	532	limit = &intel_limits_g4x_display_port;
		533	} else /* The option is for other outputs */
		534	limit = &intel_limits_i9xx_sdvo;
		535
		536	return limit;
		537	}
		538
		539	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		540	{
		541	struct drm_device *dev = crtc->dev;
		542	const intel_limit_t *limit;
		543
		544	if (HAS_PCH_SPLIT(dev))
		545	limit = intel_ironlake_limit(crtc, refclk);
		546	else if (IS_G4X(dev)) {
		547	limit = intel_g4x_limit(crtc);
		548	} else if (IS_PINEVIEW(dev)) {
		549	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		550	limit = &intel_limits_pineview_lvds;
		551	else
		552	limit = &intel_limits_pineview_sdvo;
3031	serge	553	} else if (IS_VALLEYVIEW(dev)) {
		554	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
		555	limit = &intel_limits_vlv_dac;
		556	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
		557	limit = &intel_limits_vlv_hdmi;
		558	else
		559	limit = &intel_limits_vlv_dp;
2327	Serge	560	} else if (!IS_GEN2(dev)) {
		561	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		562	limit = &intel_limits_i9xx_lvds;
		563	else
		564	limit = &intel_limits_i9xx_sdvo;
		565	} else {
		566	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		567	limit = &intel_limits_i8xx_lvds;
		568	else
		569	limit = &intel_limits_i8xx_dvo;
		570	}
		571	return limit;
		572	}
		573
		574	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		575	static void pineview_clock(int refclk, intel_clock_t *clock)
		576	{
		577	clock->m = clock->m2 + 2;
		578	clock->p = clock->p1 * clock->p2;
		579	clock->vco = refclk * clock->m / clock->n;
		580	clock->dot = clock->vco / clock->p;
		581	}
		582
		583	static void intel_clock(struct drm_device dev, int refclk, intel_clock_t clock)
		584	{
		585	if (IS_PINEVIEW(dev)) {
		586	pineview_clock(refclk, clock);
		587	return;
		588	}
		589	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
		590	clock->p = clock->p1 * clock->p2;
		591	clock->vco = refclk * clock->m / (clock->n + 2);
		592	clock->dot = clock->vco / clock->p;
		593	}
		594
		595	/**
		596	* Returns whether any output on the specified pipe is of the specified type
		597	*/
		598	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		599	{
		600	struct drm_device *dev = crtc->dev;
		601	struct intel_encoder *encoder;
		602
3031	serge	603	for_each_encoder_on_crtc(dev, crtc, encoder)
		604	if (encoder->type == type)
2327	Serge	605	return true;
		606
		607	return false;
		608	}
		609
		610	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		611	/**
		612	* Returns whether the given set of divisors are valid for a given refclk with
		613	* the given connectors.
		614	*/
		615
		616	static bool intel_PLL_is_valid(struct drm_device *dev,
		617	const intel_limit_t *limit,
		618	const intel_clock_t *clock)
		619	{
		620	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	621	INTELPllInvalid("p1 out of range\n");
2327	Serge	622	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
2342	Serge	623	INTELPllInvalid("p out of range\n");
2327	Serge	624	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	625	INTELPllInvalid("m2 out of range\n");
2327	Serge	626	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	627	INTELPllInvalid("m1 out of range\n");
2327	Serge	628	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
2342	Serge	629	INTELPllInvalid("m1 <= m2\n");
2327	Serge	630	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
2342	Serge	631	INTELPllInvalid("m out of range\n");
2327	Serge	632	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
2342	Serge	633	INTELPllInvalid("n out of range\n");
2327	Serge	634	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	635	INTELPllInvalid("vco out of range\n");
2327	Serge	636	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		637	* connector, etc., rather than just a single range.
		638	*/
		639	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	640	INTELPllInvalid("dot out of range\n");
2327	Serge	641
		642	return true;
		643	}
		644
		645	static bool
		646	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	647	int target, int refclk, intel_clock_t *match_clock,
		648	intel_clock_t *best_clock)
2327	Serge	649
		650	{
		651	struct drm_device *dev = crtc->dev;
		652	intel_clock_t clock;
		653	int err = target;
		654
3480	Serge	655	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2327	Serge	656	/*
3480	Serge	657	* For LVDS just rely on its current settings for dual-channel.
		658	* We haven't figured out how to reliably set up different
		659	* single/dual channel state, if we even can.
2327	Serge	660	*/
3480	Serge	661	if (intel_is_dual_link_lvds(dev))
2327	Serge	662	clock.p2 = limit->p2.p2_fast;
		663	else
		664	clock.p2 = limit->p2.p2_slow;
		665	} else {
		666	if (target < limit->p2.dot_limit)
		667	clock.p2 = limit->p2.p2_slow;
		668	else
		669	clock.p2 = limit->p2.p2_fast;
		670	}
		671
2342	Serge	672	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	673
		674	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		675	clock.m1++) {
		676	for (clock.m2 = limit->m2.min;
		677	clock.m2 <= limit->m2.max; clock.m2++) {
		678	/* m1 is always 0 in Pineview */
		679	if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
		680	break;
		681	for (clock.n = limit->n.min;
		682	clock.n <= limit->n.max; clock.n++) {
		683	for (clock.p1 = limit->p1.min;
		684	clock.p1 <= limit->p1.max; clock.p1++) {
		685	int this_err;
		686
		687	intel_clock(dev, refclk, &clock);
		688	if (!intel_PLL_is_valid(dev, limit,
		689	&clock))
		690	continue;
3031	serge	691	if (match_clock &&
		692	clock.p != match_clock->p)
		693	continue;
2327	Serge	694
		695	this_err = abs(clock.dot - target);
		696	if (this_err < err) {
		697	*best_clock = clock;
		698	err = this_err;
		699	}
		700	}
		701	}
		702	}
		703	}
		704
		705	return (err != target);
		706	}
		707
		708	static bool
		709	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	710	int target, int refclk, intel_clock_t *match_clock,
		711	intel_clock_t *best_clock)
2327	Serge	712	{
		713	struct drm_device *dev = crtc->dev;
		714	intel_clock_t clock;
		715	int max_n;
		716	bool found;
		717	/* approximately equals target * 0.00585 */
		718	int err_most = (target >> 8) + (target >> 9);
		719	found = false;
		720
		721	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		722	int lvds_reg;
		723
		724	if (HAS_PCH_SPLIT(dev))
		725	lvds_reg = PCH_LVDS;
		726	else
		727	lvds_reg = LVDS;
3480	Serge	728	if (intel_is_dual_link_lvds(dev))
2327	Serge	729	clock.p2 = limit->p2.p2_fast;
		730	else
		731	clock.p2 = limit->p2.p2_slow;
		732	} else {
		733	if (target < limit->p2.dot_limit)
		734	clock.p2 = limit->p2.p2_slow;
		735	else
		736	clock.p2 = limit->p2.p2_fast;
		737	}
		738
		739	memset(best_clock, 0, sizeof(*best_clock));
		740	max_n = limit->n.max;
		741	/* based on hardware requirement, prefer smaller n to precision */
		742	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		743	/* based on hardware requirement, prefere larger m1,m2 */
		744	for (clock.m1 = limit->m1.max;
		745	clock.m1 >= limit->m1.min; clock.m1--) {
		746	for (clock.m2 = limit->m2.max;
		747	clock.m2 >= limit->m2.min; clock.m2--) {
		748	for (clock.p1 = limit->p1.max;
		749	clock.p1 >= limit->p1.min; clock.p1--) {
		750	int this_err;
		751
		752	intel_clock(dev, refclk, &clock);
		753	if (!intel_PLL_is_valid(dev, limit,
		754	&clock))
		755	continue;
3031	serge	756	if (match_clock &&
		757	clock.p != match_clock->p)
		758	continue;
2327	Serge	759
		760	this_err = abs(clock.dot - target);
		761	if (this_err < err_most) {
		762	*best_clock = clock;
		763	err_most = this_err;
		764	max_n = clock.n;
		765	found = true;
		766	}
		767	}
		768	}
		769	}
		770	}
		771	return found;
		772	}
		773
		774	static bool
		775	intel_find_pll_ironlake_dp(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	776	int target, int refclk, intel_clock_t *match_clock,
		777	intel_clock_t *best_clock)
2327	Serge	778	{
		779	struct drm_device *dev = crtc->dev;
		780	intel_clock_t clock;
		781
		782	if (target < 200000) {
		783	clock.n = 1;
		784	clock.p1 = 2;
		785	clock.p2 = 10;
		786	clock.m1 = 12;
		787	clock.m2 = 9;
		788	} else {
		789	clock.n = 2;
		790	clock.p1 = 1;
		791	clock.p2 = 10;
		792	clock.m1 = 14;
		793	clock.m2 = 8;
		794	}
		795	intel_clock(dev, refclk, &clock);
		796	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		797	return true;
		798	}
		799
		800	/* DisplayPort has only two frequencies, 162MHz and 270MHz */
		801	static bool
		802	intel_find_pll_g4x_dp(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	803	int target, int refclk, intel_clock_t *match_clock,
		804	intel_clock_t *best_clock)
2327	Serge	805	{
		806	intel_clock_t clock;
		807	if (target < 200000) {
		808	clock.p1 = 2;
		809	clock.p2 = 10;
		810	clock.n = 2;
		811	clock.m1 = 23;
		812	clock.m2 = 8;
		813	} else {
		814	clock.p1 = 1;
		815	clock.p2 = 10;
		816	clock.n = 1;
		817	clock.m1 = 14;
		818	clock.m2 = 2;
		819	}
		820	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
		821	clock.p = (clock.p1 * clock.p2);
		822	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
		823	clock.vco = 0;
		824	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		825	return true;
		826	}
3031	serge	827	static bool
		828	intel_vlv_find_best_pll(const intel_limit_t limit, struct drm_crtc crtc,
		829	int target, int refclk, intel_clock_t *match_clock,
		830	intel_clock_t *best_clock)
		831	{
		832	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
		833	u32 m, n, fastclk;
		834	u32 updrate, minupdate, fracbits, p;
		835	unsigned long bestppm, ppm, absppm;
		836	int dotclk, flag;
2327	Serge	837
3031	serge	838	flag = 0;
		839	dotclk = target * 1000;
		840	bestppm = 1000000;
		841	ppm = absppm = 0;
		842	fastclk = dotclk / (2*100);
		843	updrate = 0;
		844	minupdate = 19200;
		845	fracbits = 1;
		846	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
		847	bestm1 = bestm2 = bestp1 = bestp2 = 0;
		848
		849	/* based on hardware requirement, prefer smaller n to precision */
		850	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		851	updrate = refclk / n;
		852	for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
		853	for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
		854	if (p2 > 10)
		855	p2 = p2 - 1;
		856	p = p1 * p2;
		857	/* based on hardware requirement, prefer bigger m1,m2 values */
		858	for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
		859	m2 = (((2(fastclk p * n / m1 )) +
		860	refclk) / (2*refclk));
		861	m = m1 * m2;
		862	vco = updrate * m;
		863	if (vco >= limit->vco.min && vco < limit->vco.max) {
		864	ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
		865	absppm = (ppm > 0) ? ppm : (-ppm);
		866	if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
		867	bestppm = 0;
		868	flag = 1;
		869	}
		870	if (absppm < bestppm - 10) {
		871	bestppm = absppm;
		872	flag = 1;
		873	}
		874	if (flag) {
		875	bestn = n;
		876	bestm1 = m1;
		877	bestm2 = m2;
		878	bestp1 = p1;
		879	bestp2 = p2;
		880	flag = 0;
		881	}
		882	}
		883	}
		884	}
		885	}
		886	}
		887	best_clock->n = bestn;
		888	best_clock->m1 = bestm1;
		889	best_clock->m2 = bestm2;
		890	best_clock->p1 = bestp1;
		891	best_clock->p2 = bestp2;
		892
		893	return true;
		894	}
		895
3243	Serge	896	enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
		897	enum pipe pipe)
		898	{
		899	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		900	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		901
3746	Serge	902	return intel_crtc->config.cpu_transcoder;
3243	Serge	903	}
		904
3031	serge	905	static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
		906	{
		907	struct drm_i915_private *dev_priv = dev->dev_private;
		908	u32 frame, frame_reg = PIPEFRAME(pipe);
		909
		910	frame = I915_READ(frame_reg);
		911
		912	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		913	DRM_DEBUG_KMS("vblank wait timed out\n");
		914	}
		915
2327	Serge	916	/**
		917	* intel_wait_for_vblank - wait for vblank on a given pipe
		918	* @dev: drm device
		919	* @pipe: pipe to wait for
		920	*
		921	* Wait for vblank to occur on a given pipe. Needed for various bits of
		922	* mode setting code.
		923	*/
		924	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		925	{
		926	struct drm_i915_private *dev_priv = dev->dev_private;
		927	int pipestat_reg = PIPESTAT(pipe);
		928
3031	serge	929	if (INTEL_INFO(dev)->gen >= 5) {
		930	ironlake_wait_for_vblank(dev, pipe);
		931	return;
		932	}
		933
2327	Serge	934	/* Clear existing vblank status. Note this will clear any other
		935	* sticky status fields as well.
		936	*
		937	* This races with i915_driver_irq_handler() with the result
		938	* that either function could miss a vblank event. Here it is not
		939	* fatal, as we will either wait upon the next vblank interrupt or
		940	* timeout. Generally speaking intel_wait_for_vblank() is only
		941	* called during modeset at which time the GPU should be idle and
		942	* should not be performing page flips and thus not waiting on
		943	* vblanks...
		944	* Currently, the result of us stealing a vblank from the irq
		945	* handler is that a single frame will be skipped during swapbuffers.
		946	*/
		947	I915_WRITE(pipestat_reg,
		948	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		949
		950	/* Wait for vblank interrupt bit to set */
		951	if (wait_for(I915_READ(pipestat_reg) &
		952	PIPE_VBLANK_INTERRUPT_STATUS,
		953	50))
		954	DRM_DEBUG_KMS("vblank wait timed out\n");
		955	}
		956
		957	/*
		958	* intel_wait_for_pipe_off - wait for pipe to turn off
		959	* @dev: drm device
		960	* @pipe: pipe to wait for
		961	*
		962	* After disabling a pipe, we can't wait for vblank in the usual way,
		963	* spinning on the vblank interrupt status bit, since we won't actually
		964	* see an interrupt when the pipe is disabled.
		965	*
		966	* On Gen4 and above:
		967	* wait for the pipe register state bit to turn off
		968	*
		969	* Otherwise:
		970	* wait for the display line value to settle (it usually
		971	* ends up stopping at the start of the next frame).
		972	*
		973	*/
		974	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		975	{
		976	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	977	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		978	pipe);
2327	Serge	979
		980	if (INTEL_INFO(dev)->gen >= 4) {
3243	Serge	981	int reg = PIPECONF(cpu_transcoder);
2327	Serge	982
		983	/* Wait for the Pipe State to go off */
		984	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		985	100))
3031	serge	986	WARN(1, "pipe_off wait timed out\n");
2327	Serge	987	} else {
3031	serge	988	u32 last_line, line_mask;
2327	Serge	989	int reg = PIPEDSL(pipe);
3031	serge	990	unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
2327	Serge	991
3031	serge	992	if (IS_GEN2(dev))
		993	line_mask = DSL_LINEMASK_GEN2;
		994	else
		995	line_mask = DSL_LINEMASK_GEN3;
		996
2327	Serge	997	/* Wait for the display line to settle */
		998	do {
3031	serge	999	last_line = I915_READ(reg) & line_mask;
2327	Serge	1000	mdelay(5);
3031	serge	1001	} while (((I915_READ(reg) & line_mask) != last_line) &&
		1002	time_after(timeout, GetTimerTicks()));
		1003	if (time_after(GetTimerTicks(), timeout))
		1004	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1005	}
		1006	}
		1007
3480	Serge	1008	/*
		1009	* ibx_digital_port_connected - is the specified port connected?
		1010	* @dev_priv: i915 private structure
		1011	* @port: the port to test
		1012	*
		1013	* Returns true if @port is connected, false otherwise.
		1014	*/
		1015	bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
		1016	struct intel_digital_port *port)
		1017	{
		1018	u32 bit;
		1019
		1020	if (HAS_PCH_IBX(dev_priv->dev)) {
		1021	switch(port->port) {
		1022	case PORT_B:
		1023	bit = SDE_PORTB_HOTPLUG;
		1024	break;
		1025	case PORT_C:
		1026	bit = SDE_PORTC_HOTPLUG;
		1027	break;
		1028	case PORT_D:
		1029	bit = SDE_PORTD_HOTPLUG;
		1030	break;
		1031	default:
		1032	return true;
		1033	}
		1034	} else {
		1035	switch(port->port) {
		1036	case PORT_B:
		1037	bit = SDE_PORTB_HOTPLUG_CPT;
		1038	break;
		1039	case PORT_C:
		1040	bit = SDE_PORTC_HOTPLUG_CPT;
		1041	break;
		1042	case PORT_D:
		1043	bit = SDE_PORTD_HOTPLUG_CPT;
		1044	break;
		1045	default:
		1046	return true;
		1047	}
		1048	}
		1049
		1050	return I915_READ(SDEISR) & bit;
		1051	}
		1052
2327	Serge	1053	static const char *state_string(bool enabled)
		1054	{
		1055	return enabled ? "on" : "off";
		1056	}
		1057
		1058	/* Only for pre-ILK configs */
		1059	static void assert_pll(struct drm_i915_private *dev_priv,
		1060	enum pipe pipe, bool state)
		1061	{
		1062	int reg;
		1063	u32 val;
		1064	bool cur_state;
		1065
		1066	reg = DPLL(pipe);
		1067	val = I915_READ(reg);
		1068	cur_state = !!(val & DPLL_VCO_ENABLE);
		1069	WARN(cur_state != state,
		1070	"PLL state assertion failure (expected %s, current %s)\n",
		1071	state_string(state), state_string(cur_state));
		1072	}
		1073	#define assert_pll_enabled(d, p) assert_pll(d, p, true)
		1074	#define assert_pll_disabled(d, p) assert_pll(d, p, false)
		1075
		1076	/* For ILK+ */
		1077	static void assert_pch_pll(struct drm_i915_private *dev_priv,
3031	serge	1078	struct intel_pch_pll *pll,
		1079	struct intel_crtc *crtc,
		1080	bool state)
2327	Serge	1081	{
		1082	u32 val;
		1083	bool cur_state;
		1084
3031	serge	1085	if (HAS_PCH_LPT(dev_priv->dev)) {
		1086	DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		1087	return;
		1088	}
2342	Serge	1089
3031	serge	1090	if (WARN (!pll,
		1091	"asserting PCH PLL %s with no PLL\n", state_string(state)))
		1092	return;
2342	Serge	1093
3031	serge	1094	val = I915_READ(pll->pll_reg);
		1095	cur_state = !!(val & DPLL_VCO_ENABLE);
		1096	WARN(cur_state != state,
		1097	"PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
		1098	pll->pll_reg, state_string(state), state_string(cur_state), val);
2342	Serge	1099
3031	serge	1100	/* Make sure the selected PLL is correctly attached to the transcoder */
		1101	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
		1102	u32 pch_dpll;
2342	Serge	1103
3031	serge	1104	pch_dpll = I915_READ(PCH_DPLL_SEL);
		1105	cur_state = pll->pll_reg == _PCH_DPLL_B;
		1106	if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
		1107	"PLL[%d] not attached to this transcoder %d: %08x\n",
		1108	cur_state, crtc->pipe, pch_dpll)) {
		1109	cur_state = !!(val >> (4*crtc->pipe + 3));
2327	Serge	1110	WARN(cur_state != state,
3031	serge	1111	"PLL[%d] not %s on this transcoder %d: %08x\n",
		1112	pll->pll_reg == _PCH_DPLL_B,
		1113	state_string(state),
		1114	crtc->pipe,
		1115	val);
		1116	}
		1117	}
2327	Serge	1118	}
3031	serge	1119	#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
		1120	#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
2327	Serge	1121
		1122	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		1123	enum pipe pipe, bool state)
		1124	{
		1125	int reg;
		1126	u32 val;
		1127	bool cur_state;
3243	Serge	1128	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1129	pipe);
2327	Serge	1130
3480	Serge	1131	if (HAS_DDI(dev_priv->dev)) {
		1132	/* DDI does not have a specific FDI_TX register */
3243	Serge	1133	reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3031	serge	1134	val = I915_READ(reg);
3243	Serge	1135	cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
3031	serge	1136	} else {
2327	Serge	1137	reg = FDI_TX_CTL(pipe);
		1138	val = I915_READ(reg);
		1139	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	1140	}
2327	Serge	1141	WARN(cur_state != state,
		1142	"FDI TX state assertion failure (expected %s, current %s)\n",
		1143	state_string(state), state_string(cur_state));
		1144	}
		1145	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		1146	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		1147
		1148	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		1149	enum pipe pipe, bool state)
		1150	{
		1151	int reg;
		1152	u32 val;
		1153	bool cur_state;
		1154
		1155	reg = FDI_RX_CTL(pipe);
		1156	val = I915_READ(reg);
		1157	cur_state = !!(val & FDI_RX_ENABLE);
		1158	WARN(cur_state != state,
		1159	"FDI RX state assertion failure (expected %s, current %s)\n",
		1160	state_string(state), state_string(cur_state));
		1161	}
		1162	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1163	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1164
		1165	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1166	enum pipe pipe)
		1167	{
		1168	int reg;
		1169	u32 val;
		1170
		1171	/* ILK FDI PLL is always enabled */
		1172	if (dev_priv->info->gen == 5)
		1173	return;
		1174
3031	serge	1175	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
3480	Serge	1176	if (HAS_DDI(dev_priv->dev))
3031	serge	1177	return;
		1178
2327	Serge	1179	reg = FDI_TX_CTL(pipe);
		1180	val = I915_READ(reg);
		1181	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		1182	}
		1183
		1184	static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
		1185	enum pipe pipe)
		1186	{
		1187	int reg;
		1188	u32 val;
		1189
		1190	reg = FDI_RX_CTL(pipe);
		1191	val = I915_READ(reg);
		1192	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
		1193	}
		1194
		1195	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		1196	enum pipe pipe)
		1197	{
		1198	int pp_reg, lvds_reg;
		1199	u32 val;
		1200	enum pipe panel_pipe = PIPE_A;
		1201	bool locked = true;
		1202
		1203	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1204	pp_reg = PCH_PP_CONTROL;
		1205	lvds_reg = PCH_LVDS;
		1206	} else {
		1207	pp_reg = PP_CONTROL;
		1208	lvds_reg = LVDS;
		1209	}
		1210
		1211	val = I915_READ(pp_reg);
		1212	if (!(val & PANEL_POWER_ON) \|\|
		1213	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		1214	locked = false;
		1215
		1216	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		1217	panel_pipe = PIPE_B;
		1218
		1219	WARN(panel_pipe == pipe && locked,
		1220	"panel assertion failure, pipe %c regs locked\n",
		1221	pipe_name(pipe));
		1222	}
		1223
2342	Serge	1224	void assert_pipe(struct drm_i915_private *dev_priv,
2327	Serge	1225	enum pipe pipe, bool state)
		1226	{
		1227	int reg;
		1228	u32 val;
		1229	bool cur_state;
3243	Serge	1230	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1231	pipe);
2327	Serge	1232
3031	serge	1233	/* if we need the pipe A quirk it must be always on */
		1234	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		1235	state = true;
		1236
3746	Serge	1237	if (!intel_using_power_well(dev_priv->dev) &&
		1238	cpu_transcoder != TRANSCODER_EDP) {
3480	Serge	1239	cur_state = false;
		1240	} else {
3243	Serge	1241	reg = PIPECONF(cpu_transcoder);
2327	Serge	1242	val = I915_READ(reg);
		1243	cur_state = !!(val & PIPECONF_ENABLE);
3480	Serge	1244	}
		1245
2327	Serge	1246	WARN(cur_state != state,
		1247	"pipe %c assertion failure (expected %s, current %s)\n",
		1248	pipe_name(pipe), state_string(state), state_string(cur_state));
		1249	}
		1250
3031	serge	1251	static void assert_plane(struct drm_i915_private *dev_priv,
		1252	enum plane plane, bool state)
2327	Serge	1253	{
		1254	int reg;
		1255	u32 val;
3031	serge	1256	bool cur_state;
2327	Serge	1257
		1258	reg = DSPCNTR(plane);
		1259	val = I915_READ(reg);
3031	serge	1260	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
		1261	WARN(cur_state != state,
		1262	"plane %c assertion failure (expected %s, current %s)\n",
		1263	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1264	}
		1265
3031	serge	1266	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1267	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1268
2327	Serge	1269	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1270	enum pipe pipe)
		1271	{
		1272	int reg, i;
		1273	u32 val;
		1274	int cur_pipe;
		1275
		1276	/* Planes are fixed to pipes on ILK+ */
3746	Serge	1277	if (HAS_PCH_SPLIT(dev_priv->dev) \|\| IS_VALLEYVIEW(dev_priv->dev)) {
3031	serge	1278	reg = DSPCNTR(pipe);
		1279	val = I915_READ(reg);
		1280	WARN((val & DISPLAY_PLANE_ENABLE),
		1281	"plane %c assertion failure, should be disabled but not\n",
		1282	plane_name(pipe));
2327	Serge	1283	return;
3031	serge	1284	}
2327	Serge	1285
		1286	/* Need to check both planes against the pipe */
		1287	for (i = 0; i < 2; i++) {
		1288	reg = DSPCNTR(i);
		1289	val = I915_READ(reg);
		1290	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		1291	DISPPLANE_SEL_PIPE_SHIFT;
		1292	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		1293	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1294	plane_name(i), pipe_name(pipe));
		1295	}
		1296	}
		1297
3746	Serge	1298	static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
		1299	enum pipe pipe)
		1300	{
		1301	int reg, i;
		1302	u32 val;
		1303
		1304	if (!IS_VALLEYVIEW(dev_priv->dev))
		1305	return;
		1306
		1307	/* Need to check both planes against the pipe */
		1308	for (i = 0; i < dev_priv->num_plane; i++) {
		1309	reg = SPCNTR(pipe, i);
		1310	val = I915_READ(reg);
		1311	WARN((val & SP_ENABLE),
		1312	"sprite %d assertion failure, should be off on pipe %c but is still active\n",
		1313	pipe * 2 + i, pipe_name(pipe));
		1314	}
		1315	}
		1316
2327	Serge	1317	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		1318	{
		1319	u32 val;
		1320	bool enabled;
		1321
3031	serge	1322	if (HAS_PCH_LPT(dev_priv->dev)) {
		1323	DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		1324	return;
		1325	}
		1326
2327	Serge	1327	val = I915_READ(PCH_DREF_CONTROL);
		1328	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1329	DREF_SUPERSPREAD_SOURCE_MASK));
		1330	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		1331	}
		1332
		1333	static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
		1334	enum pipe pipe)
		1335	{
		1336	int reg;
		1337	u32 val;
		1338	bool enabled;
		1339
		1340	reg = TRANSCONF(pipe);
		1341	val = I915_READ(reg);
		1342	enabled = !!(val & TRANS_ENABLE);
		1343	WARN(enabled,
		1344	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1345	pipe_name(pipe));
		1346	}
		1347
		1348	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1349	enum pipe pipe, u32 port_sel, u32 val)
		1350	{
		1351	if ((val & DP_PORT_EN) == 0)
		1352	return false;
		1353
		1354	if (HAS_PCH_CPT(dev_priv->dev)) {
		1355	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1356	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1357	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1358	return false;
		1359	} else {
		1360	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1361	return false;
		1362	}
		1363	return true;
		1364	}
		1365
		1366	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1367	enum pipe pipe, u32 val)
		1368	{
3746	Serge	1369	if ((val & SDVO_ENABLE) == 0)
2327	Serge	1370	return false;
		1371
		1372	if (HAS_PCH_CPT(dev_priv->dev)) {
3746	Serge	1373	if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
2327	Serge	1374	return false;
		1375	} else {
3746	Serge	1376	if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
2327	Serge	1377	return false;
		1378	}
		1379	return true;
		1380	}
		1381
		1382	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1383	enum pipe pipe, u32 val)
		1384	{
		1385	if ((val & LVDS_PORT_EN) == 0)
		1386	return false;
		1387
		1388	if (HAS_PCH_CPT(dev_priv->dev)) {
		1389	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1390	return false;
		1391	} else {
		1392	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1393	return false;
		1394	}
		1395	return true;
		1396	}
		1397
		1398	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1399	enum pipe pipe, u32 val)
		1400	{
		1401	if ((val & ADPA_DAC_ENABLE) == 0)
		1402	return false;
		1403	if (HAS_PCH_CPT(dev_priv->dev)) {
		1404	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1405	return false;
		1406	} else {
		1407	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1408	return false;
		1409	}
		1410	return true;
		1411	}
		1412
		1413	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1414	enum pipe pipe, int reg, u32 port_sel)
		1415	{
		1416	u32 val = I915_READ(reg);
		1417	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1418	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1419	reg, pipe_name(pipe));
3031	serge	1420
		1421	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
		1422	&& (val & DP_PIPEB_SELECT),
		1423	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1424	}
		1425
		1426	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1427	enum pipe pipe, int reg)
		1428	{
		1429	u32 val = I915_READ(reg);
3031	serge	1430	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
		1431	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1432	reg, pipe_name(pipe));
3031	serge	1433
3746	Serge	1434	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
3031	serge	1435	&& (val & SDVO_PIPE_B_SELECT),
		1436	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1437	}
		1438
		1439	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1440	enum pipe pipe)
		1441	{
		1442	int reg;
		1443	u32 val;
		1444
		1445	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1446	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1447	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1448
		1449	reg = PCH_ADPA;
		1450	val = I915_READ(reg);
3031	serge	1451	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1452	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1453	pipe_name(pipe));
		1454
		1455	reg = PCH_LVDS;
		1456	val = I915_READ(reg);
3031	serge	1457	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1458	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1459	pipe_name(pipe));
		1460
3746	Serge	1461	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
		1462	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
		1463	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
2327	Serge	1464	}
		1465
		1466	/**
		1467	* intel_enable_pll - enable a PLL
		1468	* @dev_priv: i915 private structure
		1469	* @pipe: pipe PLL to enable
		1470	*
		1471	* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
		1472	* make sure the PLL reg is writable first though, since the panel write
		1473	* protect mechanism may be enabled.
		1474	*
		1475	* Note! This is for pre-ILK only.
3031	serge	1476	*
		1477	* Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
2327	Serge	1478	*/
		1479	static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1480	{
		1481	int reg;
		1482	u32 val;
		1483
		1484	/* No really, not for ILK+ */
3031	serge	1485	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
2327	Serge	1486
		1487	/* PLL is protected by panel, make sure we can write it */
		1488	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		1489	assert_panel_unlocked(dev_priv, pipe);
		1490
		1491	reg = DPLL(pipe);
		1492	val = I915_READ(reg);
		1493	val \|= DPLL_VCO_ENABLE;
		1494
		1495	/* We do this three times for luck */
		1496	I915_WRITE(reg, val);
		1497	POSTING_READ(reg);
		1498	udelay(150); /* wait for warmup */
		1499	I915_WRITE(reg, val);
		1500	POSTING_READ(reg);
		1501	udelay(150); /* wait for warmup */
		1502	I915_WRITE(reg, val);
		1503	POSTING_READ(reg);
		1504	udelay(150); /* wait for warmup */
		1505	}
		1506
		1507	/**
		1508	* intel_disable_pll - disable a PLL
		1509	* @dev_priv: i915 private structure
		1510	* @pipe: pipe PLL to disable
		1511	*
		1512	* Disable the PLL for @pipe, making sure the pipe is off first.
		1513	*
		1514	* Note! This is for pre-ILK only.
		1515	*/
		1516	static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1517	{
		1518	int reg;
		1519	u32 val;
		1520
		1521	/* Don't disable pipe A or pipe A PLLs if needed */
		1522	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1523	return;
		1524
		1525	/* Make sure the pipe isn't still relying on us */
		1526	assert_pipe_disabled(dev_priv, pipe);
		1527
		1528	reg = DPLL(pipe);
		1529	val = I915_READ(reg);
		1530	val &= ~DPLL_VCO_ENABLE;
		1531	I915_WRITE(reg, val);
		1532	POSTING_READ(reg);
		1533	}
		1534
3031	serge	1535	/* SBI access */
		1536	static void
3243	Serge	1537	intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		1538	enum intel_sbi_destination destination)
3031	serge	1539	{
3243	Serge	1540	u32 tmp;
3031	serge	1541
3480	Serge	1542	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
		1543
		1544	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
		1545	100)) {
3031	serge	1546	DRM_ERROR("timeout waiting for SBI to become ready\n");
3480	Serge	1547	return;
3031	serge	1548	}
		1549
3243	Serge	1550	I915_WRITE(SBI_ADDR, (reg << 16));
		1551	I915_WRITE(SBI_DATA, value);
3031	serge	1552
3243	Serge	1553	if (destination == SBI_ICLK)
		1554	tmp = SBI_CTL_DEST_ICLK \| SBI_CTL_OP_CRWR;
		1555	else
		1556	tmp = SBI_CTL_DEST_MPHY \| SBI_CTL_OP_IOWR;
		1557	I915_WRITE(SBI_CTL_STAT, SBI_BUSY \| tmp);
		1558
3031	serge	1559	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY \| SBI_RESPONSE_FAIL)) == 0,
		1560	100)) {
		1561	DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
3480	Serge	1562	return;
3031	serge	1563	}
		1564	}
		1565
		1566	static u32
3243	Serge	1567	intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		1568	enum intel_sbi_destination destination)
3031	serge	1569	{
		1570	u32 value = 0;
3480	Serge	1571	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
3031	serge	1572
3480	Serge	1573	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
		1574	100)) {
3031	serge	1575	DRM_ERROR("timeout waiting for SBI to become ready\n");
3480	Serge	1576	return 0;
3031	serge	1577	}
		1578
3243	Serge	1579	I915_WRITE(SBI_ADDR, (reg << 16));
3031	serge	1580
3243	Serge	1581	if (destination == SBI_ICLK)
		1582	value = SBI_CTL_DEST_ICLK \| SBI_CTL_OP_CRRD;
		1583	else
		1584	value = SBI_CTL_DEST_MPHY \| SBI_CTL_OP_IORD;
		1585	I915_WRITE(SBI_CTL_STAT, value \| SBI_BUSY);
		1586
3031	serge	1587	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY \| SBI_RESPONSE_FAIL)) == 0,
		1588	100)) {
		1589	DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
3480	Serge	1590	return 0;
3031	serge	1591	}
		1592
3480	Serge	1593	return I915_READ(SBI_DATA);
3031	serge	1594	}
		1595
2327	Serge	1596	/**
3243	Serge	1597	* ironlake_enable_pch_pll - enable PCH PLL
2327	Serge	1598	* @dev_priv: i915 private structure
		1599	* @pipe: pipe PLL to enable
		1600	*
		1601	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1602	* drives the transcoder clock.
		1603	*/
3243	Serge	1604	static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
2327	Serge	1605	{
3031	serge	1606	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		1607	struct intel_pch_pll *pll;
2327	Serge	1608	int reg;
		1609	u32 val;
		1610
3031	serge	1611	/* PCH PLLs only available on ILK, SNB and IVB */
		1612	BUG_ON(dev_priv->info->gen < 5);
		1613	pll = intel_crtc->pch_pll;
		1614	if (pll == NULL)
2342	Serge	1615	return;
		1616
3031	serge	1617	if (WARN_ON(pll->refcount == 0))
		1618	return;
2327	Serge	1619
3031	serge	1620	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
		1621	pll->pll_reg, pll->active, pll->on,
		1622	intel_crtc->base.base.id);
		1623
2327	Serge	1624	/* PCH refclock must be enabled first */
		1625	assert_pch_refclk_enabled(dev_priv);
		1626
3031	serge	1627	if (pll->active++ && pll->on) {
		1628	assert_pch_pll_enabled(dev_priv, pll, NULL);
		1629	return;
		1630	}
		1631
		1632	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
		1633
		1634	reg = pll->pll_reg;
2327	Serge	1635	val = I915_READ(reg);
		1636	val \|= DPLL_VCO_ENABLE;
		1637	I915_WRITE(reg, val);
		1638	POSTING_READ(reg);
		1639	udelay(200);
3031	serge	1640
		1641	pll->on = true;
2327	Serge	1642	}
		1643
3031	serge	1644	static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
2327	Serge	1645	{
3031	serge	1646	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		1647	struct intel_pch_pll *pll = intel_crtc->pch_pll;
2327	Serge	1648	int reg;
3031	serge	1649	u32 val;
2327	Serge	1650
		1651	/* PCH only available on ILK+ */
		1652	BUG_ON(dev_priv->info->gen < 5);
3031	serge	1653	if (pll == NULL)
		1654	return;
2327	Serge	1655
3031	serge	1656	if (WARN_ON(pll->refcount == 0))
		1657	return;
2327	Serge	1658
3031	serge	1659	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
		1660	pll->pll_reg, pll->active, pll->on,
		1661	intel_crtc->base.base.id);
2342	Serge	1662
3031	serge	1663	if (WARN_ON(pll->active == 0)) {
		1664	assert_pch_pll_disabled(dev_priv, pll, NULL);
		1665	return;
		1666	}
2342	Serge	1667
3031	serge	1668	if (--pll->active) {
		1669	assert_pch_pll_enabled(dev_priv, pll, NULL);
2342	Serge	1670	return;
3031	serge	1671	}
2342	Serge	1672
3031	serge	1673	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
		1674
		1675	/* Make sure transcoder isn't still depending on us */
		1676	assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
		1677
		1678	reg = pll->pll_reg;
2327	Serge	1679	val = I915_READ(reg);
		1680	val &= ~DPLL_VCO_ENABLE;
		1681	I915_WRITE(reg, val);
		1682	POSTING_READ(reg);
		1683	udelay(200);
3031	serge	1684
		1685	pll->on = false;
2327	Serge	1686	}
		1687
3243	Serge	1688	static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1689	enum pipe pipe)
		1690	{
3243	Serge	1691	struct drm_device *dev = dev_priv->dev;
3031	serge	1692	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3243	Serge	1693	uint32_t reg, val, pipeconf_val;
2327	Serge	1694
		1695	/* PCH only available on ILK+ */
		1696	BUG_ON(dev_priv->info->gen < 5);
		1697
		1698	/* Make sure PCH DPLL is enabled */
3031	serge	1699	assert_pch_pll_enabled(dev_priv,
		1700	to_intel_crtc(crtc)->pch_pll,
		1701	to_intel_crtc(crtc));
2327	Serge	1702
		1703	/* FDI must be feeding us bits for PCH ports */
		1704	assert_fdi_tx_enabled(dev_priv, pipe);
		1705	assert_fdi_rx_enabled(dev_priv, pipe);
		1706
3243	Serge	1707	if (HAS_PCH_CPT(dev)) {
		1708	/* Workaround: Set the timing override bit before enabling the
		1709	* pch transcoder. */
		1710	reg = TRANS_CHICKEN2(pipe);
		1711	val = I915_READ(reg);
		1712	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1713	I915_WRITE(reg, val);
3031	serge	1714	}
3243	Serge	1715
2327	Serge	1716	reg = TRANSCONF(pipe);
		1717	val = I915_READ(reg);
3031	serge	1718	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1719
		1720	if (HAS_PCH_IBX(dev_priv->dev)) {
		1721	/*
		1722	* make the BPC in transcoder be consistent with
		1723	* that in pipeconf reg.
		1724	*/
3480	Serge	1725	val &= ~PIPECONF_BPC_MASK;
		1726	val \|= pipeconf_val & PIPECONF_BPC_MASK;
2327	Serge	1727	}
3031	serge	1728
		1729	val &= ~TRANS_INTERLACE_MASK;
		1730	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		1731	if (HAS_PCH_IBX(dev_priv->dev) &&
		1732	intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
		1733	val \|= TRANS_LEGACY_INTERLACED_ILK;
		1734	else
		1735	val \|= TRANS_INTERLACED;
		1736	else
		1737	val \|= TRANS_PROGRESSIVE;
		1738
2327	Serge	1739	I915_WRITE(reg, val \| TRANS_ENABLE);
		1740	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		1741	DRM_ERROR("failed to enable transcoder %d\n", pipe);
		1742	}
		1743
3243	Serge	1744	static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
		1745	enum transcoder cpu_transcoder)
		1746	{
		1747	u32 val, pipeconf_val;
		1748
		1749	/* PCH only available on ILK+ */
		1750	BUG_ON(dev_priv->info->gen < 5);
		1751
		1752	/* FDI must be feeding us bits for PCH ports */
3480	Serge	1753	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
3243	Serge	1754	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
		1755
		1756	/* Workaround: set timing override bit. */
		1757	val = I915_READ(_TRANSA_CHICKEN2);
		1758	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1759	I915_WRITE(_TRANSA_CHICKEN2, val);
		1760
		1761	val = TRANS_ENABLE;
		1762	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
		1763
		1764	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
		1765	PIPECONF_INTERLACED_ILK)
		1766	val \|= TRANS_INTERLACED;
		1767	else
		1768	val \|= TRANS_PROGRESSIVE;
		1769
		1770	I915_WRITE(TRANSCONF(TRANSCODER_A), val);
		1771	if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
		1772	DRM_ERROR("Failed to enable PCH transcoder\n");
		1773	}
		1774
		1775	static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1776	enum pipe pipe)
		1777	{
3243	Serge	1778	struct drm_device *dev = dev_priv->dev;
		1779	uint32_t reg, val;
2327	Serge	1780
		1781	/* FDI relies on the transcoder */
		1782	assert_fdi_tx_disabled(dev_priv, pipe);
		1783	assert_fdi_rx_disabled(dev_priv, pipe);
		1784
		1785	/* Ports must be off as well */
		1786	assert_pch_ports_disabled(dev_priv, pipe);
		1787
		1788	reg = TRANSCONF(pipe);
		1789	val = I915_READ(reg);
		1790	val &= ~TRANS_ENABLE;
		1791	I915_WRITE(reg, val);
		1792	/* wait for PCH transcoder off, transcoder state */
		1793	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2342	Serge	1794	DRM_ERROR("failed to disable transcoder %d\n", pipe);
3243	Serge	1795
		1796	if (!HAS_PCH_IBX(dev)) {
		1797	/* Workaround: Clear the timing override chicken bit again. */
		1798	reg = TRANS_CHICKEN2(pipe);
		1799	val = I915_READ(reg);
		1800	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1801	I915_WRITE(reg, val);
		1802	}
2327	Serge	1803	}
		1804
3243	Serge	1805	static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
		1806	{
		1807	u32 val;
		1808
		1809	val = I915_READ(_TRANSACONF);
		1810	val &= ~TRANS_ENABLE;
		1811	I915_WRITE(_TRANSACONF, val);
		1812	/* wait for PCH transcoder off, transcoder state */
		1813	if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
		1814	DRM_ERROR("Failed to disable PCH transcoder\n");
		1815
		1816	/* Workaround: clear timing override bit. */
		1817	val = I915_READ(_TRANSA_CHICKEN2);
		1818	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1819	I915_WRITE(_TRANSA_CHICKEN2, val);
		1820	}
		1821
2327	Serge	1822	/**
		1823	* intel_enable_pipe - enable a pipe, asserting requirements
		1824	* @dev_priv: i915 private structure
		1825	* @pipe: pipe to enable
		1826	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1827	*
		1828	* Enable @pipe, making sure that various hardware specific requirements
		1829	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1830	*
		1831	* @pipe should be %PIPE_A or %PIPE_B.
		1832	*
		1833	* Will wait until the pipe is actually running (i.e. first vblank) before
		1834	* returning.
		1835	*/
		1836	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1837	bool pch_port)
		1838	{
3243	Serge	1839	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1840	pipe);
3480	Serge	1841	enum pipe pch_transcoder;
2327	Serge	1842	int reg;
		1843	u32 val;
		1844
3480	Serge	1845	if (HAS_PCH_LPT(dev_priv->dev))
3243	Serge	1846	pch_transcoder = TRANSCODER_A;
		1847	else
		1848	pch_transcoder = pipe;
		1849
2327	Serge	1850	/*
		1851	* A pipe without a PLL won't actually be able to drive bits from
		1852	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1853	* need the check.
		1854	*/
		1855	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1856	assert_pll_enabled(dev_priv, pipe);
		1857	else {
		1858	if (pch_port) {
		1859	/* if driving the PCH, we need FDI enabled */
3243	Serge	1860	assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
3480	Serge	1861	assert_fdi_tx_pll_enabled(dev_priv,
		1862	(enum pipe) cpu_transcoder);
2327	Serge	1863	}
		1864	/* FIXME: assert CPU port conditions for SNB+ */
		1865	}
		1866
3243	Serge	1867	reg = PIPECONF(cpu_transcoder);
2327	Serge	1868	val = I915_READ(reg);
		1869	if (val & PIPECONF_ENABLE)
		1870	return;
		1871
		1872	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1873	intel_wait_for_vblank(dev_priv->dev, pipe);
		1874	}
		1875
		1876	/**
		1877	* intel_disable_pipe - disable a pipe, asserting requirements
		1878	* @dev_priv: i915 private structure
		1879	* @pipe: pipe to disable
		1880	*
		1881	* Disable @pipe, making sure that various hardware specific requirements
		1882	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1883	*
		1884	* @pipe should be %PIPE_A or %PIPE_B.
		1885	*
		1886	* Will wait until the pipe has shut down before returning.
		1887	*/
		1888	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1889	enum pipe pipe)
		1890	{
3243	Serge	1891	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1892	pipe);
2327	Serge	1893	int reg;
		1894	u32 val;
		1895
3031	serge	1896	/*
2327	Serge	1897	* Make sure planes won't keep trying to pump pixels to us,
		1898	* or we might hang the display.
		1899	*/
		1900	assert_planes_disabled(dev_priv, pipe);
3746	Serge	1901	assert_sprites_disabled(dev_priv, pipe);
2327	Serge	1902
		1903	/* Don't disable pipe A or pipe A PLLs if needed */
		1904	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1905	return;
		1906
3243	Serge	1907	reg = PIPECONF(cpu_transcoder);
2327	Serge	1908	val = I915_READ(reg);
		1909	if ((val & PIPECONF_ENABLE) == 0)
		1910	return;
		1911
		1912	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1913	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		1914	}
		1915
		1916	/*
		1917	* Plane regs are double buffered, going from enabled->disabled needs a
		1918	* trigger in order to latch. The display address reg provides this.
		1919	*/
3031	serge	1920	void intel_flush_display_plane(struct drm_i915_private *dev_priv,
2327	Serge	1921	enum plane plane)
		1922	{
3243	Serge	1923	if (dev_priv->info->gen >= 4)
		1924	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1925	else
2327	Serge	1926	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1927	}
		1928
		1929	/**
		1930	* intel_enable_plane - enable a display plane on a given pipe
		1931	* @dev_priv: i915 private structure
		1932	* @plane: plane to enable
		1933	* @pipe: pipe being fed
		1934	*
		1935	* Enable @plane on @pipe, making sure that @pipe is running first.
		1936	*/
		1937	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1938	enum plane plane, enum pipe pipe)
		1939	{
		1940	int reg;
		1941	u32 val;
		1942
		1943	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1944	assert_pipe_enabled(dev_priv, pipe);
		1945
		1946	reg = DSPCNTR(plane);
		1947	val = I915_READ(reg);
		1948	if (val & DISPLAY_PLANE_ENABLE)
		1949	return;
		1950
		1951	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1952	intel_flush_display_plane(dev_priv, plane);
		1953	intel_wait_for_vblank(dev_priv->dev, pipe);
		1954	}
		1955
		1956	/**
		1957	* intel_disable_plane - disable a display plane
		1958	* @dev_priv: i915 private structure
		1959	* @plane: plane to disable
		1960	* @pipe: pipe consuming the data
		1961	*
		1962	* Disable @plane; should be an independent operation.
		1963	*/
		1964	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1965	enum plane plane, enum pipe pipe)
		1966	{
		1967	int reg;
		1968	u32 val;
		1969
		1970	reg = DSPCNTR(plane);
		1971	val = I915_READ(reg);
		1972	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1973	return;
		1974
		1975	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1976	intel_flush_display_plane(dev_priv, plane);
3031	serge	1977	intel_wait_for_vblank(dev_priv->dev, pipe);
2327	Serge	1978	}
		1979
3746	Serge	1980	static bool need_vtd_wa(struct drm_device *dev)
		1981	{
		1982	#ifdef CONFIG_INTEL_IOMMU
		1983	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		1984	return true;
		1985	#endif
		1986	return false;
		1987	}
		1988
2335	Serge	1989	int
		1990	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1991	struct drm_i915_gem_object *obj,
		1992	struct intel_ring_buffer *pipelined)
		1993	{
		1994	struct drm_i915_private *dev_priv = dev->dev_private;
		1995	u32 alignment;
		1996	int ret;
2327	Serge	1997
2335	Serge	1998	switch (obj->tiling_mode) {
		1999	case I915_TILING_NONE:
		2000	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		2001	alignment = 128 * 1024;
		2002	else if (INTEL_INFO(dev)->gen >= 4)
		2003	alignment = 4 * 1024;
		2004	else
		2005	alignment = 64 * 1024;
		2006	break;
		2007	case I915_TILING_X:
		2008	/* pin() will align the object as required by fence */
		2009	alignment = 0;
		2010	break;
		2011	case I915_TILING_Y:
3746	Serge	2012	/* Despite that we check this in framebuffer_init userspace can
		2013	* screw us over and change the tiling after the fact. Only
		2014	* pinned buffers can't change their tiling. */
		2015	DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2335	Serge	2016	return -EINVAL;
		2017	default:
		2018	BUG();
		2019	}
2327	Serge	2020
3746	Serge	2021	/* Note that the w/a also requires 64 PTE of padding following the
		2022	* bo. We currently fill all unused PTE with the shadow page and so
		2023	* we should always have valid PTE following the scanout preventing
		2024	* the VT-d warning.
		2025	*/
		2026	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		2027	alignment = 256 * 1024;
		2028
2335	Serge	2029	dev_priv->mm.interruptible = false;
		2030	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		2031	if (ret)
		2032	goto err_interruptible;
2327	Serge	2033
2335	Serge	2034	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		2035	* fence, whereas 965+ only requires a fence if using
		2036	* framebuffer compression. For simplicity, we always install
		2037	* a fence as the cost is not that onerous.
		2038	*/
3480	Serge	2039	ret = i915_gem_object_get_fence(obj);
		2040	if (ret)
		2041	goto err_unpin;
2327	Serge	2042
3480	Serge	2043	i915_gem_object_pin_fence(obj);
		2044
2335	Serge	2045	dev_priv->mm.interruptible = true;
		2046	return 0;
2327	Serge	2047
2335	Serge	2048	err_unpin:
2344	Serge	2049	i915_gem_object_unpin(obj);
2335	Serge	2050	err_interruptible:
		2051	dev_priv->mm.interruptible = true;
		2052	return ret;
		2053	}
2327	Serge	2054
3031	serge	2055	void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
		2056	{
		2057	// i915_gem_object_unpin_fence(obj);
		2058	// i915_gem_object_unpin(obj);
		2059	}
		2060
		2061	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		2062	* is assumed to be a power-of-two. */
3480	Serge	2063	unsigned long intel_gen4_compute_page_offset(int x, int y,
		2064	unsigned int tiling_mode,
		2065	unsigned int cpp,
3031	serge	2066	unsigned int pitch)
		2067	{
3480	Serge	2068	if (tiling_mode != I915_TILING_NONE) {
		2069	unsigned int tile_rows, tiles;
3031	serge	2070
		2071	tile_rows = *y / 8;
		2072	*y %= 8;
		2073
3480	Serge	2074	tiles = *x / (512/cpp);
		2075	*x %= 512/cpp;
		2076
3031	serge	2077	return tile_rows * pitch * 8 + tiles * 4096;
3480	Serge	2078	} else {
		2079	unsigned int offset;
		2080
		2081	offset = y pitch + x cpp;
		2082	*y = 0;
		2083	*x = (offset & 4095) / cpp;
		2084	return offset & -4096;
		2085	}
3031	serge	2086	}
		2087
2327	Serge	2088	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		2089	int x, int y)
		2090	{
		2091	struct drm_device *dev = crtc->dev;
		2092	struct drm_i915_private *dev_priv = dev->dev_private;
		2093	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2094	struct intel_framebuffer *intel_fb;
		2095	struct drm_i915_gem_object *obj;
		2096	int plane = intel_crtc->plane;
3031	serge	2097	unsigned long linear_offset;
2327	Serge	2098	u32 dspcntr;
		2099	u32 reg;
		2100
		2101	switch (plane) {
		2102	case 0:
		2103	case 1:
		2104	break;
		2105	default:
		2106	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		2107	return -EINVAL;
		2108	}
		2109
		2110	intel_fb = to_intel_framebuffer(fb);
		2111	obj = intel_fb->obj;
		2112
		2113	reg = DSPCNTR(plane);
		2114	dspcntr = I915_READ(reg);
		2115	/* Mask out pixel format bits in case we change it */
		2116	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	2117	switch (fb->pixel_format) {
		2118	case DRM_FORMAT_C8:
2327	Serge	2119	dspcntr \|= DISPPLANE_8BPP;
		2120	break;
3243	Serge	2121	case DRM_FORMAT_XRGB1555:
		2122	case DRM_FORMAT_ARGB1555:
		2123	dspcntr \|= DISPPLANE_BGRX555;
		2124	break;
		2125	case DRM_FORMAT_RGB565:
		2126	dspcntr \|= DISPPLANE_BGRX565;
		2127	break;
		2128	case DRM_FORMAT_XRGB8888:
		2129	case DRM_FORMAT_ARGB8888:
		2130	dspcntr \|= DISPPLANE_BGRX888;
		2131	break;
		2132	case DRM_FORMAT_XBGR8888:
		2133	case DRM_FORMAT_ABGR8888:
		2134	dspcntr \|= DISPPLANE_RGBX888;
		2135	break;
		2136	case DRM_FORMAT_XRGB2101010:
		2137	case DRM_FORMAT_ARGB2101010:
		2138	dspcntr \|= DISPPLANE_BGRX101010;
2327	Serge	2139	break;
3243	Serge	2140	case DRM_FORMAT_XBGR2101010:
		2141	case DRM_FORMAT_ABGR2101010:
		2142	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	2143	break;
		2144	default:
3746	Serge	2145	BUG();
2327	Serge	2146	}
3243	Serge	2147
2327	Serge	2148	if (INTEL_INFO(dev)->gen >= 4) {
		2149	if (obj->tiling_mode != I915_TILING_NONE)
		2150	dspcntr \|= DISPPLANE_TILED;
		2151	else
		2152	dspcntr &= ~DISPPLANE_TILED;
		2153	}
		2154
		2155	I915_WRITE(reg, dspcntr);
		2156
3031	serge	2157	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327	Serge	2158
3031	serge	2159	if (INTEL_INFO(dev)->gen >= 4) {
		2160	intel_crtc->dspaddr_offset =
3480	Serge	2161	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2162	fb->bits_per_pixel / 8,
		2163	fb->pitches[0]);
		2164	linear_offset -= intel_crtc->dspaddr_offset;
		2165	} else {
		2166	intel_crtc->dspaddr_offset = linear_offset;
		2167	}
		2168
		2169	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		2170	obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2342	Serge	2171	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327	Serge	2172	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	2173	I915_MODIFY_DISPBASE(DSPSURF(plane),
		2174	obj->gtt_offset + intel_crtc->dspaddr_offset);
2327	Serge	2175	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2176	I915_WRITE(DSPLINOFF(plane), linear_offset);
2327	Serge	2177	} else
3031	serge	2178	I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2327	Serge	2179	POSTING_READ(reg);
		2180
		2181	return 0;
		2182	}
		2183
		2184	static int ironlake_update_plane(struct drm_crtc *crtc,
		2185	struct drm_framebuffer *fb, int x, int y)
		2186	{
		2187	struct drm_device *dev = crtc->dev;
		2188	struct drm_i915_private *dev_priv = dev->dev_private;
		2189	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2190	struct intel_framebuffer *intel_fb;
		2191	struct drm_i915_gem_object *obj;
		2192	int plane = intel_crtc->plane;
3031	serge	2193	unsigned long linear_offset;
2327	Serge	2194	u32 dspcntr;
		2195	u32 reg;
		2196
		2197	switch (plane) {
		2198	case 0:
		2199	case 1:
2342	Serge	2200	case 2:
2327	Serge	2201	break;
		2202	default:
		2203	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		2204	return -EINVAL;
		2205	}
		2206
		2207	intel_fb = to_intel_framebuffer(fb);
		2208	obj = intel_fb->obj;
		2209
		2210	reg = DSPCNTR(plane);
		2211	dspcntr = I915_READ(reg);
		2212	/* Mask out pixel format bits in case we change it */
		2213	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	2214	switch (fb->pixel_format) {
		2215	case DRM_FORMAT_C8:
2327	Serge	2216	dspcntr \|= DISPPLANE_8BPP;
		2217	break;
3243	Serge	2218	case DRM_FORMAT_RGB565:
		2219	dspcntr \|= DISPPLANE_BGRX565;
2327	Serge	2220	break;
3243	Serge	2221	case DRM_FORMAT_XRGB8888:
		2222	case DRM_FORMAT_ARGB8888:
		2223	dspcntr \|= DISPPLANE_BGRX888;
		2224	break;
		2225	case DRM_FORMAT_XBGR8888:
		2226	case DRM_FORMAT_ABGR8888:
		2227	dspcntr \|= DISPPLANE_RGBX888;
		2228	break;
		2229	case DRM_FORMAT_XRGB2101010:
		2230	case DRM_FORMAT_ARGB2101010:
		2231	dspcntr \|= DISPPLANE_BGRX101010;
		2232	break;
		2233	case DRM_FORMAT_XBGR2101010:
		2234	case DRM_FORMAT_ABGR2101010:
		2235	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	2236	break;
		2237	default:
3746	Serge	2238	BUG();
2327	Serge	2239	}
		2240
3480	Serge	2241	if (obj->tiling_mode != I915_TILING_NONE)
		2242	dspcntr \|= DISPPLANE_TILED;
		2243	else
2327	Serge	2244	dspcntr &= ~DISPPLANE_TILED;
		2245
		2246	/* must disable */
		2247	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2248
		2249	I915_WRITE(reg, dspcntr);
		2250
3031	serge	2251	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
		2252	intel_crtc->dspaddr_offset =
3480	Serge	2253	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2254	fb->bits_per_pixel / 8,
		2255	fb->pitches[0]);
		2256	linear_offset -= intel_crtc->dspaddr_offset;
2327	Serge	2257
3031	serge	2258	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		2259	obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2342	Serge	2260	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3031	serge	2261	I915_MODIFY_DISPBASE(DSPSURF(plane),
		2262	obj->gtt_offset + intel_crtc->dspaddr_offset);
3243	Serge	2263	if (IS_HASWELL(dev)) {
		2264	I915_WRITE(DSPOFFSET(plane), (y << 16) \| x);
		2265	} else {
2330	Serge	2266	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2267	I915_WRITE(DSPLINOFF(plane), linear_offset);
3243	Serge	2268	}
2330	Serge	2269	POSTING_READ(reg);
2327	Serge	2270
		2271	return 0;
		2272	}
		2273
		2274	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2275	static int
		2276	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2277	int x, int y, enum mode_set_atomic state)
		2278	{
		2279	struct drm_device *dev = crtc->dev;
		2280	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2281
		2282	if (dev_priv->display.disable_fbc)
		2283	dev_priv->display.disable_fbc(dev);
		2284	intel_increase_pllclock(crtc);
		2285
		2286	return dev_priv->display.update_plane(crtc, fb, x, y);
		2287	}
		2288
		2289	#if 0
		2290	static int
		2291	intel_finish_fb(struct drm_framebuffer *old_fb)
		2292	{
		2293	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
		2294	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		2295	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	2296	int ret;
		2297
3031	serge	2298	/* Big Hammer, we also need to ensure that any pending
		2299	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2300	* current scanout is retired before unpinning the old
		2301	* framebuffer.
		2302	*
		2303	* This should only fail upon a hung GPU, in which case we
		2304	* can safely continue.
		2305	*/
		2306	dev_priv->mm.interruptible = false;
		2307	ret = i915_gem_object_finish_gpu(obj);
		2308	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	2309
3031	serge	2310	return ret;
2327	Serge	2311	}
3031	serge	2312	#endif
2327	Serge	2313
		2314	static int
		2315	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
3031	serge	2316	struct drm_framebuffer *fb)
2327	Serge	2317	{
		2318	struct drm_device *dev = crtc->dev;
3031	serge	2319	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2320	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2321	struct drm_framebuffer *old_fb;
2342	Serge	2322	int ret;
2327	Serge	2323
		2324	/* no fb bound */
3031	serge	2325	if (!fb) {
2327	Serge	2326	DRM_ERROR("No FB bound\n");
		2327	return 0;
		2328	}
		2329
3746	Serge	2330	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
3031	serge	2331	DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
		2332	intel_crtc->plane,
3746	Serge	2333	INTEL_INFO(dev)->num_pipes);
2327	Serge	2334	return -EINVAL;
		2335	}
		2336
		2337	mutex_lock(&dev->struct_mutex);
3031	serge	2338	// ret = intel_pin_and_fence_fb_obj(dev,
		2339	// to_intel_framebuffer(fb)->obj,
		2340	// NULL);
		2341	// if (ret != 0) {
		2342	// mutex_unlock(&dev->struct_mutex);
		2343	// DRM_ERROR("pin & fence failed\n");
		2344	// return ret;
		2345	// }
2327	Serge	2346
3031	serge	2347
		2348	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2327	Serge	2349	if (ret) {
3031	serge	2350	intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2327	Serge	2351	mutex_unlock(&dev->struct_mutex);
		2352	DRM_ERROR("failed to update base address\n");
3243	Serge	2353	return ret;
2327	Serge	2354	}
		2355
3031	serge	2356	old_fb = crtc->fb;
		2357	crtc->fb = fb;
		2358	crtc->x = x;
		2359	crtc->y = y;
		2360
		2361	if (old_fb) {
		2362	intel_wait_for_vblank(dev, intel_crtc->pipe);
		2363	intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
		2364	}
		2365
		2366	intel_update_fbc(dev);
2336	Serge	2367	mutex_unlock(&dev->struct_mutex);
2327	Serge	2368
2336	Serge	2369	return 0;
2327	Serge	2370	}
		2371
		2372	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2373	{
		2374	struct drm_device *dev = crtc->dev;
		2375	struct drm_i915_private *dev_priv = dev->dev_private;
		2376	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2377	int pipe = intel_crtc->pipe;
		2378	u32 reg, temp;
		2379
		2380	/* enable normal train */
		2381	reg = FDI_TX_CTL(pipe);
		2382	temp = I915_READ(reg);
		2383	if (IS_IVYBRIDGE(dev)) {
		2384	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2385	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2386	} else {
		2387	temp &= ~FDI_LINK_TRAIN_NONE;
		2388	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2389	}
		2390	I915_WRITE(reg, temp);
		2391
		2392	reg = FDI_RX_CTL(pipe);
		2393	temp = I915_READ(reg);
		2394	if (HAS_PCH_CPT(dev)) {
		2395	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2396	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2397	} else {
		2398	temp &= ~FDI_LINK_TRAIN_NONE;
		2399	temp \|= FDI_LINK_TRAIN_NONE;
		2400	}
		2401	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2402
		2403	/* wait one idle pattern time */
		2404	POSTING_READ(reg);
		2405	udelay(1000);
		2406
		2407	/* IVB wants error correction enabled */
		2408	if (IS_IVYBRIDGE(dev))
		2409	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2410	FDI_FE_ERRC_ENABLE);
		2411	}
		2412
3243	Serge	2413	static void ivb_modeset_global_resources(struct drm_device *dev)
2327	Serge	2414	{
		2415	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2416	struct intel_crtc *pipe_B_crtc =
		2417	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		2418	struct intel_crtc *pipe_C_crtc =
		2419	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
		2420	uint32_t temp;
2327	Serge	2421
3243	Serge	2422	/* When everything is off disable fdi C so that we could enable fdi B
		2423	* with all lanes. XXX: This misses the case where a pipe is not using
		2424	* any pch resources and so doesn't need any fdi lanes. */
		2425	if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
		2426	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		2427	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		2428
		2429	temp = I915_READ(SOUTH_CHICKEN1);
		2430	temp &= ~FDI_BC_BIFURCATION_SELECT;
		2431	DRM_DEBUG_KMS("disabling fdi C rx\n");
		2432	I915_WRITE(SOUTH_CHICKEN1, temp);
		2433	}
2327	Serge	2434	}
		2435
		2436	/* The FDI link training functions for ILK/Ibexpeak. */
		2437	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2438	{
		2439	struct drm_device *dev = crtc->dev;
		2440	struct drm_i915_private *dev_priv = dev->dev_private;
		2441	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2442	int pipe = intel_crtc->pipe;
		2443	int plane = intel_crtc->plane;
		2444	u32 reg, temp, tries;
		2445
		2446	/* FDI needs bits from pipe & plane first */
		2447	assert_pipe_enabled(dev_priv, pipe);
		2448	assert_plane_enabled(dev_priv, plane);
		2449
		2450	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2451	for train result */
		2452	reg = FDI_RX_IMR(pipe);
		2453	temp = I915_READ(reg);
		2454	temp &= ~FDI_RX_SYMBOL_LOCK;
		2455	temp &= ~FDI_RX_BIT_LOCK;
		2456	I915_WRITE(reg, temp);
		2457	I915_READ(reg);
		2458	udelay(150);
		2459
		2460	/* enable CPU FDI TX and PCH FDI RX */
		2461	reg = FDI_TX_CTL(pipe);
		2462	temp = I915_READ(reg);
		2463	temp &= ~(7 << 19);
		2464	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2465	temp &= ~FDI_LINK_TRAIN_NONE;
		2466	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2467	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2468
		2469	reg = FDI_RX_CTL(pipe);
		2470	temp = I915_READ(reg);
		2471	temp &= ~FDI_LINK_TRAIN_NONE;
		2472	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2473	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2474
		2475	POSTING_READ(reg);
		2476	udelay(150);
		2477
		2478	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2479	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2480	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2481	FDI_RX_PHASE_SYNC_POINTER_EN);
		2482
		2483	reg = FDI_RX_IIR(pipe);
		2484	for (tries = 0; tries < 5; tries++) {
		2485	temp = I915_READ(reg);
		2486	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2487
		2488	if ((temp & FDI_RX_BIT_LOCK)) {
		2489	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2490	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2491	break;
		2492	}
		2493	}
		2494	if (tries == 5)
		2495	DRM_ERROR("FDI train 1 fail!\n");
		2496
		2497	/* Train 2 */
		2498	reg = FDI_TX_CTL(pipe);
		2499	temp = I915_READ(reg);
		2500	temp &= ~FDI_LINK_TRAIN_NONE;
		2501	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2502	I915_WRITE(reg, temp);
		2503
		2504	reg = FDI_RX_CTL(pipe);
		2505	temp = I915_READ(reg);
		2506	temp &= ~FDI_LINK_TRAIN_NONE;
		2507	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2508	I915_WRITE(reg, temp);
		2509
		2510	POSTING_READ(reg);
		2511	udelay(150);
		2512
		2513	reg = FDI_RX_IIR(pipe);
		2514	for (tries = 0; tries < 5; tries++) {
		2515	temp = I915_READ(reg);
		2516	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2517
		2518	if (temp & FDI_RX_SYMBOL_LOCK) {
		2519	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2520	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2521	break;
		2522	}
		2523	}
		2524	if (tries == 5)
		2525	DRM_ERROR("FDI train 2 fail!\n");
		2526
		2527	DRM_DEBUG_KMS("FDI train done\n");
		2528
		2529	}
		2530
2342	Serge	2531	static const int snb_b_fdi_train_param[] = {
2327	Serge	2532	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2533	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2534	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2535	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2536	};
		2537
		2538	/* The FDI link training functions for SNB/Cougarpoint. */
		2539	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2540	{
		2541	struct drm_device *dev = crtc->dev;
		2542	struct drm_i915_private *dev_priv = dev->dev_private;
		2543	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2544	int pipe = intel_crtc->pipe;
3031	serge	2545	u32 reg, temp, i, retry;
2327	Serge	2546
		2547	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2548	for train result */
		2549	reg = FDI_RX_IMR(pipe);
		2550	temp = I915_READ(reg);
		2551	temp &= ~FDI_RX_SYMBOL_LOCK;
		2552	temp &= ~FDI_RX_BIT_LOCK;
		2553	I915_WRITE(reg, temp);
		2554
		2555	POSTING_READ(reg);
		2556	udelay(150);
		2557
		2558	/* enable CPU FDI TX and PCH FDI RX */
		2559	reg = FDI_TX_CTL(pipe);
		2560	temp = I915_READ(reg);
		2561	temp &= ~(7 << 19);
		2562	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2563	temp &= ~FDI_LINK_TRAIN_NONE;
		2564	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2565	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2566	/* SNB-B */
		2567	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2568	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2569
3243	Serge	2570	I915_WRITE(FDI_RX_MISC(pipe),
		2571	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2572
2327	Serge	2573	reg = FDI_RX_CTL(pipe);
		2574	temp = I915_READ(reg);
		2575	if (HAS_PCH_CPT(dev)) {
		2576	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2577	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2578	} else {
		2579	temp &= ~FDI_LINK_TRAIN_NONE;
		2580	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2581	}
		2582	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2583
		2584	POSTING_READ(reg);
		2585	udelay(150);
		2586
2342	Serge	2587	for (i = 0; i < 4; i++) {
2327	Serge	2588	reg = FDI_TX_CTL(pipe);
		2589	temp = I915_READ(reg);
		2590	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2591	temp \|= snb_b_fdi_train_param[i];
		2592	I915_WRITE(reg, temp);
		2593
		2594	POSTING_READ(reg);
		2595	udelay(500);
		2596
3031	serge	2597	for (retry = 0; retry < 5; retry++) {
2327	Serge	2598	reg = FDI_RX_IIR(pipe);
		2599	temp = I915_READ(reg);
		2600	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2601	if (temp & FDI_RX_BIT_LOCK) {
		2602	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2603	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2604	break;
		2605	}
3031	serge	2606	udelay(50);
		2607	}
		2608	if (retry < 5)
		2609	break;
2327	Serge	2610	}
		2611	if (i == 4)
		2612	DRM_ERROR("FDI train 1 fail!\n");
		2613
		2614	/* Train 2 */
		2615	reg = FDI_TX_CTL(pipe);
		2616	temp = I915_READ(reg);
		2617	temp &= ~FDI_LINK_TRAIN_NONE;
		2618	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2619	if (IS_GEN6(dev)) {
		2620	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2621	/* SNB-B */
		2622	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2623	}
		2624	I915_WRITE(reg, temp);
		2625
		2626	reg = FDI_RX_CTL(pipe);
		2627	temp = I915_READ(reg);
		2628	if (HAS_PCH_CPT(dev)) {
		2629	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2630	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2631	} else {
		2632	temp &= ~FDI_LINK_TRAIN_NONE;
		2633	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2634	}
		2635	I915_WRITE(reg, temp);
		2636
		2637	POSTING_READ(reg);
		2638	udelay(150);
		2639
2342	Serge	2640	for (i = 0; i < 4; i++) {
2327	Serge	2641	reg = FDI_TX_CTL(pipe);
		2642	temp = I915_READ(reg);
		2643	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2644	temp \|= snb_b_fdi_train_param[i];
		2645	I915_WRITE(reg, temp);
		2646
		2647	POSTING_READ(reg);
		2648	udelay(500);
		2649
3031	serge	2650	for (retry = 0; retry < 5; retry++) {
2327	Serge	2651	reg = FDI_RX_IIR(pipe);
		2652	temp = I915_READ(reg);
		2653	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2654	if (temp & FDI_RX_SYMBOL_LOCK) {
		2655	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2656	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2657	break;
		2658	}
3031	serge	2659	udelay(50);
		2660	}
		2661	if (retry < 5)
		2662	break;
2327	Serge	2663	}
		2664	if (i == 4)
		2665	DRM_ERROR("FDI train 2 fail!\n");
		2666
		2667	DRM_DEBUG_KMS("FDI train done.\n");
		2668	}
		2669
		2670	/* Manual link training for Ivy Bridge A0 parts */
		2671	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2672	{
		2673	struct drm_device *dev = crtc->dev;
		2674	struct drm_i915_private *dev_priv = dev->dev_private;
		2675	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2676	int pipe = intel_crtc->pipe;
		2677	u32 reg, temp, i;
		2678
		2679	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2680	for train result */
		2681	reg = FDI_RX_IMR(pipe);
		2682	temp = I915_READ(reg);
		2683	temp &= ~FDI_RX_SYMBOL_LOCK;
		2684	temp &= ~FDI_RX_BIT_LOCK;
		2685	I915_WRITE(reg, temp);
		2686
		2687	POSTING_READ(reg);
		2688	udelay(150);
		2689
3243	Serge	2690	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		2691	I915_READ(FDI_RX_IIR(pipe)));
		2692
2327	Serge	2693	/* enable CPU FDI TX and PCH FDI RX */
		2694	reg = FDI_TX_CTL(pipe);
		2695	temp = I915_READ(reg);
		2696	temp &= ~(7 << 19);
		2697	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2698	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2699	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2700	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2701	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2342	Serge	2702	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2703	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2704
3243	Serge	2705	I915_WRITE(FDI_RX_MISC(pipe),
		2706	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2707
2327	Serge	2708	reg = FDI_RX_CTL(pipe);
		2709	temp = I915_READ(reg);
		2710	temp &= ~FDI_LINK_TRAIN_AUTO;
		2711	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2712	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342	Serge	2713	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2714	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2715
		2716	POSTING_READ(reg);
		2717	udelay(150);
		2718
2342	Serge	2719	for (i = 0; i < 4; i++) {
2327	Serge	2720	reg = FDI_TX_CTL(pipe);
		2721	temp = I915_READ(reg);
		2722	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2723	temp \|= snb_b_fdi_train_param[i];
		2724	I915_WRITE(reg, temp);
		2725
		2726	POSTING_READ(reg);
		2727	udelay(500);
		2728
		2729	reg = FDI_RX_IIR(pipe);
		2730	temp = I915_READ(reg);
		2731	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2732
		2733	if (temp & FDI_RX_BIT_LOCK \|\|
		2734	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2735	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
3243	Serge	2736	DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2327	Serge	2737	break;
		2738	}
		2739	}
		2740	if (i == 4)
		2741	DRM_ERROR("FDI train 1 fail!\n");
		2742
		2743	/* Train 2 */
		2744	reg = FDI_TX_CTL(pipe);
		2745	temp = I915_READ(reg);
		2746	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2747	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2748	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2749	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2750	I915_WRITE(reg, temp);
		2751
		2752	reg = FDI_RX_CTL(pipe);
		2753	temp = I915_READ(reg);
		2754	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2755	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2756	I915_WRITE(reg, temp);
		2757
		2758	POSTING_READ(reg);
		2759	udelay(150);
		2760
2342	Serge	2761	for (i = 0; i < 4; i++) {
2327	Serge	2762	reg = FDI_TX_CTL(pipe);
		2763	temp = I915_READ(reg);
		2764	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2765	temp \|= snb_b_fdi_train_param[i];
		2766	I915_WRITE(reg, temp);
		2767
		2768	POSTING_READ(reg);
		2769	udelay(500);
		2770
		2771	reg = FDI_RX_IIR(pipe);
		2772	temp = I915_READ(reg);
		2773	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2774
		2775	if (temp & FDI_RX_SYMBOL_LOCK) {
		2776	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
3243	Serge	2777	DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2327	Serge	2778	break;
		2779	}
		2780	}
		2781	if (i == 4)
		2782	DRM_ERROR("FDI train 2 fail!\n");
		2783
		2784	DRM_DEBUG_KMS("FDI train done.\n");
		2785	}
		2786
3031	serge	2787	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	2788	{
3031	serge	2789	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	2790	struct drm_i915_private *dev_priv = dev->dev_private;
		2791	int pipe = intel_crtc->pipe;
		2792	u32 reg, temp;
		2793
		2794
		2795	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2796	reg = FDI_RX_CTL(pipe);
		2797	temp = I915_READ(reg);
		2798	temp &= ~((0x7 << 19) \| (0x7 << 16));
		2799	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
3480	Serge	2800	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2801	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2802
		2803	POSTING_READ(reg);
		2804	udelay(200);
		2805
		2806	/* Switch from Rawclk to PCDclk */
		2807	temp = I915_READ(reg);
		2808	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2809
		2810	POSTING_READ(reg);
		2811	udelay(200);
		2812
		2813	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2814	reg = FDI_TX_CTL(pipe);
		2815	temp = I915_READ(reg);
		2816	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2817	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2818
		2819	POSTING_READ(reg);
		2820	udelay(100);
		2821	}
		2822	}
		2823
3031	serge	2824	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		2825	{
		2826	struct drm_device *dev = intel_crtc->base.dev;
		2827	struct drm_i915_private *dev_priv = dev->dev_private;
		2828	int pipe = intel_crtc->pipe;
		2829	u32 reg, temp;
		2830
		2831	/* Switch from PCDclk to Rawclk */
		2832	reg = FDI_RX_CTL(pipe);
		2833	temp = I915_READ(reg);
		2834	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		2835
		2836	/* Disable CPU FDI TX PLL */
		2837	reg = FDI_TX_CTL(pipe);
		2838	temp = I915_READ(reg);
		2839	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		2840
		2841	POSTING_READ(reg);
		2842	udelay(100);
		2843
		2844	reg = FDI_RX_CTL(pipe);
		2845	temp = I915_READ(reg);
		2846	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		2847
		2848	/* Wait for the clocks to turn off. */
		2849	POSTING_READ(reg);
		2850	udelay(100);
		2851	}
		2852
2327	Serge	2853	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2854	{
		2855	struct drm_device *dev = crtc->dev;
		2856	struct drm_i915_private *dev_priv = dev->dev_private;
		2857	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2858	int pipe = intel_crtc->pipe;
		2859	u32 reg, temp;
		2860
		2861	/* disable CPU FDI tx and PCH FDI rx */
		2862	reg = FDI_TX_CTL(pipe);
		2863	temp = I915_READ(reg);
		2864	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2865	POSTING_READ(reg);
		2866
		2867	reg = FDI_RX_CTL(pipe);
		2868	temp = I915_READ(reg);
		2869	temp &= ~(0x7 << 16);
3480	Serge	2870	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2871	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2872
		2873	POSTING_READ(reg);
		2874	udelay(100);
		2875
		2876	/* Ironlake workaround, disable clock pointer after downing FDI */
		2877	if (HAS_PCH_IBX(dev)) {
		2878	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2879	}
		2880
		2881	/* still set train pattern 1 */
		2882	reg = FDI_TX_CTL(pipe);
		2883	temp = I915_READ(reg);
		2884	temp &= ~FDI_LINK_TRAIN_NONE;
		2885	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2886	I915_WRITE(reg, temp);
		2887
		2888	reg = FDI_RX_CTL(pipe);
		2889	temp = I915_READ(reg);
		2890	if (HAS_PCH_CPT(dev)) {
		2891	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2892	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2893	} else {
		2894	temp &= ~FDI_LINK_TRAIN_NONE;
		2895	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2896	}
		2897	/* BPC in FDI rx is consistent with that in PIPECONF */
		2898	temp &= ~(0x07 << 16);
3480	Serge	2899	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2900	I915_WRITE(reg, temp);
		2901
		2902	POSTING_READ(reg);
		2903	udelay(100);
		2904	}
		2905
3031	serge	2906	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2327	Serge	2907	{
3031	serge	2908	struct drm_device *dev = crtc->dev;
2327	Serge	2909	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	2910	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2911	unsigned long flags;
		2912	bool pending;
2327	Serge	2913
3480	Serge	2914	if (i915_reset_in_progress(&dev_priv->gpu_error) \|\|
		2915	intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3031	serge	2916	return false;
2327	Serge	2917
3031	serge	2918	spin_lock_irqsave(&dev->event_lock, flags);
		2919	pending = to_intel_crtc(crtc)->unpin_work != NULL;
		2920	spin_unlock_irqrestore(&dev->event_lock, flags);
		2921
		2922	return pending;
2327	Serge	2923	}
		2924
3031	serge	2925	#if 0
2327	Serge	2926	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2927	{
3031	serge	2928	struct drm_device *dev = crtc->dev;
		2929	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2930
		2931	if (crtc->fb == NULL)
		2932	return;
		2933
3480	Serge	2934	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
		2935
2360	Serge	2936	wait_event(dev_priv->pending_flip_queue,
3031	serge	2937	!intel_crtc_has_pending_flip(crtc));
		2938
		2939	mutex_lock(&dev->struct_mutex);
		2940	intel_finish_fb(crtc->fb);
		2941	mutex_unlock(&dev->struct_mutex);
2327	Serge	2942	}
3031	serge	2943	#endif
2327	Serge	2944
		2945
		2946
3031	serge	2947	/* Program iCLKIP clock to the desired frequency */
		2948	static void lpt_program_iclkip(struct drm_crtc *crtc)
		2949	{
		2950	struct drm_device *dev = crtc->dev;
		2951	struct drm_i915_private *dev_priv = dev->dev_private;
		2952	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		2953	u32 temp;
		2954
3480	Serge	2955	mutex_lock(&dev_priv->dpio_lock);
		2956
3031	serge	2957	/* It is necessary to ungate the pixclk gate prior to programming
		2958	* the divisors, and gate it back when it is done.
		2959	*/
		2960	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		2961
		2962	/* Disable SSCCTL */
		2963	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3243	Serge	2964	intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) \|
		2965	SBI_SSCCTL_DISABLE,
		2966	SBI_ICLK);
3031	serge	2967
		2968	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
		2969	if (crtc->mode.clock == 20000) {
		2970	auxdiv = 1;
		2971	divsel = 0x41;
		2972	phaseinc = 0x20;
		2973	} else {
		2974	/* The iCLK virtual clock root frequency is in MHz,
		2975	* but the crtc->mode.clock in in KHz. To get the divisors,
		2976	* it is necessary to divide one by another, so we
		2977	* convert the virtual clock precision to KHz here for higher
		2978	* precision.
		2979	*/
		2980	u32 iclk_virtual_root_freq = 172800 * 1000;
		2981	u32 iclk_pi_range = 64;
		2982	u32 desired_divisor, msb_divisor_value, pi_value;
		2983
		2984	desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		2985	msb_divisor_value = desired_divisor / iclk_pi_range;
		2986	pi_value = desired_divisor % iclk_pi_range;
		2987
		2988	auxdiv = 0;
		2989	divsel = msb_divisor_value - 2;
		2990	phaseinc = pi_value;
		2991	}
		2992
		2993	/* This should not happen with any sane values */
		2994	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		2995	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		2996	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		2997	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		2998
		2999	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
		3000	crtc->mode.clock,
		3001	auxdiv,
		3002	divsel,
		3003	phasedir,
		3004	phaseinc);
		3005
		3006	/* Program SSCDIVINTPHASE6 */
3243	Serge	3007	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3031	serge	3008	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		3009	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		3010	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		3011	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		3012	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		3013	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
3243	Serge	3014	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031	serge	3015
		3016	/* Program SSCAUXDIV */
3243	Serge	3017	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3031	serge	3018	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		3019	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3243	Serge	3020	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3031	serge	3021
		3022	/* Enable modulator and associated divider */
3243	Serge	3023	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3031	serge	3024	temp &= ~SBI_SSCCTL_DISABLE;
3243	Serge	3025	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3031	serge	3026
		3027	/* Wait for initialization time */
		3028	udelay(24);
		3029
		3030	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3480	Serge	3031
		3032	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	3033	}
		3034
2327	Serge	3035	/*
		3036	* Enable PCH resources required for PCH ports:
		3037	* - PCH PLLs
		3038	* - FDI training & RX/TX
		3039	* - update transcoder timings
		3040	* - DP transcoding bits
		3041	* - transcoder
		3042	*/
		3043	static void ironlake_pch_enable(struct drm_crtc *crtc)
		3044	{
		3045	struct drm_device *dev = crtc->dev;
		3046	struct drm_i915_private *dev_priv = dev->dev_private;
		3047	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3048	int pipe = intel_crtc->pipe;
3031	serge	3049	u32 reg, temp;
2327	Serge	3050
3031	serge	3051	assert_transcoder_disabled(dev_priv, pipe);
		3052
3243	Serge	3053	/* Write the TU size bits before fdi link training, so that error
		3054	* detection works. */
		3055	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		3056	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		3057
2327	Serge	3058	/* For PCH output, training FDI link */
		3059	dev_priv->display.fdi_link_train(crtc);
		3060
3243	Serge	3061	/* XXX: pch pll's can be enabled any time before we enable the PCH
		3062	* transcoder, and we actually should do this to not upset any PCH
		3063	* transcoder that already use the clock when we share it.
		3064	*
		3065	* Note that enable_pch_pll tries to do the right thing, but get_pch_pll
		3066	* unconditionally resets the pll - we need that to have the right LVDS
		3067	* enable sequence. */
		3068	ironlake_enable_pch_pll(intel_crtc);
2327	Serge	3069
3243	Serge	3070	if (HAS_PCH_CPT(dev)) {
3031	serge	3071	u32 sel;
2342	Serge	3072
2327	Serge	3073	temp = I915_READ(PCH_DPLL_SEL);
3031	serge	3074	switch (pipe) {
		3075	default:
		3076	case 0:
		3077	temp \|= TRANSA_DPLL_ENABLE;
		3078	sel = TRANSA_DPLLB_SEL;
		3079	break;
		3080	case 1:
		3081	temp \|= TRANSB_DPLL_ENABLE;
		3082	sel = TRANSB_DPLLB_SEL;
		3083	break;
		3084	case 2:
		3085	temp \|= TRANSC_DPLL_ENABLE;
		3086	sel = TRANSC_DPLLB_SEL;
		3087	break;
2342	Serge	3088	}
3031	serge	3089	if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
		3090	temp \|= sel;
		3091	else
		3092	temp &= ~sel;
2327	Serge	3093	I915_WRITE(PCH_DPLL_SEL, temp);
		3094	}
		3095
		3096	/* set transcoder timing, panel must allow it */
		3097	assert_panel_unlocked(dev_priv, pipe);
		3098	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
		3099	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
		3100	I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
		3101
		3102	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
		3103	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
		3104	I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3031	serge	3105	I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2327	Serge	3106
		3107	intel_fdi_normal_train(crtc);
		3108
		3109	/* For PCH DP, enable TRANS_DP_CTL */
		3110	if (HAS_PCH_CPT(dev) &&
2342	Serge	3111	(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		3112	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3480	Serge	3113	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2327	Serge	3114	reg = TRANS_DP_CTL(pipe);
		3115	temp = I915_READ(reg);
		3116	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		3117	TRANS_DP_SYNC_MASK \|
		3118	TRANS_DP_BPC_MASK);
		3119	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		3120	TRANS_DP_ENH_FRAMING);
		3121	temp \|= bpc << 9; /* same format but at 11:9 */
		3122
		3123	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		3124	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		3125	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		3126	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		3127
		3128	switch (intel_trans_dp_port_sel(crtc)) {
		3129	case PCH_DP_B:
		3130	temp \|= TRANS_DP_PORT_SEL_B;
		3131	break;
		3132	case PCH_DP_C:
		3133	temp \|= TRANS_DP_PORT_SEL_C;
		3134	break;
		3135	case PCH_DP_D:
		3136	temp \|= TRANS_DP_PORT_SEL_D;
		3137	break;
		3138	default:
3243	Serge	3139	BUG();
2327	Serge	3140	}
		3141
		3142	I915_WRITE(reg, temp);
		3143	}
		3144
3243	Serge	3145	ironlake_enable_pch_transcoder(dev_priv, pipe);
2327	Serge	3146	}
		3147
3243	Serge	3148	static void lpt_pch_enable(struct drm_crtc *crtc)
		3149	{
		3150	struct drm_device *dev = crtc->dev;
		3151	struct drm_i915_private *dev_priv = dev->dev_private;
		3152	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	3153	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3154
		3155	assert_transcoder_disabled(dev_priv, TRANSCODER_A);
		3156
		3157	lpt_program_iclkip(crtc);
		3158
		3159	/* Set transcoder timing. */
		3160	I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
		3161	I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
		3162	I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
		3163
		3164	I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
		3165	I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
		3166	I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
		3167	I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
		3168
		3169	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
		3170	}
		3171
3031	serge	3172	static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
		3173	{
		3174	struct intel_pch_pll *pll = intel_crtc->pch_pll;
		3175
		3176	if (pll == NULL)
		3177	return;
		3178
		3179	if (pll->refcount == 0) {
		3180	WARN(1, "bad PCH PLL refcount\n");
		3181	return;
		3182	}
		3183
		3184	--pll->refcount;
		3185	intel_crtc->pch_pll = NULL;
		3186	}
		3187
		3188	static struct intel_pch_pll intel_get_pch_pll(struct intel_crtc intel_crtc, u32 dpll, u32 fp)
		3189	{
		3190	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		3191	struct intel_pch_pll *pll;
		3192	int i;
		3193
		3194	pll = intel_crtc->pch_pll;
		3195	if (pll) {
		3196	DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
		3197	intel_crtc->base.base.id, pll->pll_reg);
		3198	goto prepare;
		3199	}
		3200
		3201	if (HAS_PCH_IBX(dev_priv->dev)) {
		3202	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
		3203	i = intel_crtc->pipe;
		3204	pll = &dev_priv->pch_plls[i];
		3205
		3206	DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
		3207	intel_crtc->base.base.id, pll->pll_reg);
		3208
		3209	goto found;
		3210	}
		3211
		3212	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		3213	pll = &dev_priv->pch_plls[i];
		3214
		3215	/* Only want to check enabled timings first */
		3216	if (pll->refcount == 0)
		3217	continue;
		3218
		3219	if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
		3220	fp == I915_READ(pll->fp0_reg)) {
		3221	DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
		3222	intel_crtc->base.base.id,
		3223	pll->pll_reg, pll->refcount, pll->active);
		3224
		3225	goto found;
		3226	}
		3227	}
		3228
		3229	/* Ok no matching timings, maybe there's a free one? */
		3230	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		3231	pll = &dev_priv->pch_plls[i];
		3232	if (pll->refcount == 0) {
		3233	DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
		3234	intel_crtc->base.base.id, pll->pll_reg);
		3235	goto found;
		3236	}
		3237	}
		3238
		3239	return NULL;
		3240
		3241	found:
		3242	intel_crtc->pch_pll = pll;
		3243	pll->refcount++;
		3244	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
		3245	prepare: /* separate function? */
		3246	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
		3247
		3248	/* Wait for the clocks to stabilize before rewriting the regs */
		3249	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
		3250	POSTING_READ(pll->pll_reg);
		3251	udelay(150);
		3252
		3253	I915_WRITE(pll->fp0_reg, fp);
		3254	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
		3255	pll->on = false;
		3256	return pll;
		3257	}
		3258
2342	Serge	3259	void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
		3260	{
		3261	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3262	int dslreg = PIPEDSL(pipe);
2342	Serge	3263	u32 temp;
		3264
		3265	temp = I915_READ(dslreg);
		3266	udelay(500);
		3267	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		3268	if (wait_for(I915_READ(dslreg) != temp, 5))
		3269	DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
		3270	}
		3271	}
		3272
2327	Serge	3273	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		3274	{
		3275	struct drm_device *dev = crtc->dev;
		3276	struct drm_i915_private *dev_priv = dev->dev_private;
		3277	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3278	struct intel_encoder *encoder;
2327	Serge	3279	int pipe = intel_crtc->pipe;
		3280	int plane = intel_crtc->plane;
		3281	u32 temp;
		3282
3031	serge	3283	WARN_ON(!crtc->enabled);
		3284
2327	Serge	3285	if (intel_crtc->active)
		3286	return;
		3287
		3288	intel_crtc->active = true;
		3289	intel_update_watermarks(dev);
		3290
		3291	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		3292	temp = I915_READ(PCH_LVDS);
		3293	if ((temp & LVDS_PORT_EN) == 0)
		3294	I915_WRITE(PCH_LVDS, temp \| LVDS_PORT_EN);
		3295	}
		3296
		3297
3746	Serge	3298	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3299	/* Note: FDI PLL enabling _must_ be done before we enable the
		3300	* cpu pipes, hence this is separate from all the other fdi/pch
		3301	* enabling. */
3031	serge	3302	ironlake_fdi_pll_enable(intel_crtc);
		3303	} else {
		3304	assert_fdi_tx_disabled(dev_priv, pipe);
		3305	assert_fdi_rx_disabled(dev_priv, pipe);
		3306	}
2327	Serge	3307
3031	serge	3308	for_each_encoder_on_crtc(dev, crtc, encoder)
		3309	if (encoder->pre_enable)
		3310	encoder->pre_enable(encoder);
		3311
2327	Serge	3312	/* Enable panel fitting for LVDS */
		3313	if (dev_priv->pch_pf_size &&
3243	Serge	3314	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\|
		3315	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2327	Serge	3316	/* Force use of hard-coded filter coefficients
		3317	* as some pre-programmed values are broken,
		3318	* e.g. x201.
		3319	*/
3243	Serge	3320	if (IS_IVYBRIDGE(dev))
		3321	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3 \|
		3322	PF_PIPE_SEL_IVB(pipe));
		3323	else
2327	Serge	3324	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		3325	I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		3326	I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
		3327	}
		3328
		3329	/*
		3330	* On ILK+ LUT must be loaded before the pipe is running but with
		3331	* clocks enabled
		3332	*/
		3333	intel_crtc_load_lut(crtc);
		3334
3746	Serge	3335	intel_enable_pipe(dev_priv, pipe,
		3336	intel_crtc->config.has_pch_encoder);
2327	Serge	3337	intel_enable_plane(dev_priv, plane, pipe);
		3338
3746	Serge	3339	if (intel_crtc->config.has_pch_encoder)
2327	Serge	3340	ironlake_pch_enable(crtc);
		3341
		3342	mutex_lock(&dev->struct_mutex);
		3343	intel_update_fbc(dev);
		3344	mutex_unlock(&dev->struct_mutex);
		3345
		3346	// intel_crtc_update_cursor(crtc, true);
3031	serge	3347
		3348	for_each_encoder_on_crtc(dev, crtc, encoder)
		3349	encoder->enable(encoder);
		3350
		3351	if (HAS_PCH_CPT(dev))
		3352	intel_cpt_verify_modeset(dev, intel_crtc->pipe);
		3353
		3354	/*
		3355	* There seems to be a race in PCH platform hw (at least on some
		3356	* outputs) where an enabled pipe still completes any pageflip right
		3357	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3358	* as the first vblank happend, everything works as expected. Hence just
		3359	* wait for one vblank before returning to avoid strange things
		3360	* happening.
		3361	*/
		3362	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	3363	}
		3364
3243	Serge	3365	static void haswell_crtc_enable(struct drm_crtc *crtc)
		3366	{
		3367	struct drm_device *dev = crtc->dev;
		3368	struct drm_i915_private *dev_priv = dev->dev_private;
		3369	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3370	struct intel_encoder *encoder;
		3371	int pipe = intel_crtc->pipe;
		3372	int plane = intel_crtc->plane;
		3373
		3374	WARN_ON(!crtc->enabled);
		3375
		3376	if (intel_crtc->active)
		3377	return;
		3378
		3379	intel_crtc->active = true;
		3380	intel_update_watermarks(dev);
		3381
3746	Serge	3382	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3383	dev_priv->display.fdi_link_train(crtc);
		3384
		3385	for_each_encoder_on_crtc(dev, crtc, encoder)
		3386	if (encoder->pre_enable)
		3387	encoder->pre_enable(encoder);
		3388
		3389	intel_ddi_enable_pipe_clock(intel_crtc);
		3390
		3391	/* Enable panel fitting for eDP */
		3392	if (dev_priv->pch_pf_size &&
		3393	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		3394	/* Force use of hard-coded filter coefficients
		3395	* as some pre-programmed values are broken,
		3396	* e.g. x201.
		3397	*/
		3398	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3 \|
		3399	PF_PIPE_SEL_IVB(pipe));
		3400	I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		3401	I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
		3402	}
		3403
		3404	/*
		3405	* On ILK+ LUT must be loaded before the pipe is running but with
		3406	* clocks enabled
		3407	*/
		3408	intel_crtc_load_lut(crtc);
		3409
		3410	intel_ddi_set_pipe_settings(crtc);
3746	Serge	3411	intel_ddi_enable_transcoder_func(crtc);
3243	Serge	3412
3746	Serge	3413	intel_enable_pipe(dev_priv, pipe,
		3414	intel_crtc->config.has_pch_encoder);
3243	Serge	3415	intel_enable_plane(dev_priv, plane, pipe);
		3416
3746	Serge	3417	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3418	lpt_pch_enable(crtc);
		3419
		3420	mutex_lock(&dev->struct_mutex);
		3421	intel_update_fbc(dev);
		3422	mutex_unlock(&dev->struct_mutex);
		3423
		3424	// intel_crtc_update_cursor(crtc, true);
		3425
		3426	for_each_encoder_on_crtc(dev, crtc, encoder)
		3427	encoder->enable(encoder);
		3428
		3429	/*
		3430	* There seems to be a race in PCH platform hw (at least on some
		3431	* outputs) where an enabled pipe still completes any pageflip right
		3432	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3433	* as the first vblank happend, everything works as expected. Hence just
		3434	* wait for one vblank before returning to avoid strange things
		3435	* happening.
		3436	*/
		3437	intel_wait_for_vblank(dev, intel_crtc->pipe);
		3438	}
		3439
2327	Serge	3440	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		3441	{
		3442	struct drm_device *dev = crtc->dev;
		3443	struct drm_i915_private *dev_priv = dev->dev_private;
		3444	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3445	struct intel_encoder *encoder;
2327	Serge	3446	int pipe = intel_crtc->pipe;
		3447	int plane = intel_crtc->plane;
		3448	u32 reg, temp;
		3449
3031	serge	3450
2327	Serge	3451	if (!intel_crtc->active)
		3452	return;
		3453
3031	serge	3454	for_each_encoder_on_crtc(dev, crtc, encoder)
		3455	encoder->disable(encoder);
2336	Serge	3456
3031	serge	3457	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3458	// drm_vblank_off(dev, pipe);
		3459	// intel_crtc_update_cursor(crtc, false);
		3460
		3461	intel_disable_plane(dev_priv, plane, pipe);
		3462
		3463	if (dev_priv->cfb_plane == plane)
		3464	intel_disable_fbc(dev);
		3465
		3466	intel_disable_pipe(dev_priv, pipe);
		3467
		3468	/* Disable PF */
		3469	I915_WRITE(PF_CTL(pipe), 0);
		3470	I915_WRITE(PF_WIN_SZ(pipe), 0);
		3471
3031	serge	3472	for_each_encoder_on_crtc(dev, crtc, encoder)
		3473	if (encoder->post_disable)
		3474	encoder->post_disable(encoder);
		3475
2327	Serge	3476	ironlake_fdi_disable(crtc);
		3477
3243	Serge	3478	ironlake_disable_pch_transcoder(dev_priv, pipe);
2327	Serge	3479
		3480	if (HAS_PCH_CPT(dev)) {
		3481	/* disable TRANS_DP_CTL */
		3482	reg = TRANS_DP_CTL(pipe);
		3483	temp = I915_READ(reg);
		3484	temp &= ~(TRANS_DP_OUTPUT_ENABLE \| TRANS_DP_PORT_SEL_MASK);
		3485	temp \|= TRANS_DP_PORT_SEL_NONE;
		3486	I915_WRITE(reg, temp);
		3487
		3488	/* disable DPLL_SEL */
		3489	temp = I915_READ(PCH_DPLL_SEL);
		3490	switch (pipe) {
		3491	case 0:
2342	Serge	3492	temp &= ~(TRANSA_DPLL_ENABLE \| TRANSA_DPLLB_SEL);
2327	Serge	3493	break;
		3494	case 1:
		3495	temp &= ~(TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
		3496	break;
		3497	case 2:
2342	Serge	3498	/* C shares PLL A or B */
2327	Serge	3499	temp &= ~(TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL);
		3500	break;
		3501	default:
		3502	BUG(); /* wtf */
		3503	}
		3504	I915_WRITE(PCH_DPLL_SEL, temp);
		3505	}
		3506
		3507	/* disable PCH DPLL */
3031	serge	3508	intel_disable_pch_pll(intel_crtc);
2327	Serge	3509
3031	serge	3510	ironlake_fdi_pll_disable(intel_crtc);
2327	Serge	3511
		3512	intel_crtc->active = false;
		3513	intel_update_watermarks(dev);
		3514
		3515	mutex_lock(&dev->struct_mutex);
		3516	intel_update_fbc(dev);
		3517	mutex_unlock(&dev->struct_mutex);
		3518	}
		3519
3243	Serge	3520	static void haswell_crtc_disable(struct drm_crtc *crtc)
		3521	{
		3522	struct drm_device *dev = crtc->dev;
		3523	struct drm_i915_private *dev_priv = dev->dev_private;
		3524	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3525	struct intel_encoder *encoder;
		3526	int pipe = intel_crtc->pipe;
		3527	int plane = intel_crtc->plane;
3746	Serge	3528	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3529
		3530	if (!intel_crtc->active)
		3531	return;
		3532
		3533	for_each_encoder_on_crtc(dev, crtc, encoder)
		3534	encoder->disable(encoder);
		3535
		3536
		3537	intel_disable_plane(dev_priv, plane, pipe);
		3538
		3539	if (dev_priv->cfb_plane == plane)
		3540	intel_disable_fbc(dev);
		3541
		3542	intel_disable_pipe(dev_priv, pipe);
		3543
		3544	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
		3545
3746	Serge	3546	/* XXX: Once we have proper panel fitter state tracking implemented with
		3547	* hardware state read/check support we should switch to only disable
		3548	* the panel fitter when we know it's used. */
		3549	if (intel_using_power_well(dev)) {
3243	Serge	3550	I915_WRITE(PF_CTL(pipe), 0);
		3551	I915_WRITE(PF_WIN_SZ(pipe), 0);
3746	Serge	3552	}
3243	Serge	3553
		3554	intel_ddi_disable_pipe_clock(intel_crtc);
		3555
		3556	for_each_encoder_on_crtc(dev, crtc, encoder)
		3557	if (encoder->post_disable)
		3558	encoder->post_disable(encoder);
		3559
3746	Serge	3560	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3561	lpt_disable_pch_transcoder(dev_priv);
		3562	intel_ddi_fdi_disable(crtc);
		3563	}
		3564
		3565	intel_crtc->active = false;
		3566	intel_update_watermarks(dev);
		3567
		3568	mutex_lock(&dev->struct_mutex);
		3569	intel_update_fbc(dev);
		3570	mutex_unlock(&dev->struct_mutex);
		3571	}
		3572
3031	serge	3573	static void ironlake_crtc_off(struct drm_crtc *crtc)
2327	Serge	3574	{
		3575	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3576	intel_put_pch_pll(intel_crtc);
2327	Serge	3577	}
		3578
3243	Serge	3579	static void haswell_crtc_off(struct drm_crtc *crtc)
		3580	{
		3581	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3582
		3583	/* Stop saying we're using TRANSCODER_EDP because some other CRTC might
		3584	* start using it. */
3746	Serge	3585	intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3243	Serge	3586
		3587	intel_ddi_put_crtc_pll(crtc);
		3588	}
		3589
2327	Serge	3590	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3591	{
		3592	if (!enable && intel_crtc->overlay) {
		3593	struct drm_device *dev = intel_crtc->base.dev;
		3594	struct drm_i915_private *dev_priv = dev->dev_private;
		3595
		3596	mutex_lock(&dev->struct_mutex);
		3597	dev_priv->mm.interruptible = false;
		3598	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3599	dev_priv->mm.interruptible = true;
		3600	mutex_unlock(&dev->struct_mutex);
		3601	}
		3602
		3603	/* Let userspace switch the overlay on again. In most cases userspace
		3604	* has to recompute where to put it anyway.
		3605	*/
		3606	}
		3607
3480	Serge	3608	/**
		3609	* i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
		3610	* cursor plane briefly if not already running after enabling the display
		3611	* plane.
		3612	* This workaround avoids occasional blank screens when self refresh is
		3613	* enabled.
		3614	*/
		3615	static void
		3616	g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
		3617	{
		3618	u32 cntl = I915_READ(CURCNTR(pipe));
		3619
		3620	if ((cntl & CURSOR_MODE) == 0) {
		3621	u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
		3622
		3623	I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
		3624	I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
		3625	intel_wait_for_vblank(dev_priv->dev, pipe);
		3626	I915_WRITE(CURCNTR(pipe), cntl);
		3627	I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
		3628	I915_WRITE(FW_BLC_SELF, fw_bcl_self);
		3629	}
		3630	}
		3631
2327	Serge	3632	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3633	{
		3634	struct drm_device *dev = crtc->dev;
		3635	struct drm_i915_private *dev_priv = dev->dev_private;
		3636	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3637	struct intel_encoder *encoder;
2327	Serge	3638	int pipe = intel_crtc->pipe;
		3639	int plane = intel_crtc->plane;
		3640
3031	serge	3641	WARN_ON(!crtc->enabled);
		3642
2327	Serge	3643	if (intel_crtc->active)
		3644	return;
		3645
		3646	intel_crtc->active = true;
		3647	intel_update_watermarks(dev);
		3648
		3649	intel_enable_pll(dev_priv, pipe);
3480	Serge	3650
		3651	for_each_encoder_on_crtc(dev, crtc, encoder)
		3652	if (encoder->pre_enable)
		3653	encoder->pre_enable(encoder);
		3654
2327	Serge	3655	intel_enable_pipe(dev_priv, pipe, false);
		3656	intel_enable_plane(dev_priv, plane, pipe);
3480	Serge	3657	if (IS_G4X(dev))
		3658	g4x_fixup_plane(dev_priv, pipe);
2327	Serge	3659
		3660	intel_crtc_load_lut(crtc);
		3661	intel_update_fbc(dev);
		3662
		3663	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3664	intel_crtc_dpms_overlay(intel_crtc, true);
		3665	// intel_crtc_update_cursor(crtc, true);
3031	serge	3666
		3667	for_each_encoder_on_crtc(dev, crtc, encoder)
		3668	encoder->enable(encoder);
2327	Serge	3669	}
		3670
3746	Serge	3671	static void i9xx_pfit_disable(struct intel_crtc *crtc)
		3672	{
		3673	struct drm_device *dev = crtc->base.dev;
		3674	struct drm_i915_private *dev_priv = dev->dev_private;
		3675	enum pipe pipe;
		3676	uint32_t pctl = I915_READ(PFIT_CONTROL);
		3677
		3678	assert_pipe_disabled(dev_priv, crtc->pipe);
		3679
		3680	if (INTEL_INFO(dev)->gen >= 4)
		3681	pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
		3682	else
		3683	pipe = PIPE_B;
		3684
		3685	if (pipe == crtc->pipe) {
		3686	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
		3687	I915_WRITE(PFIT_CONTROL, 0);
		3688	}
		3689	}
		3690
2327	Serge	3691	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3692	{
		3693	struct drm_device *dev = crtc->dev;
		3694	struct drm_i915_private *dev_priv = dev->dev_private;
		3695	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3696	struct intel_encoder *encoder;
2327	Serge	3697	int pipe = intel_crtc->pipe;
		3698	int plane = intel_crtc->plane;
		3699
		3700	if (!intel_crtc->active)
		3701	return;
		3702
3031	serge	3703	for_each_encoder_on_crtc(dev, crtc, encoder)
		3704	encoder->disable(encoder);
		3705
2327	Serge	3706	/* Give the overlay scaler a chance to disable if it's on this pipe */
3031	serge	3707	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3708	// drm_vblank_off(dev, pipe);
		3709	intel_crtc_dpms_overlay(intel_crtc, false);
		3710	// intel_crtc_update_cursor(crtc, false);
		3711
		3712	if (dev_priv->cfb_plane == plane)
		3713	intel_disable_fbc(dev);
		3714
		3715	intel_disable_plane(dev_priv, plane, pipe);
		3716	intel_disable_pipe(dev_priv, pipe);
3480	Serge	3717
3746	Serge	3718	i9xx_pfit_disable(intel_crtc);
3480	Serge	3719
2327	Serge	3720	intel_disable_pll(dev_priv, pipe);
		3721
		3722	intel_crtc->active = false;
		3723	intel_update_fbc(dev);
		3724	intel_update_watermarks(dev);
		3725	}
		3726
3031	serge	3727	static void i9xx_crtc_off(struct drm_crtc *crtc)
2327	Serge	3728	{
		3729	}
		3730
3031	serge	3731	static void intel_crtc_update_sarea(struct drm_crtc *crtc,
		3732	bool enabled)
2330	Serge	3733	{
		3734	struct drm_device *dev = crtc->dev;
		3735	struct drm_i915_master_private *master_priv;
		3736	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3737	int pipe = intel_crtc->pipe;
2327	Serge	3738
		3739
2340	Serge	3740	#if 0
2330	Serge	3741	if (!dev->primary->master)
		3742	return;
2327	Serge	3743
2330	Serge	3744	master_priv = dev->primary->master->driver_priv;
		3745	if (!master_priv->sarea_priv)
		3746	return;
2327	Serge	3747
2330	Serge	3748	switch (pipe) {
		3749	case 0:
		3750	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3751	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3752	break;
		3753	case 1:
		3754	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3755	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3756	break;
		3757	default:
		3758	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3759	break;
		3760	}
2340	Serge	3761	#endif
		3762
2330	Serge	3763	}
2327	Serge	3764
3031	serge	3765	/**
		3766	* Sets the power management mode of the pipe and plane.
		3767	*/
		3768	void intel_crtc_update_dpms(struct drm_crtc *crtc)
		3769	{
		3770	struct drm_device *dev = crtc->dev;
		3771	struct drm_i915_private *dev_priv = dev->dev_private;
		3772	struct intel_encoder *intel_encoder;
		3773	bool enable = false;
		3774
		3775	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		3776	enable \|= intel_encoder->connectors_active;
		3777
		3778	if (enable)
		3779	dev_priv->display.crtc_enable(crtc);
		3780	else
		3781	dev_priv->display.crtc_disable(crtc);
		3782
		3783	intel_crtc_update_sarea(crtc, enable);
		3784	}
		3785
2330	Serge	3786	static void intel_crtc_disable(struct drm_crtc *crtc)
		3787	{
		3788	struct drm_device *dev = crtc->dev;
3031	serge	3789	struct drm_connector *connector;
		3790	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	3791	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	3792
3031	serge	3793	/* crtc should still be enabled when we disable it. */
		3794	WARN_ON(!crtc->enabled);
2327	Serge	3795
3480	Serge	3796	intel_crtc->eld_vld = false;
3031	serge	3797	dev_priv->display.crtc_disable(crtc);
		3798	intel_crtc_update_sarea(crtc, false);
		3799	dev_priv->display.off(crtc);
		3800
		3801	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
		3802	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
		3803
		3804	// if (crtc->fb) {
		3805	// mutex_lock(&dev->struct_mutex);
		3806	// intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
		3807	// mutex_unlock(&dev->struct_mutex);
		3808	// crtc->fb = NULL;
		3809	// }
		3810
		3811	/* Update computed state. */
		3812	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		3813	if (!connector->encoder \|\| !connector->encoder->crtc)
		3814	continue;
		3815
		3816	if (connector->encoder->crtc != crtc)
		3817	continue;
		3818
		3819	connector->dpms = DRM_MODE_DPMS_OFF;
		3820	to_intel_encoder(connector->encoder)->connectors_active = false;
2330	Serge	3821	}
		3822	}
2327	Serge	3823
3031	serge	3824	void intel_modeset_disable(struct drm_device *dev)
2330	Serge	3825	{
3031	serge	3826	struct drm_crtc *crtc;
		3827
		3828	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		3829	if (crtc->enabled)
		3830	intel_crtc_disable(crtc);
		3831	}
2330	Serge	3832	}
2327	Serge	3833
3031	serge	3834	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3835	{
3031	serge	3836	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3837
		3838	drm_encoder_cleanup(encoder);
		3839	kfree(intel_encoder);
2330	Serge	3840	}
2327	Serge	3841
3031	serge	3842	/* Simple dpms helper for encodres with just one connector, no cloning and only
		3843	* one kind of off state. It clamps all !ON modes to fully OFF and changes the
		3844	* state of the entire output pipe. */
		3845	void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
2330	Serge	3846	{
3031	serge	3847	if (mode == DRM_MODE_DPMS_ON) {
		3848	encoder->connectors_active = true;
		3849
		3850	intel_crtc_update_dpms(encoder->base.crtc);
		3851	} else {
		3852	encoder->connectors_active = false;
		3853
		3854	intel_crtc_update_dpms(encoder->base.crtc);
		3855	}
2330	Serge	3856	}
2327	Serge	3857
3031	serge	3858	/* Cross check the actual hw state with our own modeset state tracking (and it's
		3859	* internal consistency). */
		3860	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	3861	{
3031	serge	3862	if (connector->get_hw_state(connector)) {
		3863	struct intel_encoder *encoder = connector->encoder;
		3864	struct drm_crtc *crtc;
		3865	bool encoder_enabled;
		3866	enum pipe pipe;
		3867
		3868	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		3869	connector->base.base.id,
		3870	drm_get_connector_name(&connector->base));
		3871
		3872	WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		3873	"wrong connector dpms state\n");
		3874	WARN(connector->base.encoder != &encoder->base,
		3875	"active connector not linked to encoder\n");
		3876	WARN(!encoder->connectors_active,
		3877	"encoder->connectors_active not set\n");
		3878
		3879	encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		3880	WARN(!encoder_enabled, "encoder not enabled\n");
		3881	if (WARN_ON(!encoder->base.crtc))
		3882	return;
		3883
		3884	crtc = encoder->base.crtc;
		3885
		3886	WARN(!crtc->enabled, "crtc not enabled\n");
		3887	WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		3888	WARN(pipe != to_intel_crtc(crtc)->pipe,
		3889	"encoder active on the wrong pipe\n");
		3890	}
2330	Serge	3891	}
2327	Serge	3892
3031	serge	3893	/* Even simpler default implementation, if there's really no special case to
		3894	* consider. */
		3895	void intel_connector_dpms(struct drm_connector *connector, int mode)
2330	Serge	3896	{
3031	serge	3897	struct intel_encoder *encoder = intel_attached_encoder(connector);
2342	Serge	3898
3031	serge	3899	/* All the simple cases only support two dpms states. */
		3900	if (mode != DRM_MODE_DPMS_ON)
		3901	mode = DRM_MODE_DPMS_OFF;
2342	Serge	3902
3031	serge	3903	if (mode == connector->dpms)
		3904	return;
		3905
		3906	connector->dpms = mode;
		3907
		3908	/* Only need to change hw state when actually enabled */
		3909	if (encoder->base.crtc)
		3910	intel_encoder_dpms(encoder, mode);
		3911	else
		3912	WARN_ON(encoder->connectors_active != false);
		3913
		3914	intel_modeset_check_state(connector->dev);
2330	Serge	3915	}
2327	Serge	3916
3031	serge	3917	/* Simple connector->get_hw_state implementation for encoders that support only
		3918	* one connector and no cloning and hence the encoder state determines the state
		3919	* of the connector. */
		3920	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	3921	{
3031	serge	3922	enum pipe pipe = 0;
		3923	struct intel_encoder *encoder = connector->encoder;
2330	Serge	3924
3031	serge	3925	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	3926	}
		3927
3746	Serge	3928	static bool intel_crtc_compute_config(struct drm_crtc *crtc,
		3929	struct intel_crtc_config *pipe_config)
2330	Serge	3930	{
		3931	struct drm_device *dev = crtc->dev;
3746	Serge	3932	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
2330	Serge	3933
		3934	if (HAS_PCH_SPLIT(dev)) {
		3935	/* FDI link clock is fixed at 2.7G */
3746	Serge	3936	if (pipe_config->requested_mode.clock * 3
		3937	> IRONLAKE_FDI_FREQ * 4)
2330	Serge	3938	return false;
		3939	}
		3940
3031	serge	3941	/* All interlaced capable intel hw wants timings in frames. Note though
		3942	* that intel_lvds_mode_fixup does some funny tricks with the crtc
		3943	* timings, so we need to be careful not to clobber these.*/
3746	Serge	3944	if (!pipe_config->timings_set)
2330	Serge	3945	drm_mode_set_crtcinfo(adjusted_mode, 0);
		3946
3031	serge	3947	/* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
		3948	* with a hsync front porch of 0.
		3949	*/
		3950	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
		3951	adjusted_mode->hsync_start == adjusted_mode->hdisplay)
		3952	return false;
		3953
3746	Serge	3954	if ((IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
		3955	pipe_config->pipe_bpp = 103; / 12bpc is gen5+ */
		3956	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
		3957	/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		3958	* for lvds. */
		3959	pipe_config->pipe_bpp = 8*3;
		3960	}
		3961
2330	Serge	3962	return true;
		3963	}
		3964
3031	serge	3965	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		3966	{
		3967	return 400000; /* FIXME */
		3968	}
		3969
2327	Serge	3970	static int i945_get_display_clock_speed(struct drm_device *dev)
		3971	{
		3972	return 400000;
		3973	}
		3974
		3975	static int i915_get_display_clock_speed(struct drm_device *dev)
		3976	{
		3977	return 333000;
		3978	}
		3979
		3980	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		3981	{
		3982	return 200000;
		3983	}
		3984
		3985	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		3986	{
		3987	u16 gcfgc = 0;
		3988
		3989	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		3990
		3991	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		3992	return 133000;
		3993	else {
		3994	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		3995	case GC_DISPLAY_CLOCK_333_MHZ:
		3996	return 333000;
		3997	default:
		3998	case GC_DISPLAY_CLOCK_190_200_MHZ:
		3999	return 190000;
		4000	}
		4001	}
		4002	}
		4003
		4004	static int i865_get_display_clock_speed(struct drm_device *dev)
		4005	{
		4006	return 266000;
		4007	}
		4008
		4009	static int i855_get_display_clock_speed(struct drm_device *dev)
		4010	{
		4011	u16 hpllcc = 0;
		4012	/* Assume that the hardware is in the high speed state. This
		4013	* should be the default.
		4014	*/
		4015	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		4016	case GC_CLOCK_133_200:
		4017	case GC_CLOCK_100_200:
		4018	return 200000;
		4019	case GC_CLOCK_166_250:
		4020	return 250000;
		4021	case GC_CLOCK_100_133:
		4022	return 133000;
		4023	}
		4024
		4025	/* Shouldn't happen */
		4026	return 0;
		4027	}
		4028
		4029	static int i830_get_display_clock_speed(struct drm_device *dev)
		4030	{
		4031	return 133000;
		4032	}
		4033
		4034	static void
3746	Serge	4035	intel_reduce_m_n_ratio(uint32_t num, uint32_t den)
2327	Serge	4036	{
3746	Serge	4037	while (*num > DATA_LINK_M_N_MASK \|\|
		4038	*den > DATA_LINK_M_N_MASK) {
2327	Serge	4039	*num >>= 1;
		4040	*den >>= 1;
		4041	}
		4042	}
		4043
3746	Serge	4044	static void compute_m_n(unsigned int m, unsigned int n,
		4045	uint32_t ret_m, uint32_t ret_n)
		4046	{
		4047	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
		4048	ret_m = div_u64((uint64_t) m *ret_n, n);
		4049	intel_reduce_m_n_ratio(ret_m, ret_n);
		4050	}
		4051
3480	Serge	4052	void
		4053	intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		4054	int pixel_clock, int link_clock,
		4055	struct intel_link_m_n *m_n)
2327	Serge	4056	{
3480	Serge	4057	m_n->tu = 64;
3746	Serge	4058
		4059	compute_m_n(bits_per_pixel * pixel_clock,
		4060	link_clock * nlanes * 8,
		4061	&m_n->gmch_m, &m_n->gmch_n);
		4062
		4063	compute_m_n(pixel_clock, link_clock,
		4064	&m_n->link_m, &m_n->link_n);
2327	Serge	4065	}
		4066
		4067	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		4068	{
2342	Serge	4069	if (i915_panel_use_ssc >= 0)
		4070	return i915_panel_use_ssc != 0;
		4071	return dev_priv->lvds_use_ssc
2327	Serge	4072	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		4073	}
		4074
3031	serge	4075	static int vlv_get_refclk(struct drm_crtc *crtc)
2327	Serge	4076	{
3031	serge	4077	struct drm_device *dev = crtc->dev;
		4078	struct drm_i915_private *dev_priv = dev->dev_private;
		4079	int refclk = 27000; /* for DP & HDMI */
2327	Serge	4080
3031	serge	4081	return 100000; /* only one validated so far */
2327	Serge	4082
3031	serge	4083	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		4084	refclk = 96000;
		4085	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		4086	if (intel_panel_use_ssc(dev_priv))
		4087	refclk = 100000;
		4088	else
		4089	refclk = 96000;
		4090	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		4091	refclk = 100000;
		4092	}
2327	Serge	4093
3031	serge	4094	return refclk;
		4095	}
2327	Serge	4096
3031	serge	4097	static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
		4098	{
		4099	struct drm_device *dev = crtc->dev;
		4100	struct drm_i915_private *dev_priv = dev->dev_private;
		4101	int refclk;
2327	Serge	4102
3031	serge	4103	if (IS_VALLEYVIEW(dev)) {
		4104	refclk = vlv_get_refclk(crtc);
		4105	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4106	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		4107	refclk = dev_priv->lvds_ssc_freq * 1000;
		4108	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4109	refclk / 1000);
		4110	} else if (!IS_GEN2(dev)) {
		4111	refclk = 96000;
		4112	} else {
		4113	refclk = 48000;
		4114	}
2327	Serge	4115
3031	serge	4116	return refclk;
		4117	}
2327	Serge	4118
3746	Serge	4119	static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
3031	serge	4120	{
3746	Serge	4121	unsigned dotclock = crtc->config.adjusted_mode.clock;
		4122	struct dpll *clock = &crtc->config.dpll;
		4123
3031	serge	4124	/* SDVO TV has fixed PLL values depend on its clock range,
		4125	this mirrors vbios setting. */
3746	Serge	4126	if (dotclock >= 100000 && dotclock < 140500) {
3031	serge	4127	clock->p1 = 2;
		4128	clock->p2 = 10;
		4129	clock->n = 3;
		4130	clock->m1 = 16;
		4131	clock->m2 = 8;
3746	Serge	4132	} else if (dotclock >= 140500 && dotclock <= 200000) {
3031	serge	4133	clock->p1 = 1;
		4134	clock->p2 = 10;
		4135	clock->n = 6;
		4136	clock->m1 = 12;
		4137	clock->m2 = 8;
		4138	}
3746	Serge	4139
		4140	crtc->config.clock_set = true;
3031	serge	4141	}
2327	Serge	4142
3746	Serge	4143	static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
3031	serge	4144	intel_clock_t *reduced_clock)
		4145	{
3746	Serge	4146	struct drm_device *dev = crtc->base.dev;
3031	serge	4147	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4148	int pipe = crtc->pipe;
3031	serge	4149	u32 fp, fp2 = 0;
3746	Serge	4150	struct dpll *clock = &crtc->config.dpll;
2327	Serge	4151
3031	serge	4152	if (IS_PINEVIEW(dev)) {
		4153	fp = (1 << clock->n) << 16 \| clock->m1 << 8 \| clock->m2;
		4154	if (reduced_clock)
		4155	fp2 = (1 << reduced_clock->n) << 16 \|
		4156	reduced_clock->m1 << 8 \| reduced_clock->m2;
		4157	} else {
		4158	fp = clock->n << 16 \| clock->m1 << 8 \| clock->m2;
		4159	if (reduced_clock)
		4160	fp2 = reduced_clock->n << 16 \| reduced_clock->m1 << 8 \|
		4161	reduced_clock->m2;
		4162	}
2327	Serge	4163
3031	serge	4164	I915_WRITE(FP0(pipe), fp);
2327	Serge	4165
3746	Serge	4166	crtc->lowfreq_avail = false;
		4167	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4168	reduced_clock && i915_powersave) {
		4169	I915_WRITE(FP1(pipe), fp2);
3746	Serge	4170	crtc->lowfreq_avail = true;
3031	serge	4171	} else {
		4172	I915_WRITE(FP1(pipe), fp);
		4173	}
		4174	}
2327	Serge	4175
3746	Serge	4176	static void intel_dp_set_m_n(struct intel_crtc *crtc)
3031	serge	4177	{
3746	Serge	4178	if (crtc->config.has_pch_encoder)
		4179	intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4180	else
		4181	intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4182	}
		4183
		4184	static void vlv_update_pll(struct intel_crtc *crtc)
		4185	{
		4186	struct drm_device *dev = crtc->base.dev;
3031	serge	4187	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4188	int pipe = crtc->pipe;
3031	serge	4189	u32 dpll, mdiv, pdiv;
		4190	u32 bestn, bestm1, bestm2, bestp1, bestp2;
3243	Serge	4191	bool is_sdvo;
		4192	u32 temp;
2327	Serge	4193
3480	Serge	4194	mutex_lock(&dev_priv->dpio_lock);
		4195
3746	Serge	4196	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) \|\|
		4197	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
2327	Serge	4198
3243	Serge	4199	dpll = DPLL_VGA_MODE_DIS;
		4200	dpll \|= DPLL_EXT_BUFFER_ENABLE_VLV;
		4201	dpll \|= DPLL_REFA_CLK_ENABLE_VLV;
		4202	dpll \|= DPLL_INTEGRATED_CLOCK_VLV;
		4203
		4204	I915_WRITE(DPLL(pipe), dpll);
		4205	POSTING_READ(DPLL(pipe));
		4206
3746	Serge	4207	bestn = crtc->config.dpll.n;
		4208	bestm1 = crtc->config.dpll.m1;
		4209	bestm2 = crtc->config.dpll.m2;
		4210	bestp1 = crtc->config.dpll.p1;
		4211	bestp2 = crtc->config.dpll.p2;
3031	serge	4212
3243	Serge	4213	/*
		4214	* In Valleyview PLL and program lane counter registers are exposed
		4215	* through DPIO interface
		4216	*/
3031	serge	4217	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		4218	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		4219	mdiv \|= ((bestn << DPIO_N_SHIFT));
		4220	mdiv \|= (1 << DPIO_POST_DIV_SHIFT);
		4221	mdiv \|= (1 << DPIO_K_SHIFT);
		4222	mdiv \|= DPIO_ENABLE_CALIBRATION;
		4223	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
		4224
		4225	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
		4226
3243	Serge	4227	pdiv = (1 << DPIO_REFSEL_OVERRIDE) \| (5 << DPIO_PLL_MODESEL_SHIFT) \|
3031	serge	4228	(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) \| (1<<20) \|
3243	Serge	4229	(7 << DPIO_PLL_REFCLK_SEL_SHIFT) \| (8 << DPIO_DRIVER_CTL_SHIFT) \|
		4230	(5 << DPIO_CLK_BIAS_CTL_SHIFT);
3031	serge	4231	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
		4232
3243	Serge	4233	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
3031	serge	4234
		4235	dpll \|= DPLL_VCO_ENABLE;
		4236	I915_WRITE(DPLL(pipe), dpll);
		4237	POSTING_READ(DPLL(pipe));
		4238	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		4239	DRM_ERROR("DPLL %d failed to lock\n", pipe);
		4240
3243	Serge	4241	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
3031	serge	4242
3746	Serge	4243	if (crtc->config.has_dp_encoder)
		4244	intel_dp_set_m_n(crtc);
3243	Serge	4245
		4246	I915_WRITE(DPLL(pipe), dpll);
		4247
		4248	/* Wait for the clocks to stabilize. */
		4249	POSTING_READ(DPLL(pipe));
		4250	udelay(150);
		4251
		4252	temp = 0;
		4253	if (is_sdvo) {
3031	serge	4254	temp = 0;
3746	Serge	4255	if (crtc->config.pixel_multiplier > 1) {
		4256	temp = (crtc->config.pixel_multiplier - 1)
		4257	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4258	}
3243	Serge	4259	}
3031	serge	4260	I915_WRITE(DPLL_MD(pipe), temp);
		4261	POSTING_READ(DPLL_MD(pipe));
3243	Serge	4262
		4263	/* Now program lane control registers */
3746	Serge	4264	if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
		4265	\|\| intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
3243	Serge	4266	temp = 0x1000C4;
		4267	if(pipe == 1)
		4268	temp \|= (1 << 21);
		4269	intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
3031	serge	4270	}
3746	Serge	4271
		4272	if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3243	Serge	4273	temp = 0x1000C4;
		4274	if(pipe == 1)
		4275	temp \|= (1 << 21);
		4276	intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
		4277	}
3480	Serge	4278
		4279	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	4280	}
		4281
3746	Serge	4282	static void i9xx_update_pll(struct intel_crtc *crtc,
		4283	intel_clock_t *reduced_clock,
3031	serge	4284	int num_connectors)
		4285	{
3746	Serge	4286	struct drm_device *dev = crtc->base.dev;
3031	serge	4287	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	4288	struct intel_encoder *encoder;
3746	Serge	4289	int pipe = crtc->pipe;
3031	serge	4290	u32 dpll;
		4291	bool is_sdvo;
3746	Serge	4292	struct dpll *clock = &crtc->config.dpll;
3031	serge	4293
3746	Serge	4294	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4295
3746	Serge	4296	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) \|\|
		4297	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
3031	serge	4298
		4299	dpll = DPLL_VGA_MODE_DIS;
		4300
3746	Serge	4301	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
3031	serge	4302	dpll \|= DPLLB_MODE_LVDS;
		4303	else
		4304	dpll \|= DPLLB_MODE_DAC_SERIAL;
3746	Serge	4305
3031	serge	4306	if (is_sdvo) {
3746	Serge	4307	if ((crtc->config.pixel_multiplier > 1) &&
		4308	(IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev))) {
		4309	dpll \|= (crtc->config.pixel_multiplier - 1)
		4310	<< SDVO_MULTIPLIER_SHIFT_HIRES;
2342	Serge	4311	}
3031	serge	4312	dpll \|= DPLL_DVO_HIGH_SPEED;
2342	Serge	4313	}
3746	Serge	4314	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
3031	serge	4315	dpll \|= DPLL_DVO_HIGH_SPEED;
2342	Serge	4316
3031	serge	4317	/* compute bitmask from p1 value */
		4318	if (IS_PINEVIEW(dev))
		4319	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4320	else {
		4321	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4322	if (IS_G4X(dev) && reduced_clock)
		4323	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4324	}
		4325	switch (clock->p2) {
		4326	case 5:
		4327	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4328	break;
		4329	case 7:
		4330	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4331	break;
		4332	case 10:
		4333	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4334	break;
		4335	case 14:
		4336	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4337	break;
		4338	}
		4339	if (INTEL_INFO(dev)->gen >= 4)
		4340	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	4341
3746	Serge	4342	if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
3031	serge	4343	dpll \|= PLL_REF_INPUT_TVCLKINBC;
3746	Serge	4344	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
3031	serge	4345	/* XXX: just matching BIOS for now */
		4346	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4347	dpll \|= 3;
3746	Serge	4348	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4349	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4350	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4351	else
		4352	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	4353
3031	serge	4354	dpll \|= DPLL_VCO_ENABLE;
		4355	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		4356	POSTING_READ(DPLL(pipe));
		4357	udelay(150);
2327	Serge	4358
3746	Serge	4359	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
3480	Serge	4360	if (encoder->pre_pll_enable)
		4361	encoder->pre_pll_enable(encoder);
2327	Serge	4362
3746	Serge	4363	if (crtc->config.has_dp_encoder)
		4364	intel_dp_set_m_n(crtc);
2327	Serge	4365
3031	serge	4366	I915_WRITE(DPLL(pipe), dpll);
2327	Serge	4367
3031	serge	4368	/* Wait for the clocks to stabilize. */
		4369	POSTING_READ(DPLL(pipe));
		4370	udelay(150);
2327	Serge	4371
3031	serge	4372	if (INTEL_INFO(dev)->gen >= 4) {
		4373	u32 temp = 0;
		4374	if (is_sdvo) {
		4375	temp = 0;
3746	Serge	4376	if (crtc->config.pixel_multiplier > 1) {
		4377	temp = (crtc->config.pixel_multiplier - 1)
		4378	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4379	}
3031	serge	4380	}
		4381	I915_WRITE(DPLL_MD(pipe), temp);
		4382	} else {
		4383	/* The pixel multiplier can only be updated once the
		4384	* DPLL is enabled and the clocks are stable.
		4385	*
		4386	* So write it again.
		4387	*/
		4388	I915_WRITE(DPLL(pipe), dpll);
		4389	}
		4390	}
2327	Serge	4391
3746	Serge	4392	static void i8xx_update_pll(struct intel_crtc *crtc,
3031	serge	4393	struct drm_display_mode *adjusted_mode,
3746	Serge	4394	intel_clock_t *reduced_clock,
3031	serge	4395	int num_connectors)
		4396	{
3746	Serge	4397	struct drm_device *dev = crtc->base.dev;
3031	serge	4398	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	4399	struct intel_encoder *encoder;
3746	Serge	4400	int pipe = crtc->pipe;
3031	serge	4401	u32 dpll;
3746	Serge	4402	struct dpll *clock = &crtc->config.dpll;
2327	Serge	4403
3746	Serge	4404	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4405
3031	serge	4406	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	4407
3746	Serge	4408	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
3031	serge	4409	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4410	} else {
		4411	if (clock->p1 == 2)
		4412	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4413	else
		4414	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4415	if (clock->p2 == 4)
		4416	dpll \|= PLL_P2_DIVIDE_BY_4;
		4417	}
2327	Serge	4418
3746	Serge	4419	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4420	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4421	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4422	else
		4423	dpll \|= PLL_REF_INPUT_DREFCLK;
		4424
		4425	dpll \|= DPLL_VCO_ENABLE;
		4426	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		4427	POSTING_READ(DPLL(pipe));
		4428	udelay(150);
		4429
3746	Serge	4430	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
3480	Serge	4431	if (encoder->pre_pll_enable)
		4432	encoder->pre_pll_enable(encoder);
3031	serge	4433
		4434	I915_WRITE(DPLL(pipe), dpll);
		4435
		4436	/* Wait for the clocks to stabilize. */
		4437	POSTING_READ(DPLL(pipe));
		4438	udelay(150);
		4439
		4440	/* The pixel multiplier can only be updated once the
		4441	* DPLL is enabled and the clocks are stable.
		4442	*
		4443	* So write it again.
		4444	*/
		4445	I915_WRITE(DPLL(pipe), dpll);
		4446	}
		4447
3243	Serge	4448	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
		4449	struct drm_display_mode *mode,
		4450	struct drm_display_mode *adjusted_mode)
		4451	{
		4452	struct drm_device *dev = intel_crtc->base.dev;
		4453	struct drm_i915_private *dev_priv = dev->dev_private;
		4454	enum pipe pipe = intel_crtc->pipe;
3746	Serge	4455	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	4456	uint32_t vsyncshift;
		4457
		4458	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		4459	/* the chip adds 2 halflines automatically */
		4460	adjusted_mode->crtc_vtotal -= 1;
		4461	adjusted_mode->crtc_vblank_end -= 1;
		4462	vsyncshift = adjusted_mode->crtc_hsync_start
		4463	- adjusted_mode->crtc_htotal / 2;
		4464	} else {
		4465	vsyncshift = 0;
		4466	}
		4467
		4468	if (INTEL_INFO(dev)->gen > 3)
		4469	I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
		4470
		4471	I915_WRITE(HTOTAL(cpu_transcoder),
		4472	(adjusted_mode->crtc_hdisplay - 1) \|
		4473	((adjusted_mode->crtc_htotal - 1) << 16));
		4474	I915_WRITE(HBLANK(cpu_transcoder),
		4475	(adjusted_mode->crtc_hblank_start - 1) \|
		4476	((adjusted_mode->crtc_hblank_end - 1) << 16));
		4477	I915_WRITE(HSYNC(cpu_transcoder),
		4478	(adjusted_mode->crtc_hsync_start - 1) \|
		4479	((adjusted_mode->crtc_hsync_end - 1) << 16));
		4480
		4481	I915_WRITE(VTOTAL(cpu_transcoder),
		4482	(adjusted_mode->crtc_vdisplay - 1) \|
		4483	((adjusted_mode->crtc_vtotal - 1) << 16));
		4484	I915_WRITE(VBLANK(cpu_transcoder),
		4485	(adjusted_mode->crtc_vblank_start - 1) \|
		4486	((adjusted_mode->crtc_vblank_end - 1) << 16));
		4487	I915_WRITE(VSYNC(cpu_transcoder),
		4488	(adjusted_mode->crtc_vsync_start - 1) \|
		4489	((adjusted_mode->crtc_vsync_end - 1) << 16));
		4490
		4491	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
		4492	* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
		4493	* documented on the DDI_FUNC_CTL register description, EDP Input Select
		4494	* bits. */
		4495	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
		4496	(pipe == PIPE_B \|\| pipe == PIPE_C))
		4497	I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
		4498
		4499	/* pipesrc controls the size that is scaled from, which should
		4500	* always be the user's requested size.
		4501	*/
		4502	I915_WRITE(PIPESRC(pipe),
		4503	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		4504	}
		4505
3746	Serge	4506	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
		4507	{
		4508	struct drm_device *dev = intel_crtc->base.dev;
		4509	struct drm_i915_private *dev_priv = dev->dev_private;
		4510	uint32_t pipeconf;
		4511
		4512	pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
		4513
		4514	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4515	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4516	* core speed.
		4517	*
		4518	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4519	* pipe == 0 check?
		4520	*/
		4521	if (intel_crtc->config.requested_mode.clock >
		4522	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4523	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4524	else
		4525	pipeconf &= ~PIPECONF_DOUBLE_WIDE;
		4526	}
		4527
		4528	/* default to 8bpc */
		4529	pipeconf &= ~(PIPECONF_BPC_MASK \| PIPECONF_DITHER_EN);
		4530	if (intel_crtc->config.has_dp_encoder) {
		4531	if (intel_crtc->config.dither) {
		4532	pipeconf \|= PIPECONF_6BPC \|
		4533	PIPECONF_DITHER_EN \|
		4534	PIPECONF_DITHER_TYPE_SP;
		4535	}
		4536	}
		4537
		4538	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
		4539	INTEL_OUTPUT_EDP)) {
		4540	if (intel_crtc->config.dither) {
		4541	pipeconf \|= PIPECONF_6BPC \|
		4542	PIPECONF_ENABLE \|
		4543	I965_PIPECONF_ACTIVE;
		4544	}
		4545	}
		4546
		4547	if (HAS_PIPE_CXSR(dev)) {
		4548	if (intel_crtc->lowfreq_avail) {
		4549	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		4550	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		4551	} else {
		4552	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		4553	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		4554	}
		4555	}
		4556
		4557	pipeconf &= ~PIPECONF_INTERLACE_MASK;
		4558	if (!IS_GEN2(dev) &&
		4559	intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
		4560	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		4561	else
		4562	pipeconf \|= PIPECONF_PROGRESSIVE;
		4563
		4564	if (IS_VALLEYVIEW(dev)) {
		4565	if (intel_crtc->config.limited_color_range)
		4566	pipeconf \|= PIPECONF_COLOR_RANGE_SELECT;
		4567	else
		4568	pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
		4569	}
		4570
		4571	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
		4572	POSTING_READ(PIPECONF(intel_crtc->pipe));
		4573	}
		4574
3031	serge	4575	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4576	int x, int y,
		4577	struct drm_framebuffer *fb)
		4578	{
		4579	struct drm_device *dev = crtc->dev;
		4580	struct drm_i915_private *dev_priv = dev->dev_private;
		4581	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	4582	struct drm_display_mode *adjusted_mode =
		4583	&intel_crtc->config.adjusted_mode;
		4584	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
3031	serge	4585	int pipe = intel_crtc->pipe;
		4586	int plane = intel_crtc->plane;
		4587	int refclk, num_connectors = 0;
		4588	intel_clock_t clock, reduced_clock;
3746	Serge	4589	u32 dspcntr;
3031	serge	4590	bool ok, has_reduced_clock = false, is_sdvo = false;
3746	Serge	4591	bool is_lvds = false, is_tv = false;
3031	serge	4592	struct intel_encoder *encoder;
		4593	const intel_limit_t *limit;
		4594	int ret;
		4595
		4596	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4597	switch (encoder->type) {
		4598	case INTEL_OUTPUT_LVDS:
		4599	is_lvds = true;
		4600	break;
		4601	case INTEL_OUTPUT_SDVO:
		4602	case INTEL_OUTPUT_HDMI:
		4603	is_sdvo = true;
		4604	if (encoder->needs_tv_clock)
		4605	is_tv = true;
		4606	break;
		4607	case INTEL_OUTPUT_TVOUT:
		4608	is_tv = true;
		4609	break;
		4610	}
		4611
		4612	num_connectors++;
		4613	}
		4614
		4615	refclk = i9xx_get_refclk(crtc, num_connectors);
		4616
		4617	/*
		4618	* Returns a set of divisors for the desired target clock with the given
		4619	* refclk, or FALSE. The returned values represent the clock equation:
		4620	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4621	*/
		4622	limit = intel_limit(crtc, refclk);
		4623	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
		4624	&clock);
		4625	if (!ok) {
		4626	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4627	return -EINVAL;
		4628	}
		4629
		4630	/* Ensure that the cursor is valid for the new mode before changing... */
		4631	// intel_crtc_update_cursor(crtc, true);
		4632
		4633	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4634	/*
		4635	* Ensure we match the reduced clock's P to the target clock.
		4636	* If the clocks don't match, we can't switch the display clock
		4637	* by using the FP0/FP1. In such case we will disable the LVDS
		4638	* downclock feature.
		4639	*/
		4640	has_reduced_clock = limit->find_pll(limit, crtc,
		4641	dev_priv->lvds_downclock,
		4642	refclk,
		4643	&clock,
		4644	&reduced_clock);
		4645	}
3746	Serge	4646	/* Compat-code for transition, will disappear. */
		4647	if (!intel_crtc->config.clock_set) {
		4648	intel_crtc->config.dpll.n = clock.n;
		4649	intel_crtc->config.dpll.m1 = clock.m1;
		4650	intel_crtc->config.dpll.m2 = clock.m2;
		4651	intel_crtc->config.dpll.p1 = clock.p1;
		4652	intel_crtc->config.dpll.p2 = clock.p2;
		4653	}
3031	serge	4654
		4655	if (is_sdvo && is_tv)
3746	Serge	4656	i9xx_adjust_sdvo_tv_clock(intel_crtc);
3031	serge	4657
		4658	if (IS_GEN2(dev))
3746	Serge	4659	i8xx_update_pll(intel_crtc, adjusted_mode,
3243	Serge	4660	has_reduced_clock ? &reduced_clock : NULL,
		4661	num_connectors);
3031	serge	4662	else if (IS_VALLEYVIEW(dev))
3746	Serge	4663	vlv_update_pll(intel_crtc);
3031	serge	4664	else
3746	Serge	4665	i9xx_update_pll(intel_crtc,
3031	serge	4666	has_reduced_clock ? &reduced_clock : NULL,
		4667	num_connectors);
		4668
		4669	/* Set up the display plane register */
		4670	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4671
3746	Serge	4672	if (!IS_VALLEYVIEW(dev)) {
3031	serge	4673	if (pipe == 0)
		4674	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4675	else
		4676	dspcntr \|= DISPPLANE_SEL_PIPE_B;
3243	Serge	4677	}
		4678
3031	serge	4679	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
		4680	drm_mode_debug_printmodeline(mode);
		4681
3243	Serge	4682	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2327	Serge	4683
3031	serge	4684	/* pipesrc and dspsize control the size that is scaled from,
		4685	* which should always be the user's requested size.
		4686	*/
		4687	I915_WRITE(DSPSIZE(plane),
		4688	((mode->vdisplay - 1) << 16) \|
		4689	(mode->hdisplay - 1));
		4690	I915_WRITE(DSPPOS(plane), 0);
2327	Serge	4691
3746	Serge	4692	i9xx_set_pipeconf(intel_crtc);
		4693
3031	serge	4694	intel_enable_pipe(dev_priv, pipe, false);
2327	Serge	4695
3031	serge	4696	intel_wait_for_vblank(dev, pipe);
2327	Serge	4697
3031	serge	4698	I915_WRITE(DSPCNTR(plane), dspcntr);
		4699	POSTING_READ(DSPCNTR(plane));
2327	Serge	4700
3031	serge	4701	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	4702
3031	serge	4703	intel_update_watermarks(dev);
		4704
2327	Serge	4705	return ret;
		4706	}
		4707
3746	Serge	4708	static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
		4709	struct intel_crtc_config *pipe_config)
		4710	{
		4711	struct drm_device *dev = crtc->base.dev;
		4712	struct drm_i915_private *dev_priv = dev->dev_private;
		4713	uint32_t tmp;
		4714
		4715	tmp = I915_READ(PIPECONF(crtc->pipe));
		4716	if (!(tmp & PIPECONF_ENABLE))
		4717	return false;
		4718
		4719	return true;
		4720	}
		4721
3243	Serge	4722	static void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	4723	{
		4724	struct drm_i915_private *dev_priv = dev->dev_private;
		4725	struct drm_mode_config *mode_config = &dev->mode_config;
		4726	struct intel_encoder *encoder;
3746	Serge	4727	u32 val, final;
2327	Serge	4728	bool has_lvds = false;
2342	Serge	4729	bool has_cpu_edp = false;
		4730	bool has_pch_edp = false;
		4731	bool has_panel = false;
		4732	bool has_ck505 = false;
		4733	bool can_ssc = false;
2327	Serge	4734
		4735	/* We need to take the global config into account */
		4736	list_for_each_entry(encoder, &mode_config->encoder_list,
		4737	base.head) {
		4738	switch (encoder->type) {
		4739	case INTEL_OUTPUT_LVDS:
2342	Serge	4740	has_panel = true;
2327	Serge	4741	has_lvds = true;
2342	Serge	4742	break;
2327	Serge	4743	case INTEL_OUTPUT_EDP:
2342	Serge	4744	has_panel = true;
		4745	if (intel_encoder_is_pch_edp(&encoder->base))
		4746	has_pch_edp = true;
		4747	else
		4748	has_cpu_edp = true;
2327	Serge	4749	break;
		4750	}
		4751	}
2342	Serge	4752
		4753	if (HAS_PCH_IBX(dev)) {
		4754	has_ck505 = dev_priv->display_clock_mode;
		4755	can_ssc = has_ck505;
		4756	} else {
		4757	has_ck505 = false;
		4758	can_ssc = true;
2327	Serge	4759	}
		4760
2342	Serge	4761	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
		4762	has_panel, has_lvds, has_pch_edp, has_cpu_edp,
		4763	has_ck505);
		4764
2327	Serge	4765	/* Ironlake: try to setup display ref clock before DPLL
		4766	* enabling. This is only under driver's control after
		4767	* PCH B stepping, previous chipset stepping should be
		4768	* ignoring this setting.
		4769	*/
3746	Serge	4770	val = I915_READ(PCH_DREF_CONTROL);
		4771
		4772	/* As we must carefully and slowly disable/enable each source in turn,
		4773	* compute the final state we want first and check if we need to
		4774	* make any changes at all.
		4775	*/
		4776	final = val;
		4777	final &= ~DREF_NONSPREAD_SOURCE_MASK;
		4778	if (has_ck505)
		4779	final \|= DREF_NONSPREAD_CK505_ENABLE;
		4780	else
		4781	final \|= DREF_NONSPREAD_SOURCE_ENABLE;
		4782
		4783	final &= ~DREF_SSC_SOURCE_MASK;
		4784	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		4785	final &= ~DREF_SSC1_ENABLE;
		4786
		4787	if (has_panel) {
		4788	final \|= DREF_SSC_SOURCE_ENABLE;
		4789
		4790	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		4791	final \|= DREF_SSC1_ENABLE;
		4792
		4793	if (has_cpu_edp) {
		4794	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		4795	final \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		4796	else
		4797	final \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		4798	} else
		4799	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		4800	} else {
		4801	final \|= DREF_SSC_SOURCE_DISABLE;
		4802	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		4803	}
		4804
		4805	if (final == val)
		4806	return;
		4807
2327	Serge	4808	/* Always enable nonspread source */
3746	Serge	4809	val &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	4810
		4811	if (has_ck505)
3746	Serge	4812	val \|= DREF_NONSPREAD_CK505_ENABLE;
2342	Serge	4813	else
3746	Serge	4814	val \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	4815
		4816	if (has_panel) {
3746	Serge	4817	val &= ~DREF_SSC_SOURCE_MASK;
		4818	val \|= DREF_SSC_SOURCE_ENABLE;
2327	Serge	4819
2342	Serge	4820	/* SSC must be turned on before enabling the CPU output */
		4821	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		4822	DRM_DEBUG_KMS("Using SSC on panel\n");
3746	Serge	4823	val \|= DREF_SSC1_ENABLE;
3031	serge	4824	} else
3746	Serge	4825	val &= ~DREF_SSC1_ENABLE;
2327	Serge	4826
2342	Serge	4827	/* Get SSC going before enabling the outputs */
3746	Serge	4828	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	4829	POSTING_READ(PCH_DREF_CONTROL);
		4830	udelay(200);
2342	Serge	4831
3746	Serge	4832	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2327	Serge	4833
		4834	/* Enable CPU source on CPU attached eDP */
2342	Serge	4835	if (has_cpu_edp) {
		4836	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		4837	DRM_DEBUG_KMS("Using SSC on eDP\n");
3746	Serge	4838	val \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2342	Serge	4839	}
2327	Serge	4840	else
3746	Serge	4841	val \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	4842	} else
3746	Serge	4843	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	4844
3746	Serge	4845	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	4846	POSTING_READ(PCH_DREF_CONTROL);
		4847	udelay(200);
2327	Serge	4848	} else {
2342	Serge	4849	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		4850
3746	Serge	4851	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2342	Serge	4852
		4853	/* Turn off CPU output */
3746	Serge	4854	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	4855
3746	Serge	4856	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	4857	POSTING_READ(PCH_DREF_CONTROL);
		4858	udelay(200);
2342	Serge	4859
		4860	/* Turn off the SSC source */
3746	Serge	4861	val &= ~DREF_SSC_SOURCE_MASK;
		4862	val \|= DREF_SSC_SOURCE_DISABLE;
2342	Serge	4863
		4864	/* Turn off SSC1 */
3746	Serge	4865	val &= ~DREF_SSC1_ENABLE;
2342	Serge	4866
3746	Serge	4867	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	4868	POSTING_READ(PCH_DREF_CONTROL);
		4869	udelay(200);
2327	Serge	4870	}
3746	Serge	4871
		4872	BUG_ON(val != final);
2327	Serge	4873	}
		4874
3243	Serge	4875	/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
		4876	static void lpt_init_pch_refclk(struct drm_device *dev)
		4877	{
		4878	struct drm_i915_private *dev_priv = dev->dev_private;
		4879	struct drm_mode_config *mode_config = &dev->mode_config;
		4880	struct intel_encoder *encoder;
		4881	bool has_vga = false;
		4882	bool is_sdv = false;
		4883	u32 tmp;
		4884
		4885	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		4886	switch (encoder->type) {
		4887	case INTEL_OUTPUT_ANALOG:
		4888	has_vga = true;
		4889	break;
		4890	}
		4891	}
		4892
		4893	if (!has_vga)
		4894	return;
		4895
3480	Serge	4896	mutex_lock(&dev_priv->dpio_lock);
		4897
3243	Serge	4898	/* XXX: Rip out SDV support once Haswell ships for real. */
		4899	if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
		4900	is_sdv = true;
		4901
		4902	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		4903	tmp &= ~SBI_SSCCTL_DISABLE;
		4904	tmp \|= SBI_SSCCTL_PATHALT;
		4905	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		4906
		4907	udelay(24);
		4908
		4909	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		4910	tmp &= ~SBI_SSCCTL_PATHALT;
		4911	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		4912
		4913	if (!is_sdv) {
		4914	tmp = I915_READ(SOUTH_CHICKEN2);
		4915	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;
		4916	I915_WRITE(SOUTH_CHICKEN2, tmp);
		4917
		4918	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
		4919	FDI_MPHY_IOSFSB_RESET_STATUS, 100))
		4920	DRM_ERROR("FDI mPHY reset assert timeout\n");
		4921
		4922	tmp = I915_READ(SOUTH_CHICKEN2);
		4923	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		4924	I915_WRITE(SOUTH_CHICKEN2, tmp);
		4925
		4926	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
		4927	FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
		4928	100))
		4929	DRM_ERROR("FDI mPHY reset de-assert timeout\n");
		4930	}
		4931
		4932	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
		4933	tmp &= ~(0xFF << 24);
		4934	tmp \|= (0x12 << 24);
		4935	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
		4936
		4937	if (is_sdv) {
		4938	tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
		4939	tmp \|= 0x7FFF;
		4940	intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
		4941	}
		4942
		4943	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
		4944	tmp \|= (1 << 11);
		4945	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
		4946
		4947	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
		4948	tmp \|= (1 << 11);
		4949	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
		4950
		4951	if (is_sdv) {
		4952	tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
		4953	tmp \|= (0x3F << 24) \| (0xF << 20) \| (0xF << 16);
		4954	intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
		4955
		4956	tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
		4957	tmp \|= (0x3F << 24) \| (0xF << 20) \| (0xF << 16);
		4958	intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
		4959
		4960	tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
		4961	tmp \|= (0x3F << 8);
		4962	intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
		4963
		4964	tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
		4965	tmp \|= (0x3F << 8);
		4966	intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
		4967	}
		4968
		4969	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
		4970	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		4971	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
		4972
		4973	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
		4974	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		4975	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
		4976
		4977	if (!is_sdv) {
		4978	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		4979	tmp &= ~(7 << 13);
		4980	tmp \|= (5 << 13);
		4981	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
		4982
		4983	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		4984	tmp &= ~(7 << 13);
		4985	tmp \|= (5 << 13);
		4986	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
		4987	}
		4988
		4989	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
		4990	tmp &= ~0xFF;
		4991	tmp \|= 0x1C;
		4992	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
		4993
		4994	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
		4995	tmp &= ~0xFF;
		4996	tmp \|= 0x1C;
		4997	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
		4998
		4999	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
		5000	tmp &= ~(0xFF << 16);
		5001	tmp \|= (0x1C << 16);
		5002	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
		5003
		5004	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
		5005	tmp &= ~(0xFF << 16);
		5006	tmp \|= (0x1C << 16);
		5007	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
		5008
		5009	if (!is_sdv) {
		5010	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		5011	tmp \|= (1 << 27);
		5012	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
		5013
		5014	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		5015	tmp \|= (1 << 27);
		5016	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
		5017
		5018	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		5019	tmp &= ~(0xF << 28);
		5020	tmp \|= (4 << 28);
		5021	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
		5022
		5023	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		5024	tmp &= ~(0xF << 28);
		5025	tmp \|= (4 << 28);
		5026	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
		5027	}
		5028
		5029	/* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
		5030	tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
		5031	tmp \|= SBI_DBUFF0_ENABLE;
		5032	intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
3480	Serge	5033
		5034	mutex_unlock(&dev_priv->dpio_lock);
3243	Serge	5035	}
		5036
		5037	/*
		5038	* Initialize reference clocks when the driver loads
		5039	*/
		5040	void intel_init_pch_refclk(struct drm_device *dev)
		5041	{
		5042	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		5043	ironlake_init_pch_refclk(dev);
		5044	else if (HAS_PCH_LPT(dev))
		5045	lpt_init_pch_refclk(dev);
		5046	}
		5047
2342	Serge	5048	static int ironlake_get_refclk(struct drm_crtc *crtc)
		5049	{
		5050	struct drm_device *dev = crtc->dev;
		5051	struct drm_i915_private *dev_priv = dev->dev_private;
		5052	struct intel_encoder *encoder;
		5053	struct intel_encoder *edp_encoder = NULL;
		5054	int num_connectors = 0;
		5055	bool is_lvds = false;
		5056
3031	serge	5057	for_each_encoder_on_crtc(dev, crtc, encoder) {
2342	Serge	5058	switch (encoder->type) {
		5059	case INTEL_OUTPUT_LVDS:
		5060	is_lvds = true;
		5061	break;
		5062	case INTEL_OUTPUT_EDP:
		5063	edp_encoder = encoder;
		5064	break;
		5065	}
		5066	num_connectors++;
		5067	}
		5068
		5069	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		5070	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		5071	dev_priv->lvds_ssc_freq);
		5072	return dev_priv->lvds_ssc_freq * 1000;
		5073	}
		5074
		5075	return 120000;
		5076	}
		5077
3031	serge	5078	static void ironlake_set_pipeconf(struct drm_crtc *crtc,
		5079	struct drm_display_mode *adjusted_mode,
		5080	bool dither)
		5081	{
		5082	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5083	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5084	int pipe = intel_crtc->pipe;
		5085	uint32_t val;
		5086
		5087	val = I915_READ(PIPECONF(pipe));
		5088
3480	Serge	5089	val &= ~PIPECONF_BPC_MASK;
3746	Serge	5090	switch (intel_crtc->config.pipe_bpp) {
3031	serge	5091	case 18:
3480	Serge	5092	val \|= PIPECONF_6BPC;
3031	serge	5093	break;
		5094	case 24:
3480	Serge	5095	val \|= PIPECONF_8BPC;
3031	serge	5096	break;
		5097	case 30:
3480	Serge	5098	val \|= PIPECONF_10BPC;
3031	serge	5099	break;
		5100	case 36:
3480	Serge	5101	val \|= PIPECONF_12BPC;
3031	serge	5102	break;
		5103	default:
3243	Serge	5104	/* Case prevented by intel_choose_pipe_bpp_dither. */
		5105	BUG();
3031	serge	5106	}
		5107
		5108	val &= ~(PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_MASK);
		5109	if (dither)
		5110	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5111
		5112	val &= ~PIPECONF_INTERLACE_MASK;
		5113	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		5114	val \|= PIPECONF_INTERLACED_ILK;
		5115	else
		5116	val \|= PIPECONF_PROGRESSIVE;
		5117
3746	Serge	5118	if (intel_crtc->config.limited_color_range)
3480	Serge	5119	val \|= PIPECONF_COLOR_RANGE_SELECT;
		5120	else
		5121	val &= ~PIPECONF_COLOR_RANGE_SELECT;
		5122
3031	serge	5123	I915_WRITE(PIPECONF(pipe), val);
		5124	POSTING_READ(PIPECONF(pipe));
		5125	}
		5126
3480	Serge	5127	/*
		5128	* Set up the pipe CSC unit.
		5129	*
		5130	* Currently only full range RGB to limited range RGB conversion
		5131	* is supported, but eventually this should handle various
		5132	* RGB<->YCbCr scenarios as well.
		5133	*/
3746	Serge	5134	static void intel_set_pipe_csc(struct drm_crtc *crtc)
3480	Serge	5135	{
		5136	struct drm_device *dev = crtc->dev;
		5137	struct drm_i915_private *dev_priv = dev->dev_private;
		5138	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5139	int pipe = intel_crtc->pipe;
		5140	uint16_t coeff = 0x7800; /* 1.0 */
		5141
		5142	/*
		5143	* TODO: Check what kind of values actually come out of the pipe
		5144	* with these coeff/postoff values and adjust to get the best
		5145	* accuracy. Perhaps we even need to take the bpc value into
		5146	* consideration.
		5147	*/
		5148
3746	Serge	5149	if (intel_crtc->config.limited_color_range)
3480	Serge	5150	coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
		5151
		5152	/*
		5153	* GY/GU and RY/RU should be the other way around according
		5154	* to BSpec, but reality doesn't agree. Just set them up in
		5155	* a way that results in the correct picture.
		5156	*/
		5157	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
		5158	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
		5159
		5160	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
		5161	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
		5162
		5163	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
		5164	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
		5165
		5166	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
		5167	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
		5168	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
		5169
		5170	if (INTEL_INFO(dev)->gen > 6) {
		5171	uint16_t postoff = 0;
		5172
3746	Serge	5173	if (intel_crtc->config.limited_color_range)
3480	Serge	5174	postoff = (16 * (1 << 13) / 255) & 0x1fff;
		5175
		5176	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		5177	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		5178	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
		5179
		5180	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
		5181	} else {
		5182	uint32_t mode = CSC_MODE_YUV_TO_RGB;
		5183
3746	Serge	5184	if (intel_crtc->config.limited_color_range)
3480	Serge	5185	mode \|= CSC_BLACK_SCREEN_OFFSET;
		5186
		5187	I915_WRITE(PIPE_CSC_MODE(pipe), mode);
		5188	}
		5189	}
		5190
3243	Serge	5191	static void haswell_set_pipeconf(struct drm_crtc *crtc,
		5192	struct drm_display_mode *adjusted_mode,
		5193	bool dither)
		5194	{
		5195	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5196	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5197	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	5198	uint32_t val;
		5199
		5200	val = I915_READ(PIPECONF(cpu_transcoder));
		5201
		5202	val &= ~(PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_MASK);
		5203	if (dither)
		5204	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5205
		5206	val &= ~PIPECONF_INTERLACE_MASK_HSW;
		5207	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		5208	val \|= PIPECONF_INTERLACED_ILK;
		5209	else
		5210	val \|= PIPECONF_PROGRESSIVE;
		5211
		5212	I915_WRITE(PIPECONF(cpu_transcoder), val);
		5213	POSTING_READ(PIPECONF(cpu_transcoder));
		5214	}
		5215
3031	serge	5216	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
		5217	struct drm_display_mode *adjusted_mode,
		5218	intel_clock_t *clock,
		5219	bool *has_reduced_clock,
		5220	intel_clock_t *reduced_clock)
		5221	{
		5222	struct drm_device *dev = crtc->dev;
		5223	struct drm_i915_private *dev_priv = dev->dev_private;
		5224	struct intel_encoder *intel_encoder;
		5225	int refclk;
		5226	const intel_limit_t *limit;
		5227	bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
		5228
		5229	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5230	switch (intel_encoder->type) {
		5231	case INTEL_OUTPUT_LVDS:
		5232	is_lvds = true;
		5233	break;
		5234	case INTEL_OUTPUT_SDVO:
		5235	case INTEL_OUTPUT_HDMI:
		5236	is_sdvo = true;
		5237	if (intel_encoder->needs_tv_clock)
		5238	is_tv = true;
		5239	break;
		5240	case INTEL_OUTPUT_TVOUT:
		5241	is_tv = true;
		5242	break;
		5243	}
		5244	}
		5245
		5246	refclk = ironlake_get_refclk(crtc);
		5247
		5248	/*
		5249	* Returns a set of divisors for the desired target clock with the given
		5250	* refclk, or FALSE. The returned values represent the clock equation:
		5251	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		5252	*/
		5253	limit = intel_limit(crtc, refclk);
		5254	ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
		5255	clock);
		5256	if (!ret)
		5257	return false;
		5258
		5259	if (is_lvds && dev_priv->lvds_downclock_avail) {
		5260	/*
		5261	* Ensure we match the reduced clock's P to the target clock.
		5262	* If the clocks don't match, we can't switch the display clock
		5263	* by using the FP0/FP1. In such case we will disable the LVDS
		5264	* downclock feature.
		5265	*/
		5266	*has_reduced_clock = limit->find_pll(limit, crtc,
		5267	dev_priv->lvds_downclock,
		5268	refclk,
		5269	clock,
		5270	reduced_clock);
		5271	}
		5272
		5273	if (is_sdvo && is_tv)
3746	Serge	5274	i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
3031	serge	5275
		5276	return true;
		5277	}
		5278
3243	Serge	5279	static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
		5280	{
		5281	struct drm_i915_private *dev_priv = dev->dev_private;
		5282	uint32_t temp;
		5283
		5284	temp = I915_READ(SOUTH_CHICKEN1);
		5285	if (temp & FDI_BC_BIFURCATION_SELECT)
		5286	return;
		5287
		5288	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		5289	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		5290
		5291	temp \|= FDI_BC_BIFURCATION_SELECT;
		5292	DRM_DEBUG_KMS("enabling fdi C rx\n");
		5293	I915_WRITE(SOUTH_CHICKEN1, temp);
		5294	POSTING_READ(SOUTH_CHICKEN1);
		5295	}
		5296
		5297	static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
		5298	{
		5299	struct drm_device *dev = intel_crtc->base.dev;
		5300	struct drm_i915_private *dev_priv = dev->dev_private;
		5301	struct intel_crtc *pipe_B_crtc =
		5302	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		5303
		5304	DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
		5305	intel_crtc->pipe, intel_crtc->fdi_lanes);
		5306	if (intel_crtc->fdi_lanes > 4) {
		5307	DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
		5308	intel_crtc->pipe, intel_crtc->fdi_lanes);
		5309	/* Clamp lanes to avoid programming the hw with bogus values. */
		5310	intel_crtc->fdi_lanes = 4;
		5311
		5312	return false;
		5313	}
		5314
3746	Serge	5315	if (INTEL_INFO(dev)->num_pipes == 2)
3243	Serge	5316	return true;
		5317
		5318	switch (intel_crtc->pipe) {
		5319	case PIPE_A:
		5320	return true;
		5321	case PIPE_B:
		5322	if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		5323	intel_crtc->fdi_lanes > 2) {
		5324	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
		5325	intel_crtc->pipe, intel_crtc->fdi_lanes);
		5326	/* Clamp lanes to avoid programming the hw with bogus values. */
		5327	intel_crtc->fdi_lanes = 2;
		5328
		5329	return false;
		5330	}
		5331
		5332	if (intel_crtc->fdi_lanes > 2)
		5333	WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		5334	else
		5335	cpt_enable_fdi_bc_bifurcation(dev);
		5336
		5337	return true;
		5338	case PIPE_C:
		5339	if (!pipe_B_crtc->base.enabled \|\| pipe_B_crtc->fdi_lanes <= 2) {
		5340	if (intel_crtc->fdi_lanes > 2) {
		5341	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
		5342	intel_crtc->pipe, intel_crtc->fdi_lanes);
		5343	/* Clamp lanes to avoid programming the hw with bogus values. */
		5344	intel_crtc->fdi_lanes = 2;
		5345
		5346	return false;
		5347	}
		5348	} else {
		5349	DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
		5350	return false;
		5351	}
		5352
		5353	cpt_enable_fdi_bc_bifurcation(dev);
		5354
		5355	return true;
		5356	default:
		5357	BUG();
		5358	}
		5359	}
		5360
		5361	int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
		5362	{
		5363	/*
		5364	* Account for spread spectrum to avoid
		5365	* oversubscribing the link. Max center spread
		5366	* is 2.5%; use 5% for safety's sake.
		5367	*/
		5368	u32 bps = target_clock * bpp * 21 / 20;
		5369	return bps / (link_bw * 8) + 1;
		5370	}
		5371
3746	Serge	5372	void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
		5373	struct intel_link_m_n *m_n)
2327	Serge	5374	{
3746	Serge	5375	struct drm_device *dev = crtc->base.dev;
		5376	struct drm_i915_private *dev_priv = dev->dev_private;
		5377	int pipe = crtc->pipe;
		5378
		5379	I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		5380	I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
		5381	I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
		5382	I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
		5383	}
		5384
		5385	void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
		5386	struct intel_link_m_n *m_n)
		5387	{
		5388	struct drm_device *dev = crtc->base.dev;
		5389	struct drm_i915_private *dev_priv = dev->dev_private;
		5390	int pipe = crtc->pipe;
		5391	enum transcoder transcoder = crtc->config.cpu_transcoder;
		5392
		5393	if (INTEL_INFO(dev)->gen >= 5) {
		5394	I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		5395	I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		5396	I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		5397	I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
		5398	} else {
		5399	I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		5400	I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
		5401	I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
		5402	I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
		5403	}
		5404	}
		5405
		5406	static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
		5407	{
2327	Serge	5408	struct drm_device *dev = crtc->dev;
		5409	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5410	struct drm_display_mode *adjusted_mode =
		5411	&intel_crtc->config.adjusted_mode;
3480	Serge	5412	struct intel_link_m_n m_n = {0};
3746	Serge	5413	int target_clock, lane, link_bw;
2327	Serge	5414
		5415	/* FDI is a binary signal running at ~2.7GHz, encoding
		5416	* each output octet as 10 bits. The actual frequency
		5417	* is stored as a divider into a 100MHz clock, and the
		5418	* mode pixel clock is stored in units of 1KHz.
		5419	* Hence the bw of each lane in terms of the mode signal
		5420	* is:
		5421	*/
		5422	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		5423
3746	Serge	5424	if (intel_crtc->config.pixel_target_clock)
		5425	target_clock = intel_crtc->config.pixel_target_clock;
3031	serge	5426	else
		5427	target_clock = adjusted_mode->clock;
		5428
3243	Serge	5429	lane = ironlake_get_lanes_required(target_clock, link_bw,
3746	Serge	5430	intel_crtc->config.pipe_bpp);
3031	serge	5431
2327	Serge	5432	intel_crtc->fdi_lanes = lane;
		5433
3746	Serge	5434	if (intel_crtc->config.pixel_multiplier > 1)
		5435	link_bw *= intel_crtc->config.pixel_multiplier;
		5436	intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
		5437	link_bw, &m_n);
2327	Serge	5438
3746	Serge	5439	intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
3243	Serge	5440	}
2327	Serge	5441
3243	Serge	5442	static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
3746	Serge	5443	intel_clock_t clock, u32 fp,
		5444	intel_clock_t reduced_clock, u32 fp2)
3243	Serge	5445	{
		5446	struct drm_crtc *crtc = &intel_crtc->base;
		5447	struct drm_device *dev = crtc->dev;
		5448	struct drm_i915_private *dev_priv = dev->dev_private;
		5449	struct intel_encoder *intel_encoder;
		5450	uint32_t dpll;
3746	Serge	5451	int factor, num_connectors = 0;
3243	Serge	5452	bool is_lvds = false, is_sdvo = false, is_tv = false;
		5453
		5454	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5455	switch (intel_encoder->type) {
		5456	case INTEL_OUTPUT_LVDS:
		5457	is_lvds = true;
		5458	break;
		5459	case INTEL_OUTPUT_SDVO:
		5460	case INTEL_OUTPUT_HDMI:
		5461	is_sdvo = true;
		5462	if (intel_encoder->needs_tv_clock)
		5463	is_tv = true;
		5464	break;
		5465	case INTEL_OUTPUT_TVOUT:
		5466	is_tv = true;
		5467	break;
		5468	}
		5469
		5470	num_connectors++;
		5471	}
		5472
2327	Serge	5473	/* Enable autotuning of the PLL clock (if permissible) */
		5474	factor = 21;
		5475	if (is_lvds) {
		5476	if ((intel_panel_use_ssc(dev_priv) &&
		5477	dev_priv->lvds_ssc_freq == 100) \|\|
3746	Serge	5478	(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
2327	Serge	5479	factor = 25;
		5480	} else if (is_sdvo && is_tv)
		5481	factor = 20;
		5482
3243	Serge	5483	if (clock->m < factor * clock->n)
3746	Serge	5484	*fp \|= FP_CB_TUNE;
2327	Serge	5485
3746	Serge	5486	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		5487	*fp2 \|= FP_CB_TUNE;
		5488
2327	Serge	5489	dpll = 0;
		5490
		5491	if (is_lvds)
		5492	dpll \|= DPLLB_MODE_LVDS;
		5493	else
		5494	dpll \|= DPLLB_MODE_DAC_SERIAL;
		5495	if (is_sdvo) {
3746	Serge	5496	if (intel_crtc->config.pixel_multiplier > 1) {
		5497	dpll \|= (intel_crtc->config.pixel_multiplier - 1)
		5498	<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2327	Serge	5499	}
		5500	dpll \|= DPLL_DVO_HIGH_SPEED;
		5501	}
3746	Serge	5502	if (intel_crtc->config.has_dp_encoder &&
		5503	intel_crtc->config.has_pch_encoder)
2327	Serge	5504	dpll \|= DPLL_DVO_HIGH_SPEED;
		5505
		5506	/* compute bitmask from p1 value */
3243	Serge	5507	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2327	Serge	5508	/* also FPA1 */
3243	Serge	5509	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2327	Serge	5510
3243	Serge	5511	switch (clock->p2) {
2327	Serge	5512	case 5:
		5513	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		5514	break;
		5515	case 7:
		5516	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		5517	break;
		5518	case 10:
		5519	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		5520	break;
		5521	case 14:
		5522	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		5523	break;
		5524	}
		5525
		5526	if (is_sdvo && is_tv)
		5527	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		5528	else if (is_tv)
		5529	/* XXX: just matching BIOS for now */
		5530	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		5531	dpll \|= 3;
		5532	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		5533	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5534	else
		5535	dpll \|= PLL_REF_INPUT_DREFCLK;
		5536
3243	Serge	5537	return dpll;
		5538	}
		5539
		5540	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		5541	int x, int y,
		5542	struct drm_framebuffer *fb)
		5543	{
		5544	struct drm_device *dev = crtc->dev;
		5545	struct drm_i915_private *dev_priv = dev->dev_private;
		5546	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5547	struct drm_display_mode *adjusted_mode =
		5548	&intel_crtc->config.adjusted_mode;
		5549	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
3243	Serge	5550	int pipe = intel_crtc->pipe;
		5551	int plane = intel_crtc->plane;
		5552	int num_connectors = 0;
		5553	intel_clock_t clock, reduced_clock;
		5554	u32 dpll, fp = 0, fp2 = 0;
		5555	bool ok, has_reduced_clock = false;
3746	Serge	5556	bool is_lvds = false;
3243	Serge	5557	struct intel_encoder *encoder;
		5558	int ret;
		5559	bool dither, fdi_config_ok;
		5560
		5561	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5562	switch (encoder->type) {
		5563	case INTEL_OUTPUT_LVDS:
		5564	is_lvds = true;
		5565	break;
		5566	}
		5567
		5568	num_connectors++;
		5569	}
		5570
		5571	WARN(!(HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)),
		5572	"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
		5573
3746	Serge	5574	intel_crtc->config.cpu_transcoder = pipe;
		5575
3243	Serge	5576	ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
		5577	&has_reduced_clock, &reduced_clock);
		5578	if (!ok) {
		5579	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		5580	return -EINVAL;
		5581	}
3746	Serge	5582	/* Compat-code for transition, will disappear. */
		5583	if (!intel_crtc->config.clock_set) {
		5584	intel_crtc->config.dpll.n = clock.n;
		5585	intel_crtc->config.dpll.m1 = clock.m1;
		5586	intel_crtc->config.dpll.m2 = clock.m2;
		5587	intel_crtc->config.dpll.p1 = clock.p1;
		5588	intel_crtc->config.dpll.p2 = clock.p2;
		5589	}
3243	Serge	5590
		5591	/* Ensure that the cursor is valid for the new mode before changing... */
		5592	// intel_crtc_update_cursor(crtc, true);
		5593
		5594	/* determine panel color depth */
3746	Serge	5595	dither = intel_crtc->config.dither;
3243	Serge	5596	if (is_lvds && dev_priv->lvds_dither)
		5597	dither = true;
		5598
		5599	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;
		5600	if (has_reduced_clock)
		5601	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|
		5602	reduced_clock.m2;
		5603
3746	Serge	5604	dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
		5605	has_reduced_clock ? &fp2 : NULL);
3243	Serge	5606
2342	Serge	5607	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
2327	Serge	5608	drm_mode_debug_printmodeline(mode);
		5609
3243	Serge	5610	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
3746	Serge	5611	if (intel_crtc->config.has_pch_encoder) {
3031	serge	5612	struct intel_pch_pll *pll;
2327	Serge	5613
3031	serge	5614	pll = intel_get_pch_pll(intel_crtc, dpll, fp);
		5615	if (pll == NULL) {
		5616	DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
		5617	pipe);
2342	Serge	5618	return -EINVAL;
2327	Serge	5619	}
3031	serge	5620	} else
		5621	intel_put_pch_pll(intel_crtc);
2327	Serge	5622
3746	Serge	5623	if (intel_crtc->config.has_dp_encoder)
		5624	intel_dp_set_m_n(intel_crtc);
2342	Serge	5625
3480	Serge	5626	for_each_encoder_on_crtc(dev, crtc, encoder)
		5627	if (encoder->pre_pll_enable)
		5628	encoder->pre_pll_enable(encoder);
2327	Serge	5629
3031	serge	5630	if (intel_crtc->pch_pll) {
		5631	I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
2327	Serge	5632
		5633	/* Wait for the clocks to stabilize. */
3031	serge	5634	POSTING_READ(intel_crtc->pch_pll->pll_reg);
2327	Serge	5635	udelay(150);
		5636
		5637	/* The pixel multiplier can only be updated once the
		5638	* DPLL is enabled and the clocks are stable.
		5639	*
		5640	* So write it again.
		5641	*/
3031	serge	5642	I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
2327	Serge	5643	}
		5644
		5645	intel_crtc->lowfreq_avail = false;
3031	serge	5646	if (intel_crtc->pch_pll) {
2327	Serge	5647	if (is_lvds && has_reduced_clock && i915_powersave) {
3031	serge	5648	I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
2327	Serge	5649	intel_crtc->lowfreq_avail = true;
		5650	} else {
3031	serge	5651	I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
2327	Serge	5652	}
2342	Serge	5653	}
2327	Serge	5654
3243	Serge	5655	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
		5656
		5657	/* Note, this also computes intel_crtc->fdi_lanes which is used below in
		5658	* ironlake_check_fdi_lanes. */
3746	Serge	5659	intel_crtc->fdi_lanes = 0;
		5660	if (intel_crtc->config.has_pch_encoder)
		5661	ironlake_fdi_set_m_n(crtc);
3243	Serge	5662
		5663	fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
		5664
		5665	ironlake_set_pipeconf(crtc, adjusted_mode, dither);
		5666
		5667	intel_wait_for_vblank(dev, pipe);
		5668
		5669	/* Set up the display plane register */
		5670	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
		5671	POSTING_READ(DSPCNTR(plane));
		5672
		5673	ret = intel_pipe_set_base(crtc, x, y, fb);
		5674
		5675	intel_update_watermarks(dev);
		5676
		5677	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
		5678
		5679	return fdi_config_ok ? ret : -EINVAL;
		5680	}
		5681
3746	Serge	5682	static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
		5683	struct intel_crtc_config *pipe_config)
		5684	{
		5685	struct drm_device *dev = crtc->base.dev;
		5686	struct drm_i915_private *dev_priv = dev->dev_private;
		5687	uint32_t tmp;
		5688
		5689	tmp = I915_READ(PIPECONF(crtc->pipe));
		5690	if (!(tmp & PIPECONF_ENABLE))
		5691	return false;
		5692
		5693	if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
		5694	pipe_config->has_pch_encoder = true;
		5695
		5696	return true;
		5697	}
		5698
3480	Serge	5699	static void haswell_modeset_global_resources(struct drm_device *dev)
		5700	{
		5701	struct drm_i915_private *dev_priv = dev->dev_private;
		5702	bool enable = false;
		5703	struct intel_crtc *crtc;
		5704	struct intel_encoder *encoder;
		5705
		5706	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
		5707	if (crtc->pipe != PIPE_A && crtc->base.enabled)
		5708	enable = true;
		5709	/* XXX: Should check for edp transcoder here, but thanks to init
		5710	* sequence that's not yet available. Just in case desktop eDP
		5711	* on PORT D is possible on haswell, too. */
		5712	}
		5713
		5714	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		5715	base.head) {
		5716	if (encoder->type != INTEL_OUTPUT_EDP &&
		5717	encoder->connectors_active)
		5718	enable = true;
		5719	}
		5720
		5721	/* Even the eDP panel fitter is outside the always-on well. */
		5722	if (dev_priv->pch_pf_size)
		5723	enable = true;
		5724
		5725	intel_set_power_well(dev, enable);
		5726	}
		5727
3243	Serge	5728	static int haswell_crtc_mode_set(struct drm_crtc *crtc,
		5729	int x, int y,
		5730	struct drm_framebuffer *fb)
		5731	{
		5732	struct drm_device *dev = crtc->dev;
		5733	struct drm_i915_private *dev_priv = dev->dev_private;
		5734	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5735	struct drm_display_mode *adjusted_mode =
		5736	&intel_crtc->config.adjusted_mode;
		5737	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
3243	Serge	5738	int pipe = intel_crtc->pipe;
		5739	int plane = intel_crtc->plane;
		5740	int num_connectors = 0;
3746	Serge	5741	bool is_cpu_edp = false;
3243	Serge	5742	struct intel_encoder *encoder;
		5743	int ret;
		5744	bool dither;
		5745
		5746	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5747	switch (encoder->type) {
		5748	case INTEL_OUTPUT_EDP:
		5749	if (!intel_encoder_is_pch_edp(&encoder->base))
		5750	is_cpu_edp = true;
		5751	break;
		5752	}
		5753
		5754	num_connectors++;
		5755	}
		5756
		5757	if (is_cpu_edp)
3746	Serge	5758	intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
3243	Serge	5759	else
3746	Serge	5760	intel_crtc->config.cpu_transcoder = pipe;
3243	Serge	5761
		5762	/* We are not sure yet this won't happen. */
		5763	WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
		5764	INTEL_PCH_TYPE(dev));
		5765
		5766	WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
		5767	num_connectors, pipe_name(pipe));
		5768
3746	Serge	5769	WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
3243	Serge	5770	(PIPECONF_ENABLE \| I965_PIPECONF_ACTIVE));
		5771
		5772	WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
		5773
		5774	if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
		5775	return -EINVAL;
		5776
		5777	/* Ensure that the cursor is valid for the new mode before changing... */
		5778	// intel_crtc_update_cursor(crtc, true);
		5779
		5780	/* determine panel color depth */
3746	Serge	5781	dither = intel_crtc->config.dither;
3243	Serge	5782
		5783	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
		5784	drm_mode_debug_printmodeline(mode);
		5785
3746	Serge	5786	if (intel_crtc->config.has_dp_encoder)
		5787	intel_dp_set_m_n(intel_crtc);
2327	Serge	5788
3243	Serge	5789	intel_crtc->lowfreq_avail = false;
2327	Serge	5790
3243	Serge	5791	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
		5792
3746	Serge	5793	if (intel_crtc->config.has_pch_encoder)
		5794	ironlake_fdi_set_m_n(crtc);
3243	Serge	5795
		5796	haswell_set_pipeconf(crtc, adjusted_mode, dither);
2327	Serge	5797
3746	Serge	5798	intel_set_pipe_csc(crtc);
3480	Serge	5799
3031	serge	5800	/* Set up the display plane register */
3480	Serge	5801	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE \| DISPPLANE_PIPE_CSC_ENABLE);
2327	Serge	5802	POSTING_READ(DSPCNTR(plane));
		5803
3031	serge	5804	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	5805
		5806	intel_update_watermarks(dev);
		5807
3031	serge	5808	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
2336	Serge	5809
2327	Serge	5810	return ret;
		5811	}
		5812
3746	Serge	5813	static bool haswell_get_pipe_config(struct intel_crtc *crtc,
		5814	struct intel_crtc_config *pipe_config)
		5815	{
		5816	struct drm_device *dev = crtc->base.dev;
		5817	struct drm_i915_private *dev_priv = dev->dev_private;
		5818	uint32_t tmp;
		5819
		5820	tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder));
		5821	if (!(tmp & PIPECONF_ENABLE))
		5822	return false;
		5823
		5824	/*
		5825	* aswell has only FDI/PCH transcoder A. It is which is connected to
		5826	* DDI E. So just check whether this pipe is wired to DDI E and whether
		5827	* the PCH transcoder is on.
		5828	*/
		5829	tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
		5830	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
		5831	I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
		5832	pipe_config->has_pch_encoder = true;
		5833
		5834
		5835	return true;
		5836	}
		5837
2330	Serge	5838	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		5839	int x, int y,
3031	serge	5840	struct drm_framebuffer *fb)
2330	Serge	5841	{
		5842	struct drm_device *dev = crtc->dev;
		5843	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	5844	struct drm_encoder_helper_funcs *encoder_funcs;
		5845	struct intel_encoder *encoder;
2330	Serge	5846	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5847	struct drm_display_mode *adjusted_mode =
		5848	&intel_crtc->config.adjusted_mode;
		5849	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
2330	Serge	5850	int pipe = intel_crtc->pipe;
		5851	int ret;
2327	Serge	5852
3031	serge	5853	drm_vblank_pre_modeset(dev, pipe);
2327	Serge	5854
3746	Serge	5855	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
		5856
3031	serge	5857	drm_vblank_post_modeset(dev, pipe);
2327	Serge	5858
3243	Serge	5859	if (ret != 0)
2330	Serge	5860	return ret;
3243	Serge	5861
		5862	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5863	DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
		5864	encoder->base.base.id,
		5865	drm_get_encoder_name(&encoder->base),
		5866	mode->base.id, mode->name);
3746	Serge	5867	if (encoder->mode_set) {
		5868	encoder->mode_set(encoder);
		5869	} else {
3243	Serge	5870	encoder_funcs = encoder->base.helper_private;
		5871	encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
		5872	}
3746	Serge	5873	}
3243	Serge	5874
		5875	return 0;
2330	Serge	5876	}
2327	Serge	5877
2342	Serge	5878	static bool intel_eld_uptodate(struct drm_connector *connector,
		5879	int reg_eldv, uint32_t bits_eldv,
		5880	int reg_elda, uint32_t bits_elda,
		5881	int reg_edid)
		5882	{
		5883	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5884	uint8_t *eld = connector->eld;
		5885	uint32_t i;
		5886
		5887	i = I915_READ(reg_eldv);
		5888	i &= bits_eldv;
		5889
		5890	if (!eld[0])
		5891	return !i;
		5892
		5893	if (!i)
		5894	return false;
		5895
		5896	i = I915_READ(reg_elda);
		5897	i &= ~bits_elda;
		5898	I915_WRITE(reg_elda, i);
		5899
		5900	for (i = 0; i < eld[2]; i++)
		5901	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
		5902	return false;
		5903
		5904	return true;
		5905	}
		5906
		5907	static void g4x_write_eld(struct drm_connector *connector,
		5908	struct drm_crtc *crtc)
		5909	{
		5910	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5911	uint8_t *eld = connector->eld;
		5912	uint32_t eldv;
		5913	uint32_t len;
		5914	uint32_t i;
		5915
		5916	i = I915_READ(G4X_AUD_VID_DID);
		5917
		5918	if (i == INTEL_AUDIO_DEVBLC \|\| i == INTEL_AUDIO_DEVCL)
		5919	eldv = G4X_ELDV_DEVCL_DEVBLC;
		5920	else
		5921	eldv = G4X_ELDV_DEVCTG;
		5922
		5923	if (intel_eld_uptodate(connector,
		5924	G4X_AUD_CNTL_ST, eldv,
		5925	G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
		5926	G4X_HDMIW_HDMIEDID))
		5927	return;
		5928
		5929	i = I915_READ(G4X_AUD_CNTL_ST);
		5930	i &= ~(eldv \| G4X_ELD_ADDR);
		5931	len = (i >> 9) & 0x1f; /* ELD buffer size */
		5932	I915_WRITE(G4X_AUD_CNTL_ST, i);
		5933
		5934	if (!eld[0])
		5935	return;
		5936
		5937	len = min_t(uint8_t, eld[2], len);
		5938	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		5939	for (i = 0; i < len; i++)
		5940	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
		5941
		5942	i = I915_READ(G4X_AUD_CNTL_ST);
		5943	i \|= eldv;
		5944	I915_WRITE(G4X_AUD_CNTL_ST, i);
		5945	}
		5946
3031	serge	5947	static void haswell_write_eld(struct drm_connector *connector,
		5948	struct drm_crtc *crtc)
		5949	{
		5950	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5951	uint8_t *eld = connector->eld;
		5952	struct drm_device *dev = crtc->dev;
3480	Serge	5953	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	5954	uint32_t eldv;
		5955	uint32_t i;
		5956	int len;
		5957	int pipe = to_intel_crtc(crtc)->pipe;
		5958	int tmp;
		5959
		5960	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
		5961	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
		5962	int aud_config = HSW_AUD_CFG(pipe);
		5963	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
		5964
		5965
		5966	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
		5967
		5968	/* Audio output enable */
		5969	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
		5970	tmp = I915_READ(aud_cntrl_st2);
		5971	tmp \|= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
		5972	I915_WRITE(aud_cntrl_st2, tmp);
		5973
		5974	/* Wait for 1 vertical blank */
		5975	intel_wait_for_vblank(dev, pipe);
		5976
		5977	/* Set ELD valid state */
		5978	tmp = I915_READ(aud_cntrl_st2);
		5979	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
		5980	tmp \|= (AUDIO_ELD_VALID_A << (pipe * 4));
		5981	I915_WRITE(aud_cntrl_st2, tmp);
		5982	tmp = I915_READ(aud_cntrl_st2);
		5983	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
		5984
		5985	/* Enable HDMI mode */
		5986	tmp = I915_READ(aud_config);
		5987	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
		5988	/* clear N_programing_enable and N_value_index */
		5989	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX \| AUD_CONFIG_N_PROG_ENABLE);
		5990	I915_WRITE(aud_config, tmp);
		5991
		5992	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
		5993
		5994	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
3480	Serge	5995	intel_crtc->eld_vld = true;
3031	serge	5996
		5997	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		5998	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		5999	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
		6000	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6001	} else
		6002	I915_WRITE(aud_config, 0);
		6003
		6004	if (intel_eld_uptodate(connector,
		6005	aud_cntrl_st2, eldv,
		6006	aud_cntl_st, IBX_ELD_ADDRESS,
		6007	hdmiw_hdmiedid))
		6008	return;
		6009
		6010	i = I915_READ(aud_cntrl_st2);
		6011	i &= ~eldv;
		6012	I915_WRITE(aud_cntrl_st2, i);
		6013
		6014	if (!eld[0])
		6015	return;
		6016
		6017	i = I915_READ(aud_cntl_st);
		6018	i &= ~IBX_ELD_ADDRESS;
		6019	I915_WRITE(aud_cntl_st, i);
		6020	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
		6021	DRM_DEBUG_DRIVER("port num:%d\n", i);
		6022
		6023	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6024	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6025	for (i = 0; i < len; i++)
		6026	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6027
		6028	i = I915_READ(aud_cntrl_st2);
		6029	i \|= eldv;
		6030	I915_WRITE(aud_cntrl_st2, i);
		6031
		6032	}
		6033
2342	Serge	6034	static void ironlake_write_eld(struct drm_connector *connector,
		6035	struct drm_crtc *crtc)
		6036	{
		6037	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6038	uint8_t *eld = connector->eld;
		6039	uint32_t eldv;
		6040	uint32_t i;
		6041	int len;
		6042	int hdmiw_hdmiedid;
3031	serge	6043	int aud_config;
2342	Serge	6044	int aud_cntl_st;
		6045	int aud_cntrl_st2;
3031	serge	6046	int pipe = to_intel_crtc(crtc)->pipe;
2342	Serge	6047
		6048	if (HAS_PCH_IBX(connector->dev)) {
3031	serge	6049	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		6050	aud_config = IBX_AUD_CFG(pipe);
		6051	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
2342	Serge	6052	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
		6053	} else {
3031	serge	6054	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		6055	aud_config = CPT_AUD_CFG(pipe);
		6056	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
2342	Serge	6057	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
		6058	}
		6059
3031	serge	6060	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
2342	Serge	6061
		6062	i = I915_READ(aud_cntl_st);
3031	serge	6063	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
2342	Serge	6064	if (!i) {
		6065	DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		6066	/* operate blindly on all ports */
		6067	eldv = IBX_ELD_VALIDB;
		6068	eldv \|= IBX_ELD_VALIDB << 4;
		6069	eldv \|= IBX_ELD_VALIDB << 8;
		6070	} else {
		6071	DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
		6072	eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
		6073	}
		6074
		6075	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6076	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6077	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
3031	serge	6078	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6079	} else
		6080	I915_WRITE(aud_config, 0);
2342	Serge	6081
		6082	if (intel_eld_uptodate(connector,
		6083	aud_cntrl_st2, eldv,
		6084	aud_cntl_st, IBX_ELD_ADDRESS,
		6085	hdmiw_hdmiedid))
		6086	return;
		6087
		6088	i = I915_READ(aud_cntrl_st2);
		6089	i &= ~eldv;
		6090	I915_WRITE(aud_cntrl_st2, i);
		6091
		6092	if (!eld[0])
		6093	return;
		6094
		6095	i = I915_READ(aud_cntl_st);
		6096	i &= ~IBX_ELD_ADDRESS;
		6097	I915_WRITE(aud_cntl_st, i);
		6098
		6099	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6100	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6101	for (i = 0; i < len; i++)
		6102	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6103
		6104	i = I915_READ(aud_cntrl_st2);
		6105	i \|= eldv;
		6106	I915_WRITE(aud_cntrl_st2, i);
		6107	}
		6108
		6109	void intel_write_eld(struct drm_encoder *encoder,
		6110	struct drm_display_mode *mode)
		6111	{
		6112	struct drm_crtc *crtc = encoder->crtc;
		6113	struct drm_connector *connector;
		6114	struct drm_device *dev = encoder->dev;
		6115	struct drm_i915_private *dev_priv = dev->dev_private;
		6116
		6117	connector = drm_select_eld(encoder, mode);
		6118	if (!connector)
		6119	return;
		6120
		6121	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		6122	connector->base.id,
		6123	drm_get_connector_name(connector),
		6124	connector->encoder->base.id,
		6125	drm_get_encoder_name(connector->encoder));
		6126
		6127	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
		6128
		6129	if (dev_priv->display.write_eld)
		6130	dev_priv->display.write_eld(connector, crtc);
		6131	}
		6132
2327	Serge	6133	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		6134	void intel_crtc_load_lut(struct drm_crtc *crtc)
		6135	{
		6136	struct drm_device *dev = crtc->dev;
		6137	struct drm_i915_private *dev_priv = dev->dev_private;
		6138	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6139	int palreg = PALETTE(intel_crtc->pipe);
		6140	int i;
		6141
		6142	/* The clocks have to be on to load the palette. */
3031	serge	6143	if (!crtc->enabled \|\| !intel_crtc->active)
2327	Serge	6144	return;
		6145
		6146	/* use legacy palette for Ironlake */
		6147	if (HAS_PCH_SPLIT(dev))
		6148	palreg = LGC_PALETTE(intel_crtc->pipe);
		6149
		6150	for (i = 0; i < 256; i++) {
		6151	I915_WRITE(palreg + 4 * i,
		6152	(intel_crtc->lut_r[i] << 16) \|
		6153	(intel_crtc->lut_g[i] << 8) \|
		6154	intel_crtc->lut_b[i]);
		6155	}
		6156	}
		6157
3031	serge	6158	#if 0
		6159	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
		6160	{
		6161	struct drm_device *dev = crtc->dev;
		6162	struct drm_i915_private *dev_priv = dev->dev_private;
		6163	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6164	bool visible = base != 0;
		6165	u32 cntl;
2327	Serge	6166
3031	serge	6167	if (intel_crtc->cursor_visible == visible)
		6168	return;
2327	Serge	6169
3031	serge	6170	cntl = I915_READ(_CURACNTR);
		6171	if (visible) {
		6172	/* On these chipsets we can only modify the base whilst
		6173	* the cursor is disabled.
		6174	*/
		6175	I915_WRITE(_CURABASE, base);
2327	Serge	6176
3031	serge	6177	cntl &= ~(CURSOR_FORMAT_MASK);
		6178	/* XXX width must be 64, stride 256 => 0x00 << 28 */
		6179	cntl \|= CURSOR_ENABLE \|
		6180	CURSOR_GAMMA_ENABLE \|
		6181	CURSOR_FORMAT_ARGB;
		6182	} else
		6183	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);
		6184	I915_WRITE(_CURACNTR, cntl);
2327	Serge	6185
3031	serge	6186	intel_crtc->cursor_visible = visible;
		6187	}
2327	Serge	6188
3031	serge	6189	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
		6190	{
		6191	struct drm_device *dev = crtc->dev;
		6192	struct drm_i915_private *dev_priv = dev->dev_private;
		6193	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6194	int pipe = intel_crtc->pipe;
		6195	bool visible = base != 0;
2327	Serge	6196
3031	serge	6197	if (intel_crtc->cursor_visible != visible) {
		6198	uint32_t cntl = I915_READ(CURCNTR(pipe));
		6199	if (base) {
		6200	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);
		6201	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6202	cntl \|= pipe << 28; /* Connect to correct pipe */
		6203	} else {
		6204	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6205	cntl \|= CURSOR_MODE_DISABLE;
		6206	}
		6207	I915_WRITE(CURCNTR(pipe), cntl);
2327	Serge	6208
3031	serge	6209	intel_crtc->cursor_visible = visible;
		6210	}
		6211	/* and commit changes on next vblank */
		6212	I915_WRITE(CURBASE(pipe), base);
		6213	}
2327	Serge	6214
3031	serge	6215	static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
		6216	{
		6217	struct drm_device *dev = crtc->dev;
		6218	struct drm_i915_private *dev_priv = dev->dev_private;
		6219	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6220	int pipe = intel_crtc->pipe;
		6221	bool visible = base != 0;
2327	Serge	6222
3031	serge	6223	if (intel_crtc->cursor_visible != visible) {
		6224	uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		6225	if (base) {
		6226	cntl &= ~CURSOR_MODE;
		6227	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6228	} else {
		6229	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6230	cntl \|= CURSOR_MODE_DISABLE;
		6231	}
3480	Serge	6232	if (IS_HASWELL(dev))
		6233	cntl \|= CURSOR_PIPE_CSC_ENABLE;
3031	serge	6234	I915_WRITE(CURCNTR_IVB(pipe), cntl);
2327	Serge	6235
3031	serge	6236	intel_crtc->cursor_visible = visible;
		6237	}
		6238	/* and commit changes on next vblank */
		6239	I915_WRITE(CURBASE_IVB(pipe), base);
		6240	}
2327	Serge	6241
3031	serge	6242	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
		6243	static void intel_crtc_update_cursor(struct drm_crtc *crtc,
		6244	bool on)
		6245	{
		6246	struct drm_device *dev = crtc->dev;
		6247	struct drm_i915_private *dev_priv = dev->dev_private;
		6248	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6249	int pipe = intel_crtc->pipe;
		6250	int x = intel_crtc->cursor_x;
		6251	int y = intel_crtc->cursor_y;
		6252	u32 base, pos;
		6253	bool visible;
2327	Serge	6254
3031	serge	6255	pos = 0;
2327	Serge	6256
3031	serge	6257	if (on && crtc->enabled && crtc->fb) {
		6258	base = intel_crtc->cursor_addr;
		6259	if (x > (int) crtc->fb->width)
		6260	base = 0;
2327	Serge	6261
3031	serge	6262	if (y > (int) crtc->fb->height)
		6263	base = 0;
		6264	} else
		6265	base = 0;
2327	Serge	6266
3031	serge	6267	if (x < 0) {
		6268	if (x + intel_crtc->cursor_width < 0)
		6269	base = 0;
2327	Serge	6270
3031	serge	6271	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		6272	x = -x;
		6273	}
		6274	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	6275
3031	serge	6276	if (y < 0) {
		6277	if (y + intel_crtc->cursor_height < 0)
		6278	base = 0;
2327	Serge	6279
3031	serge	6280	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		6281	y = -y;
		6282	}
		6283	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	6284
3031	serge	6285	visible = base != 0;
		6286	if (!visible && !intel_crtc->cursor_visible)
		6287	return;
2327	Serge	6288
3031	serge	6289	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev)) {
		6290	I915_WRITE(CURPOS_IVB(pipe), pos);
		6291	ivb_update_cursor(crtc, base);
		6292	} else {
		6293	I915_WRITE(CURPOS(pipe), pos);
		6294	if (IS_845G(dev) \|\| IS_I865G(dev))
		6295	i845_update_cursor(crtc, base);
		6296	else
		6297	i9xx_update_cursor(crtc, base);
		6298	}
		6299	}
2327	Serge	6300
3031	serge	6301	static int intel_crtc_cursor_set(struct drm_crtc *crtc,
		6302	struct drm_file *file,
		6303	uint32_t handle,
		6304	uint32_t width, uint32_t height)
		6305	{
		6306	struct drm_device *dev = crtc->dev;
		6307	struct drm_i915_private *dev_priv = dev->dev_private;
		6308	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6309	struct drm_i915_gem_object *obj;
		6310	uint32_t addr;
		6311	int ret;
2327	Serge	6312
3031	serge	6313	/* if we want to turn off the cursor ignore width and height */
		6314	if (!handle) {
		6315	DRM_DEBUG_KMS("cursor off\n");
		6316	addr = 0;
		6317	obj = NULL;
		6318	mutex_lock(&dev->struct_mutex);
		6319	goto finish;
		6320	}
2327	Serge	6321
3031	serge	6322	/* Currently we only support 64x64 cursors */
		6323	if (width != 64 \|\| height != 64) {
		6324	DRM_ERROR("we currently only support 64x64 cursors\n");
		6325	return -EINVAL;
		6326	}
2327	Serge	6327
3031	serge	6328	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
		6329	if (&obj->base == NULL)
		6330	return -ENOENT;
2327	Serge	6331
3031	serge	6332	if (obj->base.size < width * height * 4) {
		6333	DRM_ERROR("buffer is to small\n");
		6334	ret = -ENOMEM;
		6335	goto fail;
		6336	}
2327	Serge	6337
3031	serge	6338	/* we only need to pin inside GTT if cursor is non-phy */
		6339	mutex_lock(&dev->struct_mutex);
		6340	if (!dev_priv->info->cursor_needs_physical) {
3746	Serge	6341	unsigned alignment;
		6342
3031	serge	6343	if (obj->tiling_mode) {
		6344	DRM_ERROR("cursor cannot be tiled\n");
		6345	ret = -EINVAL;
		6346	goto fail_locked;
		6347	}
2327	Serge	6348
3746	Serge	6349	/* Note that the w/a also requires 2 PTE of padding following
		6350	* the bo. We currently fill all unused PTE with the shadow
		6351	* page and so we should always have valid PTE following the
		6352	* cursor preventing the VT-d warning.
		6353	*/
		6354	alignment = 0;
		6355	if (need_vtd_wa(dev))
		6356	alignment = 64*1024;
		6357
		6358	ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
3031	serge	6359	if (ret) {
		6360	DRM_ERROR("failed to move cursor bo into the GTT\n");
		6361	goto fail_locked;
		6362	}
2327	Serge	6363
3031	serge	6364	ret = i915_gem_object_put_fence(obj);
		6365	if (ret) {
		6366	DRM_ERROR("failed to release fence for cursor");
		6367	goto fail_unpin;
		6368	}
2327	Serge	6369
3031	serge	6370	addr = obj->gtt_offset;
		6371	} else {
		6372	int align = IS_I830(dev) ? 16 * 1024 : 256;
		6373	ret = i915_gem_attach_phys_object(dev, obj,
		6374	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
		6375	align);
		6376	if (ret) {
		6377	DRM_ERROR("failed to attach phys object\n");
		6378	goto fail_locked;
		6379	}
		6380	addr = obj->phys_obj->handle->busaddr;
		6381	}
2327	Serge	6382
3031	serge	6383	if (IS_GEN2(dev))
		6384	I915_WRITE(CURSIZE, (height << 12) \| width);
2327	Serge	6385
3031	serge	6386	finish:
		6387	if (intel_crtc->cursor_bo) {
		6388	if (dev_priv->info->cursor_needs_physical) {
		6389	if (intel_crtc->cursor_bo != obj)
		6390	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		6391	} else
		6392	i915_gem_object_unpin(intel_crtc->cursor_bo);
		6393	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
		6394	}
2327	Serge	6395
3031	serge	6396	mutex_unlock(&dev->struct_mutex);
2327	Serge	6397
3031	serge	6398	intel_crtc->cursor_addr = addr;
		6399	intel_crtc->cursor_bo = obj;
		6400	intel_crtc->cursor_width = width;
		6401	intel_crtc->cursor_height = height;
2327	Serge	6402
3031	serge	6403	// intel_crtc_update_cursor(crtc, true);
2327	Serge	6404
3031	serge	6405	return 0;
		6406	fail_unpin:
		6407	i915_gem_object_unpin(obj);
		6408	fail_locked:
		6409	mutex_unlock(&dev->struct_mutex);
		6410	fail:
		6411	drm_gem_object_unreference_unlocked(&obj->base);
		6412	return ret;
		6413	}
2327	Serge	6414
3031	serge	6415	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
		6416	{
		6417	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6418
		6419	intel_crtc->cursor_x = x;
		6420	intel_crtc->cursor_y = y;
		6421
		6422	// intel_crtc_update_cursor(crtc, true);
		6423
		6424	return 0;
		6425	}
		6426	#endif
		6427
2332	Serge	6428	/** Sets the color ramps on behalf of RandR */
		6429	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		6430	u16 blue, int regno)
		6431	{
		6432	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6433
2332	Serge	6434	intel_crtc->lut_r[regno] = red >> 8;
		6435	intel_crtc->lut_g[regno] = green >> 8;
		6436	intel_crtc->lut_b[regno] = blue >> 8;
		6437	}
2327	Serge	6438
2332	Serge	6439	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		6440	u16 *blue, int regno)
		6441	{
		6442	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6443
2332	Serge	6444	*red = intel_crtc->lut_r[regno] << 8;
		6445	*green = intel_crtc->lut_g[regno] << 8;
		6446	*blue = intel_crtc->lut_b[regno] << 8;
		6447	}
2327	Serge	6448
2330	Serge	6449	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		6450	u16 *blue, uint32_t start, uint32_t size)
		6451	{
		6452	int end = (start + size > 256) ? 256 : start + size, i;
		6453	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6454
2330	Serge	6455	for (i = start; i < end; i++) {
		6456	intel_crtc->lut_r[i] = red[i] >> 8;
		6457	intel_crtc->lut_g[i] = green[i] >> 8;
		6458	intel_crtc->lut_b[i] = blue[i] >> 8;
		6459	}
2327	Serge	6460
2330	Serge	6461	intel_crtc_load_lut(crtc);
		6462	}
2327	Serge	6463
2330	Serge	6464	/* VESA 640x480x72Hz mode to set on the pipe */
		6465	static struct drm_display_mode load_detect_mode = {
		6466	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		6467	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		6468	};
2327	Serge	6469
3031	serge	6470	static struct drm_framebuffer *
		6471	intel_framebuffer_create(struct drm_device *dev,
		6472	struct drm_mode_fb_cmd2 *mode_cmd,
		6473	struct drm_i915_gem_object *obj)
		6474	{
		6475	struct intel_framebuffer *intel_fb;
		6476	int ret;
2327	Serge	6477
3031	serge	6478	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		6479	if (!intel_fb) {
		6480	drm_gem_object_unreference_unlocked(&obj->base);
		6481	return ERR_PTR(-ENOMEM);
		6482	}
2327	Serge	6483
3031	serge	6484	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
		6485	if (ret) {
		6486	drm_gem_object_unreference_unlocked(&obj->base);
		6487	kfree(intel_fb);
		6488	return ERR_PTR(ret);
		6489	}
2327	Serge	6490
3031	serge	6491	return &intel_fb->base;
		6492	}
2327	Serge	6493
2330	Serge	6494	static u32
		6495	intel_framebuffer_pitch_for_width(int width, int bpp)
		6496	{
		6497	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		6498	return ALIGN(pitch, 64);
		6499	}
2327	Serge	6500
2330	Serge	6501	static u32
		6502	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		6503	{
		6504	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		6505	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		6506	}
2327	Serge	6507
2330	Serge	6508	static struct drm_framebuffer *
		6509	intel_framebuffer_create_for_mode(struct drm_device *dev,
		6510	struct drm_display_mode *mode,
		6511	int depth, int bpp)
		6512	{
		6513	struct drm_i915_gem_object *obj;
3243	Serge	6514	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327	Serge	6515
2330	Serge	6516	// obj = i915_gem_alloc_object(dev,
		6517	// intel_framebuffer_size_for_mode(mode, bpp));
		6518	// if (obj == NULL)
		6519	return ERR_PTR(-ENOMEM);
2327	Serge	6520
2330	Serge	6521	// mode_cmd.width = mode->hdisplay;
		6522	// mode_cmd.height = mode->vdisplay;
		6523	// mode_cmd.depth = depth;
		6524	// mode_cmd.bpp = bpp;
		6525	// mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
2327	Serge	6526
2330	Serge	6527	// return intel_framebuffer_create(dev, &mode_cmd, obj);
		6528	}
2327	Serge	6529
2330	Serge	6530	static struct drm_framebuffer *
		6531	mode_fits_in_fbdev(struct drm_device *dev,
		6532	struct drm_display_mode *mode)
		6533	{
		6534	struct drm_i915_private *dev_priv = dev->dev_private;
		6535	struct drm_i915_gem_object *obj;
		6536	struct drm_framebuffer *fb;
2327	Serge	6537
2330	Serge	6538	// if (dev_priv->fbdev == NULL)
		6539	// return NULL;
2327	Serge	6540
2330	Serge	6541	// obj = dev_priv->fbdev->ifb.obj;
		6542	// if (obj == NULL)
		6543	return NULL;
2327	Serge	6544
2330	Serge	6545	// if (obj->base.size < mode->vdisplay * fb->pitch)
3031	serge	6546	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		6547	fb->bits_per_pixel))
2330	Serge	6548	// return NULL;
2327	Serge	6549
3031	serge	6550	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		6551	return NULL;
		6552
2330	Serge	6553	// return fb;
		6554	}
2327	Serge	6555
3031	serge	6556	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	6557	struct drm_display_mode *mode,
		6558	struct intel_load_detect_pipe *old)
		6559	{
		6560	struct intel_crtc *intel_crtc;
3031	serge	6561	struct intel_encoder *intel_encoder =
		6562	intel_attached_encoder(connector);
2330	Serge	6563	struct drm_crtc *possible_crtc;
		6564	struct drm_encoder *encoder = &intel_encoder->base;
		6565	struct drm_crtc *crtc = NULL;
		6566	struct drm_device *dev = encoder->dev;
3031	serge	6567	struct drm_framebuffer *fb;
2330	Serge	6568	int i = -1;
2327	Serge	6569
2330	Serge	6570	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		6571	connector->base.id, drm_get_connector_name(connector),
		6572	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	6573
2330	Serge	6574	/*
		6575	* Algorithm gets a little messy:
		6576	*
		6577	* - if the connector already has an assigned crtc, use it (but make
		6578	* sure it's on first)
		6579	*
		6580	* - try to find the first unused crtc that can drive this connector,
		6581	* and use that if we find one
		6582	*/
2327	Serge	6583
2330	Serge	6584	/* See if we already have a CRTC for this connector */
		6585	if (encoder->crtc) {
		6586	crtc = encoder->crtc;
2327	Serge	6587
3480	Serge	6588	mutex_lock(&crtc->mutex);
		6589
3031	serge	6590	old->dpms_mode = connector->dpms;
2330	Serge	6591	old->load_detect_temp = false;
2327	Serge	6592
2330	Serge	6593	/* Make sure the crtc and connector are running */
3031	serge	6594	if (connector->dpms != DRM_MODE_DPMS_ON)
		6595	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	6596
2330	Serge	6597	return true;
		6598	}
2327	Serge	6599
2330	Serge	6600	/* Find an unused one (if possible) */
		6601	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		6602	i++;
		6603	if (!(encoder->possible_crtcs & (1 << i)))
		6604	continue;
		6605	if (!possible_crtc->enabled) {
		6606	crtc = possible_crtc;
		6607	break;
		6608	}
		6609	}
2327	Serge	6610
2330	Serge	6611	/*
		6612	* If we didn't find an unused CRTC, don't use any.
		6613	*/
		6614	if (!crtc) {
		6615	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		6616	return false;
		6617	}
2327	Serge	6618
3480	Serge	6619	mutex_lock(&crtc->mutex);
3031	serge	6620	intel_encoder->new_crtc = to_intel_crtc(crtc);
		6621	to_intel_connector(connector)->new_encoder = intel_encoder;
2327	Serge	6622
2330	Serge	6623	intel_crtc = to_intel_crtc(crtc);
3031	serge	6624	old->dpms_mode = connector->dpms;
2330	Serge	6625	old->load_detect_temp = true;
		6626	old->release_fb = NULL;
2327	Serge	6627
2330	Serge	6628	if (!mode)
		6629	mode = &load_detect_mode;
2327	Serge	6630
2330	Serge	6631	/* We need a framebuffer large enough to accommodate all accesses
		6632	* that the plane may generate whilst we perform load detection.
		6633	* We can not rely on the fbcon either being present (we get called
		6634	* during its initialisation to detect all boot displays, or it may
		6635	* not even exist) or that it is large enough to satisfy the
		6636	* requested mode.
		6637	*/
3031	serge	6638	fb = mode_fits_in_fbdev(dev, mode);
		6639	if (fb == NULL) {
2330	Serge	6640	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	6641	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		6642	old->release_fb = fb;
2330	Serge	6643	} else
		6644	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	6645	if (IS_ERR(fb)) {
2330	Serge	6646	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
3480	Serge	6647	mutex_unlock(&crtc->mutex);
3243	Serge	6648	return false;
2330	Serge	6649	}
2327	Serge	6650
3480	Serge	6651	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
2330	Serge	6652	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		6653	if (old->release_fb)
		6654	old->release_fb->funcs->destroy(old->release_fb);
3480	Serge	6655	mutex_unlock(&crtc->mutex);
3243	Serge	6656	return false;
2330	Serge	6657	}
2327	Serge	6658
2330	Serge	6659	/* let the connector get through one full cycle before testing */
		6660	intel_wait_for_vblank(dev, intel_crtc->pipe);
		6661	return true;
		6662	}
2327	Serge	6663
3031	serge	6664	void intel_release_load_detect_pipe(struct drm_connector *connector,
2330	Serge	6665	struct intel_load_detect_pipe *old)
		6666	{
3031	serge	6667	struct intel_encoder *intel_encoder =
		6668	intel_attached_encoder(connector);
2330	Serge	6669	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	6670	struct drm_crtc *crtc = encoder->crtc;
2327	Serge	6671
2330	Serge	6672	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		6673	connector->base.id, drm_get_connector_name(connector),
		6674	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	6675
2330	Serge	6676	if (old->load_detect_temp) {
3031	serge	6677	to_intel_connector(connector)->new_encoder = NULL;
		6678	intel_encoder->new_crtc = NULL;
		6679	intel_set_mode(crtc, NULL, 0, 0, NULL);
		6680
3480	Serge	6681	if (old->release_fb) {
		6682	drm_framebuffer_unregister_private(old->release_fb);
		6683	drm_framebuffer_unreference(old->release_fb);
		6684	}
2327	Serge	6685
3480	Serge	6686	mutex_unlock(&crtc->mutex);
2330	Serge	6687	return;
		6688	}
2327	Serge	6689
2330	Serge	6690	/* Switch crtc and encoder back off if necessary */
3031	serge	6691	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		6692	connector->funcs->dpms(connector, old->dpms_mode);
3480	Serge	6693
		6694	mutex_unlock(&crtc->mutex);
2330	Serge	6695	}
2327	Serge	6696
2330	Serge	6697	/* Returns the clock of the currently programmed mode of the given pipe. */
		6698	static int intel_crtc_clock_get(struct drm_device dev, struct drm_crtc crtc)
		6699	{
		6700	struct drm_i915_private *dev_priv = dev->dev_private;
		6701	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6702	int pipe = intel_crtc->pipe;
		6703	u32 dpll = I915_READ(DPLL(pipe));
		6704	u32 fp;
		6705	intel_clock_t clock;
2327	Serge	6706
2330	Serge	6707	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		6708	fp = I915_READ(FP0(pipe));
		6709	else
		6710	fp = I915_READ(FP1(pipe));
2327	Serge	6711
2330	Serge	6712	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		6713	if (IS_PINEVIEW(dev)) {
		6714	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		6715	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		6716	} else {
		6717	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		6718	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		6719	}
2327	Serge	6720
2330	Serge	6721	if (!IS_GEN2(dev)) {
		6722	if (IS_PINEVIEW(dev))
		6723	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		6724	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		6725	else
		6726	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		6727	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	6728
2330	Serge	6729	switch (dpll & DPLL_MODE_MASK) {
		6730	case DPLLB_MODE_DAC_SERIAL:
		6731	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		6732	5 : 10;
		6733	break;
		6734	case DPLLB_MODE_LVDS:
		6735	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		6736	7 : 14;
		6737	break;
		6738	default:
		6739	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		6740	"mode\n", (int)(dpll & DPLL_MODE_MASK));
		6741	return 0;
		6742	}
2327	Serge	6743
2330	Serge	6744	/* XXX: Handle the 100Mhz refclk */
		6745	intel_clock(dev, 96000, &clock);
		6746	} else {
		6747	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	6748
2330	Serge	6749	if (is_lvds) {
		6750	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		6751	DPLL_FPA01_P1_POST_DIV_SHIFT);
		6752	clock.p2 = 14;
2327	Serge	6753
2330	Serge	6754	if ((dpll & PLL_REF_INPUT_MASK) ==
		6755	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		6756	/* XXX: might not be 66MHz */
		6757	intel_clock(dev, 66000, &clock);
		6758	} else
		6759	intel_clock(dev, 48000, &clock);
		6760	} else {
		6761	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		6762	clock.p1 = 2;
		6763	else {
		6764	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		6765	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		6766	}
		6767	if (dpll & PLL_P2_DIVIDE_BY_4)
		6768	clock.p2 = 4;
		6769	else
		6770	clock.p2 = 2;
2327	Serge	6771
2330	Serge	6772	intel_clock(dev, 48000, &clock);
		6773	}
		6774	}
2327	Serge	6775
2330	Serge	6776	/* XXX: It would be nice to validate the clocks, but we can't reuse
		6777	* i830PllIsValid() because it relies on the xf86_config connector
		6778	* configuration being accurate, which it isn't necessarily.
		6779	*/
2327	Serge	6780
2330	Serge	6781	return clock.dot;
		6782	}
2327	Serge	6783
2330	Serge	6784	/** Returns the currently programmed mode of the given pipe. */
		6785	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		6786	struct drm_crtc *crtc)
		6787	{
		6788	struct drm_i915_private *dev_priv = dev->dev_private;
		6789	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	6790	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
2330	Serge	6791	struct drm_display_mode *mode;
3243	Serge	6792	int htot = I915_READ(HTOTAL(cpu_transcoder));
		6793	int hsync = I915_READ(HSYNC(cpu_transcoder));
		6794	int vtot = I915_READ(VTOTAL(cpu_transcoder));
		6795	int vsync = I915_READ(VSYNC(cpu_transcoder));
2327	Serge	6796
2330	Serge	6797	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		6798	if (!mode)
		6799	return NULL;
		6800
		6801	mode->clock = intel_crtc_clock_get(dev, crtc);
		6802	mode->hdisplay = (htot & 0xffff) + 1;
		6803	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		6804	mode->hsync_start = (hsync & 0xffff) + 1;
		6805	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		6806	mode->vdisplay = (vtot & 0xffff) + 1;
		6807	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		6808	mode->vsync_start = (vsync & 0xffff) + 1;
		6809	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		6810
		6811	drm_mode_set_name(mode);
		6812
		6813	return mode;
		6814	}
		6815
2327	Serge	6816	static void intel_increase_pllclock(struct drm_crtc *crtc)
		6817	{
		6818	struct drm_device *dev = crtc->dev;
		6819	drm_i915_private_t *dev_priv = dev->dev_private;
		6820	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6821	int pipe = intel_crtc->pipe;
		6822	int dpll_reg = DPLL(pipe);
		6823	int dpll;
		6824
		6825	if (HAS_PCH_SPLIT(dev))
		6826	return;
		6827
		6828	if (!dev_priv->lvds_downclock_avail)
		6829	return;
		6830
		6831	dpll = I915_READ(dpll_reg);
		6832	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		6833	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		6834
3031	serge	6835	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	6836
		6837	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		6838	I915_WRITE(dpll_reg, dpll);
		6839	intel_wait_for_vblank(dev, pipe);
		6840
		6841	dpll = I915_READ(dpll_reg);
		6842	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		6843	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		6844	}
		6845	}
		6846
3031	serge	6847	static void intel_decrease_pllclock(struct drm_crtc *crtc)
		6848	{
		6849	struct drm_device *dev = crtc->dev;
		6850	drm_i915_private_t *dev_priv = dev->dev_private;
		6851	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6852
3031	serge	6853	if (HAS_PCH_SPLIT(dev))
		6854	return;
2327	Serge	6855
3031	serge	6856	if (!dev_priv->lvds_downclock_avail)
		6857	return;
2327	Serge	6858
3031	serge	6859	/*
		6860	* Since this is called by a timer, we should never get here in
		6861	* the manual case.
		6862	*/
		6863	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		6864	int pipe = intel_crtc->pipe;
		6865	int dpll_reg = DPLL(pipe);
		6866	int dpll;
2327	Serge	6867
3031	serge	6868	DRM_DEBUG_DRIVER("downclocking LVDS\n");
2327	Serge	6869
3031	serge	6870	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	6871
3031	serge	6872	dpll = I915_READ(dpll_reg);
		6873	dpll \|= DISPLAY_RATE_SELECT_FPA1;
		6874	I915_WRITE(dpll_reg, dpll);
		6875	intel_wait_for_vblank(dev, pipe);
		6876	dpll = I915_READ(dpll_reg);
		6877	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
		6878	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
		6879	}
2327	Serge	6880
3031	serge	6881	}
2327	Serge	6882
3031	serge	6883	void intel_mark_busy(struct drm_device *dev)
		6884	{
		6885	i915_update_gfx_val(dev->dev_private);
		6886	}
2327	Serge	6887
3031	serge	6888	void intel_mark_idle(struct drm_device *dev)
		6889	{
		6890	struct drm_crtc *crtc;
2327	Serge	6891
3031	serge	6892	if (!i915_powersave)
		6893	return;
2327	Serge	6894
3031	serge	6895	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		6896	if (!crtc->fb)
		6897	continue;
2327	Serge	6898
3480	Serge	6899	intel_decrease_pllclock(crtc);
3031	serge	6900	}
		6901	}
2327	Serge	6902
3480	Serge	6903	void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
3031	serge	6904	{
		6905	struct drm_device *dev = obj->base.dev;
		6906	struct drm_crtc *crtc;
2327	Serge	6907
3031	serge	6908	if (!i915_powersave)
		6909	return;
2327	Serge	6910
3031	serge	6911	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		6912	if (!crtc->fb)
		6913	continue;
2327	Serge	6914
3031	serge	6915	if (to_intel_framebuffer(crtc->fb)->obj == obj)
3480	Serge	6916	intel_increase_pllclock(crtc);
3031	serge	6917	}
		6918	}
2327	Serge	6919
2330	Serge	6920	static void intel_crtc_destroy(struct drm_crtc *crtc)
		6921	{
		6922	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6923	struct drm_device *dev = crtc->dev;
		6924	struct intel_unpin_work *work;
		6925	unsigned long flags;
2327	Serge	6926
2330	Serge	6927	spin_lock_irqsave(&dev->event_lock, flags);
		6928	work = intel_crtc->unpin_work;
		6929	intel_crtc->unpin_work = NULL;
		6930	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6931
2330	Serge	6932	if (work) {
		6933	// cancel_work_sync(&work->work);
		6934	kfree(work);
		6935	}
2327	Serge	6936
2330	Serge	6937	drm_crtc_cleanup(crtc);
2327	Serge	6938
2330	Serge	6939	kfree(intel_crtc);
		6940	}
2327	Serge	6941
3031	serge	6942	#if 0
		6943	static void intel_unpin_work_fn(struct work_struct *__work)
		6944	{
		6945	struct intel_unpin_work *work =
		6946	container_of(__work, struct intel_unpin_work, work);
3243	Serge	6947	struct drm_device *dev = work->crtc->dev;
2327	Serge	6948
3243	Serge	6949	mutex_lock(&dev->struct_mutex);
3031	serge	6950	intel_unpin_fb_obj(work->old_fb_obj);
		6951	drm_gem_object_unreference(&work->pending_flip_obj->base);
		6952	drm_gem_object_unreference(&work->old_fb_obj->base);
2327	Serge	6953
3243	Serge	6954	intel_update_fbc(dev);
		6955	mutex_unlock(&dev->struct_mutex);
		6956
		6957	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
		6958	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
		6959
3031	serge	6960	kfree(work);
		6961	}
2327	Serge	6962
3031	serge	6963	static void do_intel_finish_page_flip(struct drm_device *dev,
		6964	struct drm_crtc *crtc)
		6965	{
		6966	drm_i915_private_t *dev_priv = dev->dev_private;
		6967	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6968	struct intel_unpin_work *work;
		6969	unsigned long flags;
2327	Serge	6970
3031	serge	6971	/* Ignore early vblank irqs */
		6972	if (intel_crtc == NULL)
		6973	return;
2327	Serge	6974
3031	serge	6975	spin_lock_irqsave(&dev->event_lock, flags);
		6976	work = intel_crtc->unpin_work;
3243	Serge	6977
		6978	/* Ensure we don't miss a work->pending update ... */
		6979	smp_rmb();
		6980
		6981	if (work == NULL \|\| atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
3031	serge	6982	spin_unlock_irqrestore(&dev->event_lock, flags);
		6983	return;
		6984	}
2327	Serge	6985
3243	Serge	6986	/* and that the unpin work is consistent wrt ->pending. */
		6987	smp_rmb();
		6988
3031	serge	6989	intel_crtc->unpin_work = NULL;
2327	Serge	6990
3243	Serge	6991	if (work->event)
		6992	drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
2327	Serge	6993
3031	serge	6994	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	6995
3031	serge	6996	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6997
3480	Serge	6998	wake_up_all(&dev_priv->pending_flip_queue);
2327	Serge	6999
3243	Serge	7000	queue_work(dev_priv->wq, &work->work);
		7001
3031	serge	7002	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
		7003	}
2327	Serge	7004
3031	serge	7005	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		7006	{
		7007	drm_i915_private_t *dev_priv = dev->dev_private;
		7008	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	7009
3031	serge	7010	do_intel_finish_page_flip(dev, crtc);
		7011	}
2327	Serge	7012
3031	serge	7013	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		7014	{
		7015	drm_i915_private_t *dev_priv = dev->dev_private;
		7016	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	7017
3031	serge	7018	do_intel_finish_page_flip(dev, crtc);
		7019	}
2327	Serge	7020
3031	serge	7021	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		7022	{
		7023	drm_i915_private_t *dev_priv = dev->dev_private;
		7024	struct intel_crtc *intel_crtc =
		7025	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		7026	unsigned long flags;
2327	Serge	7027
3243	Serge	7028	/* NB: An MMIO update of the plane base pointer will also
		7029	* generate a page-flip completion irq, i.e. every modeset
		7030	* is also accompanied by a spurious intel_prepare_page_flip().
		7031	*/
3031	serge	7032	spin_lock_irqsave(&dev->event_lock, flags);
3243	Serge	7033	if (intel_crtc->unpin_work)
		7034	atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
3031	serge	7035	spin_unlock_irqrestore(&dev->event_lock, flags);
		7036	}
2327	Serge	7037
3243	Serge	7038	inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
		7039	{
		7040	/* Ensure that the work item is consistent when activating it ... */
		7041	smp_wmb();
		7042	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
		7043	/* and that it is marked active as soon as the irq could fire. */
		7044	smp_wmb();
		7045	}
		7046
3031	serge	7047	static int intel_gen2_queue_flip(struct drm_device *dev,
		7048	struct drm_crtc *crtc,
		7049	struct drm_framebuffer *fb,
		7050	struct drm_i915_gem_object *obj)
		7051	{
		7052	struct drm_i915_private *dev_priv = dev->dev_private;
		7053	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7054	u32 flip_mask;
		7055	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7056	int ret;
2327	Serge	7057
3031	serge	7058	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7059	if (ret)
		7060	goto err;
2327	Serge	7061
3031	serge	7062	ret = intel_ring_begin(ring, 6);
		7063	if (ret)
		7064	goto err_unpin;
2327	Serge	7065
3031	serge	7066	/* Can't queue multiple flips, so wait for the previous
		7067	* one to finish before executing the next.
		7068	*/
		7069	if (intel_crtc->plane)
		7070	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7071	else
		7072	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7073	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7074	intel_ring_emit(ring, MI_NOOP);
		7075	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7076	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7077	intel_ring_emit(ring, fb->pitches[0]);
		7078	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		7079	intel_ring_emit(ring, 0); /* aux display base address, unused */
3243	Serge	7080
		7081	intel_mark_page_flip_active(intel_crtc);
3031	serge	7082	intel_ring_advance(ring);
		7083	return 0;
2327	Serge	7084
3031	serge	7085	err_unpin:
		7086	intel_unpin_fb_obj(obj);
		7087	err:
		7088	return ret;
		7089	}
2327	Serge	7090
3031	serge	7091	static int intel_gen3_queue_flip(struct drm_device *dev,
		7092	struct drm_crtc *crtc,
		7093	struct drm_framebuffer *fb,
		7094	struct drm_i915_gem_object *obj)
		7095	{
		7096	struct drm_i915_private *dev_priv = dev->dev_private;
		7097	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7098	u32 flip_mask;
		7099	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7100	int ret;
2327	Serge	7101
3031	serge	7102	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7103	if (ret)
		7104	goto err;
2327	Serge	7105
3031	serge	7106	ret = intel_ring_begin(ring, 6);
		7107	if (ret)
		7108	goto err_unpin;
2327	Serge	7109
3031	serge	7110	if (intel_crtc->plane)
		7111	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7112	else
		7113	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7114	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7115	intel_ring_emit(ring, MI_NOOP);
		7116	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		7117	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7118	intel_ring_emit(ring, fb->pitches[0]);
		7119	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		7120	intel_ring_emit(ring, MI_NOOP);
2327	Serge	7121
3243	Serge	7122	intel_mark_page_flip_active(intel_crtc);
3031	serge	7123	intel_ring_advance(ring);
		7124	return 0;
2327	Serge	7125
3031	serge	7126	err_unpin:
		7127	intel_unpin_fb_obj(obj);
		7128	err:
		7129	return ret;
		7130	}
2327	Serge	7131
3031	serge	7132	static int intel_gen4_queue_flip(struct drm_device *dev,
		7133	struct drm_crtc *crtc,
		7134	struct drm_framebuffer *fb,
		7135	struct drm_i915_gem_object *obj)
		7136	{
		7137	struct drm_i915_private *dev_priv = dev->dev_private;
		7138	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7139	uint32_t pf, pipesrc;
		7140	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7141	int ret;
2327	Serge	7142
3031	serge	7143	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7144	if (ret)
		7145	goto err;
2327	Serge	7146
3031	serge	7147	ret = intel_ring_begin(ring, 4);
		7148	if (ret)
		7149	goto err_unpin;
2327	Serge	7150
3031	serge	7151	/* i965+ uses the linear or tiled offsets from the
		7152	* Display Registers (which do not change across a page-flip)
		7153	* so we need only reprogram the base address.
		7154	*/
		7155	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7156	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7157	intel_ring_emit(ring, fb->pitches[0]);
		7158	intel_ring_emit(ring,
		7159	(obj->gtt_offset + intel_crtc->dspaddr_offset) \|
		7160	obj->tiling_mode);
2327	Serge	7161
3031	serge	7162	/* XXX Enabling the panel-fitter across page-flip is so far
		7163	* untested on non-native modes, so ignore it for now.
		7164	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		7165	*/
		7166	pf = 0;
		7167	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7168	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7169
		7170	intel_mark_page_flip_active(intel_crtc);
3031	serge	7171	intel_ring_advance(ring);
		7172	return 0;
2327	Serge	7173
3031	serge	7174	err_unpin:
		7175	intel_unpin_fb_obj(obj);
		7176	err:
		7177	return ret;
		7178	}
2327	Serge	7179
3031	serge	7180	static int intel_gen6_queue_flip(struct drm_device *dev,
		7181	struct drm_crtc *crtc,
		7182	struct drm_framebuffer *fb,
		7183	struct drm_i915_gem_object *obj)
		7184	{
		7185	struct drm_i915_private *dev_priv = dev->dev_private;
		7186	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7187	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7188	uint32_t pf, pipesrc;
		7189	int ret;
2327	Serge	7190
3031	serge	7191	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7192	if (ret)
		7193	goto err;
2327	Serge	7194
3031	serge	7195	ret = intel_ring_begin(ring, 4);
		7196	if (ret)
		7197	goto err_unpin;
2327	Serge	7198
3031	serge	7199	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7200	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7201	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
		7202	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
2327	Serge	7203
3031	serge	7204	/* Contrary to the suggestions in the documentation,
		7205	* "Enable Panel Fitter" does not seem to be required when page
		7206	* flipping with a non-native mode, and worse causes a normal
		7207	* modeset to fail.
		7208	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		7209	*/
		7210	pf = 0;
		7211	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7212	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7213
		7214	intel_mark_page_flip_active(intel_crtc);
3031	serge	7215	intel_ring_advance(ring);
		7216	return 0;
2327	Serge	7217
3031	serge	7218	err_unpin:
		7219	intel_unpin_fb_obj(obj);
		7220	err:
		7221	return ret;
		7222	}
2327	Serge	7223
3031	serge	7224	/*
		7225	* On gen7 we currently use the blit ring because (in early silicon at least)
		7226	* the render ring doesn't give us interrpts for page flip completion, which
		7227	* means clients will hang after the first flip is queued. Fortunately the
		7228	* blit ring generates interrupts properly, so use it instead.
		7229	*/
		7230	static int intel_gen7_queue_flip(struct drm_device *dev,
		7231	struct drm_crtc *crtc,
		7232	struct drm_framebuffer *fb,
		7233	struct drm_i915_gem_object *obj)
		7234	{
		7235	struct drm_i915_private *dev_priv = dev->dev_private;
		7236	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7237	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
		7238	uint32_t plane_bit = 0;
		7239	int ret;
2327	Serge	7240
3031	serge	7241	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7242	if (ret)
		7243	goto err;
2327	Serge	7244
3031	serge	7245	switch(intel_crtc->plane) {
		7246	case PLANE_A:
		7247	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		7248	break;
		7249	case PLANE_B:
		7250	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		7251	break;
		7252	case PLANE_C:
		7253	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		7254	break;
		7255	default:
		7256	WARN_ONCE(1, "unknown plane in flip command\n");
		7257	ret = -ENODEV;
		7258	goto err_unpin;
		7259	}
2327	Serge	7260
3031	serge	7261	ret = intel_ring_begin(ring, 4);
		7262	if (ret)
		7263	goto err_unpin;
2327	Serge	7264
3031	serge	7265	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		7266	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
		7267	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		7268	intel_ring_emit(ring, (MI_NOOP));
3243	Serge	7269
		7270	intel_mark_page_flip_active(intel_crtc);
3031	serge	7271	intel_ring_advance(ring);
		7272	return 0;
2327	Serge	7273
3031	serge	7274	err_unpin:
		7275	intel_unpin_fb_obj(obj);
		7276	err:
		7277	return ret;
		7278	}
2327	Serge	7279
3031	serge	7280	static int intel_default_queue_flip(struct drm_device *dev,
		7281	struct drm_crtc *crtc,
		7282	struct drm_framebuffer *fb,
		7283	struct drm_i915_gem_object *obj)
		7284	{
		7285	return -ENODEV;
		7286	}
2327	Serge	7287
3031	serge	7288	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		7289	struct drm_framebuffer *fb,
		7290	struct drm_pending_vblank_event *event)
		7291	{
		7292	struct drm_device *dev = crtc->dev;
		7293	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	7294	struct drm_framebuffer *old_fb = crtc->fb;
		7295	struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
3031	serge	7296	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7297	struct intel_unpin_work *work;
		7298	unsigned long flags;
		7299	int ret;
2327	Serge	7300
3031	serge	7301	/* Can't change pixel format via MI display flips. */
		7302	if (fb->pixel_format != crtc->fb->pixel_format)
		7303	return -EINVAL;
2327	Serge	7304
3031	serge	7305	/*
		7306	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		7307	* Note that pitch changes could also affect these register.
		7308	*/
		7309	if (INTEL_INFO(dev)->gen > 3 &&
		7310	(fb->offsets[0] != crtc->fb->offsets[0] \|\|
		7311	fb->pitches[0] != crtc->fb->pitches[0]))
		7312	return -EINVAL;
2327	Serge	7313
3031	serge	7314	work = kzalloc(sizeof *work, GFP_KERNEL);
		7315	if (work == NULL)
		7316	return -ENOMEM;
2327	Serge	7317
3031	serge	7318	work->event = event;
3243	Serge	7319	work->crtc = crtc;
3480	Serge	7320	work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
3031	serge	7321	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	7322
3031	serge	7323	ret = drm_vblank_get(dev, intel_crtc->pipe);
		7324	if (ret)
		7325	goto free_work;
2327	Serge	7326
3031	serge	7327	/* We borrow the event spin lock for protecting unpin_work */
		7328	spin_lock_irqsave(&dev->event_lock, flags);
		7329	if (intel_crtc->unpin_work) {
		7330	spin_unlock_irqrestore(&dev->event_lock, flags);
		7331	kfree(work);
		7332	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	7333
3031	serge	7334	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		7335	return -EBUSY;
		7336	}
		7337	intel_crtc->unpin_work = work;
		7338	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7339
3243	Serge	7340	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		7341	flush_workqueue(dev_priv->wq);
		7342
3031	serge	7343	ret = i915_mutex_lock_interruptible(dev);
		7344	if (ret)
		7345	goto cleanup;
2327	Serge	7346
3031	serge	7347	/* Reference the objects for the scheduled work. */
		7348	drm_gem_object_reference(&work->old_fb_obj->base);
		7349	drm_gem_object_reference(&obj->base);
2327	Serge	7350
3031	serge	7351	crtc->fb = fb;
2327	Serge	7352
3031	serge	7353	work->pending_flip_obj = obj;
2327	Serge	7354
3031	serge	7355	work->enable_stall_check = true;
		7356
3243	Serge	7357	atomic_inc(&intel_crtc->unpin_work_count);
3480	Serge	7358	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3031	serge	7359
		7360	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
		7361	if (ret)
		7362	goto cleanup_pending;
		7363
		7364	intel_disable_fbc(dev);
		7365	intel_mark_fb_busy(obj);
		7366	mutex_unlock(&dev->struct_mutex);
		7367
		7368	trace_i915_flip_request(intel_crtc->plane, obj);
		7369
		7370	return 0;
		7371
		7372	cleanup_pending:
3243	Serge	7373	atomic_dec(&intel_crtc->unpin_work_count);
3480	Serge	7374	crtc->fb = old_fb;
3031	serge	7375	drm_gem_object_unreference(&work->old_fb_obj->base);
		7376	drm_gem_object_unreference(&obj->base);
		7377	mutex_unlock(&dev->struct_mutex);
		7378
		7379	cleanup:
		7380	spin_lock_irqsave(&dev->event_lock, flags);
		7381	intel_crtc->unpin_work = NULL;
		7382	spin_unlock_irqrestore(&dev->event_lock, flags);
		7383
		7384	drm_vblank_put(dev, intel_crtc->pipe);
		7385	free_work:
		7386	kfree(work);
		7387
		7388	return ret;
		7389	}
		7390
		7391	#endif
		7392
		7393	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		7394	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		7395	.load_lut = intel_crtc_load_lut,
		7396	};
		7397
		7398	bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
2330	Serge	7399	{
3031	serge	7400	struct intel_encoder *other_encoder;
		7401	struct drm_crtc *crtc = &encoder->new_crtc->base;
2327	Serge	7402
3031	serge	7403	if (WARN_ON(!crtc))
		7404	return false;
2327	Serge	7405
3031	serge	7406	list_for_each_entry(other_encoder,
		7407	&crtc->dev->mode_config.encoder_list,
		7408	base.head) {
		7409
		7410	if (&other_encoder->new_crtc->base != crtc \|\|
		7411	encoder == other_encoder)
		7412	continue;
		7413	else
		7414	return true;
		7415	}
		7416
		7417	return false;
		7418	}
		7419
		7420	static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
		7421	struct drm_crtc *crtc)
		7422	{
		7423	struct drm_device *dev;
		7424	struct drm_crtc *tmp;
		7425	int crtc_mask = 1;
		7426
		7427	WARN(!crtc, "checking null crtc?\n");
		7428
		7429	dev = crtc->dev;
		7430
		7431	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		7432	if (tmp == crtc)
		7433	break;
		7434	crtc_mask <<= 1;
		7435	}
		7436
		7437	if (encoder->possible_crtcs & crtc_mask)
		7438	return true;
		7439	return false;
		7440	}
		7441
		7442	/**
		7443	* intel_modeset_update_staged_output_state
		7444	*
		7445	* Updates the staged output configuration state, e.g. after we've read out the
		7446	* current hw state.
		7447	*/
		7448	static void intel_modeset_update_staged_output_state(struct drm_device *dev)
		7449	{
		7450	struct intel_encoder *encoder;
		7451	struct intel_connector *connector;
		7452
		7453	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7454	base.head) {
		7455	connector->new_encoder =
		7456	to_intel_encoder(connector->base.encoder);
		7457	}
		7458
		7459	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7460	base.head) {
		7461	encoder->new_crtc =
		7462	to_intel_crtc(encoder->base.crtc);
		7463	}
		7464	}
		7465
		7466	/**
		7467	* intel_modeset_commit_output_state
		7468	*
		7469	* This function copies the stage display pipe configuration to the real one.
		7470	*/
		7471	static void intel_modeset_commit_output_state(struct drm_device *dev)
		7472	{
		7473	struct intel_encoder *encoder;
		7474	struct intel_connector *connector;
		7475
		7476	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7477	base.head) {
		7478	connector->base.encoder = &connector->new_encoder->base;
		7479	}
		7480
		7481	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7482	base.head) {
		7483	encoder->base.crtc = &encoder->new_crtc->base;
		7484	}
		7485	}
		7486
3746	Serge	7487	static int
		7488	pipe_config_set_bpp(struct drm_crtc *crtc,
		7489	struct drm_framebuffer *fb,
		7490	struct intel_crtc_config *pipe_config)
		7491	{
		7492	struct drm_device *dev = crtc->dev;
		7493	struct drm_connector *connector;
		7494	int bpp;
		7495
		7496	switch (fb->pixel_format) {
		7497	case DRM_FORMAT_C8:
		7498	bpp = 83; / since we go through a colormap */
		7499	break;
		7500	case DRM_FORMAT_XRGB1555:
		7501	case DRM_FORMAT_ARGB1555:
		7502	/* checked in intel_framebuffer_init already */
		7503	if (WARN_ON(INTEL_INFO(dev)->gen > 3))
		7504	return -EINVAL;
		7505	case DRM_FORMAT_RGB565:
		7506	bpp = 63; / min is 18bpp */
		7507	break;
		7508	case DRM_FORMAT_XBGR8888:
		7509	case DRM_FORMAT_ABGR8888:
		7510	/* checked in intel_framebuffer_init already */
		7511	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		7512	return -EINVAL;
		7513	case DRM_FORMAT_XRGB8888:
		7514	case DRM_FORMAT_ARGB8888:
		7515	bpp = 8*3;
		7516	break;
		7517	case DRM_FORMAT_XRGB2101010:
		7518	case DRM_FORMAT_ARGB2101010:
		7519	case DRM_FORMAT_XBGR2101010:
		7520	case DRM_FORMAT_ABGR2101010:
		7521	/* checked in intel_framebuffer_init already */
		7522	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		7523	return -EINVAL;
		7524	bpp = 10*3;
		7525	break;
		7526	/* TODO: gen4+ supports 16 bpc floating point, too. */
		7527	default:
		7528	DRM_DEBUG_KMS("unsupported depth\n");
		7529	return -EINVAL;
		7530	}
		7531
		7532	pipe_config->pipe_bpp = bpp;
		7533
		7534	/* Clamp display bpp to EDID value */
		7535	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7536	head) {
		7537	if (connector->encoder && connector->encoder->crtc != crtc)
		7538	continue;
		7539
		7540	/* Don't use an invalid EDID bpc value */
		7541	if (connector->display_info.bpc &&
		7542	connector->display_info.bpc * 3 < bpp) {
		7543	DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
		7544	bpp, connector->display_info.bpc*3);
		7545	pipe_config->pipe_bpp = connector->display_info.bpc*3;
		7546	}
		7547	}
		7548
		7549	return bpp;
		7550	}
		7551
		7552	static struct intel_crtc_config *
		7553	intel_modeset_pipe_config(struct drm_crtc *crtc,
		7554	struct drm_framebuffer *fb,
3031	serge	7555	struct drm_display_mode *mode)
		7556	{
		7557	struct drm_device *dev = crtc->dev;
		7558	struct drm_encoder_helper_funcs *encoder_funcs;
		7559	struct intel_encoder *encoder;
3746	Serge	7560	struct intel_crtc_config *pipe_config;
		7561	int plane_bpp;
3031	serge	7562
3746	Serge	7563	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
		7564	if (!pipe_config)
3031	serge	7565	return ERR_PTR(-ENOMEM);
		7566
3746	Serge	7567	drm_mode_copy(&pipe_config->adjusted_mode, mode);
		7568	drm_mode_copy(&pipe_config->requested_mode, mode);
		7569
		7570	plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
		7571	if (plane_bpp < 0)
		7572	goto fail;
		7573
3031	serge	7574	/* Pass our mode to the connectors and the CRTC to give them a chance to
		7575	* adjust it according to limitations or connector properties, and also
		7576	* a chance to reject the mode entirely.
2330	Serge	7577	*/
3031	serge	7578	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7579	base.head) {
2327	Serge	7580
3031	serge	7581	if (&encoder->new_crtc->base != crtc)
		7582	continue;
3746	Serge	7583
		7584	if (encoder->compute_config) {
		7585	if (!(encoder->compute_config(encoder, pipe_config))) {
		7586	DRM_DEBUG_KMS("Encoder config failure\n");
		7587	goto fail;
		7588	}
		7589
		7590	continue;
		7591	}
		7592
3031	serge	7593	encoder_funcs = encoder->base.helper_private;
3746	Serge	7594	if (!(encoder_funcs->mode_fixup(&encoder->base,
		7595	&pipe_config->requested_mode,
		7596	&pipe_config->adjusted_mode))) {
3031	serge	7597	DRM_DEBUG_KMS("Encoder fixup failed\n");
		7598	goto fail;
		7599	}
		7600	}
2327	Serge	7601
3746	Serge	7602	if (!(intel_crtc_compute_config(crtc, pipe_config))) {
3031	serge	7603	DRM_DEBUG_KMS("CRTC fixup failed\n");
		7604	goto fail;
		7605	}
		7606	DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
2327	Serge	7607
3746	Serge	7608	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
		7609	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		7610	plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
		7611
		7612	return pipe_config;
3031	serge	7613	fail:
3746	Serge	7614	kfree(pipe_config);
3031	serge	7615	return ERR_PTR(-EINVAL);
		7616	}
2327	Serge	7617
3031	serge	7618	/* Computes which crtcs are affected and sets the relevant bits in the mask. For
		7619	* simplicity we use the crtc's pipe number (because it's easier to obtain). */
		7620	static void
		7621	intel_modeset_affected_pipes(struct drm_crtc crtc, unsigned modeset_pipes,
		7622	unsigned prepare_pipes, unsigned disable_pipes)
		7623	{
		7624	struct intel_crtc *intel_crtc;
		7625	struct drm_device *dev = crtc->dev;
		7626	struct intel_encoder *encoder;
		7627	struct intel_connector *connector;
		7628	struct drm_crtc *tmp_crtc;
		7629
		7630	disable_pipes = modeset_pipes = *prepare_pipes = 0;
		7631
		7632	/* Check which crtcs have changed outputs connected to them, these need
		7633	* to be part of the prepare_pipes mask. We don't (yet) support global
		7634	* modeset across multiple crtcs, so modeset_pipes will only have one
		7635	* bit set at most. */
		7636	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7637	base.head) {
		7638	if (connector->base.encoder == &connector->new_encoder->base)
		7639	continue;
		7640
		7641	if (connector->base.encoder) {
		7642	tmp_crtc = connector->base.encoder->crtc;
		7643
		7644	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		7645	}
		7646
		7647	if (connector->new_encoder)
		7648	*prepare_pipes \|=
		7649	1 << connector->new_encoder->new_crtc->pipe;
		7650	}
		7651
		7652	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7653	base.head) {
		7654	if (encoder->base.crtc == &encoder->new_crtc->base)
		7655	continue;
		7656
		7657	if (encoder->base.crtc) {
		7658	tmp_crtc = encoder->base.crtc;
		7659
		7660	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		7661	}
		7662
		7663	if (encoder->new_crtc)
		7664	*prepare_pipes \|= 1 << encoder->new_crtc->pipe;
		7665	}
		7666
		7667	/* Check for any pipes that will be fully disabled ... */
		7668	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		7669	base.head) {
		7670	bool used = false;
		7671
		7672	/* Don't try to disable disabled crtcs. */
		7673	if (!intel_crtc->base.enabled)
		7674	continue;
		7675
		7676	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7677	base.head) {
		7678	if (encoder->new_crtc == intel_crtc)
		7679	used = true;
		7680	}
		7681
		7682	if (!used)
		7683	*disable_pipes \|= 1 << intel_crtc->pipe;
		7684	}
		7685
		7686
		7687	/* set_mode is also used to update properties on life display pipes. */
		7688	intel_crtc = to_intel_crtc(crtc);
		7689	if (crtc->enabled)
		7690	*prepare_pipes \|= 1 << intel_crtc->pipe;
		7691
3746	Serge	7692	/*
		7693	* For simplicity do a full modeset on any pipe where the output routing
		7694	* changed. We could be more clever, but that would require us to be
		7695	* more careful with calling the relevant encoder->mode_set functions.
		7696	*/
3031	serge	7697	if (*prepare_pipes)
		7698	modeset_pipes = prepare_pipes;
		7699
		7700	/* ... and mask these out. */
		7701	modeset_pipes &= ~(disable_pipes);
		7702	prepare_pipes &= ~(disable_pipes);
3746	Serge	7703
		7704	/*
		7705	* HACK: We don't (yet) fully support global modesets. intel_set_config
		7706	* obies this rule, but the modeset restore mode of
		7707	* intel_modeset_setup_hw_state does not.
		7708	*/
		7709	*modeset_pipes &= 1 << intel_crtc->pipe;
		7710	*prepare_pipes &= 1 << intel_crtc->pipe;
2330	Serge	7711	}
2327	Serge	7712
3031	serge	7713	static bool intel_crtc_in_use(struct drm_crtc *crtc)
2330	Serge	7714	{
3031	serge	7715	struct drm_encoder *encoder;
2330	Serge	7716	struct drm_device *dev = crtc->dev;
2327	Serge	7717
3031	serge	7718	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		7719	if (encoder->crtc == crtc)
		7720	return true;
		7721
		7722	return false;
		7723	}
		7724
		7725	static void
		7726	intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
		7727	{
		7728	struct intel_encoder *intel_encoder;
		7729	struct intel_crtc *intel_crtc;
		7730	struct drm_connector *connector;
		7731
		7732	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
		7733	base.head) {
		7734	if (!intel_encoder->base.crtc)
		7735	continue;
		7736
		7737	intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
		7738
		7739	if (prepare_pipes & (1 << intel_crtc->pipe))
		7740	intel_encoder->connectors_active = false;
		7741	}
		7742
		7743	intel_modeset_commit_output_state(dev);
		7744
		7745	/* Update computed state. */
		7746	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		7747	base.head) {
		7748	intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
		7749	}
		7750
		7751	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		7752	if (!connector->encoder \|\| !connector->encoder->crtc)
		7753	continue;
		7754
		7755	intel_crtc = to_intel_crtc(connector->encoder->crtc);
		7756
		7757	if (prepare_pipes & (1 << intel_crtc->pipe)) {
		7758	struct drm_property *dpms_property =
		7759	dev->mode_config.dpms_property;
		7760
		7761	connector->dpms = DRM_MODE_DPMS_ON;
3243	Serge	7762	drm_object_property_set_value(&connector->base,
3031	serge	7763	dpms_property,
		7764	DRM_MODE_DPMS_ON);
		7765
		7766	intel_encoder = to_intel_encoder(connector->encoder);
		7767	intel_encoder->connectors_active = true;
		7768	}
		7769	}
		7770
		7771	}
		7772
		7773	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		7774	list_for_each_entry((intel_crtc), \
		7775	&(dev)->mode_config.crtc_list, \
		7776	base.head) \
		7777	if (mask & (1 <<(intel_crtc)->pipe)) \
		7778
3746	Serge	7779	static bool
		7780	intel_pipe_config_compare(struct intel_crtc_config *current_config,
		7781	struct intel_crtc_config *pipe_config)
		7782	{
		7783	if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
		7784	DRM_ERROR("mismatch in has_pch_encoder "
		7785	"(expected %i, found %i)\n",
		7786	current_config->has_pch_encoder,
		7787	pipe_config->has_pch_encoder);
		7788	return false;
		7789	}
		7790
		7791	return true;
		7792	}
		7793
3031	serge	7794	void
		7795	intel_modeset_check_state(struct drm_device *dev)
		7796	{
3746	Serge	7797	drm_i915_private_t *dev_priv = dev->dev_private;
3031	serge	7798	struct intel_crtc *crtc;
		7799	struct intel_encoder *encoder;
		7800	struct intel_connector *connector;
3746	Serge	7801	struct intel_crtc_config pipe_config;
3031	serge	7802
		7803	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7804	base.head) {
		7805	/* This also checks the encoder/connector hw state with the
		7806	* ->get_hw_state callbacks. */
		7807	intel_connector_check_state(connector);
		7808
		7809	WARN(&connector->new_encoder->base != connector->base.encoder,
		7810	"connector's staged encoder doesn't match current encoder\n");
		7811	}
		7812
		7813	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7814	base.head) {
		7815	bool enabled = false;
		7816	bool active = false;
		7817	enum pipe pipe, tracked_pipe;
		7818
		7819	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		7820	encoder->base.base.id,
		7821	drm_get_encoder_name(&encoder->base));
		7822
		7823	WARN(&encoder->new_crtc->base != encoder->base.crtc,
		7824	"encoder's stage crtc doesn't match current crtc\n");
		7825	WARN(encoder->connectors_active && !encoder->base.crtc,
		7826	"encoder's active_connectors set, but no crtc\n");
		7827
		7828	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7829	base.head) {
		7830	if (connector->base.encoder != &encoder->base)
		7831	continue;
		7832	enabled = true;
		7833	if (connector->base.dpms != DRM_MODE_DPMS_OFF)
		7834	active = true;
		7835	}
		7836	WARN(!!encoder->base.crtc != enabled,
		7837	"encoder's enabled state mismatch "
		7838	"(expected %i, found %i)\n",
		7839	!!encoder->base.crtc, enabled);
		7840	WARN(active && !encoder->base.crtc,
		7841	"active encoder with no crtc\n");
		7842
		7843	WARN(encoder->connectors_active != active,
		7844	"encoder's computed active state doesn't match tracked active state "
		7845	"(expected %i, found %i)\n", active, encoder->connectors_active);
		7846
		7847	active = encoder->get_hw_state(encoder, &pipe);
		7848	WARN(active != encoder->connectors_active,
		7849	"encoder's hw state doesn't match sw tracking "
		7850	"(expected %i, found %i)\n",
		7851	encoder->connectors_active, active);
		7852
		7853	if (!encoder->base.crtc)
		7854	continue;
		7855
		7856	tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		7857	WARN(active && pipe != tracked_pipe,
		7858	"active encoder's pipe doesn't match"
		7859	"(expected %i, found %i)\n",
		7860	tracked_pipe, pipe);
		7861
		7862	}
		7863
		7864	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		7865	base.head) {
		7866	bool enabled = false;
		7867	bool active = false;
		7868
		7869	DRM_DEBUG_KMS("[CRTC:%d]\n",
		7870	crtc->base.base.id);
		7871
		7872	WARN(crtc->active && !crtc->base.enabled,
		7873	"active crtc, but not enabled in sw tracking\n");
		7874
		7875	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7876	base.head) {
		7877	if (encoder->base.crtc != &crtc->base)
		7878	continue;
		7879	enabled = true;
		7880	if (encoder->connectors_active)
		7881	active = true;
		7882	}
		7883	WARN(active != crtc->active,
		7884	"crtc's computed active state doesn't match tracked active state "
		7885	"(expected %i, found %i)\n", active, crtc->active);
		7886	WARN(enabled != crtc->base.enabled,
		7887	"crtc's computed enabled state doesn't match tracked enabled state "
		7888	"(expected %i, found %i)\n", enabled, crtc->base.enabled);
		7889
3746	Serge	7890	memset(&pipe_config, 0, sizeof(pipe_config));
		7891	active = dev_priv->display.get_pipe_config(crtc,
		7892	&pipe_config);
		7893
		7894	/* hw state is inconsistent with the pipe A quirk */
		7895	if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		7896	active = crtc->active;
		7897
		7898	WARN(crtc->active != active,
		7899	"crtc active state doesn't match with hw state "
		7900	"(expected %i, found %i)\n", crtc->active, active);
		7901
		7902	WARN(active &&
		7903	!intel_pipe_config_compare(&crtc->config, &pipe_config),
		7904	"pipe state doesn't match!\n");
3031	serge	7905	}
		7906	}
		7907
3746	Serge	7908	static int __intel_set_mode(struct drm_crtc *crtc,
3031	serge	7909	struct drm_display_mode *mode,
		7910	int x, int y, struct drm_framebuffer *fb)
		7911	{
		7912	struct drm_device *dev = crtc->dev;
		7913	drm_i915_private_t *dev_priv = dev->dev_private;
3746	Serge	7914	struct drm_display_mode saved_mode, saved_hwmode;
		7915	struct intel_crtc_config *pipe_config = NULL;
3031	serge	7916	struct intel_crtc *intel_crtc;
		7917	unsigned disable_pipes, prepare_pipes, modeset_pipes;
3480	Serge	7918	int ret = 0;
3031	serge	7919
3480	Serge	7920	saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
		7921	if (!saved_mode)
		7922	return -ENOMEM;
		7923	saved_hwmode = saved_mode + 1;
		7924
3031	serge	7925	intel_modeset_affected_pipes(crtc, &modeset_pipes,
		7926	&prepare_pipes, &disable_pipes);
		7927
3480	Serge	7928	*saved_hwmode = crtc->hwmode;
		7929	*saved_mode = crtc->mode;
3031	serge	7930
		7931	/* Hack: Because we don't (yet) support global modeset on multiple
		7932	* crtcs, we don't keep track of the new mode for more than one crtc.
		7933	* Hence simply check whether any bit is set in modeset_pipes in all the
		7934	* pieces of code that are not yet converted to deal with mutliple crtcs
		7935	* changing their mode at the same time. */
		7936	if (modeset_pipes) {
3746	Serge	7937	pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
		7938	if (IS_ERR(pipe_config)) {
		7939	ret = PTR_ERR(pipe_config);
		7940	pipe_config = NULL;
		7941
3480	Serge	7942	goto out;
3031	serge	7943	}
		7944	}
		7945
3746	Serge	7946	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		7947	modeset_pipes, prepare_pipes, disable_pipes);
		7948
		7949	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		7950	intel_crtc_disable(&intel_crtc->base);
		7951
3031	serge	7952	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		7953	if (intel_crtc->base.enabled)
		7954	dev_priv->display.crtc_disable(&intel_crtc->base);
		7955	}
		7956
		7957	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
		7958	* to set it here already despite that we pass it down the callchain.
2330	Serge	7959	*/
3746	Serge	7960	if (modeset_pipes) {
		7961	enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
3031	serge	7962	crtc->mode = *mode;
3746	Serge	7963	/* mode_set/enable/disable functions rely on a correct pipe
		7964	* config. */
		7965	to_intel_crtc(crtc)->config = *pipe_config;
		7966	to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
		7967	}
2327	Serge	7968
3031	serge	7969	/* Only after disabling all output pipelines that will be changed can we
		7970	* update the the output configuration. */
		7971	intel_modeset_update_state(dev, prepare_pipes);
		7972
3243	Serge	7973	if (dev_priv->display.modeset_global_resources)
		7974	dev_priv->display.modeset_global_resources(dev);
		7975
3031	serge	7976	/* Set up the DPLL and any encoders state that needs to adjust or depend
		7977	* on the DPLL.
2330	Serge	7978	*/
3031	serge	7979	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
3480	Serge	7980	ret = intel_crtc_mode_set(&intel_crtc->base,
3031	serge	7981	x, y, fb);
3480	Serge	7982	if (ret)
3031	serge	7983	goto done;
		7984	}
		7985
		7986	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
		7987	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		7988	dev_priv->display.crtc_enable(&intel_crtc->base);
		7989
		7990	if (modeset_pipes) {
		7991	/* Store real post-adjustment hardware mode. */
3746	Serge	7992	crtc->hwmode = pipe_config->adjusted_mode;
3031	serge	7993
		7994	/* Calculate and store various constants which
		7995	* are later needed by vblank and swap-completion
		7996	* timestamping. They are derived from true hwmode.
		7997	*/
		7998	drm_calc_timestamping_constants(crtc);
		7999	}
		8000
		8001	/* FIXME: add subpixel order */
		8002	done:
3480	Serge	8003	if (ret && crtc->enabled) {
		8004	crtc->hwmode = *saved_hwmode;
		8005	crtc->mode = *saved_mode;
3031	serge	8006	}
		8007
3480	Serge	8008	out:
3746	Serge	8009	kfree(pipe_config);
3480	Serge	8010	kfree(saved_mode);
3031	serge	8011	return ret;
2330	Serge	8012	}
2327	Serge	8013
3746	Serge	8014	int intel_set_mode(struct drm_crtc *crtc,
		8015	struct drm_display_mode *mode,
		8016	int x, int y, struct drm_framebuffer *fb)
		8017	{
		8018	int ret;
		8019
		8020	ret = __intel_set_mode(crtc, mode, x, y, fb);
		8021
		8022	if (ret == 0)
		8023	intel_modeset_check_state(crtc->dev);
		8024
		8025	return ret;
		8026	}
		8027
3480	Serge	8028	void intel_crtc_restore_mode(struct drm_crtc *crtc)
		8029	{
		8030	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
		8031	}
		8032
3031	serge	8033	#undef for_each_intel_crtc_masked
2327	Serge	8034
3031	serge	8035	static void intel_set_config_free(struct intel_set_config *config)
		8036	{
		8037	if (!config)
		8038	return;
		8039
		8040	kfree(config->save_connector_encoders);
		8041	kfree(config->save_encoder_crtcs);
		8042	kfree(config);
		8043	}
		8044
		8045	static int intel_set_config_save_state(struct drm_device *dev,
		8046	struct intel_set_config *config)
		8047	{
		8048	struct drm_encoder *encoder;
		8049	struct drm_connector *connector;
		8050	int count;
		8051
		8052	config->save_encoder_crtcs =
		8053	kcalloc(dev->mode_config.num_encoder,
		8054	sizeof(struct drm_crtc *), GFP_KERNEL);
		8055	if (!config->save_encoder_crtcs)
		8056	return -ENOMEM;
		8057
		8058	config->save_connector_encoders =
		8059	kcalloc(dev->mode_config.num_connector,
		8060	sizeof(struct drm_encoder *), GFP_KERNEL);
		8061	if (!config->save_connector_encoders)
		8062	return -ENOMEM;
		8063
		8064	/* Copy data. Note that driver private data is not affected.
		8065	* Should anything bad happen only the expected state is
		8066	* restored, not the drivers personal bookkeeping.
		8067	*/
		8068	count = 0;
		8069	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		8070	config->save_encoder_crtcs[count++] = encoder->crtc;
		8071	}
		8072
		8073	count = 0;
		8074	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		8075	config->save_connector_encoders[count++] = connector->encoder;
		8076	}
		8077
		8078	return 0;
		8079	}
		8080
		8081	static void intel_set_config_restore_state(struct drm_device *dev,
		8082	struct intel_set_config *config)
		8083	{
		8084	struct intel_encoder *encoder;
		8085	struct intel_connector *connector;
		8086	int count;
		8087
		8088	count = 0;
		8089	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		8090	encoder->new_crtc =
		8091	to_intel_crtc(config->save_encoder_crtcs[count++]);
		8092	}
		8093
		8094	count = 0;
		8095	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		8096	connector->new_encoder =
		8097	to_intel_encoder(config->save_connector_encoders[count++]);
		8098	}
		8099	}
		8100
3746	Serge	8101	static bool
		8102	is_crtc_connector_off(struct drm_crtc crtc, struct drm_connector connectors,
		8103	int num_connectors)
		8104	{
		8105	int i;
		8106
		8107	for (i = 0; i < num_connectors; i++)
		8108	if (connectors[i].encoder &&
		8109	connectors[i].encoder->crtc == crtc &&
		8110	connectors[i].dpms != DRM_MODE_DPMS_ON)
		8111	return true;
		8112
		8113	return false;
		8114	}
		8115
3031	serge	8116	static void
		8117	intel_set_config_compute_mode_changes(struct drm_mode_set *set,
		8118	struct intel_set_config *config)
		8119	{
		8120
		8121	/* We should be able to check here if the fb has the same properties
		8122	* and then just flip_or_move it */
3746	Serge	8123	if (set->connectors != NULL &&
		8124	is_crtc_connector_off(set->crtc, *set->connectors,
		8125	set->num_connectors)) {
		8126	config->mode_changed = true;
		8127	} else if (set->crtc->fb != set->fb) {
3031	serge	8128	/* If we have no fb then treat it as a full mode set */
		8129	if (set->crtc->fb == NULL) {
		8130	DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
		8131	config->mode_changed = true;
		8132	} else if (set->fb == NULL) {
		8133	config->mode_changed = true;
3746	Serge	8134	} else if (set->fb->pixel_format !=
		8135	set->crtc->fb->pixel_format) {
3031	serge	8136	config->mode_changed = true;
3746	Serge	8137	} else {
3031	serge	8138	config->fb_changed = true;
		8139	}
3746	Serge	8140	}
3031	serge	8141
		8142	if (set->fb && (set->x != set->crtc->x \|\| set->y != set->crtc->y))
		8143	config->fb_changed = true;
		8144
		8145	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		8146	DRM_DEBUG_KMS("modes are different, full mode set\n");
		8147	drm_mode_debug_printmodeline(&set->crtc->mode);
		8148	drm_mode_debug_printmodeline(set->mode);
		8149	config->mode_changed = true;
		8150	}
		8151	}
		8152
		8153	static int
		8154	intel_modeset_stage_output_state(struct drm_device *dev,
		8155	struct drm_mode_set *set,
		8156	struct intel_set_config *config)
		8157	{
		8158	struct drm_crtc *new_crtc;
		8159	struct intel_connector *connector;
		8160	struct intel_encoder *encoder;
		8161	int count, ro;
		8162
3480	Serge	8163	/* The upper layers ensure that we either disable a crtc or have a list
3031	serge	8164	* of connectors. For paranoia, double-check this. */
		8165	WARN_ON(!set->fb && (set->num_connectors != 0));
		8166	WARN_ON(set->fb && (set->num_connectors == 0));
		8167
		8168	count = 0;
		8169	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8170	base.head) {
		8171	/* Otherwise traverse passed in connector list and get encoders
		8172	* for them. */
		8173	for (ro = 0; ro < set->num_connectors; ro++) {
		8174	if (set->connectors[ro] == &connector->base) {
		8175	connector->new_encoder = connector->encoder;
		8176	break;
		8177	}
		8178	}
		8179
		8180	/* If we disable the crtc, disable all its connectors. Also, if
		8181	* the connector is on the changing crtc but not on the new
		8182	* connector list, disable it. */
		8183	if ((!set->fb \|\| ro == set->num_connectors) &&
		8184	connector->base.encoder &&
		8185	connector->base.encoder->crtc == set->crtc) {
		8186	connector->new_encoder = NULL;
		8187
		8188	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
		8189	connector->base.base.id,
		8190	drm_get_connector_name(&connector->base));
		8191	}
		8192
		8193
		8194	if (&connector->new_encoder->base != connector->base.encoder) {
		8195	DRM_DEBUG_KMS("encoder changed, full mode switch\n");
		8196	config->mode_changed = true;
		8197	}
		8198	}
		8199	/* connector->new_encoder is now updated for all connectors. */
		8200
		8201	/* Update crtc of enabled connectors. */
		8202	count = 0;
		8203	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8204	base.head) {
		8205	if (!connector->new_encoder)
		8206	continue;
		8207
		8208	new_crtc = connector->new_encoder->base.crtc;
		8209
		8210	for (ro = 0; ro < set->num_connectors; ro++) {
		8211	if (set->connectors[ro] == &connector->base)
		8212	new_crtc = set->crtc;
		8213	}
		8214
		8215	/* Make sure the new CRTC will work with the encoder */
		8216	if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
		8217	new_crtc)) {
		8218	return -EINVAL;
		8219	}
		8220	connector->encoder->new_crtc = to_intel_crtc(new_crtc);
		8221
		8222	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
		8223	connector->base.base.id,
		8224	drm_get_connector_name(&connector->base),
		8225	new_crtc->base.id);
		8226	}
		8227
		8228	/* Check for any encoders that needs to be disabled. */
		8229	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8230	base.head) {
		8231	list_for_each_entry(connector,
		8232	&dev->mode_config.connector_list,
		8233	base.head) {
		8234	if (connector->new_encoder == encoder) {
		8235	WARN_ON(!connector->new_encoder->new_crtc);
		8236
		8237	goto next_encoder;
		8238	}
		8239	}
		8240	encoder->new_crtc = NULL;
		8241	next_encoder:
		8242	/* Only now check for crtc changes so we don't miss encoders
		8243	* that will be disabled. */
		8244	if (&encoder->new_crtc->base != encoder->base.crtc) {
		8245	DRM_DEBUG_KMS("crtc changed, full mode switch\n");
		8246	config->mode_changed = true;
		8247	}
		8248	}
		8249	/* Now we've also updated encoder->new_crtc for all encoders. */
		8250
		8251	return 0;
		8252	}
		8253
		8254	static int intel_crtc_set_config(struct drm_mode_set *set)
		8255	{
		8256	struct drm_device *dev;
		8257	struct drm_mode_set save_set;
		8258	struct intel_set_config *config;
		8259	int ret;
		8260
		8261	BUG_ON(!set);
		8262	BUG_ON(!set->crtc);
		8263	BUG_ON(!set->crtc->helper_private);
		8264
3480	Serge	8265	/* Enforce sane interface api - has been abused by the fb helper. */
		8266	BUG_ON(!set->mode && set->fb);
		8267	BUG_ON(set->fb && set->num_connectors == 0);
3031	serge	8268
		8269	if (set->fb) {
		8270	DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
		8271	set->crtc->base.id, set->fb->base.id,
		8272	(int)set->num_connectors, set->x, set->y);
		8273	} else {
		8274	DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
		8275	}
		8276
		8277	dev = set->crtc->dev;
		8278
		8279	ret = -ENOMEM;
		8280	config = kzalloc(sizeof(*config), GFP_KERNEL);
		8281	if (!config)
		8282	goto out_config;
		8283
		8284	ret = intel_set_config_save_state(dev, config);
		8285	if (ret)
		8286	goto out_config;
		8287
		8288	save_set.crtc = set->crtc;
		8289	save_set.mode = &set->crtc->mode;
		8290	save_set.x = set->crtc->x;
		8291	save_set.y = set->crtc->y;
		8292	save_set.fb = set->crtc->fb;
		8293
		8294	/* Compute whether we need a full modeset, only an fb base update or no
		8295	* change at all. In the future we might also check whether only the
		8296	* mode changed, e.g. for LVDS where we only change the panel fitter in
		8297	* such cases. */
		8298	intel_set_config_compute_mode_changes(set, config);
		8299
		8300	ret = intel_modeset_stage_output_state(dev, set, config);
		8301	if (ret)
		8302	goto fail;
		8303
		8304	if (config->mode_changed) {
		8305	if (set->mode) {
		8306	DRM_DEBUG_KMS("attempting to set mode from"
		8307	" userspace\n");
		8308	drm_mode_debug_printmodeline(set->mode);
		8309	}
		8310
3480	Serge	8311	ret = intel_set_mode(set->crtc, set->mode,
		8312	set->x, set->y, set->fb);
3031	serge	8313	} else if (config->fb_changed) {
3746	Serge	8314	// intel_crtc_wait_for_pending_flips(set->crtc);
		8315
3031	serge	8316	ret = intel_pipe_set_base(set->crtc,
		8317	set->x, set->y, set->fb);
		8318	}
		8319
3746	Serge	8320	if (ret) {
		8321	DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
		8322	set->crtc->base.id, ret);
3031	serge	8323	fail:
		8324	intel_set_config_restore_state(dev, config);
		8325
		8326	/* Try to restore the config */
		8327	if (config->mode_changed &&
3480	Serge	8328	intel_set_mode(save_set.crtc, save_set.mode,
3031	serge	8329	save_set.x, save_set.y, save_set.fb))
		8330	DRM_ERROR("failed to restore config after modeset failure\n");
3746	Serge	8331	}
3031	serge	8332
		8333	out_config:
		8334	intel_set_config_free(config);
		8335	return ret;
		8336	}
		8337
2330	Serge	8338	static const struct drm_crtc_funcs intel_crtc_funcs = {
		8339	// .cursor_set = intel_crtc_cursor_set,
		8340	// .cursor_move = intel_crtc_cursor_move,
		8341	.gamma_set = intel_crtc_gamma_set,
3031	serge	8342	.set_config = intel_crtc_set_config,
2330	Serge	8343	.destroy = intel_crtc_destroy,
		8344	// .page_flip = intel_crtc_page_flip,
		8345	};
2327	Serge	8346
3243	Serge	8347	static void intel_cpu_pll_init(struct drm_device *dev)
		8348	{
3480	Serge	8349	if (HAS_DDI(dev))
3243	Serge	8350	intel_ddi_pll_init(dev);
		8351	}
		8352
3031	serge	8353	static void intel_pch_pll_init(struct drm_device *dev)
		8354	{
		8355	drm_i915_private_t *dev_priv = dev->dev_private;
		8356	int i;
		8357
		8358	if (dev_priv->num_pch_pll == 0) {
		8359	DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
		8360	return;
		8361	}
		8362
		8363	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		8364	dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
		8365	dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
		8366	dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
		8367	}
		8368	}
		8369
2330	Serge	8370	static void intel_crtc_init(struct drm_device *dev, int pipe)
		8371	{
		8372	drm_i915_private_t *dev_priv = dev->dev_private;
		8373	struct intel_crtc *intel_crtc;
		8374	int i;
2327	Serge	8375
2330	Serge	8376	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		8377	if (intel_crtc == NULL)
		8378	return;
2327	Serge	8379
2330	Serge	8380	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	8381
2330	Serge	8382	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		8383	for (i = 0; i < 256; i++) {
		8384	intel_crtc->lut_r[i] = i;
		8385	intel_crtc->lut_g[i] = i;
		8386	intel_crtc->lut_b[i] = i;
		8387	}
2327	Serge	8388
2330	Serge	8389	/* Swap pipes & planes for FBC on pre-965 */
		8390	intel_crtc->pipe = pipe;
		8391	intel_crtc->plane = pipe;
3746	Serge	8392	intel_crtc->config.cpu_transcoder = pipe;
2330	Serge	8393	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		8394	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		8395	intel_crtc->plane = !pipe;
		8396	}
2327	Serge	8397
2330	Serge	8398	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		8399	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		8400	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		8401	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	8402
2330	Serge	8403	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
		8404	}
2327	Serge	8405
3031	serge	8406	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		8407	struct drm_file *file)
		8408	{
		8409	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
		8410	struct drm_mode_object *drmmode_obj;
		8411	struct intel_crtc *crtc;
2327	Serge	8412
3482	Serge	8413	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		8414	return -ENODEV;
		8415
3031	serge	8416	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
		8417	DRM_MODE_OBJECT_CRTC);
2327	Serge	8418
3031	serge	8419	if (!drmmode_obj) {
		8420	DRM_ERROR("no such CRTC id\n");
		8421	return -EINVAL;
		8422	}
2327	Serge	8423
3031	serge	8424	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
		8425	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	8426
3031	serge	8427	return 0;
		8428	}
2327	Serge	8429
3031	serge	8430	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	8431	{
3031	serge	8432	struct drm_device *dev = encoder->base.dev;
		8433	struct intel_encoder *source_encoder;
2330	Serge	8434	int index_mask = 0;
		8435	int entry = 0;
2327	Serge	8436
3031	serge	8437	list_for_each_entry(source_encoder,
		8438	&dev->mode_config.encoder_list, base.head) {
		8439
		8440	if (encoder == source_encoder)
2330	Serge	8441	index_mask \|= (1 << entry);
3031	serge	8442
		8443	/* Intel hw has only one MUX where enocoders could be cloned. */
		8444	if (encoder->cloneable && source_encoder->cloneable)
		8445	index_mask \|= (1 << entry);
		8446
2330	Serge	8447	entry++;
		8448	}
2327	Serge	8449
2330	Serge	8450	return index_mask;
		8451	}
2327	Serge	8452
2330	Serge	8453	static bool has_edp_a(struct drm_device *dev)
		8454	{
		8455	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	8456
2330	Serge	8457	if (!IS_MOBILE(dev))
		8458	return false;
2327	Serge	8459
2330	Serge	8460	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		8461	return false;
2327	Serge	8462
2330	Serge	8463	if (IS_GEN5(dev) &&
		8464	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		8465	return false;
2327	Serge	8466
2330	Serge	8467	return true;
		8468	}
2327	Serge	8469
2330	Serge	8470	static void intel_setup_outputs(struct drm_device *dev)
		8471	{
		8472	struct drm_i915_private *dev_priv = dev->dev_private;
		8473	struct intel_encoder *encoder;
		8474	bool dpd_is_edp = false;
3031	serge	8475	bool has_lvds;
2327	Serge	8476
2330	Serge	8477	has_lvds = intel_lvds_init(dev);
		8478	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		8479	/* disable the panel fitter on everything but LVDS */
		8480	I915_WRITE(PFIT_CONTROL, 0);
		8481	}
2327	Serge	8482
3746	Serge	8483	if (!IS_ULT(dev))
2330	Serge	8484	intel_crt_init(dev);
2327	Serge	8485
3480	Serge	8486	if (HAS_DDI(dev)) {
2330	Serge	8487	int found;
2327	Serge	8488
3031	serge	8489	/* Haswell uses DDI functions to detect digital outputs */
		8490	found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		8491	/* DDI A only supports eDP */
		8492	if (found)
		8493	intel_ddi_init(dev, PORT_A);
		8494
		8495	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		8496	* register */
		8497	found = I915_READ(SFUSE_STRAP);
		8498
		8499	if (found & SFUSE_STRAP_DDIB_DETECTED)
		8500	intel_ddi_init(dev, PORT_B);
		8501	if (found & SFUSE_STRAP_DDIC_DETECTED)
		8502	intel_ddi_init(dev, PORT_C);
		8503	if (found & SFUSE_STRAP_DDID_DETECTED)
		8504	intel_ddi_init(dev, PORT_D);
		8505	} else if (HAS_PCH_SPLIT(dev)) {
		8506	int found;
3243	Serge	8507	dpd_is_edp = intel_dpd_is_edp(dev);
3031	serge	8508
3243	Serge	8509	if (has_edp_a(dev))
		8510	intel_dp_init(dev, DP_A, PORT_A);
		8511
3746	Serge	8512	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
2330	Serge	8513	/* PCH SDVOB multiplex with HDMIB */
3031	serge	8514	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	8515	if (!found)
3746	Serge	8516	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
2330	Serge	8517	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	8518	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	8519	}
2327	Serge	8520
3746	Serge	8521	if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
		8522	intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
2327	Serge	8523
3746	Serge	8524	if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
		8525	intel_hdmi_init(dev, PCH_HDMID, PORT_D);
2327	Serge	8526
2330	Serge	8527	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	8528	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	8529
3243	Serge	8530	if (I915_READ(PCH_DP_D) & DP_DETECTED)
3031	serge	8531	intel_dp_init(dev, PCH_DP_D, PORT_D);
		8532	} else if (IS_VALLEYVIEW(dev)) {
3243	Serge	8533	/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
3480	Serge	8534	if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
		8535	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
3243	Serge	8536
3746	Serge	8537	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
		8538	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
		8539	PORT_B);
3480	Serge	8540	if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
		8541	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
3031	serge	8542	}
2330	Serge	8543	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		8544	bool found = false;
2327	Serge	8545
3746	Serge	8546	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	8547	DRM_DEBUG_KMS("probing SDVOB\n");
3746	Serge	8548	found = intel_sdvo_init(dev, GEN3_SDVOB, true);
2330	Serge	8549	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		8550	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3746	Serge	8551	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
2330	Serge	8552	}
2327	Serge	8553
2330	Serge	8554	if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
		8555	DRM_DEBUG_KMS("probing DP_B\n");
3031	serge	8556	intel_dp_init(dev, DP_B, PORT_B);
2330	Serge	8557	}
		8558	}
2327	Serge	8559
2330	Serge	8560	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	8561
3746	Serge	8562	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	8563	DRM_DEBUG_KMS("probing SDVOC\n");
3746	Serge	8564	found = intel_sdvo_init(dev, GEN3_SDVOC, false);
2330	Serge	8565	}
2327	Serge	8566
3746	Serge	8567	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
2327	Serge	8568
2330	Serge	8569	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		8570	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3746	Serge	8571	intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
2330	Serge	8572	}
		8573	if (SUPPORTS_INTEGRATED_DP(dev)) {
		8574	DRM_DEBUG_KMS("probing DP_C\n");
3031	serge	8575	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	8576	}
		8577	}
2327	Serge	8578
2330	Serge	8579	if (SUPPORTS_INTEGRATED_DP(dev) &&
		8580	(I915_READ(DP_D) & DP_DETECTED)) {
		8581	DRM_DEBUG_KMS("probing DP_D\n");
3031	serge	8582	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	8583	}
		8584	} else if (IS_GEN2(dev))
		8585	intel_dvo_init(dev);
2327	Serge	8586
2330	Serge	8587	// if (SUPPORTS_TV(dev))
		8588	// intel_tv_init(dev);
2327	Serge	8589
2330	Serge	8590	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		8591	encoder->base.possible_crtcs = encoder->crtc_mask;
		8592	encoder->base.possible_clones =
3031	serge	8593	intel_encoder_clones(encoder);
2330	Serge	8594	}
2327	Serge	8595
3243	Serge	8596	intel_init_pch_refclk(dev);
		8597
		8598	drm_helper_move_panel_connectors_to_head(dev);
2330	Serge	8599	}
		8600
		8601
		8602
2335	Serge	8603	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		8604	// .destroy = intel_user_framebuffer_destroy,
		8605	// .create_handle = intel_user_framebuffer_create_handle,
		8606	};
2327	Serge	8607
2335	Serge	8608	int intel_framebuffer_init(struct drm_device *dev,
		8609	struct intel_framebuffer *intel_fb,
2342	Serge	8610	struct drm_mode_fb_cmd2 *mode_cmd,
2335	Serge	8611	struct drm_i915_gem_object *obj)
		8612	{
		8613	int ret;
2327	Serge	8614
3243	Serge	8615	if (obj->tiling_mode == I915_TILING_Y) {
		8616	DRM_DEBUG("hardware does not support tiling Y\n");
2335	Serge	8617	return -EINVAL;
3243	Serge	8618	}
2327	Serge	8619
3243	Serge	8620	if (mode_cmd->pitches[0] & 63) {
		8621	DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
		8622	mode_cmd->pitches[0]);
		8623	return -EINVAL;
		8624	}
		8625
		8626	/* FIXME <= Gen4 stride limits are bit unclear */
		8627	if (mode_cmd->pitches[0] > 32768) {
		8628	DRM_DEBUG("pitch (%d) must be at less than 32768\n",
		8629	mode_cmd->pitches[0]);
		8630	return -EINVAL;
		8631	}
		8632
		8633	if (obj->tiling_mode != I915_TILING_NONE &&
		8634	mode_cmd->pitches[0] != obj->stride) {
		8635	DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
		8636	mode_cmd->pitches[0], obj->stride);
2335	Serge	8637	return -EINVAL;
3243	Serge	8638	}
2327	Serge	8639
3243	Serge	8640	/* Reject formats not supported by any plane early. */
2342	Serge	8641	switch (mode_cmd->pixel_format) {
3243	Serge	8642	case DRM_FORMAT_C8:
2342	Serge	8643	case DRM_FORMAT_RGB565:
		8644	case DRM_FORMAT_XRGB8888:
3243	Serge	8645	case DRM_FORMAT_ARGB8888:
		8646	break;
		8647	case DRM_FORMAT_XRGB1555:
		8648	case DRM_FORMAT_ARGB1555:
		8649	if (INTEL_INFO(dev)->gen > 3) {
		8650	DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
		8651	return -EINVAL;
		8652	}
		8653	break;
3031	serge	8654	case DRM_FORMAT_XBGR8888:
3243	Serge	8655	case DRM_FORMAT_ABGR8888:
2342	Serge	8656	case DRM_FORMAT_XRGB2101010:
		8657	case DRM_FORMAT_ARGB2101010:
3243	Serge	8658	case DRM_FORMAT_XBGR2101010:
		8659	case DRM_FORMAT_ABGR2101010:
		8660	if (INTEL_INFO(dev)->gen < 4) {
		8661	DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
		8662	return -EINVAL;
		8663	}
2335	Serge	8664	break;
2342	Serge	8665	case DRM_FORMAT_YUYV:
		8666	case DRM_FORMAT_UYVY:
		8667	case DRM_FORMAT_YVYU:
		8668	case DRM_FORMAT_VYUY:
3243	Serge	8669	if (INTEL_INFO(dev)->gen < 5) {
		8670	DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
		8671	return -EINVAL;
		8672	}
2342	Serge	8673	break;
2335	Serge	8674	default:
3243	Serge	8675	DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
2335	Serge	8676	return -EINVAL;
		8677	}
2327	Serge	8678
3243	Serge	8679	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
		8680	if (mode_cmd->offsets[0] != 0)
		8681	return -EINVAL;
		8682
3480	Serge	8683	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		8684	intel_fb->obj = obj;
		8685
2335	Serge	8686	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		8687	if (ret) {
		8688	DRM_ERROR("framebuffer init failed %d\n", ret);
		8689	return ret;
		8690	}
2327	Serge	8691
2335	Serge	8692	return 0;
		8693	}
2327	Serge	8694
		8695
2360	Serge	8696	static const struct drm_mode_config_funcs intel_mode_funcs = {
		8697	.fb_create = NULL /intel_user_framebuffer_create/,
3480	Serge	8698	.output_poll_changed = intel_fb_output_poll_changed,
2360	Serge	8699	};
2327	Serge	8700
3031	serge	8701	/* Set up chip specific display functions */
		8702	static void intel_init_display(struct drm_device *dev)
		8703	{
		8704	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	8705
3480	Serge	8706	if (HAS_DDI(dev)) {
3746	Serge	8707	dev_priv->display.get_pipe_config = haswell_get_pipe_config;
3243	Serge	8708	dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
		8709	dev_priv->display.crtc_enable = haswell_crtc_enable;
		8710	dev_priv->display.crtc_disable = haswell_crtc_disable;
		8711	dev_priv->display.off = haswell_crtc_off;
		8712	dev_priv->display.update_plane = ironlake_update_plane;
		8713	} else if (HAS_PCH_SPLIT(dev)) {
3746	Serge	8714	dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
3031	serge	8715	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		8716	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		8717	dev_priv->display.crtc_disable = ironlake_crtc_disable;
		8718	dev_priv->display.off = ironlake_crtc_off;
		8719	dev_priv->display.update_plane = ironlake_update_plane;
		8720	} else {
3746	Serge	8721	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
3031	serge	8722	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		8723	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		8724	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		8725	dev_priv->display.off = i9xx_crtc_off;
		8726	dev_priv->display.update_plane = i9xx_update_plane;
		8727	}
2327	Serge	8728
3031	serge	8729	/* Returns the core display clock speed */
		8730	if (IS_VALLEYVIEW(dev))
		8731	dev_priv->display.get_display_clock_speed =
		8732	valleyview_get_display_clock_speed;
		8733	else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		8734	dev_priv->display.get_display_clock_speed =
		8735	i945_get_display_clock_speed;
		8736	else if (IS_I915G(dev))
		8737	dev_priv->display.get_display_clock_speed =
		8738	i915_get_display_clock_speed;
		8739	else if (IS_I945GM(dev) \|\| IS_845G(dev) \|\| IS_PINEVIEW_M(dev))
		8740	dev_priv->display.get_display_clock_speed =
		8741	i9xx_misc_get_display_clock_speed;
		8742	else if (IS_I915GM(dev))
		8743	dev_priv->display.get_display_clock_speed =
		8744	i915gm_get_display_clock_speed;
		8745	else if (IS_I865G(dev))
		8746	dev_priv->display.get_display_clock_speed =
		8747	i865_get_display_clock_speed;
		8748	else if (IS_I85X(dev))
		8749	dev_priv->display.get_display_clock_speed =
		8750	i855_get_display_clock_speed;
		8751	else /* 852, 830 */
		8752	dev_priv->display.get_display_clock_speed =
		8753	i830_get_display_clock_speed;
2327	Serge	8754
3031	serge	8755	if (HAS_PCH_SPLIT(dev)) {
		8756	if (IS_GEN5(dev)) {
		8757	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		8758	dev_priv->display.write_eld = ironlake_write_eld;
		8759	} else if (IS_GEN6(dev)) {
		8760	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		8761	dev_priv->display.write_eld = ironlake_write_eld;
		8762	} else if (IS_IVYBRIDGE(dev)) {
		8763	/* FIXME: detect B0+ stepping and use auto training */
		8764	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		8765	dev_priv->display.write_eld = ironlake_write_eld;
3243	Serge	8766	dev_priv->display.modeset_global_resources =
		8767	ivb_modeset_global_resources;
3031	serge	8768	} else if (IS_HASWELL(dev)) {
		8769	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		8770	dev_priv->display.write_eld = haswell_write_eld;
3480	Serge	8771	dev_priv->display.modeset_global_resources =
		8772	haswell_modeset_global_resources;
		8773	}
3031	serge	8774	} else if (IS_G4X(dev)) {
		8775	dev_priv->display.write_eld = g4x_write_eld;
		8776	}
2327	Serge	8777
3031	serge	8778	/* Default just returns -ENODEV to indicate unsupported */
		8779	// dev_priv->display.queue_flip = intel_default_queue_flip;
2327	Serge	8780
		8781
		8782
		8783
3031	serge	8784	}
		8785
		8786	/*
		8787	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		8788	* resume, or other times. This quirk makes sure that's the case for
		8789	* affected systems.
		8790	*/
		8791	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	8792	{
		8793	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	8794
3031	serge	8795	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		8796	DRM_INFO("applying pipe a force quirk\n");
		8797	}
2327	Serge	8798
3031	serge	8799	/*
		8800	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		8801	*/
		8802	static void quirk_ssc_force_disable(struct drm_device *dev)
		8803	{
		8804	struct drm_i915_private *dev_priv = dev->dev_private;
		8805	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		8806	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	8807	}
2327	Serge	8808
3031	serge	8809	/*
		8810	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		8811	* brightness value
		8812	*/
		8813	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	8814	{
		8815	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8816	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		8817	DRM_INFO("applying inverted panel brightness quirk\n");
		8818	}
2327	Serge	8819
3031	serge	8820	struct intel_quirk {
		8821	int device;
		8822	int subsystem_vendor;
		8823	int subsystem_device;
		8824	void (hook)(struct drm_device dev);
		8825	};
2327	Serge	8826
3031	serge	8827	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		8828	struct intel_dmi_quirk {
		8829	void (hook)(struct drm_device dev);
		8830	const struct dmi_system_id (*dmi_id_list)[];
		8831	};
2327	Serge	8832
3031	serge	8833	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		8834	{
		8835	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		8836	return 1;
2330	Serge	8837	}
2327	Serge	8838
3031	serge	8839	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		8840	{
		8841	.dmi_id_list = &(const struct dmi_system_id[]) {
		8842	{
		8843	.callback = intel_dmi_reverse_brightness,
		8844	.ident = "NCR Corporation",
		8845	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		8846	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		8847	},
		8848	},
		8849	{ } /* terminating entry */
		8850	},
		8851	.hook = quirk_invert_brightness,
		8852	},
		8853	};
2327	Serge	8854
3031	serge	8855	static struct intel_quirk intel_quirks[] = {
		8856	/* HP Mini needs pipe A force quirk (LP: #322104) */
		8857	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327	Serge	8858
3031	serge	8859	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		8860	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	8861
3031	serge	8862	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		8863	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	8864
3031	serge	8865	/* 830/845 need to leave pipe A & dpll A up */
		8866	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		8867	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
2327	Serge	8868
3031	serge	8869	/* Lenovo U160 cannot use SSC on LVDS */
		8870	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	8871
3031	serge	8872	/* Sony Vaio Y cannot use SSC on LVDS */
		8873	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	8874
3031	serge	8875	/* Acer Aspire 5734Z must invert backlight brightness */
		8876	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
3480	Serge	8877
		8878	/* Acer/eMachines G725 */
		8879	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
		8880
		8881	/* Acer/eMachines e725 */
		8882	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
		8883
		8884	/* Acer/Packard Bell NCL20 */
		8885	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
		8886
		8887	/* Acer Aspire 4736Z */
		8888	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
3031	serge	8889	};
2327	Serge	8890
3031	serge	8891	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	8892	{
3031	serge	8893	struct pci_dev *d = dev->pdev;
		8894	int i;
2327	Serge	8895
3031	serge	8896	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		8897	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	8898
3031	serge	8899	if (d->device == q->device &&
		8900	(d->subsystem_vendor == q->subsystem_vendor \|\|
		8901	q->subsystem_vendor == PCI_ANY_ID) &&
		8902	(d->subsystem_device == q->subsystem_device \|\|
		8903	q->subsystem_device == PCI_ANY_ID))
		8904	q->hook(dev);
		8905	}
		8906	// for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
		8907	// if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
		8908	// intel_dmi_quirks[i].hook(dev);
		8909	// }
2330	Serge	8910	}
2327	Serge	8911
3031	serge	8912	/* Disable the VGA plane that we never use */
		8913	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	8914	{
		8915	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8916	u8 sr1;
3480	Serge	8917	u32 vga_reg = i915_vgacntrl_reg(dev);
2327	Serge	8918
3031	serge	8919	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		8920	out8(SR01, VGA_SR_INDEX);
		8921	sr1 = in8(VGA_SR_DATA);
		8922	out8(sr1 \| 1<<5, VGA_SR_DATA);
		8923	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		8924	udelay(300);
2327	Serge	8925
3031	serge	8926	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		8927	POSTING_READ(vga_reg);
2330	Serge	8928	}
		8929
3031	serge	8930	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	8931	{
3480	Serge	8932	intel_init_power_well(dev);
2342	Serge	8933
3031	serge	8934	intel_prepare_ddi(dev);
2342	Serge	8935
3031	serge	8936	intel_init_clock_gating(dev);
		8937
3482	Serge	8938	mutex_lock(&dev->struct_mutex);
		8939	intel_enable_gt_powersave(dev);
		8940	mutex_unlock(&dev->struct_mutex);
2342	Serge	8941	}
		8942
3031	serge	8943	void intel_modeset_init(struct drm_device *dev)
2330	Serge	8944	{
3031	serge	8945	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	8946	int i, j, ret;
2330	Serge	8947
3031	serge	8948	drm_mode_config_init(dev);
2330	Serge	8949
3031	serge	8950	dev->mode_config.min_width = 0;
		8951	dev->mode_config.min_height = 0;
2330	Serge	8952
3031	serge	8953	dev->mode_config.preferred_depth = 24;
		8954	dev->mode_config.prefer_shadow = 1;
2330	Serge	8955
3031	serge	8956	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	8957
3031	serge	8958	intel_init_quirks(dev);
2330	Serge	8959
3031	serge	8960	intel_init_pm(dev);
2330	Serge	8961
3746	Serge	8962	if (INTEL_INFO(dev)->num_pipes == 0)
		8963	return;
		8964
3031	serge	8965	intel_init_display(dev);
2330	Serge	8966
3031	serge	8967	if (IS_GEN2(dev)) {
		8968	dev->mode_config.max_width = 2048;
		8969	dev->mode_config.max_height = 2048;
		8970	} else if (IS_GEN3(dev)) {
		8971	dev->mode_config.max_width = 4096;
		8972	dev->mode_config.max_height = 4096;
		8973	} else {
		8974	dev->mode_config.max_width = 8192;
		8975	dev->mode_config.max_height = 8192;
		8976	}
3480	Serge	8977	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
2330	Serge	8978
3031	serge	8979	DRM_DEBUG_KMS("%d display pipe%s available.\n",
3746	Serge	8980	INTEL_INFO(dev)->num_pipes,
		8981	INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
2330	Serge	8982
3746	Serge	8983	for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
3031	serge	8984	intel_crtc_init(dev, i);
3746	Serge	8985	for (j = 0; j < dev_priv->num_plane; j++) {
		8986	ret = intel_plane_init(dev, i, j);
3031	serge	8987	if (ret)
3746	Serge	8988	DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
		8989	i, j, ret);
		8990	}
2330	Serge	8991	}
		8992
3243	Serge	8993	intel_cpu_pll_init(dev);
3031	serge	8994	intel_pch_pll_init(dev);
2330	Serge	8995
3031	serge	8996	/* Just disable it once at startup */
		8997	i915_disable_vga(dev);
		8998	intel_setup_outputs(dev);
3480	Serge	8999
		9000	/* Just in case the BIOS is doing something questionable. */
		9001	intel_disable_fbc(dev);
3031	serge	9002	}
2330	Serge	9003
3031	serge	9004	static void
		9005	intel_connector_break_all_links(struct intel_connector *connector)
		9006	{
		9007	connector->base.dpms = DRM_MODE_DPMS_OFF;
		9008	connector->base.encoder = NULL;
		9009	connector->encoder->connectors_active = false;
		9010	connector->encoder->base.crtc = NULL;
2330	Serge	9011	}
		9012
3031	serge	9013	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	9014	{
3031	serge	9015	struct intel_connector *connector;
		9016	struct drm_connector *crt = NULL;
		9017	struct intel_load_detect_pipe load_detect_temp;
2330	Serge	9018
3031	serge	9019	/* We can't just switch on the pipe A, we need to set things up with a
		9020	* proper mode and output configuration. As a gross hack, enable pipe A
		9021	* by enabling the load detect pipe once. */
		9022	list_for_each_entry(connector,
		9023	&dev->mode_config.connector_list,
		9024	base.head) {
		9025	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		9026	crt = &connector->base;
		9027	break;
2330	Serge	9028	}
		9029	}
		9030
3031	serge	9031	if (!crt)
		9032	return;
2330	Serge	9033
3031	serge	9034	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		9035	intel_release_load_detect_pipe(crt, &load_detect_temp);
2327	Serge	9036
		9037
		9038	}
		9039
3031	serge	9040	static bool
		9041	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	9042	{
3746	Serge	9043	struct drm_device *dev = crtc->base.dev;
		9044	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9045	u32 reg, val;
2327	Serge	9046
3746	Serge	9047	if (INTEL_INFO(dev)->num_pipes == 1)
3031	serge	9048	return true;
2327	Serge	9049
3031	serge	9050	reg = DSPCNTR(!crtc->plane);
		9051	val = I915_READ(reg);
2327	Serge	9052
3031	serge	9053	if ((val & DISPLAY_PLANE_ENABLE) &&
		9054	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		9055	return false;
2327	Serge	9056
3031	serge	9057	return true;
2327	Serge	9058	}
		9059
3031	serge	9060	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	9061	{
3031	serge	9062	struct drm_device *dev = crtc->base.dev;
2327	Serge	9063	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9064	u32 reg;
2327	Serge	9065
3031	serge	9066	/* Clear any frame start delays used for debugging left by the BIOS */
3746	Serge	9067	reg = PIPECONF(crtc->config.cpu_transcoder);
3031	serge	9068	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	9069
3031	serge	9070	/* We need to sanitize the plane -> pipe mapping first because this will
		9071	* disable the crtc (and hence change the state) if it is wrong. Note
		9072	* that gen4+ has a fixed plane -> pipe mapping. */
		9073	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		9074	struct intel_connector *connector;
		9075	bool plane;
2327	Serge	9076
3031	serge	9077	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		9078	crtc->base.base.id);
2327	Serge	9079
3031	serge	9080	/* Pipe has the wrong plane attached and the plane is active.
		9081	* Temporarily change the plane mapping and disable everything
		9082	* ... */
		9083	plane = crtc->plane;
		9084	crtc->plane = !plane;
		9085	dev_priv->display.crtc_disable(&crtc->base);
		9086	crtc->plane = plane;
2342	Serge	9087
3031	serge	9088	/* ... and break all links. */
		9089	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9090	base.head) {
		9091	if (connector->encoder->base.crtc != &crtc->base)
		9092	continue;
2327	Serge	9093
3031	serge	9094	intel_connector_break_all_links(connector);
		9095	}
2327	Serge	9096
3031	serge	9097	WARN_ON(crtc->active);
		9098	crtc->base.enabled = false;
		9099	}
2327	Serge	9100
3031	serge	9101	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		9102	crtc->pipe == PIPE_A && !crtc->active) {
		9103	/* BIOS forgot to enable pipe A, this mostly happens after
		9104	* resume. Force-enable the pipe to fix this, the update_dpms
		9105	* call below we restore the pipe to the right state, but leave
		9106	* the required bits on. */
		9107	intel_enable_pipe_a(dev);
		9108	}
2327	Serge	9109
3031	serge	9110	/* Adjust the state of the output pipe according to whether we
		9111	* have active connectors/encoders. */
		9112	intel_crtc_update_dpms(&crtc->base);
2327	Serge	9113
3031	serge	9114	if (crtc->active != crtc->base.enabled) {
		9115	struct intel_encoder *encoder;
2327	Serge	9116
3031	serge	9117	/* This can happen either due to bugs in the get_hw_state
		9118	* functions or because the pipe is force-enabled due to the
		9119	* pipe A quirk. */
		9120	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		9121	crtc->base.base.id,
		9122	crtc->base.enabled ? "enabled" : "disabled",
		9123	crtc->active ? "enabled" : "disabled");
2327	Serge	9124
3031	serge	9125	crtc->base.enabled = crtc->active;
2327	Serge	9126
3031	serge	9127	/* Because we only establish the connector -> encoder ->
		9128	* crtc links if something is active, this means the
		9129	* crtc is now deactivated. Break the links. connector
		9130	* -> encoder links are only establish when things are
		9131	* actually up, hence no need to break them. */
		9132	WARN_ON(crtc->active);
2327	Serge	9133
3031	serge	9134	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		9135	WARN_ON(encoder->connectors_active);
		9136	encoder->base.crtc = NULL;
		9137	}
		9138	}
2327	Serge	9139	}
		9140
3031	serge	9141	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	9142	{
3031	serge	9143	struct intel_connector *connector;
		9144	struct drm_device *dev = encoder->base.dev;
2327	Serge	9145
3031	serge	9146	/* We need to check both for a crtc link (meaning that the
		9147	* encoder is active and trying to read from a pipe) and the
		9148	* pipe itself being active. */
		9149	bool has_active_crtc = encoder->base.crtc &&
		9150	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	9151
3031	serge	9152	if (encoder->connectors_active && !has_active_crtc) {
		9153	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		9154	encoder->base.base.id,
		9155	drm_get_encoder_name(&encoder->base));
2327	Serge	9156
3031	serge	9157	/* Connector is active, but has no active pipe. This is
		9158	* fallout from our resume register restoring. Disable
		9159	* the encoder manually again. */
		9160	if (encoder->base.crtc) {
		9161	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		9162	encoder->base.base.id,
		9163	drm_get_encoder_name(&encoder->base));
		9164	encoder->disable(encoder);
		9165	}
2327	Serge	9166
3031	serge	9167	/* Inconsistent output/port/pipe state happens presumably due to
		9168	* a bug in one of the get_hw_state functions. Or someplace else
		9169	* in our code, like the register restore mess on resume. Clamp
		9170	* things to off as a safer default. */
		9171	list_for_each_entry(connector,
		9172	&dev->mode_config.connector_list,
		9173	base.head) {
		9174	if (connector->encoder != encoder)
		9175	continue;
2327	Serge	9176
3031	serge	9177	intel_connector_break_all_links(connector);
		9178	}
		9179	}
		9180	/* Enabled encoders without active connectors will be fixed in
		9181	* the crtc fixup. */
2327	Serge	9182	}
		9183
3746	Serge	9184	void i915_redisable_vga(struct drm_device *dev)
		9185	{
		9186	struct drm_i915_private *dev_priv = dev->dev_private;
		9187	u32 vga_reg = i915_vgacntrl_reg(dev);
		9188
		9189	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
		9190	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
		9191	i915_disable_vga(dev);
		9192	}
		9193	}
		9194
3031	serge	9195	/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
		9196	* and i915 state tracking structures. */
3243	Serge	9197	void intel_modeset_setup_hw_state(struct drm_device *dev,
		9198	bool force_restore)
2332	Serge	9199	{
		9200	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9201	enum pipe pipe;
		9202	u32 tmp;
3746	Serge	9203	struct drm_plane *plane;
3031	serge	9204	struct intel_crtc *crtc;
		9205	struct intel_encoder *encoder;
		9206	struct intel_connector *connector;
2327	Serge	9207
3480	Serge	9208	if (HAS_DDI(dev)) {
3243	Serge	9209	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
		9210
		9211	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		9212	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		9213	case TRANS_DDI_EDP_INPUT_A_ON:
		9214	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		9215	pipe = PIPE_A;
		9216	break;
		9217	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		9218	pipe = PIPE_B;
		9219	break;
		9220	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		9221	pipe = PIPE_C;
		9222	break;
3746	Serge	9223	default:
		9224	/* A bogus value has been programmed, disable
		9225	* the transcoder */
		9226	WARN(1, "Bogus eDP source %08x\n", tmp);
		9227	intel_ddi_disable_transcoder_func(dev_priv,
		9228	TRANSCODER_EDP);
		9229	goto setup_pipes;
3243	Serge	9230	}
		9231
		9232	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3746	Serge	9233	crtc->config.cpu_transcoder = TRANSCODER_EDP;
3243	Serge	9234
		9235	DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
		9236	pipe_name(pipe));
		9237	}
		9238	}
		9239
3746	Serge	9240	setup_pipes:
		9241	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		9242	base.head) {
		9243	enum transcoder tmp = crtc->config.cpu_transcoder;
		9244	memset(&crtc->config, 0, sizeof(crtc->config));
		9245	crtc->config.cpu_transcoder = tmp;
2327	Serge	9246
3746	Serge	9247	crtc->active = dev_priv->display.get_pipe_config(crtc,
		9248	&crtc->config);
2327	Serge	9249
3031	serge	9250	crtc->base.enabled = crtc->active;
2330	Serge	9251
3031	serge	9252	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		9253	crtc->base.base.id,
		9254	crtc->active ? "enabled" : "disabled");
2339	Serge	9255	}
2332	Serge	9256
3480	Serge	9257	if (HAS_DDI(dev))
3243	Serge	9258	intel_ddi_setup_hw_pll_state(dev);
		9259
3031	serge	9260	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9261	base.head) {
		9262	pipe = 0;
2332	Serge	9263
3031	serge	9264	if (encoder->get_hw_state(encoder, &pipe)) {
		9265	encoder->base.crtc =
		9266	dev_priv->pipe_to_crtc_mapping[pipe];
		9267	} else {
		9268	encoder->base.crtc = NULL;
		9269	}
2332	Serge	9270
3031	serge	9271	encoder->connectors_active = false;
		9272	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
		9273	encoder->base.base.id,
		9274	drm_get_encoder_name(&encoder->base),
		9275	encoder->base.crtc ? "enabled" : "disabled",
		9276	pipe);
		9277	}
2332	Serge	9278
3031	serge	9279	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9280	base.head) {
		9281	if (connector->get_hw_state(connector)) {
		9282	connector->base.dpms = DRM_MODE_DPMS_ON;
		9283	connector->encoder->connectors_active = true;
		9284	connector->base.encoder = &connector->encoder->base;
		9285	} else {
		9286	connector->base.dpms = DRM_MODE_DPMS_OFF;
		9287	connector->base.encoder = NULL;
		9288	}
		9289	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		9290	connector->base.base.id,
		9291	drm_get_connector_name(&connector->base),
		9292	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	9293	}
		9294
3031	serge	9295	/* HW state is read out, now we need to sanitize this mess. */
		9296	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9297	base.head) {
		9298	intel_sanitize_encoder(encoder);
2332	Serge	9299	}
		9300
3031	serge	9301	for_each_pipe(pipe) {
		9302	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		9303	intel_sanitize_crtc(crtc);
2332	Serge	9304	}
		9305
3243	Serge	9306	if (force_restore) {
3746	Serge	9307	/*
		9308	* We need to use raw interfaces for restoring state to avoid
		9309	* checking (bogus) intermediate states.
		9310	*/
3243	Serge	9311	for_each_pipe(pipe) {
3746	Serge	9312	struct drm_crtc *crtc =
		9313	dev_priv->pipe_to_crtc_mapping[pipe];
		9314
		9315	__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
		9316	crtc->fb);
3243	Serge	9317	}
3746	Serge	9318	list_for_each_entry(plane, &dev->mode_config.plane_list, head)
		9319	intel_plane_restore(plane);
3243	Serge	9320
3746	Serge	9321	i915_redisable_vga(dev);
3243	Serge	9322	} else {
3031	serge	9323	intel_modeset_update_staged_output_state(dev);
3243	Serge	9324	}
2332	Serge	9325
3031	serge	9326	intel_modeset_check_state(dev);
3243	Serge	9327
		9328	drm_mode_config_reset(dev);
2332	Serge	9329	}
		9330
3031	serge	9331	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	9332	{
3031	serge	9333	intel_modeset_init_hw(dev);
2330	Serge	9334
3031	serge	9335	// intel_setup_overlay(dev);
2330	Serge	9336
3243	Serge	9337	intel_modeset_setup_hw_state(dev, false);
2330	Serge	9338	}
		9339
3031	serge	9340	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	9341	{
3031	serge	9342	#if 0
		9343	struct drm_i915_private *dev_priv = dev->dev_private;
		9344	struct drm_crtc *crtc;
		9345	struct intel_crtc *intel_crtc;
2327	Serge	9346
3031	serge	9347	// drm_kms_helper_poll_fini(dev);
		9348	mutex_lock(&dev->struct_mutex);
2327	Serge	9349
3031	serge	9350	// intel_unregister_dsm_handler();
2327	Serge	9351
		9352
3031	serge	9353	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		9354	/* Skip inactive CRTCs */
		9355	if (!crtc->fb)
		9356	continue;
2342	Serge	9357
3031	serge	9358	intel_crtc = to_intel_crtc(crtc);
		9359	intel_increase_pllclock(crtc);
		9360	}
2342	Serge	9361
3031	serge	9362	intel_disable_fbc(dev);
2342	Serge	9363
3031	serge	9364	intel_disable_gt_powersave(dev);
2342	Serge	9365
3031	serge	9366	ironlake_teardown_rc6(dev);
2327	Serge	9367
3031	serge	9368	if (IS_VALLEYVIEW(dev))
		9369	vlv_init_dpio(dev);
2327	Serge	9370
3031	serge	9371	mutex_unlock(&dev->struct_mutex);
2327	Serge	9372
3031	serge	9373	/* Disable the irq before mode object teardown, for the irq might
		9374	* enqueue unpin/hotplug work. */
		9375	// drm_irq_uninstall(dev);
		9376	// cancel_work_sync(&dev_priv->hotplug_work);
		9377	// cancel_work_sync(&dev_priv->rps.work);
2327	Serge	9378
3031	serge	9379	/* flush any delayed tasks or pending work */
		9380	// flush_scheduled_work();
2327	Serge	9381
3031	serge	9382	drm_mode_config_cleanup(dev);
2327	Serge	9383	#endif
		9384	}
		9385
		9386	/*
3031	serge	9387	* Return which encoder is currently attached for connector.
2327	Serge	9388	*/
3031	serge	9389	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	9390	{
3031	serge	9391	return &intel_attached_encoder(connector)->base;
		9392	}
2327	Serge	9393
3031	serge	9394	void intel_connector_attach_encoder(struct intel_connector *connector,
		9395	struct intel_encoder *encoder)
		9396	{
		9397	connector->encoder = encoder;
		9398	drm_mode_connector_attach_encoder(&connector->base,
		9399	&encoder->base);
2327	Serge	9400	}
		9401
		9402	/*
3031	serge	9403	* set vga decode state - true == enable VGA decode
2327	Serge	9404	*/
3031	serge	9405	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	9406	{
2330	Serge	9407	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9408	u16 gmch_ctrl;
2327	Serge	9409
3031	serge	9410	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
		9411	if (state)
		9412	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	9413	else
3031	serge	9414	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
		9415	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
		9416	return 0;
2330	Serge	9417	}
		9418
3031	serge	9419	#ifdef CONFIG_DEBUG_FS
		9420	#include
2327	Serge	9421
3031	serge	9422	struct intel_display_error_state {
		9423	struct intel_cursor_error_state {
		9424	u32 control;
		9425	u32 position;
		9426	u32 base;
		9427	u32 size;
		9428	} cursor[I915_MAX_PIPES];
2327	Serge	9429
3031	serge	9430	struct intel_pipe_error_state {
		9431	u32 conf;
		9432	u32 source;
2327	Serge	9433
3031	serge	9434	u32 htotal;
		9435	u32 hblank;
		9436	u32 hsync;
		9437	u32 vtotal;
		9438	u32 vblank;
		9439	u32 vsync;
		9440	} pipe[I915_MAX_PIPES];
2327	Serge	9441
3031	serge	9442	struct intel_plane_error_state {
		9443	u32 control;
		9444	u32 stride;
		9445	u32 size;
		9446	u32 pos;
		9447	u32 addr;
		9448	u32 surface;
		9449	u32 tile_offset;
		9450	} plane[I915_MAX_PIPES];
		9451	};
2327	Serge	9452
3031	serge	9453	struct intel_display_error_state *
		9454	intel_display_capture_error_state(struct drm_device *dev)
		9455	{
		9456	drm_i915_private_t *dev_priv = dev->dev_private;
		9457	struct intel_display_error_state *error;
3243	Serge	9458	enum transcoder cpu_transcoder;
3031	serge	9459	int i;
2327	Serge	9460
3031	serge	9461	error = kmalloc(sizeof(*error), GFP_ATOMIC);
		9462	if (error == NULL)
		9463	return NULL;
2327	Serge	9464
3031	serge	9465	for_each_pipe(i) {
3243	Serge	9466	cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
		9467
3746	Serge	9468	if (INTEL_INFO(dev)->gen <= 6 \|\| IS_VALLEYVIEW(dev)) {
3031	serge	9469	error->cursor[i].control = I915_READ(CURCNTR(i));
		9470	error->cursor[i].position = I915_READ(CURPOS(i));
		9471	error->cursor[i].base = I915_READ(CURBASE(i));
3746	Serge	9472	} else {
		9473	error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
		9474	error->cursor[i].position = I915_READ(CURPOS_IVB(i));
		9475	error->cursor[i].base = I915_READ(CURBASE_IVB(i));
		9476	}
2327	Serge	9477
3031	serge	9478	error->plane[i].control = I915_READ(DSPCNTR(i));
		9479	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
3746	Serge	9480	if (INTEL_INFO(dev)->gen <= 3) {
3031	serge	9481	error->plane[i].size = I915_READ(DSPSIZE(i));
		9482	error->plane[i].pos = I915_READ(DSPPOS(i));
3746	Serge	9483	}
		9484	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3031	serge	9485	error->plane[i].addr = I915_READ(DSPADDR(i));
		9486	if (INTEL_INFO(dev)->gen >= 4) {
		9487	error->plane[i].surface = I915_READ(DSPSURF(i));
		9488	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		9489	}
2327	Serge	9490
3243	Serge	9491	error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
3031	serge	9492	error->pipe[i].source = I915_READ(PIPESRC(i));
3243	Serge	9493	error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		9494	error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		9495	error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		9496	error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		9497	error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		9498	error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
3031	serge	9499	}
2327	Serge	9500
3031	serge	9501	return error;
2330	Serge	9502	}
2327	Serge	9503
3031	serge	9504	void
		9505	intel_display_print_error_state(struct seq_file *m,
		9506	struct drm_device *dev,
		9507	struct intel_display_error_state *error)
2332	Serge	9508	{
3031	serge	9509	int i;
2330	Serge	9510
3746	Serge	9511	seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
3031	serge	9512	for_each_pipe(i) {
		9513	seq_printf(m, "Pipe [%d]:\n", i);
		9514	seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
		9515	seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
		9516	seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
		9517	seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
		9518	seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
		9519	seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
		9520	seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
		9521	seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
2332	Serge	9522
3031	serge	9523	seq_printf(m, "Plane [%d]:\n", i);
		9524	seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
		9525	seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
3746	Serge	9526	if (INTEL_INFO(dev)->gen <= 3) {
3031	serge	9527	seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
		9528	seq_printf(m, " POS: %08x\n", error->plane[i].pos);
3746	Serge	9529	}
		9530	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3031	serge	9531	seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
		9532	if (INTEL_INFO(dev)->gen >= 4) {
		9533	seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
		9534	seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
		9535	}
2332	Serge	9536
3031	serge	9537	seq_printf(m, "Cursor [%d]:\n", i);
		9538	seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		9539	seq_printf(m, " POS: %08x\n", error->cursor[i].position);
		9540	seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
		9541	}
2327	Serge	9542	}
3031	serge	9543	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c @ 5097 – Rev 3746