WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
		27	//#include
		28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
2327	Serge	33	//#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
3031	serge	40	#include
		41	#include
		42	//#include
2327	Serge	43
		44	phys_addr_t get_bus_addr(void);
		45
		46	static inline __attribute__((const))
		47	bool is_power_of_2(unsigned long n)
		48	{
		49	return (n != 0 && ((n & (n - 1)) == 0));
		50	}
		51
2330	Serge	52	#define MAX_ERRNO 4095
		53
		54	#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
		55
		56	static inline long IS_ERR(const void *ptr)
		57	{
		58	return IS_ERR_VALUE((unsigned long)ptr);
		59	}
		60
		61	static inline void *ERR_PTR(long error)
		62	{
		63	return (void *) error;
		64	}
		65
		66
2327	Serge	67	#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
		68
2342	Serge	69	bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
2327	Serge	70	static void intel_increase_pllclock(struct drm_crtc *crtc);
3031	serge	71	//static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	72
		73	typedef struct {
		74	/* given values */
		75	int n;
		76	int m1, m2;
		77	int p1, p2;
		78	/* derived values */
		79	int dot;
		80	int vco;
		81	int m;
		82	int p;
		83	} intel_clock_t;
		84
		85	typedef struct {
		86	int min, max;
		87	} intel_range_t;
		88
		89	typedef struct {
		90	int dot_limit;
		91	int p2_slow, p2_fast;
		92	} intel_p2_t;
		93
		94	#define INTEL_P2_NUM 2
		95	typedef struct intel_limit intel_limit_t;
		96	struct intel_limit {
		97	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		98	intel_p2_t p2;
		99	bool (* find_pll)(const intel_limit_t , struct drm_crtc ,
3031	serge	100	int, int, intel_clock_t , intel_clock_t );
2327	Serge	101	};
		102
		103	/* FDI */
		104	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		105
		106	static bool
		107	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	108	int target, int refclk, intel_clock_t *match_clock,
		109	intel_clock_t *best_clock);
2327	Serge	110	static bool
		111	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	112	int target, int refclk, intel_clock_t *match_clock,
		113	intel_clock_t *best_clock);
2327	Serge	114
		115	static bool
		116	intel_find_pll_g4x_dp(const intel_limit_t , struct drm_crtc crtc,
3031	serge	117	int target, int refclk, intel_clock_t *match_clock,
		118	intel_clock_t *best_clock);
2327	Serge	119	static bool
		120	intel_find_pll_ironlake_dp(const intel_limit_t , struct drm_crtc crtc,
3031	serge	121	int target, int refclk, intel_clock_t *match_clock,
		122	intel_clock_t *best_clock);
2327	Serge	123
3031	serge	124	static bool
		125	intel_vlv_find_best_pll(const intel_limit_t limit, struct drm_crtc crtc,
		126	int target, int refclk, intel_clock_t *match_clock,
		127	intel_clock_t *best_clock);
		128
2327	Serge	129	static inline u32 /* units of 100MHz */
		130	intel_fdi_link_freq(struct drm_device *dev)
		131	{
		132	if (IS_GEN5(dev)) {
		133	struct drm_i915_private *dev_priv = dev->dev_private;
		134	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		135	} else
		136	return 27;
		137	}
		138
		139	static const intel_limit_t intel_limits_i8xx_dvo = {
		140	.dot = { .min = 25000, .max = 350000 },
		141	.vco = { .min = 930000, .max = 1400000 },
		142	.n = { .min = 3, .max = 16 },
		143	.m = { .min = 96, .max = 140 },
		144	.m1 = { .min = 18, .max = 26 },
		145	.m2 = { .min = 6, .max = 16 },
		146	.p = { .min = 4, .max = 128 },
		147	.p1 = { .min = 2, .max = 33 },
		148	.p2 = { .dot_limit = 165000,
		149	.p2_slow = 4, .p2_fast = 2 },
		150	.find_pll = intel_find_best_PLL,
		151	};
		152
		153	static const intel_limit_t intel_limits_i8xx_lvds = {
		154	.dot = { .min = 25000, .max = 350000 },
		155	.vco = { .min = 930000, .max = 1400000 },
		156	.n = { .min = 3, .max = 16 },
		157	.m = { .min = 96, .max = 140 },
		158	.m1 = { .min = 18, .max = 26 },
		159	.m2 = { .min = 6, .max = 16 },
		160	.p = { .min = 4, .max = 128 },
		161	.p1 = { .min = 1, .max = 6 },
		162	.p2 = { .dot_limit = 165000,
		163	.p2_slow = 14, .p2_fast = 7 },
		164	.find_pll = intel_find_best_PLL,
		165	};
		166
		167	static const intel_limit_t intel_limits_i9xx_sdvo = {
		168	.dot = { .min = 20000, .max = 400000 },
		169	.vco = { .min = 1400000, .max = 2800000 },
		170	.n = { .min = 1, .max = 6 },
		171	.m = { .min = 70, .max = 120 },
		172	.m1 = { .min = 10, .max = 22 },
		173	.m2 = { .min = 5, .max = 9 },
		174	.p = { .min = 5, .max = 80 },
		175	.p1 = { .min = 1, .max = 8 },
		176	.p2 = { .dot_limit = 200000,
		177	.p2_slow = 10, .p2_fast = 5 },
		178	.find_pll = intel_find_best_PLL,
		179	};
		180
		181	static const intel_limit_t intel_limits_i9xx_lvds = {
		182	.dot = { .min = 20000, .max = 400000 },
		183	.vco = { .min = 1400000, .max = 2800000 },
		184	.n = { .min = 1, .max = 6 },
		185	.m = { .min = 70, .max = 120 },
		186	.m1 = { .min = 10, .max = 22 },
		187	.m2 = { .min = 5, .max = 9 },
		188	.p = { .min = 7, .max = 98 },
		189	.p1 = { .min = 1, .max = 8 },
		190	.p2 = { .dot_limit = 112000,
		191	.p2_slow = 14, .p2_fast = 7 },
		192	.find_pll = intel_find_best_PLL,
		193	};
		194
		195
		196	static const intel_limit_t intel_limits_g4x_sdvo = {
		197	.dot = { .min = 25000, .max = 270000 },
		198	.vco = { .min = 1750000, .max = 3500000},
		199	.n = { .min = 1, .max = 4 },
		200	.m = { .min = 104, .max = 138 },
		201	.m1 = { .min = 17, .max = 23 },
		202	.m2 = { .min = 5, .max = 11 },
		203	.p = { .min = 10, .max = 30 },
		204	.p1 = { .min = 1, .max = 3},
		205	.p2 = { .dot_limit = 270000,
		206	.p2_slow = 10,
		207	.p2_fast = 10
		208	},
		209	.find_pll = intel_g4x_find_best_PLL,
		210	};
		211
		212	static const intel_limit_t intel_limits_g4x_hdmi = {
		213	.dot = { .min = 22000, .max = 400000 },
		214	.vco = { .min = 1750000, .max = 3500000},
		215	.n = { .min = 1, .max = 4 },
		216	.m = { .min = 104, .max = 138 },
		217	.m1 = { .min = 16, .max = 23 },
		218	.m2 = { .min = 5, .max = 11 },
		219	.p = { .min = 5, .max = 80 },
		220	.p1 = { .min = 1, .max = 8},
		221	.p2 = { .dot_limit = 165000,
		222	.p2_slow = 10, .p2_fast = 5 },
		223	.find_pll = intel_g4x_find_best_PLL,
		224	};
		225
		226	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		227	.dot = { .min = 20000, .max = 115000 },
		228	.vco = { .min = 1750000, .max = 3500000 },
		229	.n = { .min = 1, .max = 3 },
		230	.m = { .min = 104, .max = 138 },
		231	.m1 = { .min = 17, .max = 23 },
		232	.m2 = { .min = 5, .max = 11 },
		233	.p = { .min = 28, .max = 112 },
		234	.p1 = { .min = 2, .max = 8 },
		235	.p2 = { .dot_limit = 0,
		236	.p2_slow = 14, .p2_fast = 14
		237	},
		238	.find_pll = intel_g4x_find_best_PLL,
		239	};
		240
		241	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		242	.dot = { .min = 80000, .max = 224000 },
		243	.vco = { .min = 1750000, .max = 3500000 },
		244	.n = { .min = 1, .max = 3 },
		245	.m = { .min = 104, .max = 138 },
		246	.m1 = { .min = 17, .max = 23 },
		247	.m2 = { .min = 5, .max = 11 },
		248	.p = { .min = 14, .max = 42 },
		249	.p1 = { .min = 2, .max = 6 },
		250	.p2 = { .dot_limit = 0,
		251	.p2_slow = 7, .p2_fast = 7
		252	},
		253	.find_pll = intel_g4x_find_best_PLL,
		254	};
		255
		256	static const intel_limit_t intel_limits_g4x_display_port = {
		257	.dot = { .min = 161670, .max = 227000 },
		258	.vco = { .min = 1750000, .max = 3500000},
		259	.n = { .min = 1, .max = 2 },
		260	.m = { .min = 97, .max = 108 },
		261	.m1 = { .min = 0x10, .max = 0x12 },
		262	.m2 = { .min = 0x05, .max = 0x06 },
		263	.p = { .min = 10, .max = 20 },
		264	.p1 = { .min = 1, .max = 2},
		265	.p2 = { .dot_limit = 0,
		266	.p2_slow = 10, .p2_fast = 10 },
		267	.find_pll = intel_find_pll_g4x_dp,
		268	};
		269
		270	static const intel_limit_t intel_limits_pineview_sdvo = {
		271	.dot = { .min = 20000, .max = 400000},
		272	.vco = { .min = 1700000, .max = 3500000 },
		273	/* Pineview's Ncounter is a ring counter */
		274	.n = { .min = 3, .max = 6 },
		275	.m = { .min = 2, .max = 256 },
		276	/* Pineview only has one combined m divider, which we treat as m2. */
		277	.m1 = { .min = 0, .max = 0 },
		278	.m2 = { .min = 0, .max = 254 },
		279	.p = { .min = 5, .max = 80 },
		280	.p1 = { .min = 1, .max = 8 },
		281	.p2 = { .dot_limit = 200000,
		282	.p2_slow = 10, .p2_fast = 5 },
		283	.find_pll = intel_find_best_PLL,
		284	};
		285
		286	static const intel_limit_t intel_limits_pineview_lvds = {
		287	.dot = { .min = 20000, .max = 400000 },
		288	.vco = { .min = 1700000, .max = 3500000 },
		289	.n = { .min = 3, .max = 6 },
		290	.m = { .min = 2, .max = 256 },
		291	.m1 = { .min = 0, .max = 0 },
		292	.m2 = { .min = 0, .max = 254 },
		293	.p = { .min = 7, .max = 112 },
		294	.p1 = { .min = 1, .max = 8 },
		295	.p2 = { .dot_limit = 112000,
		296	.p2_slow = 14, .p2_fast = 14 },
		297	.find_pll = intel_find_best_PLL,
		298	};
		299
		300	/* Ironlake / Sandybridge
		301	*
		302	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		303	* the range value for them is (actual_value - 2).
		304	*/
		305	static const intel_limit_t intel_limits_ironlake_dac = {
		306	.dot = { .min = 25000, .max = 350000 },
		307	.vco = { .min = 1760000, .max = 3510000 },
		308	.n = { .min = 1, .max = 5 },
		309	.m = { .min = 79, .max = 127 },
		310	.m1 = { .min = 12, .max = 22 },
		311	.m2 = { .min = 5, .max = 9 },
		312	.p = { .min = 5, .max = 80 },
		313	.p1 = { .min = 1, .max = 8 },
		314	.p2 = { .dot_limit = 225000,
		315	.p2_slow = 10, .p2_fast = 5 },
		316	.find_pll = intel_g4x_find_best_PLL,
		317	};
		318
		319	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		320	.dot = { .min = 25000, .max = 350000 },
		321	.vco = { .min = 1760000, .max = 3510000 },
		322	.n = { .min = 1, .max = 3 },
		323	.m = { .min = 79, .max = 118 },
		324	.m1 = { .min = 12, .max = 22 },
		325	.m2 = { .min = 5, .max = 9 },
		326	.p = { .min = 28, .max = 112 },
		327	.p1 = { .min = 2, .max = 8 },
		328	.p2 = { .dot_limit = 225000,
		329	.p2_slow = 14, .p2_fast = 14 },
		330	.find_pll = intel_g4x_find_best_PLL,
		331	};
		332
		333	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		334	.dot = { .min = 25000, .max = 350000 },
		335	.vco = { .min = 1760000, .max = 3510000 },
		336	.n = { .min = 1, .max = 3 },
		337	.m = { .min = 79, .max = 127 },
		338	.m1 = { .min = 12, .max = 22 },
		339	.m2 = { .min = 5, .max = 9 },
		340	.p = { .min = 14, .max = 56 },
		341	.p1 = { .min = 2, .max = 8 },
		342	.p2 = { .dot_limit = 225000,
		343	.p2_slow = 7, .p2_fast = 7 },
		344	.find_pll = intel_g4x_find_best_PLL,
		345	};
		346
		347	/* LVDS 100mhz refclk limits. */
		348	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		349	.dot = { .min = 25000, .max = 350000 },
		350	.vco = { .min = 1760000, .max = 3510000 },
		351	.n = { .min = 1, .max = 2 },
		352	.m = { .min = 79, .max = 126 },
		353	.m1 = { .min = 12, .max = 22 },
		354	.m2 = { .min = 5, .max = 9 },
		355	.p = { .min = 28, .max = 112 },
2342	Serge	356	.p1 = { .min = 2, .max = 8 },
2327	Serge	357	.p2 = { .dot_limit = 225000,
		358	.p2_slow = 14, .p2_fast = 14 },
		359	.find_pll = intel_g4x_find_best_PLL,
		360	};
		361
		362	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		363	.dot = { .min = 25000, .max = 350000 },
		364	.vco = { .min = 1760000, .max = 3510000 },
		365	.n = { .min = 1, .max = 3 },
		366	.m = { .min = 79, .max = 126 },
		367	.m1 = { .min = 12, .max = 22 },
		368	.m2 = { .min = 5, .max = 9 },
		369	.p = { .min = 14, .max = 42 },
2342	Serge	370	.p1 = { .min = 2, .max = 6 },
2327	Serge	371	.p2 = { .dot_limit = 225000,
		372	.p2_slow = 7, .p2_fast = 7 },
		373	.find_pll = intel_g4x_find_best_PLL,
		374	};
		375
		376	static const intel_limit_t intel_limits_ironlake_display_port = {
		377	.dot = { .min = 25000, .max = 350000 },
		378	.vco = { .min = 1760000, .max = 3510000},
		379	.n = { .min = 1, .max = 2 },
		380	.m = { .min = 81, .max = 90 },
		381	.m1 = { .min = 12, .max = 22 },
		382	.m2 = { .min = 5, .max = 9 },
		383	.p = { .min = 10, .max = 20 },
		384	.p1 = { .min = 1, .max = 2},
		385	.p2 = { .dot_limit = 0,
		386	.p2_slow = 10, .p2_fast = 10 },
		387	.find_pll = intel_find_pll_ironlake_dp,
		388	};
		389
3031	serge	390	static const intel_limit_t intel_limits_vlv_dac = {
		391	.dot = { .min = 25000, .max = 270000 },
		392	.vco = { .min = 4000000, .max = 6000000 },
		393	.n = { .min = 1, .max = 7 },
		394	.m = { .min = 22, .max = 450 }, /* guess */
		395	.m1 = { .min = 2, .max = 3 },
		396	.m2 = { .min = 11, .max = 156 },
		397	.p = { .min = 10, .max = 30 },
		398	.p1 = { .min = 2, .max = 3 },
		399	.p2 = { .dot_limit = 270000,
		400	.p2_slow = 2, .p2_fast = 20 },
		401	.find_pll = intel_vlv_find_best_pll,
		402	};
		403
		404	static const intel_limit_t intel_limits_vlv_hdmi = {
		405	.dot = { .min = 20000, .max = 165000 },
		406	.vco = { .min = 5994000, .max = 4000000 },
		407	.n = { .min = 1, .max = 7 },
		408	.m = { .min = 60, .max = 300 }, /* guess */
		409	.m1 = { .min = 2, .max = 3 },
		410	.m2 = { .min = 11, .max = 156 },
		411	.p = { .min = 10, .max = 30 },
		412	.p1 = { .min = 2, .max = 3 },
		413	.p2 = { .dot_limit = 270000,
		414	.p2_slow = 2, .p2_fast = 20 },
		415	.find_pll = intel_vlv_find_best_pll,
		416	};
		417
		418	static const intel_limit_t intel_limits_vlv_dp = {
		419	.dot = { .min = 162000, .max = 270000 },
		420	.vco = { .min = 5994000, .max = 4000000 },
		421	.n = { .min = 1, .max = 7 },
		422	.m = { .min = 60, .max = 300 }, /* guess */
		423	.m1 = { .min = 2, .max = 3 },
		424	.m2 = { .min = 11, .max = 156 },
		425	.p = { .min = 10, .max = 30 },
		426	.p1 = { .min = 2, .max = 3 },
		427	.p2 = { .dot_limit = 270000,
		428	.p2_slow = 2, .p2_fast = 20 },
		429	.find_pll = intel_vlv_find_best_pll,
		430	};
		431
		432	u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
		433	{
		434	unsigned long flags;
		435	u32 val = 0;
		436
		437	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
		438	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		439	DRM_ERROR("DPIO idle wait timed out\n");
		440	goto out_unlock;
		441	}
		442
		443	I915_WRITE(DPIO_REG, reg);
		444	I915_WRITE(DPIO_PKT, DPIO_RID \| DPIO_OP_READ \| DPIO_PORTID \|
		445	DPIO_BYTE);
		446	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		447	DRM_ERROR("DPIO read wait timed out\n");
		448	goto out_unlock;
		449	}
		450	val = I915_READ(DPIO_DATA);
		451
		452	out_unlock:
		453	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
		454	return val;
		455	}
		456
		457	static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
		458	u32 val)
		459	{
		460	unsigned long flags;
		461
		462	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
		463	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		464	DRM_ERROR("DPIO idle wait timed out\n");
		465	goto out_unlock;
		466	}
		467
		468	I915_WRITE(DPIO_DATA, val);
		469	I915_WRITE(DPIO_REG, reg);
		470	I915_WRITE(DPIO_PKT, DPIO_RID \| DPIO_OP_WRITE \| DPIO_PORTID \|
		471	DPIO_BYTE);
		472	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
		473	DRM_ERROR("DPIO write wait timed out\n");
		474
		475	out_unlock:
		476	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
		477	}
		478
		479	static void vlv_init_dpio(struct drm_device *dev)
		480	{
		481	struct drm_i915_private *dev_priv = dev->dev_private;
		482
		483	/* Reset the DPIO config */
		484	I915_WRITE(DPIO_CTL, 0);
		485	POSTING_READ(DPIO_CTL);
		486	I915_WRITE(DPIO_CTL, 1);
		487	POSTING_READ(DPIO_CTL);
		488	}
		489
		490	static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
		491	{
		492	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
		493	return 1;
		494	}
		495
		496	static const struct dmi_system_id intel_dual_link_lvds[] = {
		497	{
		498	.callback = intel_dual_link_lvds_callback,
		499	.ident = "Apple MacBook Pro (Core i5/i7 Series)",
		500	.matches = {
		501	DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
		502	DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
		503	},
		504	},
		505	{ } /* terminating entry */
		506	};
		507
		508	static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
		509	unsigned int reg)
		510	{
		511	unsigned int val;
		512
		513	/* use the module option value if specified */
		514	if (i915_lvds_channel_mode > 0)
		515	return i915_lvds_channel_mode == 2;
		516
		517	// if (dmi_check_system(intel_dual_link_lvds))
		518	// return true;
		519
		520	if (dev_priv->lvds_val)
		521	val = dev_priv->lvds_val;
		522	else {
		523	/* BIOS should set the proper LVDS register value at boot, but
		524	* in reality, it doesn't set the value when the lid is closed;
		525	* we need to check "the value to be set" in VBT when LVDS
		526	* register is uninitialized.
		527	*/
		528	val = I915_READ(reg);
		529	if (!(val & ~(LVDS_PIPE_MASK \| LVDS_DETECTED)))
		530	val = dev_priv->bios_lvds_val;
		531	dev_priv->lvds_val = val;
		532	}
		533	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
		534	}
		535
2327	Serge	536	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		537	int refclk)
		538	{
		539	struct drm_device *dev = crtc->dev;
		540	struct drm_i915_private *dev_priv = dev->dev_private;
		541	const intel_limit_t *limit;
		542
		543	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3031	serge	544	if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
2327	Serge	545	/* LVDS dual channel */
		546	if (refclk == 100000)
		547	limit = &intel_limits_ironlake_dual_lvds_100m;
		548	else
		549	limit = &intel_limits_ironlake_dual_lvds;
		550	} else {
		551	if (refclk == 100000)
		552	limit = &intel_limits_ironlake_single_lvds_100m;
		553	else
		554	limit = &intel_limits_ironlake_single_lvds;
		555	}
		556	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		557	HAS_eDP)
		558	limit = &intel_limits_ironlake_display_port;
		559	else
		560	limit = &intel_limits_ironlake_dac;
		561
		562	return limit;
		563	}
		564
		565	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		566	{
		567	struct drm_device *dev = crtc->dev;
		568	struct drm_i915_private *dev_priv = dev->dev_private;
		569	const intel_limit_t *limit;
		570
		571	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3031	serge	572	if (is_dual_link_lvds(dev_priv, LVDS))
2327	Serge	573	/* LVDS with dual channel */
		574	limit = &intel_limits_g4x_dual_channel_lvds;
		575	else
		576	/* LVDS with dual channel */
		577	limit = &intel_limits_g4x_single_channel_lvds;
		578	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		579	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		580	limit = &intel_limits_g4x_hdmi;
		581	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		582	limit = &intel_limits_g4x_sdvo;
2342	Serge	583	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2327	Serge	584	limit = &intel_limits_g4x_display_port;
		585	} else /* The option is for other outputs */
		586	limit = &intel_limits_i9xx_sdvo;
		587
		588	return limit;
		589	}
		590
		591	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		592	{
		593	struct drm_device *dev = crtc->dev;
		594	const intel_limit_t *limit;
		595
		596	if (HAS_PCH_SPLIT(dev))
		597	limit = intel_ironlake_limit(crtc, refclk);
		598	else if (IS_G4X(dev)) {
		599	limit = intel_g4x_limit(crtc);
		600	} else if (IS_PINEVIEW(dev)) {
		601	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		602	limit = &intel_limits_pineview_lvds;
		603	else
		604	limit = &intel_limits_pineview_sdvo;
3031	serge	605	} else if (IS_VALLEYVIEW(dev)) {
		606	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
		607	limit = &intel_limits_vlv_dac;
		608	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
		609	limit = &intel_limits_vlv_hdmi;
		610	else
		611	limit = &intel_limits_vlv_dp;
2327	Serge	612	} else if (!IS_GEN2(dev)) {
		613	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		614	limit = &intel_limits_i9xx_lvds;
		615	else
		616	limit = &intel_limits_i9xx_sdvo;
		617	} else {
		618	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		619	limit = &intel_limits_i8xx_lvds;
		620	else
		621	limit = &intel_limits_i8xx_dvo;
		622	}
		623	return limit;
		624	}
		625
		626	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		627	static void pineview_clock(int refclk, intel_clock_t *clock)
		628	{
		629	clock->m = clock->m2 + 2;
		630	clock->p = clock->p1 * clock->p2;
		631	clock->vco = refclk * clock->m / clock->n;
		632	clock->dot = clock->vco / clock->p;
		633	}
		634
		635	static void intel_clock(struct drm_device dev, int refclk, intel_clock_t clock)
		636	{
		637	if (IS_PINEVIEW(dev)) {
		638	pineview_clock(refclk, clock);
		639	return;
		640	}
		641	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
		642	clock->p = clock->p1 * clock->p2;
		643	clock->vco = refclk * clock->m / (clock->n + 2);
		644	clock->dot = clock->vco / clock->p;
		645	}
		646
		647	/**
		648	* Returns whether any output on the specified pipe is of the specified type
		649	*/
		650	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		651	{
		652	struct drm_device *dev = crtc->dev;
		653	struct intel_encoder *encoder;
		654
3031	serge	655	for_each_encoder_on_crtc(dev, crtc, encoder)
		656	if (encoder->type == type)
2327	Serge	657	return true;
		658
		659	return false;
		660	}
		661
		662	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		663	/**
		664	* Returns whether the given set of divisors are valid for a given refclk with
		665	* the given connectors.
		666	*/
		667
		668	static bool intel_PLL_is_valid(struct drm_device *dev,
		669	const intel_limit_t *limit,
		670	const intel_clock_t *clock)
		671	{
		672	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	673	INTELPllInvalid("p1 out of range\n");
2327	Serge	674	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
2342	Serge	675	INTELPllInvalid("p out of range\n");
2327	Serge	676	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	677	INTELPllInvalid("m2 out of range\n");
2327	Serge	678	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	679	INTELPllInvalid("m1 out of range\n");
2327	Serge	680	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
2342	Serge	681	INTELPllInvalid("m1 <= m2\n");
2327	Serge	682	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
2342	Serge	683	INTELPllInvalid("m out of range\n");
2327	Serge	684	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
2342	Serge	685	INTELPllInvalid("n out of range\n");
2327	Serge	686	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	687	INTELPllInvalid("vco out of range\n");
2327	Serge	688	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		689	* connector, etc., rather than just a single range.
		690	*/
		691	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	692	INTELPllInvalid("dot out of range\n");
2327	Serge	693
		694	return true;
		695	}
		696
		697	static bool
		698	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	699	int target, int refclk, intel_clock_t *match_clock,
		700	intel_clock_t *best_clock)
2327	Serge	701
		702	{
		703	struct drm_device *dev = crtc->dev;
		704	struct drm_i915_private *dev_priv = dev->dev_private;
		705	intel_clock_t clock;
		706	int err = target;
		707
		708	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		709	(I915_READ(LVDS)) != 0) {
		710	/*
		711	* For LVDS, if the panel is on, just rely on its current
		712	* settings for dual-channel. We haven't figured out how to
		713	* reliably set up different single/dual channel state, if we
		714	* even can.
		715	*/
3031	serge	716	if (is_dual_link_lvds(dev_priv, LVDS))
2327	Serge	717	clock.p2 = limit->p2.p2_fast;
		718	else
		719	clock.p2 = limit->p2.p2_slow;
		720	} else {
		721	if (target < limit->p2.dot_limit)
		722	clock.p2 = limit->p2.p2_slow;
		723	else
		724	clock.p2 = limit->p2.p2_fast;
		725	}
		726
2342	Serge	727	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	728
		729	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		730	clock.m1++) {
		731	for (clock.m2 = limit->m2.min;
		732	clock.m2 <= limit->m2.max; clock.m2++) {
		733	/* m1 is always 0 in Pineview */
		734	if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
		735	break;
		736	for (clock.n = limit->n.min;
		737	clock.n <= limit->n.max; clock.n++) {
		738	for (clock.p1 = limit->p1.min;
		739	clock.p1 <= limit->p1.max; clock.p1++) {
		740	int this_err;
		741
		742	intel_clock(dev, refclk, &clock);
		743	if (!intel_PLL_is_valid(dev, limit,
		744	&clock))
		745	continue;
3031	serge	746	if (match_clock &&
		747	clock.p != match_clock->p)
		748	continue;
2327	Serge	749
		750	this_err = abs(clock.dot - target);
		751	if (this_err < err) {
		752	*best_clock = clock;
		753	err = this_err;
		754	}
		755	}
		756	}
		757	}
		758	}
		759
		760	return (err != target);
		761	}
		762
		763	static bool
		764	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	765	int target, int refclk, intel_clock_t *match_clock,
		766	intel_clock_t *best_clock)
2327	Serge	767	{
		768	struct drm_device *dev = crtc->dev;
		769	struct drm_i915_private *dev_priv = dev->dev_private;
		770	intel_clock_t clock;
		771	int max_n;
		772	bool found;
		773	/* approximately equals target * 0.00585 */
		774	int err_most = (target >> 8) + (target >> 9);
		775	found = false;
		776
		777	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		778	int lvds_reg;
		779
		780	if (HAS_PCH_SPLIT(dev))
		781	lvds_reg = PCH_LVDS;
		782	else
		783	lvds_reg = LVDS;
		784	if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
		785	LVDS_CLKB_POWER_UP)
		786	clock.p2 = limit->p2.p2_fast;
		787	else
		788	clock.p2 = limit->p2.p2_slow;
		789	} else {
		790	if (target < limit->p2.dot_limit)
		791	clock.p2 = limit->p2.p2_slow;
		792	else
		793	clock.p2 = limit->p2.p2_fast;
		794	}
		795
		796	memset(best_clock, 0, sizeof(*best_clock));
		797	max_n = limit->n.max;
		798	/* based on hardware requirement, prefer smaller n to precision */
		799	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		800	/* based on hardware requirement, prefere larger m1,m2 */
		801	for (clock.m1 = limit->m1.max;
		802	clock.m1 >= limit->m1.min; clock.m1--) {
		803	for (clock.m2 = limit->m2.max;
		804	clock.m2 >= limit->m2.min; clock.m2--) {
		805	for (clock.p1 = limit->p1.max;
		806	clock.p1 >= limit->p1.min; clock.p1--) {
		807	int this_err;
		808
		809	intel_clock(dev, refclk, &clock);
		810	if (!intel_PLL_is_valid(dev, limit,
		811	&clock))
		812	continue;
3031	serge	813	if (match_clock &&
		814	clock.p != match_clock->p)
		815	continue;
2327	Serge	816
		817	this_err = abs(clock.dot - target);
		818	if (this_err < err_most) {
		819	*best_clock = clock;
		820	err_most = this_err;
		821	max_n = clock.n;
		822	found = true;
		823	}
		824	}
		825	}
		826	}
		827	}
		828	return found;
		829	}
		830
		831	static bool
		832	intel_find_pll_ironlake_dp(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	833	int target, int refclk, intel_clock_t *match_clock,
		834	intel_clock_t *best_clock)
2327	Serge	835	{
		836	struct drm_device *dev = crtc->dev;
		837	intel_clock_t clock;
		838
		839	if (target < 200000) {
		840	clock.n = 1;
		841	clock.p1 = 2;
		842	clock.p2 = 10;
		843	clock.m1 = 12;
		844	clock.m2 = 9;
		845	} else {
		846	clock.n = 2;
		847	clock.p1 = 1;
		848	clock.p2 = 10;
		849	clock.m1 = 14;
		850	clock.m2 = 8;
		851	}
		852	intel_clock(dev, refclk, &clock);
		853	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		854	return true;
		855	}
		856
		857	/* DisplayPort has only two frequencies, 162MHz and 270MHz */
		858	static bool
		859	intel_find_pll_g4x_dp(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	860	int target, int refclk, intel_clock_t *match_clock,
		861	intel_clock_t *best_clock)
2327	Serge	862	{
		863	intel_clock_t clock;
		864	if (target < 200000) {
		865	clock.p1 = 2;
		866	clock.p2 = 10;
		867	clock.n = 2;
		868	clock.m1 = 23;
		869	clock.m2 = 8;
		870	} else {
		871	clock.p1 = 1;
		872	clock.p2 = 10;
		873	clock.n = 1;
		874	clock.m1 = 14;
		875	clock.m2 = 2;
		876	}
		877	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
		878	clock.p = (clock.p1 * clock.p2);
		879	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
		880	clock.vco = 0;
		881	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		882	return true;
		883	}
3031	serge	884	static bool
		885	intel_vlv_find_best_pll(const intel_limit_t limit, struct drm_crtc crtc,
		886	int target, int refclk, intel_clock_t *match_clock,
		887	intel_clock_t *best_clock)
		888	{
		889	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
		890	u32 m, n, fastclk;
		891	u32 updrate, minupdate, fracbits, p;
		892	unsigned long bestppm, ppm, absppm;
		893	int dotclk, flag;
2327	Serge	894
3031	serge	895	flag = 0;
		896	dotclk = target * 1000;
		897	bestppm = 1000000;
		898	ppm = absppm = 0;
		899	fastclk = dotclk / (2*100);
		900	updrate = 0;
		901	minupdate = 19200;
		902	fracbits = 1;
		903	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
		904	bestm1 = bestm2 = bestp1 = bestp2 = 0;
		905
		906	/* based on hardware requirement, prefer smaller n to precision */
		907	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		908	updrate = refclk / n;
		909	for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
		910	for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
		911	if (p2 > 10)
		912	p2 = p2 - 1;
		913	p = p1 * p2;
		914	/* based on hardware requirement, prefer bigger m1,m2 values */
		915	for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
		916	m2 = (((2(fastclk p * n / m1 )) +
		917	refclk) / (2*refclk));
		918	m = m1 * m2;
		919	vco = updrate * m;
		920	if (vco >= limit->vco.min && vco < limit->vco.max) {
		921	ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
		922	absppm = (ppm > 0) ? ppm : (-ppm);
		923	if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
		924	bestppm = 0;
		925	flag = 1;
		926	}
		927	if (absppm < bestppm - 10) {
		928	bestppm = absppm;
		929	flag = 1;
		930	}
		931	if (flag) {
		932	bestn = n;
		933	bestm1 = m1;
		934	bestm2 = m2;
		935	bestp1 = p1;
		936	bestp2 = p2;
		937	flag = 0;
		938	}
		939	}
		940	}
		941	}
		942	}
		943	}
		944	best_clock->n = bestn;
		945	best_clock->m1 = bestm1;
		946	best_clock->m2 = bestm2;
		947	best_clock->p1 = bestp1;
		948	best_clock->p2 = bestp2;
		949
		950	return true;
		951	}
		952
		953	static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
		954	{
		955	struct drm_i915_private *dev_priv = dev->dev_private;
		956	u32 frame, frame_reg = PIPEFRAME(pipe);
		957
		958	frame = I915_READ(frame_reg);
		959
		960	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		961	DRM_DEBUG_KMS("vblank wait timed out\n");
		962	}
		963
2327	Serge	964	/**
		965	* intel_wait_for_vblank - wait for vblank on a given pipe
		966	* @dev: drm device
		967	* @pipe: pipe to wait for
		968	*
		969	* Wait for vblank to occur on a given pipe. Needed for various bits of
		970	* mode setting code.
		971	*/
		972	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		973	{
		974	struct drm_i915_private *dev_priv = dev->dev_private;
		975	int pipestat_reg = PIPESTAT(pipe);
		976
3031	serge	977	if (INTEL_INFO(dev)->gen >= 5) {
		978	ironlake_wait_for_vblank(dev, pipe);
		979	return;
		980	}
		981
2327	Serge	982	/* Clear existing vblank status. Note this will clear any other
		983	* sticky status fields as well.
		984	*
		985	* This races with i915_driver_irq_handler() with the result
		986	* that either function could miss a vblank event. Here it is not
		987	* fatal, as we will either wait upon the next vblank interrupt or
		988	* timeout. Generally speaking intel_wait_for_vblank() is only
		989	* called during modeset at which time the GPU should be idle and
		990	* should not be performing page flips and thus not waiting on
		991	* vblanks...
		992	* Currently, the result of us stealing a vblank from the irq
		993	* handler is that a single frame will be skipped during swapbuffers.
		994	*/
		995	I915_WRITE(pipestat_reg,
		996	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		997
		998	/* Wait for vblank interrupt bit to set */
		999	if (wait_for(I915_READ(pipestat_reg) &
		1000	PIPE_VBLANK_INTERRUPT_STATUS,
		1001	50))
		1002	DRM_DEBUG_KMS("vblank wait timed out\n");
		1003	}
		1004
		1005	/*
		1006	* intel_wait_for_pipe_off - wait for pipe to turn off
		1007	* @dev: drm device
		1008	* @pipe: pipe to wait for
		1009	*
		1010	* After disabling a pipe, we can't wait for vblank in the usual way,
		1011	* spinning on the vblank interrupt status bit, since we won't actually
		1012	* see an interrupt when the pipe is disabled.
		1013	*
		1014	* On Gen4 and above:
		1015	* wait for the pipe register state bit to turn off
		1016	*
		1017	* Otherwise:
		1018	* wait for the display line value to settle (it usually
		1019	* ends up stopping at the start of the next frame).
		1020	*
		1021	*/
		1022	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		1023	{
		1024	struct drm_i915_private *dev_priv = dev->dev_private;
		1025
		1026	if (INTEL_INFO(dev)->gen >= 4) {
		1027	int reg = PIPECONF(pipe);
		1028
		1029	/* Wait for the Pipe State to go off */
		1030	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		1031	100))
3031	serge	1032	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1033	} else {
3031	serge	1034	u32 last_line, line_mask;
2327	Serge	1035	int reg = PIPEDSL(pipe);
3031	serge	1036	unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
2327	Serge	1037
3031	serge	1038	if (IS_GEN2(dev))
		1039	line_mask = DSL_LINEMASK_GEN2;
		1040	else
		1041	line_mask = DSL_LINEMASK_GEN3;
		1042
2327	Serge	1043	/* Wait for the display line to settle */
		1044	do {
3031	serge	1045	last_line = I915_READ(reg) & line_mask;
2327	Serge	1046	mdelay(5);
3031	serge	1047	} while (((I915_READ(reg) & line_mask) != last_line) &&
		1048	time_after(timeout, GetTimerTicks()));
		1049	if (time_after(GetTimerTicks(), timeout))
		1050	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1051	}
		1052	}
		1053
		1054	static const char *state_string(bool enabled)
		1055	{
		1056	return enabled ? "on" : "off";
		1057	}
		1058
		1059	/* Only for pre-ILK configs */
		1060	static void assert_pll(struct drm_i915_private *dev_priv,
		1061	enum pipe pipe, bool state)
		1062	{
		1063	int reg;
		1064	u32 val;
		1065	bool cur_state;
		1066
		1067	reg = DPLL(pipe);
		1068	val = I915_READ(reg);
		1069	cur_state = !!(val & DPLL_VCO_ENABLE);
		1070	WARN(cur_state != state,
		1071	"PLL state assertion failure (expected %s, current %s)\n",
		1072	state_string(state), state_string(cur_state));
		1073	}
		1074	#define assert_pll_enabled(d, p) assert_pll(d, p, true)
		1075	#define assert_pll_disabled(d, p) assert_pll(d, p, false)
		1076
		1077	/* For ILK+ */
		1078	static void assert_pch_pll(struct drm_i915_private *dev_priv,
3031	serge	1079	struct intel_pch_pll *pll,
		1080	struct intel_crtc *crtc,
		1081	bool state)
2327	Serge	1082	{
		1083	u32 val;
		1084	bool cur_state;
		1085
3031	serge	1086	if (HAS_PCH_LPT(dev_priv->dev)) {
		1087	DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		1088	return;
		1089	}
2342	Serge	1090
3031	serge	1091	if (WARN (!pll,
		1092	"asserting PCH PLL %s with no PLL\n", state_string(state)))
		1093	return;
2342	Serge	1094
3031	serge	1095	val = I915_READ(pll->pll_reg);
		1096	cur_state = !!(val & DPLL_VCO_ENABLE);
		1097	WARN(cur_state != state,
		1098	"PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
		1099	pll->pll_reg, state_string(state), state_string(cur_state), val);
2342	Serge	1100
3031	serge	1101	/* Make sure the selected PLL is correctly attached to the transcoder */
		1102	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
		1103	u32 pch_dpll;
2342	Serge	1104
3031	serge	1105	pch_dpll = I915_READ(PCH_DPLL_SEL);
		1106	cur_state = pll->pll_reg == _PCH_DPLL_B;
		1107	if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
		1108	"PLL[%d] not attached to this transcoder %d: %08x\n",
		1109	cur_state, crtc->pipe, pch_dpll)) {
		1110	cur_state = !!(val >> (4*crtc->pipe + 3));
2327	Serge	1111	WARN(cur_state != state,
3031	serge	1112	"PLL[%d] not %s on this transcoder %d: %08x\n",
		1113	pll->pll_reg == _PCH_DPLL_B,
		1114	state_string(state),
		1115	crtc->pipe,
		1116	val);
		1117	}
		1118	}
2327	Serge	1119	}
3031	serge	1120	#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
		1121	#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
2327	Serge	1122
		1123	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		1124	enum pipe pipe, bool state)
		1125	{
		1126	int reg;
		1127	u32 val;
		1128	bool cur_state;
		1129
3031	serge	1130	if (IS_HASWELL(dev_priv->dev)) {
		1131	/* On Haswell, DDI is used instead of FDI_TX_CTL */
		1132	reg = DDI_FUNC_CTL(pipe);
		1133	val = I915_READ(reg);
		1134	cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
		1135	} else {
2327	Serge	1136	reg = FDI_TX_CTL(pipe);
		1137	val = I915_READ(reg);
		1138	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	1139	}
2327	Serge	1140	WARN(cur_state != state,
		1141	"FDI TX state assertion failure (expected %s, current %s)\n",
		1142	state_string(state), state_string(cur_state));
		1143	}
		1144	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		1145	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		1146
		1147	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		1148	enum pipe pipe, bool state)
		1149	{
		1150	int reg;
		1151	u32 val;
		1152	bool cur_state;
		1153
3031	serge	1154	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		1155	DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
		1156	return;
		1157	} else {
2327	Serge	1158	reg = FDI_RX_CTL(pipe);
		1159	val = I915_READ(reg);
		1160	cur_state = !!(val & FDI_RX_ENABLE);
3031	serge	1161	}
2327	Serge	1162	WARN(cur_state != state,
		1163	"FDI RX state assertion failure (expected %s, current %s)\n",
		1164	state_string(state), state_string(cur_state));
		1165	}
		1166	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1167	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1168
		1169	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1170	enum pipe pipe)
		1171	{
		1172	int reg;
		1173	u32 val;
		1174
		1175	/* ILK FDI PLL is always enabled */
		1176	if (dev_priv->info->gen == 5)
		1177	return;
		1178
3031	serge	1179	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
		1180	if (IS_HASWELL(dev_priv->dev))
		1181	return;
		1182
2327	Serge	1183	reg = FDI_TX_CTL(pipe);
		1184	val = I915_READ(reg);
		1185	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		1186	}
		1187
		1188	static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
		1189	enum pipe pipe)
		1190	{
		1191	int reg;
		1192	u32 val;
		1193
3031	serge	1194	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		1195	DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
		1196	return;
		1197	}
2327	Serge	1198	reg = FDI_RX_CTL(pipe);
		1199	val = I915_READ(reg);
		1200	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
		1201	}
		1202
		1203	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		1204	enum pipe pipe)
		1205	{
		1206	int pp_reg, lvds_reg;
		1207	u32 val;
		1208	enum pipe panel_pipe = PIPE_A;
		1209	bool locked = true;
		1210
		1211	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1212	pp_reg = PCH_PP_CONTROL;
		1213	lvds_reg = PCH_LVDS;
		1214	} else {
		1215	pp_reg = PP_CONTROL;
		1216	lvds_reg = LVDS;
		1217	}
		1218
		1219	val = I915_READ(pp_reg);
		1220	if (!(val & PANEL_POWER_ON) \|\|
		1221	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		1222	locked = false;
		1223
		1224	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		1225	panel_pipe = PIPE_B;
		1226
		1227	WARN(panel_pipe == pipe && locked,
		1228	"panel assertion failure, pipe %c regs locked\n",
		1229	pipe_name(pipe));
		1230	}
		1231
2342	Serge	1232	void assert_pipe(struct drm_i915_private *dev_priv,
2327	Serge	1233	enum pipe pipe, bool state)
		1234	{
		1235	int reg;
		1236	u32 val;
		1237	bool cur_state;
		1238
3031	serge	1239	/* if we need the pipe A quirk it must be always on */
		1240	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		1241	state = true;
		1242
2327	Serge	1243	reg = PIPECONF(pipe);
		1244	val = I915_READ(reg);
		1245	cur_state = !!(val & PIPECONF_ENABLE);
		1246	WARN(cur_state != state,
		1247	"pipe %c assertion failure (expected %s, current %s)\n",
		1248	pipe_name(pipe), state_string(state), state_string(cur_state));
		1249	}
		1250
3031	serge	1251	static void assert_plane(struct drm_i915_private *dev_priv,
		1252	enum plane plane, bool state)
2327	Serge	1253	{
		1254	int reg;
		1255	u32 val;
3031	serge	1256	bool cur_state;
2327	Serge	1257
		1258	reg = DSPCNTR(plane);
		1259	val = I915_READ(reg);
3031	serge	1260	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
		1261	WARN(cur_state != state,
		1262	"plane %c assertion failure (expected %s, current %s)\n",
		1263	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1264	}
		1265
3031	serge	1266	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1267	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1268
2327	Serge	1269	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1270	enum pipe pipe)
		1271	{
		1272	int reg, i;
		1273	u32 val;
		1274	int cur_pipe;
		1275
		1276	/* Planes are fixed to pipes on ILK+ */
3031	serge	1277	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1278	reg = DSPCNTR(pipe);
		1279	val = I915_READ(reg);
		1280	WARN((val & DISPLAY_PLANE_ENABLE),
		1281	"plane %c assertion failure, should be disabled but not\n",
		1282	plane_name(pipe));
2327	Serge	1283	return;
3031	serge	1284	}
2327	Serge	1285
		1286	/* Need to check both planes against the pipe */
		1287	for (i = 0; i < 2; i++) {
		1288	reg = DSPCNTR(i);
		1289	val = I915_READ(reg);
		1290	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		1291	DISPPLANE_SEL_PIPE_SHIFT;
		1292	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		1293	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1294	plane_name(i), pipe_name(pipe));
		1295	}
		1296	}
		1297
		1298	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		1299	{
		1300	u32 val;
		1301	bool enabled;
		1302
3031	serge	1303	if (HAS_PCH_LPT(dev_priv->dev)) {
		1304	DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		1305	return;
		1306	}
		1307
2327	Serge	1308	val = I915_READ(PCH_DREF_CONTROL);
		1309	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1310	DREF_SUPERSPREAD_SOURCE_MASK));
		1311	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		1312	}
		1313
		1314	static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
		1315	enum pipe pipe)
		1316	{
		1317	int reg;
		1318	u32 val;
		1319	bool enabled;
		1320
		1321	reg = TRANSCONF(pipe);
		1322	val = I915_READ(reg);
		1323	enabled = !!(val & TRANS_ENABLE);
		1324	WARN(enabled,
		1325	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1326	pipe_name(pipe));
		1327	}
		1328
		1329	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1330	enum pipe pipe, u32 port_sel, u32 val)
		1331	{
		1332	if ((val & DP_PORT_EN) == 0)
		1333	return false;
		1334
		1335	if (HAS_PCH_CPT(dev_priv->dev)) {
		1336	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1337	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1338	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1339	return false;
		1340	} else {
		1341	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1342	return false;
		1343	}
		1344	return true;
		1345	}
		1346
		1347	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1348	enum pipe pipe, u32 val)
		1349	{
		1350	if ((val & PORT_ENABLE) == 0)
		1351	return false;
		1352
		1353	if (HAS_PCH_CPT(dev_priv->dev)) {
		1354	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1355	return false;
		1356	} else {
		1357	if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
		1358	return false;
		1359	}
		1360	return true;
		1361	}
		1362
		1363	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1364	enum pipe pipe, u32 val)
		1365	{
		1366	if ((val & LVDS_PORT_EN) == 0)
		1367	return false;
		1368
		1369	if (HAS_PCH_CPT(dev_priv->dev)) {
		1370	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1371	return false;
		1372	} else {
		1373	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1374	return false;
		1375	}
		1376	return true;
		1377	}
		1378
		1379	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1380	enum pipe pipe, u32 val)
		1381	{
		1382	if ((val & ADPA_DAC_ENABLE) == 0)
		1383	return false;
		1384	if (HAS_PCH_CPT(dev_priv->dev)) {
		1385	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1386	return false;
		1387	} else {
		1388	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1389	return false;
		1390	}
		1391	return true;
		1392	}
		1393
		1394	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1395	enum pipe pipe, int reg, u32 port_sel)
		1396	{
		1397	u32 val = I915_READ(reg);
		1398	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1399	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1400	reg, pipe_name(pipe));
3031	serge	1401
		1402	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
		1403	&& (val & DP_PIPEB_SELECT),
		1404	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1405	}
		1406
		1407	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1408	enum pipe pipe, int reg)
		1409	{
		1410	u32 val = I915_READ(reg);
3031	serge	1411	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
		1412	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1413	reg, pipe_name(pipe));
3031	serge	1414
		1415	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
		1416	&& (val & SDVO_PIPE_B_SELECT),
		1417	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1418	}
		1419
		1420	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1421	enum pipe pipe)
		1422	{
		1423	int reg;
		1424	u32 val;
		1425
		1426	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1427	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1428	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1429
		1430	reg = PCH_ADPA;
		1431	val = I915_READ(reg);
3031	serge	1432	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1433	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1434	pipe_name(pipe));
		1435
		1436	reg = PCH_LVDS;
		1437	val = I915_READ(reg);
3031	serge	1438	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1439	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1440	pipe_name(pipe));
		1441
		1442	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
		1443	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
		1444	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
		1445	}
		1446
		1447	/**
		1448	* intel_enable_pll - enable a PLL
		1449	* @dev_priv: i915 private structure
		1450	* @pipe: pipe PLL to enable
		1451	*
		1452	* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
		1453	* make sure the PLL reg is writable first though, since the panel write
		1454	* protect mechanism may be enabled.
		1455	*
		1456	* Note! This is for pre-ILK only.
3031	serge	1457	*
		1458	* Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
2327	Serge	1459	*/
		1460	static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1461	{
		1462	int reg;
		1463	u32 val;
		1464
		1465	/* No really, not for ILK+ */
3031	serge	1466	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
2327	Serge	1467
		1468	/* PLL is protected by panel, make sure we can write it */
		1469	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		1470	assert_panel_unlocked(dev_priv, pipe);
		1471
		1472	reg = DPLL(pipe);
		1473	val = I915_READ(reg);
		1474	val \|= DPLL_VCO_ENABLE;
		1475
		1476	/* We do this three times for luck */
		1477	I915_WRITE(reg, val);
		1478	POSTING_READ(reg);
		1479	udelay(150); /* wait for warmup */
		1480	I915_WRITE(reg, val);
		1481	POSTING_READ(reg);
		1482	udelay(150); /* wait for warmup */
		1483	I915_WRITE(reg, val);
		1484	POSTING_READ(reg);
		1485	udelay(150); /* wait for warmup */
		1486	}
		1487
		1488	/**
		1489	* intel_disable_pll - disable a PLL
		1490	* @dev_priv: i915 private structure
		1491	* @pipe: pipe PLL to disable
		1492	*
		1493	* Disable the PLL for @pipe, making sure the pipe is off first.
		1494	*
		1495	* Note! This is for pre-ILK only.
		1496	*/
		1497	static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1498	{
		1499	int reg;
		1500	u32 val;
		1501
		1502	/* Don't disable pipe A or pipe A PLLs if needed */
		1503	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1504	return;
		1505
		1506	/* Make sure the pipe isn't still relying on us */
		1507	assert_pipe_disabled(dev_priv, pipe);
		1508
		1509	reg = DPLL(pipe);
		1510	val = I915_READ(reg);
		1511	val &= ~DPLL_VCO_ENABLE;
		1512	I915_WRITE(reg, val);
		1513	POSTING_READ(reg);
		1514	}
		1515
3031	serge	1516	/* SBI access */
		1517	static void
		1518	intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
		1519	{
		1520	unsigned long flags;
		1521
		1522	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
		1523	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
		1524	100)) {
		1525	DRM_ERROR("timeout waiting for SBI to become ready\n");
		1526	goto out_unlock;
		1527	}
		1528
		1529	I915_WRITE(SBI_ADDR,
		1530	(reg << 16));
		1531	I915_WRITE(SBI_DATA,
		1532	value);
		1533	I915_WRITE(SBI_CTL_STAT,
		1534	SBI_BUSY \|
		1535	SBI_CTL_OP_CRWR);
		1536
		1537	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY \| SBI_RESPONSE_FAIL)) == 0,
		1538	100)) {
		1539	DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
		1540	goto out_unlock;
		1541	}
		1542
		1543	out_unlock:
		1544	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
		1545	}
		1546
		1547	static u32
		1548	intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
		1549	{
		1550	unsigned long flags;
		1551	u32 value = 0;
		1552
		1553	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
		1554	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
		1555	100)) {
		1556	DRM_ERROR("timeout waiting for SBI to become ready\n");
		1557	goto out_unlock;
		1558	}
		1559
		1560	I915_WRITE(SBI_ADDR,
		1561	(reg << 16));
		1562	I915_WRITE(SBI_CTL_STAT,
		1563	SBI_BUSY \|
		1564	SBI_CTL_OP_CRRD);
		1565
		1566	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY \| SBI_RESPONSE_FAIL)) == 0,
		1567	100)) {
		1568	DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
		1569	goto out_unlock;
		1570	}
		1571
		1572	value = I915_READ(SBI_DATA);
		1573
		1574	out_unlock:
		1575	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
		1576	return value;
		1577	}
		1578
2327	Serge	1579	/**
		1580	* intel_enable_pch_pll - enable PCH PLL
		1581	* @dev_priv: i915 private structure
		1582	* @pipe: pipe PLL to enable
		1583	*
		1584	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1585	* drives the transcoder clock.
		1586	*/
3031	serge	1587	static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
2327	Serge	1588	{
3031	serge	1589	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		1590	struct intel_pch_pll *pll;
2327	Serge	1591	int reg;
		1592	u32 val;
		1593
3031	serge	1594	/* PCH PLLs only available on ILK, SNB and IVB */
		1595	BUG_ON(dev_priv->info->gen < 5);
		1596	pll = intel_crtc->pch_pll;
		1597	if (pll == NULL)
2342	Serge	1598	return;
		1599
3031	serge	1600	if (WARN_ON(pll->refcount == 0))
		1601	return;
2327	Serge	1602
3031	serge	1603	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
		1604	pll->pll_reg, pll->active, pll->on,
		1605	intel_crtc->base.base.id);
		1606
2327	Serge	1607	/* PCH refclock must be enabled first */
		1608	assert_pch_refclk_enabled(dev_priv);
		1609
3031	serge	1610	if (pll->active++ && pll->on) {
		1611	assert_pch_pll_enabled(dev_priv, pll, NULL);
		1612	return;
		1613	}
		1614
		1615	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
		1616
		1617	reg = pll->pll_reg;
2327	Serge	1618	val = I915_READ(reg);
		1619	val \|= DPLL_VCO_ENABLE;
		1620	I915_WRITE(reg, val);
		1621	POSTING_READ(reg);
		1622	udelay(200);
3031	serge	1623
		1624	pll->on = true;
2327	Serge	1625	}
		1626
3031	serge	1627	static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
2327	Serge	1628	{
3031	serge	1629	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		1630	struct intel_pch_pll *pll = intel_crtc->pch_pll;
2327	Serge	1631	int reg;
3031	serge	1632	u32 val;
2327	Serge	1633
		1634	/* PCH only available on ILK+ */
		1635	BUG_ON(dev_priv->info->gen < 5);
3031	serge	1636	if (pll == NULL)
		1637	return;
2327	Serge	1638
3031	serge	1639	if (WARN_ON(pll->refcount == 0))
		1640	return;
2327	Serge	1641
3031	serge	1642	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
		1643	pll->pll_reg, pll->active, pll->on,
		1644	intel_crtc->base.base.id);
2342	Serge	1645
3031	serge	1646	if (WARN_ON(pll->active == 0)) {
		1647	assert_pch_pll_disabled(dev_priv, pll, NULL);
		1648	return;
		1649	}
2342	Serge	1650
3031	serge	1651	if (--pll->active) {
		1652	assert_pch_pll_enabled(dev_priv, pll, NULL);
2342	Serge	1653	return;
3031	serge	1654	}
2342	Serge	1655
3031	serge	1656	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
		1657
		1658	/* Make sure transcoder isn't still depending on us */
		1659	assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
		1660
		1661	reg = pll->pll_reg;
2327	Serge	1662	val = I915_READ(reg);
		1663	val &= ~DPLL_VCO_ENABLE;
		1664	I915_WRITE(reg, val);
		1665	POSTING_READ(reg);
		1666	udelay(200);
3031	serge	1667
		1668	pll->on = false;
2327	Serge	1669	}
		1670
		1671	static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
		1672	enum pipe pipe)
		1673	{
		1674	int reg;
3031	serge	1675	u32 val, pipeconf_val;
		1676	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	1677
		1678	/* PCH only available on ILK+ */
		1679	BUG_ON(dev_priv->info->gen < 5);
		1680
		1681	/* Make sure PCH DPLL is enabled */
3031	serge	1682	assert_pch_pll_enabled(dev_priv,
		1683	to_intel_crtc(crtc)->pch_pll,
		1684	to_intel_crtc(crtc));
2327	Serge	1685
		1686	/* FDI must be feeding us bits for PCH ports */
		1687	assert_fdi_tx_enabled(dev_priv, pipe);
		1688	assert_fdi_rx_enabled(dev_priv, pipe);
		1689
3031	serge	1690	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		1691	DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
		1692	return;
		1693	}
2327	Serge	1694	reg = TRANSCONF(pipe);
		1695	val = I915_READ(reg);
3031	serge	1696	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1697
		1698	if (HAS_PCH_IBX(dev_priv->dev)) {
		1699	/*
		1700	* make the BPC in transcoder be consistent with
		1701	* that in pipeconf reg.
		1702	*/
		1703	val &= ~PIPE_BPC_MASK;
3031	serge	1704	val \|= pipeconf_val & PIPE_BPC_MASK;
2327	Serge	1705	}
3031	serge	1706
		1707	val &= ~TRANS_INTERLACE_MASK;
		1708	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		1709	if (HAS_PCH_IBX(dev_priv->dev) &&
		1710	intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
		1711	val \|= TRANS_LEGACY_INTERLACED_ILK;
		1712	else
		1713	val \|= TRANS_INTERLACED;
		1714	else
		1715	val \|= TRANS_PROGRESSIVE;
		1716
2327	Serge	1717	I915_WRITE(reg, val \| TRANS_ENABLE);
		1718	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		1719	DRM_ERROR("failed to enable transcoder %d\n", pipe);
		1720	}
		1721
		1722	static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
		1723	enum pipe pipe)
		1724	{
		1725	int reg;
		1726	u32 val;
		1727
		1728	/* FDI relies on the transcoder */
		1729	assert_fdi_tx_disabled(dev_priv, pipe);
		1730	assert_fdi_rx_disabled(dev_priv, pipe);
		1731
		1732	/* Ports must be off as well */
		1733	assert_pch_ports_disabled(dev_priv, pipe);
		1734
		1735	reg = TRANSCONF(pipe);
		1736	val = I915_READ(reg);
		1737	val &= ~TRANS_ENABLE;
		1738	I915_WRITE(reg, val);
		1739	/* wait for PCH transcoder off, transcoder state */
		1740	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2342	Serge	1741	DRM_ERROR("failed to disable transcoder %d\n", pipe);
2327	Serge	1742	}
		1743
		1744	/**
		1745	* intel_enable_pipe - enable a pipe, asserting requirements
		1746	* @dev_priv: i915 private structure
		1747	* @pipe: pipe to enable
		1748	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1749	*
		1750	* Enable @pipe, making sure that various hardware specific requirements
		1751	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1752	*
		1753	* @pipe should be %PIPE_A or %PIPE_B.
		1754	*
		1755	* Will wait until the pipe is actually running (i.e. first vblank) before
		1756	* returning.
		1757	*/
		1758	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1759	bool pch_port)
		1760	{
		1761	int reg;
		1762	u32 val;
		1763
		1764	/*
		1765	* A pipe without a PLL won't actually be able to drive bits from
		1766	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1767	* need the check.
		1768	*/
		1769	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1770	assert_pll_enabled(dev_priv, pipe);
		1771	else {
		1772	if (pch_port) {
		1773	/* if driving the PCH, we need FDI enabled */
		1774	assert_fdi_rx_pll_enabled(dev_priv, pipe);
		1775	assert_fdi_tx_pll_enabled(dev_priv, pipe);
		1776	}
		1777	/* FIXME: assert CPU port conditions for SNB+ */
		1778	}
		1779
		1780	reg = PIPECONF(pipe);
		1781	val = I915_READ(reg);
		1782	if (val & PIPECONF_ENABLE)
		1783	return;
		1784
		1785	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1786	intel_wait_for_vblank(dev_priv->dev, pipe);
		1787	}
		1788
		1789	/**
		1790	* intel_disable_pipe - disable a pipe, asserting requirements
		1791	* @dev_priv: i915 private structure
		1792	* @pipe: pipe to disable
		1793	*
		1794	* Disable @pipe, making sure that various hardware specific requirements
		1795	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1796	*
		1797	* @pipe should be %PIPE_A or %PIPE_B.
		1798	*
		1799	* Will wait until the pipe has shut down before returning.
		1800	*/
		1801	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1802	enum pipe pipe)
		1803	{
		1804	int reg;
		1805	u32 val;
		1806
3031	serge	1807	/*
2327	Serge	1808	* Make sure planes won't keep trying to pump pixels to us,
		1809	* or we might hang the display.
		1810	*/
		1811	assert_planes_disabled(dev_priv, pipe);
		1812
		1813	/* Don't disable pipe A or pipe A PLLs if needed */
		1814	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1815	return;
		1816
		1817	reg = PIPECONF(pipe);
		1818	val = I915_READ(reg);
		1819	if ((val & PIPECONF_ENABLE) == 0)
		1820	return;
		1821
		1822	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1823	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		1824	}
		1825
		1826	/*
		1827	* Plane regs are double buffered, going from enabled->disabled needs a
		1828	* trigger in order to latch. The display address reg provides this.
		1829	*/
3031	serge	1830	void intel_flush_display_plane(struct drm_i915_private *dev_priv,
2327	Serge	1831	enum plane plane)
		1832	{
		1833	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1834	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1835	}
		1836
		1837	/**
		1838	* intel_enable_plane - enable a display plane on a given pipe
		1839	* @dev_priv: i915 private structure
		1840	* @plane: plane to enable
		1841	* @pipe: pipe being fed
		1842	*
		1843	* Enable @plane on @pipe, making sure that @pipe is running first.
		1844	*/
		1845	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1846	enum plane plane, enum pipe pipe)
		1847	{
		1848	int reg;
		1849	u32 val;
		1850
		1851	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1852	assert_pipe_enabled(dev_priv, pipe);
		1853
		1854	reg = DSPCNTR(plane);
		1855	val = I915_READ(reg);
		1856	if (val & DISPLAY_PLANE_ENABLE)
		1857	return;
		1858
		1859	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1860	intel_flush_display_plane(dev_priv, plane);
		1861	intel_wait_for_vblank(dev_priv->dev, pipe);
		1862	}
		1863
		1864	/**
		1865	* intel_disable_plane - disable a display plane
		1866	* @dev_priv: i915 private structure
		1867	* @plane: plane to disable
		1868	* @pipe: pipe consuming the data
		1869	*
		1870	* Disable @plane; should be an independent operation.
		1871	*/
		1872	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1873	enum plane plane, enum pipe pipe)
		1874	{
		1875	int reg;
		1876	u32 val;
		1877
		1878	reg = DSPCNTR(plane);
		1879	val = I915_READ(reg);
		1880	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1881	return;
		1882
		1883	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1884	intel_flush_display_plane(dev_priv, plane);
3031	serge	1885	intel_wait_for_vblank(dev_priv->dev, pipe);
2327	Serge	1886	}
		1887
2335	Serge	1888	int
		1889	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1890	struct drm_i915_gem_object *obj,
		1891	struct intel_ring_buffer *pipelined)
		1892	{
		1893	struct drm_i915_private *dev_priv = dev->dev_private;
		1894	u32 alignment;
		1895	int ret;
2327	Serge	1896
2335	Serge	1897	switch (obj->tiling_mode) {
		1898	case I915_TILING_NONE:
		1899	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		1900	alignment = 128 * 1024;
		1901	else if (INTEL_INFO(dev)->gen >= 4)
		1902	alignment = 4 * 1024;
		1903	else
		1904	alignment = 64 * 1024;
		1905	break;
		1906	case I915_TILING_X:
		1907	/* pin() will align the object as required by fence */
		1908	alignment = 0;
		1909	break;
		1910	case I915_TILING_Y:
		1911	/* FIXME: Is this true? */
		1912	DRM_ERROR("Y tiled not allowed for scan out buffers\n");
		1913	return -EINVAL;
		1914	default:
		1915	BUG();
		1916	}
2327	Serge	1917
2335	Serge	1918	dev_priv->mm.interruptible = false;
		1919	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		1920	if (ret)
		1921	goto err_interruptible;
2327	Serge	1922
2335	Serge	1923	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		1924	* fence, whereas 965+ only requires a fence if using
		1925	* framebuffer compression. For simplicity, we always install
		1926	* a fence as the cost is not that onerous.
		1927	*/
		1928	// if (obj->tiling_mode != I915_TILING_NONE) {
		1929	// ret = i915_gem_object_get_fence(obj, pipelined);
		1930	// if (ret)
		1931	// goto err_unpin;
		1932	// }
2327	Serge	1933
2335	Serge	1934	dev_priv->mm.interruptible = true;
		1935	return 0;
2327	Serge	1936
2335	Serge	1937	err_unpin:
2344	Serge	1938	i915_gem_object_unpin(obj);
2335	Serge	1939	err_interruptible:
		1940	dev_priv->mm.interruptible = true;
		1941	return ret;
		1942	}
2327	Serge	1943
3031	serge	1944	void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
		1945	{
		1946	// i915_gem_object_unpin_fence(obj);
		1947	// i915_gem_object_unpin(obj);
		1948	}
		1949
		1950	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		1951	* is assumed to be a power-of-two. */
		1952	static unsigned long gen4_compute_dspaddr_offset_xtiled(int x, int y,
		1953	unsigned int bpp,
		1954	unsigned int pitch)
		1955	{
		1956	int tile_rows, tiles;
		1957
		1958	tile_rows = *y / 8;
		1959	*y %= 8;
		1960	tiles = *x / (512/bpp);
		1961	*x %= 512/bpp;
		1962
		1963	return tile_rows * pitch * 8 + tiles * 4096;
		1964	}
		1965
2327	Serge	1966	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		1967	int x, int y)
		1968	{
		1969	struct drm_device *dev = crtc->dev;
		1970	struct drm_i915_private *dev_priv = dev->dev_private;
		1971	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1972	struct intel_framebuffer *intel_fb;
		1973	struct drm_i915_gem_object *obj;
		1974	int plane = intel_crtc->plane;
3031	serge	1975	unsigned long linear_offset;
2327	Serge	1976	u32 dspcntr;
		1977	u32 reg;
		1978
		1979	switch (plane) {
		1980	case 0:
		1981	case 1:
		1982	break;
		1983	default:
		1984	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		1985	return -EINVAL;
		1986	}
		1987
		1988	intel_fb = to_intel_framebuffer(fb);
		1989	obj = intel_fb->obj;
		1990
		1991	reg = DSPCNTR(plane);
		1992	dspcntr = I915_READ(reg);
		1993	/* Mask out pixel format bits in case we change it */
		1994	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
		1995	switch (fb->bits_per_pixel) {
		1996	case 8:
		1997	dspcntr \|= DISPPLANE_8BPP;
		1998	break;
		1999	case 16:
		2000	if (fb->depth == 15)
		2001	dspcntr \|= DISPPLANE_15_16BPP;
		2002	else
		2003	dspcntr \|= DISPPLANE_16BPP;
		2004	break;
		2005	case 24:
		2006	case 32:
		2007	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
		2008	break;
		2009	default:
		2010	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		2011	return -EINVAL;
		2012	}
		2013	if (INTEL_INFO(dev)->gen >= 4) {
		2014	if (obj->tiling_mode != I915_TILING_NONE)
		2015	dspcntr \|= DISPPLANE_TILED;
		2016	else
		2017	dspcntr &= ~DISPPLANE_TILED;
		2018	}
		2019
		2020	I915_WRITE(reg, dspcntr);
		2021
3031	serge	2022	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327	Serge	2023
3031	serge	2024	if (INTEL_INFO(dev)->gen >= 4) {
		2025	intel_crtc->dspaddr_offset =
		2026	gen4_compute_dspaddr_offset_xtiled(&x, &y,
		2027	fb->bits_per_pixel / 8,
		2028	fb->pitches[0]);
		2029	linear_offset -= intel_crtc->dspaddr_offset;
		2030	} else {
		2031	intel_crtc->dspaddr_offset = linear_offset;
		2032	}
		2033
		2034	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		2035	obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2342	Serge	2036	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327	Serge	2037	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	2038	I915_MODIFY_DISPBASE(DSPSURF(plane),
		2039	obj->gtt_offset + intel_crtc->dspaddr_offset);
2327	Serge	2040	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2041	I915_WRITE(DSPLINOFF(plane), linear_offset);
2327	Serge	2042	} else
3031	serge	2043	I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2327	Serge	2044	POSTING_READ(reg);
		2045
		2046	return 0;
		2047	}
		2048
		2049	static int ironlake_update_plane(struct drm_crtc *crtc,
		2050	struct drm_framebuffer *fb, int x, int y)
		2051	{
		2052	struct drm_device *dev = crtc->dev;
		2053	struct drm_i915_private *dev_priv = dev->dev_private;
		2054	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2055	struct intel_framebuffer *intel_fb;
		2056	struct drm_i915_gem_object *obj;
		2057	int plane = intel_crtc->plane;
3031	serge	2058	unsigned long linear_offset;
2327	Serge	2059	u32 dspcntr;
		2060	u32 reg;
		2061
		2062	switch (plane) {
		2063	case 0:
		2064	case 1:
2342	Serge	2065	case 2:
2327	Serge	2066	break;
		2067	default:
		2068	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		2069	return -EINVAL;
		2070	}
		2071
		2072	intel_fb = to_intel_framebuffer(fb);
		2073	obj = intel_fb->obj;
		2074
		2075	reg = DSPCNTR(plane);
		2076	dspcntr = I915_READ(reg);
		2077	/* Mask out pixel format bits in case we change it */
		2078	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
		2079	switch (fb->bits_per_pixel) {
		2080	case 8:
		2081	dspcntr \|= DISPPLANE_8BPP;
		2082	break;
		2083	case 16:
		2084	if (fb->depth != 16)
		2085	return -EINVAL;
		2086
		2087	dspcntr \|= DISPPLANE_16BPP;
		2088	break;
		2089	case 24:
		2090	case 32:
		2091	if (fb->depth == 24)
		2092	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
		2093	else if (fb->depth == 30)
		2094	dspcntr \|= DISPPLANE_32BPP_30BIT_NO_ALPHA;
		2095	else
		2096	return -EINVAL;
		2097	break;
		2098	default:
		2099	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		2100	return -EINVAL;
		2101	}
		2102
		2103	// if (obj->tiling_mode != I915_TILING_NONE)
		2104	// dspcntr \|= DISPPLANE_TILED;
		2105	// else
		2106	dspcntr &= ~DISPPLANE_TILED;
		2107
		2108	/* must disable */
		2109	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2110
		2111	I915_WRITE(reg, dspcntr);
		2112
3031	serge	2113	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
		2114	intel_crtc->dspaddr_offset =
		2115	gen4_compute_dspaddr_offset_xtiled(&x, &y,
		2116	fb->bits_per_pixel / 8,
		2117	fb->pitches[0]);
		2118	linear_offset -= intel_crtc->dspaddr_offset;
2327	Serge	2119
3031	serge	2120	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		2121	obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2342	Serge	2122	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3031	serge	2123	I915_MODIFY_DISPBASE(DSPSURF(plane),
		2124	obj->gtt_offset + intel_crtc->dspaddr_offset);
2330	Serge	2125	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2126	I915_WRITE(DSPLINOFF(plane), linear_offset);
2330	Serge	2127	POSTING_READ(reg);
2327	Serge	2128
		2129	return 0;
		2130	}
		2131
		2132	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2133	static int
		2134	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2135	int x, int y, enum mode_set_atomic state)
		2136	{
		2137	struct drm_device *dev = crtc->dev;
		2138	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2139
		2140	if (dev_priv->display.disable_fbc)
		2141	dev_priv->display.disable_fbc(dev);
		2142	intel_increase_pllclock(crtc);
		2143
		2144	return dev_priv->display.update_plane(crtc, fb, x, y);
		2145	}
		2146
		2147	#if 0
		2148	static int
		2149	intel_finish_fb(struct drm_framebuffer *old_fb)
		2150	{
		2151	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
		2152	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		2153	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	2154	int ret;
		2155
3031	serge	2156	wait_event(dev_priv->pending_flip_queue,
		2157	atomic_read(&dev_priv->mm.wedged) \|\|
		2158	atomic_read(&obj->pending_flip) == 0);
2327	Serge	2159
3031	serge	2160	/* Big Hammer, we also need to ensure that any pending
		2161	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2162	* current scanout is retired before unpinning the old
		2163	* framebuffer.
		2164	*
		2165	* This should only fail upon a hung GPU, in which case we
		2166	* can safely continue.
		2167	*/
		2168	dev_priv->mm.interruptible = false;
		2169	ret = i915_gem_object_finish_gpu(obj);
		2170	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	2171
3031	serge	2172	return ret;
2327	Serge	2173	}
3031	serge	2174	#endif
2327	Serge	2175
		2176	static int
		2177	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
3031	serge	2178	struct drm_framebuffer *fb)
2327	Serge	2179	{
		2180	struct drm_device *dev = crtc->dev;
3031	serge	2181	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2182	struct drm_i915_master_private *master_priv;
		2183	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2184	struct drm_framebuffer *old_fb;
2342	Serge	2185	int ret;
2327	Serge	2186
		2187	/* no fb bound */
3031	serge	2188	if (!fb) {
2327	Serge	2189	DRM_ERROR("No FB bound\n");
		2190	return 0;
		2191	}
		2192
3031	serge	2193	if(intel_crtc->plane > dev_priv->num_pipe) {
		2194	DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
		2195	intel_crtc->plane,
		2196	dev_priv->num_pipe);
2327	Serge	2197	return -EINVAL;
		2198	}
		2199
		2200	mutex_lock(&dev->struct_mutex);
3031	serge	2201	// ret = intel_pin_and_fence_fb_obj(dev,
		2202	// to_intel_framebuffer(fb)->obj,
		2203	// NULL);
		2204	// if (ret != 0) {
		2205	// mutex_unlock(&dev->struct_mutex);
		2206	// DRM_ERROR("pin & fence failed\n");
		2207	// return ret;
		2208	// }
2327	Serge	2209
3031	serge	2210	// if (crtc->fb)
		2211	// intel_finish_fb(crtc->fb);
		2212
		2213	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2327	Serge	2214	if (ret) {
3031	serge	2215	intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2327	Serge	2216	mutex_unlock(&dev->struct_mutex);
		2217	DRM_ERROR("failed to update base address\n");
		2218	return ret;
		2219	}
		2220
3031	serge	2221	old_fb = crtc->fb;
		2222	crtc->fb = fb;
		2223	crtc->x = x;
		2224	crtc->y = y;
		2225
		2226	if (old_fb) {
		2227	intel_wait_for_vblank(dev, intel_crtc->pipe);
		2228	intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
		2229	}
		2230
		2231	intel_update_fbc(dev);
2336	Serge	2232	mutex_unlock(&dev->struct_mutex);
2327	Serge	2233
2336	Serge	2234	return 0;
2327	Serge	2235	}
		2236
		2237	static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
		2238	{
		2239	struct drm_device *dev = crtc->dev;
		2240	struct drm_i915_private *dev_priv = dev->dev_private;
		2241	u32 dpa_ctl;
		2242
		2243	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
		2244	dpa_ctl = I915_READ(DP_A);
		2245	dpa_ctl &= ~DP_PLL_FREQ_MASK;
		2246
		2247	if (clock < 200000) {
		2248	u32 temp;
		2249	dpa_ctl \|= DP_PLL_FREQ_160MHZ;
		2250	/* workaround for 160Mhz:
		2251	1) program 0x4600c bits 15:0 = 0x8124
		2252	2) program 0x46010 bit 0 = 1
		2253	3) program 0x46034 bit 24 = 1
		2254	4) program 0x64000 bit 14 = 1
		2255	*/
		2256	temp = I915_READ(0x4600c);
		2257	temp &= 0xffff0000;
		2258	I915_WRITE(0x4600c, temp \| 0x8124);
		2259
		2260	temp = I915_READ(0x46010);
		2261	I915_WRITE(0x46010, temp \| 1);
		2262
		2263	temp = I915_READ(0x46034);
		2264	I915_WRITE(0x46034, temp \| (1 << 24));
		2265	} else {
		2266	dpa_ctl \|= DP_PLL_FREQ_270MHZ;
		2267	}
		2268	I915_WRITE(DP_A, dpa_ctl);
		2269
		2270	POSTING_READ(DP_A);
		2271	udelay(500);
		2272	}
		2273
		2274	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2275	{
		2276	struct drm_device *dev = crtc->dev;
		2277	struct drm_i915_private *dev_priv = dev->dev_private;
		2278	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2279	int pipe = intel_crtc->pipe;
		2280	u32 reg, temp;
		2281
		2282	/* enable normal train */
		2283	reg = FDI_TX_CTL(pipe);
		2284	temp = I915_READ(reg);
		2285	if (IS_IVYBRIDGE(dev)) {
		2286	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2287	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2288	} else {
		2289	temp &= ~FDI_LINK_TRAIN_NONE;
		2290	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2291	}
		2292	I915_WRITE(reg, temp);
		2293
		2294	reg = FDI_RX_CTL(pipe);
		2295	temp = I915_READ(reg);
		2296	if (HAS_PCH_CPT(dev)) {
		2297	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2298	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2299	} else {
		2300	temp &= ~FDI_LINK_TRAIN_NONE;
		2301	temp \|= FDI_LINK_TRAIN_NONE;
		2302	}
		2303	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2304
		2305	/* wait one idle pattern time */
		2306	POSTING_READ(reg);
		2307	udelay(1000);
		2308
		2309	/* IVB wants error correction enabled */
		2310	if (IS_IVYBRIDGE(dev))
		2311	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2312	FDI_FE_ERRC_ENABLE);
		2313	}
		2314
		2315	static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
		2316	{
		2317	struct drm_i915_private *dev_priv = dev->dev_private;
		2318	u32 flags = I915_READ(SOUTH_CHICKEN1);
		2319
		2320	flags \|= FDI_PHASE_SYNC_OVR(pipe);
		2321	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
		2322	flags \|= FDI_PHASE_SYNC_EN(pipe);
		2323	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
		2324	POSTING_READ(SOUTH_CHICKEN1);
		2325	}
		2326
		2327	/* The FDI link training functions for ILK/Ibexpeak. */
		2328	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2329	{
		2330	struct drm_device *dev = crtc->dev;
		2331	struct drm_i915_private *dev_priv = dev->dev_private;
		2332	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2333	int pipe = intel_crtc->pipe;
		2334	int plane = intel_crtc->plane;
		2335	u32 reg, temp, tries;
		2336
		2337	/* FDI needs bits from pipe & plane first */
		2338	assert_pipe_enabled(dev_priv, pipe);
		2339	assert_plane_enabled(dev_priv, plane);
		2340
		2341	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2342	for train result */
		2343	reg = FDI_RX_IMR(pipe);
		2344	temp = I915_READ(reg);
		2345	temp &= ~FDI_RX_SYMBOL_LOCK;
		2346	temp &= ~FDI_RX_BIT_LOCK;
		2347	I915_WRITE(reg, temp);
		2348	I915_READ(reg);
		2349	udelay(150);
		2350
		2351	/* enable CPU FDI TX and PCH FDI RX */
		2352	reg = FDI_TX_CTL(pipe);
		2353	temp = I915_READ(reg);
		2354	temp &= ~(7 << 19);
		2355	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2356	temp &= ~FDI_LINK_TRAIN_NONE;
		2357	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2358	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2359
		2360	reg = FDI_RX_CTL(pipe);
		2361	temp = I915_READ(reg);
		2362	temp &= ~FDI_LINK_TRAIN_NONE;
		2363	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2364	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2365
		2366	POSTING_READ(reg);
		2367	udelay(150);
		2368
		2369	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2370	if (HAS_PCH_IBX(dev)) {
		2371	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2372	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2373	FDI_RX_PHASE_SYNC_POINTER_EN);
		2374	}
		2375
		2376	reg = FDI_RX_IIR(pipe);
		2377	for (tries = 0; tries < 5; tries++) {
		2378	temp = I915_READ(reg);
		2379	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2380
		2381	if ((temp & FDI_RX_BIT_LOCK)) {
		2382	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2383	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2384	break;
		2385	}
		2386	}
		2387	if (tries == 5)
		2388	DRM_ERROR("FDI train 1 fail!\n");
		2389
		2390	/* Train 2 */
		2391	reg = FDI_TX_CTL(pipe);
		2392	temp = I915_READ(reg);
		2393	temp &= ~FDI_LINK_TRAIN_NONE;
		2394	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2395	I915_WRITE(reg, temp);
		2396
		2397	reg = FDI_RX_CTL(pipe);
		2398	temp = I915_READ(reg);
		2399	temp &= ~FDI_LINK_TRAIN_NONE;
		2400	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2401	I915_WRITE(reg, temp);
		2402
		2403	POSTING_READ(reg);
		2404	udelay(150);
		2405
		2406	reg = FDI_RX_IIR(pipe);
		2407	for (tries = 0; tries < 5; tries++) {
		2408	temp = I915_READ(reg);
		2409	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2410
		2411	if (temp & FDI_RX_SYMBOL_LOCK) {
		2412	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2413	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2414	break;
		2415	}
		2416	}
		2417	if (tries == 5)
		2418	DRM_ERROR("FDI train 2 fail!\n");
		2419
		2420	DRM_DEBUG_KMS("FDI train done\n");
		2421
		2422	}
		2423
2342	Serge	2424	static const int snb_b_fdi_train_param[] = {
2327	Serge	2425	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2426	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2427	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2428	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2429	};
		2430
		2431	/* The FDI link training functions for SNB/Cougarpoint. */
		2432	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2433	{
		2434	struct drm_device *dev = crtc->dev;
		2435	struct drm_i915_private *dev_priv = dev->dev_private;
		2436	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2437	int pipe = intel_crtc->pipe;
3031	serge	2438	u32 reg, temp, i, retry;
2327	Serge	2439
		2440	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2441	for train result */
		2442	reg = FDI_RX_IMR(pipe);
		2443	temp = I915_READ(reg);
		2444	temp &= ~FDI_RX_SYMBOL_LOCK;
		2445	temp &= ~FDI_RX_BIT_LOCK;
		2446	I915_WRITE(reg, temp);
		2447
		2448	POSTING_READ(reg);
		2449	udelay(150);
		2450
		2451	/* enable CPU FDI TX and PCH FDI RX */
		2452	reg = FDI_TX_CTL(pipe);
		2453	temp = I915_READ(reg);
		2454	temp &= ~(7 << 19);
		2455	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2456	temp &= ~FDI_LINK_TRAIN_NONE;
		2457	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2458	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2459	/* SNB-B */
		2460	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2461	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2462
		2463	reg = FDI_RX_CTL(pipe);
		2464	temp = I915_READ(reg);
		2465	if (HAS_PCH_CPT(dev)) {
		2466	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2467	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2468	} else {
		2469	temp &= ~FDI_LINK_TRAIN_NONE;
		2470	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2471	}
		2472	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2473
		2474	POSTING_READ(reg);
		2475	udelay(150);
		2476
		2477	if (HAS_PCH_CPT(dev))
		2478	cpt_phase_pointer_enable(dev, pipe);
		2479
2342	Serge	2480	for (i = 0; i < 4; i++) {
2327	Serge	2481	reg = FDI_TX_CTL(pipe);
		2482	temp = I915_READ(reg);
		2483	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2484	temp \|= snb_b_fdi_train_param[i];
		2485	I915_WRITE(reg, temp);
		2486
		2487	POSTING_READ(reg);
		2488	udelay(500);
		2489
3031	serge	2490	for (retry = 0; retry < 5; retry++) {
2327	Serge	2491	reg = FDI_RX_IIR(pipe);
		2492	temp = I915_READ(reg);
		2493	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2494	if (temp & FDI_RX_BIT_LOCK) {
		2495	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2496	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2497	break;
		2498	}
3031	serge	2499	udelay(50);
		2500	}
		2501	if (retry < 5)
		2502	break;
2327	Serge	2503	}
		2504	if (i == 4)
		2505	DRM_ERROR("FDI train 1 fail!\n");
		2506
		2507	/* Train 2 */
		2508	reg = FDI_TX_CTL(pipe);
		2509	temp = I915_READ(reg);
		2510	temp &= ~FDI_LINK_TRAIN_NONE;
		2511	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2512	if (IS_GEN6(dev)) {
		2513	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2514	/* SNB-B */
		2515	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2516	}
		2517	I915_WRITE(reg, temp);
		2518
		2519	reg = FDI_RX_CTL(pipe);
		2520	temp = I915_READ(reg);
		2521	if (HAS_PCH_CPT(dev)) {
		2522	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2523	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2524	} else {
		2525	temp &= ~FDI_LINK_TRAIN_NONE;
		2526	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2527	}
		2528	I915_WRITE(reg, temp);
		2529
		2530	POSTING_READ(reg);
		2531	udelay(150);
		2532
2342	Serge	2533	for (i = 0; i < 4; i++) {
2327	Serge	2534	reg = FDI_TX_CTL(pipe);
		2535	temp = I915_READ(reg);
		2536	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2537	temp \|= snb_b_fdi_train_param[i];
		2538	I915_WRITE(reg, temp);
		2539
		2540	POSTING_READ(reg);
		2541	udelay(500);
		2542
3031	serge	2543	for (retry = 0; retry < 5; retry++) {
2327	Serge	2544	reg = FDI_RX_IIR(pipe);
		2545	temp = I915_READ(reg);
		2546	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2547	if (temp & FDI_RX_SYMBOL_LOCK) {
		2548	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2549	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2550	break;
		2551	}
3031	serge	2552	udelay(50);
		2553	}
		2554	if (retry < 5)
		2555	break;
2327	Serge	2556	}
		2557	if (i == 4)
		2558	DRM_ERROR("FDI train 2 fail!\n");
		2559
		2560	DRM_DEBUG_KMS("FDI train done.\n");
		2561	}
		2562
		2563	/* Manual link training for Ivy Bridge A0 parts */
		2564	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2565	{
		2566	struct drm_device *dev = crtc->dev;
		2567	struct drm_i915_private *dev_priv = dev->dev_private;
		2568	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2569	int pipe = intel_crtc->pipe;
		2570	u32 reg, temp, i;
		2571
		2572	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2573	for train result */
		2574	reg = FDI_RX_IMR(pipe);
		2575	temp = I915_READ(reg);
		2576	temp &= ~FDI_RX_SYMBOL_LOCK;
		2577	temp &= ~FDI_RX_BIT_LOCK;
		2578	I915_WRITE(reg, temp);
		2579
		2580	POSTING_READ(reg);
		2581	udelay(150);
		2582
		2583	/* enable CPU FDI TX and PCH FDI RX */
		2584	reg = FDI_TX_CTL(pipe);
		2585	temp = I915_READ(reg);
		2586	temp &= ~(7 << 19);
		2587	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2588	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2589	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2590	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2591	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2342	Serge	2592	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2593	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2594
		2595	reg = FDI_RX_CTL(pipe);
		2596	temp = I915_READ(reg);
		2597	temp &= ~FDI_LINK_TRAIN_AUTO;
		2598	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2599	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342	Serge	2600	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2601	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2602
		2603	POSTING_READ(reg);
		2604	udelay(150);
		2605
		2606	if (HAS_PCH_CPT(dev))
		2607	cpt_phase_pointer_enable(dev, pipe);
		2608
2342	Serge	2609	for (i = 0; i < 4; i++) {
2327	Serge	2610	reg = FDI_TX_CTL(pipe);
		2611	temp = I915_READ(reg);
		2612	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2613	temp \|= snb_b_fdi_train_param[i];
		2614	I915_WRITE(reg, temp);
		2615
		2616	POSTING_READ(reg);
		2617	udelay(500);
		2618
		2619	reg = FDI_RX_IIR(pipe);
		2620	temp = I915_READ(reg);
		2621	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2622
		2623	if (temp & FDI_RX_BIT_LOCK \|\|
		2624	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2625	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2626	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2627	break;
		2628	}
		2629	}
		2630	if (i == 4)
		2631	DRM_ERROR("FDI train 1 fail!\n");
		2632
		2633	/* Train 2 */
		2634	reg = FDI_TX_CTL(pipe);
		2635	temp = I915_READ(reg);
		2636	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2637	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2638	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2639	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2640	I915_WRITE(reg, temp);
		2641
		2642	reg = FDI_RX_CTL(pipe);
		2643	temp = I915_READ(reg);
		2644	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2645	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2646	I915_WRITE(reg, temp);
		2647
		2648	POSTING_READ(reg);
		2649	udelay(150);
		2650
2342	Serge	2651	for (i = 0; i < 4; i++) {
2327	Serge	2652	reg = FDI_TX_CTL(pipe);
		2653	temp = I915_READ(reg);
		2654	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2655	temp \|= snb_b_fdi_train_param[i];
		2656	I915_WRITE(reg, temp);
		2657
		2658	POSTING_READ(reg);
		2659	udelay(500);
		2660
		2661	reg = FDI_RX_IIR(pipe);
		2662	temp = I915_READ(reg);
		2663	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2664
		2665	if (temp & FDI_RX_SYMBOL_LOCK) {
		2666	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2667	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2668	break;
		2669	}
		2670	}
		2671	if (i == 4)
		2672	DRM_ERROR("FDI train 2 fail!\n");
		2673
		2674	DRM_DEBUG_KMS("FDI train done.\n");
		2675	}
		2676
3031	serge	2677	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	2678	{
3031	serge	2679	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	2680	struct drm_i915_private *dev_priv = dev->dev_private;
		2681	int pipe = intel_crtc->pipe;
		2682	u32 reg, temp;
		2683
		2684	/* Write the TU size bits so error detection works */
		2685	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		2686	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		2687
		2688	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2689	reg = FDI_RX_CTL(pipe);
		2690	temp = I915_READ(reg);
		2691	temp &= ~((0x7 << 19) \| (0x7 << 16));
		2692	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2693	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2694	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2695
		2696	POSTING_READ(reg);
		2697	udelay(200);
		2698
		2699	/* Switch from Rawclk to PCDclk */
		2700	temp = I915_READ(reg);
		2701	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2702
		2703	POSTING_READ(reg);
		2704	udelay(200);
		2705
3031	serge	2706	/* On Haswell, the PLL configuration for ports and pipes is handled
		2707	* separately, as part of DDI setup */
		2708	if (!IS_HASWELL(dev)) {
2327	Serge	2709	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2710	reg = FDI_TX_CTL(pipe);
		2711	temp = I915_READ(reg);
		2712	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2713	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2714
		2715	POSTING_READ(reg);
		2716	udelay(100);
		2717	}
3031	serge	2718	}
2327	Serge	2719	}
		2720
3031	serge	2721	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		2722	{
		2723	struct drm_device *dev = intel_crtc->base.dev;
		2724	struct drm_i915_private *dev_priv = dev->dev_private;
		2725	int pipe = intel_crtc->pipe;
		2726	u32 reg, temp;
		2727
		2728	/* Switch from PCDclk to Rawclk */
		2729	reg = FDI_RX_CTL(pipe);
		2730	temp = I915_READ(reg);
		2731	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		2732
		2733	/* Disable CPU FDI TX PLL */
		2734	reg = FDI_TX_CTL(pipe);
		2735	temp = I915_READ(reg);
		2736	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		2737
		2738	POSTING_READ(reg);
		2739	udelay(100);
		2740
		2741	reg = FDI_RX_CTL(pipe);
		2742	temp = I915_READ(reg);
		2743	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		2744
		2745	/* Wait for the clocks to turn off. */
		2746	POSTING_READ(reg);
		2747	udelay(100);
		2748	}
		2749
2327	Serge	2750	static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
		2751	{
		2752	struct drm_i915_private *dev_priv = dev->dev_private;
		2753	u32 flags = I915_READ(SOUTH_CHICKEN1);
		2754
		2755	flags &= ~(FDI_PHASE_SYNC_EN(pipe));
		2756	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
		2757	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
		2758	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
		2759	POSTING_READ(SOUTH_CHICKEN1);
		2760	}
		2761	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2762	{
		2763	struct drm_device *dev = crtc->dev;
		2764	struct drm_i915_private *dev_priv = dev->dev_private;
		2765	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2766	int pipe = intel_crtc->pipe;
		2767	u32 reg, temp;
		2768
		2769	/* disable CPU FDI tx and PCH FDI rx */
		2770	reg = FDI_TX_CTL(pipe);
		2771	temp = I915_READ(reg);
		2772	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2773	POSTING_READ(reg);
		2774
		2775	reg = FDI_RX_CTL(pipe);
		2776	temp = I915_READ(reg);
		2777	temp &= ~(0x7 << 16);
		2778	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2779	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2780
		2781	POSTING_READ(reg);
		2782	udelay(100);
		2783
		2784	/* Ironlake workaround, disable clock pointer after downing FDI */
		2785	if (HAS_PCH_IBX(dev)) {
		2786	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2787	I915_WRITE(FDI_RX_CHICKEN(pipe),
		2788	I915_READ(FDI_RX_CHICKEN(pipe) &
		2789	~FDI_RX_PHASE_SYNC_POINTER_EN));
		2790	} else if (HAS_PCH_CPT(dev)) {
		2791	cpt_phase_pointer_disable(dev, pipe);
		2792	}
		2793
		2794	/* still set train pattern 1 */
		2795	reg = FDI_TX_CTL(pipe);
		2796	temp = I915_READ(reg);
		2797	temp &= ~FDI_LINK_TRAIN_NONE;
		2798	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2799	I915_WRITE(reg, temp);
		2800
		2801	reg = FDI_RX_CTL(pipe);
		2802	temp = I915_READ(reg);
		2803	if (HAS_PCH_CPT(dev)) {
		2804	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2805	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2806	} else {
		2807	temp &= ~FDI_LINK_TRAIN_NONE;
		2808	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2809	}
		2810	/* BPC in FDI rx is consistent with that in PIPECONF */
		2811	temp &= ~(0x07 << 16);
		2812	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2813	I915_WRITE(reg, temp);
		2814
		2815	POSTING_READ(reg);
		2816	udelay(100);
		2817	}
		2818
3031	serge	2819	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2327	Serge	2820	{
3031	serge	2821	struct drm_device *dev = crtc->dev;
2327	Serge	2822	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2823	unsigned long flags;
		2824	bool pending;
2327	Serge	2825
3031	serge	2826	if (atomic_read(&dev_priv->mm.wedged))
		2827	return false;
2327	Serge	2828
3031	serge	2829	spin_lock_irqsave(&dev->event_lock, flags);
		2830	pending = to_intel_crtc(crtc)->unpin_work != NULL;
		2831	spin_unlock_irqrestore(&dev->event_lock, flags);
		2832
		2833	return pending;
2327	Serge	2834	}
		2835
3031	serge	2836	#if 0
2327	Serge	2837	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2838	{
3031	serge	2839	struct drm_device *dev = crtc->dev;
		2840	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2841
		2842	if (crtc->fb == NULL)
		2843	return;
		2844
2360	Serge	2845	wait_event(dev_priv->pending_flip_queue,
3031	serge	2846	!intel_crtc_has_pending_flip(crtc));
		2847
		2848	mutex_lock(&dev->struct_mutex);
		2849	intel_finish_fb(crtc->fb);
		2850	mutex_unlock(&dev->struct_mutex);
2327	Serge	2851	}
3031	serge	2852	#endif
2327	Serge	2853
		2854	static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
		2855	{
		2856	struct drm_device *dev = crtc->dev;
3031	serge	2857	struct intel_encoder *intel_encoder;
2327	Serge	2858
		2859	/*
		2860	* If there's a non-PCH eDP on this crtc, it must be DP_A, and that
		2861	* must be driven by its own crtc; no sharing is possible.
		2862	*/
3031	serge	2863	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2327	Serge	2864
3031	serge	2865	/* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
		2866	* CPU handles all others */
		2867	if (IS_HASWELL(dev)) {
		2868	/* It is still unclear how this will work on PPT, so throw up a warning */
		2869	WARN_ON(!HAS_PCH_LPT(dev));
		2870
		2871	if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
		2872	DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
		2873	return true;
		2874	} else {
		2875	DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
		2876	intel_encoder->type);
		2877	return false;
		2878	}
		2879	}
		2880
		2881	switch (intel_encoder->type) {
2327	Serge	2882	case INTEL_OUTPUT_EDP:
3031	serge	2883	if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2327	Serge	2884	return false;
		2885	continue;
		2886	}
		2887	}
		2888
		2889	return true;
		2890	}
		2891
3031	serge	2892	/* Program iCLKIP clock to the desired frequency */
		2893	static void lpt_program_iclkip(struct drm_crtc *crtc)
		2894	{
		2895	struct drm_device *dev = crtc->dev;
		2896	struct drm_i915_private *dev_priv = dev->dev_private;
		2897	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		2898	u32 temp;
		2899
		2900	/* It is necessary to ungate the pixclk gate prior to programming
		2901	* the divisors, and gate it back when it is done.
		2902	*/
		2903	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		2904
		2905	/* Disable SSCCTL */
		2906	intel_sbi_write(dev_priv, SBI_SSCCTL6,
		2907	intel_sbi_read(dev_priv, SBI_SSCCTL6) \|
		2908	SBI_SSCCTL_DISABLE);
		2909
		2910	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
		2911	if (crtc->mode.clock == 20000) {
		2912	auxdiv = 1;
		2913	divsel = 0x41;
		2914	phaseinc = 0x20;
		2915	} else {
		2916	/* The iCLK virtual clock root frequency is in MHz,
		2917	* but the crtc->mode.clock in in KHz. To get the divisors,
		2918	* it is necessary to divide one by another, so we
		2919	* convert the virtual clock precision to KHz here for higher
		2920	* precision.
		2921	*/
		2922	u32 iclk_virtual_root_freq = 172800 * 1000;
		2923	u32 iclk_pi_range = 64;
		2924	u32 desired_divisor, msb_divisor_value, pi_value;
		2925
		2926	desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		2927	msb_divisor_value = desired_divisor / iclk_pi_range;
		2928	pi_value = desired_divisor % iclk_pi_range;
		2929
		2930	auxdiv = 0;
		2931	divsel = msb_divisor_value - 2;
		2932	phaseinc = pi_value;
		2933	}
		2934
		2935	/* This should not happen with any sane values */
		2936	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		2937	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		2938	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		2939	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		2940
		2941	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
		2942	crtc->mode.clock,
		2943	auxdiv,
		2944	divsel,
		2945	phasedir,
		2946	phaseinc);
		2947
		2948	/* Program SSCDIVINTPHASE6 */
		2949	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
		2950	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		2951	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		2952	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		2953	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		2954	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		2955	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
		2956
		2957	intel_sbi_write(dev_priv,
		2958	SBI_SSCDIVINTPHASE6,
		2959	temp);
		2960
		2961	/* Program SSCAUXDIV */
		2962	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
		2963	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		2964	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
		2965	intel_sbi_write(dev_priv,
		2966	SBI_SSCAUXDIV6,
		2967	temp);
		2968
		2969
		2970	/* Enable modulator and associated divider */
		2971	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
		2972	temp &= ~SBI_SSCCTL_DISABLE;
		2973	intel_sbi_write(dev_priv,
		2974	SBI_SSCCTL6,
		2975	temp);
		2976
		2977	/* Wait for initialization time */
		2978	udelay(24);
		2979
		2980	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
		2981	}
		2982
2327	Serge	2983	/*
		2984	* Enable PCH resources required for PCH ports:
		2985	* - PCH PLLs
		2986	* - FDI training & RX/TX
		2987	* - update transcoder timings
		2988	* - DP transcoding bits
		2989	* - transcoder
		2990	*/
		2991	static void ironlake_pch_enable(struct drm_crtc *crtc)
		2992	{
		2993	struct drm_device *dev = crtc->dev;
		2994	struct drm_i915_private *dev_priv = dev->dev_private;
		2995	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2996	int pipe = intel_crtc->pipe;
3031	serge	2997	u32 reg, temp;
2327	Serge	2998
3031	serge	2999	assert_transcoder_disabled(dev_priv, pipe);
		3000
2327	Serge	3001	/* For PCH output, training FDI link */
		3002	dev_priv->display.fdi_link_train(crtc);
		3003
3031	serge	3004	intel_enable_pch_pll(intel_crtc);
2327	Serge	3005
3031	serge	3006	if (HAS_PCH_LPT(dev)) {
		3007	DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
		3008	lpt_program_iclkip(crtc);
		3009	} else if (HAS_PCH_CPT(dev)) {
		3010	u32 sel;
2342	Serge	3011
2327	Serge	3012	temp = I915_READ(PCH_DPLL_SEL);
3031	serge	3013	switch (pipe) {
		3014	default:
		3015	case 0:
		3016	temp \|= TRANSA_DPLL_ENABLE;
		3017	sel = TRANSA_DPLLB_SEL;
		3018	break;
		3019	case 1:
		3020	temp \|= TRANSB_DPLL_ENABLE;
		3021	sel = TRANSB_DPLLB_SEL;
		3022	break;
		3023	case 2:
		3024	temp \|= TRANSC_DPLL_ENABLE;
		3025	sel = TRANSC_DPLLB_SEL;
		3026	break;
2342	Serge	3027	}
3031	serge	3028	if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
		3029	temp \|= sel;
		3030	else
		3031	temp &= ~sel;
2327	Serge	3032	I915_WRITE(PCH_DPLL_SEL, temp);
		3033	}
		3034
		3035	/* set transcoder timing, panel must allow it */
		3036	assert_panel_unlocked(dev_priv, pipe);
		3037	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
		3038	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
		3039	I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
		3040
		3041	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
		3042	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
		3043	I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3031	serge	3044	I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2327	Serge	3045
3031	serge	3046	if (!IS_HASWELL(dev))
2327	Serge	3047	intel_fdi_normal_train(crtc);
		3048
		3049	/* For PCH DP, enable TRANS_DP_CTL */
		3050	if (HAS_PCH_CPT(dev) &&
2342	Serge	3051	(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		3052	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2327	Serge	3053	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
		3054	reg = TRANS_DP_CTL(pipe);
		3055	temp = I915_READ(reg);
		3056	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		3057	TRANS_DP_SYNC_MASK \|
		3058	TRANS_DP_BPC_MASK);
		3059	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		3060	TRANS_DP_ENH_FRAMING);
		3061	temp \|= bpc << 9; /* same format but at 11:9 */
		3062
		3063	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		3064	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		3065	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		3066	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		3067
		3068	switch (intel_trans_dp_port_sel(crtc)) {
		3069	case PCH_DP_B:
		3070	temp \|= TRANS_DP_PORT_SEL_B;
		3071	break;
		3072	case PCH_DP_C:
		3073	temp \|= TRANS_DP_PORT_SEL_C;
		3074	break;
		3075	case PCH_DP_D:
		3076	temp \|= TRANS_DP_PORT_SEL_D;
		3077	break;
		3078	default:
		3079	DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
		3080	temp \|= TRANS_DP_PORT_SEL_B;
		3081	break;
		3082	}
		3083
		3084	I915_WRITE(reg, temp);
		3085	}
		3086
		3087	intel_enable_transcoder(dev_priv, pipe);
		3088	}
		3089
3031	serge	3090	static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
		3091	{
		3092	struct intel_pch_pll *pll = intel_crtc->pch_pll;
		3093
		3094	if (pll == NULL)
		3095	return;
		3096
		3097	if (pll->refcount == 0) {
		3098	WARN(1, "bad PCH PLL refcount\n");
		3099	return;
		3100	}
		3101
		3102	--pll->refcount;
		3103	intel_crtc->pch_pll = NULL;
		3104	}
		3105
		3106	static struct intel_pch_pll intel_get_pch_pll(struct intel_crtc intel_crtc, u32 dpll, u32 fp)
		3107	{
		3108	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		3109	struct intel_pch_pll *pll;
		3110	int i;
		3111
		3112	pll = intel_crtc->pch_pll;
		3113	if (pll) {
		3114	DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
		3115	intel_crtc->base.base.id, pll->pll_reg);
		3116	goto prepare;
		3117	}
		3118
		3119	if (HAS_PCH_IBX(dev_priv->dev)) {
		3120	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
		3121	i = intel_crtc->pipe;
		3122	pll = &dev_priv->pch_plls[i];
		3123
		3124	DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
		3125	intel_crtc->base.base.id, pll->pll_reg);
		3126
		3127	goto found;
		3128	}
		3129
		3130	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		3131	pll = &dev_priv->pch_plls[i];
		3132
		3133	/* Only want to check enabled timings first */
		3134	if (pll->refcount == 0)
		3135	continue;
		3136
		3137	if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
		3138	fp == I915_READ(pll->fp0_reg)) {
		3139	DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
		3140	intel_crtc->base.base.id,
		3141	pll->pll_reg, pll->refcount, pll->active);
		3142
		3143	goto found;
		3144	}
		3145	}
		3146
		3147	/* Ok no matching timings, maybe there's a free one? */
		3148	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		3149	pll = &dev_priv->pch_plls[i];
		3150	if (pll->refcount == 0) {
		3151	DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
		3152	intel_crtc->base.base.id, pll->pll_reg);
		3153	goto found;
		3154	}
		3155	}
		3156
		3157	return NULL;
		3158
		3159	found:
		3160	intel_crtc->pch_pll = pll;
		3161	pll->refcount++;
		3162	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
		3163	prepare: /* separate function? */
		3164	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
		3165
		3166	/* Wait for the clocks to stabilize before rewriting the regs */
		3167	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
		3168	POSTING_READ(pll->pll_reg);
		3169	udelay(150);
		3170
		3171	I915_WRITE(pll->fp0_reg, fp);
		3172	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
		3173	pll->on = false;
		3174	return pll;
		3175	}
		3176
2342	Serge	3177	void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
		3178	{
		3179	struct drm_i915_private *dev_priv = dev->dev_private;
		3180	int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
		3181	u32 temp;
		3182
		3183	temp = I915_READ(dslreg);
		3184	udelay(500);
		3185	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		3186	/* Without this, mode sets may fail silently on FDI */
		3187	I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
		3188	udelay(250);
		3189	I915_WRITE(tc2reg, 0);
		3190	if (wait_for(I915_READ(dslreg) != temp, 5))
		3191	DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
		3192	}
		3193	}
		3194
2327	Serge	3195	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		3196	{
		3197	struct drm_device *dev = crtc->dev;
		3198	struct drm_i915_private *dev_priv = dev->dev_private;
		3199	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3200	struct intel_encoder *encoder;
2327	Serge	3201	int pipe = intel_crtc->pipe;
		3202	int plane = intel_crtc->plane;
		3203	u32 temp;
		3204	bool is_pch_port;
		3205
3031	serge	3206	WARN_ON(!crtc->enabled);
		3207
2327	Serge	3208	if (intel_crtc->active)
		3209	return;
		3210
		3211	intel_crtc->active = true;
		3212	intel_update_watermarks(dev);
		3213
		3214	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		3215	temp = I915_READ(PCH_LVDS);
		3216	if ((temp & LVDS_PORT_EN) == 0)
		3217	I915_WRITE(PCH_LVDS, temp \| LVDS_PORT_EN);
		3218	}
		3219
		3220	is_pch_port = intel_crtc_driving_pch(crtc);
		3221
3031	serge	3222	if (is_pch_port) {
		3223	ironlake_fdi_pll_enable(intel_crtc);
		3224	} else {
		3225	assert_fdi_tx_disabled(dev_priv, pipe);
		3226	assert_fdi_rx_disabled(dev_priv, pipe);
		3227	}
2327	Serge	3228
3031	serge	3229	for_each_encoder_on_crtc(dev, crtc, encoder)
		3230	if (encoder->pre_enable)
		3231	encoder->pre_enable(encoder);
		3232
2327	Serge	3233	/* Enable panel fitting for LVDS */
		3234	if (dev_priv->pch_pf_size &&
		3235	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\| HAS_eDP)) {
		3236	/* Force use of hard-coded filter coefficients
		3237	* as some pre-programmed values are broken,
		3238	* e.g. x201.
		3239	*/
		3240	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		3241	I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		3242	I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
		3243	}
		3244
		3245	/*
		3246	* On ILK+ LUT must be loaded before the pipe is running but with
		3247	* clocks enabled
		3248	*/
		3249	intel_crtc_load_lut(crtc);
		3250
		3251	intel_enable_pipe(dev_priv, pipe, is_pch_port);
		3252	intel_enable_plane(dev_priv, plane, pipe);
		3253
		3254	if (is_pch_port)
		3255	ironlake_pch_enable(crtc);
		3256
		3257	mutex_lock(&dev->struct_mutex);
		3258	intel_update_fbc(dev);
		3259	mutex_unlock(&dev->struct_mutex);
		3260
		3261	// intel_crtc_update_cursor(crtc, true);
3031	serge	3262
		3263	for_each_encoder_on_crtc(dev, crtc, encoder)
		3264	encoder->enable(encoder);
		3265
		3266	if (HAS_PCH_CPT(dev))
		3267	intel_cpt_verify_modeset(dev, intel_crtc->pipe);
		3268
		3269	/*
		3270	* There seems to be a race in PCH platform hw (at least on some
		3271	* outputs) where an enabled pipe still completes any pageflip right
		3272	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3273	* as the first vblank happend, everything works as expected. Hence just
		3274	* wait for one vblank before returning to avoid strange things
		3275	* happening.
		3276	*/
		3277	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	3278	}
		3279
		3280	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		3281	{
		3282	struct drm_device *dev = crtc->dev;
		3283	struct drm_i915_private *dev_priv = dev->dev_private;
		3284	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3285	struct intel_encoder *encoder;
2327	Serge	3286	int pipe = intel_crtc->pipe;
		3287	int plane = intel_crtc->plane;
		3288	u32 reg, temp;
		3289
3031	serge	3290
2327	Serge	3291	if (!intel_crtc->active)
		3292	return;
		3293
3031	serge	3294	for_each_encoder_on_crtc(dev, crtc, encoder)
		3295	encoder->disable(encoder);
2336	Serge	3296
3031	serge	3297	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3298	// drm_vblank_off(dev, pipe);
		3299	// intel_crtc_update_cursor(crtc, false);
		3300
		3301	intel_disable_plane(dev_priv, plane, pipe);
		3302
		3303	if (dev_priv->cfb_plane == plane)
		3304	intel_disable_fbc(dev);
		3305
		3306	intel_disable_pipe(dev_priv, pipe);
		3307
		3308	/* Disable PF */
		3309	I915_WRITE(PF_CTL(pipe), 0);
		3310	I915_WRITE(PF_WIN_SZ(pipe), 0);
		3311
3031	serge	3312	for_each_encoder_on_crtc(dev, crtc, encoder)
		3313	if (encoder->post_disable)
		3314	encoder->post_disable(encoder);
		3315
2327	Serge	3316	ironlake_fdi_disable(crtc);
		3317
		3318	intel_disable_transcoder(dev_priv, pipe);
		3319
		3320	if (HAS_PCH_CPT(dev)) {
		3321	/* disable TRANS_DP_CTL */
		3322	reg = TRANS_DP_CTL(pipe);
		3323	temp = I915_READ(reg);
		3324	temp &= ~(TRANS_DP_OUTPUT_ENABLE \| TRANS_DP_PORT_SEL_MASK);
		3325	temp \|= TRANS_DP_PORT_SEL_NONE;
		3326	I915_WRITE(reg, temp);
		3327
		3328	/* disable DPLL_SEL */
		3329	temp = I915_READ(PCH_DPLL_SEL);
		3330	switch (pipe) {
		3331	case 0:
2342	Serge	3332	temp &= ~(TRANSA_DPLL_ENABLE \| TRANSA_DPLLB_SEL);
2327	Serge	3333	break;
		3334	case 1:
		3335	temp &= ~(TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
		3336	break;
		3337	case 2:
2342	Serge	3338	/* C shares PLL A or B */
2327	Serge	3339	temp &= ~(TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL);
		3340	break;
		3341	default:
		3342	BUG(); /* wtf */
		3343	}
		3344	I915_WRITE(PCH_DPLL_SEL, temp);
		3345	}
		3346
		3347	/* disable PCH DPLL */
3031	serge	3348	intel_disable_pch_pll(intel_crtc);
2327	Serge	3349
3031	serge	3350	ironlake_fdi_pll_disable(intel_crtc);
2327	Serge	3351
		3352	intel_crtc->active = false;
		3353	intel_update_watermarks(dev);
		3354
		3355	mutex_lock(&dev->struct_mutex);
		3356	intel_update_fbc(dev);
		3357	mutex_unlock(&dev->struct_mutex);
		3358	}
		3359
3031	serge	3360	static void ironlake_crtc_off(struct drm_crtc *crtc)
2327	Serge	3361	{
		3362	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3363	intel_put_pch_pll(intel_crtc);
2327	Serge	3364	}
		3365
		3366	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3367	{
		3368	if (!enable && intel_crtc->overlay) {
		3369	struct drm_device *dev = intel_crtc->base.dev;
		3370	struct drm_i915_private *dev_priv = dev->dev_private;
		3371
		3372	mutex_lock(&dev->struct_mutex);
		3373	dev_priv->mm.interruptible = false;
		3374	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3375	dev_priv->mm.interruptible = true;
		3376	mutex_unlock(&dev->struct_mutex);
		3377	}
		3378
		3379	/* Let userspace switch the overlay on again. In most cases userspace
		3380	* has to recompute where to put it anyway.
		3381	*/
		3382	}
		3383
		3384	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3385	{
		3386	struct drm_device *dev = crtc->dev;
		3387	struct drm_i915_private *dev_priv = dev->dev_private;
		3388	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3389	struct intel_encoder *encoder;
2327	Serge	3390	int pipe = intel_crtc->pipe;
		3391	int plane = intel_crtc->plane;
		3392
3031	serge	3393	WARN_ON(!crtc->enabled);
		3394
2327	Serge	3395	if (intel_crtc->active)
		3396	return;
		3397
		3398	intel_crtc->active = true;
		3399	intel_update_watermarks(dev);
		3400
		3401	intel_enable_pll(dev_priv, pipe);
		3402	intel_enable_pipe(dev_priv, pipe, false);
		3403	intel_enable_plane(dev_priv, plane, pipe);
		3404
		3405	intel_crtc_load_lut(crtc);
		3406	intel_update_fbc(dev);
		3407
		3408	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3409	intel_crtc_dpms_overlay(intel_crtc, true);
		3410	// intel_crtc_update_cursor(crtc, true);
3031	serge	3411
		3412	for_each_encoder_on_crtc(dev, crtc, encoder)
		3413	encoder->enable(encoder);
2327	Serge	3414	}
		3415
		3416	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3417	{
		3418	struct drm_device *dev = crtc->dev;
		3419	struct drm_i915_private *dev_priv = dev->dev_private;
		3420	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3421	struct intel_encoder *encoder;
2327	Serge	3422	int pipe = intel_crtc->pipe;
		3423	int plane = intel_crtc->plane;
		3424
3031	serge	3425
2327	Serge	3426	if (!intel_crtc->active)
		3427	return;
		3428
3031	serge	3429	for_each_encoder_on_crtc(dev, crtc, encoder)
		3430	encoder->disable(encoder);
		3431
2327	Serge	3432	/* Give the overlay scaler a chance to disable if it's on this pipe */
3031	serge	3433	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3434	// drm_vblank_off(dev, pipe);
		3435	intel_crtc_dpms_overlay(intel_crtc, false);
		3436	// intel_crtc_update_cursor(crtc, false);
		3437
		3438	if (dev_priv->cfb_plane == plane)
		3439	intel_disable_fbc(dev);
		3440
		3441	intel_disable_plane(dev_priv, plane, pipe);
		3442	intel_disable_pipe(dev_priv, pipe);
		3443	intel_disable_pll(dev_priv, pipe);
		3444
		3445	intel_crtc->active = false;
		3446	intel_update_fbc(dev);
		3447	intel_update_watermarks(dev);
		3448	}
		3449
3031	serge	3450	static void i9xx_crtc_off(struct drm_crtc *crtc)
2327	Serge	3451	{
		3452	}
		3453
3031	serge	3454	static void intel_crtc_update_sarea(struct drm_crtc *crtc,
		3455	bool enabled)
2330	Serge	3456	{
		3457	struct drm_device *dev = crtc->dev;
		3458	struct drm_i915_master_private *master_priv;
		3459	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3460	int pipe = intel_crtc->pipe;
2327	Serge	3461
		3462
2340	Serge	3463	#if 0
2330	Serge	3464	if (!dev->primary->master)
		3465	return;
2327	Serge	3466
2330	Serge	3467	master_priv = dev->primary->master->driver_priv;
		3468	if (!master_priv->sarea_priv)
		3469	return;
2327	Serge	3470
2330	Serge	3471	switch (pipe) {
		3472	case 0:
		3473	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3474	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3475	break;
		3476	case 1:
		3477	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3478	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3479	break;
		3480	default:
		3481	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3482	break;
		3483	}
2340	Serge	3484	#endif
		3485
2330	Serge	3486	}
2327	Serge	3487
3031	serge	3488	/**
		3489	* Sets the power management mode of the pipe and plane.
		3490	*/
		3491	void intel_crtc_update_dpms(struct drm_crtc *crtc)
		3492	{
		3493	struct drm_device *dev = crtc->dev;
		3494	struct drm_i915_private *dev_priv = dev->dev_private;
		3495	struct intel_encoder *intel_encoder;
		3496	bool enable = false;
		3497
		3498	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		3499	enable \|= intel_encoder->connectors_active;
		3500
		3501	if (enable)
		3502	dev_priv->display.crtc_enable(crtc);
		3503	else
		3504	dev_priv->display.crtc_disable(crtc);
		3505
		3506	intel_crtc_update_sarea(crtc, enable);
		3507	}
		3508
		3509	static void intel_crtc_noop(struct drm_crtc *crtc)
		3510	{
		3511	}
		3512
2330	Serge	3513	static void intel_crtc_disable(struct drm_crtc *crtc)
		3514	{
		3515	struct drm_device *dev = crtc->dev;
3031	serge	3516	struct drm_connector *connector;
		3517	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	3518
3031	serge	3519	/* crtc should still be enabled when we disable it. */
		3520	WARN_ON(!crtc->enabled);
2327	Serge	3521
3031	serge	3522	dev_priv->display.crtc_disable(crtc);
		3523	intel_crtc_update_sarea(crtc, false);
		3524	dev_priv->display.off(crtc);
		3525
		3526	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
		3527	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
		3528
		3529	// if (crtc->fb) {
		3530	// mutex_lock(&dev->struct_mutex);
		3531	// intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
		3532	// mutex_unlock(&dev->struct_mutex);
		3533	// crtc->fb = NULL;
		3534	// }
		3535
		3536	/* Update computed state. */
		3537	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		3538	if (!connector->encoder \|\| !connector->encoder->crtc)
		3539	continue;
		3540
		3541	if (connector->encoder->crtc != crtc)
		3542	continue;
		3543
		3544	connector->dpms = DRM_MODE_DPMS_OFF;
		3545	to_intel_encoder(connector->encoder)->connectors_active = false;
2330	Serge	3546	}
		3547	}
2327	Serge	3548
3031	serge	3549	void intel_modeset_disable(struct drm_device *dev)
2330	Serge	3550	{
3031	serge	3551	struct drm_crtc *crtc;
		3552
		3553	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		3554	if (crtc->enabled)
		3555	intel_crtc_disable(crtc);
		3556	}
2330	Serge	3557	}
2327	Serge	3558
3031	serge	3559	void intel_encoder_noop(struct drm_encoder *encoder)
2330	Serge	3560	{
		3561	}
2327	Serge	3562
3031	serge	3563	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3564	{
3031	serge	3565	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3566
		3567	drm_encoder_cleanup(encoder);
		3568	kfree(intel_encoder);
2330	Serge	3569	}
2327	Serge	3570
3031	serge	3571	/* Simple dpms helper for encodres with just one connector, no cloning and only
		3572	* one kind of off state. It clamps all !ON modes to fully OFF and changes the
		3573	* state of the entire output pipe. */
		3574	void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
2330	Serge	3575	{
3031	serge	3576	if (mode == DRM_MODE_DPMS_ON) {
		3577	encoder->connectors_active = true;
		3578
		3579	intel_crtc_update_dpms(encoder->base.crtc);
		3580	} else {
		3581	encoder->connectors_active = false;
		3582
		3583	intel_crtc_update_dpms(encoder->base.crtc);
		3584	}
2330	Serge	3585	}
2327	Serge	3586
3031	serge	3587	/* Cross check the actual hw state with our own modeset state tracking (and it's
		3588	* internal consistency). */
		3589	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	3590	{
3031	serge	3591	if (connector->get_hw_state(connector)) {
		3592	struct intel_encoder *encoder = connector->encoder;
		3593	struct drm_crtc *crtc;
		3594	bool encoder_enabled;
		3595	enum pipe pipe;
		3596
		3597	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		3598	connector->base.base.id,
		3599	drm_get_connector_name(&connector->base));
		3600
		3601	WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		3602	"wrong connector dpms state\n");
		3603	WARN(connector->base.encoder != &encoder->base,
		3604	"active connector not linked to encoder\n");
		3605	WARN(!encoder->connectors_active,
		3606	"encoder->connectors_active not set\n");
		3607
		3608	encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		3609	WARN(!encoder_enabled, "encoder not enabled\n");
		3610	if (WARN_ON(!encoder->base.crtc))
		3611	return;
		3612
		3613	crtc = encoder->base.crtc;
		3614
		3615	WARN(!crtc->enabled, "crtc not enabled\n");
		3616	WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		3617	WARN(pipe != to_intel_crtc(crtc)->pipe,
		3618	"encoder active on the wrong pipe\n");
		3619	}
2330	Serge	3620	}
2327	Serge	3621
3031	serge	3622	/* Even simpler default implementation, if there's really no special case to
		3623	* consider. */
		3624	void intel_connector_dpms(struct drm_connector *connector, int mode)
2330	Serge	3625	{
3031	serge	3626	struct intel_encoder *encoder = intel_attached_encoder(connector);
2342	Serge	3627
3031	serge	3628	/* All the simple cases only support two dpms states. */
		3629	if (mode != DRM_MODE_DPMS_ON)
		3630	mode = DRM_MODE_DPMS_OFF;
2342	Serge	3631
3031	serge	3632	if (mode == connector->dpms)
		3633	return;
		3634
		3635	connector->dpms = mode;
		3636
		3637	/* Only need to change hw state when actually enabled */
		3638	if (encoder->base.crtc)
		3639	intel_encoder_dpms(encoder, mode);
		3640	else
		3641	WARN_ON(encoder->connectors_active != false);
		3642
		3643	intel_modeset_check_state(connector->dev);
2330	Serge	3644	}
2327	Serge	3645
3031	serge	3646	/* Simple connector->get_hw_state implementation for encoders that support only
		3647	* one connector and no cloning and hence the encoder state determines the state
		3648	* of the connector. */
		3649	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	3650	{
3031	serge	3651	enum pipe pipe = 0;
		3652	struct intel_encoder *encoder = connector->encoder;
2330	Serge	3653
3031	serge	3654	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	3655	}
		3656
		3657	static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3031	serge	3658	const struct drm_display_mode *mode,
2330	Serge	3659	struct drm_display_mode *adjusted_mode)
		3660	{
		3661	struct drm_device *dev = crtc->dev;
		3662
		3663	if (HAS_PCH_SPLIT(dev)) {
		3664	/* FDI link clock is fixed at 2.7G */
		3665	if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
		3666	return false;
		3667	}
		3668
3031	serge	3669	/* All interlaced capable intel hw wants timings in frames. Note though
		3670	* that intel_lvds_mode_fixup does some funny tricks with the crtc
		3671	* timings, so we need to be careful not to clobber these.*/
		3672	if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
2330	Serge	3673	drm_mode_set_crtcinfo(adjusted_mode, 0);
		3674
3031	serge	3675	/* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
		3676	* with a hsync front porch of 0.
		3677	*/
		3678	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
		3679	adjusted_mode->hsync_start == adjusted_mode->hdisplay)
		3680	return false;
		3681
2330	Serge	3682	return true;
		3683	}
		3684
3031	serge	3685	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		3686	{
		3687	return 400000; /* FIXME */
		3688	}
		3689
2327	Serge	3690	static int i945_get_display_clock_speed(struct drm_device *dev)
		3691	{
		3692	return 400000;
		3693	}
		3694
		3695	static int i915_get_display_clock_speed(struct drm_device *dev)
		3696	{
		3697	return 333000;
		3698	}
		3699
		3700	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		3701	{
		3702	return 200000;
		3703	}
		3704
		3705	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		3706	{
		3707	u16 gcfgc = 0;
		3708
		3709	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		3710
		3711	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		3712	return 133000;
		3713	else {
		3714	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		3715	case GC_DISPLAY_CLOCK_333_MHZ:
		3716	return 333000;
		3717	default:
		3718	case GC_DISPLAY_CLOCK_190_200_MHZ:
		3719	return 190000;
		3720	}
		3721	}
		3722	}
		3723
		3724	static int i865_get_display_clock_speed(struct drm_device *dev)
		3725	{
		3726	return 266000;
		3727	}
		3728
		3729	static int i855_get_display_clock_speed(struct drm_device *dev)
		3730	{
		3731	u16 hpllcc = 0;
		3732	/* Assume that the hardware is in the high speed state. This
		3733	* should be the default.
		3734	*/
		3735	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		3736	case GC_CLOCK_133_200:
		3737	case GC_CLOCK_100_200:
		3738	return 200000;
		3739	case GC_CLOCK_166_250:
		3740	return 250000;
		3741	case GC_CLOCK_100_133:
		3742	return 133000;
		3743	}
		3744
		3745	/* Shouldn't happen */
		3746	return 0;
		3747	}
		3748
		3749	static int i830_get_display_clock_speed(struct drm_device *dev)
		3750	{
		3751	return 133000;
		3752	}
		3753
		3754	struct fdi_m_n {
		3755	u32 tu;
		3756	u32 gmch_m;
		3757	u32 gmch_n;
		3758	u32 link_m;
		3759	u32 link_n;
		3760	};
		3761
		3762	static void
		3763	fdi_reduce_ratio(u32 num, u32 den)
		3764	{
		3765	while (num > 0xffffff \|\| den > 0xffffff) {
		3766	*num >>= 1;
		3767	*den >>= 1;
		3768	}
		3769	}
		3770
		3771	static void
		3772	ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
		3773	int link_clock, struct fdi_m_n *m_n)
		3774	{
		3775	m_n->tu = 64; /* default size */
		3776
		3777	/* BUG_ON(pixel_clock > INT_MAX / 36); */
		3778	m_n->gmch_m = bits_per_pixel * pixel_clock;
		3779	m_n->gmch_n = link_clock * nlanes * 8;
		3780	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
		3781
		3782	m_n->link_m = pixel_clock;
		3783	m_n->link_n = link_clock;
		3784	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
		3785	}
		3786
		3787	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		3788	{
2342	Serge	3789	if (i915_panel_use_ssc >= 0)
		3790	return i915_panel_use_ssc != 0;
		3791	return dev_priv->lvds_use_ssc
2327	Serge	3792	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		3793	}
		3794
		3795	/**
		3796	* intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
		3797	* @crtc: CRTC structure
2342	Serge	3798	* @mode: requested mode
2327	Serge	3799	*
		3800	* A pipe may be connected to one or more outputs. Based on the depth of the
		3801	* attached framebuffer, choose a good color depth to use on the pipe.
		3802	*
		3803	* If possible, match the pipe depth to the fb depth. In some cases, this
		3804	* isn't ideal, because the connected output supports a lesser or restricted
		3805	* set of depths. Resolve that here:
		3806	* LVDS typically supports only 6bpc, so clamp down in that case
		3807	* HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
		3808	* Displays may support a restricted set as well, check EDID and clamp as
		3809	* appropriate.
2342	Serge	3810	* DP may want to dither down to 6bpc to fit larger modes
2327	Serge	3811	*
		3812	* RETURNS:
		3813	* Dithering requirement (i.e. false if display bpc and pipe bpc match,
		3814	* true if they don't match).
		3815	*/
		3816	static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3031	serge	3817	struct drm_framebuffer *fb,
2342	Serge	3818	unsigned int *pipe_bpp,
		3819	struct drm_display_mode *mode)
2327	Serge	3820	{
		3821	struct drm_device *dev = crtc->dev;
		3822	struct drm_i915_private *dev_priv = dev->dev_private;
		3823	struct drm_connector *connector;
3031	serge	3824	struct intel_encoder *intel_encoder;
2327	Serge	3825	unsigned int display_bpc = UINT_MAX, bpc;
		3826
		3827	/* Walk the encoders & connectors on this crtc, get min bpc */
3031	serge	3828	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2327	Serge	3829
		3830	if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
		3831	unsigned int lvds_bpc;
		3832
		3833	if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
		3834	LVDS_A3_POWER_UP)
		3835	lvds_bpc = 8;
		3836	else
		3837	lvds_bpc = 6;
		3838
		3839	if (lvds_bpc < display_bpc) {
2342	Serge	3840	DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
2327	Serge	3841	display_bpc = lvds_bpc;
		3842	}
		3843	continue;
		3844	}
		3845
		3846	/* Not one of the known troublemakers, check the EDID */
		3847	list_for_each_entry(connector, &dev->mode_config.connector_list,
		3848	head) {
3031	serge	3849	if (connector->encoder != &intel_encoder->base)
2327	Serge	3850	continue;
		3851
		3852	/* Don't use an invalid EDID bpc value */
		3853	if (connector->display_info.bpc &&
		3854	connector->display_info.bpc < display_bpc) {
2342	Serge	3855	DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
2327	Serge	3856	display_bpc = connector->display_info.bpc;
3031	serge	3857	}
		3858	}
2327	Serge	3859
3120	serge	3860	if (intel_encoder->type == INTEL_OUTPUT_EDP) {
		3861	/* Use VBT settings if we have an eDP panel */
		3862	unsigned int edp_bpc = dev_priv->edp.bpp / 3;
		3863
		3864	if (edp_bpc < display_bpc) {
		3865	DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
		3866	display_bpc = edp_bpc;
		3867	}
		3868	continue;
		3869	}
		3870
2327	Serge	3871	/*
		3872	* HDMI is either 12 or 8, so if the display lets 10bpc sneak
		3873	* through, clamp it down. (Note: >12bpc will be caught below.)
		3874	*/
		3875	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		3876	if (display_bpc > 8 && display_bpc < 12) {
2342	Serge	3877	DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
2327	Serge	3878	display_bpc = 12;
		3879	} else {
2342	Serge	3880	DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
2327	Serge	3881	display_bpc = 8;
		3882	}
		3883	}
		3884	}
		3885
2342	Serge	3886	if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
		3887	DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
		3888	display_bpc = 6;
		3889	}
		3890
2327	Serge	3891	/*
		3892	* We could just drive the pipe at the highest bpc all the time and
		3893	* enable dithering as needed, but that costs bandwidth. So choose
		3894	* the minimum value that expresses the full color range of the fb but
		3895	* also stays within the max display bpc discovered above.
		3896	*/
		3897
3031	serge	3898	switch (fb->depth) {
2327	Serge	3899	case 8:
		3900	bpc = 8; /* since we go through a colormap */
		3901	break;
		3902	case 15:
		3903	case 16:
		3904	bpc = 6; /* min is 18bpp */
		3905	break;
		3906	case 24:
2342	Serge	3907	bpc = 8;
2327	Serge	3908	break;
		3909	case 30:
2342	Serge	3910	bpc = 10;
2327	Serge	3911	break;
		3912	case 48:
2342	Serge	3913	bpc = 12;
2327	Serge	3914	break;
		3915	default:
		3916	DRM_DEBUG("unsupported depth, assuming 24 bits\n");
		3917	bpc = min((unsigned int)8, display_bpc);
		3918	break;
		3919	}
		3920
2342	Serge	3921	display_bpc = min(display_bpc, bpc);
		3922
		3923	DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3031	serge	3924	bpc, display_bpc);
2327	Serge	3925
2342	Serge	3926	pipe_bpp = display_bpc 3;
2327	Serge	3927
		3928	return display_bpc != bpc;
		3929	}
		3930
3031	serge	3931	static int vlv_get_refclk(struct drm_crtc *crtc)
2327	Serge	3932	{
3031	serge	3933	struct drm_device *dev = crtc->dev;
		3934	struct drm_i915_private *dev_priv = dev->dev_private;
		3935	int refclk = 27000; /* for DP & HDMI */
2327	Serge	3936
3031	serge	3937	return 100000; /* only one validated so far */
2327	Serge	3938
3031	serge	3939	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		3940	refclk = 96000;
		3941	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		3942	if (intel_panel_use_ssc(dev_priv))
		3943	refclk = 100000;
		3944	else
		3945	refclk = 96000;
		3946	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		3947	refclk = 100000;
		3948	}
2327	Serge	3949
3031	serge	3950	return refclk;
		3951	}
2327	Serge	3952
3031	serge	3953	static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
		3954	{
		3955	struct drm_device *dev = crtc->dev;
		3956	struct drm_i915_private *dev_priv = dev->dev_private;
		3957	int refclk;
2327	Serge	3958
3031	serge	3959	if (IS_VALLEYVIEW(dev)) {
		3960	refclk = vlv_get_refclk(crtc);
		3961	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		3962	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		3963	refclk = dev_priv->lvds_ssc_freq * 1000;
		3964	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		3965	refclk / 1000);
		3966	} else if (!IS_GEN2(dev)) {
		3967	refclk = 96000;
		3968	} else {
		3969	refclk = 48000;
		3970	}
2327	Serge	3971
3031	serge	3972	return refclk;
		3973	}
2327	Serge	3974
3031	serge	3975	static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
		3976	intel_clock_t *clock)
		3977	{
		3978	/* SDVO TV has fixed PLL values depend on its clock range,
		3979	this mirrors vbios setting. */
		3980	if (adjusted_mode->clock >= 100000
		3981	&& adjusted_mode->clock < 140500) {
		3982	clock->p1 = 2;
		3983	clock->p2 = 10;
		3984	clock->n = 3;
		3985	clock->m1 = 16;
		3986	clock->m2 = 8;
		3987	} else if (adjusted_mode->clock >= 140500
		3988	&& adjusted_mode->clock <= 200000) {
		3989	clock->p1 = 1;
		3990	clock->p2 = 10;
		3991	clock->n = 6;
		3992	clock->m1 = 12;
		3993	clock->m2 = 8;
		3994	}
		3995	}
2327	Serge	3996
3031	serge	3997	static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
		3998	intel_clock_t *clock,
		3999	intel_clock_t *reduced_clock)
		4000	{
		4001	struct drm_device *dev = crtc->dev;
		4002	struct drm_i915_private *dev_priv = dev->dev_private;
		4003	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4004	int pipe = intel_crtc->pipe;
		4005	u32 fp, fp2 = 0;
2327	Serge	4006
3031	serge	4007	if (IS_PINEVIEW(dev)) {
		4008	fp = (1 << clock->n) << 16 \| clock->m1 << 8 \| clock->m2;
		4009	if (reduced_clock)
		4010	fp2 = (1 << reduced_clock->n) << 16 \|
		4011	reduced_clock->m1 << 8 \| reduced_clock->m2;
		4012	} else {
		4013	fp = clock->n << 16 \| clock->m1 << 8 \| clock->m2;
		4014	if (reduced_clock)
		4015	fp2 = reduced_clock->n << 16 \| reduced_clock->m1 << 8 \|
		4016	reduced_clock->m2;
		4017	}
2327	Serge	4018
3031	serge	4019	I915_WRITE(FP0(pipe), fp);
2327	Serge	4020
3031	serge	4021	intel_crtc->lowfreq_avail = false;
		4022	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4023	reduced_clock && i915_powersave) {
		4024	I915_WRITE(FP1(pipe), fp2);
		4025	intel_crtc->lowfreq_avail = true;
		4026	} else {
		4027	I915_WRITE(FP1(pipe), fp);
		4028	}
		4029	}
2327	Serge	4030
3031	serge	4031	static void intel_update_lvds(struct drm_crtc crtc, intel_clock_t clock,
		4032	struct drm_display_mode *adjusted_mode)
		4033	{
		4034	struct drm_device *dev = crtc->dev;
		4035	struct drm_i915_private *dev_priv = dev->dev_private;
		4036	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4037	int pipe = intel_crtc->pipe;
		4038	u32 temp;
2327	Serge	4039
3031	serge	4040	temp = I915_READ(LVDS);
		4041	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
		4042	if (pipe == 1) {
		4043	temp \|= LVDS_PIPEB_SELECT;
		4044	} else {
		4045	temp &= ~LVDS_PIPEB_SELECT;
		4046	}
		4047	/* set the corresponsding LVDS_BORDER bit */
		4048	temp \|= dev_priv->lvds_border_bits;
		4049	/* Set the B0-B3 data pairs corresponding to whether we're going to
		4050	* set the DPLLs for dual-channel mode or not.
		4051	*/
		4052	if (clock->p2 == 7)
		4053	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
		4054	else
		4055	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
2327	Serge	4056
3031	serge	4057	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		4058	* appropriately here, but we need to look more thoroughly into how
		4059	* panels behave in the two modes.
		4060	*/
		4061	/* set the dithering flag on LVDS as needed */
		4062	if (INTEL_INFO(dev)->gen >= 4) {
		4063	if (dev_priv->lvds_dither)
		4064	temp \|= LVDS_ENABLE_DITHER;
		4065	else
		4066	temp &= ~LVDS_ENABLE_DITHER;
		4067	}
		4068	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
		4069	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
		4070	temp \|= LVDS_HSYNC_POLARITY;
		4071	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
		4072	temp \|= LVDS_VSYNC_POLARITY;
		4073	I915_WRITE(LVDS, temp);
		4074	}
2327	Serge	4075
3031	serge	4076	static void vlv_update_pll(struct drm_crtc *crtc,
		4077	struct drm_display_mode *mode,
		4078	struct drm_display_mode *adjusted_mode,
		4079	intel_clock_t clock, intel_clock_t reduced_clock,
		4080	int refclk, int num_connectors)
		4081	{
		4082	struct drm_device *dev = crtc->dev;
		4083	struct drm_i915_private *dev_priv = dev->dev_private;
		4084	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4085	int pipe = intel_crtc->pipe;
		4086	u32 dpll, mdiv, pdiv;
		4087	u32 bestn, bestm1, bestm2, bestp1, bestp2;
		4088	bool is_hdmi;
2327	Serge	4089
3031	serge	4090	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
2327	Serge	4091
3031	serge	4092	bestn = clock->n;
		4093	bestm1 = clock->m1;
		4094	bestm2 = clock->m2;
		4095	bestp1 = clock->p1;
		4096	bestp2 = clock->p2;
		4097
		4098	/* Enable DPIO clock input */
		4099	dpll = DPLL_EXT_BUFFER_ENABLE_VLV \| DPLL_REFA_CLK_ENABLE_VLV \|
		4100	DPLL_VGA_MODE_DIS \| DPLL_INTEGRATED_CLOCK_VLV;
		4101	I915_WRITE(DPLL(pipe), dpll);
		4102	POSTING_READ(DPLL(pipe));
		4103
		4104	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		4105	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		4106	mdiv \|= ((bestn << DPIO_N_SHIFT));
		4107	mdiv \|= (1 << DPIO_POST_DIV_SHIFT);
		4108	mdiv \|= (1 << DPIO_K_SHIFT);
		4109	mdiv \|= DPIO_ENABLE_CALIBRATION;
		4110	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
		4111
		4112	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
		4113
		4114	pdiv = DPIO_REFSEL_OVERRIDE \| (5 << DPIO_PLL_MODESEL_SHIFT) \|
		4115	(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) \| (1<<20) \|
		4116	(8 << DPIO_DRIVER_CTL_SHIFT) \| (5 << DPIO_CLK_BIAS_CTL_SHIFT);
		4117	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
		4118
		4119	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
		4120
		4121	dpll \|= DPLL_VCO_ENABLE;
		4122	I915_WRITE(DPLL(pipe), dpll);
		4123	POSTING_READ(DPLL(pipe));
		4124	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		4125	DRM_ERROR("DPLL %d failed to lock\n", pipe);
		4126
		4127	if (is_hdmi) {
		4128	u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
		4129
		4130	if (temp > 1)
		4131	temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4132	else
		4133	temp = 0;
		4134
		4135	I915_WRITE(DPLL_MD(pipe), temp);
		4136	POSTING_READ(DPLL_MD(pipe));
		4137	}
		4138
		4139	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
		4140	}
		4141
		4142	static void i9xx_update_pll(struct drm_crtc *crtc,
		4143	struct drm_display_mode *mode,
		4144	struct drm_display_mode *adjusted_mode,
		4145	intel_clock_t clock, intel_clock_t reduced_clock,
		4146	int num_connectors)
		4147	{
		4148	struct drm_device *dev = crtc->dev;
		4149	struct drm_i915_private *dev_priv = dev->dev_private;
		4150	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4151	int pipe = intel_crtc->pipe;
		4152	u32 dpll;
		4153	bool is_sdvo;
		4154
		4155	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) \|\|
		4156	intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
		4157
		4158	dpll = DPLL_VGA_MODE_DIS;
		4159
		4160	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		4161	dpll \|= DPLLB_MODE_LVDS;
		4162	else
		4163	dpll \|= DPLLB_MODE_DAC_SERIAL;
		4164	if (is_sdvo) {
		4165	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		4166	if (pixel_multiplier > 1) {
		4167	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev))
		4168	dpll \|= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2342	Serge	4169	}
3031	serge	4170	dpll \|= DPLL_DVO_HIGH_SPEED;
2342	Serge	4171	}
3031	serge	4172	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		4173	dpll \|= DPLL_DVO_HIGH_SPEED;
2342	Serge	4174
3031	serge	4175	/* compute bitmask from p1 value */
		4176	if (IS_PINEVIEW(dev))
		4177	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4178	else {
		4179	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4180	if (IS_G4X(dev) && reduced_clock)
		4181	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4182	}
		4183	switch (clock->p2) {
		4184	case 5:
		4185	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4186	break;
		4187	case 7:
		4188	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4189	break;
		4190	case 10:
		4191	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4192	break;
		4193	case 14:
		4194	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4195	break;
		4196	}
		4197	if (INTEL_INFO(dev)->gen >= 4)
		4198	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	4199
3031	serge	4200	if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		4201	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		4202	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		4203	/* XXX: just matching BIOS for now */
		4204	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4205	dpll \|= 3;
		4206	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4207	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4208	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4209	else
		4210	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	4211
3031	serge	4212	dpll \|= DPLL_VCO_ENABLE;
		4213	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		4214	POSTING_READ(DPLL(pipe));
		4215	udelay(150);
2327	Serge	4216
3031	serge	4217	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		4218	* This is an exception to the general rule that mode_set doesn't turn
		4219	* things on.
		4220	*/
		4221	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		4222	intel_update_lvds(crtc, clock, adjusted_mode);
2327	Serge	4223
3031	serge	4224	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		4225	intel_dp_set_m_n(crtc, mode, adjusted_mode);
2327	Serge	4226
3031	serge	4227	I915_WRITE(DPLL(pipe), dpll);
2327	Serge	4228
3031	serge	4229	/* Wait for the clocks to stabilize. */
		4230	POSTING_READ(DPLL(pipe));
		4231	udelay(150);
2327	Serge	4232
3031	serge	4233	if (INTEL_INFO(dev)->gen >= 4) {
		4234	u32 temp = 0;
		4235	if (is_sdvo) {
		4236	temp = intel_mode_get_pixel_multiplier(adjusted_mode);
		4237	if (temp > 1)
		4238	temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4239	else
		4240	temp = 0;
		4241	}
		4242	I915_WRITE(DPLL_MD(pipe), temp);
		4243	} else {
		4244	/* The pixel multiplier can only be updated once the
		4245	* DPLL is enabled and the clocks are stable.
		4246	*
		4247	* So write it again.
		4248	*/
		4249	I915_WRITE(DPLL(pipe), dpll);
		4250	}
		4251	}
2327	Serge	4252
3031	serge	4253	static void i8xx_update_pll(struct drm_crtc *crtc,
		4254	struct drm_display_mode *adjusted_mode,
		4255	intel_clock_t *clock,
		4256	int num_connectors)
		4257	{
		4258	struct drm_device *dev = crtc->dev;
		4259	struct drm_i915_private *dev_priv = dev->dev_private;
		4260	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4261	int pipe = intel_crtc->pipe;
		4262	u32 dpll;
2327	Serge	4263
3031	serge	4264	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	4265
3031	serge	4266	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		4267	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4268	} else {
		4269	if (clock->p1 == 2)
		4270	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4271	else
		4272	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4273	if (clock->p2 == 4)
		4274	dpll \|= PLL_P2_DIVIDE_BY_4;
		4275	}
2327	Serge	4276
3031	serge	4277	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		4278	/* XXX: just matching BIOS for now */
		4279	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4280	dpll \|= 3;
		4281	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4282	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4283	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4284	else
		4285	dpll \|= PLL_REF_INPUT_DREFCLK;
		4286
		4287	dpll \|= DPLL_VCO_ENABLE;
		4288	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		4289	POSTING_READ(DPLL(pipe));
		4290	udelay(150);
		4291
		4292	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		4293	* This is an exception to the general rule that mode_set doesn't turn
		4294	* things on.
		4295	*/
		4296	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		4297	intel_update_lvds(crtc, clock, adjusted_mode);
		4298
		4299	I915_WRITE(DPLL(pipe), dpll);
		4300
		4301	/* Wait for the clocks to stabilize. */
		4302	POSTING_READ(DPLL(pipe));
		4303	udelay(150);
		4304
		4305	/* The pixel multiplier can only be updated once the
		4306	* DPLL is enabled and the clocks are stable.
		4307	*
		4308	* So write it again.
		4309	*/
		4310	I915_WRITE(DPLL(pipe), dpll);
		4311	}
		4312
		4313	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4314	struct drm_display_mode *mode,
		4315	struct drm_display_mode *adjusted_mode,
		4316	int x, int y,
		4317	struct drm_framebuffer *fb)
		4318	{
		4319	struct drm_device *dev = crtc->dev;
		4320	struct drm_i915_private *dev_priv = dev->dev_private;
		4321	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4322	int pipe = intel_crtc->pipe;
		4323	int plane = intel_crtc->plane;
		4324	int refclk, num_connectors = 0;
		4325	intel_clock_t clock, reduced_clock;
		4326	u32 dspcntr, pipeconf, vsyncshift;
		4327	bool ok, has_reduced_clock = false, is_sdvo = false;
		4328	bool is_lvds = false, is_tv = false, is_dp = false;
		4329	struct intel_encoder *encoder;
		4330	const intel_limit_t *limit;
		4331	int ret;
		4332
		4333	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4334	switch (encoder->type) {
		4335	case INTEL_OUTPUT_LVDS:
		4336	is_lvds = true;
		4337	break;
		4338	case INTEL_OUTPUT_SDVO:
		4339	case INTEL_OUTPUT_HDMI:
		4340	is_sdvo = true;
		4341	if (encoder->needs_tv_clock)
		4342	is_tv = true;
		4343	break;
		4344	case INTEL_OUTPUT_TVOUT:
		4345	is_tv = true;
		4346	break;
		4347	case INTEL_OUTPUT_DISPLAYPORT:
		4348	is_dp = true;
		4349	break;
		4350	}
		4351
		4352	num_connectors++;
		4353	}
		4354
		4355	refclk = i9xx_get_refclk(crtc, num_connectors);
		4356
		4357	/*
		4358	* Returns a set of divisors for the desired target clock with the given
		4359	* refclk, or FALSE. The returned values represent the clock equation:
		4360	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4361	*/
		4362	limit = intel_limit(crtc, refclk);
		4363	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
		4364	&clock);
		4365	if (!ok) {
		4366	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4367	return -EINVAL;
		4368	}
		4369
		4370	/* Ensure that the cursor is valid for the new mode before changing... */
		4371	// intel_crtc_update_cursor(crtc, true);
		4372
		4373	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4374	/*
		4375	* Ensure we match the reduced clock's P to the target clock.
		4376	* If the clocks don't match, we can't switch the display clock
		4377	* by using the FP0/FP1. In such case we will disable the LVDS
		4378	* downclock feature.
		4379	*/
		4380	has_reduced_clock = limit->find_pll(limit, crtc,
		4381	dev_priv->lvds_downclock,
		4382	refclk,
		4383	&clock,
		4384	&reduced_clock);
		4385	}
		4386
		4387	if (is_sdvo && is_tv)
		4388	i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
		4389
		4390	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
		4391	&reduced_clock : NULL);
		4392
		4393	if (IS_GEN2(dev))
		4394	i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
		4395	else if (IS_VALLEYVIEW(dev))
		4396	vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
		4397	refclk, num_connectors);
		4398	else
		4399	i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
		4400	has_reduced_clock ? &reduced_clock : NULL,
		4401	num_connectors);
		4402
		4403	/* setup pipeconf */
		4404	pipeconf = I915_READ(PIPECONF(pipe));
		4405
		4406	/* Set up the display plane register */
		4407	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4408
		4409	if (pipe == 0)
		4410	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4411	else
		4412	dspcntr \|= DISPPLANE_SEL_PIPE_B;
		4413
		4414	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4415	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4416	* core speed.
		4417	*
		4418	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4419	* pipe == 0 check?
		4420	*/
		4421	if (mode->clock >
		4422	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4423	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4424	else
		4425	pipeconf &= ~PIPECONF_DOUBLE_WIDE;
		4426	}
		4427
		4428	/* default to 8bpc */
		4429	pipeconf &= ~(PIPECONF_BPP_MASK \| PIPECONF_DITHER_EN);
		4430	if (is_dp) {
		4431	if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
		4432	pipeconf \|= PIPECONF_BPP_6 \|
		4433	PIPECONF_DITHER_EN \|
		4434	PIPECONF_DITHER_TYPE_SP;
		4435	}
		4436	}
		4437
		4438	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
		4439	drm_mode_debug_printmodeline(mode);
		4440
		4441	if (HAS_PIPE_CXSR(dev)) {
		4442	if (intel_crtc->lowfreq_avail) {
		4443	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		4444	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		4445	} else {
		4446	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		4447	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		4448	}
		4449	}
		4450
2360	Serge	4451	pipeconf &= ~PIPECONF_INTERLACE_MASK;
3031	serge	4452	if (!IS_GEN2(dev) &&
		4453	adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		4454	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		4455	/* the chip adds 2 halflines automatically */
		4456	adjusted_mode->crtc_vtotal -= 1;
		4457	adjusted_mode->crtc_vblank_end -= 1;
		4458	vsyncshift = adjusted_mode->crtc_hsync_start
		4459	- adjusted_mode->crtc_htotal/2;
		4460	} else {
2360	Serge	4461	pipeconf \|= PIPECONF_PROGRESSIVE;
3031	serge	4462	vsyncshift = 0;
		4463	}
2327	Serge	4464
3031	serge	4465	if (!IS_GEN3(dev))
		4466	I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
2327	Serge	4467
3031	serge	4468	I915_WRITE(HTOTAL(pipe),
		4469	(adjusted_mode->crtc_hdisplay - 1) \|
		4470	((adjusted_mode->crtc_htotal - 1) << 16));
		4471	I915_WRITE(HBLANK(pipe),
		4472	(adjusted_mode->crtc_hblank_start - 1) \|
		4473	((adjusted_mode->crtc_hblank_end - 1) << 16));
		4474	I915_WRITE(HSYNC(pipe),
		4475	(adjusted_mode->crtc_hsync_start - 1) \|
		4476	((adjusted_mode->crtc_hsync_end - 1) << 16));
2327	Serge	4477
3031	serge	4478	I915_WRITE(VTOTAL(pipe),
		4479	(adjusted_mode->crtc_vdisplay - 1) \|
		4480	((adjusted_mode->crtc_vtotal - 1) << 16));
		4481	I915_WRITE(VBLANK(pipe),
		4482	(adjusted_mode->crtc_vblank_start - 1) \|
		4483	((adjusted_mode->crtc_vblank_end - 1) << 16));
		4484	I915_WRITE(VSYNC(pipe),
		4485	(adjusted_mode->crtc_vsync_start - 1) \|
		4486	((adjusted_mode->crtc_vsync_end - 1) << 16));
2327	Serge	4487
3031	serge	4488	/* pipesrc and dspsize control the size that is scaled from,
		4489	* which should always be the user's requested size.
		4490	*/
		4491	I915_WRITE(DSPSIZE(plane),
		4492	((mode->vdisplay - 1) << 16) \|
		4493	(mode->hdisplay - 1));
		4494	I915_WRITE(DSPPOS(plane), 0);
		4495	I915_WRITE(PIPESRC(pipe),
		4496	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
2327	Serge	4497
3031	serge	4498	I915_WRITE(PIPECONF(pipe), pipeconf);
		4499	POSTING_READ(PIPECONF(pipe));
		4500	intel_enable_pipe(dev_priv, pipe, false);
2327	Serge	4501
3031	serge	4502	intel_wait_for_vblank(dev, pipe);
2327	Serge	4503
3031	serge	4504	I915_WRITE(DSPCNTR(plane), dspcntr);
		4505	POSTING_READ(DSPCNTR(plane));
2327	Serge	4506
3031	serge	4507	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	4508
3031	serge	4509	intel_update_watermarks(dev);
		4510
2327	Serge	4511	return ret;
		4512	}
		4513
2342	Serge	4514	/*
		4515	* Initialize reference clocks when the driver loads
		4516	*/
		4517	void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	4518	{
		4519	struct drm_i915_private *dev_priv = dev->dev_private;
		4520	struct drm_mode_config *mode_config = &dev->mode_config;
		4521	struct intel_encoder *encoder;
		4522	u32 temp;
		4523	bool has_lvds = false;
2342	Serge	4524	bool has_cpu_edp = false;
		4525	bool has_pch_edp = false;
		4526	bool has_panel = false;
		4527	bool has_ck505 = false;
		4528	bool can_ssc = false;
2327	Serge	4529
		4530	/* We need to take the global config into account */
		4531	list_for_each_entry(encoder, &mode_config->encoder_list,
		4532	base.head) {
		4533	switch (encoder->type) {
		4534	case INTEL_OUTPUT_LVDS:
2342	Serge	4535	has_panel = true;
2327	Serge	4536	has_lvds = true;
2342	Serge	4537	break;
2327	Serge	4538	case INTEL_OUTPUT_EDP:
2342	Serge	4539	has_panel = true;
		4540	if (intel_encoder_is_pch_edp(&encoder->base))
		4541	has_pch_edp = true;
		4542	else
		4543	has_cpu_edp = true;
2327	Serge	4544	break;
		4545	}
		4546	}
2342	Serge	4547
		4548	if (HAS_PCH_IBX(dev)) {
		4549	has_ck505 = dev_priv->display_clock_mode;
		4550	can_ssc = has_ck505;
		4551	} else {
		4552	has_ck505 = false;
		4553	can_ssc = true;
2327	Serge	4554	}
		4555
2342	Serge	4556	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
		4557	has_panel, has_lvds, has_pch_edp, has_cpu_edp,
		4558	has_ck505);
		4559
2327	Serge	4560	/* Ironlake: try to setup display ref clock before DPLL
		4561	* enabling. This is only under driver's control after
		4562	* PCH B stepping, previous chipset stepping should be
		4563	* ignoring this setting.
		4564	*/
		4565	temp = I915_READ(PCH_DREF_CONTROL);
		4566	/* Always enable nonspread source */
		4567	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	4568
		4569	if (has_ck505)
		4570	temp \|= DREF_NONSPREAD_CK505_ENABLE;
		4571	else
2327	Serge	4572	temp \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	4573
		4574	if (has_panel) {
2327	Serge	4575	temp &= ~DREF_SSC_SOURCE_MASK;
		4576	temp \|= DREF_SSC_SOURCE_ENABLE;
		4577
2342	Serge	4578	/* SSC must be turned on before enabling the CPU output */
		4579	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		4580	DRM_DEBUG_KMS("Using SSC on panel\n");
		4581	temp \|= DREF_SSC1_ENABLE;
3031	serge	4582	} else
		4583	temp &= ~DREF_SSC1_ENABLE;
2327	Serge	4584
2342	Serge	4585	/* Get SSC going before enabling the outputs */
2327	Serge	4586	I915_WRITE(PCH_DREF_CONTROL, temp);
		4587	POSTING_READ(PCH_DREF_CONTROL);
		4588	udelay(200);
2342	Serge	4589
2327	Serge	4590	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		4591
		4592	/* Enable CPU source on CPU attached eDP */
2342	Serge	4593	if (has_cpu_edp) {
		4594	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		4595	DRM_DEBUG_KMS("Using SSC on eDP\n");
2327	Serge	4596	temp \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2342	Serge	4597	}
2327	Serge	4598	else
		4599	temp \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	4600	} else
		4601	temp \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		4602
		4603	I915_WRITE(PCH_DREF_CONTROL, temp);
		4604	POSTING_READ(PCH_DREF_CONTROL);
		4605	udelay(200);
2327	Serge	4606	} else {
2342	Serge	4607	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		4608
		4609	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		4610
		4611	/* Turn off CPU output */
		4612	temp \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		4613
2327	Serge	4614	I915_WRITE(PCH_DREF_CONTROL, temp);
		4615	POSTING_READ(PCH_DREF_CONTROL);
		4616	udelay(200);
2342	Serge	4617
		4618	/* Turn off the SSC source */
		4619	temp &= ~DREF_SSC_SOURCE_MASK;
		4620	temp \|= DREF_SSC_SOURCE_DISABLE;
		4621
		4622	/* Turn off SSC1 */
		4623	temp &= ~ DREF_SSC1_ENABLE;
		4624
		4625	I915_WRITE(PCH_DREF_CONTROL, temp);
		4626	POSTING_READ(PCH_DREF_CONTROL);
		4627	udelay(200);
2327	Serge	4628	}
		4629	}
		4630
2342	Serge	4631	static int ironlake_get_refclk(struct drm_crtc *crtc)
		4632	{
		4633	struct drm_device *dev = crtc->dev;
		4634	struct drm_i915_private *dev_priv = dev->dev_private;
		4635	struct intel_encoder *encoder;
		4636	struct intel_encoder *edp_encoder = NULL;
		4637	int num_connectors = 0;
		4638	bool is_lvds = false;
		4639
3031	serge	4640	for_each_encoder_on_crtc(dev, crtc, encoder) {
2342	Serge	4641	switch (encoder->type) {
		4642	case INTEL_OUTPUT_LVDS:
		4643	is_lvds = true;
		4644	break;
		4645	case INTEL_OUTPUT_EDP:
		4646	edp_encoder = encoder;
		4647	break;
		4648	}
		4649	num_connectors++;
		4650	}
		4651
		4652	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		4653	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4654	dev_priv->lvds_ssc_freq);
		4655	return dev_priv->lvds_ssc_freq * 1000;
		4656	}
		4657
		4658	return 120000;
		4659	}
		4660
3031	serge	4661	static void ironlake_set_pipeconf(struct drm_crtc *crtc,
		4662	struct drm_display_mode *adjusted_mode,
		4663	bool dither)
		4664	{
		4665	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		4666	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4667	int pipe = intel_crtc->pipe;
		4668	uint32_t val;
		4669
		4670	val = I915_READ(PIPECONF(pipe));
		4671
		4672	val &= ~PIPE_BPC_MASK;
		4673	switch (intel_crtc->bpp) {
		4674	case 18:
		4675	val \|= PIPE_6BPC;
		4676	break;
		4677	case 24:
		4678	val \|= PIPE_8BPC;
		4679	break;
		4680	case 30:
		4681	val \|= PIPE_10BPC;
		4682	break;
		4683	case 36:
		4684	val \|= PIPE_12BPC;
		4685	break;
		4686	default:
		4687	val \|= PIPE_8BPC;
		4688	break;
		4689	}
		4690
		4691	val &= ~(PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_MASK);
		4692	if (dither)
		4693	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		4694
		4695	val &= ~PIPECONF_INTERLACE_MASK;
		4696	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		4697	val \|= PIPECONF_INTERLACED_ILK;
		4698	else
		4699	val \|= PIPECONF_PROGRESSIVE;
		4700
		4701	I915_WRITE(PIPECONF(pipe), val);
		4702	POSTING_READ(PIPECONF(pipe));
		4703	}
		4704
		4705	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
		4706	struct drm_display_mode *adjusted_mode,
		4707	intel_clock_t *clock,
		4708	bool *has_reduced_clock,
		4709	intel_clock_t *reduced_clock)
		4710	{
		4711	struct drm_device *dev = crtc->dev;
		4712	struct drm_i915_private *dev_priv = dev->dev_private;
		4713	struct intel_encoder *intel_encoder;
		4714	int refclk;
		4715	const intel_limit_t *limit;
		4716	bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
		4717
		4718	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		4719	switch (intel_encoder->type) {
		4720	case INTEL_OUTPUT_LVDS:
		4721	is_lvds = true;
		4722	break;
		4723	case INTEL_OUTPUT_SDVO:
		4724	case INTEL_OUTPUT_HDMI:
		4725	is_sdvo = true;
		4726	if (intel_encoder->needs_tv_clock)
		4727	is_tv = true;
		4728	break;
		4729	case INTEL_OUTPUT_TVOUT:
		4730	is_tv = true;
		4731	break;
		4732	}
		4733	}
		4734
		4735	refclk = ironlake_get_refclk(crtc);
		4736
		4737	/*
		4738	* Returns a set of divisors for the desired target clock with the given
		4739	* refclk, or FALSE. The returned values represent the clock equation:
		4740	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4741	*/
		4742	limit = intel_limit(crtc, refclk);
		4743	ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
		4744	clock);
		4745	if (!ret)
		4746	return false;
		4747
		4748	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4749	/*
		4750	* Ensure we match the reduced clock's P to the target clock.
		4751	* If the clocks don't match, we can't switch the display clock
		4752	* by using the FP0/FP1. In such case we will disable the LVDS
		4753	* downclock feature.
		4754	*/
		4755	*has_reduced_clock = limit->find_pll(limit, crtc,
		4756	dev_priv->lvds_downclock,
		4757	refclk,
		4758	clock,
		4759	reduced_clock);
		4760	}
		4761
		4762	if (is_sdvo && is_tv)
		4763	i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
		4764
		4765	return true;
		4766	}
		4767
2327	Serge	4768	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		4769	struct drm_display_mode *mode,
		4770	struct drm_display_mode *adjusted_mode,
		4771	int x, int y,
3031	serge	4772	struct drm_framebuffer *fb)
2327	Serge	4773	{
		4774	struct drm_device *dev = crtc->dev;
		4775	struct drm_i915_private *dev_priv = dev->dev_private;
		4776	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4777	int pipe = intel_crtc->pipe;
		4778	int plane = intel_crtc->plane;
3031	serge	4779	int num_connectors = 0;
2327	Serge	4780	intel_clock_t clock, reduced_clock;
3031	serge	4781	u32 dpll, fp = 0, fp2 = 0;
2327	Serge	4782	bool ok, has_reduced_clock = false, is_sdvo = false;
		4783	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3031	serge	4784	struct intel_encoder encoder, edp_encoder = NULL;
2327	Serge	4785	int ret;
		4786	struct fdi_m_n m_n = {0};
		4787	u32 temp;
		4788	int target_clock, pixel_multiplier, lane, link_bw, factor;
		4789	unsigned int pipe_bpp;
		4790	bool dither;
3031	serge	4791	bool is_cpu_edp = false, is_pch_edp = false;
2327	Serge	4792
3031	serge	4793	for_each_encoder_on_crtc(dev, crtc, encoder) {
2327	Serge	4794	switch (encoder->type) {
		4795	case INTEL_OUTPUT_LVDS:
		4796	is_lvds = true;
		4797	break;
		4798	case INTEL_OUTPUT_SDVO:
		4799	case INTEL_OUTPUT_HDMI:
		4800	is_sdvo = true;
		4801	if (encoder->needs_tv_clock)
		4802	is_tv = true;
		4803	break;
		4804	case INTEL_OUTPUT_TVOUT:
		4805	is_tv = true;
		4806	break;
		4807	case INTEL_OUTPUT_ANALOG:
		4808	is_crt = true;
		4809	break;
		4810	case INTEL_OUTPUT_DISPLAYPORT:
		4811	is_dp = true;
		4812	break;
		4813	case INTEL_OUTPUT_EDP:
3031	serge	4814	is_dp = true;
		4815	if (intel_encoder_is_pch_edp(&encoder->base))
		4816	is_pch_edp = true;
		4817	else
		4818	is_cpu_edp = true;
		4819	edp_encoder = encoder;
2327	Serge	4820	break;
		4821	}
		4822
		4823	num_connectors++;
		4824	}
		4825
3031	serge	4826	ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
		4827	&has_reduced_clock, &reduced_clock);
2327	Serge	4828	if (!ok) {
		4829	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4830	return -EINVAL;
		4831	}
		4832
		4833	/* Ensure that the cursor is valid for the new mode before changing... */
		4834	// intel_crtc_update_cursor(crtc, true);
		4835
		4836	/* FDI link */
		4837	pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		4838	lane = 0;
		4839	/* CPU eDP doesn't require FDI link, so just set DP M/N
		4840	according to current link config */
3031	serge	4841	if (is_cpu_edp) {
		4842	intel_edp_link_config(edp_encoder, &lane, &link_bw);
2327	Serge	4843	} else {
		4844	/* FDI is a binary signal running at ~2.7GHz, encoding
		4845	* each output octet as 10 bits. The actual frequency
		4846	* is stored as a divider into a 100MHz clock, and the
		4847	* mode pixel clock is stored in units of 1KHz.
		4848	* Hence the bw of each lane in terms of the mode signal
		4849	* is:
		4850	*/
		4851	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		4852	}
		4853
3031	serge	4854	/* [e]DP over FDI requires target mode clock instead of link clock. */
		4855	if (edp_encoder)
		4856	target_clock = intel_edp_target_clock(edp_encoder, mode);
		4857	else if (is_dp)
		4858	target_clock = mode->clock;
		4859	else
		4860	target_clock = adjusted_mode->clock;
		4861
2327	Serge	4862	/* determine panel color depth */
3031	serge	4863	dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp,
		4864	adjusted_mode);
		4865	if (is_lvds && dev_priv->lvds_dither)
		4866	dither = true;
		4867
		4868	if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
		4869	pipe_bpp != 36) {
2327	Serge	4870	WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
		4871	pipe_bpp);
		4872	pipe_bpp = 24;
		4873	}
		4874	intel_crtc->bpp = pipe_bpp;
		4875
		4876	if (!lane) {
		4877	/*
		4878	* Account for spread spectrum to avoid
		4879	* oversubscribing the link. Max center spread
		4880	* is 2.5%; use 5% for safety's sake.
		4881	*/
		4882	u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
		4883	lane = bps / (link_bw * 8) + 1;
		4884	}
		4885
		4886	intel_crtc->fdi_lanes = lane;
		4887
		4888	if (pixel_multiplier > 1)
		4889	link_bw *= pixel_multiplier;
		4890	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
		4891	&m_n);
		4892
		4893	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;
		4894	if (has_reduced_clock)
		4895	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|
		4896	reduced_clock.m2;
		4897
		4898	/* Enable autotuning of the PLL clock (if permissible) */
		4899	factor = 21;
		4900	if (is_lvds) {
		4901	if ((intel_panel_use_ssc(dev_priv) &&
		4902	dev_priv->lvds_ssc_freq == 100) \|\|
		4903	(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
		4904	factor = 25;
		4905	} else if (is_sdvo && is_tv)
		4906	factor = 20;
		4907
		4908	if (clock.m < factor * clock.n)
		4909	fp \|= FP_CB_TUNE;
		4910
		4911	dpll = 0;
		4912
		4913	if (is_lvds)
		4914	dpll \|= DPLLB_MODE_LVDS;
		4915	else
		4916	dpll \|= DPLLB_MODE_DAC_SERIAL;
		4917	if (is_sdvo) {
		4918	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		4919	if (pixel_multiplier > 1) {
		4920	dpll \|= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
		4921	}
		4922	dpll \|= DPLL_DVO_HIGH_SPEED;
		4923	}
3031	serge	4924	if (is_dp && !is_cpu_edp)
2327	Serge	4925	dpll \|= DPLL_DVO_HIGH_SPEED;
		4926
		4927	/* compute bitmask from p1 value */
		4928	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4929	/* also FPA1 */
		4930	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4931
		4932	switch (clock.p2) {
		4933	case 5:
		4934	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4935	break;
		4936	case 7:
		4937	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4938	break;
		4939	case 10:
		4940	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4941	break;
		4942	case 14:
		4943	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4944	break;
		4945	}
		4946
		4947	if (is_sdvo && is_tv)
		4948	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		4949	else if (is_tv)
		4950	/* XXX: just matching BIOS for now */
		4951	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4952	dpll \|= 3;
		4953	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4954	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4955	else
		4956	dpll \|= PLL_REF_INPUT_DREFCLK;
		4957
2342	Serge	4958	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
2327	Serge	4959	drm_mode_debug_printmodeline(mode);
		4960
3031	serge	4961	/* CPU eDP is the only output that doesn't need a PCH PLL of its own on
		4962	* pre-Haswell/LPT generation */
		4963	if (HAS_PCH_LPT(dev)) {
		4964	DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
		4965	pipe);
		4966	} else if (!is_cpu_edp) {
		4967	struct intel_pch_pll *pll;
2327	Serge	4968
3031	serge	4969	pll = intel_get_pch_pll(intel_crtc, dpll, fp);
		4970	if (pll == NULL) {
		4971	DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
		4972	pipe);
2342	Serge	4973	return -EINVAL;
2327	Serge	4974	}
3031	serge	4975	} else
		4976	intel_put_pch_pll(intel_crtc);
2327	Serge	4977
		4978	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		4979	* This is an exception to the general rule that mode_set doesn't turn
		4980	* things on.
		4981	*/
		4982	if (is_lvds) {
		4983	temp = I915_READ(PCH_LVDS);
		4984	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
2342	Serge	4985	if (HAS_PCH_CPT(dev)) {
		4986	temp &= ~PORT_TRANS_SEL_MASK;
		4987	temp \|= PORT_TRANS_SEL_CPT(pipe);
		4988	} else {
		4989	if (pipe == 1)
2327	Serge	4990	temp \|= LVDS_PIPEB_SELECT;
		4991	else
		4992	temp &= ~LVDS_PIPEB_SELECT;
		4993	}
2342	Serge	4994
2327	Serge	4995	/* set the corresponsding LVDS_BORDER bit */
		4996	temp \|= dev_priv->lvds_border_bits;
		4997	/* Set the B0-B3 data pairs corresponding to whether we're going to
		4998	* set the DPLLs for dual-channel mode or not.
		4999	*/
		5000	if (clock.p2 == 7)
		5001	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
		5002	else
		5003	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
		5004
		5005	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		5006	* appropriately here, but we need to look more thoroughly into how
		5007	* panels behave in the two modes.
		5008	*/
3031	serge	5009	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
2327	Serge	5010	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3031	serge	5011	temp \|= LVDS_HSYNC_POLARITY;
2327	Serge	5012	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3031	serge	5013	temp \|= LVDS_VSYNC_POLARITY;
2327	Serge	5014	I915_WRITE(PCH_LVDS, temp);
		5015	}
		5016
3031	serge	5017	if (is_dp && !is_cpu_edp) {
2327	Serge	5018	intel_dp_set_m_n(crtc, mode, adjusted_mode);
		5019	} else {
		5020	/* For non-DP output, clear any trans DP clock recovery setting.*/
		5021	I915_WRITE(TRANSDATA_M1(pipe), 0);
		5022	I915_WRITE(TRANSDATA_N1(pipe), 0);
		5023	I915_WRITE(TRANSDPLINK_M1(pipe), 0);
		5024	I915_WRITE(TRANSDPLINK_N1(pipe), 0);
		5025	}
		5026
3031	serge	5027	if (intel_crtc->pch_pll) {
		5028	I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
2327	Serge	5029
		5030	/* Wait for the clocks to stabilize. */
3031	serge	5031	POSTING_READ(intel_crtc->pch_pll->pll_reg);
2327	Serge	5032	udelay(150);
		5033
		5034	/* The pixel multiplier can only be updated once the
		5035	* DPLL is enabled and the clocks are stable.
		5036	*
		5037	* So write it again.
		5038	*/
3031	serge	5039	I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
2327	Serge	5040	}
		5041
		5042	intel_crtc->lowfreq_avail = false;
3031	serge	5043	if (intel_crtc->pch_pll) {
2327	Serge	5044	if (is_lvds && has_reduced_clock && i915_powersave) {
3031	serge	5045	I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
2327	Serge	5046	intel_crtc->lowfreq_avail = true;
		5047	} else {
3031	serge	5048	I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
2327	Serge	5049	}
2342	Serge	5050	}
2327	Serge	5051
		5052	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		5053	/* the chip adds 2 halflines automatically */
		5054	adjusted_mode->crtc_vtotal -= 1;
		5055	adjusted_mode->crtc_vblank_end -= 1;
3031	serge	5056	I915_WRITE(VSYNCSHIFT(pipe),
		5057	adjusted_mode->crtc_hsync_start
		5058	- adjusted_mode->crtc_htotal/2);
		5059	} else {
		5060	I915_WRITE(VSYNCSHIFT(pipe), 0);
		5061	}
2327	Serge	5062
		5063	I915_WRITE(HTOTAL(pipe),
		5064	(adjusted_mode->crtc_hdisplay - 1) \|
		5065	((adjusted_mode->crtc_htotal - 1) << 16));
		5066	I915_WRITE(HBLANK(pipe),
		5067	(adjusted_mode->crtc_hblank_start - 1) \|
		5068	((adjusted_mode->crtc_hblank_end - 1) << 16));
		5069	I915_WRITE(HSYNC(pipe),
		5070	(adjusted_mode->crtc_hsync_start - 1) \|
		5071	((adjusted_mode->crtc_hsync_end - 1) << 16));
		5072
		5073	I915_WRITE(VTOTAL(pipe),
		5074	(adjusted_mode->crtc_vdisplay - 1) \|
		5075	((adjusted_mode->crtc_vtotal - 1) << 16));
		5076	I915_WRITE(VBLANK(pipe),
		5077	(adjusted_mode->crtc_vblank_start - 1) \|
		5078	((adjusted_mode->crtc_vblank_end - 1) << 16));
		5079	I915_WRITE(VSYNC(pipe),
		5080	(adjusted_mode->crtc_vsync_start - 1) \|
		5081	((adjusted_mode->crtc_vsync_end - 1) << 16));
		5082
		5083	/* pipesrc controls the size that is scaled from, which should
		5084	* always be the user's requested size.
		5085	*/
		5086	I915_WRITE(PIPESRC(pipe),
		5087	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		5088
		5089	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) \| m_n.gmch_m);
		5090	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
		5091	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
		5092	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
		5093
3031	serge	5094	if (is_cpu_edp)
2327	Serge	5095	ironlake_set_pll_edp(crtc, adjusted_mode->clock);
		5096
3031	serge	5097	ironlake_set_pipeconf(crtc, adjusted_mode, dither);
2327	Serge	5098
		5099	intel_wait_for_vblank(dev, pipe);
		5100
3031	serge	5101	/* Set up the display plane register */
		5102	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
2327	Serge	5103	POSTING_READ(DSPCNTR(plane));
		5104
3031	serge	5105	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	5106
		5107	intel_update_watermarks(dev);
		5108
3031	serge	5109	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
2336	Serge	5110
2327	Serge	5111	return ret;
		5112	}
		5113
2330	Serge	5114	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		5115	struct drm_display_mode *mode,
		5116	struct drm_display_mode *adjusted_mode,
		5117	int x, int y,
3031	serge	5118	struct drm_framebuffer *fb)
2330	Serge	5119	{
		5120	struct drm_device *dev = crtc->dev;
		5121	struct drm_i915_private *dev_priv = dev->dev_private;
		5122	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5123	int pipe = intel_crtc->pipe;
		5124	int ret;
2327	Serge	5125
3031	serge	5126	drm_vblank_pre_modeset(dev, pipe);
2327	Serge	5127
2330	Serge	5128	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
3031	serge	5129	x, y, fb);
		5130	drm_vblank_post_modeset(dev, pipe);
2327	Serge	5131
2330	Serge	5132	return ret;
		5133	}
2327	Serge	5134
2342	Serge	5135	static bool intel_eld_uptodate(struct drm_connector *connector,
		5136	int reg_eldv, uint32_t bits_eldv,
		5137	int reg_elda, uint32_t bits_elda,
		5138	int reg_edid)
		5139	{
		5140	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5141	uint8_t *eld = connector->eld;
		5142	uint32_t i;
		5143
		5144	i = I915_READ(reg_eldv);
		5145	i &= bits_eldv;
		5146
		5147	if (!eld[0])
		5148	return !i;
		5149
		5150	if (!i)
		5151	return false;
		5152
		5153	i = I915_READ(reg_elda);
		5154	i &= ~bits_elda;
		5155	I915_WRITE(reg_elda, i);
		5156
		5157	for (i = 0; i < eld[2]; i++)
		5158	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
		5159	return false;
		5160
		5161	return true;
		5162	}
		5163
		5164	static void g4x_write_eld(struct drm_connector *connector,
		5165	struct drm_crtc *crtc)
		5166	{
		5167	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5168	uint8_t *eld = connector->eld;
		5169	uint32_t eldv;
		5170	uint32_t len;
		5171	uint32_t i;
		5172
		5173	i = I915_READ(G4X_AUD_VID_DID);
		5174
		5175	if (i == INTEL_AUDIO_DEVBLC \|\| i == INTEL_AUDIO_DEVCL)
		5176	eldv = G4X_ELDV_DEVCL_DEVBLC;
		5177	else
		5178	eldv = G4X_ELDV_DEVCTG;
		5179
		5180	if (intel_eld_uptodate(connector,
		5181	G4X_AUD_CNTL_ST, eldv,
		5182	G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
		5183	G4X_HDMIW_HDMIEDID))
		5184	return;
		5185
		5186	i = I915_READ(G4X_AUD_CNTL_ST);
		5187	i &= ~(eldv \| G4X_ELD_ADDR);
		5188	len = (i >> 9) & 0x1f; /* ELD buffer size */
		5189	I915_WRITE(G4X_AUD_CNTL_ST, i);
		5190
		5191	if (!eld[0])
		5192	return;
		5193
		5194	len = min_t(uint8_t, eld[2], len);
		5195	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		5196	for (i = 0; i < len; i++)
		5197	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
		5198
		5199	i = I915_READ(G4X_AUD_CNTL_ST);
		5200	i \|= eldv;
		5201	I915_WRITE(G4X_AUD_CNTL_ST, i);
		5202	}
		5203
3031	serge	5204	static void haswell_write_eld(struct drm_connector *connector,
		5205	struct drm_crtc *crtc)
		5206	{
		5207	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5208	uint8_t *eld = connector->eld;
		5209	struct drm_device *dev = crtc->dev;
		5210	uint32_t eldv;
		5211	uint32_t i;
		5212	int len;
		5213	int pipe = to_intel_crtc(crtc)->pipe;
		5214	int tmp;
		5215
		5216	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
		5217	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
		5218	int aud_config = HSW_AUD_CFG(pipe);
		5219	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
		5220
		5221
		5222	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
		5223
		5224	/* Audio output enable */
		5225	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
		5226	tmp = I915_READ(aud_cntrl_st2);
		5227	tmp \|= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
		5228	I915_WRITE(aud_cntrl_st2, tmp);
		5229
		5230	/* Wait for 1 vertical blank */
		5231	intel_wait_for_vblank(dev, pipe);
		5232
		5233	/* Set ELD valid state */
		5234	tmp = I915_READ(aud_cntrl_st2);
		5235	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
		5236	tmp \|= (AUDIO_ELD_VALID_A << (pipe * 4));
		5237	I915_WRITE(aud_cntrl_st2, tmp);
		5238	tmp = I915_READ(aud_cntrl_st2);
		5239	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
		5240
		5241	/* Enable HDMI mode */
		5242	tmp = I915_READ(aud_config);
		5243	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
		5244	/* clear N_programing_enable and N_value_index */
		5245	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX \| AUD_CONFIG_N_PROG_ENABLE);
		5246	I915_WRITE(aud_config, tmp);
		5247
		5248	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
		5249
		5250	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
		5251
		5252	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		5253	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		5254	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
		5255	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		5256	} else
		5257	I915_WRITE(aud_config, 0);
		5258
		5259	if (intel_eld_uptodate(connector,
		5260	aud_cntrl_st2, eldv,
		5261	aud_cntl_st, IBX_ELD_ADDRESS,
		5262	hdmiw_hdmiedid))
		5263	return;
		5264
		5265	i = I915_READ(aud_cntrl_st2);
		5266	i &= ~eldv;
		5267	I915_WRITE(aud_cntrl_st2, i);
		5268
		5269	if (!eld[0])
		5270	return;
		5271
		5272	i = I915_READ(aud_cntl_st);
		5273	i &= ~IBX_ELD_ADDRESS;
		5274	I915_WRITE(aud_cntl_st, i);
		5275	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
		5276	DRM_DEBUG_DRIVER("port num:%d\n", i);
		5277
		5278	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		5279	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		5280	for (i = 0; i < len; i++)
		5281	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		5282
		5283	i = I915_READ(aud_cntrl_st2);
		5284	i \|= eldv;
		5285	I915_WRITE(aud_cntrl_st2, i);
		5286
		5287	}
		5288
2342	Serge	5289	static void ironlake_write_eld(struct drm_connector *connector,
		5290	struct drm_crtc *crtc)
		5291	{
		5292	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5293	uint8_t *eld = connector->eld;
		5294	uint32_t eldv;
		5295	uint32_t i;
		5296	int len;
		5297	int hdmiw_hdmiedid;
3031	serge	5298	int aud_config;
2342	Serge	5299	int aud_cntl_st;
		5300	int aud_cntrl_st2;
3031	serge	5301	int pipe = to_intel_crtc(crtc)->pipe;
2342	Serge	5302
		5303	if (HAS_PCH_IBX(connector->dev)) {
3031	serge	5304	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		5305	aud_config = IBX_AUD_CFG(pipe);
		5306	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
2342	Serge	5307	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
		5308	} else {
3031	serge	5309	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		5310	aud_config = CPT_AUD_CFG(pipe);
		5311	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
2342	Serge	5312	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
		5313	}
		5314
3031	serge	5315	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
2342	Serge	5316
		5317	i = I915_READ(aud_cntl_st);
3031	serge	5318	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
2342	Serge	5319	if (!i) {
		5320	DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		5321	/* operate blindly on all ports */
		5322	eldv = IBX_ELD_VALIDB;
		5323	eldv \|= IBX_ELD_VALIDB << 4;
		5324	eldv \|= IBX_ELD_VALIDB << 8;
		5325	} else {
		5326	DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
		5327	eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
		5328	}
		5329
		5330	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		5331	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		5332	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
3031	serge	5333	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		5334	} else
		5335	I915_WRITE(aud_config, 0);
2342	Serge	5336
		5337	if (intel_eld_uptodate(connector,
		5338	aud_cntrl_st2, eldv,
		5339	aud_cntl_st, IBX_ELD_ADDRESS,
		5340	hdmiw_hdmiedid))
		5341	return;
		5342
		5343	i = I915_READ(aud_cntrl_st2);
		5344	i &= ~eldv;
		5345	I915_WRITE(aud_cntrl_st2, i);
		5346
		5347	if (!eld[0])
		5348	return;
		5349
		5350	i = I915_READ(aud_cntl_st);
		5351	i &= ~IBX_ELD_ADDRESS;
		5352	I915_WRITE(aud_cntl_st, i);
		5353
		5354	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		5355	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		5356	for (i = 0; i < len; i++)
		5357	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		5358
		5359	i = I915_READ(aud_cntrl_st2);
		5360	i \|= eldv;
		5361	I915_WRITE(aud_cntrl_st2, i);
		5362	}
		5363
		5364	void intel_write_eld(struct drm_encoder *encoder,
		5365	struct drm_display_mode *mode)
		5366	{
		5367	struct drm_crtc *crtc = encoder->crtc;
		5368	struct drm_connector *connector;
		5369	struct drm_device *dev = encoder->dev;
		5370	struct drm_i915_private *dev_priv = dev->dev_private;
		5371
		5372	connector = drm_select_eld(encoder, mode);
		5373	if (!connector)
		5374	return;
		5375
		5376	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5377	connector->base.id,
		5378	drm_get_connector_name(connector),
		5379	connector->encoder->base.id,
		5380	drm_get_encoder_name(connector->encoder));
		5381
		5382	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
		5383
		5384	if (dev_priv->display.write_eld)
		5385	dev_priv->display.write_eld(connector, crtc);
		5386	}
		5387
2327	Serge	5388	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		5389	void intel_crtc_load_lut(struct drm_crtc *crtc)
		5390	{
		5391	struct drm_device *dev = crtc->dev;
		5392	struct drm_i915_private *dev_priv = dev->dev_private;
		5393	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5394	int palreg = PALETTE(intel_crtc->pipe);
		5395	int i;
		5396
		5397	/* The clocks have to be on to load the palette. */
3031	serge	5398	if (!crtc->enabled \|\| !intel_crtc->active)
2327	Serge	5399	return;
		5400
		5401	/* use legacy palette for Ironlake */
		5402	if (HAS_PCH_SPLIT(dev))
		5403	palreg = LGC_PALETTE(intel_crtc->pipe);
		5404
		5405	for (i = 0; i < 256; i++) {
		5406	I915_WRITE(palreg + 4 * i,
		5407	(intel_crtc->lut_r[i] << 16) \|
		5408	(intel_crtc->lut_g[i] << 8) \|
		5409	intel_crtc->lut_b[i]);
		5410	}
		5411	}
		5412
3031	serge	5413	#if 0
		5414	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
		5415	{
		5416	struct drm_device *dev = crtc->dev;
		5417	struct drm_i915_private *dev_priv = dev->dev_private;
		5418	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5419	bool visible = base != 0;
		5420	u32 cntl;
2327	Serge	5421
3031	serge	5422	if (intel_crtc->cursor_visible == visible)
		5423	return;
2327	Serge	5424
3031	serge	5425	cntl = I915_READ(_CURACNTR);
		5426	if (visible) {
		5427	/* On these chipsets we can only modify the base whilst
		5428	* the cursor is disabled.
		5429	*/
		5430	I915_WRITE(_CURABASE, base);
2327	Serge	5431
3031	serge	5432	cntl &= ~(CURSOR_FORMAT_MASK);
		5433	/* XXX width must be 64, stride 256 => 0x00 << 28 */
		5434	cntl \|= CURSOR_ENABLE \|
		5435	CURSOR_GAMMA_ENABLE \|
		5436	CURSOR_FORMAT_ARGB;
		5437	} else
		5438	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);
		5439	I915_WRITE(_CURACNTR, cntl);
2327	Serge	5440
3031	serge	5441	intel_crtc->cursor_visible = visible;
		5442	}
2327	Serge	5443
3031	serge	5444	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
		5445	{
		5446	struct drm_device *dev = crtc->dev;
		5447	struct drm_i915_private *dev_priv = dev->dev_private;
		5448	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5449	int pipe = intel_crtc->pipe;
		5450	bool visible = base != 0;
2327	Serge	5451
3031	serge	5452	if (intel_crtc->cursor_visible != visible) {
		5453	uint32_t cntl = I915_READ(CURCNTR(pipe));
		5454	if (base) {
		5455	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);
		5456	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		5457	cntl \|= pipe << 28; /* Connect to correct pipe */
		5458	} else {
		5459	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		5460	cntl \|= CURSOR_MODE_DISABLE;
		5461	}
		5462	I915_WRITE(CURCNTR(pipe), cntl);
2327	Serge	5463
3031	serge	5464	intel_crtc->cursor_visible = visible;
		5465	}
		5466	/* and commit changes on next vblank */
		5467	I915_WRITE(CURBASE(pipe), base);
		5468	}
2327	Serge	5469
3031	serge	5470	static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
		5471	{
		5472	struct drm_device *dev = crtc->dev;
		5473	struct drm_i915_private *dev_priv = dev->dev_private;
		5474	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5475	int pipe = intel_crtc->pipe;
		5476	bool visible = base != 0;
2327	Serge	5477
3031	serge	5478	if (intel_crtc->cursor_visible != visible) {
		5479	uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		5480	if (base) {
		5481	cntl &= ~CURSOR_MODE;
		5482	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		5483	} else {
		5484	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		5485	cntl \|= CURSOR_MODE_DISABLE;
		5486	}
		5487	I915_WRITE(CURCNTR_IVB(pipe), cntl);
2327	Serge	5488
3031	serge	5489	intel_crtc->cursor_visible = visible;
		5490	}
		5491	/* and commit changes on next vblank */
		5492	I915_WRITE(CURBASE_IVB(pipe), base);
		5493	}
2327	Serge	5494
3031	serge	5495	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
		5496	static void intel_crtc_update_cursor(struct drm_crtc *crtc,
		5497	bool on)
		5498	{
		5499	struct drm_device *dev = crtc->dev;
		5500	struct drm_i915_private *dev_priv = dev->dev_private;
		5501	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5502	int pipe = intel_crtc->pipe;
		5503	int x = intel_crtc->cursor_x;
		5504	int y = intel_crtc->cursor_y;
		5505	u32 base, pos;
		5506	bool visible;
2327	Serge	5507
3031	serge	5508	pos = 0;
2327	Serge	5509
3031	serge	5510	if (on && crtc->enabled && crtc->fb) {
		5511	base = intel_crtc->cursor_addr;
		5512	if (x > (int) crtc->fb->width)
		5513	base = 0;
2327	Serge	5514
3031	serge	5515	if (y > (int) crtc->fb->height)
		5516	base = 0;
		5517	} else
		5518	base = 0;
2327	Serge	5519
3031	serge	5520	if (x < 0) {
		5521	if (x + intel_crtc->cursor_width < 0)
		5522	base = 0;
2327	Serge	5523
3031	serge	5524	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		5525	x = -x;
		5526	}
		5527	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	5528
3031	serge	5529	if (y < 0) {
		5530	if (y + intel_crtc->cursor_height < 0)
		5531	base = 0;
2327	Serge	5532
3031	serge	5533	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		5534	y = -y;
		5535	}
		5536	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	5537
3031	serge	5538	visible = base != 0;
		5539	if (!visible && !intel_crtc->cursor_visible)
		5540	return;
2327	Serge	5541
3031	serge	5542	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev)) {
		5543	I915_WRITE(CURPOS_IVB(pipe), pos);
		5544	ivb_update_cursor(crtc, base);
		5545	} else {
		5546	I915_WRITE(CURPOS(pipe), pos);
		5547	if (IS_845G(dev) \|\| IS_I865G(dev))
		5548	i845_update_cursor(crtc, base);
		5549	else
		5550	i9xx_update_cursor(crtc, base);
		5551	}
		5552	}
2327	Serge	5553
3031	serge	5554	static int intel_crtc_cursor_set(struct drm_crtc *crtc,
		5555	struct drm_file *file,
		5556	uint32_t handle,
		5557	uint32_t width, uint32_t height)
		5558	{
		5559	struct drm_device *dev = crtc->dev;
		5560	struct drm_i915_private *dev_priv = dev->dev_private;
		5561	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5562	struct drm_i915_gem_object *obj;
		5563	uint32_t addr;
		5564	int ret;
2327	Serge	5565
3031	serge	5566	/* if we want to turn off the cursor ignore width and height */
		5567	if (!handle) {
		5568	DRM_DEBUG_KMS("cursor off\n");
		5569	addr = 0;
		5570	obj = NULL;
		5571	mutex_lock(&dev->struct_mutex);
		5572	goto finish;
		5573	}
2327	Serge	5574
3031	serge	5575	/* Currently we only support 64x64 cursors */
		5576	if (width != 64 \|\| height != 64) {
		5577	DRM_ERROR("we currently only support 64x64 cursors\n");
		5578	return -EINVAL;
		5579	}
2327	Serge	5580
3031	serge	5581	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
		5582	if (&obj->base == NULL)
		5583	return -ENOENT;
2327	Serge	5584
3031	serge	5585	if (obj->base.size < width * height * 4) {
		5586	DRM_ERROR("buffer is to small\n");
		5587	ret = -ENOMEM;
		5588	goto fail;
		5589	}
2327	Serge	5590
3031	serge	5591	/* we only need to pin inside GTT if cursor is non-phy */
		5592	mutex_lock(&dev->struct_mutex);
		5593	if (!dev_priv->info->cursor_needs_physical) {
		5594	if (obj->tiling_mode) {
		5595	DRM_ERROR("cursor cannot be tiled\n");
		5596	ret = -EINVAL;
		5597	goto fail_locked;
		5598	}
2327	Serge	5599
3031	serge	5600	ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
		5601	if (ret) {
		5602	DRM_ERROR("failed to move cursor bo into the GTT\n");
		5603	goto fail_locked;
		5604	}
2327	Serge	5605
3031	serge	5606	ret = i915_gem_object_put_fence(obj);
		5607	if (ret) {
		5608	DRM_ERROR("failed to release fence for cursor");
		5609	goto fail_unpin;
		5610	}
2327	Serge	5611
3031	serge	5612	addr = obj->gtt_offset;
		5613	} else {
		5614	int align = IS_I830(dev) ? 16 * 1024 : 256;
		5615	ret = i915_gem_attach_phys_object(dev, obj,
		5616	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
		5617	align);
		5618	if (ret) {
		5619	DRM_ERROR("failed to attach phys object\n");
		5620	goto fail_locked;
		5621	}
		5622	addr = obj->phys_obj->handle->busaddr;
		5623	}
2327	Serge	5624
3031	serge	5625	if (IS_GEN2(dev))
		5626	I915_WRITE(CURSIZE, (height << 12) \| width);
2327	Serge	5627
3031	serge	5628	finish:
		5629	if (intel_crtc->cursor_bo) {
		5630	if (dev_priv->info->cursor_needs_physical) {
		5631	if (intel_crtc->cursor_bo != obj)
		5632	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		5633	} else
		5634	i915_gem_object_unpin(intel_crtc->cursor_bo);
		5635	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
		5636	}
2327	Serge	5637
3031	serge	5638	mutex_unlock(&dev->struct_mutex);
2327	Serge	5639
3031	serge	5640	intel_crtc->cursor_addr = addr;
		5641	intel_crtc->cursor_bo = obj;
		5642	intel_crtc->cursor_width = width;
		5643	intel_crtc->cursor_height = height;
2327	Serge	5644
3031	serge	5645	// intel_crtc_update_cursor(crtc, true);
2327	Serge	5646
3031	serge	5647	return 0;
		5648	fail_unpin:
		5649	i915_gem_object_unpin(obj);
		5650	fail_locked:
		5651	mutex_unlock(&dev->struct_mutex);
		5652	fail:
		5653	drm_gem_object_unreference_unlocked(&obj->base);
		5654	return ret;
		5655	}
2327	Serge	5656
3031	serge	5657	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
		5658	{
		5659	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5660
		5661	intel_crtc->cursor_x = x;
		5662	intel_crtc->cursor_y = y;
		5663
		5664	// intel_crtc_update_cursor(crtc, true);
		5665
		5666	return 0;
		5667	}
		5668	#endif
		5669
2332	Serge	5670	/** Sets the color ramps on behalf of RandR */
		5671	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		5672	u16 blue, int regno)
		5673	{
		5674	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5675
2332	Serge	5676	intel_crtc->lut_r[regno] = red >> 8;
		5677	intel_crtc->lut_g[regno] = green >> 8;
		5678	intel_crtc->lut_b[regno] = blue >> 8;
		5679	}
2327	Serge	5680
2332	Serge	5681	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		5682	u16 *blue, int regno)
		5683	{
		5684	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5685
2332	Serge	5686	*red = intel_crtc->lut_r[regno] << 8;
		5687	*green = intel_crtc->lut_g[regno] << 8;
		5688	*blue = intel_crtc->lut_b[regno] << 8;
		5689	}
2327	Serge	5690
2330	Serge	5691	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		5692	u16 *blue, uint32_t start, uint32_t size)
		5693	{
		5694	int end = (start + size > 256) ? 256 : start + size, i;
		5695	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5696
2330	Serge	5697	for (i = start; i < end; i++) {
		5698	intel_crtc->lut_r[i] = red[i] >> 8;
		5699	intel_crtc->lut_g[i] = green[i] >> 8;
		5700	intel_crtc->lut_b[i] = blue[i] >> 8;
		5701	}
2327	Serge	5702
2330	Serge	5703	intel_crtc_load_lut(crtc);
		5704	}
2327	Serge	5705
2330	Serge	5706	/**
		5707	* Get a pipe with a simple mode set on it for doing load-based monitor
		5708	* detection.
		5709	*
		5710	* It will be up to the load-detect code to adjust the pipe as appropriate for
		5711	* its requirements. The pipe will be connected to no other encoders.
		5712	*
		5713	* Currently this code will only succeed if there is a pipe with no encoders
		5714	* configured for it. In the future, it could choose to temporarily disable
		5715	* some outputs to free up a pipe for its use.
		5716	*
		5717	* \return crtc, or NULL if no pipes are available.
		5718	*/
2327	Serge	5719
2330	Serge	5720	/* VESA 640x480x72Hz mode to set on the pipe */
		5721	static struct drm_display_mode load_detect_mode = {
		5722	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		5723	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		5724	};
2327	Serge	5725
3031	serge	5726	static struct drm_framebuffer *
		5727	intel_framebuffer_create(struct drm_device *dev,
		5728	struct drm_mode_fb_cmd2 *mode_cmd,
		5729	struct drm_i915_gem_object *obj)
		5730	{
		5731	struct intel_framebuffer *intel_fb;
		5732	int ret;
2327	Serge	5733
3031	serge	5734	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		5735	if (!intel_fb) {
		5736	drm_gem_object_unreference_unlocked(&obj->base);
		5737	return ERR_PTR(-ENOMEM);
		5738	}
2327	Serge	5739
3031	serge	5740	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
		5741	if (ret) {
		5742	drm_gem_object_unreference_unlocked(&obj->base);
		5743	kfree(intel_fb);
		5744	return ERR_PTR(ret);
		5745	}
2327	Serge	5746
3031	serge	5747	return &intel_fb->base;
		5748	}
2327	Serge	5749
2330	Serge	5750	static u32
		5751	intel_framebuffer_pitch_for_width(int width, int bpp)
		5752	{
		5753	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		5754	return ALIGN(pitch, 64);
		5755	}
2327	Serge	5756
2330	Serge	5757	static u32
		5758	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		5759	{
		5760	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		5761	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		5762	}
2327	Serge	5763
2330	Serge	5764	static struct drm_framebuffer *
		5765	intel_framebuffer_create_for_mode(struct drm_device *dev,
		5766	struct drm_display_mode *mode,
		5767	int depth, int bpp)
		5768	{
		5769	struct drm_i915_gem_object *obj;
2344	Serge	5770	struct drm_mode_fb_cmd2 mode_cmd;
2327	Serge	5771
2330	Serge	5772	// obj = i915_gem_alloc_object(dev,
		5773	// intel_framebuffer_size_for_mode(mode, bpp));
		5774	// if (obj == NULL)
		5775	return ERR_PTR(-ENOMEM);
2327	Serge	5776
2330	Serge	5777	// mode_cmd.width = mode->hdisplay;
		5778	// mode_cmd.height = mode->vdisplay;
		5779	// mode_cmd.depth = depth;
		5780	// mode_cmd.bpp = bpp;
		5781	// mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
2327	Serge	5782
2330	Serge	5783	// return intel_framebuffer_create(dev, &mode_cmd, obj);
		5784	}
2327	Serge	5785
2330	Serge	5786	static struct drm_framebuffer *
		5787	mode_fits_in_fbdev(struct drm_device *dev,
		5788	struct drm_display_mode *mode)
		5789	{
		5790	struct drm_i915_private *dev_priv = dev->dev_private;
		5791	struct drm_i915_gem_object *obj;
		5792	struct drm_framebuffer *fb;
2327	Serge	5793
2330	Serge	5794	// if (dev_priv->fbdev == NULL)
		5795	// return NULL;
2327	Serge	5796
2330	Serge	5797	// obj = dev_priv->fbdev->ifb.obj;
		5798	// if (obj == NULL)
		5799	return NULL;
2327	Serge	5800
2330	Serge	5801	// if (obj->base.size < mode->vdisplay * fb->pitch)
3031	serge	5802	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		5803	fb->bits_per_pixel))
2330	Serge	5804	// return NULL;
2327	Serge	5805
3031	serge	5806	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		5807	return NULL;
		5808
2330	Serge	5809	// return fb;
		5810	}
2327	Serge	5811
3031	serge	5812	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	5813	struct drm_display_mode *mode,
		5814	struct intel_load_detect_pipe *old)
		5815	{
		5816	struct intel_crtc *intel_crtc;
3031	serge	5817	struct intel_encoder *intel_encoder =
		5818	intel_attached_encoder(connector);
2330	Serge	5819	struct drm_crtc *possible_crtc;
		5820	struct drm_encoder *encoder = &intel_encoder->base;
		5821	struct drm_crtc *crtc = NULL;
		5822	struct drm_device *dev = encoder->dev;
3031	serge	5823	struct drm_framebuffer *fb;
2330	Serge	5824	int i = -1;
2327	Serge	5825
2330	Serge	5826	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5827	connector->base.id, drm_get_connector_name(connector),
		5828	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	5829
2330	Serge	5830	/*
		5831	* Algorithm gets a little messy:
		5832	*
		5833	* - if the connector already has an assigned crtc, use it (but make
		5834	* sure it's on first)
		5835	*
		5836	* - try to find the first unused crtc that can drive this connector,
		5837	* and use that if we find one
		5838	*/
2327	Serge	5839
2330	Serge	5840	/* See if we already have a CRTC for this connector */
		5841	if (encoder->crtc) {
		5842	crtc = encoder->crtc;
2327	Serge	5843
3031	serge	5844	old->dpms_mode = connector->dpms;
2330	Serge	5845	old->load_detect_temp = false;
2327	Serge	5846
2330	Serge	5847	/* Make sure the crtc and connector are running */
3031	serge	5848	if (connector->dpms != DRM_MODE_DPMS_ON)
		5849	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	5850
2330	Serge	5851	return true;
		5852	}
2327	Serge	5853
2330	Serge	5854	/* Find an unused one (if possible) */
		5855	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		5856	i++;
		5857	if (!(encoder->possible_crtcs & (1 << i)))
		5858	continue;
		5859	if (!possible_crtc->enabled) {
		5860	crtc = possible_crtc;
		5861	break;
		5862	}
		5863	}
2327	Serge	5864
2330	Serge	5865	/*
		5866	* If we didn't find an unused CRTC, don't use any.
		5867	*/
		5868	if (!crtc) {
		5869	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		5870	return false;
		5871	}
2327	Serge	5872
3031	serge	5873	intel_encoder->new_crtc = to_intel_crtc(crtc);
		5874	to_intel_connector(connector)->new_encoder = intel_encoder;
2327	Serge	5875
2330	Serge	5876	intel_crtc = to_intel_crtc(crtc);
3031	serge	5877	old->dpms_mode = connector->dpms;
2330	Serge	5878	old->load_detect_temp = true;
		5879	old->release_fb = NULL;
2327	Serge	5880
2330	Serge	5881	if (!mode)
		5882	mode = &load_detect_mode;
2327	Serge	5883
2330	Serge	5884	/* We need a framebuffer large enough to accommodate all accesses
		5885	* that the plane may generate whilst we perform load detection.
		5886	* We can not rely on the fbcon either being present (we get called
		5887	* during its initialisation to detect all boot displays, or it may
		5888	* not even exist) or that it is large enough to satisfy the
		5889	* requested mode.
		5890	*/
3031	serge	5891	fb = mode_fits_in_fbdev(dev, mode);
		5892	if (fb == NULL) {
2330	Serge	5893	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	5894	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		5895	old->release_fb = fb;
2330	Serge	5896	} else
		5897	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	5898	if (IS_ERR(fb)) {
2330	Serge	5899	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
3031	serge	5900	goto fail;
2330	Serge	5901	}
2327	Serge	5902
3031	serge	5903	if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
2330	Serge	5904	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		5905	if (old->release_fb)
		5906	old->release_fb->funcs->destroy(old->release_fb);
3031	serge	5907	goto fail;
2330	Serge	5908	}
2327	Serge	5909
2330	Serge	5910	/* let the connector get through one full cycle before testing */
		5911	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	5912
2330	Serge	5913	return true;
3031	serge	5914	fail:
		5915	connector->encoder = NULL;
		5916	encoder->crtc = NULL;
		5917	return false;
2330	Serge	5918	}
2327	Serge	5919
3031	serge	5920	void intel_release_load_detect_pipe(struct drm_connector *connector,
2330	Serge	5921	struct intel_load_detect_pipe *old)
		5922	{
3031	serge	5923	struct intel_encoder *intel_encoder =
		5924	intel_attached_encoder(connector);
2330	Serge	5925	struct drm_encoder *encoder = &intel_encoder->base;
2327	Serge	5926
2330	Serge	5927	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5928	connector->base.id, drm_get_connector_name(connector),
		5929	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	5930
2330	Serge	5931	if (old->load_detect_temp) {
3031	serge	5932	struct drm_crtc *crtc = encoder->crtc;
2327	Serge	5933
3031	serge	5934	to_intel_connector(connector)->new_encoder = NULL;
		5935	intel_encoder->new_crtc = NULL;
		5936	intel_set_mode(crtc, NULL, 0, 0, NULL);
		5937
2330	Serge	5938	if (old->release_fb)
		5939	old->release_fb->funcs->destroy(old->release_fb);
2327	Serge	5940
2330	Serge	5941	return;
		5942	}
2327	Serge	5943
2330	Serge	5944	/* Switch crtc and encoder back off if necessary */
3031	serge	5945	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		5946	connector->funcs->dpms(connector, old->dpms_mode);
2330	Serge	5947	}
2327	Serge	5948
2330	Serge	5949	/* Returns the clock of the currently programmed mode of the given pipe. */
		5950	static int intel_crtc_clock_get(struct drm_device dev, struct drm_crtc crtc)
		5951	{
		5952	struct drm_i915_private *dev_priv = dev->dev_private;
		5953	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5954	int pipe = intel_crtc->pipe;
		5955	u32 dpll = I915_READ(DPLL(pipe));
		5956	u32 fp;
		5957	intel_clock_t clock;
2327	Serge	5958
2330	Serge	5959	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		5960	fp = I915_READ(FP0(pipe));
		5961	else
		5962	fp = I915_READ(FP1(pipe));
2327	Serge	5963
2330	Serge	5964	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		5965	if (IS_PINEVIEW(dev)) {
		5966	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		5967	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		5968	} else {
		5969	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		5970	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		5971	}
2327	Serge	5972
2330	Serge	5973	if (!IS_GEN2(dev)) {
		5974	if (IS_PINEVIEW(dev))
		5975	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		5976	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		5977	else
		5978	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		5979	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	5980
2330	Serge	5981	switch (dpll & DPLL_MODE_MASK) {
		5982	case DPLLB_MODE_DAC_SERIAL:
		5983	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		5984	5 : 10;
		5985	break;
		5986	case DPLLB_MODE_LVDS:
		5987	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		5988	7 : 14;
		5989	break;
		5990	default:
		5991	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		5992	"mode\n", (int)(dpll & DPLL_MODE_MASK));
		5993	return 0;
		5994	}
2327	Serge	5995
2330	Serge	5996	/* XXX: Handle the 100Mhz refclk */
		5997	intel_clock(dev, 96000, &clock);
		5998	} else {
		5999	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	6000
2330	Serge	6001	if (is_lvds) {
		6002	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		6003	DPLL_FPA01_P1_POST_DIV_SHIFT);
		6004	clock.p2 = 14;
2327	Serge	6005
2330	Serge	6006	if ((dpll & PLL_REF_INPUT_MASK) ==
		6007	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		6008	/* XXX: might not be 66MHz */
		6009	intel_clock(dev, 66000, &clock);
		6010	} else
		6011	intel_clock(dev, 48000, &clock);
		6012	} else {
		6013	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		6014	clock.p1 = 2;
		6015	else {
		6016	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		6017	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		6018	}
		6019	if (dpll & PLL_P2_DIVIDE_BY_4)
		6020	clock.p2 = 4;
		6021	else
		6022	clock.p2 = 2;
2327	Serge	6023
2330	Serge	6024	intel_clock(dev, 48000, &clock);
		6025	}
		6026	}
2327	Serge	6027
2330	Serge	6028	/* XXX: It would be nice to validate the clocks, but we can't reuse
		6029	* i830PllIsValid() because it relies on the xf86_config connector
		6030	* configuration being accurate, which it isn't necessarily.
		6031	*/
2327	Serge	6032
2330	Serge	6033	return clock.dot;
		6034	}
2327	Serge	6035
2330	Serge	6036	/** Returns the currently programmed mode of the given pipe. */
		6037	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		6038	struct drm_crtc *crtc)
		6039	{
		6040	struct drm_i915_private *dev_priv = dev->dev_private;
		6041	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6042	int pipe = intel_crtc->pipe;
		6043	struct drm_display_mode *mode;
		6044	int htot = I915_READ(HTOTAL(pipe));
		6045	int hsync = I915_READ(HSYNC(pipe));
		6046	int vtot = I915_READ(VTOTAL(pipe));
		6047	int vsync = I915_READ(VSYNC(pipe));
2327	Serge	6048
2330	Serge	6049	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		6050	if (!mode)
		6051	return NULL;
		6052
		6053	mode->clock = intel_crtc_clock_get(dev, crtc);
		6054	mode->hdisplay = (htot & 0xffff) + 1;
		6055	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		6056	mode->hsync_start = (hsync & 0xffff) + 1;
		6057	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		6058	mode->vdisplay = (vtot & 0xffff) + 1;
		6059	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		6060	mode->vsync_start = (vsync & 0xffff) + 1;
		6061	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		6062
		6063	drm_mode_set_name(mode);
		6064
		6065	return mode;
		6066	}
		6067
2327	Serge	6068	static void intel_increase_pllclock(struct drm_crtc *crtc)
		6069	{
		6070	struct drm_device *dev = crtc->dev;
		6071	drm_i915_private_t *dev_priv = dev->dev_private;
		6072	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6073	int pipe = intel_crtc->pipe;
		6074	int dpll_reg = DPLL(pipe);
		6075	int dpll;
		6076
		6077	if (HAS_PCH_SPLIT(dev))
		6078	return;
		6079
		6080	if (!dev_priv->lvds_downclock_avail)
		6081	return;
		6082
		6083	dpll = I915_READ(dpll_reg);
		6084	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		6085	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		6086
3031	serge	6087	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	6088
		6089	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		6090	I915_WRITE(dpll_reg, dpll);
		6091	intel_wait_for_vblank(dev, pipe);
		6092
		6093	dpll = I915_READ(dpll_reg);
		6094	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		6095	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		6096	}
		6097	}
		6098
3031	serge	6099	static void intel_decrease_pllclock(struct drm_crtc *crtc)
		6100	{
		6101	struct drm_device *dev = crtc->dev;
		6102	drm_i915_private_t *dev_priv = dev->dev_private;
		6103	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6104
3031	serge	6105	if (HAS_PCH_SPLIT(dev))
		6106	return;
2327	Serge	6107
3031	serge	6108	if (!dev_priv->lvds_downclock_avail)
		6109	return;
2327	Serge	6110
3031	serge	6111	/*
		6112	* Since this is called by a timer, we should never get here in
		6113	* the manual case.
		6114	*/
		6115	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		6116	int pipe = intel_crtc->pipe;
		6117	int dpll_reg = DPLL(pipe);
		6118	int dpll;
2327	Serge	6119
3031	serge	6120	DRM_DEBUG_DRIVER("downclocking LVDS\n");
2327	Serge	6121
3031	serge	6122	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	6123
3031	serge	6124	dpll = I915_READ(dpll_reg);
		6125	dpll \|= DISPLAY_RATE_SELECT_FPA1;
		6126	I915_WRITE(dpll_reg, dpll);
		6127	intel_wait_for_vblank(dev, pipe);
		6128	dpll = I915_READ(dpll_reg);
		6129	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
		6130	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
		6131	}
2327	Serge	6132
3031	serge	6133	}
2327	Serge	6134
3031	serge	6135	void intel_mark_busy(struct drm_device *dev)
		6136	{
		6137	i915_update_gfx_val(dev->dev_private);
		6138	}
2327	Serge	6139
3031	serge	6140	void intel_mark_idle(struct drm_device *dev)
		6141	{
		6142	}
2327	Serge	6143
3031	serge	6144	void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
		6145	{
		6146	struct drm_device *dev = obj->base.dev;
		6147	struct drm_crtc *crtc;
2327	Serge	6148
3031	serge	6149	if (!i915_powersave)
		6150	return;
2327	Serge	6151
3031	serge	6152	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		6153	if (!crtc->fb)
		6154	continue;
2327	Serge	6155
3031	serge	6156	if (to_intel_framebuffer(crtc->fb)->obj == obj)
		6157	intel_increase_pllclock(crtc);
		6158	}
		6159	}
2327	Serge	6160
3031	serge	6161	void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
		6162	{
		6163	struct drm_device *dev = obj->base.dev;
		6164	struct drm_crtc *crtc;
2327	Serge	6165
3031	serge	6166	if (!i915_powersave)
		6167	return;
2327	Serge	6168
3031	serge	6169	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		6170	if (!crtc->fb)
		6171	continue;
2327	Serge	6172
3031	serge	6173	if (to_intel_framebuffer(crtc->fb)->obj == obj)
		6174	intel_decrease_pllclock(crtc);
		6175	}
		6176	}
2327	Serge	6177
2330	Serge	6178	static void intel_crtc_destroy(struct drm_crtc *crtc)
		6179	{
		6180	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6181	struct drm_device *dev = crtc->dev;
		6182	struct intel_unpin_work *work;
		6183	unsigned long flags;
2327	Serge	6184
2330	Serge	6185	spin_lock_irqsave(&dev->event_lock, flags);
		6186	work = intel_crtc->unpin_work;
		6187	intel_crtc->unpin_work = NULL;
		6188	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6189
2330	Serge	6190	if (work) {
		6191	// cancel_work_sync(&work->work);
		6192	kfree(work);
		6193	}
2327	Serge	6194
2330	Serge	6195	drm_crtc_cleanup(crtc);
2327	Serge	6196
2330	Serge	6197	kfree(intel_crtc);
		6198	}
2327	Serge	6199
3031	serge	6200	#if 0
		6201	static void intel_unpin_work_fn(struct work_struct *__work)
		6202	{
		6203	struct intel_unpin_work *work =
		6204	container_of(__work, struct intel_unpin_work, work);
2327	Serge	6205
3031	serge	6206	mutex_lock(&work->dev->struct_mutex);
		6207	intel_unpin_fb_obj(work->old_fb_obj);
		6208	drm_gem_object_unreference(&work->pending_flip_obj->base);
		6209	drm_gem_object_unreference(&work->old_fb_obj->base);
2327	Serge	6210
3031	serge	6211	intel_update_fbc(work->dev);
		6212	mutex_unlock(&work->dev->struct_mutex);
		6213	kfree(work);
		6214	}
2327	Serge	6215
3031	serge	6216	static void do_intel_finish_page_flip(struct drm_device *dev,
		6217	struct drm_crtc *crtc)
		6218	{
		6219	drm_i915_private_t *dev_priv = dev->dev_private;
		6220	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6221	struct intel_unpin_work *work;
		6222	struct drm_i915_gem_object *obj;
		6223	struct drm_pending_vblank_event *e;
		6224	struct timeval tvbl;
		6225	unsigned long flags;
2327	Serge	6226
3031	serge	6227	/* Ignore early vblank irqs */
		6228	if (intel_crtc == NULL)
		6229	return;
2327	Serge	6230
3031	serge	6231	spin_lock_irqsave(&dev->event_lock, flags);
		6232	work = intel_crtc->unpin_work;
		6233	if (work == NULL \|\| !work->pending) {
		6234	spin_unlock_irqrestore(&dev->event_lock, flags);
		6235	return;
		6236	}
2327	Serge	6237
3031	serge	6238	intel_crtc->unpin_work = NULL;
2327	Serge	6239
3031	serge	6240	if (work->event) {
		6241	e = work->event;
		6242	e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
2327	Serge	6243
3031	serge	6244	e->event.tv_sec = tvbl.tv_sec;
		6245	e->event.tv_usec = tvbl.tv_usec;
2327	Serge	6246
3031	serge	6247	list_add_tail(&e->base.link,
		6248	&e->base.file_priv->event_list);
		6249	wake_up_interruptible(&e->base.file_priv->event_wait);
		6250	}
2327	Serge	6251
3031	serge	6252	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	6253
3031	serge	6254	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6255
3031	serge	6256	obj = work->old_fb_obj;
2327	Serge	6257
3031	serge	6258	atomic_clear_mask(1 << intel_crtc->plane,
		6259	&obj->pending_flip.counter);
2327	Serge	6260
3031	serge	6261	wake_up(&dev_priv->pending_flip_queue);
		6262	schedule_work(&work->work);
2327	Serge	6263
3031	serge	6264	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
		6265	}
2327	Serge	6266
3031	serge	6267	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		6268	{
		6269	drm_i915_private_t *dev_priv = dev->dev_private;
		6270	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	6271
3031	serge	6272	do_intel_finish_page_flip(dev, crtc);
		6273	}
2327	Serge	6274
3031	serge	6275	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		6276	{
		6277	drm_i915_private_t *dev_priv = dev->dev_private;
		6278	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	6279
3031	serge	6280	do_intel_finish_page_flip(dev, crtc);
		6281	}
2327	Serge	6282
3031	serge	6283	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		6284	{
		6285	drm_i915_private_t *dev_priv = dev->dev_private;
		6286	struct intel_crtc *intel_crtc =
		6287	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		6288	unsigned long flags;
2327	Serge	6289
3031	serge	6290	spin_lock_irqsave(&dev->event_lock, flags);
		6291	if (intel_crtc->unpin_work) {
		6292	if ((++intel_crtc->unpin_work->pending) > 1)
		6293	DRM_ERROR("Prepared flip multiple times\n");
		6294	} else {
		6295	DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
		6296	}
		6297	spin_unlock_irqrestore(&dev->event_lock, flags);
		6298	}
2327	Serge	6299
3031	serge	6300	static int intel_gen2_queue_flip(struct drm_device *dev,
		6301	struct drm_crtc *crtc,
		6302	struct drm_framebuffer *fb,
		6303	struct drm_i915_gem_object *obj)
		6304	{
		6305	struct drm_i915_private *dev_priv = dev->dev_private;
		6306	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6307	u32 flip_mask;
		6308	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		6309	int ret;
2327	Serge	6310
3031	serge	6311	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6312	if (ret)
		6313	goto err;
2327	Serge	6314
3031	serge	6315	ret = intel_ring_begin(ring, 6);
		6316	if (ret)
		6317	goto err_unpin;
2327	Serge	6318
3031	serge	6319	/* Can't queue multiple flips, so wait for the previous
		6320	* one to finish before executing the next.
		6321	*/
		6322	if (intel_crtc->plane)
		6323	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		6324	else
		6325	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		6326	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		6327	intel_ring_emit(ring, MI_NOOP);
		6328	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		6329	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		6330	intel_ring_emit(ring, fb->pitches[0]);
		6331	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		6332	intel_ring_emit(ring, 0); /* aux display base address, unused */
		6333	intel_ring_advance(ring);
		6334	return 0;
2327	Serge	6335
3031	serge	6336	err_unpin:
		6337	intel_unpin_fb_obj(obj);
		6338	err:
		6339	return ret;
		6340	}
2327	Serge	6341
3031	serge	6342	static int intel_gen3_queue_flip(struct drm_device *dev,
		6343	struct drm_crtc *crtc,
		6344	struct drm_framebuffer *fb,
		6345	struct drm_i915_gem_object *obj)
		6346	{
		6347	struct drm_i915_private *dev_priv = dev->dev_private;
		6348	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6349	u32 flip_mask;
		6350	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		6351	int ret;
2327	Serge	6352
3031	serge	6353	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6354	if (ret)
		6355	goto err;
2327	Serge	6356
3031	serge	6357	ret = intel_ring_begin(ring, 6);
		6358	if (ret)
		6359	goto err_unpin;
2327	Serge	6360
3031	serge	6361	if (intel_crtc->plane)
		6362	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		6363	else
		6364	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		6365	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		6366	intel_ring_emit(ring, MI_NOOP);
		6367	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		6368	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		6369	intel_ring_emit(ring, fb->pitches[0]);
		6370	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		6371	intel_ring_emit(ring, MI_NOOP);
2327	Serge	6372
3031	serge	6373	intel_ring_advance(ring);
		6374	return 0;
2327	Serge	6375
3031	serge	6376	err_unpin:
		6377	intel_unpin_fb_obj(obj);
		6378	err:
		6379	return ret;
		6380	}
2327	Serge	6381
3031	serge	6382	static int intel_gen4_queue_flip(struct drm_device *dev,
		6383	struct drm_crtc *crtc,
		6384	struct drm_framebuffer *fb,
		6385	struct drm_i915_gem_object *obj)
		6386	{
		6387	struct drm_i915_private *dev_priv = dev->dev_private;
		6388	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6389	uint32_t pf, pipesrc;
		6390	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		6391	int ret;
2327	Serge	6392
3031	serge	6393	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6394	if (ret)
		6395	goto err;
2327	Serge	6396
3031	serge	6397	ret = intel_ring_begin(ring, 4);
		6398	if (ret)
		6399	goto err_unpin;
2327	Serge	6400
3031	serge	6401	/* i965+ uses the linear or tiled offsets from the
		6402	* Display Registers (which do not change across a page-flip)
		6403	* so we need only reprogram the base address.
		6404	*/
		6405	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		6406	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		6407	intel_ring_emit(ring, fb->pitches[0]);
		6408	intel_ring_emit(ring,
		6409	(obj->gtt_offset + intel_crtc->dspaddr_offset) \|
		6410	obj->tiling_mode);
2327	Serge	6411
3031	serge	6412	/* XXX Enabling the panel-fitter across page-flip is so far
		6413	* untested on non-native modes, so ignore it for now.
		6414	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		6415	*/
		6416	pf = 0;
		6417	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		6418	intel_ring_emit(ring, pf \| pipesrc);
		6419	intel_ring_advance(ring);
		6420	return 0;
2327	Serge	6421
3031	serge	6422	err_unpin:
		6423	intel_unpin_fb_obj(obj);
		6424	err:
		6425	return ret;
		6426	}
2327	Serge	6427
3031	serge	6428	static int intel_gen6_queue_flip(struct drm_device *dev,
		6429	struct drm_crtc *crtc,
		6430	struct drm_framebuffer *fb,
		6431	struct drm_i915_gem_object *obj)
		6432	{
		6433	struct drm_i915_private *dev_priv = dev->dev_private;
		6434	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6435	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		6436	uint32_t pf, pipesrc;
		6437	int ret;
2327	Serge	6438
3031	serge	6439	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6440	if (ret)
		6441	goto err;
2327	Serge	6442
3031	serge	6443	ret = intel_ring_begin(ring, 4);
		6444	if (ret)
		6445	goto err_unpin;
2327	Serge	6446
3031	serge	6447	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		6448	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		6449	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
		6450	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
2327	Serge	6451
3031	serge	6452	/* Contrary to the suggestions in the documentation,
		6453	* "Enable Panel Fitter" does not seem to be required when page
		6454	* flipping with a non-native mode, and worse causes a normal
		6455	* modeset to fail.
		6456	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		6457	*/
		6458	pf = 0;
		6459	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		6460	intel_ring_emit(ring, pf \| pipesrc);
		6461	intel_ring_advance(ring);
		6462	return 0;
2327	Serge	6463
3031	serge	6464	err_unpin:
		6465	intel_unpin_fb_obj(obj);
		6466	err:
		6467	return ret;
		6468	}
2327	Serge	6469
3031	serge	6470	/*
		6471	* On gen7 we currently use the blit ring because (in early silicon at least)
		6472	* the render ring doesn't give us interrpts for page flip completion, which
		6473	* means clients will hang after the first flip is queued. Fortunately the
		6474	* blit ring generates interrupts properly, so use it instead.
		6475	*/
		6476	static int intel_gen7_queue_flip(struct drm_device *dev,
		6477	struct drm_crtc *crtc,
		6478	struct drm_framebuffer *fb,
		6479	struct drm_i915_gem_object *obj)
		6480	{
		6481	struct drm_i915_private *dev_priv = dev->dev_private;
		6482	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6483	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
		6484	uint32_t plane_bit = 0;
		6485	int ret;
2327	Serge	6486
3031	serge	6487	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6488	if (ret)
		6489	goto err;
2327	Serge	6490
3031	serge	6491	switch(intel_crtc->plane) {
		6492	case PLANE_A:
		6493	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		6494	break;
		6495	case PLANE_B:
		6496	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		6497	break;
		6498	case PLANE_C:
		6499	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		6500	break;
		6501	default:
		6502	WARN_ONCE(1, "unknown plane in flip command\n");
		6503	ret = -ENODEV;
		6504	goto err_unpin;
		6505	}
2327	Serge	6506
3031	serge	6507	ret = intel_ring_begin(ring, 4);
		6508	if (ret)
		6509	goto err_unpin;
2327	Serge	6510
3031	serge	6511	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		6512	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
		6513	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		6514	intel_ring_emit(ring, (MI_NOOP));
		6515	intel_ring_advance(ring);
		6516	return 0;
2327	Serge	6517
3031	serge	6518	err_unpin:
		6519	intel_unpin_fb_obj(obj);
		6520	err:
		6521	return ret;
		6522	}
2327	Serge	6523
3031	serge	6524	static int intel_default_queue_flip(struct drm_device *dev,
		6525	struct drm_crtc *crtc,
		6526	struct drm_framebuffer *fb,
		6527	struct drm_i915_gem_object *obj)
		6528	{
		6529	return -ENODEV;
		6530	}
2327	Serge	6531
3031	serge	6532	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		6533	struct drm_framebuffer *fb,
		6534	struct drm_pending_vblank_event *event)
		6535	{
		6536	struct drm_device *dev = crtc->dev;
		6537	struct drm_i915_private *dev_priv = dev->dev_private;
		6538	struct intel_framebuffer *intel_fb;
		6539	struct drm_i915_gem_object *obj;
		6540	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6541	struct intel_unpin_work *work;
		6542	unsigned long flags;
		6543	int ret;
2327	Serge	6544
3031	serge	6545	/* Can't change pixel format via MI display flips. */
		6546	if (fb->pixel_format != crtc->fb->pixel_format)
		6547	return -EINVAL;
2327	Serge	6548
3031	serge	6549	/*
		6550	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		6551	* Note that pitch changes could also affect these register.
		6552	*/
		6553	if (INTEL_INFO(dev)->gen > 3 &&
		6554	(fb->offsets[0] != crtc->fb->offsets[0] \|\|
		6555	fb->pitches[0] != crtc->fb->pitches[0]))
		6556	return -EINVAL;
2327	Serge	6557
3031	serge	6558	work = kzalloc(sizeof *work, GFP_KERNEL);
		6559	if (work == NULL)
		6560	return -ENOMEM;
2327	Serge	6561
3031	serge	6562	work->event = event;
		6563	work->dev = crtc->dev;
		6564	intel_fb = to_intel_framebuffer(crtc->fb);
		6565	work->old_fb_obj = intel_fb->obj;
		6566	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	6567
3031	serge	6568	ret = drm_vblank_get(dev, intel_crtc->pipe);
		6569	if (ret)
		6570	goto free_work;
2327	Serge	6571
3031	serge	6572	/* We borrow the event spin lock for protecting unpin_work */
		6573	spin_lock_irqsave(&dev->event_lock, flags);
		6574	if (intel_crtc->unpin_work) {
		6575	spin_unlock_irqrestore(&dev->event_lock, flags);
		6576	kfree(work);
		6577	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	6578
3031	serge	6579	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		6580	return -EBUSY;
		6581	}
		6582	intel_crtc->unpin_work = work;
		6583	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6584
3031	serge	6585	intel_fb = to_intel_framebuffer(fb);
		6586	obj = intel_fb->obj;
2327	Serge	6587
3031	serge	6588	ret = i915_mutex_lock_interruptible(dev);
		6589	if (ret)
		6590	goto cleanup;
2327	Serge	6591
3031	serge	6592	/* Reference the objects for the scheduled work. */
		6593	drm_gem_object_reference(&work->old_fb_obj->base);
		6594	drm_gem_object_reference(&obj->base);
2327	Serge	6595
3031	serge	6596	crtc->fb = fb;
2327	Serge	6597
3031	serge	6598	work->pending_flip_obj = obj;
2327	Serge	6599
3031	serge	6600	work->enable_stall_check = true;
		6601
		6602	/* Block clients from rendering to the new back buffer until
		6603	* the flip occurs and the object is no longer visible.
		6604	*/
		6605	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
		6606
		6607	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
		6608	if (ret)
		6609	goto cleanup_pending;
		6610
		6611	intel_disable_fbc(dev);
		6612	intel_mark_fb_busy(obj);
		6613	mutex_unlock(&dev->struct_mutex);
		6614
		6615	trace_i915_flip_request(intel_crtc->plane, obj);
		6616
		6617	return 0;
		6618
		6619	cleanup_pending:
		6620	atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
		6621	drm_gem_object_unreference(&work->old_fb_obj->base);
		6622	drm_gem_object_unreference(&obj->base);
		6623	mutex_unlock(&dev->struct_mutex);
		6624
		6625	cleanup:
		6626	spin_lock_irqsave(&dev->event_lock, flags);
		6627	intel_crtc->unpin_work = NULL;
		6628	spin_unlock_irqrestore(&dev->event_lock, flags);
		6629
		6630	drm_vblank_put(dev, intel_crtc->pipe);
		6631	free_work:
		6632	kfree(work);
		6633
		6634	return ret;
		6635	}
		6636
		6637	#endif
		6638
		6639	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		6640	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		6641	.load_lut = intel_crtc_load_lut,
		6642	.disable = intel_crtc_noop,
		6643	};
		6644
		6645	bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
2330	Serge	6646	{
3031	serge	6647	struct intel_encoder *other_encoder;
		6648	struct drm_crtc *crtc = &encoder->new_crtc->base;
2327	Serge	6649
3031	serge	6650	if (WARN_ON(!crtc))
		6651	return false;
2327	Serge	6652
3031	serge	6653	list_for_each_entry(other_encoder,
		6654	&crtc->dev->mode_config.encoder_list,
		6655	base.head) {
		6656
		6657	if (&other_encoder->new_crtc->base != crtc \|\|
		6658	encoder == other_encoder)
		6659	continue;
		6660	else
		6661	return true;
		6662	}
		6663
		6664	return false;
		6665	}
		6666
		6667	static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
		6668	struct drm_crtc *crtc)
		6669	{
		6670	struct drm_device *dev;
		6671	struct drm_crtc *tmp;
		6672	int crtc_mask = 1;
		6673
		6674	WARN(!crtc, "checking null crtc?\n");
		6675
		6676	dev = crtc->dev;
		6677
		6678	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		6679	if (tmp == crtc)
		6680	break;
		6681	crtc_mask <<= 1;
		6682	}
		6683
		6684	if (encoder->possible_crtcs & crtc_mask)
		6685	return true;
		6686	return false;
		6687	}
		6688
		6689	/**
		6690	* intel_modeset_update_staged_output_state
		6691	*
		6692	* Updates the staged output configuration state, e.g. after we've read out the
		6693	* current hw state.
		6694	*/
		6695	static void intel_modeset_update_staged_output_state(struct drm_device *dev)
		6696	{
		6697	struct intel_encoder *encoder;
		6698	struct intel_connector *connector;
		6699
		6700	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6701	base.head) {
		6702	connector->new_encoder =
		6703	to_intel_encoder(connector->base.encoder);
		6704	}
		6705
		6706	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6707	base.head) {
		6708	encoder->new_crtc =
		6709	to_intel_crtc(encoder->base.crtc);
		6710	}
		6711	}
		6712
		6713	/**
		6714	* intel_modeset_commit_output_state
		6715	*
		6716	* This function copies the stage display pipe configuration to the real one.
		6717	*/
		6718	static void intel_modeset_commit_output_state(struct drm_device *dev)
		6719	{
		6720	struct intel_encoder *encoder;
		6721	struct intel_connector *connector;
		6722
		6723	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6724	base.head) {
		6725	connector->base.encoder = &connector->new_encoder->base;
		6726	}
		6727
		6728	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6729	base.head) {
		6730	encoder->base.crtc = &encoder->new_crtc->base;
		6731	}
		6732	}
		6733
		6734	static struct drm_display_mode *
		6735	intel_modeset_adjusted_mode(struct drm_crtc *crtc,
		6736	struct drm_display_mode *mode)
		6737	{
		6738	struct drm_device *dev = crtc->dev;
		6739	struct drm_display_mode *adjusted_mode;
		6740	struct drm_encoder_helper_funcs *encoder_funcs;
		6741	struct intel_encoder *encoder;
		6742
		6743	adjusted_mode = drm_mode_duplicate(dev, mode);
		6744	if (!adjusted_mode)
		6745	return ERR_PTR(-ENOMEM);
		6746
		6747	/* Pass our mode to the connectors and the CRTC to give them a chance to
		6748	* adjust it according to limitations or connector properties, and also
		6749	* a chance to reject the mode entirely.
2330	Serge	6750	*/
3031	serge	6751	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6752	base.head) {
2327	Serge	6753
3031	serge	6754	if (&encoder->new_crtc->base != crtc)
		6755	continue;
		6756	encoder_funcs = encoder->base.helper_private;
		6757	if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
		6758	adjusted_mode))) {
		6759	DRM_DEBUG_KMS("Encoder fixup failed\n");
		6760	goto fail;
		6761	}
		6762	}
2327	Serge	6763
3031	serge	6764	if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
		6765	DRM_DEBUG_KMS("CRTC fixup failed\n");
		6766	goto fail;
		6767	}
		6768	DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
2327	Serge	6769
3031	serge	6770	return adjusted_mode;
		6771	fail:
		6772	drm_mode_destroy(dev, adjusted_mode);
		6773	return ERR_PTR(-EINVAL);
		6774	}
2327	Serge	6775
3031	serge	6776	/* Computes which crtcs are affected and sets the relevant bits in the mask. For
		6777	* simplicity we use the crtc's pipe number (because it's easier to obtain). */
		6778	static void
		6779	intel_modeset_affected_pipes(struct drm_crtc crtc, unsigned modeset_pipes,
		6780	unsigned prepare_pipes, unsigned disable_pipes)
		6781	{
		6782	struct intel_crtc *intel_crtc;
		6783	struct drm_device *dev = crtc->dev;
		6784	struct intel_encoder *encoder;
		6785	struct intel_connector *connector;
		6786	struct drm_crtc *tmp_crtc;
		6787
		6788	disable_pipes = modeset_pipes = *prepare_pipes = 0;
		6789
		6790	/* Check which crtcs have changed outputs connected to them, these need
		6791	* to be part of the prepare_pipes mask. We don't (yet) support global
		6792	* modeset across multiple crtcs, so modeset_pipes will only have one
		6793	* bit set at most. */
		6794	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6795	base.head) {
		6796	if (connector->base.encoder == &connector->new_encoder->base)
		6797	continue;
		6798
		6799	if (connector->base.encoder) {
		6800	tmp_crtc = connector->base.encoder->crtc;
		6801
		6802	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		6803	}
		6804
		6805	if (connector->new_encoder)
		6806	*prepare_pipes \|=
		6807	1 << connector->new_encoder->new_crtc->pipe;
		6808	}
		6809
		6810	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6811	base.head) {
		6812	if (encoder->base.crtc == &encoder->new_crtc->base)
		6813	continue;
		6814
		6815	if (encoder->base.crtc) {
		6816	tmp_crtc = encoder->base.crtc;
		6817
		6818	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		6819	}
		6820
		6821	if (encoder->new_crtc)
		6822	*prepare_pipes \|= 1 << encoder->new_crtc->pipe;
		6823	}
		6824
		6825	/* Check for any pipes that will be fully disabled ... */
		6826	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		6827	base.head) {
		6828	bool used = false;
		6829
		6830	/* Don't try to disable disabled crtcs. */
		6831	if (!intel_crtc->base.enabled)
		6832	continue;
		6833
		6834	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6835	base.head) {
		6836	if (encoder->new_crtc == intel_crtc)
		6837	used = true;
		6838	}
		6839
		6840	if (!used)
		6841	*disable_pipes \|= 1 << intel_crtc->pipe;
		6842	}
		6843
		6844
		6845	/* set_mode is also used to update properties on life display pipes. */
		6846	intel_crtc = to_intel_crtc(crtc);
		6847	if (crtc->enabled)
		6848	*prepare_pipes \|= 1 << intel_crtc->pipe;
		6849
		6850	/* We only support modeset on one single crtc, hence we need to do that
		6851	* only for the passed in crtc iff we change anything else than just
		6852	* disable crtcs.
		6853	*
		6854	* This is actually not true, to be fully compatible with the old crtc
		6855	* helper we automatically disable _any_ output (i.e. doesn't need to be
		6856	* connected to the crtc we're modesetting on) if it's disconnected.
		6857	* Which is a rather nutty api (since changed the output configuration
		6858	* without userspace's explicit request can lead to confusion), but
		6859	* alas. Hence we currently need to modeset on all pipes we prepare. */
		6860	if (*prepare_pipes)
		6861	modeset_pipes = prepare_pipes;
		6862
		6863	/* ... and mask these out. */
		6864	modeset_pipes &= ~(disable_pipes);
		6865	prepare_pipes &= ~(disable_pipes);
2330	Serge	6866	}
2327	Serge	6867
3031	serge	6868	static bool intel_crtc_in_use(struct drm_crtc *crtc)
2330	Serge	6869	{
3031	serge	6870	struct drm_encoder *encoder;
2330	Serge	6871	struct drm_device *dev = crtc->dev;
2327	Serge	6872
3031	serge	6873	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		6874	if (encoder->crtc == crtc)
		6875	return true;
		6876
		6877	return false;
		6878	}
		6879
		6880	static void
		6881	intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
		6882	{
		6883	struct intel_encoder *intel_encoder;
		6884	struct intel_crtc *intel_crtc;
		6885	struct drm_connector *connector;
		6886
		6887	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
		6888	base.head) {
		6889	if (!intel_encoder->base.crtc)
		6890	continue;
		6891
		6892	intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
		6893
		6894	if (prepare_pipes & (1 << intel_crtc->pipe))
		6895	intel_encoder->connectors_active = false;
		6896	}
		6897
		6898	intel_modeset_commit_output_state(dev);
		6899
		6900	/* Update computed state. */
		6901	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		6902	base.head) {
		6903	intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
		6904	}
		6905
		6906	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		6907	if (!connector->encoder \|\| !connector->encoder->crtc)
		6908	continue;
		6909
		6910	intel_crtc = to_intel_crtc(connector->encoder->crtc);
		6911
		6912	if (prepare_pipes & (1 << intel_crtc->pipe)) {
		6913	struct drm_property *dpms_property =
		6914	dev->mode_config.dpms_property;
		6915
		6916	connector->dpms = DRM_MODE_DPMS_ON;
		6917	drm_connector_property_set_value(connector,
		6918	dpms_property,
		6919	DRM_MODE_DPMS_ON);
		6920
		6921	intel_encoder = to_intel_encoder(connector->encoder);
		6922	intel_encoder->connectors_active = true;
		6923	}
		6924	}
		6925
		6926	}
		6927
		6928	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		6929	list_for_each_entry((intel_crtc), \
		6930	&(dev)->mode_config.crtc_list, \
		6931	base.head) \
		6932	if (mask & (1 <<(intel_crtc)->pipe)) \
		6933
		6934	void
		6935	intel_modeset_check_state(struct drm_device *dev)
		6936	{
		6937	struct intel_crtc *crtc;
		6938	struct intel_encoder *encoder;
		6939	struct intel_connector *connector;
		6940
		6941	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6942	base.head) {
		6943	/* This also checks the encoder/connector hw state with the
		6944	* ->get_hw_state callbacks. */
		6945	intel_connector_check_state(connector);
		6946
		6947	WARN(&connector->new_encoder->base != connector->base.encoder,
		6948	"connector's staged encoder doesn't match current encoder\n");
		6949	}
		6950
		6951	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6952	base.head) {
		6953	bool enabled = false;
		6954	bool active = false;
		6955	enum pipe pipe, tracked_pipe;
		6956
		6957	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		6958	encoder->base.base.id,
		6959	drm_get_encoder_name(&encoder->base));
		6960
		6961	WARN(&encoder->new_crtc->base != encoder->base.crtc,
		6962	"encoder's stage crtc doesn't match current crtc\n");
		6963	WARN(encoder->connectors_active && !encoder->base.crtc,
		6964	"encoder's active_connectors set, but no crtc\n");
		6965
		6966	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6967	base.head) {
		6968	if (connector->base.encoder != &encoder->base)
		6969	continue;
		6970	enabled = true;
		6971	if (connector->base.dpms != DRM_MODE_DPMS_OFF)
		6972	active = true;
		6973	}
		6974	WARN(!!encoder->base.crtc != enabled,
		6975	"encoder's enabled state mismatch "
		6976	"(expected %i, found %i)\n",
		6977	!!encoder->base.crtc, enabled);
		6978	WARN(active && !encoder->base.crtc,
		6979	"active encoder with no crtc\n");
		6980
		6981	WARN(encoder->connectors_active != active,
		6982	"encoder's computed active state doesn't match tracked active state "
		6983	"(expected %i, found %i)\n", active, encoder->connectors_active);
		6984
		6985	active = encoder->get_hw_state(encoder, &pipe);
		6986	WARN(active != encoder->connectors_active,
		6987	"encoder's hw state doesn't match sw tracking "
		6988	"(expected %i, found %i)\n",
		6989	encoder->connectors_active, active);
		6990
		6991	if (!encoder->base.crtc)
		6992	continue;
		6993
		6994	tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		6995	WARN(active && pipe != tracked_pipe,
		6996	"active encoder's pipe doesn't match"
		6997	"(expected %i, found %i)\n",
		6998	tracked_pipe, pipe);
		6999
		7000	}
		7001
		7002	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		7003	base.head) {
		7004	bool enabled = false;
		7005	bool active = false;
		7006
		7007	DRM_DEBUG_KMS("[CRTC:%d]\n",
		7008	crtc->base.base.id);
		7009
		7010	WARN(crtc->active && !crtc->base.enabled,
		7011	"active crtc, but not enabled in sw tracking\n");
		7012
		7013	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7014	base.head) {
		7015	if (encoder->base.crtc != &crtc->base)
		7016	continue;
		7017	enabled = true;
		7018	if (encoder->connectors_active)
		7019	active = true;
		7020	}
		7021	WARN(active != crtc->active,
		7022	"crtc's computed active state doesn't match tracked active state "
		7023	"(expected %i, found %i)\n", active, crtc->active);
		7024	WARN(enabled != crtc->base.enabled,
		7025	"crtc's computed enabled state doesn't match tracked enabled state "
		7026	"(expected %i, found %i)\n", enabled, crtc->base.enabled);
		7027
		7028	assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
		7029	}
		7030	}
		7031
		7032	bool intel_set_mode(struct drm_crtc *crtc,
		7033	struct drm_display_mode *mode,
		7034	int x, int y, struct drm_framebuffer *fb)
		7035	{
		7036	struct drm_device *dev = crtc->dev;
		7037	drm_i915_private_t *dev_priv = dev->dev_private;
		7038	struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
		7039	struct drm_encoder_helper_funcs *encoder_funcs;
		7040	struct drm_encoder *encoder;
		7041	struct intel_crtc *intel_crtc;
		7042	unsigned disable_pipes, prepare_pipes, modeset_pipes;
		7043	bool ret = true;
		7044
		7045	intel_modeset_affected_pipes(crtc, &modeset_pipes,
		7046	&prepare_pipes, &disable_pipes);
		7047
		7048	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		7049	modeset_pipes, prepare_pipes, disable_pipes);
		7050
		7051	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		7052	intel_crtc_disable(&intel_crtc->base);
		7053
		7054	saved_hwmode = crtc->hwmode;
		7055	saved_mode = crtc->mode;
		7056
		7057	/* Hack: Because we don't (yet) support global modeset on multiple
		7058	* crtcs, we don't keep track of the new mode for more than one crtc.
		7059	* Hence simply check whether any bit is set in modeset_pipes in all the
		7060	* pieces of code that are not yet converted to deal with mutliple crtcs
		7061	* changing their mode at the same time. */
		7062	adjusted_mode = NULL;
		7063	if (modeset_pipes) {
		7064	adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
		7065	if (IS_ERR(adjusted_mode)) {
		7066	return false;
		7067	}
		7068	}
		7069
		7070	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		7071	if (intel_crtc->base.enabled)
		7072	dev_priv->display.crtc_disable(&intel_crtc->base);
		7073	}
		7074
		7075	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
		7076	* to set it here already despite that we pass it down the callchain.
2330	Serge	7077	*/
3031	serge	7078	if (modeset_pipes)
		7079	crtc->mode = *mode;
2327	Serge	7080
3031	serge	7081	/* Only after disabling all output pipelines that will be changed can we
		7082	* update the the output configuration. */
		7083	intel_modeset_update_state(dev, prepare_pipes);
		7084
		7085	/* Set up the DPLL and any encoders state that needs to adjust or depend
		7086	* on the DPLL.
2330	Serge	7087	*/
3031	serge	7088	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
		7089	ret = !intel_crtc_mode_set(&intel_crtc->base,
		7090	mode, adjusted_mode,
		7091	x, y, fb);
		7092	if (!ret)
		7093	goto done;
		7094
		7095	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		7096
		7097	if (encoder->crtc != &intel_crtc->base)
		7098	continue;
		7099
		7100	DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
		7101	encoder->base.id, drm_get_encoder_name(encoder),
		7102	mode->base.id, mode->name);
		7103	encoder_funcs = encoder->helper_private;
		7104	encoder_funcs->mode_set(encoder, mode, adjusted_mode);
		7105	}
		7106	}
		7107
		7108	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
		7109	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		7110	dev_priv->display.crtc_enable(&intel_crtc->base);
		7111
		7112	if (modeset_pipes) {
		7113	/* Store real post-adjustment hardware mode. */
		7114	crtc->hwmode = *adjusted_mode;
		7115
		7116	/* Calculate and store various constants which
		7117	* are later needed by vblank and swap-completion
		7118	* timestamping. They are derived from true hwmode.
		7119	*/
		7120	drm_calc_timestamping_constants(crtc);
		7121	}
		7122
		7123	/* FIXME: add subpixel order */
		7124	done:
		7125	drm_mode_destroy(dev, adjusted_mode);
		7126	if (!ret && crtc->enabled) {
		7127	crtc->hwmode = saved_hwmode;
		7128	crtc->mode = saved_mode;
		7129	} else {
		7130	intel_modeset_check_state(dev);
		7131	}
		7132
		7133	return ret;
2330	Serge	7134	}
2327	Serge	7135
3031	serge	7136	#undef for_each_intel_crtc_masked
2327	Serge	7137
3031	serge	7138	static void intel_set_config_free(struct intel_set_config *config)
		7139	{
		7140	if (!config)
		7141	return;
		7142
		7143	kfree(config->save_connector_encoders);
		7144	kfree(config->save_encoder_crtcs);
		7145	kfree(config);
		7146	}
		7147
		7148	static int intel_set_config_save_state(struct drm_device *dev,
		7149	struct intel_set_config *config)
		7150	{
		7151	struct drm_encoder *encoder;
		7152	struct drm_connector *connector;
		7153	int count;
		7154
		7155	config->save_encoder_crtcs =
		7156	kcalloc(dev->mode_config.num_encoder,
		7157	sizeof(struct drm_crtc *), GFP_KERNEL);
		7158	if (!config->save_encoder_crtcs)
		7159	return -ENOMEM;
		7160
		7161	config->save_connector_encoders =
		7162	kcalloc(dev->mode_config.num_connector,
		7163	sizeof(struct drm_encoder *), GFP_KERNEL);
		7164	if (!config->save_connector_encoders)
		7165	return -ENOMEM;
		7166
		7167	/* Copy data. Note that driver private data is not affected.
		7168	* Should anything bad happen only the expected state is
		7169	* restored, not the drivers personal bookkeeping.
		7170	*/
		7171	count = 0;
		7172	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		7173	config->save_encoder_crtcs[count++] = encoder->crtc;
		7174	}
		7175
		7176	count = 0;
		7177	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		7178	config->save_connector_encoders[count++] = connector->encoder;
		7179	}
		7180
		7181	return 0;
		7182	}
		7183
		7184	static void intel_set_config_restore_state(struct drm_device *dev,
		7185	struct intel_set_config *config)
		7186	{
		7187	struct intel_encoder *encoder;
		7188	struct intel_connector *connector;
		7189	int count;
		7190
		7191	count = 0;
		7192	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		7193	encoder->new_crtc =
		7194	to_intel_crtc(config->save_encoder_crtcs[count++]);
		7195	}
		7196
		7197	count = 0;
		7198	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		7199	connector->new_encoder =
		7200	to_intel_encoder(config->save_connector_encoders[count++]);
		7201	}
		7202	}
		7203
		7204	static void
		7205	intel_set_config_compute_mode_changes(struct drm_mode_set *set,
		7206	struct intel_set_config *config)
		7207	{
		7208
		7209	/* We should be able to check here if the fb has the same properties
		7210	* and then just flip_or_move it */
		7211	if (set->crtc->fb != set->fb) {
		7212	/* If we have no fb then treat it as a full mode set */
		7213	if (set->crtc->fb == NULL) {
		7214	DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
		7215	config->mode_changed = true;
		7216	} else if (set->fb == NULL) {
		7217	config->mode_changed = true;
		7218	} else if (set->fb->depth != set->crtc->fb->depth) {
		7219	config->mode_changed = true;
		7220	} else if (set->fb->bits_per_pixel !=
		7221	set->crtc->fb->bits_per_pixel) {
		7222	config->mode_changed = true;
		7223	} else
		7224	config->fb_changed = true;
		7225	}
		7226
		7227	if (set->fb && (set->x != set->crtc->x \|\| set->y != set->crtc->y))
		7228	config->fb_changed = true;
		7229
		7230	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		7231	DRM_DEBUG_KMS("modes are different, full mode set\n");
		7232	drm_mode_debug_printmodeline(&set->crtc->mode);
		7233	drm_mode_debug_printmodeline(set->mode);
		7234	config->mode_changed = true;
		7235	}
		7236	}
		7237
		7238	static int
		7239	intel_modeset_stage_output_state(struct drm_device *dev,
		7240	struct drm_mode_set *set,
		7241	struct intel_set_config *config)
		7242	{
		7243	struct drm_crtc *new_crtc;
		7244	struct intel_connector *connector;
		7245	struct intel_encoder *encoder;
		7246	int count, ro;
		7247
		7248	/* The upper layers ensure that we either disabl a crtc or have a list
		7249	* of connectors. For paranoia, double-check this. */
		7250	WARN_ON(!set->fb && (set->num_connectors != 0));
		7251	WARN_ON(set->fb && (set->num_connectors == 0));
		7252
		7253	count = 0;
		7254	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7255	base.head) {
		7256	/* Otherwise traverse passed in connector list and get encoders
		7257	* for them. */
		7258	for (ro = 0; ro < set->num_connectors; ro++) {
		7259	if (set->connectors[ro] == &connector->base) {
		7260	connector->new_encoder = connector->encoder;
		7261	break;
		7262	}
		7263	}
		7264
		7265	/* If we disable the crtc, disable all its connectors. Also, if
		7266	* the connector is on the changing crtc but not on the new
		7267	* connector list, disable it. */
		7268	if ((!set->fb \|\| ro == set->num_connectors) &&
		7269	connector->base.encoder &&
		7270	connector->base.encoder->crtc == set->crtc) {
		7271	connector->new_encoder = NULL;
		7272
		7273	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
		7274	connector->base.base.id,
		7275	drm_get_connector_name(&connector->base));
		7276	}
		7277
		7278
		7279	if (&connector->new_encoder->base != connector->base.encoder) {
		7280	DRM_DEBUG_KMS("encoder changed, full mode switch\n");
		7281	config->mode_changed = true;
		7282	}
		7283
		7284	/* Disable all disconnected encoders. */
		7285	if (connector->base.status == connector_status_disconnected)
		7286	connector->new_encoder = NULL;
		7287	}
		7288	/* connector->new_encoder is now updated for all connectors. */
		7289
		7290	/* Update crtc of enabled connectors. */
		7291	count = 0;
		7292	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7293	base.head) {
		7294	if (!connector->new_encoder)
		7295	continue;
		7296
		7297	new_crtc = connector->new_encoder->base.crtc;
		7298
		7299	for (ro = 0; ro < set->num_connectors; ro++) {
		7300	if (set->connectors[ro] == &connector->base)
		7301	new_crtc = set->crtc;
		7302	}
		7303
		7304	/* Make sure the new CRTC will work with the encoder */
		7305	if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
		7306	new_crtc)) {
		7307	return -EINVAL;
		7308	}
		7309	connector->encoder->new_crtc = to_intel_crtc(new_crtc);
		7310
		7311	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
		7312	connector->base.base.id,
		7313	drm_get_connector_name(&connector->base),
		7314	new_crtc->base.id);
		7315	}
		7316
		7317	/* Check for any encoders that needs to be disabled. */
		7318	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7319	base.head) {
		7320	list_for_each_entry(connector,
		7321	&dev->mode_config.connector_list,
		7322	base.head) {
		7323	if (connector->new_encoder == encoder) {
		7324	WARN_ON(!connector->new_encoder->new_crtc);
		7325
		7326	goto next_encoder;
		7327	}
		7328	}
		7329	encoder->new_crtc = NULL;
		7330	next_encoder:
		7331	/* Only now check for crtc changes so we don't miss encoders
		7332	* that will be disabled. */
		7333	if (&encoder->new_crtc->base != encoder->base.crtc) {
		7334	DRM_DEBUG_KMS("crtc changed, full mode switch\n");
		7335	config->mode_changed = true;
		7336	}
		7337	}
		7338	/* Now we've also updated encoder->new_crtc for all encoders. */
		7339
		7340	return 0;
		7341	}
		7342
		7343	static int intel_crtc_set_config(struct drm_mode_set *set)
		7344	{
		7345	struct drm_device *dev;
		7346	struct drm_mode_set save_set;
		7347	struct intel_set_config *config;
		7348	int ret;
		7349
		7350	BUG_ON(!set);
		7351	BUG_ON(!set->crtc);
		7352	BUG_ON(!set->crtc->helper_private);
		7353
		7354	if (!set->mode)
		7355	set->fb = NULL;
		7356
		7357	/* The fb helper likes to play gross jokes with ->mode_set_config.
		7358	* Unfortunately the crtc helper doesn't do much at all for this case,
		7359	* so we have to cope with this madness until the fb helper is fixed up. */
		7360	if (set->fb && set->num_connectors == 0)
		7361	return 0;
		7362
		7363	if (set->fb) {
		7364	DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
		7365	set->crtc->base.id, set->fb->base.id,
		7366	(int)set->num_connectors, set->x, set->y);
		7367	} else {
		7368	DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
		7369	}
		7370
		7371	dev = set->crtc->dev;
		7372
		7373	ret = -ENOMEM;
		7374	config = kzalloc(sizeof(*config), GFP_KERNEL);
		7375	if (!config)
		7376	goto out_config;
		7377
		7378	ret = intel_set_config_save_state(dev, config);
		7379	if (ret)
		7380	goto out_config;
		7381
		7382	save_set.crtc = set->crtc;
		7383	save_set.mode = &set->crtc->mode;
		7384	save_set.x = set->crtc->x;
		7385	save_set.y = set->crtc->y;
		7386	save_set.fb = set->crtc->fb;
		7387
		7388	/* Compute whether we need a full modeset, only an fb base update or no
		7389	* change at all. In the future we might also check whether only the
		7390	* mode changed, e.g. for LVDS where we only change the panel fitter in
		7391	* such cases. */
		7392	intel_set_config_compute_mode_changes(set, config);
		7393
		7394	ret = intel_modeset_stage_output_state(dev, set, config);
		7395	if (ret)
		7396	goto fail;
		7397
		7398	if (config->mode_changed) {
		7399	if (set->mode) {
		7400	DRM_DEBUG_KMS("attempting to set mode from"
		7401	" userspace\n");
		7402	drm_mode_debug_printmodeline(set->mode);
		7403	}
		7404
		7405	if (!intel_set_mode(set->crtc, set->mode,
		7406	set->x, set->y, set->fb)) {
		7407	DRM_ERROR("failed to set mode on [CRTC:%d]\n",
		7408	set->crtc->base.id);
		7409	ret = -EINVAL;
		7410	goto fail;
		7411	}
		7412	} else if (config->fb_changed) {
		7413	ret = intel_pipe_set_base(set->crtc,
		7414	set->x, set->y, set->fb);
		7415	}
		7416
		7417	intel_set_config_free(config);
		7418
		7419	return 0;
		7420
		7421	fail:
		7422	intel_set_config_restore_state(dev, config);
		7423
		7424	/* Try to restore the config */
		7425	if (config->mode_changed &&
		7426	!intel_set_mode(save_set.crtc, save_set.mode,
		7427	save_set.x, save_set.y, save_set.fb))
		7428	DRM_ERROR("failed to restore config after modeset failure\n");
		7429
		7430	out_config:
		7431	intel_set_config_free(config);
		7432	return ret;
		7433	}
		7434
2330	Serge	7435	static const struct drm_crtc_funcs intel_crtc_funcs = {
		7436	// .cursor_set = intel_crtc_cursor_set,
		7437	// .cursor_move = intel_crtc_cursor_move,
		7438	.gamma_set = intel_crtc_gamma_set,
3031	serge	7439	.set_config = intel_crtc_set_config,
2330	Serge	7440	.destroy = intel_crtc_destroy,
		7441	// .page_flip = intel_crtc_page_flip,
		7442	};
2327	Serge	7443
3031	serge	7444	static void intel_pch_pll_init(struct drm_device *dev)
		7445	{
		7446	drm_i915_private_t *dev_priv = dev->dev_private;
		7447	int i;
		7448
		7449	if (dev_priv->num_pch_pll == 0) {
		7450	DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
		7451	return;
		7452	}
		7453
		7454	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		7455	dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
		7456	dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
		7457	dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
		7458	}
		7459	}
		7460
2330	Serge	7461	static void intel_crtc_init(struct drm_device *dev, int pipe)
		7462	{
		7463	drm_i915_private_t *dev_priv = dev->dev_private;
		7464	struct intel_crtc *intel_crtc;
		7465	int i;
2327	Serge	7466
2330	Serge	7467	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		7468	if (intel_crtc == NULL)
		7469	return;
2327	Serge	7470
2330	Serge	7471	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	7472
2330	Serge	7473	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		7474	for (i = 0; i < 256; i++) {
		7475	intel_crtc->lut_r[i] = i;
		7476	intel_crtc->lut_g[i] = i;
		7477	intel_crtc->lut_b[i] = i;
		7478	}
2327	Serge	7479
2330	Serge	7480	/* Swap pipes & planes for FBC on pre-965 */
		7481	intel_crtc->pipe = pipe;
		7482	intel_crtc->plane = pipe;
		7483	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		7484	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		7485	intel_crtc->plane = !pipe;
		7486	}
2327	Serge	7487
2330	Serge	7488	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		7489	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		7490	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		7491	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	7492
2330	Serge	7493	intel_crtc->bpp = 24; /* default for pre-Ironlake */
2327	Serge	7494
2330	Serge	7495	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2327	Serge	7496
3037	serge	7497	DRM_DEBUG_KMS("CRTC %d mode %x FB %x enable %d\n",
3031	serge	7498	intel_crtc->base.base.id, intel_crtc->base.mode,
		7499	intel_crtc->base.fb, intel_crtc->base.enabled);
2327	Serge	7500
2330	Serge	7501	}
2327	Serge	7502
3031	serge	7503	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		7504	struct drm_file *file)
		7505	{
		7506	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
		7507	struct drm_mode_object *drmmode_obj;
		7508	struct intel_crtc *crtc;
2327	Serge	7509
3031	serge	7510	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
		7511	DRM_MODE_OBJECT_CRTC);
2327	Serge	7512
3031	serge	7513	if (!drmmode_obj) {
		7514	DRM_ERROR("no such CRTC id\n");
		7515	return -EINVAL;
		7516	}
2327	Serge	7517
3031	serge	7518	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
		7519	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	7520
3031	serge	7521	return 0;
		7522	}
2327	Serge	7523
3031	serge	7524	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	7525	{
3031	serge	7526	struct drm_device *dev = encoder->base.dev;
		7527	struct intel_encoder *source_encoder;
2330	Serge	7528	int index_mask = 0;
		7529	int entry = 0;
2327	Serge	7530
3031	serge	7531	list_for_each_entry(source_encoder,
		7532	&dev->mode_config.encoder_list, base.head) {
		7533
		7534	if (encoder == source_encoder)
2330	Serge	7535	index_mask \|= (1 << entry);
3031	serge	7536
		7537	/* Intel hw has only one MUX where enocoders could be cloned. */
		7538	if (encoder->cloneable && source_encoder->cloneable)
		7539	index_mask \|= (1 << entry);
		7540
2330	Serge	7541	entry++;
		7542	}
2327	Serge	7543
2330	Serge	7544	return index_mask;
		7545	}
2327	Serge	7546
2330	Serge	7547	static bool has_edp_a(struct drm_device *dev)
		7548	{
		7549	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	7550
2330	Serge	7551	if (!IS_MOBILE(dev))
		7552	return false;
2327	Serge	7553
2330	Serge	7554	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		7555	return false;
2327	Serge	7556
2330	Serge	7557	if (IS_GEN5(dev) &&
		7558	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		7559	return false;
2327	Serge	7560
2330	Serge	7561	return true;
		7562	}
2327	Serge	7563
2330	Serge	7564	static void intel_setup_outputs(struct drm_device *dev)
		7565	{
		7566	struct drm_i915_private *dev_priv = dev->dev_private;
		7567	struct intel_encoder *encoder;
		7568	bool dpd_is_edp = false;
3031	serge	7569	bool has_lvds;
2327	Serge	7570
2330	Serge	7571	has_lvds = intel_lvds_init(dev);
		7572	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		7573	/* disable the panel fitter on everything but LVDS */
		7574	I915_WRITE(PFIT_CONTROL, 0);
		7575	}
2327	Serge	7576
2330	Serge	7577	if (HAS_PCH_SPLIT(dev)) {
		7578	dpd_is_edp = intel_dpd_is_edp(dev);
2327	Serge	7579
2330	Serge	7580	if (has_edp_a(dev))
3031	serge	7581	intel_dp_init(dev, DP_A, PORT_A);
2327	Serge	7582
2330	Serge	7583	if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
3031	serge	7584	intel_dp_init(dev, PCH_DP_D, PORT_D);
2330	Serge	7585	}
2327	Serge	7586
2330	Serge	7587	intel_crt_init(dev);
2327	Serge	7588
3031	serge	7589	if (IS_HASWELL(dev)) {
2330	Serge	7590	int found;
2327	Serge	7591
3031	serge	7592	/* Haswell uses DDI functions to detect digital outputs */
		7593	found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		7594	/* DDI A only supports eDP */
		7595	if (found)
		7596	intel_ddi_init(dev, PORT_A);
		7597
		7598	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		7599	* register */
		7600	found = I915_READ(SFUSE_STRAP);
		7601
		7602	if (found & SFUSE_STRAP_DDIB_DETECTED)
		7603	intel_ddi_init(dev, PORT_B);
		7604	if (found & SFUSE_STRAP_DDIC_DETECTED)
		7605	intel_ddi_init(dev, PORT_C);
		7606	if (found & SFUSE_STRAP_DDID_DETECTED)
		7607	intel_ddi_init(dev, PORT_D);
		7608	} else if (HAS_PCH_SPLIT(dev)) {
		7609	int found;
		7610
2330	Serge	7611	if (I915_READ(HDMIB) & PORT_DETECTED) {
		7612	/* PCH SDVOB multiplex with HDMIB */
3031	serge	7613	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	7614	if (!found)
3031	serge	7615	intel_hdmi_init(dev, HDMIB, PORT_B);
2330	Serge	7616	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	7617	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	7618	}
2327	Serge	7619
2330	Serge	7620	if (I915_READ(HDMIC) & PORT_DETECTED)
3031	serge	7621	intel_hdmi_init(dev, HDMIC, PORT_C);
2327	Serge	7622
3031	serge	7623	if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
		7624	intel_hdmi_init(dev, HDMID, PORT_D);
2327	Serge	7625
2330	Serge	7626	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	7627	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	7628
2330	Serge	7629	if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
3031	serge	7630	intel_dp_init(dev, PCH_DP_D, PORT_D);
		7631	} else if (IS_VALLEYVIEW(dev)) {
		7632	int found;
2327	Serge	7633
3031	serge	7634	if (I915_READ(SDVOB) & PORT_DETECTED) {
		7635	/* SDVOB multiplex with HDMIB */
		7636	found = intel_sdvo_init(dev, SDVOB, true);
		7637	if (!found)
		7638	intel_hdmi_init(dev, SDVOB, PORT_B);
		7639	if (!found && (I915_READ(DP_B) & DP_DETECTED))
		7640	intel_dp_init(dev, DP_B, PORT_B);
		7641	}
		7642
		7643	if (I915_READ(SDVOC) & PORT_DETECTED)
		7644	intel_hdmi_init(dev, SDVOC, PORT_C);
		7645
		7646	/* Shares lanes with HDMI on SDVOC */
		7647	if (I915_READ(DP_C) & DP_DETECTED)
		7648	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	7649	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		7650	bool found = false;
2327	Serge	7651
2330	Serge	7652	if (I915_READ(SDVOB) & SDVO_DETECTED) {
		7653	DRM_DEBUG_KMS("probing SDVOB\n");
3031	serge	7654	found = intel_sdvo_init(dev, SDVOB, true);
2330	Serge	7655	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		7656	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3031	serge	7657	intel_hdmi_init(dev, SDVOB, PORT_B);
2330	Serge	7658	}
2327	Serge	7659
2330	Serge	7660	if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
		7661	DRM_DEBUG_KMS("probing DP_B\n");
3031	serge	7662	intel_dp_init(dev, DP_B, PORT_B);
2330	Serge	7663	}
		7664	}
2327	Serge	7665
2330	Serge	7666	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	7667
2330	Serge	7668	if (I915_READ(SDVOB) & SDVO_DETECTED) {
		7669	DRM_DEBUG_KMS("probing SDVOC\n");
3031	serge	7670	found = intel_sdvo_init(dev, SDVOC, false);
2330	Serge	7671	}
2327	Serge	7672
2330	Serge	7673	if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
2327	Serge	7674
2330	Serge	7675	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		7676	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3031	serge	7677	intel_hdmi_init(dev, SDVOC, PORT_C);
2330	Serge	7678	}
		7679	if (SUPPORTS_INTEGRATED_DP(dev)) {
		7680	DRM_DEBUG_KMS("probing DP_C\n");
3031	serge	7681	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	7682	}
		7683	}
2327	Serge	7684
2330	Serge	7685	if (SUPPORTS_INTEGRATED_DP(dev) &&
		7686	(I915_READ(DP_D) & DP_DETECTED)) {
		7687	DRM_DEBUG_KMS("probing DP_D\n");
3031	serge	7688	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	7689	}
		7690	} else if (IS_GEN2(dev))
		7691	intel_dvo_init(dev);
2327	Serge	7692
2330	Serge	7693	// if (SUPPORTS_TV(dev))
		7694	// intel_tv_init(dev);
2327	Serge	7695
2330	Serge	7696	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		7697	encoder->base.possible_crtcs = encoder->crtc_mask;
		7698	encoder->base.possible_clones =
3031	serge	7699	intel_encoder_clones(encoder);
2330	Serge	7700	}
2327	Serge	7701
3031	serge	7702	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
2342	Serge	7703	ironlake_init_pch_refclk(dev);
2330	Serge	7704	}
		7705
		7706
		7707
2335	Serge	7708	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		7709	// .destroy = intel_user_framebuffer_destroy,
		7710	// .create_handle = intel_user_framebuffer_create_handle,
		7711	};
2327	Serge	7712
2335	Serge	7713	int intel_framebuffer_init(struct drm_device *dev,
		7714	struct intel_framebuffer *intel_fb,
2342	Serge	7715	struct drm_mode_fb_cmd2 *mode_cmd,
2335	Serge	7716	struct drm_i915_gem_object *obj)
		7717	{
		7718	int ret;
2327	Serge	7719
2335	Serge	7720	if (obj->tiling_mode == I915_TILING_Y)
		7721	return -EINVAL;
2327	Serge	7722
2342	Serge	7723	if (mode_cmd->pitches[0] & 63)
2335	Serge	7724	return -EINVAL;
2327	Serge	7725
2342	Serge	7726	switch (mode_cmd->pixel_format) {
		7727	case DRM_FORMAT_RGB332:
		7728	case DRM_FORMAT_RGB565:
		7729	case DRM_FORMAT_XRGB8888:
3031	serge	7730	case DRM_FORMAT_XBGR8888:
2342	Serge	7731	case DRM_FORMAT_ARGB8888:
		7732	case DRM_FORMAT_XRGB2101010:
		7733	case DRM_FORMAT_ARGB2101010:
		7734	/* RGB formats are common across chipsets */
2335	Serge	7735	break;
2342	Serge	7736	case DRM_FORMAT_YUYV:
		7737	case DRM_FORMAT_UYVY:
		7738	case DRM_FORMAT_YVYU:
		7739	case DRM_FORMAT_VYUY:
		7740	break;
2335	Serge	7741	default:
3031	serge	7742	DRM_DEBUG_KMS("unsupported pixel format %u\n",
		7743	mode_cmd->pixel_format);
2335	Serge	7744	return -EINVAL;
		7745	}
2327	Serge	7746
2335	Serge	7747	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		7748	if (ret) {
		7749	DRM_ERROR("framebuffer init failed %d\n", ret);
		7750	return ret;
		7751	}
2327	Serge	7752
2335	Serge	7753	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		7754	intel_fb->obj = obj;
		7755	return 0;
		7756	}
2327	Serge	7757
		7758
2360	Serge	7759	static const struct drm_mode_config_funcs intel_mode_funcs = {
		7760	.fb_create = NULL /intel_user_framebuffer_create/,
		7761	.output_poll_changed = NULL /intel_fb_output_poll_changed/,
		7762	};
2327	Serge	7763
3031	serge	7764	/* Set up chip specific display functions */
		7765	static void intel_init_display(struct drm_device *dev)
		7766	{
		7767	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	7768
3031	serge	7769	/* We always want a DPMS function */
		7770	if (HAS_PCH_SPLIT(dev)) {
		7771	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		7772	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		7773	dev_priv->display.crtc_disable = ironlake_crtc_disable;
		7774	dev_priv->display.off = ironlake_crtc_off;
		7775	dev_priv->display.update_plane = ironlake_update_plane;
		7776	} else {
		7777	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		7778	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		7779	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		7780	dev_priv->display.off = i9xx_crtc_off;
		7781	dev_priv->display.update_plane = i9xx_update_plane;
		7782	}
2327	Serge	7783
3031	serge	7784	/* Returns the core display clock speed */
		7785	if (IS_VALLEYVIEW(dev))
		7786	dev_priv->display.get_display_clock_speed =
		7787	valleyview_get_display_clock_speed;
		7788	else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		7789	dev_priv->display.get_display_clock_speed =
		7790	i945_get_display_clock_speed;
		7791	else if (IS_I915G(dev))
		7792	dev_priv->display.get_display_clock_speed =
		7793	i915_get_display_clock_speed;
		7794	else if (IS_I945GM(dev) \|\| IS_845G(dev) \|\| IS_PINEVIEW_M(dev))
		7795	dev_priv->display.get_display_clock_speed =
		7796	i9xx_misc_get_display_clock_speed;
		7797	else if (IS_I915GM(dev))
		7798	dev_priv->display.get_display_clock_speed =
		7799	i915gm_get_display_clock_speed;
		7800	else if (IS_I865G(dev))
		7801	dev_priv->display.get_display_clock_speed =
		7802	i865_get_display_clock_speed;
		7803	else if (IS_I85X(dev))
		7804	dev_priv->display.get_display_clock_speed =
		7805	i855_get_display_clock_speed;
		7806	else /* 852, 830 */
		7807	dev_priv->display.get_display_clock_speed =
		7808	i830_get_display_clock_speed;
2327	Serge	7809
3031	serge	7810	if (HAS_PCH_SPLIT(dev)) {
		7811	if (IS_GEN5(dev)) {
		7812	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		7813	dev_priv->display.write_eld = ironlake_write_eld;
		7814	} else if (IS_GEN6(dev)) {
		7815	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		7816	dev_priv->display.write_eld = ironlake_write_eld;
		7817	} else if (IS_IVYBRIDGE(dev)) {
		7818	/* FIXME: detect B0+ stepping and use auto training */
		7819	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		7820	dev_priv->display.write_eld = ironlake_write_eld;
		7821	} else if (IS_HASWELL(dev)) {
		7822	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		7823	dev_priv->display.write_eld = haswell_write_eld;
		7824	} else
		7825	dev_priv->display.update_wm = NULL;
		7826	} else if (IS_G4X(dev)) {
		7827	dev_priv->display.write_eld = g4x_write_eld;
		7828	}
2327	Serge	7829
3031	serge	7830	/* Default just returns -ENODEV to indicate unsupported */
		7831	// dev_priv->display.queue_flip = intel_default_queue_flip;
2327	Serge	7832
		7833
		7834
		7835
3031	serge	7836	}
		7837
		7838	/*
		7839	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		7840	* resume, or other times. This quirk makes sure that's the case for
		7841	* affected systems.
		7842	*/
		7843	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	7844	{
		7845	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	7846
3031	serge	7847	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		7848	DRM_INFO("applying pipe a force quirk\n");
		7849	}
2327	Serge	7850
3031	serge	7851	/*
		7852	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		7853	*/
		7854	static void quirk_ssc_force_disable(struct drm_device *dev)
		7855	{
		7856	struct drm_i915_private *dev_priv = dev->dev_private;
		7857	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		7858	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	7859	}
2327	Serge	7860
3031	serge	7861	/*
		7862	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		7863	* brightness value
		7864	*/
		7865	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	7866	{
		7867	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	7868	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		7869	DRM_INFO("applying inverted panel brightness quirk\n");
		7870	}
2327	Serge	7871
3031	serge	7872	struct intel_quirk {
		7873	int device;
		7874	int subsystem_vendor;
		7875	int subsystem_device;
		7876	void (hook)(struct drm_device dev);
		7877	};
2327	Serge	7878
3031	serge	7879	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		7880	struct intel_dmi_quirk {
		7881	void (hook)(struct drm_device dev);
		7882	const struct dmi_system_id (*dmi_id_list)[];
		7883	};
2327	Serge	7884
3031	serge	7885	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		7886	{
		7887	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		7888	return 1;
2330	Serge	7889	}
2327	Serge	7890
3031	serge	7891	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		7892	{
		7893	.dmi_id_list = &(const struct dmi_system_id[]) {
		7894	{
		7895	.callback = intel_dmi_reverse_brightness,
		7896	.ident = "NCR Corporation",
		7897	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		7898	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		7899	},
		7900	},
		7901	{ } /* terminating entry */
		7902	},
		7903	.hook = quirk_invert_brightness,
		7904	},
		7905	};
2327	Serge	7906
3031	serge	7907	static struct intel_quirk intel_quirks[] = {
		7908	/* HP Mini needs pipe A force quirk (LP: #322104) */
		7909	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327	Serge	7910
3031	serge	7911	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		7912	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	7913
3031	serge	7914	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		7915	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	7916
3031	serge	7917	/* 830/845 need to leave pipe A & dpll A up */
		7918	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		7919	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
2327	Serge	7920
3031	serge	7921	/* Lenovo U160 cannot use SSC on LVDS */
		7922	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	7923
3031	serge	7924	/* Sony Vaio Y cannot use SSC on LVDS */
		7925	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	7926
3031	serge	7927	/* Acer Aspire 5734Z must invert backlight brightness */
		7928	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
		7929	};
2327	Serge	7930
3031	serge	7931	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	7932	{
3031	serge	7933	struct pci_dev *d = dev->pdev;
		7934	int i;
2327	Serge	7935
3031	serge	7936	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		7937	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	7938
3031	serge	7939	if (d->device == q->device &&
		7940	(d->subsystem_vendor == q->subsystem_vendor \|\|
		7941	q->subsystem_vendor == PCI_ANY_ID) &&
		7942	(d->subsystem_device == q->subsystem_device \|\|
		7943	q->subsystem_device == PCI_ANY_ID))
		7944	q->hook(dev);
		7945	}
		7946	// for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
		7947	// if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
		7948	// intel_dmi_quirks[i].hook(dev);
		7949	// }
2330	Serge	7950	}
2327	Serge	7951
3031	serge	7952	/* Disable the VGA plane that we never use */
		7953	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	7954	{
		7955	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	7956	u8 sr1;
		7957	u32 vga_reg;
2327	Serge	7958
3031	serge	7959	if (HAS_PCH_SPLIT(dev))
		7960	vga_reg = CPU_VGACNTRL;
		7961	else
		7962	vga_reg = VGACNTRL;
2327	Serge	7963
3031	serge	7964	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		7965	out8(SR01, VGA_SR_INDEX);
		7966	sr1 = in8(VGA_SR_DATA);
		7967	out8(sr1 \| 1<<5, VGA_SR_DATA);
		7968	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		7969	udelay(300);
2327	Serge	7970
3031	serge	7971	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		7972	POSTING_READ(vga_reg);
2330	Serge	7973	}
		7974
3031	serge	7975	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	7976	{
3031	serge	7977	/* We attempt to init the necessary power wells early in the initialization
		7978	* time, so the subsystems that expect power to be enabled can work.
2342	Serge	7979	*/
3031	serge	7980	intel_init_power_wells(dev);
2342	Serge	7981
3031	serge	7982	intel_prepare_ddi(dev);
2342	Serge	7983
3031	serge	7984	intel_init_clock_gating(dev);
		7985
		7986	// mutex_lock(&dev->struct_mutex);
		7987	// intel_enable_gt_powersave(dev);
		7988	// mutex_unlock(&dev->struct_mutex);
2342	Serge	7989	}
		7990
3031	serge	7991	void intel_modeset_init(struct drm_device *dev)
2330	Serge	7992	{
3031	serge	7993	struct drm_i915_private *dev_priv = dev->dev_private;
		7994	int i, ret;
2330	Serge	7995
3031	serge	7996	drm_mode_config_init(dev);
2330	Serge	7997
3031	serge	7998	dev->mode_config.min_width = 0;
		7999	dev->mode_config.min_height = 0;
2330	Serge	8000
3031	serge	8001	dev->mode_config.preferred_depth = 24;
		8002	dev->mode_config.prefer_shadow = 1;
2330	Serge	8003
3031	serge	8004	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	8005
3031	serge	8006	intel_init_quirks(dev);
2330	Serge	8007
3031	serge	8008	intel_init_pm(dev);
2330	Serge	8009
3031	serge	8010	intel_init_display(dev);
2330	Serge	8011
3031	serge	8012	if (IS_GEN2(dev)) {
		8013	dev->mode_config.max_width = 2048;
		8014	dev->mode_config.max_height = 2048;
		8015	} else if (IS_GEN3(dev)) {
		8016	dev->mode_config.max_width = 4096;
		8017	dev->mode_config.max_height = 4096;
		8018	} else {
		8019	dev->mode_config.max_width = 8192;
		8020	dev->mode_config.max_height = 8192;
		8021	}
		8022	dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
2330	Serge	8023
3031	serge	8024	DRM_DEBUG_KMS("%d display pipe%s available.\n",
		8025	dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
2330	Serge	8026
3031	serge	8027	for (i = 0; i < dev_priv->num_pipe; i++) {
		8028	intel_crtc_init(dev, i);
		8029	ret = intel_plane_init(dev, i);
		8030	if (ret)
		8031	DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
2330	Serge	8032	}
		8033
3031	serge	8034	intel_pch_pll_init(dev);
2330	Serge	8035
3031	serge	8036	/* Just disable it once at startup */
		8037	i915_disable_vga(dev);
		8038	intel_setup_outputs(dev);
		8039	}
2330	Serge	8040
3031	serge	8041	static void
		8042	intel_connector_break_all_links(struct intel_connector *connector)
		8043	{
		8044	connector->base.dpms = DRM_MODE_DPMS_OFF;
		8045	connector->base.encoder = NULL;
		8046	connector->encoder->connectors_active = false;
		8047	connector->encoder->base.crtc = NULL;
2330	Serge	8048	}
		8049
3031	serge	8050	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	8051	{
3031	serge	8052	struct intel_connector *connector;
		8053	struct drm_connector *crt = NULL;
		8054	struct intel_load_detect_pipe load_detect_temp;
2330	Serge	8055
3031	serge	8056	/* We can't just switch on the pipe A, we need to set things up with a
		8057	* proper mode and output configuration. As a gross hack, enable pipe A
		8058	* by enabling the load detect pipe once. */
		8059	list_for_each_entry(connector,
		8060	&dev->mode_config.connector_list,
		8061	base.head) {
		8062	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		8063	crt = &connector->base;
		8064	break;
2330	Serge	8065	}
		8066	}
		8067
3031	serge	8068	if (!crt)
		8069	return;
2330	Serge	8070
3031	serge	8071	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		8072	intel_release_load_detect_pipe(crt, &load_detect_temp);
2327	Serge	8073
		8074
		8075	}
		8076
3031	serge	8077	static bool
		8078	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	8079	{
3031	serge	8080	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		8081	u32 reg, val;
2327	Serge	8082
3031	serge	8083	if (dev_priv->num_pipe == 1)
		8084	return true;
2327	Serge	8085
3031	serge	8086	reg = DSPCNTR(!crtc->plane);
		8087	val = I915_READ(reg);
2327	Serge	8088
3031	serge	8089	if ((val & DISPLAY_PLANE_ENABLE) &&
		8090	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		8091	return false;
2327	Serge	8092
3031	serge	8093	return true;
2327	Serge	8094	}
		8095
3031	serge	8096	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	8097	{
3031	serge	8098	struct drm_device *dev = crtc->base.dev;
2327	Serge	8099	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8100	u32 reg;
2327	Serge	8101
3031	serge	8102	/* Clear any frame start delays used for debugging left by the BIOS */
		8103	reg = PIPECONF(crtc->pipe);
		8104	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	8105
3031	serge	8106	/* We need to sanitize the plane -> pipe mapping first because this will
		8107	* disable the crtc (and hence change the state) if it is wrong. Note
		8108	* that gen4+ has a fixed plane -> pipe mapping. */
		8109	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		8110	struct intel_connector *connector;
		8111	bool plane;
2327	Serge	8112
3031	serge	8113	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		8114	crtc->base.base.id);
2327	Serge	8115
3031	serge	8116	/* Pipe has the wrong plane attached and the plane is active.
		8117	* Temporarily change the plane mapping and disable everything
		8118	* ... */
		8119	plane = crtc->plane;
		8120	crtc->plane = !plane;
		8121	dev_priv->display.crtc_disable(&crtc->base);
		8122	crtc->plane = plane;
2342	Serge	8123
3031	serge	8124	/* ... and break all links. */
		8125	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8126	base.head) {
		8127	if (connector->encoder->base.crtc != &crtc->base)
		8128	continue;
2327	Serge	8129
3031	serge	8130	intel_connector_break_all_links(connector);
		8131	}
2327	Serge	8132
3031	serge	8133	WARN_ON(crtc->active);
		8134	crtc->base.enabled = false;
		8135	}
2327	Serge	8136
3031	serge	8137	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		8138	crtc->pipe == PIPE_A && !crtc->active) {
		8139	/* BIOS forgot to enable pipe A, this mostly happens after
		8140	* resume. Force-enable the pipe to fix this, the update_dpms
		8141	* call below we restore the pipe to the right state, but leave
		8142	* the required bits on. */
		8143	intel_enable_pipe_a(dev);
		8144	}
2327	Serge	8145
3031	serge	8146	/* Adjust the state of the output pipe according to whether we
		8147	* have active connectors/encoders. */
		8148	intel_crtc_update_dpms(&crtc->base);
2327	Serge	8149
3031	serge	8150	if (crtc->active != crtc->base.enabled) {
		8151	struct intel_encoder *encoder;
2327	Serge	8152
3031	serge	8153	/* This can happen either due to bugs in the get_hw_state
		8154	* functions or because the pipe is force-enabled due to the
		8155	* pipe A quirk. */
		8156	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		8157	crtc->base.base.id,
		8158	crtc->base.enabled ? "enabled" : "disabled",
		8159	crtc->active ? "enabled" : "disabled");
2327	Serge	8160
3031	serge	8161	crtc->base.enabled = crtc->active;
2327	Serge	8162
3031	serge	8163	/* Because we only establish the connector -> encoder ->
		8164	* crtc links if something is active, this means the
		8165	* crtc is now deactivated. Break the links. connector
		8166	* -> encoder links are only establish when things are
		8167	* actually up, hence no need to break them. */
		8168	WARN_ON(crtc->active);
2327	Serge	8169
3031	serge	8170	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		8171	WARN_ON(encoder->connectors_active);
		8172	encoder->base.crtc = NULL;
		8173	}
		8174	}
2327	Serge	8175	}
		8176
3031	serge	8177	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	8178	{
3031	serge	8179	struct intel_connector *connector;
		8180	struct drm_device *dev = encoder->base.dev;
2327	Serge	8181
3031	serge	8182	/* We need to check both for a crtc link (meaning that the
		8183	* encoder is active and trying to read from a pipe) and the
		8184	* pipe itself being active. */
		8185	bool has_active_crtc = encoder->base.crtc &&
		8186	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	8187
3031	serge	8188	if (encoder->connectors_active && !has_active_crtc) {
		8189	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		8190	encoder->base.base.id,
		8191	drm_get_encoder_name(&encoder->base));
2327	Serge	8192
3031	serge	8193	/* Connector is active, but has no active pipe. This is
		8194	* fallout from our resume register restoring. Disable
		8195	* the encoder manually again. */
		8196	if (encoder->base.crtc) {
		8197	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		8198	encoder->base.base.id,
		8199	drm_get_encoder_name(&encoder->base));
		8200	encoder->disable(encoder);
		8201	}
2327	Serge	8202
3031	serge	8203	/* Inconsistent output/port/pipe state happens presumably due to
		8204	* a bug in one of the get_hw_state functions. Or someplace else
		8205	* in our code, like the register restore mess on resume. Clamp
		8206	* things to off as a safer default. */
		8207	list_for_each_entry(connector,
		8208	&dev->mode_config.connector_list,
		8209	base.head) {
		8210	if (connector->encoder != encoder)
		8211	continue;
2327	Serge	8212
3031	serge	8213	intel_connector_break_all_links(connector);
		8214	}
		8215	}
		8216	/* Enabled encoders without active connectors will be fixed in
		8217	* the crtc fixup. */
2327	Serge	8218	}
		8219
3031	serge	8220	/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
		8221	* and i915 state tracking structures. */
		8222	void intel_modeset_setup_hw_state(struct drm_device *dev)
2332	Serge	8223	{
		8224	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8225	enum pipe pipe;
		8226	u32 tmp;
		8227	struct intel_crtc *crtc;
		8228	struct intel_encoder *encoder;
		8229	struct intel_connector *connector;
2327	Serge	8230
3031	serge	8231	for_each_pipe(pipe) {
		8232	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2327	Serge	8233
3031	serge	8234	tmp = I915_READ(PIPECONF(pipe));
		8235	if (tmp & PIPECONF_ENABLE)
		8236	crtc->active = true;
		8237	else
		8238	crtc->active = false;
2327	Serge	8239
3031	serge	8240	crtc->base.enabled = crtc->active;
2330	Serge	8241
3031	serge	8242	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		8243	crtc->base.base.id,
		8244	crtc->active ? "enabled" : "disabled");
2339	Serge	8245	}
2332	Serge	8246
3031	serge	8247	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8248	base.head) {
		8249	pipe = 0;
2332	Serge	8250
3031	serge	8251	if (encoder->get_hw_state(encoder, &pipe)) {
		8252	encoder->base.crtc =
		8253	dev_priv->pipe_to_crtc_mapping[pipe];
		8254	} else {
		8255	encoder->base.crtc = NULL;
		8256	}
2332	Serge	8257
3031	serge	8258	encoder->connectors_active = false;
		8259	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
		8260	encoder->base.base.id,
		8261	drm_get_encoder_name(&encoder->base),
		8262	encoder->base.crtc ? "enabled" : "disabled",
		8263	pipe);
		8264	}
2332	Serge	8265
3031	serge	8266	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8267	base.head) {
		8268	if (connector->get_hw_state(connector)) {
		8269	connector->base.dpms = DRM_MODE_DPMS_ON;
		8270	connector->encoder->connectors_active = true;
		8271	connector->base.encoder = &connector->encoder->base;
		8272	} else {
		8273	connector->base.dpms = DRM_MODE_DPMS_OFF;
		8274	connector->base.encoder = NULL;
		8275	}
		8276	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		8277	connector->base.base.id,
		8278	drm_get_connector_name(&connector->base),
		8279	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	8280	}
		8281
3031	serge	8282	/* HW state is read out, now we need to sanitize this mess. */
		8283	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8284	base.head) {
		8285	intel_sanitize_encoder(encoder);
2332	Serge	8286	}
		8287
3031	serge	8288	for_each_pipe(pipe) {
		8289	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		8290	intel_sanitize_crtc(crtc);
2332	Serge	8291	}
		8292
3031	serge	8293	intel_modeset_update_staged_output_state(dev);
2332	Serge	8294
3031	serge	8295	intel_modeset_check_state(dev);
2332	Serge	8296	}
		8297
3031	serge	8298	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	8299	{
3031	serge	8300	intel_modeset_init_hw(dev);
2330	Serge	8301
3031	serge	8302	// intel_setup_overlay(dev);
2330	Serge	8303
3031	serge	8304	intel_modeset_setup_hw_state(dev);
2330	Serge	8305	}
		8306
3031	serge	8307	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	8308	{
3031	serge	8309	#if 0
		8310	struct drm_i915_private *dev_priv = dev->dev_private;
		8311	struct drm_crtc *crtc;
		8312	struct intel_crtc *intel_crtc;
2327	Serge	8313
3031	serge	8314	// drm_kms_helper_poll_fini(dev);
		8315	mutex_lock(&dev->struct_mutex);
2327	Serge	8316
3031	serge	8317	// intel_unregister_dsm_handler();
2327	Serge	8318
		8319
3031	serge	8320	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		8321	/* Skip inactive CRTCs */
		8322	if (!crtc->fb)
		8323	continue;
2342	Serge	8324
3031	serge	8325	intel_crtc = to_intel_crtc(crtc);
		8326	intel_increase_pllclock(crtc);
		8327	}
2342	Serge	8328
3031	serge	8329	intel_disable_fbc(dev);
2342	Serge	8330
3031	serge	8331	intel_disable_gt_powersave(dev);
2342	Serge	8332
3031	serge	8333	ironlake_teardown_rc6(dev);
2327	Serge	8334
3031	serge	8335	if (IS_VALLEYVIEW(dev))
		8336	vlv_init_dpio(dev);
2327	Serge	8337
3031	serge	8338	mutex_unlock(&dev->struct_mutex);
2327	Serge	8339
3031	serge	8340	/* Disable the irq before mode object teardown, for the irq might
		8341	* enqueue unpin/hotplug work. */
		8342	// drm_irq_uninstall(dev);
		8343	// cancel_work_sync(&dev_priv->hotplug_work);
		8344	// cancel_work_sync(&dev_priv->rps.work);
2327	Serge	8345
3031	serge	8346	/* flush any delayed tasks or pending work */
		8347	// flush_scheduled_work();
2327	Serge	8348
3031	serge	8349	drm_mode_config_cleanup(dev);
2327	Serge	8350	#endif
		8351	}
		8352
		8353	/*
3031	serge	8354	* Return which encoder is currently attached for connector.
2327	Serge	8355	*/
3031	serge	8356	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	8357	{
3031	serge	8358	return &intel_attached_encoder(connector)->base;
		8359	}
2327	Serge	8360
3031	serge	8361	void intel_connector_attach_encoder(struct intel_connector *connector,
		8362	struct intel_encoder *encoder)
		8363	{
		8364	connector->encoder = encoder;
		8365	drm_mode_connector_attach_encoder(&connector->base,
		8366	&encoder->base);
2327	Serge	8367	}
		8368
		8369	/*
3031	serge	8370	* set vga decode state - true == enable VGA decode
2327	Serge	8371	*/
3031	serge	8372	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	8373	{
2330	Serge	8374	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8375	u16 gmch_ctrl;
2327	Serge	8376
3031	serge	8377	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
		8378	if (state)
		8379	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	8380	else
3031	serge	8381	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
		8382	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
		8383	return 0;
2330	Serge	8384	}
		8385
3031	serge	8386	#ifdef CONFIG_DEBUG_FS
		8387	#include
2327	Serge	8388
3031	serge	8389	struct intel_display_error_state {
		8390	struct intel_cursor_error_state {
		8391	u32 control;
		8392	u32 position;
		8393	u32 base;
		8394	u32 size;
		8395	} cursor[I915_MAX_PIPES];
2327	Serge	8396
3031	serge	8397	struct intel_pipe_error_state {
		8398	u32 conf;
		8399	u32 source;
2327	Serge	8400
3031	serge	8401	u32 htotal;
		8402	u32 hblank;
		8403	u32 hsync;
		8404	u32 vtotal;
		8405	u32 vblank;
		8406	u32 vsync;
		8407	} pipe[I915_MAX_PIPES];
2327	Serge	8408
3031	serge	8409	struct intel_plane_error_state {
		8410	u32 control;
		8411	u32 stride;
		8412	u32 size;
		8413	u32 pos;
		8414	u32 addr;
		8415	u32 surface;
		8416	u32 tile_offset;
		8417	} plane[I915_MAX_PIPES];
		8418	};
2327	Serge	8419
3031	serge	8420	struct intel_display_error_state *
		8421	intel_display_capture_error_state(struct drm_device *dev)
		8422	{
		8423	drm_i915_private_t *dev_priv = dev->dev_private;
		8424	struct intel_display_error_state *error;
		8425	int i;
2327	Serge	8426
3031	serge	8427	error = kmalloc(sizeof(*error), GFP_ATOMIC);
		8428	if (error == NULL)
		8429	return NULL;
2327	Serge	8430
3031	serge	8431	for_each_pipe(i) {
		8432	error->cursor[i].control = I915_READ(CURCNTR(i));
		8433	error->cursor[i].position = I915_READ(CURPOS(i));
		8434	error->cursor[i].base = I915_READ(CURBASE(i));
2327	Serge	8435
3031	serge	8436	error->plane[i].control = I915_READ(DSPCNTR(i));
		8437	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
		8438	error->plane[i].size = I915_READ(DSPSIZE(i));
		8439	error->plane[i].pos = I915_READ(DSPPOS(i));
		8440	error->plane[i].addr = I915_READ(DSPADDR(i));
		8441	if (INTEL_INFO(dev)->gen >= 4) {
		8442	error->plane[i].surface = I915_READ(DSPSURF(i));
		8443	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		8444	}
2327	Serge	8445
3031	serge	8446	error->pipe[i].conf = I915_READ(PIPECONF(i));
		8447	error->pipe[i].source = I915_READ(PIPESRC(i));
		8448	error->pipe[i].htotal = I915_READ(HTOTAL(i));
		8449	error->pipe[i].hblank = I915_READ(HBLANK(i));
		8450	error->pipe[i].hsync = I915_READ(HSYNC(i));
		8451	error->pipe[i].vtotal = I915_READ(VTOTAL(i));
		8452	error->pipe[i].vblank = I915_READ(VBLANK(i));
		8453	error->pipe[i].vsync = I915_READ(VSYNC(i));
		8454	}
2327	Serge	8455
3031	serge	8456	return error;
2330	Serge	8457	}
2327	Serge	8458
3031	serge	8459	void
		8460	intel_display_print_error_state(struct seq_file *m,
		8461	struct drm_device *dev,
		8462	struct intel_display_error_state *error)
2332	Serge	8463	{
3031	serge	8464	drm_i915_private_t *dev_priv = dev->dev_private;
		8465	int i;
2330	Serge	8466
3031	serge	8467	seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
		8468	for_each_pipe(i) {
		8469	seq_printf(m, "Pipe [%d]:\n", i);
		8470	seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
		8471	seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
		8472	seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
		8473	seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
		8474	seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
		8475	seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
		8476	seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
		8477	seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
2332	Serge	8478
3031	serge	8479	seq_printf(m, "Plane [%d]:\n", i);
		8480	seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
		8481	seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
		8482	seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
		8483	seq_printf(m, " POS: %08x\n", error->plane[i].pos);
		8484	seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
		8485	if (INTEL_INFO(dev)->gen >= 4) {
		8486	seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
		8487	seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
		8488	}
2332	Serge	8489
3031	serge	8490	seq_printf(m, "Cursor [%d]:\n", i);
		8491	seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		8492	seq_printf(m, " POS: %08x\n", error->cursor[i].position);
		8493	seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
		8494	}
2327	Serge	8495	}
3031	serge	8496	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c – Rev 3120