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2327 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | */ |
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26 | |||
27 | //#include |
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28 | #include |
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29 | //#include |
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30 | #include |
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31 | #include |
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2330 | Serge | 32 | #include |
2327 | Serge | 33 | //#include |
2342 | Serge | 34 | #include |
3031 | serge | 35 | #include |
2327 | Serge | 36 | #include "intel_drv.h" |
3031 | serge | 37 | #include |
2327 | Serge | 38 | #include "i915_drv.h" |
2351 | Serge | 39 | #include "i915_trace.h" |
3031 | serge | 40 | #include |
41 | #include |
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42 | //#include |
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2327 | Serge | 43 | |
44 | phys_addr_t get_bus_addr(void); |
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45 | |||
46 | static inline __attribute__((const)) |
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47 | bool is_power_of_2(unsigned long n) |
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48 | { |
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49 | return (n != 0 && ((n & (n - 1)) == 0)); |
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50 | } |
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51 | |||
2330 | Serge | 52 | #define MAX_ERRNO 4095 |
53 | |||
54 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
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55 | |||
56 | static inline long IS_ERR(const void *ptr) |
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57 | { |
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58 | return IS_ERR_VALUE((unsigned long)ptr); |
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59 | } |
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60 | |||
61 | static inline void *ERR_PTR(long error) |
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62 | { |
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63 | return (void *) error; |
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64 | } |
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65 | |||
66 | |||
2327 | Serge | 67 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
68 | |||
2342 | Serge | 69 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
2327 | Serge | 70 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
3031 | serge | 71 | //static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
2327 | Serge | 72 | |
73 | typedef struct { |
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74 | /* given values */ |
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75 | int n; |
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76 | int m1, m2; |
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77 | int p1, p2; |
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78 | /* derived values */ |
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79 | int dot; |
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80 | int vco; |
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81 | int m; |
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82 | int p; |
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83 | } intel_clock_t; |
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84 | |||
85 | typedef struct { |
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86 | int min, max; |
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87 | } intel_range_t; |
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88 | |||
89 | typedef struct { |
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90 | int dot_limit; |
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91 | int p2_slow, p2_fast; |
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92 | } intel_p2_t; |
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93 | |||
94 | #define INTEL_P2_NUM 2 |
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95 | typedef struct intel_limit intel_limit_t; |
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96 | struct intel_limit { |
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97 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
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98 | intel_p2_t p2; |
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99 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
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3031 | serge | 100 | int, int, intel_clock_t *, intel_clock_t *); |
2327 | Serge | 101 | }; |
102 | |||
103 | /* FDI */ |
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104 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
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105 | |||
106 | static bool |
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107 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
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3031 | serge | 108 | int target, int refclk, intel_clock_t *match_clock, |
109 | intel_clock_t *best_clock); |
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2327 | Serge | 110 | static bool |
111 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
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3031 | serge | 112 | int target, int refclk, intel_clock_t *match_clock, |
113 | intel_clock_t *best_clock); |
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2327 | Serge | 114 | |
115 | static bool |
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116 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, |
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3031 | serge | 117 | int target, int refclk, intel_clock_t *match_clock, |
118 | intel_clock_t *best_clock); |
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2327 | Serge | 119 | static bool |
120 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
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3031 | serge | 121 | int target, int refclk, intel_clock_t *match_clock, |
122 | intel_clock_t *best_clock); |
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2327 | Serge | 123 | |
3031 | serge | 124 | static bool |
125 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, |
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126 | int target, int refclk, intel_clock_t *match_clock, |
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127 | intel_clock_t *best_clock); |
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128 | |||
2327 | Serge | 129 | static inline u32 /* units of 100MHz */ |
130 | intel_fdi_link_freq(struct drm_device *dev) |
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131 | { |
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132 | if (IS_GEN5(dev)) { |
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133 | struct drm_i915_private *dev_priv = dev->dev_private; |
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134 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
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135 | } else |
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136 | return 27; |
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137 | } |
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138 | |||
139 | static const intel_limit_t intel_limits_i8xx_dvo = { |
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140 | .dot = { .min = 25000, .max = 350000 }, |
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141 | .vco = { .min = 930000, .max = 1400000 }, |
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142 | .n = { .min = 3, .max = 16 }, |
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143 | .m = { .min = 96, .max = 140 }, |
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144 | .m1 = { .min = 18, .max = 26 }, |
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145 | .m2 = { .min = 6, .max = 16 }, |
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146 | .p = { .min = 4, .max = 128 }, |
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147 | .p1 = { .min = 2, .max = 33 }, |
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148 | .p2 = { .dot_limit = 165000, |
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149 | .p2_slow = 4, .p2_fast = 2 }, |
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150 | .find_pll = intel_find_best_PLL, |
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151 | }; |
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152 | |||
153 | static const intel_limit_t intel_limits_i8xx_lvds = { |
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154 | .dot = { .min = 25000, .max = 350000 }, |
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155 | .vco = { .min = 930000, .max = 1400000 }, |
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156 | .n = { .min = 3, .max = 16 }, |
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157 | .m = { .min = 96, .max = 140 }, |
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158 | .m1 = { .min = 18, .max = 26 }, |
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159 | .m2 = { .min = 6, .max = 16 }, |
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160 | .p = { .min = 4, .max = 128 }, |
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161 | .p1 = { .min = 1, .max = 6 }, |
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162 | .p2 = { .dot_limit = 165000, |
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163 | .p2_slow = 14, .p2_fast = 7 }, |
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164 | .find_pll = intel_find_best_PLL, |
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165 | }; |
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166 | |||
167 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
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168 | .dot = { .min = 20000, .max = 400000 }, |
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169 | .vco = { .min = 1400000, .max = 2800000 }, |
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170 | .n = { .min = 1, .max = 6 }, |
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171 | .m = { .min = 70, .max = 120 }, |
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172 | .m1 = { .min = 10, .max = 22 }, |
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173 | .m2 = { .min = 5, .max = 9 }, |
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174 | .p = { .min = 5, .max = 80 }, |
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175 | .p1 = { .min = 1, .max = 8 }, |
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176 | .p2 = { .dot_limit = 200000, |
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177 | .p2_slow = 10, .p2_fast = 5 }, |
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178 | .find_pll = intel_find_best_PLL, |
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179 | }; |
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180 | |||
181 | static const intel_limit_t intel_limits_i9xx_lvds = { |
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182 | .dot = { .min = 20000, .max = 400000 }, |
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183 | .vco = { .min = 1400000, .max = 2800000 }, |
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184 | .n = { .min = 1, .max = 6 }, |
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185 | .m = { .min = 70, .max = 120 }, |
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186 | .m1 = { .min = 10, .max = 22 }, |
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187 | .m2 = { .min = 5, .max = 9 }, |
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188 | .p = { .min = 7, .max = 98 }, |
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189 | .p1 = { .min = 1, .max = 8 }, |
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190 | .p2 = { .dot_limit = 112000, |
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191 | .p2_slow = 14, .p2_fast = 7 }, |
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192 | .find_pll = intel_find_best_PLL, |
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193 | }; |
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194 | |||
195 | |||
196 | static const intel_limit_t intel_limits_g4x_sdvo = { |
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197 | .dot = { .min = 25000, .max = 270000 }, |
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198 | .vco = { .min = 1750000, .max = 3500000}, |
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199 | .n = { .min = 1, .max = 4 }, |
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200 | .m = { .min = 104, .max = 138 }, |
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201 | .m1 = { .min = 17, .max = 23 }, |
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202 | .m2 = { .min = 5, .max = 11 }, |
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203 | .p = { .min = 10, .max = 30 }, |
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204 | .p1 = { .min = 1, .max = 3}, |
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205 | .p2 = { .dot_limit = 270000, |
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206 | .p2_slow = 10, |
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207 | .p2_fast = 10 |
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208 | }, |
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209 | .find_pll = intel_g4x_find_best_PLL, |
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210 | }; |
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211 | |||
212 | static const intel_limit_t intel_limits_g4x_hdmi = { |
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213 | .dot = { .min = 22000, .max = 400000 }, |
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214 | .vco = { .min = 1750000, .max = 3500000}, |
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215 | .n = { .min = 1, .max = 4 }, |
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216 | .m = { .min = 104, .max = 138 }, |
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217 | .m1 = { .min = 16, .max = 23 }, |
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218 | .m2 = { .min = 5, .max = 11 }, |
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219 | .p = { .min = 5, .max = 80 }, |
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220 | .p1 = { .min = 1, .max = 8}, |
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221 | .p2 = { .dot_limit = 165000, |
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222 | .p2_slow = 10, .p2_fast = 5 }, |
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223 | .find_pll = intel_g4x_find_best_PLL, |
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224 | }; |
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225 | |||
226 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
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227 | .dot = { .min = 20000, .max = 115000 }, |
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228 | .vco = { .min = 1750000, .max = 3500000 }, |
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229 | .n = { .min = 1, .max = 3 }, |
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230 | .m = { .min = 104, .max = 138 }, |
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231 | .m1 = { .min = 17, .max = 23 }, |
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232 | .m2 = { .min = 5, .max = 11 }, |
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233 | .p = { .min = 28, .max = 112 }, |
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234 | .p1 = { .min = 2, .max = 8 }, |
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235 | .p2 = { .dot_limit = 0, |
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236 | .p2_slow = 14, .p2_fast = 14 |
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237 | }, |
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238 | .find_pll = intel_g4x_find_best_PLL, |
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239 | }; |
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240 | |||
241 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
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242 | .dot = { .min = 80000, .max = 224000 }, |
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243 | .vco = { .min = 1750000, .max = 3500000 }, |
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244 | .n = { .min = 1, .max = 3 }, |
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245 | .m = { .min = 104, .max = 138 }, |
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246 | .m1 = { .min = 17, .max = 23 }, |
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247 | .m2 = { .min = 5, .max = 11 }, |
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248 | .p = { .min = 14, .max = 42 }, |
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249 | .p1 = { .min = 2, .max = 6 }, |
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250 | .p2 = { .dot_limit = 0, |
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251 | .p2_slow = 7, .p2_fast = 7 |
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252 | }, |
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253 | .find_pll = intel_g4x_find_best_PLL, |
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254 | }; |
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255 | |||
256 | static const intel_limit_t intel_limits_g4x_display_port = { |
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257 | .dot = { .min = 161670, .max = 227000 }, |
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258 | .vco = { .min = 1750000, .max = 3500000}, |
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259 | .n = { .min = 1, .max = 2 }, |
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260 | .m = { .min = 97, .max = 108 }, |
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261 | .m1 = { .min = 0x10, .max = 0x12 }, |
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262 | .m2 = { .min = 0x05, .max = 0x06 }, |
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263 | .p = { .min = 10, .max = 20 }, |
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264 | .p1 = { .min = 1, .max = 2}, |
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265 | .p2 = { .dot_limit = 0, |
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266 | .p2_slow = 10, .p2_fast = 10 }, |
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267 | .find_pll = intel_find_pll_g4x_dp, |
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268 | }; |
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269 | |||
270 | static const intel_limit_t intel_limits_pineview_sdvo = { |
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271 | .dot = { .min = 20000, .max = 400000}, |
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272 | .vco = { .min = 1700000, .max = 3500000 }, |
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273 | /* Pineview's Ncounter is a ring counter */ |
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274 | .n = { .min = 3, .max = 6 }, |
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275 | .m = { .min = 2, .max = 256 }, |
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276 | /* Pineview only has one combined m divider, which we treat as m2. */ |
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277 | .m1 = { .min = 0, .max = 0 }, |
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278 | .m2 = { .min = 0, .max = 254 }, |
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279 | .p = { .min = 5, .max = 80 }, |
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280 | .p1 = { .min = 1, .max = 8 }, |
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281 | .p2 = { .dot_limit = 200000, |
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282 | .p2_slow = 10, .p2_fast = 5 }, |
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283 | .find_pll = intel_find_best_PLL, |
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284 | }; |
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285 | |||
286 | static const intel_limit_t intel_limits_pineview_lvds = { |
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287 | .dot = { .min = 20000, .max = 400000 }, |
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288 | .vco = { .min = 1700000, .max = 3500000 }, |
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289 | .n = { .min = 3, .max = 6 }, |
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290 | .m = { .min = 2, .max = 256 }, |
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291 | .m1 = { .min = 0, .max = 0 }, |
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292 | .m2 = { .min = 0, .max = 254 }, |
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293 | .p = { .min = 7, .max = 112 }, |
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294 | .p1 = { .min = 1, .max = 8 }, |
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295 | .p2 = { .dot_limit = 112000, |
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296 | .p2_slow = 14, .p2_fast = 14 }, |
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297 | .find_pll = intel_find_best_PLL, |
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298 | }; |
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299 | |||
300 | /* Ironlake / Sandybridge |
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301 | * |
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302 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
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303 | * the range value for them is (actual_value - 2). |
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304 | */ |
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305 | static const intel_limit_t intel_limits_ironlake_dac = { |
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306 | .dot = { .min = 25000, .max = 350000 }, |
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307 | .vco = { .min = 1760000, .max = 3510000 }, |
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308 | .n = { .min = 1, .max = 5 }, |
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309 | .m = { .min = 79, .max = 127 }, |
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310 | .m1 = { .min = 12, .max = 22 }, |
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311 | .m2 = { .min = 5, .max = 9 }, |
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312 | .p = { .min = 5, .max = 80 }, |
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313 | .p1 = { .min = 1, .max = 8 }, |
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314 | .p2 = { .dot_limit = 225000, |
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315 | .p2_slow = 10, .p2_fast = 5 }, |
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316 | .find_pll = intel_g4x_find_best_PLL, |
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317 | }; |
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318 | |||
319 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
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320 | .dot = { .min = 25000, .max = 350000 }, |
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321 | .vco = { .min = 1760000, .max = 3510000 }, |
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322 | .n = { .min = 1, .max = 3 }, |
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323 | .m = { .min = 79, .max = 118 }, |
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324 | .m1 = { .min = 12, .max = 22 }, |
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325 | .m2 = { .min = 5, .max = 9 }, |
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326 | .p = { .min = 28, .max = 112 }, |
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327 | .p1 = { .min = 2, .max = 8 }, |
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328 | .p2 = { .dot_limit = 225000, |
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329 | .p2_slow = 14, .p2_fast = 14 }, |
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330 | .find_pll = intel_g4x_find_best_PLL, |
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331 | }; |
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332 | |||
333 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
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334 | .dot = { .min = 25000, .max = 350000 }, |
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335 | .vco = { .min = 1760000, .max = 3510000 }, |
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336 | .n = { .min = 1, .max = 3 }, |
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337 | .m = { .min = 79, .max = 127 }, |
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338 | .m1 = { .min = 12, .max = 22 }, |
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339 | .m2 = { .min = 5, .max = 9 }, |
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340 | .p = { .min = 14, .max = 56 }, |
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341 | .p1 = { .min = 2, .max = 8 }, |
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342 | .p2 = { .dot_limit = 225000, |
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343 | .p2_slow = 7, .p2_fast = 7 }, |
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344 | .find_pll = intel_g4x_find_best_PLL, |
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345 | }; |
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346 | |||
347 | /* LVDS 100mhz refclk limits. */ |
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348 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
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349 | .dot = { .min = 25000, .max = 350000 }, |
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350 | .vco = { .min = 1760000, .max = 3510000 }, |
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351 | .n = { .min = 1, .max = 2 }, |
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352 | .m = { .min = 79, .max = 126 }, |
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353 | .m1 = { .min = 12, .max = 22 }, |
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354 | .m2 = { .min = 5, .max = 9 }, |
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355 | .p = { .min = 28, .max = 112 }, |
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2342 | Serge | 356 | .p1 = { .min = 2, .max = 8 }, |
2327 | Serge | 357 | .p2 = { .dot_limit = 225000, |
358 | .p2_slow = 14, .p2_fast = 14 }, |
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359 | .find_pll = intel_g4x_find_best_PLL, |
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360 | }; |
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361 | |||
362 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
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363 | .dot = { .min = 25000, .max = 350000 }, |
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364 | .vco = { .min = 1760000, .max = 3510000 }, |
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365 | .n = { .min = 1, .max = 3 }, |
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366 | .m = { .min = 79, .max = 126 }, |
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367 | .m1 = { .min = 12, .max = 22 }, |
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368 | .m2 = { .min = 5, .max = 9 }, |
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369 | .p = { .min = 14, .max = 42 }, |
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2342 | Serge | 370 | .p1 = { .min = 2, .max = 6 }, |
2327 | Serge | 371 | .p2 = { .dot_limit = 225000, |
372 | .p2_slow = 7, .p2_fast = 7 }, |
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373 | .find_pll = intel_g4x_find_best_PLL, |
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374 | }; |
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375 | |||
376 | static const intel_limit_t intel_limits_ironlake_display_port = { |
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377 | .dot = { .min = 25000, .max = 350000 }, |
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378 | .vco = { .min = 1760000, .max = 3510000}, |
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379 | .n = { .min = 1, .max = 2 }, |
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380 | .m = { .min = 81, .max = 90 }, |
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381 | .m1 = { .min = 12, .max = 22 }, |
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382 | .m2 = { .min = 5, .max = 9 }, |
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383 | .p = { .min = 10, .max = 20 }, |
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384 | .p1 = { .min = 1, .max = 2}, |
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385 | .p2 = { .dot_limit = 0, |
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386 | .p2_slow = 10, .p2_fast = 10 }, |
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387 | .find_pll = intel_find_pll_ironlake_dp, |
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388 | }; |
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389 | |||
3031 | serge | 390 | static const intel_limit_t intel_limits_vlv_dac = { |
391 | .dot = { .min = 25000, .max = 270000 }, |
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392 | .vco = { .min = 4000000, .max = 6000000 }, |
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393 | .n = { .min = 1, .max = 7 }, |
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394 | .m = { .min = 22, .max = 450 }, /* guess */ |
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395 | .m1 = { .min = 2, .max = 3 }, |
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396 | .m2 = { .min = 11, .max = 156 }, |
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397 | .p = { .min = 10, .max = 30 }, |
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398 | .p1 = { .min = 2, .max = 3 }, |
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399 | .p2 = { .dot_limit = 270000, |
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400 | .p2_slow = 2, .p2_fast = 20 }, |
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401 | .find_pll = intel_vlv_find_best_pll, |
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402 | }; |
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403 | |||
404 | static const intel_limit_t intel_limits_vlv_hdmi = { |
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405 | .dot = { .min = 20000, .max = 165000 }, |
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406 | .vco = { .min = 5994000, .max = 4000000 }, |
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407 | .n = { .min = 1, .max = 7 }, |
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408 | .m = { .min = 60, .max = 300 }, /* guess */ |
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409 | .m1 = { .min = 2, .max = 3 }, |
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410 | .m2 = { .min = 11, .max = 156 }, |
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411 | .p = { .min = 10, .max = 30 }, |
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412 | .p1 = { .min = 2, .max = 3 }, |
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413 | .p2 = { .dot_limit = 270000, |
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414 | .p2_slow = 2, .p2_fast = 20 }, |
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415 | .find_pll = intel_vlv_find_best_pll, |
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416 | }; |
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417 | |||
418 | static const intel_limit_t intel_limits_vlv_dp = { |
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419 | .dot = { .min = 162000, .max = 270000 }, |
||
420 | .vco = { .min = 5994000, .max = 4000000 }, |
||
421 | .n = { .min = 1, .max = 7 }, |
||
422 | .m = { .min = 60, .max = 300 }, /* guess */ |
||
423 | .m1 = { .min = 2, .max = 3 }, |
||
424 | .m2 = { .min = 11, .max = 156 }, |
||
425 | .p = { .min = 10, .max = 30 }, |
||
426 | .p1 = { .min = 2, .max = 3 }, |
||
427 | .p2 = { .dot_limit = 270000, |
||
428 | .p2_slow = 2, .p2_fast = 20 }, |
||
429 | .find_pll = intel_vlv_find_best_pll, |
||
430 | }; |
||
431 | |||
432 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
||
433 | { |
||
434 | unsigned long flags; |
||
435 | u32 val = 0; |
||
436 | |||
437 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
||
438 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
||
439 | DRM_ERROR("DPIO idle wait timed out\n"); |
||
440 | goto out_unlock; |
||
441 | } |
||
442 | |||
443 | I915_WRITE(DPIO_REG, reg); |
||
444 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | |
||
445 | DPIO_BYTE); |
||
446 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
||
447 | DRM_ERROR("DPIO read wait timed out\n"); |
||
448 | goto out_unlock; |
||
449 | } |
||
450 | val = I915_READ(DPIO_DATA); |
||
451 | |||
452 | out_unlock: |
||
453 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
||
454 | return val; |
||
455 | } |
||
456 | |||
457 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
||
458 | u32 val) |
||
459 | { |
||
460 | unsigned long flags; |
||
461 | |||
462 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
||
463 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
||
464 | DRM_ERROR("DPIO idle wait timed out\n"); |
||
465 | goto out_unlock; |
||
466 | } |
||
467 | |||
468 | I915_WRITE(DPIO_DATA, val); |
||
469 | I915_WRITE(DPIO_REG, reg); |
||
470 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | |
||
471 | DPIO_BYTE); |
||
472 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) |
||
473 | DRM_ERROR("DPIO write wait timed out\n"); |
||
474 | |||
475 | out_unlock: |
||
476 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
||
477 | } |
||
478 | |||
479 | static void vlv_init_dpio(struct drm_device *dev) |
||
480 | { |
||
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
482 | |||
483 | /* Reset the DPIO config */ |
||
484 | I915_WRITE(DPIO_CTL, 0); |
||
485 | POSTING_READ(DPIO_CTL); |
||
486 | I915_WRITE(DPIO_CTL, 1); |
||
487 | POSTING_READ(DPIO_CTL); |
||
488 | } |
||
489 | |||
490 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
||
491 | { |
||
492 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); |
||
493 | return 1; |
||
494 | } |
||
495 | |||
496 | static const struct dmi_system_id intel_dual_link_lvds[] = { |
||
497 | { |
||
498 | .callback = intel_dual_link_lvds_callback, |
||
499 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", |
||
500 | .matches = { |
||
501 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
||
502 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), |
||
503 | }, |
||
504 | }, |
||
505 | { } /* terminating entry */ |
||
506 | }; |
||
507 | |||
508 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
||
509 | unsigned int reg) |
||
510 | { |
||
511 | unsigned int val; |
||
512 | |||
513 | /* use the module option value if specified */ |
||
514 | if (i915_lvds_channel_mode > 0) |
||
515 | return i915_lvds_channel_mode == 2; |
||
516 | |||
517 | // if (dmi_check_system(intel_dual_link_lvds)) |
||
518 | // return true; |
||
519 | |||
520 | if (dev_priv->lvds_val) |
||
521 | val = dev_priv->lvds_val; |
||
522 | else { |
||
523 | /* BIOS should set the proper LVDS register value at boot, but |
||
524 | * in reality, it doesn't set the value when the lid is closed; |
||
525 | * we need to check "the value to be set" in VBT when LVDS |
||
526 | * register is uninitialized. |
||
527 | */ |
||
528 | val = I915_READ(reg); |
||
529 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
||
530 | val = dev_priv->bios_lvds_val; |
||
531 | dev_priv->lvds_val = val; |
||
532 | } |
||
533 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
||
534 | } |
||
535 | |||
2327 | Serge | 536 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
537 | int refclk) |
||
538 | { |
||
539 | struct drm_device *dev = crtc->dev; |
||
540 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
541 | const intel_limit_t *limit; |
||
542 | |||
543 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
||
3031 | serge | 544 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
2327 | Serge | 545 | /* LVDS dual channel */ |
546 | if (refclk == 100000) |
||
547 | limit = &intel_limits_ironlake_dual_lvds_100m; |
||
548 | else |
||
549 | limit = &intel_limits_ironlake_dual_lvds; |
||
550 | } else { |
||
551 | if (refclk == 100000) |
||
552 | limit = &intel_limits_ironlake_single_lvds_100m; |
||
553 | else |
||
554 | limit = &intel_limits_ironlake_single_lvds; |
||
555 | } |
||
556 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
||
557 | HAS_eDP) |
||
558 | limit = &intel_limits_ironlake_display_port; |
||
559 | else |
||
560 | limit = &intel_limits_ironlake_dac; |
||
561 | |||
562 | return limit; |
||
563 | } |
||
564 | |||
565 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
||
566 | { |
||
567 | struct drm_device *dev = crtc->dev; |
||
568 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
569 | const intel_limit_t *limit; |
||
570 | |||
571 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
||
3031 | serge | 572 | if (is_dual_link_lvds(dev_priv, LVDS)) |
2327 | Serge | 573 | /* LVDS with dual channel */ |
574 | limit = &intel_limits_g4x_dual_channel_lvds; |
||
575 | else |
||
576 | /* LVDS with dual channel */ |
||
577 | limit = &intel_limits_g4x_single_channel_lvds; |
||
578 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
||
579 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
||
580 | limit = &intel_limits_g4x_hdmi; |
||
581 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
||
582 | limit = &intel_limits_g4x_sdvo; |
||
2342 | Serge | 583 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
2327 | Serge | 584 | limit = &intel_limits_g4x_display_port; |
585 | } else /* The option is for other outputs */ |
||
586 | limit = &intel_limits_i9xx_sdvo; |
||
587 | |||
588 | return limit; |
||
589 | } |
||
590 | |||
591 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
||
592 | { |
||
593 | struct drm_device *dev = crtc->dev; |
||
594 | const intel_limit_t *limit; |
||
595 | |||
596 | if (HAS_PCH_SPLIT(dev)) |
||
597 | limit = intel_ironlake_limit(crtc, refclk); |
||
598 | else if (IS_G4X(dev)) { |
||
599 | limit = intel_g4x_limit(crtc); |
||
600 | } else if (IS_PINEVIEW(dev)) { |
||
601 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
||
602 | limit = &intel_limits_pineview_lvds; |
||
603 | else |
||
604 | limit = &intel_limits_pineview_sdvo; |
||
3031 | serge | 605 | } else if (IS_VALLEYVIEW(dev)) { |
606 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
||
607 | limit = &intel_limits_vlv_dac; |
||
608 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
||
609 | limit = &intel_limits_vlv_hdmi; |
||
610 | else |
||
611 | limit = &intel_limits_vlv_dp; |
||
2327 | Serge | 612 | } else if (!IS_GEN2(dev)) { |
613 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
||
614 | limit = &intel_limits_i9xx_lvds; |
||
615 | else |
||
616 | limit = &intel_limits_i9xx_sdvo; |
||
617 | } else { |
||
618 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
||
619 | limit = &intel_limits_i8xx_lvds; |
||
620 | else |
||
621 | limit = &intel_limits_i8xx_dvo; |
||
622 | } |
||
623 | return limit; |
||
624 | } |
||
625 | |||
626 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
||
627 | static void pineview_clock(int refclk, intel_clock_t *clock) |
||
628 | { |
||
629 | clock->m = clock->m2 + 2; |
||
630 | clock->p = clock->p1 * clock->p2; |
||
631 | clock->vco = refclk * clock->m / clock->n; |
||
632 | clock->dot = clock->vco / clock->p; |
||
633 | } |
||
634 | |||
635 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
||
636 | { |
||
637 | if (IS_PINEVIEW(dev)) { |
||
638 | pineview_clock(refclk, clock); |
||
639 | return; |
||
640 | } |
||
641 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
||
642 | clock->p = clock->p1 * clock->p2; |
||
643 | clock->vco = refclk * clock->m / (clock->n + 2); |
||
644 | clock->dot = clock->vco / clock->p; |
||
645 | } |
||
646 | |||
647 | /** |
||
648 | * Returns whether any output on the specified pipe is of the specified type |
||
649 | */ |
||
650 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
||
651 | { |
||
652 | struct drm_device *dev = crtc->dev; |
||
653 | struct intel_encoder *encoder; |
||
654 | |||
3031 | serge | 655 | for_each_encoder_on_crtc(dev, crtc, encoder) |
656 | if (encoder->type == type) |
||
2327 | Serge | 657 | return true; |
658 | |||
659 | return false; |
||
660 | } |
||
661 | |||
662 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
||
663 | /** |
||
664 | * Returns whether the given set of divisors are valid for a given refclk with |
||
665 | * the given connectors. |
||
666 | */ |
||
667 | |||
668 | static bool intel_PLL_is_valid(struct drm_device *dev, |
||
669 | const intel_limit_t *limit, |
||
670 | const intel_clock_t *clock) |
||
671 | { |
||
672 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
||
2342 | Serge | 673 | INTELPllInvalid("p1 out of range\n"); |
2327 | Serge | 674 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
2342 | Serge | 675 | INTELPllInvalid("p out of range\n"); |
2327 | Serge | 676 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
2342 | Serge | 677 | INTELPllInvalid("m2 out of range\n"); |
2327 | Serge | 678 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
2342 | Serge | 679 | INTELPllInvalid("m1 out of range\n"); |
2327 | Serge | 680 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
2342 | Serge | 681 | INTELPllInvalid("m1 <= m2\n"); |
2327 | Serge | 682 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
2342 | Serge | 683 | INTELPllInvalid("m out of range\n"); |
2327 | Serge | 684 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
2342 | Serge | 685 | INTELPllInvalid("n out of range\n"); |
2327 | Serge | 686 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
2342 | Serge | 687 | INTELPllInvalid("vco out of range\n"); |
2327 | Serge | 688 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
689 | * connector, etc., rather than just a single range. |
||
690 | */ |
||
691 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
||
2342 | Serge | 692 | INTELPllInvalid("dot out of range\n"); |
2327 | Serge | 693 | |
694 | return true; |
||
695 | } |
||
696 | |||
697 | static bool |
||
698 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
||
3031 | serge | 699 | int target, int refclk, intel_clock_t *match_clock, |
700 | intel_clock_t *best_clock) |
||
2327 | Serge | 701 | |
702 | { |
||
703 | struct drm_device *dev = crtc->dev; |
||
704 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
705 | intel_clock_t clock; |
||
706 | int err = target; |
||
707 | |||
708 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
||
709 | (I915_READ(LVDS)) != 0) { |
||
710 | /* |
||
711 | * For LVDS, if the panel is on, just rely on its current |
||
712 | * settings for dual-channel. We haven't figured out how to |
||
713 | * reliably set up different single/dual channel state, if we |
||
714 | * even can. |
||
715 | */ |
||
3031 | serge | 716 | if (is_dual_link_lvds(dev_priv, LVDS)) |
2327 | Serge | 717 | clock.p2 = limit->p2.p2_fast; |
718 | else |
||
719 | clock.p2 = limit->p2.p2_slow; |
||
720 | } else { |
||
721 | if (target < limit->p2.dot_limit) |
||
722 | clock.p2 = limit->p2.p2_slow; |
||
723 | else |
||
724 | clock.p2 = limit->p2.p2_fast; |
||
725 | } |
||
726 | |||
2342 | Serge | 727 | memset(best_clock, 0, sizeof(*best_clock)); |
2327 | Serge | 728 | |
729 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
||
730 | clock.m1++) { |
||
731 | for (clock.m2 = limit->m2.min; |
||
732 | clock.m2 <= limit->m2.max; clock.m2++) { |
||
733 | /* m1 is always 0 in Pineview */ |
||
734 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) |
||
735 | break; |
||
736 | for (clock.n = limit->n.min; |
||
737 | clock.n <= limit->n.max; clock.n++) { |
||
738 | for (clock.p1 = limit->p1.min; |
||
739 | clock.p1 <= limit->p1.max; clock.p1++) { |
||
740 | int this_err; |
||
741 | |||
742 | intel_clock(dev, refclk, &clock); |
||
743 | if (!intel_PLL_is_valid(dev, limit, |
||
744 | &clock)) |
||
745 | continue; |
||
3031 | serge | 746 | if (match_clock && |
747 | clock.p != match_clock->p) |
||
748 | continue; |
||
2327 | Serge | 749 | |
750 | this_err = abs(clock.dot - target); |
||
751 | if (this_err < err) { |
||
752 | *best_clock = clock; |
||
753 | err = this_err; |
||
754 | } |
||
755 | } |
||
756 | } |
||
757 | } |
||
758 | } |
||
759 | |||
760 | return (err != target); |
||
761 | } |
||
762 | |||
763 | static bool |
||
764 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
||
3031 | serge | 765 | int target, int refclk, intel_clock_t *match_clock, |
766 | intel_clock_t *best_clock) |
||
2327 | Serge | 767 | { |
768 | struct drm_device *dev = crtc->dev; |
||
769 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
770 | intel_clock_t clock; |
||
771 | int max_n; |
||
772 | bool found; |
||
773 | /* approximately equals target * 0.00585 */ |
||
774 | int err_most = (target >> 8) + (target >> 9); |
||
775 | found = false; |
||
776 | |||
777 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
||
778 | int lvds_reg; |
||
779 | |||
780 | if (HAS_PCH_SPLIT(dev)) |
||
781 | lvds_reg = PCH_LVDS; |
||
782 | else |
||
783 | lvds_reg = LVDS; |
||
784 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == |
||
785 | LVDS_CLKB_POWER_UP) |
||
786 | clock.p2 = limit->p2.p2_fast; |
||
787 | else |
||
788 | clock.p2 = limit->p2.p2_slow; |
||
789 | } else { |
||
790 | if (target < limit->p2.dot_limit) |
||
791 | clock.p2 = limit->p2.p2_slow; |
||
792 | else |
||
793 | clock.p2 = limit->p2.p2_fast; |
||
794 | } |
||
795 | |||
796 | memset(best_clock, 0, sizeof(*best_clock)); |
||
797 | max_n = limit->n.max; |
||
798 | /* based on hardware requirement, prefer smaller n to precision */ |
||
799 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
||
800 | /* based on hardware requirement, prefere larger m1,m2 */ |
||
801 | for (clock.m1 = limit->m1.max; |
||
802 | clock.m1 >= limit->m1.min; clock.m1--) { |
||
803 | for (clock.m2 = limit->m2.max; |
||
804 | clock.m2 >= limit->m2.min; clock.m2--) { |
||
805 | for (clock.p1 = limit->p1.max; |
||
806 | clock.p1 >= limit->p1.min; clock.p1--) { |
||
807 | int this_err; |
||
808 | |||
809 | intel_clock(dev, refclk, &clock); |
||
810 | if (!intel_PLL_is_valid(dev, limit, |
||
811 | &clock)) |
||
812 | continue; |
||
3031 | serge | 813 | if (match_clock && |
814 | clock.p != match_clock->p) |
||
815 | continue; |
||
2327 | Serge | 816 | |
817 | this_err = abs(clock.dot - target); |
||
818 | if (this_err < err_most) { |
||
819 | *best_clock = clock; |
||
820 | err_most = this_err; |
||
821 | max_n = clock.n; |
||
822 | found = true; |
||
823 | } |
||
824 | } |
||
825 | } |
||
826 | } |
||
827 | } |
||
828 | return found; |
||
829 | } |
||
830 | |||
831 | static bool |
||
832 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
||
3031 | serge | 833 | int target, int refclk, intel_clock_t *match_clock, |
834 | intel_clock_t *best_clock) |
||
2327 | Serge | 835 | { |
836 | struct drm_device *dev = crtc->dev; |
||
837 | intel_clock_t clock; |
||
838 | |||
839 | if (target < 200000) { |
||
840 | clock.n = 1; |
||
841 | clock.p1 = 2; |
||
842 | clock.p2 = 10; |
||
843 | clock.m1 = 12; |
||
844 | clock.m2 = 9; |
||
845 | } else { |
||
846 | clock.n = 2; |
||
847 | clock.p1 = 1; |
||
848 | clock.p2 = 10; |
||
849 | clock.m1 = 14; |
||
850 | clock.m2 = 8; |
||
851 | } |
||
852 | intel_clock(dev, refclk, &clock); |
||
853 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
||
854 | return true; |
||
855 | } |
||
856 | |||
857 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
||
858 | static bool |
||
859 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
||
3031 | serge | 860 | int target, int refclk, intel_clock_t *match_clock, |
861 | intel_clock_t *best_clock) |
||
2327 | Serge | 862 | { |
863 | intel_clock_t clock; |
||
864 | if (target < 200000) { |
||
865 | clock.p1 = 2; |
||
866 | clock.p2 = 10; |
||
867 | clock.n = 2; |
||
868 | clock.m1 = 23; |
||
869 | clock.m2 = 8; |
||
870 | } else { |
||
871 | clock.p1 = 1; |
||
872 | clock.p2 = 10; |
||
873 | clock.n = 1; |
||
874 | clock.m1 = 14; |
||
875 | clock.m2 = 2; |
||
876 | } |
||
877 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
||
878 | clock.p = (clock.p1 * clock.p2); |
||
879 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
||
880 | clock.vco = 0; |
||
881 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
||
882 | return true; |
||
883 | } |
||
3031 | serge | 884 | static bool |
885 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, |
||
886 | int target, int refclk, intel_clock_t *match_clock, |
||
887 | intel_clock_t *best_clock) |
||
888 | { |
||
889 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
||
890 | u32 m, n, fastclk; |
||
891 | u32 updrate, minupdate, fracbits, p; |
||
892 | unsigned long bestppm, ppm, absppm; |
||
893 | int dotclk, flag; |
||
2327 | Serge | 894 | |
3031 | serge | 895 | flag = 0; |
896 | dotclk = target * 1000; |
||
897 | bestppm = 1000000; |
||
898 | ppm = absppm = 0; |
||
899 | fastclk = dotclk / (2*100); |
||
900 | updrate = 0; |
||
901 | minupdate = 19200; |
||
902 | fracbits = 1; |
||
903 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
||
904 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
||
905 | |||
906 | /* based on hardware requirement, prefer smaller n to precision */ |
||
907 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
||
908 | updrate = refclk / n; |
||
909 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
||
910 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
||
911 | if (p2 > 10) |
||
912 | p2 = p2 - 1; |
||
913 | p = p1 * p2; |
||
914 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
||
915 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
||
916 | m2 = (((2*(fastclk * p * n / m1 )) + |
||
917 | refclk) / (2*refclk)); |
||
918 | m = m1 * m2; |
||
919 | vco = updrate * m; |
||
920 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
||
921 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
||
922 | absppm = (ppm > 0) ? ppm : (-ppm); |
||
923 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
||
924 | bestppm = 0; |
||
925 | flag = 1; |
||
926 | } |
||
927 | if (absppm < bestppm - 10) { |
||
928 | bestppm = absppm; |
||
929 | flag = 1; |
||
930 | } |
||
931 | if (flag) { |
||
932 | bestn = n; |
||
933 | bestm1 = m1; |
||
934 | bestm2 = m2; |
||
935 | bestp1 = p1; |
||
936 | bestp2 = p2; |
||
937 | flag = 0; |
||
938 | } |
||
939 | } |
||
940 | } |
||
941 | } |
||
942 | } |
||
943 | } |
||
944 | best_clock->n = bestn; |
||
945 | best_clock->m1 = bestm1; |
||
946 | best_clock->m2 = bestm2; |
||
947 | best_clock->p1 = bestp1; |
||
948 | best_clock->p2 = bestp2; |
||
949 | |||
950 | return true; |
||
951 | } |
||
952 | |||
953 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
||
954 | { |
||
955 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
956 | u32 frame, frame_reg = PIPEFRAME(pipe); |
||
957 | |||
958 | frame = I915_READ(frame_reg); |
||
959 | |||
960 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
||
961 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
||
962 | } |
||
963 | |||
2327 | Serge | 964 | /** |
965 | * intel_wait_for_vblank - wait for vblank on a given pipe |
||
966 | * @dev: drm device |
||
967 | * @pipe: pipe to wait for |
||
968 | * |
||
969 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
||
970 | * mode setting code. |
||
971 | */ |
||
972 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
||
973 | { |
||
974 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
975 | int pipestat_reg = PIPESTAT(pipe); |
||
976 | |||
3031 | serge | 977 | if (INTEL_INFO(dev)->gen >= 5) { |
978 | ironlake_wait_for_vblank(dev, pipe); |
||
979 | return; |
||
980 | } |
||
981 | |||
2327 | Serge | 982 | /* Clear existing vblank status. Note this will clear any other |
983 | * sticky status fields as well. |
||
984 | * |
||
985 | * This races with i915_driver_irq_handler() with the result |
||
986 | * that either function could miss a vblank event. Here it is not |
||
987 | * fatal, as we will either wait upon the next vblank interrupt or |
||
988 | * timeout. Generally speaking intel_wait_for_vblank() is only |
||
989 | * called during modeset at which time the GPU should be idle and |
||
990 | * should *not* be performing page flips and thus not waiting on |
||
991 | * vblanks... |
||
992 | * Currently, the result of us stealing a vblank from the irq |
||
993 | * handler is that a single frame will be skipped during swapbuffers. |
||
994 | */ |
||
995 | I915_WRITE(pipestat_reg, |
||
996 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
||
997 | |||
998 | /* Wait for vblank interrupt bit to set */ |
||
999 | if (wait_for(I915_READ(pipestat_reg) & |
||
1000 | PIPE_VBLANK_INTERRUPT_STATUS, |
||
1001 | 50)) |
||
1002 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
||
1003 | } |
||
1004 | |||
1005 | /* |
||
1006 | * intel_wait_for_pipe_off - wait for pipe to turn off |
||
1007 | * @dev: drm device |
||
1008 | * @pipe: pipe to wait for |
||
1009 | * |
||
1010 | * After disabling a pipe, we can't wait for vblank in the usual way, |
||
1011 | * spinning on the vblank interrupt status bit, since we won't actually |
||
1012 | * see an interrupt when the pipe is disabled. |
||
1013 | * |
||
1014 | * On Gen4 and above: |
||
1015 | * wait for the pipe register state bit to turn off |
||
1016 | * |
||
1017 | * Otherwise: |
||
1018 | * wait for the display line value to settle (it usually |
||
1019 | * ends up stopping at the start of the next frame). |
||
1020 | * |
||
1021 | */ |
||
1022 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
||
1023 | { |
||
1024 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1025 | |||
1026 | if (INTEL_INFO(dev)->gen >= 4) { |
||
1027 | int reg = PIPECONF(pipe); |
||
1028 | |||
1029 | /* Wait for the Pipe State to go off */ |
||
1030 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
||
1031 | 100)) |
||
3031 | serge | 1032 | WARN(1, "pipe_off wait timed out\n"); |
2327 | Serge | 1033 | } else { |
3031 | serge | 1034 | u32 last_line, line_mask; |
2327 | Serge | 1035 | int reg = PIPEDSL(pipe); |
3031 | serge | 1036 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
2327 | Serge | 1037 | |
3031 | serge | 1038 | if (IS_GEN2(dev)) |
1039 | line_mask = DSL_LINEMASK_GEN2; |
||
1040 | else |
||
1041 | line_mask = DSL_LINEMASK_GEN3; |
||
1042 | |||
2327 | Serge | 1043 | /* Wait for the display line to settle */ |
1044 | do { |
||
3031 | serge | 1045 | last_line = I915_READ(reg) & line_mask; |
2327 | Serge | 1046 | mdelay(5); |
3031 | serge | 1047 | } while (((I915_READ(reg) & line_mask) != last_line) && |
1048 | time_after(timeout, GetTimerTicks())); |
||
1049 | if (time_after(GetTimerTicks(), timeout)) |
||
1050 | WARN(1, "pipe_off wait timed out\n"); |
||
2327 | Serge | 1051 | } |
1052 | } |
||
1053 | |||
1054 | static const char *state_string(bool enabled) |
||
1055 | { |
||
1056 | return enabled ? "on" : "off"; |
||
1057 | } |
||
1058 | |||
1059 | /* Only for pre-ILK configs */ |
||
1060 | static void assert_pll(struct drm_i915_private *dev_priv, |
||
1061 | enum pipe pipe, bool state) |
||
1062 | { |
||
1063 | int reg; |
||
1064 | u32 val; |
||
1065 | bool cur_state; |
||
1066 | |||
1067 | reg = DPLL(pipe); |
||
1068 | val = I915_READ(reg); |
||
1069 | cur_state = !!(val & DPLL_VCO_ENABLE); |
||
1070 | WARN(cur_state != state, |
||
1071 | "PLL state assertion failure (expected %s, current %s)\n", |
||
1072 | state_string(state), state_string(cur_state)); |
||
1073 | } |
||
1074 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
||
1075 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
||
1076 | |||
1077 | /* For ILK+ */ |
||
1078 | static void assert_pch_pll(struct drm_i915_private *dev_priv, |
||
3031 | serge | 1079 | struct intel_pch_pll *pll, |
1080 | struct intel_crtc *crtc, |
||
1081 | bool state) |
||
2327 | Serge | 1082 | { |
1083 | u32 val; |
||
1084 | bool cur_state; |
||
1085 | |||
3031 | serge | 1086 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1087 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
||
1088 | return; |
||
1089 | } |
||
2342 | Serge | 1090 | |
3031 | serge | 1091 | if (WARN (!pll, |
1092 | "asserting PCH PLL %s with no PLL\n", state_string(state))) |
||
1093 | return; |
||
2342 | Serge | 1094 | |
3031 | serge | 1095 | val = I915_READ(pll->pll_reg); |
1096 | cur_state = !!(val & DPLL_VCO_ENABLE); |
||
1097 | WARN(cur_state != state, |
||
1098 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", |
||
1099 | pll->pll_reg, state_string(state), state_string(cur_state), val); |
||
2342 | Serge | 1100 | |
3031 | serge | 1101 | /* Make sure the selected PLL is correctly attached to the transcoder */ |
1102 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { |
||
1103 | u32 pch_dpll; |
||
2342 | Serge | 1104 | |
3031 | serge | 1105 | pch_dpll = I915_READ(PCH_DPLL_SEL); |
1106 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
||
1107 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, |
||
1108 | "PLL[%d] not attached to this transcoder %d: %08x\n", |
||
1109 | cur_state, crtc->pipe, pch_dpll)) { |
||
1110 | cur_state = !!(val >> (4*crtc->pipe + 3)); |
||
2327 | Serge | 1111 | WARN(cur_state != state, |
3031 | serge | 1112 | "PLL[%d] not %s on this transcoder %d: %08x\n", |
1113 | pll->pll_reg == _PCH_DPLL_B, |
||
1114 | state_string(state), |
||
1115 | crtc->pipe, |
||
1116 | val); |
||
1117 | } |
||
1118 | } |
||
2327 | Serge | 1119 | } |
3031 | serge | 1120 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1121 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) |
||
2327 | Serge | 1122 | |
1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
||
1124 | enum pipe pipe, bool state) |
||
1125 | { |
||
1126 | int reg; |
||
1127 | u32 val; |
||
1128 | bool cur_state; |
||
1129 | |||
3031 | serge | 1130 | if (IS_HASWELL(dev_priv->dev)) { |
1131 | /* On Haswell, DDI is used instead of FDI_TX_CTL */ |
||
1132 | reg = DDI_FUNC_CTL(pipe); |
||
1133 | val = I915_READ(reg); |
||
1134 | cur_state = !!(val & PIPE_DDI_FUNC_ENABLE); |
||
1135 | } else { |
||
2327 | Serge | 1136 | reg = FDI_TX_CTL(pipe); |
1137 | val = I915_READ(reg); |
||
1138 | cur_state = !!(val & FDI_TX_ENABLE); |
||
3031 | serge | 1139 | } |
2327 | Serge | 1140 | WARN(cur_state != state, |
1141 | "FDI TX state assertion failure (expected %s, current %s)\n", |
||
1142 | state_string(state), state_string(cur_state)); |
||
1143 | } |
||
1144 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
||
1145 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
||
1146 | |||
1147 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
||
1148 | enum pipe pipe, bool state) |
||
1149 | { |
||
1150 | int reg; |
||
1151 | u32 val; |
||
1152 | bool cur_state; |
||
1153 | |||
3031 | serge | 1154 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1155 | DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n"); |
||
1156 | return; |
||
1157 | } else { |
||
2327 | Serge | 1158 | reg = FDI_RX_CTL(pipe); |
1159 | val = I915_READ(reg); |
||
1160 | cur_state = !!(val & FDI_RX_ENABLE); |
||
3031 | serge | 1161 | } |
2327 | Serge | 1162 | WARN(cur_state != state, |
1163 | "FDI RX state assertion failure (expected %s, current %s)\n", |
||
1164 | state_string(state), state_string(cur_state)); |
||
1165 | } |
||
1166 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
||
1167 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
||
1168 | |||
1169 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
||
1170 | enum pipe pipe) |
||
1171 | { |
||
1172 | int reg; |
||
1173 | u32 val; |
||
1174 | |||
1175 | /* ILK FDI PLL is always enabled */ |
||
1176 | if (dev_priv->info->gen == 5) |
||
1177 | return; |
||
1178 | |||
3031 | serge | 1179 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1180 | if (IS_HASWELL(dev_priv->dev)) |
||
1181 | return; |
||
1182 | |||
2327 | Serge | 1183 | reg = FDI_TX_CTL(pipe); |
1184 | val = I915_READ(reg); |
||
1185 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
||
1186 | } |
||
1187 | |||
1188 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, |
||
1189 | enum pipe pipe) |
||
1190 | { |
||
1191 | int reg; |
||
1192 | u32 val; |
||
1193 | |||
3031 | serge | 1194 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1195 | DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n"); |
||
1196 | return; |
||
1197 | } |
||
2327 | Serge | 1198 | reg = FDI_RX_CTL(pipe); |
1199 | val = I915_READ(reg); |
||
1200 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); |
||
1201 | } |
||
1202 | |||
1203 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
||
1204 | enum pipe pipe) |
||
1205 | { |
||
1206 | int pp_reg, lvds_reg; |
||
1207 | u32 val; |
||
1208 | enum pipe panel_pipe = PIPE_A; |
||
1209 | bool locked = true; |
||
1210 | |||
1211 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
||
1212 | pp_reg = PCH_PP_CONTROL; |
||
1213 | lvds_reg = PCH_LVDS; |
||
1214 | } else { |
||
1215 | pp_reg = PP_CONTROL; |
||
1216 | lvds_reg = LVDS; |
||
1217 | } |
||
1218 | |||
1219 | val = I915_READ(pp_reg); |
||
1220 | if (!(val & PANEL_POWER_ON) || |
||
1221 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
||
1222 | locked = false; |
||
1223 | |||
1224 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
||
1225 | panel_pipe = PIPE_B; |
||
1226 | |||
1227 | WARN(panel_pipe == pipe && locked, |
||
1228 | "panel assertion failure, pipe %c regs locked\n", |
||
1229 | pipe_name(pipe)); |
||
1230 | } |
||
1231 | |||
2342 | Serge | 1232 | void assert_pipe(struct drm_i915_private *dev_priv, |
2327 | Serge | 1233 | enum pipe pipe, bool state) |
1234 | { |
||
1235 | int reg; |
||
1236 | u32 val; |
||
1237 | bool cur_state; |
||
1238 | |||
3031 | serge | 1239 | /* if we need the pipe A quirk it must be always on */ |
1240 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
||
1241 | state = true; |
||
1242 | |||
2327 | Serge | 1243 | reg = PIPECONF(pipe); |
1244 | val = I915_READ(reg); |
||
1245 | cur_state = !!(val & PIPECONF_ENABLE); |
||
1246 | WARN(cur_state != state, |
||
1247 | "pipe %c assertion failure (expected %s, current %s)\n", |
||
1248 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
||
1249 | } |
||
1250 | |||
3031 | serge | 1251 | static void assert_plane(struct drm_i915_private *dev_priv, |
1252 | enum plane plane, bool state) |
||
2327 | Serge | 1253 | { |
1254 | int reg; |
||
1255 | u32 val; |
||
3031 | serge | 1256 | bool cur_state; |
2327 | Serge | 1257 | |
1258 | reg = DSPCNTR(plane); |
||
1259 | val = I915_READ(reg); |
||
3031 | serge | 1260 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1261 | WARN(cur_state != state, |
||
1262 | "plane %c assertion failure (expected %s, current %s)\n", |
||
1263 | plane_name(plane), state_string(state), state_string(cur_state)); |
||
2327 | Serge | 1264 | } |
1265 | |||
3031 | serge | 1266 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1267 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
||
1268 | |||
2327 | Serge | 1269 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1270 | enum pipe pipe) |
||
1271 | { |
||
1272 | int reg, i; |
||
1273 | u32 val; |
||
1274 | int cur_pipe; |
||
1275 | |||
1276 | /* Planes are fixed to pipes on ILK+ */ |
||
3031 | serge | 1277 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1278 | reg = DSPCNTR(pipe); |
||
1279 | val = I915_READ(reg); |
||
1280 | WARN((val & DISPLAY_PLANE_ENABLE), |
||
1281 | "plane %c assertion failure, should be disabled but not\n", |
||
1282 | plane_name(pipe)); |
||
2327 | Serge | 1283 | return; |
3031 | serge | 1284 | } |
2327 | Serge | 1285 | |
1286 | /* Need to check both planes against the pipe */ |
||
1287 | for (i = 0; i < 2; i++) { |
||
1288 | reg = DSPCNTR(i); |
||
1289 | val = I915_READ(reg); |
||
1290 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
||
1291 | DISPPLANE_SEL_PIPE_SHIFT; |
||
1292 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
||
1293 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
||
1294 | plane_name(i), pipe_name(pipe)); |
||
1295 | } |
||
1296 | } |
||
1297 | |||
1298 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
||
1299 | { |
||
1300 | u32 val; |
||
1301 | bool enabled; |
||
1302 | |||
3031 | serge | 1303 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1304 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
||
1305 | return; |
||
1306 | } |
||
1307 | |||
2327 | Serge | 1308 | val = I915_READ(PCH_DREF_CONTROL); |
1309 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
||
1310 | DREF_SUPERSPREAD_SOURCE_MASK)); |
||
1311 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
||
1312 | } |
||
1313 | |||
1314 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, |
||
1315 | enum pipe pipe) |
||
1316 | { |
||
1317 | int reg; |
||
1318 | u32 val; |
||
1319 | bool enabled; |
||
1320 | |||
1321 | reg = TRANSCONF(pipe); |
||
1322 | val = I915_READ(reg); |
||
1323 | enabled = !!(val & TRANS_ENABLE); |
||
1324 | WARN(enabled, |
||
1325 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
||
1326 | pipe_name(pipe)); |
||
1327 | } |
||
1328 | |||
1329 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
||
1330 | enum pipe pipe, u32 port_sel, u32 val) |
||
1331 | { |
||
1332 | if ((val & DP_PORT_EN) == 0) |
||
1333 | return false; |
||
1334 | |||
1335 | if (HAS_PCH_CPT(dev_priv->dev)) { |
||
1336 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
||
1337 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
||
1338 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
||
1339 | return false; |
||
1340 | } else { |
||
1341 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
||
1342 | return false; |
||
1343 | } |
||
1344 | return true; |
||
1345 | } |
||
1346 | |||
1347 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
||
1348 | enum pipe pipe, u32 val) |
||
1349 | { |
||
1350 | if ((val & PORT_ENABLE) == 0) |
||
1351 | return false; |
||
1352 | |||
1353 | if (HAS_PCH_CPT(dev_priv->dev)) { |
||
1354 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
||
1355 | return false; |
||
1356 | } else { |
||
1357 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) |
||
1358 | return false; |
||
1359 | } |
||
1360 | return true; |
||
1361 | } |
||
1362 | |||
1363 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
||
1364 | enum pipe pipe, u32 val) |
||
1365 | { |
||
1366 | if ((val & LVDS_PORT_EN) == 0) |
||
1367 | return false; |
||
1368 | |||
1369 | if (HAS_PCH_CPT(dev_priv->dev)) { |
||
1370 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
||
1371 | return false; |
||
1372 | } else { |
||
1373 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
||
1374 | return false; |
||
1375 | } |
||
1376 | return true; |
||
1377 | } |
||
1378 | |||
1379 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
||
1380 | enum pipe pipe, u32 val) |
||
1381 | { |
||
1382 | if ((val & ADPA_DAC_ENABLE) == 0) |
||
1383 | return false; |
||
1384 | if (HAS_PCH_CPT(dev_priv->dev)) { |
||
1385 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
||
1386 | return false; |
||
1387 | } else { |
||
1388 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
||
1389 | return false; |
||
1390 | } |
||
1391 | return true; |
||
1392 | } |
||
1393 | |||
1394 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
||
1395 | enum pipe pipe, int reg, u32 port_sel) |
||
1396 | { |
||
1397 | u32 val = I915_READ(reg); |
||
1398 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
||
1399 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
||
1400 | reg, pipe_name(pipe)); |
||
3031 | serge | 1401 | |
1402 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
||
1403 | && (val & DP_PIPEB_SELECT), |
||
1404 | "IBX PCH dp port still using transcoder B\n"); |
||
2327 | Serge | 1405 | } |
1406 | |||
1407 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
||
1408 | enum pipe pipe, int reg) |
||
1409 | { |
||
1410 | u32 val = I915_READ(reg); |
||
3031 | serge | 1411 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1412 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
||
2327 | Serge | 1413 | reg, pipe_name(pipe)); |
3031 | serge | 1414 | |
1415 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 |
||
1416 | && (val & SDVO_PIPE_B_SELECT), |
||
1417 | "IBX PCH hdmi port still using transcoder B\n"); |
||
2327 | Serge | 1418 | } |
1419 | |||
1420 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
||
1421 | enum pipe pipe) |
||
1422 | { |
||
1423 | int reg; |
||
1424 | u32 val; |
||
1425 | |||
1426 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
||
1427 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
||
1428 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
||
1429 | |||
1430 | reg = PCH_ADPA; |
||
1431 | val = I915_READ(reg); |
||
3031 | serge | 1432 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
2327 | Serge | 1433 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1434 | pipe_name(pipe)); |
||
1435 | |||
1436 | reg = PCH_LVDS; |
||
1437 | val = I915_READ(reg); |
||
3031 | serge | 1438 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
2327 | Serge | 1439 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1440 | pipe_name(pipe)); |
||
1441 | |||
1442 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); |
||
1443 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); |
||
1444 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); |
||
1445 | } |
||
1446 | |||
1447 | /** |
||
1448 | * intel_enable_pll - enable a PLL |
||
1449 | * @dev_priv: i915 private structure |
||
1450 | * @pipe: pipe PLL to enable |
||
1451 | * |
||
1452 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to |
||
1453 | * make sure the PLL reg is writable first though, since the panel write |
||
1454 | * protect mechanism may be enabled. |
||
1455 | * |
||
1456 | * Note! This is for pre-ILK only. |
||
3031 | serge | 1457 | * |
1458 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. |
||
2327 | Serge | 1459 | */ |
1460 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
||
1461 | { |
||
1462 | int reg; |
||
1463 | u32 val; |
||
1464 | |||
1465 | /* No really, not for ILK+ */ |
||
3031 | serge | 1466 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
2327 | Serge | 1467 | |
1468 | /* PLL is protected by panel, make sure we can write it */ |
||
1469 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
||
1470 | assert_panel_unlocked(dev_priv, pipe); |
||
1471 | |||
1472 | reg = DPLL(pipe); |
||
1473 | val = I915_READ(reg); |
||
1474 | val |= DPLL_VCO_ENABLE; |
||
1475 | |||
1476 | /* We do this three times for luck */ |
||
1477 | I915_WRITE(reg, val); |
||
1478 | POSTING_READ(reg); |
||
1479 | udelay(150); /* wait for warmup */ |
||
1480 | I915_WRITE(reg, val); |
||
1481 | POSTING_READ(reg); |
||
1482 | udelay(150); /* wait for warmup */ |
||
1483 | I915_WRITE(reg, val); |
||
1484 | POSTING_READ(reg); |
||
1485 | udelay(150); /* wait for warmup */ |
||
1486 | } |
||
1487 | |||
1488 | /** |
||
1489 | * intel_disable_pll - disable a PLL |
||
1490 | * @dev_priv: i915 private structure |
||
1491 | * @pipe: pipe PLL to disable |
||
1492 | * |
||
1493 | * Disable the PLL for @pipe, making sure the pipe is off first. |
||
1494 | * |
||
1495 | * Note! This is for pre-ILK only. |
||
1496 | */ |
||
1497 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
||
1498 | { |
||
1499 | int reg; |
||
1500 | u32 val; |
||
1501 | |||
1502 | /* Don't disable pipe A or pipe A PLLs if needed */ |
||
1503 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
||
1504 | return; |
||
1505 | |||
1506 | /* Make sure the pipe isn't still relying on us */ |
||
1507 | assert_pipe_disabled(dev_priv, pipe); |
||
1508 | |||
1509 | reg = DPLL(pipe); |
||
1510 | val = I915_READ(reg); |
||
1511 | val &= ~DPLL_VCO_ENABLE; |
||
1512 | I915_WRITE(reg, val); |
||
1513 | POSTING_READ(reg); |
||
1514 | } |
||
1515 | |||
3031 | serge | 1516 | /* SBI access */ |
1517 | static void |
||
1518 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value) |
||
1519 | { |
||
1520 | unsigned long flags; |
||
1521 | |||
1522 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
||
1523 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
||
1524 | 100)) { |
||
1525 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
||
1526 | goto out_unlock; |
||
1527 | } |
||
1528 | |||
1529 | I915_WRITE(SBI_ADDR, |
||
1530 | (reg << 16)); |
||
1531 | I915_WRITE(SBI_DATA, |
||
1532 | value); |
||
1533 | I915_WRITE(SBI_CTL_STAT, |
||
1534 | SBI_BUSY | |
||
1535 | SBI_CTL_OP_CRWR); |
||
1536 | |||
1537 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
||
1538 | 100)) { |
||
1539 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
||
1540 | goto out_unlock; |
||
1541 | } |
||
1542 | |||
1543 | out_unlock: |
||
1544 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
||
1545 | } |
||
1546 | |||
1547 | static u32 |
||
1548 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg) |
||
1549 | { |
||
1550 | unsigned long flags; |
||
1551 | u32 value = 0; |
||
1552 | |||
1553 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
||
1554 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
||
1555 | 100)) { |
||
1556 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
||
1557 | goto out_unlock; |
||
1558 | } |
||
1559 | |||
1560 | I915_WRITE(SBI_ADDR, |
||
1561 | (reg << 16)); |
||
1562 | I915_WRITE(SBI_CTL_STAT, |
||
1563 | SBI_BUSY | |
||
1564 | SBI_CTL_OP_CRRD); |
||
1565 | |||
1566 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
||
1567 | 100)) { |
||
1568 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); |
||
1569 | goto out_unlock; |
||
1570 | } |
||
1571 | |||
1572 | value = I915_READ(SBI_DATA); |
||
1573 | |||
1574 | out_unlock: |
||
1575 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
||
1576 | return value; |
||
1577 | } |
||
1578 | |||
2327 | Serge | 1579 | /** |
1580 | * intel_enable_pch_pll - enable PCH PLL |
||
1581 | * @dev_priv: i915 private structure |
||
1582 | * @pipe: pipe PLL to enable |
||
1583 | * |
||
1584 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
||
1585 | * drives the transcoder clock. |
||
1586 | */ |
||
3031 | serge | 1587 | static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) |
2327 | Serge | 1588 | { |
3031 | serge | 1589 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1590 | struct intel_pch_pll *pll; |
||
2327 | Serge | 1591 | int reg; |
1592 | u32 val; |
||
1593 | |||
3031 | serge | 1594 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1595 | BUG_ON(dev_priv->info->gen < 5); |
||
1596 | pll = intel_crtc->pch_pll; |
||
1597 | if (pll == NULL) |
||
2342 | Serge | 1598 | return; |
1599 | |||
3031 | serge | 1600 | if (WARN_ON(pll->refcount == 0)) |
1601 | return; |
||
2327 | Serge | 1602 | |
3031 | serge | 1603 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", |
1604 | pll->pll_reg, pll->active, pll->on, |
||
1605 | intel_crtc->base.base.id); |
||
1606 | |||
2327 | Serge | 1607 | /* PCH refclock must be enabled first */ |
1608 | assert_pch_refclk_enabled(dev_priv); |
||
1609 | |||
3031 | serge | 1610 | if (pll->active++ && pll->on) { |
1611 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
||
1612 | return; |
||
1613 | } |
||
1614 | |||
1615 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); |
||
1616 | |||
1617 | reg = pll->pll_reg; |
||
2327 | Serge | 1618 | val = I915_READ(reg); |
1619 | val |= DPLL_VCO_ENABLE; |
||
1620 | I915_WRITE(reg, val); |
||
1621 | POSTING_READ(reg); |
||
1622 | udelay(200); |
||
3031 | serge | 1623 | |
1624 | pll->on = true; |
||
2327 | Serge | 1625 | } |
1626 | |||
3031 | serge | 1627 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
2327 | Serge | 1628 | { |
3031 | serge | 1629 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1630 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
||
2327 | Serge | 1631 | int reg; |
3031 | serge | 1632 | u32 val; |
2327 | Serge | 1633 | |
1634 | /* PCH only available on ILK+ */ |
||
1635 | BUG_ON(dev_priv->info->gen < 5); |
||
3031 | serge | 1636 | if (pll == NULL) |
1637 | return; |
||
2327 | Serge | 1638 | |
3031 | serge | 1639 | if (WARN_ON(pll->refcount == 0)) |
1640 | return; |
||
2327 | Serge | 1641 | |
3031 | serge | 1642 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1643 | pll->pll_reg, pll->active, pll->on, |
||
1644 | intel_crtc->base.base.id); |
||
2342 | Serge | 1645 | |
3031 | serge | 1646 | if (WARN_ON(pll->active == 0)) { |
1647 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
||
1648 | return; |
||
1649 | } |
||
2342 | Serge | 1650 | |
3031 | serge | 1651 | if (--pll->active) { |
1652 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
||
2342 | Serge | 1653 | return; |
3031 | serge | 1654 | } |
2342 | Serge | 1655 | |
3031 | serge | 1656 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); |
1657 | |||
1658 | /* Make sure transcoder isn't still depending on us */ |
||
1659 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); |
||
1660 | |||
1661 | reg = pll->pll_reg; |
||
2327 | Serge | 1662 | val = I915_READ(reg); |
1663 | val &= ~DPLL_VCO_ENABLE; |
||
1664 | I915_WRITE(reg, val); |
||
1665 | POSTING_READ(reg); |
||
1666 | udelay(200); |
||
3031 | serge | 1667 | |
1668 | pll->on = false; |
||
2327 | Serge | 1669 | } |
1670 | |||
1671 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
||
1672 | enum pipe pipe) |
||
1673 | { |
||
1674 | int reg; |
||
3031 | serge | 1675 | u32 val, pipeconf_val; |
1676 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
||
2327 | Serge | 1677 | |
1678 | /* PCH only available on ILK+ */ |
||
1679 | BUG_ON(dev_priv->info->gen < 5); |
||
1680 | |||
1681 | /* Make sure PCH DPLL is enabled */ |
||
3031 | serge | 1682 | assert_pch_pll_enabled(dev_priv, |
1683 | to_intel_crtc(crtc)->pch_pll, |
||
1684 | to_intel_crtc(crtc)); |
||
2327 | Serge | 1685 | |
1686 | /* FDI must be feeding us bits for PCH ports */ |
||
1687 | assert_fdi_tx_enabled(dev_priv, pipe); |
||
1688 | assert_fdi_rx_enabled(dev_priv, pipe); |
||
1689 | |||
3031 | serge | 1690 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1691 | DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n"); |
||
1692 | return; |
||
1693 | } |
||
2327 | Serge | 1694 | reg = TRANSCONF(pipe); |
1695 | val = I915_READ(reg); |
||
3031 | serge | 1696 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
2327 | Serge | 1697 | |
1698 | if (HAS_PCH_IBX(dev_priv->dev)) { |
||
1699 | /* |
||
1700 | * make the BPC in transcoder be consistent with |
||
1701 | * that in pipeconf reg. |
||
1702 | */ |
||
1703 | val &= ~PIPE_BPC_MASK; |
||
3031 | serge | 1704 | val |= pipeconf_val & PIPE_BPC_MASK; |
2327 | Serge | 1705 | } |
3031 | serge | 1706 | |
1707 | val &= ~TRANS_INTERLACE_MASK; |
||
1708 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
||
1709 | if (HAS_PCH_IBX(dev_priv->dev) && |
||
1710 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
||
1711 | val |= TRANS_LEGACY_INTERLACED_ILK; |
||
1712 | else |
||
1713 | val |= TRANS_INTERLACED; |
||
1714 | else |
||
1715 | val |= TRANS_PROGRESSIVE; |
||
1716 | |||
2327 | Serge | 1717 | I915_WRITE(reg, val | TRANS_ENABLE); |
1718 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
||
1719 | DRM_ERROR("failed to enable transcoder %d\n", pipe); |
||
1720 | } |
||
1721 | |||
1722 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, |
||
1723 | enum pipe pipe) |
||
1724 | { |
||
1725 | int reg; |
||
1726 | u32 val; |
||
1727 | |||
1728 | /* FDI relies on the transcoder */ |
||
1729 | assert_fdi_tx_disabled(dev_priv, pipe); |
||
1730 | assert_fdi_rx_disabled(dev_priv, pipe); |
||
1731 | |||
1732 | /* Ports must be off as well */ |
||
1733 | assert_pch_ports_disabled(dev_priv, pipe); |
||
1734 | |||
1735 | reg = TRANSCONF(pipe); |
||
1736 | val = I915_READ(reg); |
||
1737 | val &= ~TRANS_ENABLE; |
||
1738 | I915_WRITE(reg, val); |
||
1739 | /* wait for PCH transcoder off, transcoder state */ |
||
1740 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
||
2342 | Serge | 1741 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
2327 | Serge | 1742 | } |
1743 | |||
1744 | /** |
||
1745 | * intel_enable_pipe - enable a pipe, asserting requirements |
||
1746 | * @dev_priv: i915 private structure |
||
1747 | * @pipe: pipe to enable |
||
1748 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
||
1749 | * |
||
1750 | * Enable @pipe, making sure that various hardware specific requirements |
||
1751 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
||
1752 | * |
||
1753 | * @pipe should be %PIPE_A or %PIPE_B. |
||
1754 | * |
||
1755 | * Will wait until the pipe is actually running (i.e. first vblank) before |
||
1756 | * returning. |
||
1757 | */ |
||
1758 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
||
1759 | bool pch_port) |
||
1760 | { |
||
1761 | int reg; |
||
1762 | u32 val; |
||
1763 | |||
1764 | /* |
||
1765 | * A pipe without a PLL won't actually be able to drive bits from |
||
1766 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
||
1767 | * need the check. |
||
1768 | */ |
||
1769 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
||
1770 | assert_pll_enabled(dev_priv, pipe); |
||
1771 | else { |
||
1772 | if (pch_port) { |
||
1773 | /* if driving the PCH, we need FDI enabled */ |
||
1774 | assert_fdi_rx_pll_enabled(dev_priv, pipe); |
||
1775 | assert_fdi_tx_pll_enabled(dev_priv, pipe); |
||
1776 | } |
||
1777 | /* FIXME: assert CPU port conditions for SNB+ */ |
||
1778 | } |
||
1779 | |||
1780 | reg = PIPECONF(pipe); |
||
1781 | val = I915_READ(reg); |
||
1782 | if (val & PIPECONF_ENABLE) |
||
1783 | return; |
||
1784 | |||
1785 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
||
1786 | intel_wait_for_vblank(dev_priv->dev, pipe); |
||
1787 | } |
||
1788 | |||
1789 | /** |
||
1790 | * intel_disable_pipe - disable a pipe, asserting requirements |
||
1791 | * @dev_priv: i915 private structure |
||
1792 | * @pipe: pipe to disable |
||
1793 | * |
||
1794 | * Disable @pipe, making sure that various hardware specific requirements |
||
1795 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
||
1796 | * |
||
1797 | * @pipe should be %PIPE_A or %PIPE_B. |
||
1798 | * |
||
1799 | * Will wait until the pipe has shut down before returning. |
||
1800 | */ |
||
1801 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
||
1802 | enum pipe pipe) |
||
1803 | { |
||
1804 | int reg; |
||
1805 | u32 val; |
||
1806 | |||
3031 | serge | 1807 | /* |
2327 | Serge | 1808 | * Make sure planes won't keep trying to pump pixels to us, |
1809 | * or we might hang the display. |
||
1810 | */ |
||
1811 | assert_planes_disabled(dev_priv, pipe); |
||
1812 | |||
1813 | /* Don't disable pipe A or pipe A PLLs if needed */ |
||
1814 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
||
1815 | return; |
||
1816 | |||
1817 | reg = PIPECONF(pipe); |
||
1818 | val = I915_READ(reg); |
||
1819 | if ((val & PIPECONF_ENABLE) == 0) |
||
1820 | return; |
||
1821 | |||
1822 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
||
1823 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
||
1824 | } |
||
1825 | |||
1826 | /* |
||
1827 | * Plane regs are double buffered, going from enabled->disabled needs a |
||
1828 | * trigger in order to latch. The display address reg provides this. |
||
1829 | */ |
||
3031 | serge | 1830 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
2327 | Serge | 1831 | enum plane plane) |
1832 | { |
||
1833 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
||
1834 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
||
1835 | } |
||
1836 | |||
1837 | /** |
||
1838 | * intel_enable_plane - enable a display plane on a given pipe |
||
1839 | * @dev_priv: i915 private structure |
||
1840 | * @plane: plane to enable |
||
1841 | * @pipe: pipe being fed |
||
1842 | * |
||
1843 | * Enable @plane on @pipe, making sure that @pipe is running first. |
||
1844 | */ |
||
1845 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
||
1846 | enum plane plane, enum pipe pipe) |
||
1847 | { |
||
1848 | int reg; |
||
1849 | u32 val; |
||
1850 | |||
1851 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
||
1852 | assert_pipe_enabled(dev_priv, pipe); |
||
1853 | |||
1854 | reg = DSPCNTR(plane); |
||
1855 | val = I915_READ(reg); |
||
1856 | if (val & DISPLAY_PLANE_ENABLE) |
||
1857 | return; |
||
1858 | |||
1859 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
||
1860 | intel_flush_display_plane(dev_priv, plane); |
||
1861 | intel_wait_for_vblank(dev_priv->dev, pipe); |
||
1862 | } |
||
1863 | |||
1864 | /** |
||
1865 | * intel_disable_plane - disable a display plane |
||
1866 | * @dev_priv: i915 private structure |
||
1867 | * @plane: plane to disable |
||
1868 | * @pipe: pipe consuming the data |
||
1869 | * |
||
1870 | * Disable @plane; should be an independent operation. |
||
1871 | */ |
||
1872 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
||
1873 | enum plane plane, enum pipe pipe) |
||
1874 | { |
||
1875 | int reg; |
||
1876 | u32 val; |
||
1877 | |||
1878 | reg = DSPCNTR(plane); |
||
1879 | val = I915_READ(reg); |
||
1880 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
||
1881 | return; |
||
1882 | |||
1883 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
||
1884 | intel_flush_display_plane(dev_priv, plane); |
||
3031 | serge | 1885 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2327 | Serge | 1886 | } |
1887 | |||
2335 | Serge | 1888 | int |
1889 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
||
1890 | struct drm_i915_gem_object *obj, |
||
1891 | struct intel_ring_buffer *pipelined) |
||
1892 | { |
||
1893 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1894 | u32 alignment; |
||
1895 | int ret; |
||
2327 | Serge | 1896 | |
2335 | Serge | 1897 | switch (obj->tiling_mode) { |
1898 | case I915_TILING_NONE: |
||
1899 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
||
1900 | alignment = 128 * 1024; |
||
1901 | else if (INTEL_INFO(dev)->gen >= 4) |
||
1902 | alignment = 4 * 1024; |
||
1903 | else |
||
1904 | alignment = 64 * 1024; |
||
1905 | break; |
||
1906 | case I915_TILING_X: |
||
1907 | /* pin() will align the object as required by fence */ |
||
1908 | alignment = 0; |
||
1909 | break; |
||
1910 | case I915_TILING_Y: |
||
1911 | /* FIXME: Is this true? */ |
||
1912 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); |
||
1913 | return -EINVAL; |
||
1914 | default: |
||
1915 | BUG(); |
||
1916 | } |
||
2327 | Serge | 1917 | |
2335 | Serge | 1918 | dev_priv->mm.interruptible = false; |
1919 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
||
1920 | if (ret) |
||
1921 | goto err_interruptible; |
||
2327 | Serge | 1922 | |
2335 | Serge | 1923 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1924 | * fence, whereas 965+ only requires a fence if using |
||
1925 | * framebuffer compression. For simplicity, we always install |
||
1926 | * a fence as the cost is not that onerous. |
||
1927 | */ |
||
1928 | // if (obj->tiling_mode != I915_TILING_NONE) { |
||
1929 | // ret = i915_gem_object_get_fence(obj, pipelined); |
||
1930 | // if (ret) |
||
1931 | // goto err_unpin; |
||
1932 | // } |
||
2327 | Serge | 1933 | |
2335 | Serge | 1934 | dev_priv->mm.interruptible = true; |
1935 | return 0; |
||
2327 | Serge | 1936 | |
2335 | Serge | 1937 | err_unpin: |
2344 | Serge | 1938 | i915_gem_object_unpin(obj); |
2335 | Serge | 1939 | err_interruptible: |
1940 | dev_priv->mm.interruptible = true; |
||
1941 | return ret; |
||
1942 | } |
||
2327 | Serge | 1943 | |
3031 | serge | 1944 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1945 | { |
||
1946 | // i915_gem_object_unpin_fence(obj); |
||
1947 | // i915_gem_object_unpin(obj); |
||
1948 | } |
||
1949 | |||
1950 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
||
1951 | * is assumed to be a power-of-two. */ |
||
1952 | static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y, |
||
1953 | unsigned int bpp, |
||
1954 | unsigned int pitch) |
||
1955 | { |
||
1956 | int tile_rows, tiles; |
||
1957 | |||
1958 | tile_rows = *y / 8; |
||
1959 | *y %= 8; |
||
1960 | tiles = *x / (512/bpp); |
||
1961 | *x %= 512/bpp; |
||
1962 | |||
1963 | return tile_rows * pitch * 8 + tiles * 4096; |
||
1964 | } |
||
1965 | |||
2327 | Serge | 1966 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1967 | int x, int y) |
||
1968 | { |
||
1969 | struct drm_device *dev = crtc->dev; |
||
1970 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
1972 | struct intel_framebuffer *intel_fb; |
||
1973 | struct drm_i915_gem_object *obj; |
||
1974 | int plane = intel_crtc->plane; |
||
3031 | serge | 1975 | unsigned long linear_offset; |
2327 | Serge | 1976 | u32 dspcntr; |
1977 | u32 reg; |
||
1978 | |||
1979 | switch (plane) { |
||
1980 | case 0: |
||
1981 | case 1: |
||
1982 | break; |
||
1983 | default: |
||
1984 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
||
1985 | return -EINVAL; |
||
1986 | } |
||
1987 | |||
1988 | intel_fb = to_intel_framebuffer(fb); |
||
1989 | obj = intel_fb->obj; |
||
1990 | |||
1991 | reg = DSPCNTR(plane); |
||
1992 | dspcntr = I915_READ(reg); |
||
1993 | /* Mask out pixel format bits in case we change it */ |
||
1994 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
||
1995 | switch (fb->bits_per_pixel) { |
||
1996 | case 8: |
||
1997 | dspcntr |= DISPPLANE_8BPP; |
||
1998 | break; |
||
1999 | case 16: |
||
2000 | if (fb->depth == 15) |
||
2001 | dspcntr |= DISPPLANE_15_16BPP; |
||
2002 | else |
||
2003 | dspcntr |= DISPPLANE_16BPP; |
||
2004 | break; |
||
2005 | case 24: |
||
2006 | case 32: |
||
2007 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
||
2008 | break; |
||
2009 | default: |
||
2010 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
||
2011 | return -EINVAL; |
||
2012 | } |
||
2013 | if (INTEL_INFO(dev)->gen >= 4) { |
||
2014 | if (obj->tiling_mode != I915_TILING_NONE) |
||
2015 | dspcntr |= DISPPLANE_TILED; |
||
2016 | else |
||
2017 | dspcntr &= ~DISPPLANE_TILED; |
||
2018 | } |
||
2019 | |||
2020 | I915_WRITE(reg, dspcntr); |
||
2021 | |||
3031 | serge | 2022 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2327 | Serge | 2023 | |
3031 | serge | 2024 | if (INTEL_INFO(dev)->gen >= 4) { |
2025 | intel_crtc->dspaddr_offset = |
||
2026 | gen4_compute_dspaddr_offset_xtiled(&x, &y, |
||
2027 | fb->bits_per_pixel / 8, |
||
2028 | fb->pitches[0]); |
||
2029 | linear_offset -= intel_crtc->dspaddr_offset; |
||
2030 | } else { |
||
2031 | intel_crtc->dspaddr_offset = linear_offset; |
||
2032 | } |
||
2033 | |||
2034 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
||
2035 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); |
||
2342 | Serge | 2036 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2327 | Serge | 2037 | if (INTEL_INFO(dev)->gen >= 4) { |
3031 | serge | 2038 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2039 | obj->gtt_offset + intel_crtc->dspaddr_offset); |
||
2327 | Serge | 2040 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
3031 | serge | 2041 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2327 | Serge | 2042 | } else |
3031 | serge | 2043 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
2327 | Serge | 2044 | POSTING_READ(reg); |
2045 | |||
2046 | return 0; |
||
2047 | } |
||
2048 | |||
2049 | static int ironlake_update_plane(struct drm_crtc *crtc, |
||
2050 | struct drm_framebuffer *fb, int x, int y) |
||
2051 | { |
||
2052 | struct drm_device *dev = crtc->dev; |
||
2053 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2054 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2055 | struct intel_framebuffer *intel_fb; |
||
2056 | struct drm_i915_gem_object *obj; |
||
2057 | int plane = intel_crtc->plane; |
||
3031 | serge | 2058 | unsigned long linear_offset; |
2327 | Serge | 2059 | u32 dspcntr; |
2060 | u32 reg; |
||
2061 | |||
2062 | switch (plane) { |
||
2063 | case 0: |
||
2064 | case 1: |
||
2342 | Serge | 2065 | case 2: |
2327 | Serge | 2066 | break; |
2067 | default: |
||
2068 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
||
2069 | return -EINVAL; |
||
2070 | } |
||
2071 | |||
2072 | intel_fb = to_intel_framebuffer(fb); |
||
2073 | obj = intel_fb->obj; |
||
2074 | |||
2075 | reg = DSPCNTR(plane); |
||
2076 | dspcntr = I915_READ(reg); |
||
2077 | /* Mask out pixel format bits in case we change it */ |
||
2078 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
||
2079 | switch (fb->bits_per_pixel) { |
||
2080 | case 8: |
||
2081 | dspcntr |= DISPPLANE_8BPP; |
||
2082 | break; |
||
2083 | case 16: |
||
2084 | if (fb->depth != 16) |
||
2085 | return -EINVAL; |
||
2086 | |||
2087 | dspcntr |= DISPPLANE_16BPP; |
||
2088 | break; |
||
2089 | case 24: |
||
2090 | case 32: |
||
2091 | if (fb->depth == 24) |
||
2092 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
||
2093 | else if (fb->depth == 30) |
||
2094 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; |
||
2095 | else |
||
2096 | return -EINVAL; |
||
2097 | break; |
||
2098 | default: |
||
2099 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
||
2100 | return -EINVAL; |
||
2101 | } |
||
2102 | |||
2103 | // if (obj->tiling_mode != I915_TILING_NONE) |
||
2104 | // dspcntr |= DISPPLANE_TILED; |
||
2105 | // else |
||
2106 | dspcntr &= ~DISPPLANE_TILED; |
||
2107 | |||
2108 | /* must disable */ |
||
2109 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
||
2110 | |||
2111 | I915_WRITE(reg, dspcntr); |
||
2112 | |||
3031 | serge | 2113 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2114 | intel_crtc->dspaddr_offset = |
||
2115 | gen4_compute_dspaddr_offset_xtiled(&x, &y, |
||
2116 | fb->bits_per_pixel / 8, |
||
2117 | fb->pitches[0]); |
||
2118 | linear_offset -= intel_crtc->dspaddr_offset; |
||
2327 | Serge | 2119 | |
3031 | serge | 2120 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2121 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); |
||
2342 | Serge | 2122 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
3031 | serge | 2123 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2124 | obj->gtt_offset + intel_crtc->dspaddr_offset); |
||
2330 | Serge | 2125 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
3031 | serge | 2126 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2330 | Serge | 2127 | POSTING_READ(reg); |
2327 | Serge | 2128 | |
2129 | return 0; |
||
2130 | } |
||
2131 | |||
2132 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
||
2133 | static int |
||
2134 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
||
2135 | int x, int y, enum mode_set_atomic state) |
||
2136 | { |
||
2137 | struct drm_device *dev = crtc->dev; |
||
2138 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 2139 | |
2140 | if (dev_priv->display.disable_fbc) |
||
2141 | dev_priv->display.disable_fbc(dev); |
||
2142 | intel_increase_pllclock(crtc); |
||
2143 | |||
2144 | return dev_priv->display.update_plane(crtc, fb, x, y); |
||
2145 | } |
||
2146 | |||
2147 | #if 0 |
||
2148 | static int |
||
2149 | intel_finish_fb(struct drm_framebuffer *old_fb) |
||
2150 | { |
||
2151 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
||
2152 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
2153 | bool was_interruptible = dev_priv->mm.interruptible; |
||
2327 | Serge | 2154 | int ret; |
2155 | |||
3031 | serge | 2156 | wait_event(dev_priv->pending_flip_queue, |
2157 | atomic_read(&dev_priv->mm.wedged) || |
||
2158 | atomic_read(&obj->pending_flip) == 0); |
||
2327 | Serge | 2159 | |
3031 | serge | 2160 | /* Big Hammer, we also need to ensure that any pending |
2161 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
||
2162 | * current scanout is retired before unpinning the old |
||
2163 | * framebuffer. |
||
2164 | * |
||
2165 | * This should only fail upon a hung GPU, in which case we |
||
2166 | * can safely continue. |
||
2167 | */ |
||
2168 | dev_priv->mm.interruptible = false; |
||
2169 | ret = i915_gem_object_finish_gpu(obj); |
||
2170 | dev_priv->mm.interruptible = was_interruptible; |
||
2327 | Serge | 2171 | |
3031 | serge | 2172 | return ret; |
2327 | Serge | 2173 | } |
3031 | serge | 2174 | #endif |
2327 | Serge | 2175 | |
2176 | static int |
||
2177 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
||
3031 | serge | 2178 | struct drm_framebuffer *fb) |
2327 | Serge | 2179 | { |
2180 | struct drm_device *dev = crtc->dev; |
||
3031 | serge | 2181 | struct drm_i915_private *dev_priv = dev->dev_private; |
2327 | Serge | 2182 | struct drm_i915_master_private *master_priv; |
2183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 2184 | struct drm_framebuffer *old_fb; |
2342 | Serge | 2185 | int ret; |
2327 | Serge | 2186 | |
2187 | /* no fb bound */ |
||
3031 | serge | 2188 | if (!fb) { |
2327 | Serge | 2189 | DRM_ERROR("No FB bound\n"); |
2190 | return 0; |
||
2191 | } |
||
2192 | |||
3031 | serge | 2193 | if(intel_crtc->plane > dev_priv->num_pipe) { |
2194 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", |
||
2195 | intel_crtc->plane, |
||
2196 | dev_priv->num_pipe); |
||
2327 | Serge | 2197 | return -EINVAL; |
2198 | } |
||
2199 | |||
2200 | mutex_lock(&dev->struct_mutex); |
||
3031 | serge | 2201 | // ret = intel_pin_and_fence_fb_obj(dev, |
2202 | // to_intel_framebuffer(fb)->obj, |
||
2203 | // NULL); |
||
2204 | // if (ret != 0) { |
||
2205 | // mutex_unlock(&dev->struct_mutex); |
||
2206 | // DRM_ERROR("pin & fence failed\n"); |
||
2207 | // return ret; |
||
2208 | // } |
||
2327 | Serge | 2209 | |
3031 | serge | 2210 | // if (crtc->fb) |
2211 | // intel_finish_fb(crtc->fb); |
||
2212 | |||
2213 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
||
2327 | Serge | 2214 | if (ret) { |
3031 | serge | 2215 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2327 | Serge | 2216 | mutex_unlock(&dev->struct_mutex); |
2217 | DRM_ERROR("failed to update base address\n"); |
||
2218 | return ret; |
||
2219 | } |
||
2220 | |||
3031 | serge | 2221 | old_fb = crtc->fb; |
2222 | crtc->fb = fb; |
||
2223 | crtc->x = x; |
||
2224 | crtc->y = y; |
||
2225 | |||
2226 | if (old_fb) { |
||
2227 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
2228 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
||
2229 | } |
||
2230 | |||
2231 | intel_update_fbc(dev); |
||
2336 | Serge | 2232 | mutex_unlock(&dev->struct_mutex); |
2327 | Serge | 2233 | |
2336 | Serge | 2234 | return 0; |
2327 | Serge | 2235 | } |
2236 | |||
2237 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
||
2238 | { |
||
2239 | struct drm_device *dev = crtc->dev; |
||
2240 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2241 | u32 dpa_ctl; |
||
2242 | |||
2243 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
||
2244 | dpa_ctl = I915_READ(DP_A); |
||
2245 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
||
2246 | |||
2247 | if (clock < 200000) { |
||
2248 | u32 temp; |
||
2249 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
||
2250 | /* workaround for 160Mhz: |
||
2251 | 1) program 0x4600c bits 15:0 = 0x8124 |
||
2252 | 2) program 0x46010 bit 0 = 1 |
||
2253 | 3) program 0x46034 bit 24 = 1 |
||
2254 | 4) program 0x64000 bit 14 = 1 |
||
2255 | */ |
||
2256 | temp = I915_READ(0x4600c); |
||
2257 | temp &= 0xffff0000; |
||
2258 | I915_WRITE(0x4600c, temp | 0x8124); |
||
2259 | |||
2260 | temp = I915_READ(0x46010); |
||
2261 | I915_WRITE(0x46010, temp | 1); |
||
2262 | |||
2263 | temp = I915_READ(0x46034); |
||
2264 | I915_WRITE(0x46034, temp | (1 << 24)); |
||
2265 | } else { |
||
2266 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
||
2267 | } |
||
2268 | I915_WRITE(DP_A, dpa_ctl); |
||
2269 | |||
2270 | POSTING_READ(DP_A); |
||
2271 | udelay(500); |
||
2272 | } |
||
2273 | |||
2274 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
||
2275 | { |
||
2276 | struct drm_device *dev = crtc->dev; |
||
2277 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2279 | int pipe = intel_crtc->pipe; |
||
2280 | u32 reg, temp; |
||
2281 | |||
2282 | /* enable normal train */ |
||
2283 | reg = FDI_TX_CTL(pipe); |
||
2284 | temp = I915_READ(reg); |
||
2285 | if (IS_IVYBRIDGE(dev)) { |
||
2286 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
||
2287 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
||
2288 | } else { |
||
2289 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2290 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
||
2291 | } |
||
2292 | I915_WRITE(reg, temp); |
||
2293 | |||
2294 | reg = FDI_RX_CTL(pipe); |
||
2295 | temp = I915_READ(reg); |
||
2296 | if (HAS_PCH_CPT(dev)) { |
||
2297 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2298 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
||
2299 | } else { |
||
2300 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2301 | temp |= FDI_LINK_TRAIN_NONE; |
||
2302 | } |
||
2303 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
||
2304 | |||
2305 | /* wait one idle pattern time */ |
||
2306 | POSTING_READ(reg); |
||
2307 | udelay(1000); |
||
2308 | |||
2309 | /* IVB wants error correction enabled */ |
||
2310 | if (IS_IVYBRIDGE(dev)) |
||
2311 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
||
2312 | FDI_FE_ERRC_ENABLE); |
||
2313 | } |
||
2314 | |||
2315 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
||
2316 | { |
||
2317 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2318 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
||
2319 | |||
2320 | flags |= FDI_PHASE_SYNC_OVR(pipe); |
||
2321 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ |
||
2322 | flags |= FDI_PHASE_SYNC_EN(pipe); |
||
2323 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ |
||
2324 | POSTING_READ(SOUTH_CHICKEN1); |
||
2325 | } |
||
2326 | |||
2327 | /* The FDI link training functions for ILK/Ibexpeak. */ |
||
2328 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
||
2329 | { |
||
2330 | struct drm_device *dev = crtc->dev; |
||
2331 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2333 | int pipe = intel_crtc->pipe; |
||
2334 | int plane = intel_crtc->plane; |
||
2335 | u32 reg, temp, tries; |
||
2336 | |||
2337 | /* FDI needs bits from pipe & plane first */ |
||
2338 | assert_pipe_enabled(dev_priv, pipe); |
||
2339 | assert_plane_enabled(dev_priv, plane); |
||
2340 | |||
2341 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
||
2342 | for train result */ |
||
2343 | reg = FDI_RX_IMR(pipe); |
||
2344 | temp = I915_READ(reg); |
||
2345 | temp &= ~FDI_RX_SYMBOL_LOCK; |
||
2346 | temp &= ~FDI_RX_BIT_LOCK; |
||
2347 | I915_WRITE(reg, temp); |
||
2348 | I915_READ(reg); |
||
2349 | udelay(150); |
||
2350 | |||
2351 | /* enable CPU FDI TX and PCH FDI RX */ |
||
2352 | reg = FDI_TX_CTL(pipe); |
||
2353 | temp = I915_READ(reg); |
||
2354 | temp &= ~(7 << 19); |
||
2355 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
||
2356 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2357 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2358 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
||
2359 | |||
2360 | reg = FDI_RX_CTL(pipe); |
||
2361 | temp = I915_READ(reg); |
||
2362 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2363 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2364 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
||
2365 | |||
2366 | POSTING_READ(reg); |
||
2367 | udelay(150); |
||
2368 | |||
2369 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
||
2370 | if (HAS_PCH_IBX(dev)) { |
||
2371 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
||
2372 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
||
2373 | FDI_RX_PHASE_SYNC_POINTER_EN); |
||
2374 | } |
||
2375 | |||
2376 | reg = FDI_RX_IIR(pipe); |
||
2377 | for (tries = 0; tries < 5; tries++) { |
||
2378 | temp = I915_READ(reg); |
||
2379 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2380 | |||
2381 | if ((temp & FDI_RX_BIT_LOCK)) { |
||
2382 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
||
2383 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
||
2384 | break; |
||
2385 | } |
||
2386 | } |
||
2387 | if (tries == 5) |
||
2388 | DRM_ERROR("FDI train 1 fail!\n"); |
||
2389 | |||
2390 | /* Train 2 */ |
||
2391 | reg = FDI_TX_CTL(pipe); |
||
2392 | temp = I915_READ(reg); |
||
2393 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2394 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
||
2395 | I915_WRITE(reg, temp); |
||
2396 | |||
2397 | reg = FDI_RX_CTL(pipe); |
||
2398 | temp = I915_READ(reg); |
||
2399 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2400 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
||
2401 | I915_WRITE(reg, temp); |
||
2402 | |||
2403 | POSTING_READ(reg); |
||
2404 | udelay(150); |
||
2405 | |||
2406 | reg = FDI_RX_IIR(pipe); |
||
2407 | for (tries = 0; tries < 5; tries++) { |
||
2408 | temp = I915_READ(reg); |
||
2409 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2410 | |||
2411 | if (temp & FDI_RX_SYMBOL_LOCK) { |
||
2412 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
||
2413 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
||
2414 | break; |
||
2415 | } |
||
2416 | } |
||
2417 | if (tries == 5) |
||
2418 | DRM_ERROR("FDI train 2 fail!\n"); |
||
2419 | |||
2420 | DRM_DEBUG_KMS("FDI train done\n"); |
||
2421 | |||
2422 | } |
||
2423 | |||
2342 | Serge | 2424 | static const int snb_b_fdi_train_param[] = { |
2327 | Serge | 2425 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2426 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
||
2427 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
||
2428 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
||
2429 | }; |
||
2430 | |||
2431 | /* The FDI link training functions for SNB/Cougarpoint. */ |
||
2432 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
||
2433 | { |
||
2434 | struct drm_device *dev = crtc->dev; |
||
2435 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2436 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2437 | int pipe = intel_crtc->pipe; |
||
3031 | serge | 2438 | u32 reg, temp, i, retry; |
2327 | Serge | 2439 | |
2440 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
||
2441 | for train result */ |
||
2442 | reg = FDI_RX_IMR(pipe); |
||
2443 | temp = I915_READ(reg); |
||
2444 | temp &= ~FDI_RX_SYMBOL_LOCK; |
||
2445 | temp &= ~FDI_RX_BIT_LOCK; |
||
2446 | I915_WRITE(reg, temp); |
||
2447 | |||
2448 | POSTING_READ(reg); |
||
2449 | udelay(150); |
||
2450 | |||
2451 | /* enable CPU FDI TX and PCH FDI RX */ |
||
2452 | reg = FDI_TX_CTL(pipe); |
||
2453 | temp = I915_READ(reg); |
||
2454 | temp &= ~(7 << 19); |
||
2455 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
||
2456 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2457 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2458 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2459 | /* SNB-B */ |
||
2460 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
||
2461 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
||
2462 | |||
2463 | reg = FDI_RX_CTL(pipe); |
||
2464 | temp = I915_READ(reg); |
||
2465 | if (HAS_PCH_CPT(dev)) { |
||
2466 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2467 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
||
2468 | } else { |
||
2469 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2470 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2471 | } |
||
2472 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
||
2473 | |||
2474 | POSTING_READ(reg); |
||
2475 | udelay(150); |
||
2476 | |||
2477 | if (HAS_PCH_CPT(dev)) |
||
2478 | cpt_phase_pointer_enable(dev, pipe); |
||
2479 | |||
2342 | Serge | 2480 | for (i = 0; i < 4; i++) { |
2327 | Serge | 2481 | reg = FDI_TX_CTL(pipe); |
2482 | temp = I915_READ(reg); |
||
2483 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2484 | temp |= snb_b_fdi_train_param[i]; |
||
2485 | I915_WRITE(reg, temp); |
||
2486 | |||
2487 | POSTING_READ(reg); |
||
2488 | udelay(500); |
||
2489 | |||
3031 | serge | 2490 | for (retry = 0; retry < 5; retry++) { |
2327 | Serge | 2491 | reg = FDI_RX_IIR(pipe); |
2492 | temp = I915_READ(reg); |
||
2493 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2494 | if (temp & FDI_RX_BIT_LOCK) { |
||
2495 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
||
2496 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
||
2497 | break; |
||
2498 | } |
||
3031 | serge | 2499 | udelay(50); |
2500 | } |
||
2501 | if (retry < 5) |
||
2502 | break; |
||
2327 | Serge | 2503 | } |
2504 | if (i == 4) |
||
2505 | DRM_ERROR("FDI train 1 fail!\n"); |
||
2506 | |||
2507 | /* Train 2 */ |
||
2508 | reg = FDI_TX_CTL(pipe); |
||
2509 | temp = I915_READ(reg); |
||
2510 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2511 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
||
2512 | if (IS_GEN6(dev)) { |
||
2513 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2514 | /* SNB-B */ |
||
2515 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
||
2516 | } |
||
2517 | I915_WRITE(reg, temp); |
||
2518 | |||
2519 | reg = FDI_RX_CTL(pipe); |
||
2520 | temp = I915_READ(reg); |
||
2521 | if (HAS_PCH_CPT(dev)) { |
||
2522 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2523 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
||
2524 | } else { |
||
2525 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2526 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
||
2527 | } |
||
2528 | I915_WRITE(reg, temp); |
||
2529 | |||
2530 | POSTING_READ(reg); |
||
2531 | udelay(150); |
||
2532 | |||
2342 | Serge | 2533 | for (i = 0; i < 4; i++) { |
2327 | Serge | 2534 | reg = FDI_TX_CTL(pipe); |
2535 | temp = I915_READ(reg); |
||
2536 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2537 | temp |= snb_b_fdi_train_param[i]; |
||
2538 | I915_WRITE(reg, temp); |
||
2539 | |||
2540 | POSTING_READ(reg); |
||
2541 | udelay(500); |
||
2542 | |||
3031 | serge | 2543 | for (retry = 0; retry < 5; retry++) { |
2327 | Serge | 2544 | reg = FDI_RX_IIR(pipe); |
2545 | temp = I915_READ(reg); |
||
2546 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2547 | if (temp & FDI_RX_SYMBOL_LOCK) { |
||
2548 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
||
2549 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
||
2550 | break; |
||
2551 | } |
||
3031 | serge | 2552 | udelay(50); |
2553 | } |
||
2554 | if (retry < 5) |
||
2555 | break; |
||
2327 | Serge | 2556 | } |
2557 | if (i == 4) |
||
2558 | DRM_ERROR("FDI train 2 fail!\n"); |
||
2559 | |||
2560 | DRM_DEBUG_KMS("FDI train done.\n"); |
||
2561 | } |
||
2562 | |||
2563 | /* Manual link training for Ivy Bridge A0 parts */ |
||
2564 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
||
2565 | { |
||
2566 | struct drm_device *dev = crtc->dev; |
||
2567 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2569 | int pipe = intel_crtc->pipe; |
||
2570 | u32 reg, temp, i; |
||
2571 | |||
2572 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
||
2573 | for train result */ |
||
2574 | reg = FDI_RX_IMR(pipe); |
||
2575 | temp = I915_READ(reg); |
||
2576 | temp &= ~FDI_RX_SYMBOL_LOCK; |
||
2577 | temp &= ~FDI_RX_BIT_LOCK; |
||
2578 | I915_WRITE(reg, temp); |
||
2579 | |||
2580 | POSTING_READ(reg); |
||
2581 | udelay(150); |
||
2582 | |||
2583 | /* enable CPU FDI TX and PCH FDI RX */ |
||
2584 | reg = FDI_TX_CTL(pipe); |
||
2585 | temp = I915_READ(reg); |
||
2586 | temp &= ~(7 << 19); |
||
2587 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
||
2588 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
||
2589 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
||
2590 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2591 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
||
2342 | Serge | 2592 | temp |= FDI_COMPOSITE_SYNC; |
2327 | Serge | 2593 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2594 | |||
2595 | reg = FDI_RX_CTL(pipe); |
||
2596 | temp = I915_READ(reg); |
||
2597 | temp &= ~FDI_LINK_TRAIN_AUTO; |
||
2598 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2599 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
||
2342 | Serge | 2600 | temp |= FDI_COMPOSITE_SYNC; |
2327 | Serge | 2601 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2602 | |||
2603 | POSTING_READ(reg); |
||
2604 | udelay(150); |
||
2605 | |||
2606 | if (HAS_PCH_CPT(dev)) |
||
2607 | cpt_phase_pointer_enable(dev, pipe); |
||
2608 | |||
2342 | Serge | 2609 | for (i = 0; i < 4; i++) { |
2327 | Serge | 2610 | reg = FDI_TX_CTL(pipe); |
2611 | temp = I915_READ(reg); |
||
2612 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2613 | temp |= snb_b_fdi_train_param[i]; |
||
2614 | I915_WRITE(reg, temp); |
||
2615 | |||
2616 | POSTING_READ(reg); |
||
2617 | udelay(500); |
||
2618 | |||
2619 | reg = FDI_RX_IIR(pipe); |
||
2620 | temp = I915_READ(reg); |
||
2621 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2622 | |||
2623 | if (temp & FDI_RX_BIT_LOCK || |
||
2624 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
||
2625 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
||
2626 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
||
2627 | break; |
||
2628 | } |
||
2629 | } |
||
2630 | if (i == 4) |
||
2631 | DRM_ERROR("FDI train 1 fail!\n"); |
||
2632 | |||
2633 | /* Train 2 */ |
||
2634 | reg = FDI_TX_CTL(pipe); |
||
2635 | temp = I915_READ(reg); |
||
2636 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
||
2637 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
||
2638 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2639 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
||
2640 | I915_WRITE(reg, temp); |
||
2641 | |||
2642 | reg = FDI_RX_CTL(pipe); |
||
2643 | temp = I915_READ(reg); |
||
2644 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2645 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
||
2646 | I915_WRITE(reg, temp); |
||
2647 | |||
2648 | POSTING_READ(reg); |
||
2649 | udelay(150); |
||
2650 | |||
2342 | Serge | 2651 | for (i = 0; i < 4; i++) { |
2327 | Serge | 2652 | reg = FDI_TX_CTL(pipe); |
2653 | temp = I915_READ(reg); |
||
2654 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
||
2655 | temp |= snb_b_fdi_train_param[i]; |
||
2656 | I915_WRITE(reg, temp); |
||
2657 | |||
2658 | POSTING_READ(reg); |
||
2659 | udelay(500); |
||
2660 | |||
2661 | reg = FDI_RX_IIR(pipe); |
||
2662 | temp = I915_READ(reg); |
||
2663 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
||
2664 | |||
2665 | if (temp & FDI_RX_SYMBOL_LOCK) { |
||
2666 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
||
2667 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
||
2668 | break; |
||
2669 | } |
||
2670 | } |
||
2671 | if (i == 4) |
||
2672 | DRM_ERROR("FDI train 2 fail!\n"); |
||
2673 | |||
2674 | DRM_DEBUG_KMS("FDI train done.\n"); |
||
2675 | } |
||
2676 | |||
3031 | serge | 2677 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2327 | Serge | 2678 | { |
3031 | serge | 2679 | struct drm_device *dev = intel_crtc->base.dev; |
2327 | Serge | 2680 | struct drm_i915_private *dev_priv = dev->dev_private; |
2681 | int pipe = intel_crtc->pipe; |
||
2682 | u32 reg, temp; |
||
2683 | |||
2684 | /* Write the TU size bits so error detection works */ |
||
2685 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
||
2686 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
||
2687 | |||
2688 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
||
2689 | reg = FDI_RX_CTL(pipe); |
||
2690 | temp = I915_READ(reg); |
||
2691 | temp &= ~((0x7 << 19) | (0x7 << 16)); |
||
2692 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
||
2693 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
||
2694 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
||
2695 | |||
2696 | POSTING_READ(reg); |
||
2697 | udelay(200); |
||
2698 | |||
2699 | /* Switch from Rawclk to PCDclk */ |
||
2700 | temp = I915_READ(reg); |
||
2701 | I915_WRITE(reg, temp | FDI_PCDCLK); |
||
2702 | |||
2703 | POSTING_READ(reg); |
||
2704 | udelay(200); |
||
2705 | |||
3031 | serge | 2706 | /* On Haswell, the PLL configuration for ports and pipes is handled |
2707 | * separately, as part of DDI setup */ |
||
2708 | if (!IS_HASWELL(dev)) { |
||
2327 | Serge | 2709 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2710 | reg = FDI_TX_CTL(pipe); |
||
2711 | temp = I915_READ(reg); |
||
2712 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
||
2713 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
||
2714 | |||
2715 | POSTING_READ(reg); |
||
2716 | udelay(100); |
||
2717 | } |
||
3031 | serge | 2718 | } |
2327 | Serge | 2719 | } |
2720 | |||
3031 | serge | 2721 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2722 | { |
||
2723 | struct drm_device *dev = intel_crtc->base.dev; |
||
2724 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2725 | int pipe = intel_crtc->pipe; |
||
2726 | u32 reg, temp; |
||
2727 | |||
2728 | /* Switch from PCDclk to Rawclk */ |
||
2729 | reg = FDI_RX_CTL(pipe); |
||
2730 | temp = I915_READ(reg); |
||
2731 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
||
2732 | |||
2733 | /* Disable CPU FDI TX PLL */ |
||
2734 | reg = FDI_TX_CTL(pipe); |
||
2735 | temp = I915_READ(reg); |
||
2736 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
||
2737 | |||
2738 | POSTING_READ(reg); |
||
2739 | udelay(100); |
||
2740 | |||
2741 | reg = FDI_RX_CTL(pipe); |
||
2742 | temp = I915_READ(reg); |
||
2743 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
||
2744 | |||
2745 | /* Wait for the clocks to turn off. */ |
||
2746 | POSTING_READ(reg); |
||
2747 | udelay(100); |
||
2748 | } |
||
2749 | |||
2327 | Serge | 2750 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2751 | { |
||
2752 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2753 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
||
2754 | |||
2755 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); |
||
2756 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ |
||
2757 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); |
||
2758 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ |
||
2759 | POSTING_READ(SOUTH_CHICKEN1); |
||
2760 | } |
||
2761 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
||
2762 | { |
||
2763 | struct drm_device *dev = crtc->dev; |
||
2764 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2766 | int pipe = intel_crtc->pipe; |
||
2767 | u32 reg, temp; |
||
2768 | |||
2769 | /* disable CPU FDI tx and PCH FDI rx */ |
||
2770 | reg = FDI_TX_CTL(pipe); |
||
2771 | temp = I915_READ(reg); |
||
2772 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
||
2773 | POSTING_READ(reg); |
||
2774 | |||
2775 | reg = FDI_RX_CTL(pipe); |
||
2776 | temp = I915_READ(reg); |
||
2777 | temp &= ~(0x7 << 16); |
||
2778 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
||
2779 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
||
2780 | |||
2781 | POSTING_READ(reg); |
||
2782 | udelay(100); |
||
2783 | |||
2784 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
||
2785 | if (HAS_PCH_IBX(dev)) { |
||
2786 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
||
2787 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
||
2788 | I915_READ(FDI_RX_CHICKEN(pipe) & |
||
2789 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
||
2790 | } else if (HAS_PCH_CPT(dev)) { |
||
2791 | cpt_phase_pointer_disable(dev, pipe); |
||
2792 | } |
||
2793 | |||
2794 | /* still set train pattern 1 */ |
||
2795 | reg = FDI_TX_CTL(pipe); |
||
2796 | temp = I915_READ(reg); |
||
2797 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2798 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2799 | I915_WRITE(reg, temp); |
||
2800 | |||
2801 | reg = FDI_RX_CTL(pipe); |
||
2802 | temp = I915_READ(reg); |
||
2803 | if (HAS_PCH_CPT(dev)) { |
||
2804 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
||
2805 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
||
2806 | } else { |
||
2807 | temp &= ~FDI_LINK_TRAIN_NONE; |
||
2808 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
||
2809 | } |
||
2810 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
||
2811 | temp &= ~(0x07 << 16); |
||
2812 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
||
2813 | I915_WRITE(reg, temp); |
||
2814 | |||
2815 | POSTING_READ(reg); |
||
2816 | udelay(100); |
||
2817 | } |
||
2818 | |||
3031 | serge | 2819 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2327 | Serge | 2820 | { |
3031 | serge | 2821 | struct drm_device *dev = crtc->dev; |
2327 | Serge | 2822 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 2823 | unsigned long flags; |
2824 | bool pending; |
||
2327 | Serge | 2825 | |
3031 | serge | 2826 | if (atomic_read(&dev_priv->mm.wedged)) |
2827 | return false; |
||
2327 | Serge | 2828 | |
3031 | serge | 2829 | spin_lock_irqsave(&dev->event_lock, flags); |
2830 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
||
2831 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
2832 | |||
2833 | return pending; |
||
2327 | Serge | 2834 | } |
2835 | |||
3031 | serge | 2836 | #if 0 |
2327 | Serge | 2837 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2838 | { |
||
3031 | serge | 2839 | struct drm_device *dev = crtc->dev; |
2840 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 2841 | |
2842 | if (crtc->fb == NULL) |
||
2843 | return; |
||
2844 | |||
2360 | Serge | 2845 | wait_event(dev_priv->pending_flip_queue, |
3031 | serge | 2846 | !intel_crtc_has_pending_flip(crtc)); |
2847 | |||
2848 | mutex_lock(&dev->struct_mutex); |
||
2849 | intel_finish_fb(crtc->fb); |
||
2850 | mutex_unlock(&dev->struct_mutex); |
||
2327 | Serge | 2851 | } |
3031 | serge | 2852 | #endif |
2327 | Serge | 2853 | |
2854 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
||
2855 | { |
||
2856 | struct drm_device *dev = crtc->dev; |
||
3031 | serge | 2857 | struct intel_encoder *intel_encoder; |
2327 | Serge | 2858 | |
2859 | /* |
||
2860 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that |
||
2861 | * must be driven by its own crtc; no sharing is possible. |
||
2862 | */ |
||
3031 | serge | 2863 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
2327 | Serge | 2864 | |
3031 | serge | 2865 | /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell |
2866 | * CPU handles all others */ |
||
2867 | if (IS_HASWELL(dev)) { |
||
2868 | /* It is still unclear how this will work on PPT, so throw up a warning */ |
||
2869 | WARN_ON(!HAS_PCH_LPT(dev)); |
||
2870 | |||
2871 | if (intel_encoder->type == INTEL_OUTPUT_ANALOG) { |
||
2872 | DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n"); |
||
2873 | return true; |
||
2874 | } else { |
||
2875 | DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n", |
||
2876 | intel_encoder->type); |
||
2877 | return false; |
||
2878 | } |
||
2879 | } |
||
2880 | |||
2881 | switch (intel_encoder->type) { |
||
2327 | Serge | 2882 | case INTEL_OUTPUT_EDP: |
3031 | serge | 2883 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
2327 | Serge | 2884 | return false; |
2885 | continue; |
||
2886 | } |
||
2887 | } |
||
2888 | |||
2889 | return true; |
||
2890 | } |
||
2891 | |||
3031 | serge | 2892 | /* Program iCLKIP clock to the desired frequency */ |
2893 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
||
2894 | { |
||
2895 | struct drm_device *dev = crtc->dev; |
||
2896 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2897 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
||
2898 | u32 temp; |
||
2899 | |||
2900 | /* It is necessary to ungate the pixclk gate prior to programming |
||
2901 | * the divisors, and gate it back when it is done. |
||
2902 | */ |
||
2903 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
||
2904 | |||
2905 | /* Disable SSCCTL */ |
||
2906 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
||
2907 | intel_sbi_read(dev_priv, SBI_SSCCTL6) | |
||
2908 | SBI_SSCCTL_DISABLE); |
||
2909 | |||
2910 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
||
2911 | if (crtc->mode.clock == 20000) { |
||
2912 | auxdiv = 1; |
||
2913 | divsel = 0x41; |
||
2914 | phaseinc = 0x20; |
||
2915 | } else { |
||
2916 | /* The iCLK virtual clock root frequency is in MHz, |
||
2917 | * but the crtc->mode.clock in in KHz. To get the divisors, |
||
2918 | * it is necessary to divide one by another, so we |
||
2919 | * convert the virtual clock precision to KHz here for higher |
||
2920 | * precision. |
||
2921 | */ |
||
2922 | u32 iclk_virtual_root_freq = 172800 * 1000; |
||
2923 | u32 iclk_pi_range = 64; |
||
2924 | u32 desired_divisor, msb_divisor_value, pi_value; |
||
2925 | |||
2926 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
||
2927 | msb_divisor_value = desired_divisor / iclk_pi_range; |
||
2928 | pi_value = desired_divisor % iclk_pi_range; |
||
2929 | |||
2930 | auxdiv = 0; |
||
2931 | divsel = msb_divisor_value - 2; |
||
2932 | phaseinc = pi_value; |
||
2933 | } |
||
2934 | |||
2935 | /* This should not happen with any sane values */ |
||
2936 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
||
2937 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
||
2938 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
||
2939 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
||
2940 | |||
2941 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
||
2942 | crtc->mode.clock, |
||
2943 | auxdiv, |
||
2944 | divsel, |
||
2945 | phasedir, |
||
2946 | phaseinc); |
||
2947 | |||
2948 | /* Program SSCDIVINTPHASE6 */ |
||
2949 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6); |
||
2950 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
||
2951 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
||
2952 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
||
2953 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
||
2954 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
||
2955 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
||
2956 | |||
2957 | intel_sbi_write(dev_priv, |
||
2958 | SBI_SSCDIVINTPHASE6, |
||
2959 | temp); |
||
2960 | |||
2961 | /* Program SSCAUXDIV */ |
||
2962 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6); |
||
2963 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
||
2964 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
||
2965 | intel_sbi_write(dev_priv, |
||
2966 | SBI_SSCAUXDIV6, |
||
2967 | temp); |
||
2968 | |||
2969 | |||
2970 | /* Enable modulator and associated divider */ |
||
2971 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6); |
||
2972 | temp &= ~SBI_SSCCTL_DISABLE; |
||
2973 | intel_sbi_write(dev_priv, |
||
2974 | SBI_SSCCTL6, |
||
2975 | temp); |
||
2976 | |||
2977 | /* Wait for initialization time */ |
||
2978 | udelay(24); |
||
2979 | |||
2980 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
||
2981 | } |
||
2982 | |||
2327 | Serge | 2983 | /* |
2984 | * Enable PCH resources required for PCH ports: |
||
2985 | * - PCH PLLs |
||
2986 | * - FDI training & RX/TX |
||
2987 | * - update transcoder timings |
||
2988 | * - DP transcoding bits |
||
2989 | * - transcoder |
||
2990 | */ |
||
2991 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
||
2992 | { |
||
2993 | struct drm_device *dev = crtc->dev; |
||
2994 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2995 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2996 | int pipe = intel_crtc->pipe; |
||
3031 | serge | 2997 | u32 reg, temp; |
2327 | Serge | 2998 | |
3031 | serge | 2999 | assert_transcoder_disabled(dev_priv, pipe); |
3000 | |||
2327 | Serge | 3001 | /* For PCH output, training FDI link */ |
3002 | dev_priv->display.fdi_link_train(crtc); |
||
3003 | |||
3031 | serge | 3004 | intel_enable_pch_pll(intel_crtc); |
2327 | Serge | 3005 | |
3031 | serge | 3006 | if (HAS_PCH_LPT(dev)) { |
3007 | DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); |
||
3008 | lpt_program_iclkip(crtc); |
||
3009 | } else if (HAS_PCH_CPT(dev)) { |
||
3010 | u32 sel; |
||
2342 | Serge | 3011 | |
2327 | Serge | 3012 | temp = I915_READ(PCH_DPLL_SEL); |
3031 | serge | 3013 | switch (pipe) { |
3014 | default: |
||
3015 | case 0: |
||
3016 | temp |= TRANSA_DPLL_ENABLE; |
||
3017 | sel = TRANSA_DPLLB_SEL; |
||
3018 | break; |
||
3019 | case 1: |
||
3020 | temp |= TRANSB_DPLL_ENABLE; |
||
3021 | sel = TRANSB_DPLLB_SEL; |
||
3022 | break; |
||
3023 | case 2: |
||
3024 | temp |= TRANSC_DPLL_ENABLE; |
||
3025 | sel = TRANSC_DPLLB_SEL; |
||
3026 | break; |
||
2342 | Serge | 3027 | } |
3031 | serge | 3028 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3029 | temp |= sel; |
||
3030 | else |
||
3031 | temp &= ~sel; |
||
2327 | Serge | 3032 | I915_WRITE(PCH_DPLL_SEL, temp); |
3033 | } |
||
3034 | |||
3035 | /* set transcoder timing, panel must allow it */ |
||
3036 | assert_panel_unlocked(dev_priv, pipe); |
||
3037 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
||
3038 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); |
||
3039 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); |
||
3040 | |||
3041 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
||
3042 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); |
||
3043 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); |
||
3031 | serge | 3044 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
2327 | Serge | 3045 | |
3031 | serge | 3046 | if (!IS_HASWELL(dev)) |
2327 | Serge | 3047 | intel_fdi_normal_train(crtc); |
3048 | |||
3049 | /* For PCH DP, enable TRANS_DP_CTL */ |
||
3050 | if (HAS_PCH_CPT(dev) && |
||
2342 | Serge | 3051 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3052 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
||
2327 | Serge | 3053 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
3054 | reg = TRANS_DP_CTL(pipe); |
||
3055 | temp = I915_READ(reg); |
||
3056 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
||
3057 | TRANS_DP_SYNC_MASK | |
||
3058 | TRANS_DP_BPC_MASK); |
||
3059 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
||
3060 | TRANS_DP_ENH_FRAMING); |
||
3061 | temp |= bpc << 9; /* same format but at 11:9 */ |
||
3062 | |||
3063 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
||
3064 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
||
3065 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
||
3066 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
||
3067 | |||
3068 | switch (intel_trans_dp_port_sel(crtc)) { |
||
3069 | case PCH_DP_B: |
||
3070 | temp |= TRANS_DP_PORT_SEL_B; |
||
3071 | break; |
||
3072 | case PCH_DP_C: |
||
3073 | temp |= TRANS_DP_PORT_SEL_C; |
||
3074 | break; |
||
3075 | case PCH_DP_D: |
||
3076 | temp |= TRANS_DP_PORT_SEL_D; |
||
3077 | break; |
||
3078 | default: |
||
3079 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); |
||
3080 | temp |= TRANS_DP_PORT_SEL_B; |
||
3081 | break; |
||
3082 | } |
||
3083 | |||
3084 | I915_WRITE(reg, temp); |
||
3085 | } |
||
3086 | |||
3087 | intel_enable_transcoder(dev_priv, pipe); |
||
3088 | } |
||
3089 | |||
3031 | serge | 3090 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3091 | { |
||
3092 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
||
3093 | |||
3094 | if (pll == NULL) |
||
3095 | return; |
||
3096 | |||
3097 | if (pll->refcount == 0) { |
||
3098 | WARN(1, "bad PCH PLL refcount\n"); |
||
3099 | return; |
||
3100 | } |
||
3101 | |||
3102 | --pll->refcount; |
||
3103 | intel_crtc->pch_pll = NULL; |
||
3104 | } |
||
3105 | |||
3106 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) |
||
3107 | { |
||
3108 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
||
3109 | struct intel_pch_pll *pll; |
||
3110 | int i; |
||
3111 | |||
3112 | pll = intel_crtc->pch_pll; |
||
3113 | if (pll) { |
||
3114 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", |
||
3115 | intel_crtc->base.base.id, pll->pll_reg); |
||
3116 | goto prepare; |
||
3117 | } |
||
3118 | |||
3119 | if (HAS_PCH_IBX(dev_priv->dev)) { |
||
3120 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
||
3121 | i = intel_crtc->pipe; |
||
3122 | pll = &dev_priv->pch_plls[i]; |
||
3123 | |||
3124 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", |
||
3125 | intel_crtc->base.base.id, pll->pll_reg); |
||
3126 | |||
3127 | goto found; |
||
3128 | } |
||
3129 | |||
3130 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
||
3131 | pll = &dev_priv->pch_plls[i]; |
||
3132 | |||
3133 | /* Only want to check enabled timings first */ |
||
3134 | if (pll->refcount == 0) |
||
3135 | continue; |
||
3136 | |||
3137 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && |
||
3138 | fp == I915_READ(pll->fp0_reg)) { |
||
3139 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", |
||
3140 | intel_crtc->base.base.id, |
||
3141 | pll->pll_reg, pll->refcount, pll->active); |
||
3142 | |||
3143 | goto found; |
||
3144 | } |
||
3145 | } |
||
3146 | |||
3147 | /* Ok no matching timings, maybe there's a free one? */ |
||
3148 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
||
3149 | pll = &dev_priv->pch_plls[i]; |
||
3150 | if (pll->refcount == 0) { |
||
3151 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", |
||
3152 | intel_crtc->base.base.id, pll->pll_reg); |
||
3153 | goto found; |
||
3154 | } |
||
3155 | } |
||
3156 | |||
3157 | return NULL; |
||
3158 | |||
3159 | found: |
||
3160 | intel_crtc->pch_pll = pll; |
||
3161 | pll->refcount++; |
||
3162 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); |
||
3163 | prepare: /* separate function? */ |
||
3164 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); |
||
3165 | |||
3166 | /* Wait for the clocks to stabilize before rewriting the regs */ |
||
3167 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); |
||
3168 | POSTING_READ(pll->pll_reg); |
||
3169 | udelay(150); |
||
3170 | |||
3171 | I915_WRITE(pll->fp0_reg, fp); |
||
3172 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); |
||
3173 | pll->on = false; |
||
3174 | return pll; |
||
3175 | } |
||
3176 | |||
2342 | Serge | 3177 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3178 | { |
||
3179 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3180 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); |
||
3181 | u32 temp; |
||
3182 | |||
3183 | temp = I915_READ(dslreg); |
||
3184 | udelay(500); |
||
3185 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
||
3186 | /* Without this, mode sets may fail silently on FDI */ |
||
3187 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); |
||
3188 | udelay(250); |
||
3189 | I915_WRITE(tc2reg, 0); |
||
3190 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
||
3191 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); |
||
3192 | } |
||
3193 | } |
||
3194 | |||
2327 | Serge | 3195 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3196 | { |
||
3197 | struct drm_device *dev = crtc->dev; |
||
3198 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3200 | struct intel_encoder *encoder; |
2327 | Serge | 3201 | int pipe = intel_crtc->pipe; |
3202 | int plane = intel_crtc->plane; |
||
3203 | u32 temp; |
||
3204 | bool is_pch_port; |
||
3205 | |||
3031 | serge | 3206 | WARN_ON(!crtc->enabled); |
3207 | |||
2327 | Serge | 3208 | if (intel_crtc->active) |
3209 | return; |
||
3210 | |||
3211 | intel_crtc->active = true; |
||
3212 | intel_update_watermarks(dev); |
||
3213 | |||
3214 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
||
3215 | temp = I915_READ(PCH_LVDS); |
||
3216 | if ((temp & LVDS_PORT_EN) == 0) |
||
3217 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
||
3218 | } |
||
3219 | |||
3220 | is_pch_port = intel_crtc_driving_pch(crtc); |
||
3221 | |||
3031 | serge | 3222 | if (is_pch_port) { |
3223 | ironlake_fdi_pll_enable(intel_crtc); |
||
3224 | } else { |
||
3225 | assert_fdi_tx_disabled(dev_priv, pipe); |
||
3226 | assert_fdi_rx_disabled(dev_priv, pipe); |
||
3227 | } |
||
2327 | Serge | 3228 | |
3031 | serge | 3229 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3230 | if (encoder->pre_enable) |
||
3231 | encoder->pre_enable(encoder); |
||
3232 | |||
2327 | Serge | 3233 | /* Enable panel fitting for LVDS */ |
3234 | if (dev_priv->pch_pf_size && |
||
3235 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
||
3236 | /* Force use of hard-coded filter coefficients |
||
3237 | * as some pre-programmed values are broken, |
||
3238 | * e.g. x201. |
||
3239 | */ |
||
3240 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
||
3241 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
||
3242 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); |
||
3243 | } |
||
3244 | |||
3245 | /* |
||
3246 | * On ILK+ LUT must be loaded before the pipe is running but with |
||
3247 | * clocks enabled |
||
3248 | */ |
||
3249 | intel_crtc_load_lut(crtc); |
||
3250 | |||
3251 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
||
3252 | intel_enable_plane(dev_priv, plane, pipe); |
||
3253 | |||
3254 | if (is_pch_port) |
||
3255 | ironlake_pch_enable(crtc); |
||
3256 | |||
3257 | mutex_lock(&dev->struct_mutex); |
||
3258 | intel_update_fbc(dev); |
||
3259 | mutex_unlock(&dev->struct_mutex); |
||
3260 | |||
3261 | // intel_crtc_update_cursor(crtc, true); |
||
3031 | serge | 3262 | |
3263 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3264 | encoder->enable(encoder); |
||
3265 | |||
3266 | if (HAS_PCH_CPT(dev)) |
||
3267 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); |
||
3268 | |||
3269 | /* |
||
3270 | * There seems to be a race in PCH platform hw (at least on some |
||
3271 | * outputs) where an enabled pipe still completes any pageflip right |
||
3272 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
||
3273 | * as the first vblank happend, everything works as expected. Hence just |
||
3274 | * wait for one vblank before returning to avoid strange things |
||
3275 | * happening. |
||
3276 | */ |
||
3277 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
2327 | Serge | 3278 | } |
3279 | |||
3280 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
||
3281 | { |
||
3282 | struct drm_device *dev = crtc->dev; |
||
3283 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3285 | struct intel_encoder *encoder; |
2327 | Serge | 3286 | int pipe = intel_crtc->pipe; |
3287 | int plane = intel_crtc->plane; |
||
3288 | u32 reg, temp; |
||
3289 | |||
3031 | serge | 3290 | |
2327 | Serge | 3291 | if (!intel_crtc->active) |
3292 | return; |
||
3293 | |||
3031 | serge | 3294 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3295 | encoder->disable(encoder); |
||
2336 | Serge | 3296 | |
3031 | serge | 3297 | // intel_crtc_wait_for_pending_flips(crtc); |
2327 | Serge | 3298 | // drm_vblank_off(dev, pipe); |
3299 | // intel_crtc_update_cursor(crtc, false); |
||
3300 | |||
3301 | intel_disable_plane(dev_priv, plane, pipe); |
||
3302 | |||
3303 | if (dev_priv->cfb_plane == plane) |
||
3304 | intel_disable_fbc(dev); |
||
3305 | |||
3306 | intel_disable_pipe(dev_priv, pipe); |
||
3307 | |||
3308 | /* Disable PF */ |
||
3309 | I915_WRITE(PF_CTL(pipe), 0); |
||
3310 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
||
3311 | |||
3031 | serge | 3312 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3313 | if (encoder->post_disable) |
||
3314 | encoder->post_disable(encoder); |
||
3315 | |||
2327 | Serge | 3316 | ironlake_fdi_disable(crtc); |
3317 | |||
3318 | intel_disable_transcoder(dev_priv, pipe); |
||
3319 | |||
3320 | if (HAS_PCH_CPT(dev)) { |
||
3321 | /* disable TRANS_DP_CTL */ |
||
3322 | reg = TRANS_DP_CTL(pipe); |
||
3323 | temp = I915_READ(reg); |
||
3324 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); |
||
3325 | temp |= TRANS_DP_PORT_SEL_NONE; |
||
3326 | I915_WRITE(reg, temp); |
||
3327 | |||
3328 | /* disable DPLL_SEL */ |
||
3329 | temp = I915_READ(PCH_DPLL_SEL); |
||
3330 | switch (pipe) { |
||
3331 | case 0: |
||
2342 | Serge | 3332 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
2327 | Serge | 3333 | break; |
3334 | case 1: |
||
3335 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
||
3336 | break; |
||
3337 | case 2: |
||
2342 | Serge | 3338 | /* C shares PLL A or B */ |
2327 | Serge | 3339 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
3340 | break; |
||
3341 | default: |
||
3342 | BUG(); /* wtf */ |
||
3343 | } |
||
3344 | I915_WRITE(PCH_DPLL_SEL, temp); |
||
3345 | } |
||
3346 | |||
3347 | /* disable PCH DPLL */ |
||
3031 | serge | 3348 | intel_disable_pch_pll(intel_crtc); |
2327 | Serge | 3349 | |
3031 | serge | 3350 | ironlake_fdi_pll_disable(intel_crtc); |
2327 | Serge | 3351 | |
3352 | intel_crtc->active = false; |
||
3353 | intel_update_watermarks(dev); |
||
3354 | |||
3355 | mutex_lock(&dev->struct_mutex); |
||
3356 | intel_update_fbc(dev); |
||
3357 | mutex_unlock(&dev->struct_mutex); |
||
3358 | } |
||
3359 | |||
3031 | serge | 3360 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
2327 | Serge | 3361 | { |
3362 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3363 | intel_put_pch_pll(intel_crtc); |
2327 | Serge | 3364 | } |
3365 | |||
3366 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
||
3367 | { |
||
3368 | if (!enable && intel_crtc->overlay) { |
||
3369 | struct drm_device *dev = intel_crtc->base.dev; |
||
3370 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3371 | |||
3372 | mutex_lock(&dev->struct_mutex); |
||
3373 | dev_priv->mm.interruptible = false; |
||
3374 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
||
3375 | dev_priv->mm.interruptible = true; |
||
3376 | mutex_unlock(&dev->struct_mutex); |
||
3377 | } |
||
3378 | |||
3379 | /* Let userspace switch the overlay on again. In most cases userspace |
||
3380 | * has to recompute where to put it anyway. |
||
3381 | */ |
||
3382 | } |
||
3383 | |||
3384 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
||
3385 | { |
||
3386 | struct drm_device *dev = crtc->dev; |
||
3387 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3388 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3389 | struct intel_encoder *encoder; |
2327 | Serge | 3390 | int pipe = intel_crtc->pipe; |
3391 | int plane = intel_crtc->plane; |
||
3392 | |||
3031 | serge | 3393 | WARN_ON(!crtc->enabled); |
3394 | |||
2327 | Serge | 3395 | if (intel_crtc->active) |
3396 | return; |
||
3397 | |||
3398 | intel_crtc->active = true; |
||
3399 | intel_update_watermarks(dev); |
||
3400 | |||
3401 | intel_enable_pll(dev_priv, pipe); |
||
3402 | intel_enable_pipe(dev_priv, pipe, false); |
||
3403 | intel_enable_plane(dev_priv, plane, pipe); |
||
3404 | |||
3405 | intel_crtc_load_lut(crtc); |
||
3406 | intel_update_fbc(dev); |
||
3407 | |||
3408 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
||
3409 | intel_crtc_dpms_overlay(intel_crtc, true); |
||
3410 | // intel_crtc_update_cursor(crtc, true); |
||
3031 | serge | 3411 | |
3412 | for_each_encoder_on_crtc(dev, crtc, encoder) |
||
3413 | encoder->enable(encoder); |
||
2327 | Serge | 3414 | } |
3415 | |||
3416 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
||
3417 | { |
||
3418 | struct drm_device *dev = crtc->dev; |
||
3419 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3031 | serge | 3421 | struct intel_encoder *encoder; |
2327 | Serge | 3422 | int pipe = intel_crtc->pipe; |
3423 | int plane = intel_crtc->plane; |
||
3424 | |||
3031 | serge | 3425 | |
2327 | Serge | 3426 | if (!intel_crtc->active) |
3427 | return; |
||
3428 | |||
3031 | serge | 3429 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3430 | encoder->disable(encoder); |
||
3431 | |||
2327 | Serge | 3432 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
3031 | serge | 3433 | // intel_crtc_wait_for_pending_flips(crtc); |
2327 | Serge | 3434 | // drm_vblank_off(dev, pipe); |
3435 | intel_crtc_dpms_overlay(intel_crtc, false); |
||
3436 | // intel_crtc_update_cursor(crtc, false); |
||
3437 | |||
3438 | if (dev_priv->cfb_plane == plane) |
||
3439 | intel_disable_fbc(dev); |
||
3440 | |||
3441 | intel_disable_plane(dev_priv, plane, pipe); |
||
3442 | intel_disable_pipe(dev_priv, pipe); |
||
3443 | intel_disable_pll(dev_priv, pipe); |
||
3444 | |||
3445 | intel_crtc->active = false; |
||
3446 | intel_update_fbc(dev); |
||
3447 | intel_update_watermarks(dev); |
||
3448 | } |
||
3449 | |||
3031 | serge | 3450 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
2327 | Serge | 3451 | { |
3452 | } |
||
3453 | |||
3031 | serge | 3454 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3455 | bool enabled) |
||
2330 | Serge | 3456 | { |
3457 | struct drm_device *dev = crtc->dev; |
||
3458 | struct drm_i915_master_private *master_priv; |
||
3459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3460 | int pipe = intel_crtc->pipe; |
||
2327 | Serge | 3461 | |
3462 | |||
2340 | Serge | 3463 | #if 0 |
2330 | Serge | 3464 | if (!dev->primary->master) |
3465 | return; |
||
2327 | Serge | 3466 | |
2330 | Serge | 3467 | master_priv = dev->primary->master->driver_priv; |
3468 | if (!master_priv->sarea_priv) |
||
3469 | return; |
||
2327 | Serge | 3470 | |
2330 | Serge | 3471 | switch (pipe) { |
3472 | case 0: |
||
3473 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
||
3474 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
||
3475 | break; |
||
3476 | case 1: |
||
3477 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
||
3478 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
||
3479 | break; |
||
3480 | default: |
||
3481 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
||
3482 | break; |
||
3483 | } |
||
2340 | Serge | 3484 | #endif |
3485 | |||
2330 | Serge | 3486 | } |
2327 | Serge | 3487 | |
3031 | serge | 3488 | /** |
3489 | * Sets the power management mode of the pipe and plane. |
||
3490 | */ |
||
3491 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
||
3492 | { |
||
3493 | struct drm_device *dev = crtc->dev; |
||
3494 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3495 | struct intel_encoder *intel_encoder; |
||
3496 | bool enable = false; |
||
3497 | |||
3498 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
||
3499 | enable |= intel_encoder->connectors_active; |
||
3500 | |||
3501 | if (enable) |
||
3502 | dev_priv->display.crtc_enable(crtc); |
||
3503 | else |
||
3504 | dev_priv->display.crtc_disable(crtc); |
||
3505 | |||
3506 | intel_crtc_update_sarea(crtc, enable); |
||
3507 | } |
||
3508 | |||
3509 | static void intel_crtc_noop(struct drm_crtc *crtc) |
||
3510 | { |
||
3511 | } |
||
3512 | |||
2330 | Serge | 3513 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3514 | { |
||
3515 | struct drm_device *dev = crtc->dev; |
||
3031 | serge | 3516 | struct drm_connector *connector; |
3517 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 3518 | |
3031 | serge | 3519 | /* crtc should still be enabled when we disable it. */ |
3520 | WARN_ON(!crtc->enabled); |
||
2327 | Serge | 3521 | |
3031 | serge | 3522 | dev_priv->display.crtc_disable(crtc); |
3523 | intel_crtc_update_sarea(crtc, false); |
||
3524 | dev_priv->display.off(crtc); |
||
3525 | |||
3526 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
||
3527 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
||
3528 | |||
3529 | // if (crtc->fb) { |
||
3530 | // mutex_lock(&dev->struct_mutex); |
||
3531 | // intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
||
3532 | // mutex_unlock(&dev->struct_mutex); |
||
3533 | // crtc->fb = NULL; |
||
3534 | // } |
||
3535 | |||
3536 | /* Update computed state. */ |
||
3537 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
3538 | if (!connector->encoder || !connector->encoder->crtc) |
||
3539 | continue; |
||
3540 | |||
3541 | if (connector->encoder->crtc != crtc) |
||
3542 | continue; |
||
3543 | |||
3544 | connector->dpms = DRM_MODE_DPMS_OFF; |
||
3545 | to_intel_encoder(connector->encoder)->connectors_active = false; |
||
2330 | Serge | 3546 | } |
3547 | } |
||
2327 | Serge | 3548 | |
3031 | serge | 3549 | void intel_modeset_disable(struct drm_device *dev) |
2330 | Serge | 3550 | { |
3031 | serge | 3551 | struct drm_crtc *crtc; |
3552 | |||
3553 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
||
3554 | if (crtc->enabled) |
||
3555 | intel_crtc_disable(crtc); |
||
3556 | } |
||
2330 | Serge | 3557 | } |
2327 | Serge | 3558 | |
3031 | serge | 3559 | void intel_encoder_noop(struct drm_encoder *encoder) |
2330 | Serge | 3560 | { |
3561 | } |
||
2327 | Serge | 3562 | |
3031 | serge | 3563 | void intel_encoder_destroy(struct drm_encoder *encoder) |
2330 | Serge | 3564 | { |
3031 | serge | 3565 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
3566 | |||
3567 | drm_encoder_cleanup(encoder); |
||
3568 | kfree(intel_encoder); |
||
2330 | Serge | 3569 | } |
2327 | Serge | 3570 | |
3031 | serge | 3571 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3572 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
||
3573 | * state of the entire output pipe. */ |
||
3574 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
||
2330 | Serge | 3575 | { |
3031 | serge | 3576 | if (mode == DRM_MODE_DPMS_ON) { |
3577 | encoder->connectors_active = true; |
||
3578 | |||
3579 | intel_crtc_update_dpms(encoder->base.crtc); |
||
3580 | } else { |
||
3581 | encoder->connectors_active = false; |
||
3582 | |||
3583 | intel_crtc_update_dpms(encoder->base.crtc); |
||
3584 | } |
||
2330 | Serge | 3585 | } |
2327 | Serge | 3586 | |
3031 | serge | 3587 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3588 | * internal consistency). */ |
||
3589 | static void intel_connector_check_state(struct intel_connector *connector) |
||
2330 | Serge | 3590 | { |
3031 | serge | 3591 | if (connector->get_hw_state(connector)) { |
3592 | struct intel_encoder *encoder = connector->encoder; |
||
3593 | struct drm_crtc *crtc; |
||
3594 | bool encoder_enabled; |
||
3595 | enum pipe pipe; |
||
3596 | |||
3597 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
||
3598 | connector->base.base.id, |
||
3599 | drm_get_connector_name(&connector->base)); |
||
3600 | |||
3601 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
||
3602 | "wrong connector dpms state\n"); |
||
3603 | WARN(connector->base.encoder != &encoder->base, |
||
3604 | "active connector not linked to encoder\n"); |
||
3605 | WARN(!encoder->connectors_active, |
||
3606 | "encoder->connectors_active not set\n"); |
||
3607 | |||
3608 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
||
3609 | WARN(!encoder_enabled, "encoder not enabled\n"); |
||
3610 | if (WARN_ON(!encoder->base.crtc)) |
||
3611 | return; |
||
3612 | |||
3613 | crtc = encoder->base.crtc; |
||
3614 | |||
3615 | WARN(!crtc->enabled, "crtc not enabled\n"); |
||
3616 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
||
3617 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
||
3618 | "encoder active on the wrong pipe\n"); |
||
3619 | } |
||
2330 | Serge | 3620 | } |
2327 | Serge | 3621 | |
3031 | serge | 3622 | /* Even simpler default implementation, if there's really no special case to |
3623 | * consider. */ |
||
3624 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
||
2330 | Serge | 3625 | { |
3031 | serge | 3626 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
2342 | Serge | 3627 | |
3031 | serge | 3628 | /* All the simple cases only support two dpms states. */ |
3629 | if (mode != DRM_MODE_DPMS_ON) |
||
3630 | mode = DRM_MODE_DPMS_OFF; |
||
2342 | Serge | 3631 | |
3031 | serge | 3632 | if (mode == connector->dpms) |
3633 | return; |
||
3634 | |||
3635 | connector->dpms = mode; |
||
3636 | |||
3637 | /* Only need to change hw state when actually enabled */ |
||
3638 | if (encoder->base.crtc) |
||
3639 | intel_encoder_dpms(encoder, mode); |
||
3640 | else |
||
3641 | WARN_ON(encoder->connectors_active != false); |
||
3642 | |||
3643 | intel_modeset_check_state(connector->dev); |
||
2330 | Serge | 3644 | } |
2327 | Serge | 3645 | |
3031 | serge | 3646 | /* Simple connector->get_hw_state implementation for encoders that support only |
3647 | * one connector and no cloning and hence the encoder state determines the state |
||
3648 | * of the connector. */ |
||
3649 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
||
2330 | Serge | 3650 | { |
3031 | serge | 3651 | enum pipe pipe = 0; |
3652 | struct intel_encoder *encoder = connector->encoder; |
||
2330 | Serge | 3653 | |
3031 | serge | 3654 | return encoder->get_hw_state(encoder, &pipe); |
2330 | Serge | 3655 | } |
3656 | |||
3657 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
||
3031 | serge | 3658 | const struct drm_display_mode *mode, |
2330 | Serge | 3659 | struct drm_display_mode *adjusted_mode) |
3660 | { |
||
3661 | struct drm_device *dev = crtc->dev; |
||
3662 | |||
3663 | if (HAS_PCH_SPLIT(dev)) { |
||
3664 | /* FDI link clock is fixed at 2.7G */ |
||
3665 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
||
3666 | return false; |
||
3667 | } |
||
3668 | |||
3031 | serge | 3669 | /* All interlaced capable intel hw wants timings in frames. Note though |
3670 | * that intel_lvds_mode_fixup does some funny tricks with the crtc |
||
3671 | * timings, so we need to be careful not to clobber these.*/ |
||
3672 | if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) |
||
2330 | Serge | 3673 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
3674 | |||
3031 | serge | 3675 | /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes |
3676 | * with a hsync front porch of 0. |
||
3677 | */ |
||
3678 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
||
3679 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
||
3680 | return false; |
||
3681 | |||
2330 | Serge | 3682 | return true; |
3683 | } |
||
3684 | |||
3031 | serge | 3685 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3686 | { |
||
3687 | return 400000; /* FIXME */ |
||
3688 | } |
||
3689 | |||
2327 | Serge | 3690 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3691 | { |
||
3692 | return 400000; |
||
3693 | } |
||
3694 | |||
3695 | static int i915_get_display_clock_speed(struct drm_device *dev) |
||
3696 | { |
||
3697 | return 333000; |
||
3698 | } |
||
3699 | |||
3700 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
||
3701 | { |
||
3702 | return 200000; |
||
3703 | } |
||
3704 | |||
3705 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
||
3706 | { |
||
3707 | u16 gcfgc = 0; |
||
3708 | |||
3709 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
||
3710 | |||
3711 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
||
3712 | return 133000; |
||
3713 | else { |
||
3714 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
||
3715 | case GC_DISPLAY_CLOCK_333_MHZ: |
||
3716 | return 333000; |
||
3717 | default: |
||
3718 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
||
3719 | return 190000; |
||
3720 | } |
||
3721 | } |
||
3722 | } |
||
3723 | |||
3724 | static int i865_get_display_clock_speed(struct drm_device *dev) |
||
3725 | { |
||
3726 | return 266000; |
||
3727 | } |
||
3728 | |||
3729 | static int i855_get_display_clock_speed(struct drm_device *dev) |
||
3730 | { |
||
3731 | u16 hpllcc = 0; |
||
3732 | /* Assume that the hardware is in the high speed state. This |
||
3733 | * should be the default. |
||
3734 | */ |
||
3735 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
||
3736 | case GC_CLOCK_133_200: |
||
3737 | case GC_CLOCK_100_200: |
||
3738 | return 200000; |
||
3739 | case GC_CLOCK_166_250: |
||
3740 | return 250000; |
||
3741 | case GC_CLOCK_100_133: |
||
3742 | return 133000; |
||
3743 | } |
||
3744 | |||
3745 | /* Shouldn't happen */ |
||
3746 | return 0; |
||
3747 | } |
||
3748 | |||
3749 | static int i830_get_display_clock_speed(struct drm_device *dev) |
||
3750 | { |
||
3751 | return 133000; |
||
3752 | } |
||
3753 | |||
3754 | struct fdi_m_n { |
||
3755 | u32 tu; |
||
3756 | u32 gmch_m; |
||
3757 | u32 gmch_n; |
||
3758 | u32 link_m; |
||
3759 | u32 link_n; |
||
3760 | }; |
||
3761 | |||
3762 | static void |
||
3763 | fdi_reduce_ratio(u32 *num, u32 *den) |
||
3764 | { |
||
3765 | while (*num > 0xffffff || *den > 0xffffff) { |
||
3766 | *num >>= 1; |
||
3767 | *den >>= 1; |
||
3768 | } |
||
3769 | } |
||
3770 | |||
3771 | static void |
||
3772 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
||
3773 | int link_clock, struct fdi_m_n *m_n) |
||
3774 | { |
||
3775 | m_n->tu = 64; /* default size */ |
||
3776 | |||
3777 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
||
3778 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
||
3779 | m_n->gmch_n = link_clock * nlanes * 8; |
||
3780 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
||
3781 | |||
3782 | m_n->link_m = pixel_clock; |
||
3783 | m_n->link_n = link_clock; |
||
3784 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
||
3785 | } |
||
3786 | |||
3787 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
||
3788 | { |
||
2342 | Serge | 3789 | if (i915_panel_use_ssc >= 0) |
3790 | return i915_panel_use_ssc != 0; |
||
3791 | return dev_priv->lvds_use_ssc |
||
2327 | Serge | 3792 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
3793 | } |
||
3794 | |||
3795 | /** |
||
3796 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send |
||
3797 | * @crtc: CRTC structure |
||
2342 | Serge | 3798 | * @mode: requested mode |
2327 | Serge | 3799 | * |
3800 | * A pipe may be connected to one or more outputs. Based on the depth of the |
||
3801 | * attached framebuffer, choose a good color depth to use on the pipe. |
||
3802 | * |
||
3803 | * If possible, match the pipe depth to the fb depth. In some cases, this |
||
3804 | * isn't ideal, because the connected output supports a lesser or restricted |
||
3805 | * set of depths. Resolve that here: |
||
3806 | * LVDS typically supports only 6bpc, so clamp down in that case |
||
3807 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc |
||
3808 | * Displays may support a restricted set as well, check EDID and clamp as |
||
3809 | * appropriate. |
||
2342 | Serge | 3810 | * DP may want to dither down to 6bpc to fit larger modes |
2327 | Serge | 3811 | * |
3812 | * RETURNS: |
||
3813 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, |
||
3814 | * true if they don't match). |
||
3815 | */ |
||
3816 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, |
||
3031 | serge | 3817 | struct drm_framebuffer *fb, |
2342 | Serge | 3818 | unsigned int *pipe_bpp, |
3819 | struct drm_display_mode *mode) |
||
2327 | Serge | 3820 | { |
3821 | struct drm_device *dev = crtc->dev; |
||
3822 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3823 | struct drm_connector *connector; |
||
3031 | serge | 3824 | struct intel_encoder *intel_encoder; |
2327 | Serge | 3825 | unsigned int display_bpc = UINT_MAX, bpc; |
3826 | |||
3827 | /* Walk the encoders & connectors on this crtc, get min bpc */ |
||
3031 | serge | 3828 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
2327 | Serge | 3829 | |
3830 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { |
||
3831 | unsigned int lvds_bpc; |
||
3832 | |||
3833 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == |
||
3834 | LVDS_A3_POWER_UP) |
||
3835 | lvds_bpc = 8; |
||
3836 | else |
||
3837 | lvds_bpc = 6; |
||
3838 | |||
3839 | if (lvds_bpc < display_bpc) { |
||
2342 | Serge | 3840 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
2327 | Serge | 3841 | display_bpc = lvds_bpc; |
3842 | } |
||
3843 | continue; |
||
3844 | } |
||
3845 | |||
3846 | /* Not one of the known troublemakers, check the EDID */ |
||
3847 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
3848 | head) { |
||
3031 | serge | 3849 | if (connector->encoder != &intel_encoder->base) |
2327 | Serge | 3850 | continue; |
3851 | |||
3852 | /* Don't use an invalid EDID bpc value */ |
||
3853 | if (connector->display_info.bpc && |
||
3854 | connector->display_info.bpc < display_bpc) { |
||
2342 | Serge | 3855 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
2327 | Serge | 3856 | display_bpc = connector->display_info.bpc; |
3031 | serge | 3857 | } |
3858 | } |
||
2327 | Serge | 3859 | |
3860 | /* |
||
3861 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
||
3862 | * through, clamp it down. (Note: >12bpc will be caught below.) |
||
3863 | */ |
||
3864 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
||
3865 | if (display_bpc > 8 && display_bpc < 12) { |
||
2342 | Serge | 3866 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
2327 | Serge | 3867 | display_bpc = 12; |
3868 | } else { |
||
2342 | Serge | 3869 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
2327 | Serge | 3870 | display_bpc = 8; |
3871 | } |
||
3872 | } |
||
3873 | } |
||
3874 | |||
2342 | Serge | 3875 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
3876 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); |
||
3877 | display_bpc = 6; |
||
3878 | } |
||
3879 | |||
2327 | Serge | 3880 | /* |
3881 | * We could just drive the pipe at the highest bpc all the time and |
||
3882 | * enable dithering as needed, but that costs bandwidth. So choose |
||
3883 | * the minimum value that expresses the full color range of the fb but |
||
3884 | * also stays within the max display bpc discovered above. |
||
3885 | */ |
||
3886 | |||
3031 | serge | 3887 | switch (fb->depth) { |
2327 | Serge | 3888 | case 8: |
3889 | bpc = 8; /* since we go through a colormap */ |
||
3890 | break; |
||
3891 | case 15: |
||
3892 | case 16: |
||
3893 | bpc = 6; /* min is 18bpp */ |
||
3894 | break; |
||
3895 | case 24: |
||
2342 | Serge | 3896 | bpc = 8; |
2327 | Serge | 3897 | break; |
3898 | case 30: |
||
2342 | Serge | 3899 | bpc = 10; |
2327 | Serge | 3900 | break; |
3901 | case 48: |
||
2342 | Serge | 3902 | bpc = 12; |
2327 | Serge | 3903 | break; |
3904 | default: |
||
3905 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); |
||
3906 | bpc = min((unsigned int)8, display_bpc); |
||
3907 | break; |
||
3908 | } |
||
3909 | |||
2342 | Serge | 3910 | display_bpc = min(display_bpc, bpc); |
3911 | |||
3912 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
||
3031 | serge | 3913 | bpc, display_bpc); |
2327 | Serge | 3914 | |
2342 | Serge | 3915 | *pipe_bpp = display_bpc * 3; |
2327 | Serge | 3916 | |
3917 | return display_bpc != bpc; |
||
3918 | } |
||
3919 | |||
3031 | serge | 3920 | static int vlv_get_refclk(struct drm_crtc *crtc) |
2327 | Serge | 3921 | { |
3031 | serge | 3922 | struct drm_device *dev = crtc->dev; |
3923 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3924 | int refclk = 27000; /* for DP & HDMI */ |
||
2327 | Serge | 3925 | |
3031 | serge | 3926 | return 100000; /* only one validated so far */ |
2327 | Serge | 3927 | |
3031 | serge | 3928 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
3929 | refclk = 96000; |
||
3930 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
||
3931 | if (intel_panel_use_ssc(dev_priv)) |
||
3932 | refclk = 100000; |
||
3933 | else |
||
3934 | refclk = 96000; |
||
3935 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
||
3936 | refclk = 100000; |
||
3937 | } |
||
2327 | Serge | 3938 | |
3031 | serge | 3939 | return refclk; |
3940 | } |
||
2327 | Serge | 3941 | |
3031 | serge | 3942 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
3943 | { |
||
3944 | struct drm_device *dev = crtc->dev; |
||
3945 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3946 | int refclk; |
||
2327 | Serge | 3947 | |
3031 | serge | 3948 | if (IS_VALLEYVIEW(dev)) { |
3949 | refclk = vlv_get_refclk(crtc); |
||
3950 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
||
3951 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
||
3952 | refclk = dev_priv->lvds_ssc_freq * 1000; |
||
3953 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
||
3954 | refclk / 1000); |
||
3955 | } else if (!IS_GEN2(dev)) { |
||
3956 | refclk = 96000; |
||
3957 | } else { |
||
3958 | refclk = 48000; |
||
3959 | } |
||
2327 | Serge | 3960 | |
3031 | serge | 3961 | return refclk; |
3962 | } |
||
2327 | Serge | 3963 | |
3031 | serge | 3964 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, |
3965 | intel_clock_t *clock) |
||
3966 | { |
||
3967 | /* SDVO TV has fixed PLL values depend on its clock range, |
||
3968 | this mirrors vbios setting. */ |
||
3969 | if (adjusted_mode->clock >= 100000 |
||
3970 | && adjusted_mode->clock < 140500) { |
||
3971 | clock->p1 = 2; |
||
3972 | clock->p2 = 10; |
||
3973 | clock->n = 3; |
||
3974 | clock->m1 = 16; |
||
3975 | clock->m2 = 8; |
||
3976 | } else if (adjusted_mode->clock >= 140500 |
||
3977 | && adjusted_mode->clock <= 200000) { |
||
3978 | clock->p1 = 1; |
||
3979 | clock->p2 = 10; |
||
3980 | clock->n = 6; |
||
3981 | clock->m1 = 12; |
||
3982 | clock->m2 = 8; |
||
3983 | } |
||
3984 | } |
||
2327 | Serge | 3985 | |
3031 | serge | 3986 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
3987 | intel_clock_t *clock, |
||
3988 | intel_clock_t *reduced_clock) |
||
3989 | { |
||
3990 | struct drm_device *dev = crtc->dev; |
||
3991 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
3993 | int pipe = intel_crtc->pipe; |
||
3994 | u32 fp, fp2 = 0; |
||
2327 | Serge | 3995 | |
3031 | serge | 3996 | if (IS_PINEVIEW(dev)) { |
3997 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; |
||
3998 | if (reduced_clock) |
||
3999 | fp2 = (1 << reduced_clock->n) << 16 | |
||
4000 | reduced_clock->m1 << 8 | reduced_clock->m2; |
||
4001 | } else { |
||
4002 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; |
||
4003 | if (reduced_clock) |
||
4004 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | |
||
4005 | reduced_clock->m2; |
||
4006 | } |
||
2327 | Serge | 4007 | |
3031 | serge | 4008 | I915_WRITE(FP0(pipe), fp); |
2327 | Serge | 4009 | |
3031 | serge | 4010 | intel_crtc->lowfreq_avail = false; |
4011 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
||
4012 | reduced_clock && i915_powersave) { |
||
4013 | I915_WRITE(FP1(pipe), fp2); |
||
4014 | intel_crtc->lowfreq_avail = true; |
||
4015 | } else { |
||
4016 | I915_WRITE(FP1(pipe), fp); |
||
4017 | } |
||
4018 | } |
||
2327 | Serge | 4019 | |
3031 | serge | 4020 | static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, |
4021 | struct drm_display_mode *adjusted_mode) |
||
4022 | { |
||
4023 | struct drm_device *dev = crtc->dev; |
||
4024 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4025 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4026 | int pipe = intel_crtc->pipe; |
||
4027 | u32 temp; |
||
2327 | Serge | 4028 | |
3031 | serge | 4029 | temp = I915_READ(LVDS); |
4030 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
||
4031 | if (pipe == 1) { |
||
4032 | temp |= LVDS_PIPEB_SELECT; |
||
4033 | } else { |
||
4034 | temp &= ~LVDS_PIPEB_SELECT; |
||
4035 | } |
||
4036 | /* set the corresponsding LVDS_BORDER bit */ |
||
4037 | temp |= dev_priv->lvds_border_bits; |
||
4038 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
||
4039 | * set the DPLLs for dual-channel mode or not. |
||
4040 | */ |
||
4041 | if (clock->p2 == 7) |
||
4042 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
||
4043 | else |
||
4044 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
||
2327 | Serge | 4045 | |
3031 | serge | 4046 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
4047 | * appropriately here, but we need to look more thoroughly into how |
||
4048 | * panels behave in the two modes. |
||
4049 | */ |
||
4050 | /* set the dithering flag on LVDS as needed */ |
||
4051 | if (INTEL_INFO(dev)->gen >= 4) { |
||
4052 | if (dev_priv->lvds_dither) |
||
4053 | temp |= LVDS_ENABLE_DITHER; |
||
4054 | else |
||
4055 | temp &= ~LVDS_ENABLE_DITHER; |
||
4056 | } |
||
4057 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
||
4058 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
4059 | temp |= LVDS_HSYNC_POLARITY; |
||
4060 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
||
4061 | temp |= LVDS_VSYNC_POLARITY; |
||
4062 | I915_WRITE(LVDS, temp); |
||
4063 | } |
||
2327 | Serge | 4064 | |
3031 | serge | 4065 | static void vlv_update_pll(struct drm_crtc *crtc, |
4066 | struct drm_display_mode *mode, |
||
4067 | struct drm_display_mode *adjusted_mode, |
||
4068 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
||
4069 | int refclk, int num_connectors) |
||
4070 | { |
||
4071 | struct drm_device *dev = crtc->dev; |
||
4072 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4074 | int pipe = intel_crtc->pipe; |
||
4075 | u32 dpll, mdiv, pdiv; |
||
4076 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
||
4077 | bool is_hdmi; |
||
2327 | Serge | 4078 | |
3031 | serge | 4079 | is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); |
2327 | Serge | 4080 | |
3031 | serge | 4081 | bestn = clock->n; |
4082 | bestm1 = clock->m1; |
||
4083 | bestm2 = clock->m2; |
||
4084 | bestp1 = clock->p1; |
||
4085 | bestp2 = clock->p2; |
||
4086 | |||
4087 | /* Enable DPIO clock input */ |
||
4088 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
||
4089 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
||
4090 | I915_WRITE(DPLL(pipe), dpll); |
||
4091 | POSTING_READ(DPLL(pipe)); |
||
4092 | |||
4093 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
||
4094 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
||
4095 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
||
4096 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); |
||
4097 | mdiv |= (1 << DPIO_K_SHIFT); |
||
4098 | mdiv |= DPIO_ENABLE_CALIBRATION; |
||
4099 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
||
4100 | |||
4101 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); |
||
4102 | |||
4103 | pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) | |
||
4104 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | |
||
4105 | (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT); |
||
4106 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); |
||
4107 | |||
4108 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051); |
||
4109 | |||
4110 | dpll |= DPLL_VCO_ENABLE; |
||
4111 | I915_WRITE(DPLL(pipe), dpll); |
||
4112 | POSTING_READ(DPLL(pipe)); |
||
4113 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
||
4114 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
||
4115 | |||
4116 | if (is_hdmi) { |
||
4117 | u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
||
4118 | |||
4119 | if (temp > 1) |
||
4120 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
||
4121 | else |
||
4122 | temp = 0; |
||
4123 | |||
4124 | I915_WRITE(DPLL_MD(pipe), temp); |
||
4125 | POSTING_READ(DPLL_MD(pipe)); |
||
4126 | } |
||
4127 | |||
4128 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ |
||
4129 | } |
||
4130 | |||
4131 | static void i9xx_update_pll(struct drm_crtc *crtc, |
||
4132 | struct drm_display_mode *mode, |
||
4133 | struct drm_display_mode *adjusted_mode, |
||
4134 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
||
4135 | int num_connectors) |
||
4136 | { |
||
4137 | struct drm_device *dev = crtc->dev; |
||
4138 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4140 | int pipe = intel_crtc->pipe; |
||
4141 | u32 dpll; |
||
4142 | bool is_sdvo; |
||
4143 | |||
4144 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
||
4145 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); |
||
4146 | |||
4147 | dpll = DPLL_VGA_MODE_DIS; |
||
4148 | |||
4149 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
||
4150 | dpll |= DPLLB_MODE_LVDS; |
||
4151 | else |
||
4152 | dpll |= DPLLB_MODE_DAC_SERIAL; |
||
4153 | if (is_sdvo) { |
||
4154 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
||
4155 | if (pixel_multiplier > 1) { |
||
4156 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
||
4157 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
||
2342 | Serge | 4158 | } |
3031 | serge | 4159 | dpll |= DPLL_DVO_HIGH_SPEED; |
2342 | Serge | 4160 | } |
3031 | serge | 4161 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
4162 | dpll |= DPLL_DVO_HIGH_SPEED; |
||
2342 | Serge | 4163 | |
3031 | serge | 4164 | /* compute bitmask from p1 value */ |
4165 | if (IS_PINEVIEW(dev)) |
||
4166 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
||
4167 | else { |
||
4168 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
||
4169 | if (IS_G4X(dev) && reduced_clock) |
||
4170 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
||
4171 | } |
||
4172 | switch (clock->p2) { |
||
4173 | case 5: |
||
4174 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
||
4175 | break; |
||
4176 | case 7: |
||
4177 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
||
4178 | break; |
||
4179 | case 10: |
||
4180 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
||
4181 | break; |
||
4182 | case 14: |
||
4183 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
||
4184 | break; |
||
4185 | } |
||
4186 | if (INTEL_INFO(dev)->gen >= 4) |
||
4187 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
||
2327 | Serge | 4188 | |
3031 | serge | 4189 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
4190 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
||
4191 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
||
4192 | /* XXX: just matching BIOS for now */ |
||
4193 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
||
4194 | dpll |= 3; |
||
4195 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
||
4196 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
||
4197 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
||
4198 | else |
||
4199 | dpll |= PLL_REF_INPUT_DREFCLK; |
||
2327 | Serge | 4200 | |
3031 | serge | 4201 | dpll |= DPLL_VCO_ENABLE; |
4202 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
||
4203 | POSTING_READ(DPLL(pipe)); |
||
4204 | udelay(150); |
||
2327 | Serge | 4205 | |
3031 | serge | 4206 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4207 | * This is an exception to the general rule that mode_set doesn't turn |
||
4208 | * things on. |
||
4209 | */ |
||
4210 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
||
4211 | intel_update_lvds(crtc, clock, adjusted_mode); |
||
2327 | Serge | 4212 | |
3031 | serge | 4213 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
4214 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
||
2327 | Serge | 4215 | |
3031 | serge | 4216 | I915_WRITE(DPLL(pipe), dpll); |
2327 | Serge | 4217 | |
3031 | serge | 4218 | /* Wait for the clocks to stabilize. */ |
4219 | POSTING_READ(DPLL(pipe)); |
||
4220 | udelay(150); |
||
2327 | Serge | 4221 | |
3031 | serge | 4222 | if (INTEL_INFO(dev)->gen >= 4) { |
4223 | u32 temp = 0; |
||
4224 | if (is_sdvo) { |
||
4225 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
||
4226 | if (temp > 1) |
||
4227 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
||
4228 | else |
||
4229 | temp = 0; |
||
4230 | } |
||
4231 | I915_WRITE(DPLL_MD(pipe), temp); |
||
4232 | } else { |
||
4233 | /* The pixel multiplier can only be updated once the |
||
4234 | * DPLL is enabled and the clocks are stable. |
||
4235 | * |
||
4236 | * So write it again. |
||
4237 | */ |
||
4238 | I915_WRITE(DPLL(pipe), dpll); |
||
4239 | } |
||
4240 | } |
||
2327 | Serge | 4241 | |
3031 | serge | 4242 | static void i8xx_update_pll(struct drm_crtc *crtc, |
4243 | struct drm_display_mode *adjusted_mode, |
||
4244 | intel_clock_t *clock, |
||
4245 | int num_connectors) |
||
4246 | { |
||
4247 | struct drm_device *dev = crtc->dev; |
||
4248 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4250 | int pipe = intel_crtc->pipe; |
||
4251 | u32 dpll; |
||
2327 | Serge | 4252 | |
3031 | serge | 4253 | dpll = DPLL_VGA_MODE_DIS; |
2327 | Serge | 4254 | |
3031 | serge | 4255 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
4256 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
||
4257 | } else { |
||
4258 | if (clock->p1 == 2) |
||
4259 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
||
4260 | else |
||
4261 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
||
4262 | if (clock->p2 == 4) |
||
4263 | dpll |= PLL_P2_DIVIDE_BY_4; |
||
4264 | } |
||
2327 | Serge | 4265 | |
3031 | serge | 4266 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
4267 | /* XXX: just matching BIOS for now */ |
||
4268 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
||
4269 | dpll |= 3; |
||
4270 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
||
4271 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
||
4272 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
||
4273 | else |
||
4274 | dpll |= PLL_REF_INPUT_DREFCLK; |
||
4275 | |||
4276 | dpll |= DPLL_VCO_ENABLE; |
||
4277 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
||
4278 | POSTING_READ(DPLL(pipe)); |
||
4279 | udelay(150); |
||
4280 | |||
4281 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
||
4282 | * This is an exception to the general rule that mode_set doesn't turn |
||
4283 | * things on. |
||
4284 | */ |
||
4285 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
||
4286 | intel_update_lvds(crtc, clock, adjusted_mode); |
||
4287 | |||
4288 | I915_WRITE(DPLL(pipe), dpll); |
||
4289 | |||
4290 | /* Wait for the clocks to stabilize. */ |
||
4291 | POSTING_READ(DPLL(pipe)); |
||
4292 | udelay(150); |
||
4293 | |||
4294 | /* The pixel multiplier can only be updated once the |
||
4295 | * DPLL is enabled and the clocks are stable. |
||
4296 | * |
||
4297 | * So write it again. |
||
4298 | */ |
||
4299 | I915_WRITE(DPLL(pipe), dpll); |
||
4300 | } |
||
4301 | |||
4302 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
||
4303 | struct drm_display_mode *mode, |
||
4304 | struct drm_display_mode *adjusted_mode, |
||
4305 | int x, int y, |
||
4306 | struct drm_framebuffer *fb) |
||
4307 | { |
||
4308 | struct drm_device *dev = crtc->dev; |
||
4309 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4311 | int pipe = intel_crtc->pipe; |
||
4312 | int plane = intel_crtc->plane; |
||
4313 | int refclk, num_connectors = 0; |
||
4314 | intel_clock_t clock, reduced_clock; |
||
4315 | u32 dspcntr, pipeconf, vsyncshift; |
||
4316 | bool ok, has_reduced_clock = false, is_sdvo = false; |
||
4317 | bool is_lvds = false, is_tv = false, is_dp = false; |
||
4318 | struct intel_encoder *encoder; |
||
4319 | const intel_limit_t *limit; |
||
4320 | int ret; |
||
4321 | |||
4322 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
||
4323 | switch (encoder->type) { |
||
4324 | case INTEL_OUTPUT_LVDS: |
||
4325 | is_lvds = true; |
||
4326 | break; |
||
4327 | case INTEL_OUTPUT_SDVO: |
||
4328 | case INTEL_OUTPUT_HDMI: |
||
4329 | is_sdvo = true; |
||
4330 | if (encoder->needs_tv_clock) |
||
4331 | is_tv = true; |
||
4332 | break; |
||
4333 | case INTEL_OUTPUT_TVOUT: |
||
4334 | is_tv = true; |
||
4335 | break; |
||
4336 | case INTEL_OUTPUT_DISPLAYPORT: |
||
4337 | is_dp = true; |
||
4338 | break; |
||
4339 | } |
||
4340 | |||
4341 | num_connectors++; |
||
4342 | } |
||
4343 | |||
4344 | refclk = i9xx_get_refclk(crtc, num_connectors); |
||
4345 | |||
4346 | /* |
||
4347 | * Returns a set of divisors for the desired target clock with the given |
||
4348 | * refclk, or FALSE. The returned values represent the clock equation: |
||
4349 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
||
4350 | */ |
||
4351 | limit = intel_limit(crtc, refclk); |
||
4352 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
||
4353 | &clock); |
||
4354 | if (!ok) { |
||
4355 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
||
4356 | return -EINVAL; |
||
4357 | } |
||
4358 | |||
4359 | /* Ensure that the cursor is valid for the new mode before changing... */ |
||
4360 | // intel_crtc_update_cursor(crtc, true); |
||
4361 | |||
4362 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
||
4363 | /* |
||
4364 | * Ensure we match the reduced clock's P to the target clock. |
||
4365 | * If the clocks don't match, we can't switch the display clock |
||
4366 | * by using the FP0/FP1. In such case we will disable the LVDS |
||
4367 | * downclock feature. |
||
4368 | */ |
||
4369 | has_reduced_clock = limit->find_pll(limit, crtc, |
||
4370 | dev_priv->lvds_downclock, |
||
4371 | refclk, |
||
4372 | &clock, |
||
4373 | &reduced_clock); |
||
4374 | } |
||
4375 | |||
4376 | if (is_sdvo && is_tv) |
||
4377 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); |
||
4378 | |||
4379 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
||
4380 | &reduced_clock : NULL); |
||
4381 | |||
4382 | if (IS_GEN2(dev)) |
||
4383 | i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); |
||
4384 | else if (IS_VALLEYVIEW(dev)) |
||
4385 | vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL, |
||
4386 | refclk, num_connectors); |
||
4387 | else |
||
4388 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
||
4389 | has_reduced_clock ? &reduced_clock : NULL, |
||
4390 | num_connectors); |
||
4391 | |||
4392 | /* setup pipeconf */ |
||
4393 | pipeconf = I915_READ(PIPECONF(pipe)); |
||
4394 | |||
4395 | /* Set up the display plane register */ |
||
4396 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
||
4397 | |||
4398 | if (pipe == 0) |
||
4399 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
||
4400 | else |
||
4401 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
||
4402 | |||
4403 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
||
4404 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
||
4405 | * core speed. |
||
4406 | * |
||
4407 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
||
4408 | * pipe == 0 check? |
||
4409 | */ |
||
4410 | if (mode->clock > |
||
4411 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
||
4412 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
||
4413 | else |
||
4414 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
||
4415 | } |
||
4416 | |||
4417 | /* default to 8bpc */ |
||
4418 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); |
||
4419 | if (is_dp) { |
||
4420 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
||
4421 | pipeconf |= PIPECONF_BPP_6 | |
||
4422 | PIPECONF_DITHER_EN | |
||
4423 | PIPECONF_DITHER_TYPE_SP; |
||
4424 | } |
||
4425 | } |
||
4426 | |||
4427 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
||
4428 | drm_mode_debug_printmodeline(mode); |
||
4429 | |||
4430 | if (HAS_PIPE_CXSR(dev)) { |
||
4431 | if (intel_crtc->lowfreq_avail) { |
||
4432 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
||
4433 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
||
4434 | } else { |
||
4435 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
||
4436 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
||
4437 | } |
||
4438 | } |
||
4439 | |||
2360 | Serge | 4440 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
3031 | serge | 4441 | if (!IS_GEN2(dev) && |
4442 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
||
4443 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
||
4444 | /* the chip adds 2 halflines automatically */ |
||
4445 | adjusted_mode->crtc_vtotal -= 1; |
||
4446 | adjusted_mode->crtc_vblank_end -= 1; |
||
4447 | vsyncshift = adjusted_mode->crtc_hsync_start |
||
4448 | - adjusted_mode->crtc_htotal/2; |
||
4449 | } else { |
||
2360 | Serge | 4450 | pipeconf |= PIPECONF_PROGRESSIVE; |
3031 | serge | 4451 | vsyncshift = 0; |
4452 | } |
||
2327 | Serge | 4453 | |
3031 | serge | 4454 | if (!IS_GEN3(dev)) |
4455 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); |
||
2327 | Serge | 4456 | |
3031 | serge | 4457 | I915_WRITE(HTOTAL(pipe), |
4458 | (adjusted_mode->crtc_hdisplay - 1) | |
||
4459 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
||
4460 | I915_WRITE(HBLANK(pipe), |
||
4461 | (adjusted_mode->crtc_hblank_start - 1) | |
||
4462 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
||
4463 | I915_WRITE(HSYNC(pipe), |
||
4464 | (adjusted_mode->crtc_hsync_start - 1) | |
||
4465 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
||
2327 | Serge | 4466 | |
3031 | serge | 4467 | I915_WRITE(VTOTAL(pipe), |
4468 | (adjusted_mode->crtc_vdisplay - 1) | |
||
4469 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
||
4470 | I915_WRITE(VBLANK(pipe), |
||
4471 | (adjusted_mode->crtc_vblank_start - 1) | |
||
4472 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
||
4473 | I915_WRITE(VSYNC(pipe), |
||
4474 | (adjusted_mode->crtc_vsync_start - 1) | |
||
4475 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
||
2327 | Serge | 4476 | |
3031 | serge | 4477 | /* pipesrc and dspsize control the size that is scaled from, |
4478 | * which should always be the user's requested size. |
||
4479 | */ |
||
4480 | I915_WRITE(DSPSIZE(plane), |
||
4481 | ((mode->vdisplay - 1) << 16) | |
||
4482 | (mode->hdisplay - 1)); |
||
4483 | I915_WRITE(DSPPOS(plane), 0); |
||
4484 | I915_WRITE(PIPESRC(pipe), |
||
4485 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
||
2327 | Serge | 4486 | |
3031 | serge | 4487 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4488 | POSTING_READ(PIPECONF(pipe)); |
||
4489 | intel_enable_pipe(dev_priv, pipe, false); |
||
2327 | Serge | 4490 | |
3031 | serge | 4491 | intel_wait_for_vblank(dev, pipe); |
2327 | Serge | 4492 | |
3031 | serge | 4493 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4494 | POSTING_READ(DSPCNTR(plane)); |
||
2327 | Serge | 4495 | |
3031 | serge | 4496 | ret = intel_pipe_set_base(crtc, x, y, fb); |
2327 | Serge | 4497 | |
3031 | serge | 4498 | intel_update_watermarks(dev); |
4499 | |||
2327 | Serge | 4500 | return ret; |
4501 | } |
||
4502 | |||
2342 | Serge | 4503 | /* |
4504 | * Initialize reference clocks when the driver loads |
||
4505 | */ |
||
4506 | void ironlake_init_pch_refclk(struct drm_device *dev) |
||
2327 | Serge | 4507 | { |
4508 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4509 | struct drm_mode_config *mode_config = &dev->mode_config; |
||
4510 | struct intel_encoder *encoder; |
||
4511 | u32 temp; |
||
4512 | bool has_lvds = false; |
||
2342 | Serge | 4513 | bool has_cpu_edp = false; |
4514 | bool has_pch_edp = false; |
||
4515 | bool has_panel = false; |
||
4516 | bool has_ck505 = false; |
||
4517 | bool can_ssc = false; |
||
2327 | Serge | 4518 | |
4519 | /* We need to take the global config into account */ |
||
4520 | list_for_each_entry(encoder, &mode_config->encoder_list, |
||
4521 | base.head) { |
||
4522 | switch (encoder->type) { |
||
4523 | case INTEL_OUTPUT_LVDS: |
||
2342 | Serge | 4524 | has_panel = true; |
2327 | Serge | 4525 | has_lvds = true; |
2342 | Serge | 4526 | break; |
2327 | Serge | 4527 | case INTEL_OUTPUT_EDP: |
2342 | Serge | 4528 | has_panel = true; |
4529 | if (intel_encoder_is_pch_edp(&encoder->base)) |
||
4530 | has_pch_edp = true; |
||
4531 | else |
||
4532 | has_cpu_edp = true; |
||
2327 | Serge | 4533 | break; |
4534 | } |
||
4535 | } |
||
2342 | Serge | 4536 | |
4537 | if (HAS_PCH_IBX(dev)) { |
||
4538 | has_ck505 = dev_priv->display_clock_mode; |
||
4539 | can_ssc = has_ck505; |
||
4540 | } else { |
||
4541 | has_ck505 = false; |
||
4542 | can_ssc = true; |
||
2327 | Serge | 4543 | } |
4544 | |||
2342 | Serge | 4545 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", |
4546 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, |
||
4547 | has_ck505); |
||
4548 | |||
2327 | Serge | 4549 | /* Ironlake: try to setup display ref clock before DPLL |
4550 | * enabling. This is only under driver's control after |
||
4551 | * PCH B stepping, previous chipset stepping should be |
||
4552 | * ignoring this setting. |
||
4553 | */ |
||
4554 | temp = I915_READ(PCH_DREF_CONTROL); |
||
4555 | /* Always enable nonspread source */ |
||
4556 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
||
2342 | Serge | 4557 | |
4558 | if (has_ck505) |
||
4559 | temp |= DREF_NONSPREAD_CK505_ENABLE; |
||
4560 | else |
||
2327 | Serge | 4561 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; |
2342 | Serge | 4562 | |
4563 | if (has_panel) { |
||
2327 | Serge | 4564 | temp &= ~DREF_SSC_SOURCE_MASK; |
4565 | temp |= DREF_SSC_SOURCE_ENABLE; |
||
4566 | |||
2342 | Serge | 4567 | /* SSC must be turned on before enabling the CPU output */ |
4568 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
||
4569 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
||
4570 | temp |= DREF_SSC1_ENABLE; |
||
3031 | serge | 4571 | } else |
4572 | temp &= ~DREF_SSC1_ENABLE; |
||
2327 | Serge | 4573 | |
2342 | Serge | 4574 | /* Get SSC going before enabling the outputs */ |
2327 | Serge | 4575 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4576 | POSTING_READ(PCH_DREF_CONTROL); |
||
4577 | udelay(200); |
||
2342 | Serge | 4578 | |
2327 | Serge | 4579 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4580 | |||
4581 | /* Enable CPU source on CPU attached eDP */ |
||
2342 | Serge | 4582 | if (has_cpu_edp) { |
4583 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
||
4584 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
||
2327 | Serge | 4585 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
2342 | Serge | 4586 | } |
2327 | Serge | 4587 | else |
4588 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
||
2342 | Serge | 4589 | } else |
4590 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
||
4591 | |||
4592 | I915_WRITE(PCH_DREF_CONTROL, temp); |
||
4593 | POSTING_READ(PCH_DREF_CONTROL); |
||
4594 | udelay(200); |
||
2327 | Serge | 4595 | } else { |
2342 | Serge | 4596 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
4597 | |||
4598 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
||
4599 | |||
4600 | /* Turn off CPU output */ |
||
4601 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
||
4602 | |||
2327 | Serge | 4603 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4604 | POSTING_READ(PCH_DREF_CONTROL); |
||
4605 | udelay(200); |
||
2342 | Serge | 4606 | |
4607 | /* Turn off the SSC source */ |
||
4608 | temp &= ~DREF_SSC_SOURCE_MASK; |
||
4609 | temp |= DREF_SSC_SOURCE_DISABLE; |
||
4610 | |||
4611 | /* Turn off SSC1 */ |
||
4612 | temp &= ~ DREF_SSC1_ENABLE; |
||
4613 | |||
4614 | I915_WRITE(PCH_DREF_CONTROL, temp); |
||
4615 | POSTING_READ(PCH_DREF_CONTROL); |
||
4616 | udelay(200); |
||
2327 | Serge | 4617 | } |
4618 | } |
||
4619 | |||
2342 | Serge | 4620 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
4621 | { |
||
4622 | struct drm_device *dev = crtc->dev; |
||
4623 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4624 | struct intel_encoder *encoder; |
||
4625 | struct intel_encoder *edp_encoder = NULL; |
||
4626 | int num_connectors = 0; |
||
4627 | bool is_lvds = false; |
||
4628 | |||
3031 | serge | 4629 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
2342 | Serge | 4630 | switch (encoder->type) { |
4631 | case INTEL_OUTPUT_LVDS: |
||
4632 | is_lvds = true; |
||
4633 | break; |
||
4634 | case INTEL_OUTPUT_EDP: |
||
4635 | edp_encoder = encoder; |
||
4636 | break; |
||
4637 | } |
||
4638 | num_connectors++; |
||
4639 | } |
||
4640 | |||
4641 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
||
4642 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
||
4643 | dev_priv->lvds_ssc_freq); |
||
4644 | return dev_priv->lvds_ssc_freq * 1000; |
||
4645 | } |
||
4646 | |||
4647 | return 120000; |
||
4648 | } |
||
4649 | |||
3031 | serge | 4650 | static void ironlake_set_pipeconf(struct drm_crtc *crtc, |
4651 | struct drm_display_mode *adjusted_mode, |
||
4652 | bool dither) |
||
4653 | { |
||
4654 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
||
4655 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4656 | int pipe = intel_crtc->pipe; |
||
4657 | uint32_t val; |
||
4658 | |||
4659 | val = I915_READ(PIPECONF(pipe)); |
||
4660 | |||
4661 | val &= ~PIPE_BPC_MASK; |
||
4662 | switch (intel_crtc->bpp) { |
||
4663 | case 18: |
||
4664 | val |= PIPE_6BPC; |
||
4665 | break; |
||
4666 | case 24: |
||
4667 | val |= PIPE_8BPC; |
||
4668 | break; |
||
4669 | case 30: |
||
4670 | val |= PIPE_10BPC; |
||
4671 | break; |
||
4672 | case 36: |
||
4673 | val |= PIPE_12BPC; |
||
4674 | break; |
||
4675 | default: |
||
4676 | val |= PIPE_8BPC; |
||
4677 | break; |
||
4678 | } |
||
4679 | |||
4680 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); |
||
4681 | if (dither) |
||
4682 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
||
4683 | |||
4684 | val &= ~PIPECONF_INTERLACE_MASK; |
||
4685 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
4686 | val |= PIPECONF_INTERLACED_ILK; |
||
4687 | else |
||
4688 | val |= PIPECONF_PROGRESSIVE; |
||
4689 | |||
4690 | I915_WRITE(PIPECONF(pipe), val); |
||
4691 | POSTING_READ(PIPECONF(pipe)); |
||
4692 | } |
||
4693 | |||
4694 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
||
4695 | struct drm_display_mode *adjusted_mode, |
||
4696 | intel_clock_t *clock, |
||
4697 | bool *has_reduced_clock, |
||
4698 | intel_clock_t *reduced_clock) |
||
4699 | { |
||
4700 | struct drm_device *dev = crtc->dev; |
||
4701 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4702 | struct intel_encoder *intel_encoder; |
||
4703 | int refclk; |
||
4704 | const intel_limit_t *limit; |
||
4705 | bool ret, is_sdvo = false, is_tv = false, is_lvds = false; |
||
4706 | |||
4707 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
||
4708 | switch (intel_encoder->type) { |
||
4709 | case INTEL_OUTPUT_LVDS: |
||
4710 | is_lvds = true; |
||
4711 | break; |
||
4712 | case INTEL_OUTPUT_SDVO: |
||
4713 | case INTEL_OUTPUT_HDMI: |
||
4714 | is_sdvo = true; |
||
4715 | if (intel_encoder->needs_tv_clock) |
||
4716 | is_tv = true; |
||
4717 | break; |
||
4718 | case INTEL_OUTPUT_TVOUT: |
||
4719 | is_tv = true; |
||
4720 | break; |
||
4721 | } |
||
4722 | } |
||
4723 | |||
4724 | refclk = ironlake_get_refclk(crtc); |
||
4725 | |||
4726 | /* |
||
4727 | * Returns a set of divisors for the desired target clock with the given |
||
4728 | * refclk, or FALSE. The returned values represent the clock equation: |
||
4729 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
||
4730 | */ |
||
4731 | limit = intel_limit(crtc, refclk); |
||
4732 | ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
||
4733 | clock); |
||
4734 | if (!ret) |
||
4735 | return false; |
||
4736 | |||
4737 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
||
4738 | /* |
||
4739 | * Ensure we match the reduced clock's P to the target clock. |
||
4740 | * If the clocks don't match, we can't switch the display clock |
||
4741 | * by using the FP0/FP1. In such case we will disable the LVDS |
||
4742 | * downclock feature. |
||
4743 | */ |
||
4744 | *has_reduced_clock = limit->find_pll(limit, crtc, |
||
4745 | dev_priv->lvds_downclock, |
||
4746 | refclk, |
||
4747 | clock, |
||
4748 | reduced_clock); |
||
4749 | } |
||
4750 | |||
4751 | if (is_sdvo && is_tv) |
||
4752 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock); |
||
4753 | |||
4754 | return true; |
||
4755 | } |
||
4756 | |||
2327 | Serge | 4757 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
4758 | struct drm_display_mode *mode, |
||
4759 | struct drm_display_mode *adjusted_mode, |
||
4760 | int x, int y, |
||
3031 | serge | 4761 | struct drm_framebuffer *fb) |
2327 | Serge | 4762 | { |
4763 | struct drm_device *dev = crtc->dev; |
||
4764 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
4766 | int pipe = intel_crtc->pipe; |
||
4767 | int plane = intel_crtc->plane; |
||
3031 | serge | 4768 | int num_connectors = 0; |
2327 | Serge | 4769 | intel_clock_t clock, reduced_clock; |
3031 | serge | 4770 | u32 dpll, fp = 0, fp2 = 0; |
2327 | Serge | 4771 | bool ok, has_reduced_clock = false, is_sdvo = false; |
4772 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
||
3031 | serge | 4773 | struct intel_encoder *encoder, *edp_encoder = NULL; |
2327 | Serge | 4774 | int ret; |
4775 | struct fdi_m_n m_n = {0}; |
||
4776 | u32 temp; |
||
4777 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
||
4778 | unsigned int pipe_bpp; |
||
4779 | bool dither; |
||
3031 | serge | 4780 | bool is_cpu_edp = false, is_pch_edp = false; |
2327 | Serge | 4781 | |
3031 | serge | 4782 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
2327 | Serge | 4783 | switch (encoder->type) { |
4784 | case INTEL_OUTPUT_LVDS: |
||
4785 | is_lvds = true; |
||
4786 | break; |
||
4787 | case INTEL_OUTPUT_SDVO: |
||
4788 | case INTEL_OUTPUT_HDMI: |
||
4789 | is_sdvo = true; |
||
4790 | if (encoder->needs_tv_clock) |
||
4791 | is_tv = true; |
||
4792 | break; |
||
4793 | case INTEL_OUTPUT_TVOUT: |
||
4794 | is_tv = true; |
||
4795 | break; |
||
4796 | case INTEL_OUTPUT_ANALOG: |
||
4797 | is_crt = true; |
||
4798 | break; |
||
4799 | case INTEL_OUTPUT_DISPLAYPORT: |
||
4800 | is_dp = true; |
||
4801 | break; |
||
4802 | case INTEL_OUTPUT_EDP: |
||
3031 | serge | 4803 | is_dp = true; |
4804 | if (intel_encoder_is_pch_edp(&encoder->base)) |
||
4805 | is_pch_edp = true; |
||
4806 | else |
||
4807 | is_cpu_edp = true; |
||
4808 | edp_encoder = encoder; |
||
2327 | Serge | 4809 | break; |
4810 | } |
||
4811 | |||
4812 | num_connectors++; |
||
4813 | } |
||
4814 | |||
3031 | serge | 4815 | ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, |
4816 | &has_reduced_clock, &reduced_clock); |
||
2327 | Serge | 4817 | if (!ok) { |
4818 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
||
4819 | return -EINVAL; |
||
4820 | } |
||
4821 | |||
4822 | /* Ensure that the cursor is valid for the new mode before changing... */ |
||
4823 | // intel_crtc_update_cursor(crtc, true); |
||
4824 | |||
4825 | /* FDI link */ |
||
4826 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
||
4827 | lane = 0; |
||
4828 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
||
4829 | according to current link config */ |
||
3031 | serge | 4830 | if (is_cpu_edp) { |
4831 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
||
2327 | Serge | 4832 | } else { |
4833 | /* FDI is a binary signal running at ~2.7GHz, encoding |
||
4834 | * each output octet as 10 bits. The actual frequency |
||
4835 | * is stored as a divider into a 100MHz clock, and the |
||
4836 | * mode pixel clock is stored in units of 1KHz. |
||
4837 | * Hence the bw of each lane in terms of the mode signal |
||
4838 | * is: |
||
4839 | */ |
||
4840 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
||
4841 | } |
||
4842 | |||
3031 | serge | 4843 | /* [e]DP over FDI requires target mode clock instead of link clock. */ |
4844 | if (edp_encoder) |
||
4845 | target_clock = intel_edp_target_clock(edp_encoder, mode); |
||
4846 | else if (is_dp) |
||
4847 | target_clock = mode->clock; |
||
4848 | else |
||
4849 | target_clock = adjusted_mode->clock; |
||
4850 | |||
2327 | Serge | 4851 | /* determine panel color depth */ |
3031 | serge | 4852 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, |
4853 | adjusted_mode); |
||
4854 | if (is_lvds && dev_priv->lvds_dither) |
||
4855 | dither = true; |
||
4856 | |||
4857 | if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 && |
||
4858 | pipe_bpp != 36) { |
||
2327 | Serge | 4859 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
4860 | pipe_bpp); |
||
4861 | pipe_bpp = 24; |
||
4862 | } |
||
4863 | intel_crtc->bpp = pipe_bpp; |
||
4864 | |||
4865 | if (!lane) { |
||
4866 | /* |
||
4867 | * Account for spread spectrum to avoid |
||
4868 | * oversubscribing the link. Max center spread |
||
4869 | * is 2.5%; use 5% for safety's sake. |
||
4870 | */ |
||
4871 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
||
4872 | lane = bps / (link_bw * 8) + 1; |
||
4873 | } |
||
4874 | |||
4875 | intel_crtc->fdi_lanes = lane; |
||
4876 | |||
4877 | if (pixel_multiplier > 1) |
||
4878 | link_bw *= pixel_multiplier; |
||
4879 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
||
4880 | &m_n); |
||
4881 | |||
4882 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
||
4883 | if (has_reduced_clock) |
||
4884 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | |
||
4885 | reduced_clock.m2; |
||
4886 | |||
4887 | /* Enable autotuning of the PLL clock (if permissible) */ |
||
4888 | factor = 21; |
||
4889 | if (is_lvds) { |
||
4890 | if ((intel_panel_use_ssc(dev_priv) && |
||
4891 | dev_priv->lvds_ssc_freq == 100) || |
||
4892 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) |
||
4893 | factor = 25; |
||
4894 | } else if (is_sdvo && is_tv) |
||
4895 | factor = 20; |
||
4896 | |||
4897 | if (clock.m < factor * clock.n) |
||
4898 | fp |= FP_CB_TUNE; |
||
4899 | |||
4900 | dpll = 0; |
||
4901 | |||
4902 | if (is_lvds) |
||
4903 | dpll |= DPLLB_MODE_LVDS; |
||
4904 | else |
||
4905 | dpll |= DPLLB_MODE_DAC_SERIAL; |
||
4906 | if (is_sdvo) { |
||
4907 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
||
4908 | if (pixel_multiplier > 1) { |
||
4909 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
||
4910 | } |
||
4911 | dpll |= DPLL_DVO_HIGH_SPEED; |
||
4912 | } |
||
3031 | serge | 4913 | if (is_dp && !is_cpu_edp) |
2327 | Serge | 4914 | dpll |= DPLL_DVO_HIGH_SPEED; |
4915 | |||
4916 | /* compute bitmask from p1 value */ |
||
4917 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
||
4918 | /* also FPA1 */ |
||
4919 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
||
4920 | |||
4921 | switch (clock.p2) { |
||
4922 | case 5: |
||
4923 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
||
4924 | break; |
||
4925 | case 7: |
||
4926 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
||
4927 | break; |
||
4928 | case 10: |
||
4929 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
||
4930 | break; |
||
4931 | case 14: |
||
4932 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
||
4933 | break; |
||
4934 | } |
||
4935 | |||
4936 | if (is_sdvo && is_tv) |
||
4937 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
||
4938 | else if (is_tv) |
||
4939 | /* XXX: just matching BIOS for now */ |
||
4940 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
||
4941 | dpll |= 3; |
||
4942 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
||
4943 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
||
4944 | else |
||
4945 | dpll |= PLL_REF_INPUT_DREFCLK; |
||
4946 | |||
2342 | Serge | 4947 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
2327 | Serge | 4948 | drm_mode_debug_printmodeline(mode); |
4949 | |||
3031 | serge | 4950 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own on |
4951 | * pre-Haswell/LPT generation */ |
||
4952 | if (HAS_PCH_LPT(dev)) { |
||
4953 | DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n", |
||
4954 | pipe); |
||
4955 | } else if (!is_cpu_edp) { |
||
4956 | struct intel_pch_pll *pll; |
||
2327 | Serge | 4957 | |
3031 | serge | 4958 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
4959 | if (pll == NULL) { |
||
4960 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", |
||
4961 | pipe); |
||
2342 | Serge | 4962 | return -EINVAL; |
2327 | Serge | 4963 | } |
3031 | serge | 4964 | } else |
4965 | intel_put_pch_pll(intel_crtc); |
||
2327 | Serge | 4966 | |
4967 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
||
4968 | * This is an exception to the general rule that mode_set doesn't turn |
||
4969 | * things on. |
||
4970 | */ |
||
4971 | if (is_lvds) { |
||
4972 | temp = I915_READ(PCH_LVDS); |
||
4973 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
||
2342 | Serge | 4974 | if (HAS_PCH_CPT(dev)) { |
4975 | temp &= ~PORT_TRANS_SEL_MASK; |
||
4976 | temp |= PORT_TRANS_SEL_CPT(pipe); |
||
4977 | } else { |
||
4978 | if (pipe == 1) |
||
2327 | Serge | 4979 | temp |= LVDS_PIPEB_SELECT; |
4980 | else |
||
4981 | temp &= ~LVDS_PIPEB_SELECT; |
||
4982 | } |
||
2342 | Serge | 4983 | |
2327 | Serge | 4984 | /* set the corresponsding LVDS_BORDER bit */ |
4985 | temp |= dev_priv->lvds_border_bits; |
||
4986 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
||
4987 | * set the DPLLs for dual-channel mode or not. |
||
4988 | */ |
||
4989 | if (clock.p2 == 7) |
||
4990 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
||
4991 | else |
||
4992 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
||
4993 | |||
4994 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
||
4995 | * appropriately here, but we need to look more thoroughly into how |
||
4996 | * panels behave in the two modes. |
||
4997 | */ |
||
3031 | serge | 4998 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
2327 | Serge | 4999 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
3031 | serge | 5000 | temp |= LVDS_HSYNC_POLARITY; |
2327 | Serge | 5001 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
3031 | serge | 5002 | temp |= LVDS_VSYNC_POLARITY; |
2327 | Serge | 5003 | I915_WRITE(PCH_LVDS, temp); |
5004 | } |
||
5005 | |||
3031 | serge | 5006 | if (is_dp && !is_cpu_edp) { |
2327 | Serge | 5007 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
5008 | } else { |
||
5009 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
||
5010 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
||
5011 | I915_WRITE(TRANSDATA_N1(pipe), 0); |
||
5012 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); |
||
5013 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); |
||
5014 | } |
||
5015 | |||
3031 | serge | 5016 | if (intel_crtc->pch_pll) { |
5017 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
||
2327 | Serge | 5018 | |
5019 | /* Wait for the clocks to stabilize. */ |
||
3031 | serge | 5020 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
2327 | Serge | 5021 | udelay(150); |
5022 | |||
5023 | /* The pixel multiplier can only be updated once the |
||
5024 | * DPLL is enabled and the clocks are stable. |
||
5025 | * |
||
5026 | * So write it again. |
||
5027 | */ |
||
3031 | serge | 5028 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
2327 | Serge | 5029 | } |
5030 | |||
5031 | intel_crtc->lowfreq_avail = false; |
||
3031 | serge | 5032 | if (intel_crtc->pch_pll) { |
2327 | Serge | 5033 | if (is_lvds && has_reduced_clock && i915_powersave) { |
3031 | serge | 5034 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
2327 | Serge | 5035 | intel_crtc->lowfreq_avail = true; |
5036 | } else { |
||
3031 | serge | 5037 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
2327 | Serge | 5038 | } |
2342 | Serge | 5039 | } |
2327 | Serge | 5040 | |
5041 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
||
5042 | /* the chip adds 2 halflines automatically */ |
||
5043 | adjusted_mode->crtc_vtotal -= 1; |
||
5044 | adjusted_mode->crtc_vblank_end -= 1; |
||
3031 | serge | 5045 | I915_WRITE(VSYNCSHIFT(pipe), |
5046 | adjusted_mode->crtc_hsync_start |
||
5047 | - adjusted_mode->crtc_htotal/2); |
||
5048 | } else { |
||
5049 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
||
5050 | } |
||
2327 | Serge | 5051 | |
5052 | I915_WRITE(HTOTAL(pipe), |
||
5053 | (adjusted_mode->crtc_hdisplay - 1) | |
||
5054 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
||
5055 | I915_WRITE(HBLANK(pipe), |
||
5056 | (adjusted_mode->crtc_hblank_start - 1) | |
||
5057 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
||
5058 | I915_WRITE(HSYNC(pipe), |
||
5059 | (adjusted_mode->crtc_hsync_start - 1) | |
||
5060 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
||
5061 | |||
5062 | I915_WRITE(VTOTAL(pipe), |
||
5063 | (adjusted_mode->crtc_vdisplay - 1) | |
||
5064 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
||
5065 | I915_WRITE(VBLANK(pipe), |
||
5066 | (adjusted_mode->crtc_vblank_start - 1) | |
||
5067 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
||
5068 | I915_WRITE(VSYNC(pipe), |
||
5069 | (adjusted_mode->crtc_vsync_start - 1) | |
||
5070 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
||
5071 | |||
5072 | /* pipesrc controls the size that is scaled from, which should |
||
5073 | * always be the user's requested size. |
||
5074 | */ |
||
5075 | I915_WRITE(PIPESRC(pipe), |
||
5076 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
||
5077 | |||
5078 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
||
5079 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
||
5080 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
||
5081 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
||
5082 | |||
3031 | serge | 5083 | if (is_cpu_edp) |
2327 | Serge | 5084 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
5085 | |||
3031 | serge | 5086 | ironlake_set_pipeconf(crtc, adjusted_mode, dither); |
2327 | Serge | 5087 | |
5088 | intel_wait_for_vblank(dev, pipe); |
||
5089 | |||
3031 | serge | 5090 | /* Set up the display plane register */ |
5091 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
||
2327 | Serge | 5092 | POSTING_READ(DSPCNTR(plane)); |
5093 | |||
3031 | serge | 5094 | ret = intel_pipe_set_base(crtc, x, y, fb); |
2327 | Serge | 5095 | |
5096 | intel_update_watermarks(dev); |
||
5097 | |||
3031 | serge | 5098 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
2336 | Serge | 5099 | |
2327 | Serge | 5100 | return ret; |
5101 | } |
||
5102 | |||
2330 | Serge | 5103 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5104 | struct drm_display_mode *mode, |
||
5105 | struct drm_display_mode *adjusted_mode, |
||
5106 | int x, int y, |
||
3031 | serge | 5107 | struct drm_framebuffer *fb) |
2330 | Serge | 5108 | { |
5109 | struct drm_device *dev = crtc->dev; |
||
5110 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5111 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5112 | int pipe = intel_crtc->pipe; |
||
5113 | int ret; |
||
2327 | Serge | 5114 | |
3031 | serge | 5115 | drm_vblank_pre_modeset(dev, pipe); |
2327 | Serge | 5116 | |
2330 | Serge | 5117 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
3031 | serge | 5118 | x, y, fb); |
5119 | drm_vblank_post_modeset(dev, pipe); |
||
2327 | Serge | 5120 | |
2330 | Serge | 5121 | return ret; |
5122 | } |
||
2327 | Serge | 5123 | |
2342 | Serge | 5124 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5125 | int reg_eldv, uint32_t bits_eldv, |
||
5126 | int reg_elda, uint32_t bits_elda, |
||
5127 | int reg_edid) |
||
5128 | { |
||
5129 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
5130 | uint8_t *eld = connector->eld; |
||
5131 | uint32_t i; |
||
5132 | |||
5133 | i = I915_READ(reg_eldv); |
||
5134 | i &= bits_eldv; |
||
5135 | |||
5136 | if (!eld[0]) |
||
5137 | return !i; |
||
5138 | |||
5139 | if (!i) |
||
5140 | return false; |
||
5141 | |||
5142 | i = I915_READ(reg_elda); |
||
5143 | i &= ~bits_elda; |
||
5144 | I915_WRITE(reg_elda, i); |
||
5145 | |||
5146 | for (i = 0; i < eld[2]; i++) |
||
5147 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
||
5148 | return false; |
||
5149 | |||
5150 | return true; |
||
5151 | } |
||
5152 | |||
5153 | static void g4x_write_eld(struct drm_connector *connector, |
||
5154 | struct drm_crtc *crtc) |
||
5155 | { |
||
5156 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
5157 | uint8_t *eld = connector->eld; |
||
5158 | uint32_t eldv; |
||
5159 | uint32_t len; |
||
5160 | uint32_t i; |
||
5161 | |||
5162 | i = I915_READ(G4X_AUD_VID_DID); |
||
5163 | |||
5164 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
||
5165 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
||
5166 | else |
||
5167 | eldv = G4X_ELDV_DEVCTG; |
||
5168 | |||
5169 | if (intel_eld_uptodate(connector, |
||
5170 | G4X_AUD_CNTL_ST, eldv, |
||
5171 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
||
5172 | G4X_HDMIW_HDMIEDID)) |
||
5173 | return; |
||
5174 | |||
5175 | i = I915_READ(G4X_AUD_CNTL_ST); |
||
5176 | i &= ~(eldv | G4X_ELD_ADDR); |
||
5177 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
||
5178 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
||
5179 | |||
5180 | if (!eld[0]) |
||
5181 | return; |
||
5182 | |||
5183 | len = min_t(uint8_t, eld[2], len); |
||
5184 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
||
5185 | for (i = 0; i < len; i++) |
||
5186 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
||
5187 | |||
5188 | i = I915_READ(G4X_AUD_CNTL_ST); |
||
5189 | i |= eldv; |
||
5190 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
||
5191 | } |
||
5192 | |||
3031 | serge | 5193 | static void haswell_write_eld(struct drm_connector *connector, |
5194 | struct drm_crtc *crtc) |
||
5195 | { |
||
5196 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
5197 | uint8_t *eld = connector->eld; |
||
5198 | struct drm_device *dev = crtc->dev; |
||
5199 | uint32_t eldv; |
||
5200 | uint32_t i; |
||
5201 | int len; |
||
5202 | int pipe = to_intel_crtc(crtc)->pipe; |
||
5203 | int tmp; |
||
5204 | |||
5205 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
||
5206 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
||
5207 | int aud_config = HSW_AUD_CFG(pipe); |
||
5208 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
||
5209 | |||
5210 | |||
5211 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
||
5212 | |||
5213 | /* Audio output enable */ |
||
5214 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
||
5215 | tmp = I915_READ(aud_cntrl_st2); |
||
5216 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
||
5217 | I915_WRITE(aud_cntrl_st2, tmp); |
||
5218 | |||
5219 | /* Wait for 1 vertical blank */ |
||
5220 | intel_wait_for_vblank(dev, pipe); |
||
5221 | |||
5222 | /* Set ELD valid state */ |
||
5223 | tmp = I915_READ(aud_cntrl_st2); |
||
5224 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); |
||
5225 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
||
5226 | I915_WRITE(aud_cntrl_st2, tmp); |
||
5227 | tmp = I915_READ(aud_cntrl_st2); |
||
5228 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); |
||
5229 | |||
5230 | /* Enable HDMI mode */ |
||
5231 | tmp = I915_READ(aud_config); |
||
5232 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); |
||
5233 | /* clear N_programing_enable and N_value_index */ |
||
5234 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
||
5235 | I915_WRITE(aud_config, tmp); |
||
5236 | |||
5237 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
||
5238 | |||
5239 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
||
5240 | |||
5241 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
||
5242 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
||
5243 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
||
5244 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
||
5245 | } else |
||
5246 | I915_WRITE(aud_config, 0); |
||
5247 | |||
5248 | if (intel_eld_uptodate(connector, |
||
5249 | aud_cntrl_st2, eldv, |
||
5250 | aud_cntl_st, IBX_ELD_ADDRESS, |
||
5251 | hdmiw_hdmiedid)) |
||
5252 | return; |
||
5253 | |||
5254 | i = I915_READ(aud_cntrl_st2); |
||
5255 | i &= ~eldv; |
||
5256 | I915_WRITE(aud_cntrl_st2, i); |
||
5257 | |||
5258 | if (!eld[0]) |
||
5259 | return; |
||
5260 | |||
5261 | i = I915_READ(aud_cntl_st); |
||
5262 | i &= ~IBX_ELD_ADDRESS; |
||
5263 | I915_WRITE(aud_cntl_st, i); |
||
5264 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
||
5265 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
||
5266 | |||
5267 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
||
5268 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
||
5269 | for (i = 0; i < len; i++) |
||
5270 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
||
5271 | |||
5272 | i = I915_READ(aud_cntrl_st2); |
||
5273 | i |= eldv; |
||
5274 | I915_WRITE(aud_cntrl_st2, i); |
||
5275 | |||
5276 | } |
||
5277 | |||
2342 | Serge | 5278 | static void ironlake_write_eld(struct drm_connector *connector, |
5279 | struct drm_crtc *crtc) |
||
5280 | { |
||
5281 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
5282 | uint8_t *eld = connector->eld; |
||
5283 | uint32_t eldv; |
||
5284 | uint32_t i; |
||
5285 | int len; |
||
5286 | int hdmiw_hdmiedid; |
||
3031 | serge | 5287 | int aud_config; |
2342 | Serge | 5288 | int aud_cntl_st; |
5289 | int aud_cntrl_st2; |
||
3031 | serge | 5290 | int pipe = to_intel_crtc(crtc)->pipe; |
2342 | Serge | 5291 | |
5292 | if (HAS_PCH_IBX(connector->dev)) { |
||
3031 | serge | 5293 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
5294 | aud_config = IBX_AUD_CFG(pipe); |
||
5295 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
||
2342 | Serge | 5296 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
5297 | } else { |
||
3031 | serge | 5298 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
5299 | aud_config = CPT_AUD_CFG(pipe); |
||
5300 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
||
2342 | Serge | 5301 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
5302 | } |
||
5303 | |||
3031 | serge | 5304 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
2342 | Serge | 5305 | |
5306 | i = I915_READ(aud_cntl_st); |
||
3031 | serge | 5307 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
2342 | Serge | 5308 | if (!i) { |
5309 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
||
5310 | /* operate blindly on all ports */ |
||
5311 | eldv = IBX_ELD_VALIDB; |
||
5312 | eldv |= IBX_ELD_VALIDB << 4; |
||
5313 | eldv |= IBX_ELD_VALIDB << 8; |
||
5314 | } else { |
||
5315 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); |
||
5316 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
||
5317 | } |
||
5318 | |||
5319 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
||
5320 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
||
5321 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
||
3031 | serge | 5322 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5323 | } else |
||
5324 | I915_WRITE(aud_config, 0); |
||
2342 | Serge | 5325 | |
5326 | if (intel_eld_uptodate(connector, |
||
5327 | aud_cntrl_st2, eldv, |
||
5328 | aud_cntl_st, IBX_ELD_ADDRESS, |
||
5329 | hdmiw_hdmiedid)) |
||
5330 | return; |
||
5331 | |||
5332 | i = I915_READ(aud_cntrl_st2); |
||
5333 | i &= ~eldv; |
||
5334 | I915_WRITE(aud_cntrl_st2, i); |
||
5335 | |||
5336 | if (!eld[0]) |
||
5337 | return; |
||
5338 | |||
5339 | i = I915_READ(aud_cntl_st); |
||
5340 | i &= ~IBX_ELD_ADDRESS; |
||
5341 | I915_WRITE(aud_cntl_st, i); |
||
5342 | |||
5343 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
||
5344 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
||
5345 | for (i = 0; i < len; i++) |
||
5346 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
||
5347 | |||
5348 | i = I915_READ(aud_cntrl_st2); |
||
5349 | i |= eldv; |
||
5350 | I915_WRITE(aud_cntrl_st2, i); |
||
5351 | } |
||
5352 | |||
5353 | void intel_write_eld(struct drm_encoder *encoder, |
||
5354 | struct drm_display_mode *mode) |
||
5355 | { |
||
5356 | struct drm_crtc *crtc = encoder->crtc; |
||
5357 | struct drm_connector *connector; |
||
5358 | struct drm_device *dev = encoder->dev; |
||
5359 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5360 | |||
5361 | connector = drm_select_eld(encoder, mode); |
||
5362 | if (!connector) |
||
5363 | return; |
||
5364 | |||
5365 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
||
5366 | connector->base.id, |
||
5367 | drm_get_connector_name(connector), |
||
5368 | connector->encoder->base.id, |
||
5369 | drm_get_encoder_name(connector->encoder)); |
||
5370 | |||
5371 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
||
5372 | |||
5373 | if (dev_priv->display.write_eld) |
||
5374 | dev_priv->display.write_eld(connector, crtc); |
||
5375 | } |
||
5376 | |||
2327 | Serge | 5377 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5378 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
||
5379 | { |
||
5380 | struct drm_device *dev = crtc->dev; |
||
5381 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5382 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5383 | int palreg = PALETTE(intel_crtc->pipe); |
||
5384 | int i; |
||
5385 | |||
5386 | /* The clocks have to be on to load the palette. */ |
||
3031 | serge | 5387 | if (!crtc->enabled || !intel_crtc->active) |
2327 | Serge | 5388 | return; |
5389 | |||
5390 | /* use legacy palette for Ironlake */ |
||
5391 | if (HAS_PCH_SPLIT(dev)) |
||
5392 | palreg = LGC_PALETTE(intel_crtc->pipe); |
||
5393 | |||
5394 | for (i = 0; i < 256; i++) { |
||
5395 | I915_WRITE(palreg + 4 * i, |
||
5396 | (intel_crtc->lut_r[i] << 16) | |
||
5397 | (intel_crtc->lut_g[i] << 8) | |
||
5398 | intel_crtc->lut_b[i]); |
||
5399 | } |
||
5400 | } |
||
5401 | |||
3031 | serge | 5402 | #if 0 |
5403 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
||
5404 | { |
||
5405 | struct drm_device *dev = crtc->dev; |
||
5406 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5407 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5408 | bool visible = base != 0; |
||
5409 | u32 cntl; |
||
2327 | Serge | 5410 | |
3031 | serge | 5411 | if (intel_crtc->cursor_visible == visible) |
5412 | return; |
||
2327 | Serge | 5413 | |
3031 | serge | 5414 | cntl = I915_READ(_CURACNTR); |
5415 | if (visible) { |
||
5416 | /* On these chipsets we can only modify the base whilst |
||
5417 | * the cursor is disabled. |
||
5418 | */ |
||
5419 | I915_WRITE(_CURABASE, base); |
||
2327 | Serge | 5420 | |
3031 | serge | 5421 | cntl &= ~(CURSOR_FORMAT_MASK); |
5422 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
||
5423 | cntl |= CURSOR_ENABLE | |
||
5424 | CURSOR_GAMMA_ENABLE | |
||
5425 | CURSOR_FORMAT_ARGB; |
||
5426 | } else |
||
5427 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
||
5428 | I915_WRITE(_CURACNTR, cntl); |
||
2327 | Serge | 5429 | |
3031 | serge | 5430 | intel_crtc->cursor_visible = visible; |
5431 | } |
||
2327 | Serge | 5432 | |
3031 | serge | 5433 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
5434 | { |
||
5435 | struct drm_device *dev = crtc->dev; |
||
5436 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5437 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5438 | int pipe = intel_crtc->pipe; |
||
5439 | bool visible = base != 0; |
||
2327 | Serge | 5440 | |
3031 | serge | 5441 | if (intel_crtc->cursor_visible != visible) { |
5442 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
||
5443 | if (base) { |
||
5444 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
||
5445 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
||
5446 | cntl |= pipe << 28; /* Connect to correct pipe */ |
||
5447 | } else { |
||
5448 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
||
5449 | cntl |= CURSOR_MODE_DISABLE; |
||
5450 | } |
||
5451 | I915_WRITE(CURCNTR(pipe), cntl); |
||
2327 | Serge | 5452 | |
3031 | serge | 5453 | intel_crtc->cursor_visible = visible; |
5454 | } |
||
5455 | /* and commit changes on next vblank */ |
||
5456 | I915_WRITE(CURBASE(pipe), base); |
||
5457 | } |
||
2327 | Serge | 5458 | |
3031 | serge | 5459 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
5460 | { |
||
5461 | struct drm_device *dev = crtc->dev; |
||
5462 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5463 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5464 | int pipe = intel_crtc->pipe; |
||
5465 | bool visible = base != 0; |
||
2327 | Serge | 5466 | |
3031 | serge | 5467 | if (intel_crtc->cursor_visible != visible) { |
5468 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
||
5469 | if (base) { |
||
5470 | cntl &= ~CURSOR_MODE; |
||
5471 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
||
5472 | } else { |
||
5473 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
||
5474 | cntl |= CURSOR_MODE_DISABLE; |
||
5475 | } |
||
5476 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
||
2327 | Serge | 5477 | |
3031 | serge | 5478 | intel_crtc->cursor_visible = visible; |
5479 | } |
||
5480 | /* and commit changes on next vblank */ |
||
5481 | I915_WRITE(CURBASE_IVB(pipe), base); |
||
5482 | } |
||
2327 | Serge | 5483 | |
3031 | serge | 5484 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
5485 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
||
5486 | bool on) |
||
5487 | { |
||
5488 | struct drm_device *dev = crtc->dev; |
||
5489 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5491 | int pipe = intel_crtc->pipe; |
||
5492 | int x = intel_crtc->cursor_x; |
||
5493 | int y = intel_crtc->cursor_y; |
||
5494 | u32 base, pos; |
||
5495 | bool visible; |
||
2327 | Serge | 5496 | |
3031 | serge | 5497 | pos = 0; |
2327 | Serge | 5498 | |
3031 | serge | 5499 | if (on && crtc->enabled && crtc->fb) { |
5500 | base = intel_crtc->cursor_addr; |
||
5501 | if (x > (int) crtc->fb->width) |
||
5502 | base = 0; |
||
2327 | Serge | 5503 | |
3031 | serge | 5504 | if (y > (int) crtc->fb->height) |
5505 | base = 0; |
||
5506 | } else |
||
5507 | base = 0; |
||
2327 | Serge | 5508 | |
3031 | serge | 5509 | if (x < 0) { |
5510 | if (x + intel_crtc->cursor_width < 0) |
||
5511 | base = 0; |
||
2327 | Serge | 5512 | |
3031 | serge | 5513 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
5514 | x = -x; |
||
5515 | } |
||
5516 | pos |= x << CURSOR_X_SHIFT; |
||
2327 | Serge | 5517 | |
3031 | serge | 5518 | if (y < 0) { |
5519 | if (y + intel_crtc->cursor_height < 0) |
||
5520 | base = 0; |
||
2327 | Serge | 5521 | |
3031 | serge | 5522 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
5523 | y = -y; |
||
5524 | } |
||
5525 | pos |= y << CURSOR_Y_SHIFT; |
||
2327 | Serge | 5526 | |
3031 | serge | 5527 | visible = base != 0; |
5528 | if (!visible && !intel_crtc->cursor_visible) |
||
5529 | return; |
||
2327 | Serge | 5530 | |
3031 | serge | 5531 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
5532 | I915_WRITE(CURPOS_IVB(pipe), pos); |
||
5533 | ivb_update_cursor(crtc, base); |
||
5534 | } else { |
||
5535 | I915_WRITE(CURPOS(pipe), pos); |
||
5536 | if (IS_845G(dev) || IS_I865G(dev)) |
||
5537 | i845_update_cursor(crtc, base); |
||
5538 | else |
||
5539 | i9xx_update_cursor(crtc, base); |
||
5540 | } |
||
5541 | } |
||
2327 | Serge | 5542 | |
3031 | serge | 5543 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
5544 | struct drm_file *file, |
||
5545 | uint32_t handle, |
||
5546 | uint32_t width, uint32_t height) |
||
5547 | { |
||
5548 | struct drm_device *dev = crtc->dev; |
||
5549 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5551 | struct drm_i915_gem_object *obj; |
||
5552 | uint32_t addr; |
||
5553 | int ret; |
||
2327 | Serge | 5554 | |
3031 | serge | 5555 | /* if we want to turn off the cursor ignore width and height */ |
5556 | if (!handle) { |
||
5557 | DRM_DEBUG_KMS("cursor off\n"); |
||
5558 | addr = 0; |
||
5559 | obj = NULL; |
||
5560 | mutex_lock(&dev->struct_mutex); |
||
5561 | goto finish; |
||
5562 | } |
||
2327 | Serge | 5563 | |
3031 | serge | 5564 | /* Currently we only support 64x64 cursors */ |
5565 | if (width != 64 || height != 64) { |
||
5566 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
||
5567 | return -EINVAL; |
||
5568 | } |
||
2327 | Serge | 5569 | |
3031 | serge | 5570 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
5571 | if (&obj->base == NULL) |
||
5572 | return -ENOENT; |
||
2327 | Serge | 5573 | |
3031 | serge | 5574 | if (obj->base.size < width * height * 4) { |
5575 | DRM_ERROR("buffer is to small\n"); |
||
5576 | ret = -ENOMEM; |
||
5577 | goto fail; |
||
5578 | } |
||
2327 | Serge | 5579 | |
3031 | serge | 5580 | /* we only need to pin inside GTT if cursor is non-phy */ |
5581 | mutex_lock(&dev->struct_mutex); |
||
5582 | if (!dev_priv->info->cursor_needs_physical) { |
||
5583 | if (obj->tiling_mode) { |
||
5584 | DRM_ERROR("cursor cannot be tiled\n"); |
||
5585 | ret = -EINVAL; |
||
5586 | goto fail_locked; |
||
5587 | } |
||
2327 | Serge | 5588 | |
3031 | serge | 5589 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
5590 | if (ret) { |
||
5591 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
||
5592 | goto fail_locked; |
||
5593 | } |
||
2327 | Serge | 5594 | |
3031 | serge | 5595 | ret = i915_gem_object_put_fence(obj); |
5596 | if (ret) { |
||
5597 | DRM_ERROR("failed to release fence for cursor"); |
||
5598 | goto fail_unpin; |
||
5599 | } |
||
2327 | Serge | 5600 | |
3031 | serge | 5601 | addr = obj->gtt_offset; |
5602 | } else { |
||
5603 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
||
5604 | ret = i915_gem_attach_phys_object(dev, obj, |
||
5605 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
||
5606 | align); |
||
5607 | if (ret) { |
||
5608 | DRM_ERROR("failed to attach phys object\n"); |
||
5609 | goto fail_locked; |
||
5610 | } |
||
5611 | addr = obj->phys_obj->handle->busaddr; |
||
5612 | } |
||
2327 | Serge | 5613 | |
3031 | serge | 5614 | if (IS_GEN2(dev)) |
5615 | I915_WRITE(CURSIZE, (height << 12) | width); |
||
2327 | Serge | 5616 | |
3031 | serge | 5617 | finish: |
5618 | if (intel_crtc->cursor_bo) { |
||
5619 | if (dev_priv->info->cursor_needs_physical) { |
||
5620 | if (intel_crtc->cursor_bo != obj) |
||
5621 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
||
5622 | } else |
||
5623 | i915_gem_object_unpin(intel_crtc->cursor_bo); |
||
5624 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
||
5625 | } |
||
2327 | Serge | 5626 | |
3031 | serge | 5627 | mutex_unlock(&dev->struct_mutex); |
2327 | Serge | 5628 | |
3031 | serge | 5629 | intel_crtc->cursor_addr = addr; |
5630 | intel_crtc->cursor_bo = obj; |
||
5631 | intel_crtc->cursor_width = width; |
||
5632 | intel_crtc->cursor_height = height; |
||
2327 | Serge | 5633 | |
3031 | serge | 5634 | // intel_crtc_update_cursor(crtc, true); |
2327 | Serge | 5635 | |
3031 | serge | 5636 | return 0; |
5637 | fail_unpin: |
||
5638 | i915_gem_object_unpin(obj); |
||
5639 | fail_locked: |
||
5640 | mutex_unlock(&dev->struct_mutex); |
||
5641 | fail: |
||
5642 | drm_gem_object_unreference_unlocked(&obj->base); |
||
5643 | return ret; |
||
5644 | } |
||
2327 | Serge | 5645 | |
3031 | serge | 5646 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
5647 | { |
||
5648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5649 | |||
5650 | intel_crtc->cursor_x = x; |
||
5651 | intel_crtc->cursor_y = y; |
||
5652 | |||
5653 | // intel_crtc_update_cursor(crtc, true); |
||
5654 | |||
5655 | return 0; |
||
5656 | } |
||
5657 | #endif |
||
5658 | |||
2332 | Serge | 5659 | /** Sets the color ramps on behalf of RandR */ |
5660 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
||
5661 | u16 blue, int regno) |
||
5662 | { |
||
5663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2327 | Serge | 5664 | |
2332 | Serge | 5665 | intel_crtc->lut_r[regno] = red >> 8; |
5666 | intel_crtc->lut_g[regno] = green >> 8; |
||
5667 | intel_crtc->lut_b[regno] = blue >> 8; |
||
5668 | } |
||
2327 | Serge | 5669 | |
2332 | Serge | 5670 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
5671 | u16 *blue, int regno) |
||
5672 | { |
||
5673 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2327 | Serge | 5674 | |
2332 | Serge | 5675 | *red = intel_crtc->lut_r[regno] << 8; |
5676 | *green = intel_crtc->lut_g[regno] << 8; |
||
5677 | *blue = intel_crtc->lut_b[regno] << 8; |
||
5678 | } |
||
2327 | Serge | 5679 | |
2330 | Serge | 5680 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
5681 | u16 *blue, uint32_t start, uint32_t size) |
||
5682 | { |
||
5683 | int end = (start + size > 256) ? 256 : start + size, i; |
||
5684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2327 | Serge | 5685 | |
2330 | Serge | 5686 | for (i = start; i < end; i++) { |
5687 | intel_crtc->lut_r[i] = red[i] >> 8; |
||
5688 | intel_crtc->lut_g[i] = green[i] >> 8; |
||
5689 | intel_crtc->lut_b[i] = blue[i] >> 8; |
||
5690 | } |
||
2327 | Serge | 5691 | |
2330 | Serge | 5692 | intel_crtc_load_lut(crtc); |
5693 | } |
||
2327 | Serge | 5694 | |
2330 | Serge | 5695 | /** |
5696 | * Get a pipe with a simple mode set on it for doing load-based monitor |
||
5697 | * detection. |
||
5698 | * |
||
5699 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
||
5700 | * its requirements. The pipe will be connected to no other encoders. |
||
5701 | * |
||
5702 | * Currently this code will only succeed if there is a pipe with no encoders |
||
5703 | * configured for it. In the future, it could choose to temporarily disable |
||
5704 | * some outputs to free up a pipe for its use. |
||
5705 | * |
||
5706 | * \return crtc, or NULL if no pipes are available. |
||
5707 | */ |
||
2327 | Serge | 5708 | |
2330 | Serge | 5709 | /* VESA 640x480x72Hz mode to set on the pipe */ |
5710 | static struct drm_display_mode load_detect_mode = { |
||
5711 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
||
5712 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
||
5713 | }; |
||
2327 | Serge | 5714 | |
3031 | serge | 5715 | static struct drm_framebuffer * |
5716 | intel_framebuffer_create(struct drm_device *dev, |
||
5717 | struct drm_mode_fb_cmd2 *mode_cmd, |
||
5718 | struct drm_i915_gem_object *obj) |
||
5719 | { |
||
5720 | struct intel_framebuffer *intel_fb; |
||
5721 | int ret; |
||
2327 | Serge | 5722 | |
3031 | serge | 5723 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
5724 | if (!intel_fb) { |
||
5725 | drm_gem_object_unreference_unlocked(&obj->base); |
||
5726 | return ERR_PTR(-ENOMEM); |
||
5727 | } |
||
2327 | Serge | 5728 | |
3031 | serge | 5729 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
5730 | if (ret) { |
||
5731 | drm_gem_object_unreference_unlocked(&obj->base); |
||
5732 | kfree(intel_fb); |
||
5733 | return ERR_PTR(ret); |
||
5734 | } |
||
2327 | Serge | 5735 | |
3031 | serge | 5736 | return &intel_fb->base; |
5737 | } |
||
2327 | Serge | 5738 | |
2330 | Serge | 5739 | static u32 |
5740 | intel_framebuffer_pitch_for_width(int width, int bpp) |
||
5741 | { |
||
5742 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
||
5743 | return ALIGN(pitch, 64); |
||
5744 | } |
||
2327 | Serge | 5745 | |
2330 | Serge | 5746 | static u32 |
5747 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
||
5748 | { |
||
5749 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
||
5750 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
||
5751 | } |
||
2327 | Serge | 5752 | |
2330 | Serge | 5753 | static struct drm_framebuffer * |
5754 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
||
5755 | struct drm_display_mode *mode, |
||
5756 | int depth, int bpp) |
||
5757 | { |
||
5758 | struct drm_i915_gem_object *obj; |
||
2344 | Serge | 5759 | struct drm_mode_fb_cmd2 mode_cmd; |
2327 | Serge | 5760 | |
2330 | Serge | 5761 | // obj = i915_gem_alloc_object(dev, |
5762 | // intel_framebuffer_size_for_mode(mode, bpp)); |
||
5763 | // if (obj == NULL) |
||
5764 | return ERR_PTR(-ENOMEM); |
||
2327 | Serge | 5765 | |
2330 | Serge | 5766 | // mode_cmd.width = mode->hdisplay; |
5767 | // mode_cmd.height = mode->vdisplay; |
||
5768 | // mode_cmd.depth = depth; |
||
5769 | // mode_cmd.bpp = bpp; |
||
5770 | // mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp); |
||
2327 | Serge | 5771 | |
2330 | Serge | 5772 | // return intel_framebuffer_create(dev, &mode_cmd, obj); |
5773 | } |
||
2327 | Serge | 5774 | |
2330 | Serge | 5775 | static struct drm_framebuffer * |
5776 | mode_fits_in_fbdev(struct drm_device *dev, |
||
5777 | struct drm_display_mode *mode) |
||
5778 | { |
||
5779 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5780 | struct drm_i915_gem_object *obj; |
||
5781 | struct drm_framebuffer *fb; |
||
2327 | Serge | 5782 | |
2330 | Serge | 5783 | // if (dev_priv->fbdev == NULL) |
5784 | // return NULL; |
||
2327 | Serge | 5785 | |
2330 | Serge | 5786 | // obj = dev_priv->fbdev->ifb.obj; |
5787 | // if (obj == NULL) |
||
5788 | return NULL; |
||
2327 | Serge | 5789 | |
2330 | Serge | 5790 | // if (obj->base.size < mode->vdisplay * fb->pitch) |
3031 | serge | 5791 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
5792 | fb->bits_per_pixel)) |
||
2330 | Serge | 5793 | // return NULL; |
2327 | Serge | 5794 | |
3031 | serge | 5795 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
5796 | return NULL; |
||
5797 | |||
2330 | Serge | 5798 | // return fb; |
5799 | } |
||
2327 | Serge | 5800 | |
3031 | serge | 5801 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
2330 | Serge | 5802 | struct drm_display_mode *mode, |
5803 | struct intel_load_detect_pipe *old) |
||
5804 | { |
||
5805 | struct intel_crtc *intel_crtc; |
||
3031 | serge | 5806 | struct intel_encoder *intel_encoder = |
5807 | intel_attached_encoder(connector); |
||
2330 | Serge | 5808 | struct drm_crtc *possible_crtc; |
5809 | struct drm_encoder *encoder = &intel_encoder->base; |
||
5810 | struct drm_crtc *crtc = NULL; |
||
5811 | struct drm_device *dev = encoder->dev; |
||
3031 | serge | 5812 | struct drm_framebuffer *fb; |
2330 | Serge | 5813 | int i = -1; |
2327 | Serge | 5814 | |
2330 | Serge | 5815 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5816 | connector->base.id, drm_get_connector_name(connector), |
||
5817 | encoder->base.id, drm_get_encoder_name(encoder)); |
||
2327 | Serge | 5818 | |
2330 | Serge | 5819 | /* |
5820 | * Algorithm gets a little messy: |
||
5821 | * |
||
5822 | * - if the connector already has an assigned crtc, use it (but make |
||
5823 | * sure it's on first) |
||
5824 | * |
||
5825 | * - try to find the first unused crtc that can drive this connector, |
||
5826 | * and use that if we find one |
||
5827 | */ |
||
2327 | Serge | 5828 | |
2330 | Serge | 5829 | /* See if we already have a CRTC for this connector */ |
5830 | if (encoder->crtc) { |
||
5831 | crtc = encoder->crtc; |
||
2327 | Serge | 5832 | |
3031 | serge | 5833 | old->dpms_mode = connector->dpms; |
2330 | Serge | 5834 | old->load_detect_temp = false; |
2327 | Serge | 5835 | |
2330 | Serge | 5836 | /* Make sure the crtc and connector are running */ |
3031 | serge | 5837 | if (connector->dpms != DRM_MODE_DPMS_ON) |
5838 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
||
2327 | Serge | 5839 | |
2330 | Serge | 5840 | return true; |
5841 | } |
||
2327 | Serge | 5842 | |
2330 | Serge | 5843 | /* Find an unused one (if possible) */ |
5844 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
||
5845 | i++; |
||
5846 | if (!(encoder->possible_crtcs & (1 << i))) |
||
5847 | continue; |
||
5848 | if (!possible_crtc->enabled) { |
||
5849 | crtc = possible_crtc; |
||
5850 | break; |
||
5851 | } |
||
5852 | } |
||
2327 | Serge | 5853 | |
2330 | Serge | 5854 | /* |
5855 | * If we didn't find an unused CRTC, don't use any. |
||
5856 | */ |
||
5857 | if (!crtc) { |
||
5858 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
||
5859 | return false; |
||
5860 | } |
||
2327 | Serge | 5861 | |
3031 | serge | 5862 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
5863 | to_intel_connector(connector)->new_encoder = intel_encoder; |
||
2327 | Serge | 5864 | |
2330 | Serge | 5865 | intel_crtc = to_intel_crtc(crtc); |
3031 | serge | 5866 | old->dpms_mode = connector->dpms; |
2330 | Serge | 5867 | old->load_detect_temp = true; |
5868 | old->release_fb = NULL; |
||
2327 | Serge | 5869 | |
2330 | Serge | 5870 | if (!mode) |
5871 | mode = &load_detect_mode; |
||
2327 | Serge | 5872 | |
2330 | Serge | 5873 | /* We need a framebuffer large enough to accommodate all accesses |
5874 | * that the plane may generate whilst we perform load detection. |
||
5875 | * We can not rely on the fbcon either being present (we get called |
||
5876 | * during its initialisation to detect all boot displays, or it may |
||
5877 | * not even exist) or that it is large enough to satisfy the |
||
5878 | * requested mode. |
||
5879 | */ |
||
3031 | serge | 5880 | fb = mode_fits_in_fbdev(dev, mode); |
5881 | if (fb == NULL) { |
||
2330 | Serge | 5882 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
3031 | serge | 5883 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
5884 | old->release_fb = fb; |
||
2330 | Serge | 5885 | } else |
5886 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
||
3031 | serge | 5887 | if (IS_ERR(fb)) { |
2330 | Serge | 5888 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
3031 | serge | 5889 | goto fail; |
2330 | Serge | 5890 | } |
2327 | Serge | 5891 | |
3031 | serge | 5892 | if (!intel_set_mode(crtc, mode, 0, 0, fb)) { |
2330 | Serge | 5893 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
5894 | if (old->release_fb) |
||
5895 | old->release_fb->funcs->destroy(old->release_fb); |
||
3031 | serge | 5896 | goto fail; |
2330 | Serge | 5897 | } |
2327 | Serge | 5898 | |
2330 | Serge | 5899 | /* let the connector get through one full cycle before testing */ |
5900 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
2327 | Serge | 5901 | |
2330 | Serge | 5902 | return true; |
3031 | serge | 5903 | fail: |
5904 | connector->encoder = NULL; |
||
5905 | encoder->crtc = NULL; |
||
5906 | return false; |
||
2330 | Serge | 5907 | } |
2327 | Serge | 5908 | |
3031 | serge | 5909 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
2330 | Serge | 5910 | struct intel_load_detect_pipe *old) |
5911 | { |
||
3031 | serge | 5912 | struct intel_encoder *intel_encoder = |
5913 | intel_attached_encoder(connector); |
||
2330 | Serge | 5914 | struct drm_encoder *encoder = &intel_encoder->base; |
2327 | Serge | 5915 | |
2330 | Serge | 5916 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5917 | connector->base.id, drm_get_connector_name(connector), |
||
5918 | encoder->base.id, drm_get_encoder_name(encoder)); |
||
2327 | Serge | 5919 | |
2330 | Serge | 5920 | if (old->load_detect_temp) { |
3031 | serge | 5921 | struct drm_crtc *crtc = encoder->crtc; |
2327 | Serge | 5922 | |
3031 | serge | 5923 | to_intel_connector(connector)->new_encoder = NULL; |
5924 | intel_encoder->new_crtc = NULL; |
||
5925 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
||
5926 | |||
2330 | Serge | 5927 | if (old->release_fb) |
5928 | old->release_fb->funcs->destroy(old->release_fb); |
||
2327 | Serge | 5929 | |
2330 | Serge | 5930 | return; |
5931 | } |
||
2327 | Serge | 5932 | |
2330 | Serge | 5933 | /* Switch crtc and encoder back off if necessary */ |
3031 | serge | 5934 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
5935 | connector->funcs->dpms(connector, old->dpms_mode); |
||
2330 | Serge | 5936 | } |
2327 | Serge | 5937 | |
2330 | Serge | 5938 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
5939 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
||
5940 | { |
||
5941 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
5943 | int pipe = intel_crtc->pipe; |
||
5944 | u32 dpll = I915_READ(DPLL(pipe)); |
||
5945 | u32 fp; |
||
5946 | intel_clock_t clock; |
||
2327 | Serge | 5947 | |
2330 | Serge | 5948 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
5949 | fp = I915_READ(FP0(pipe)); |
||
5950 | else |
||
5951 | fp = I915_READ(FP1(pipe)); |
||
2327 | Serge | 5952 | |
2330 | Serge | 5953 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
5954 | if (IS_PINEVIEW(dev)) { |
||
5955 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
||
5956 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
||
5957 | } else { |
||
5958 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
||
5959 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
||
5960 | } |
||
2327 | Serge | 5961 | |
2330 | Serge | 5962 | if (!IS_GEN2(dev)) { |
5963 | if (IS_PINEVIEW(dev)) |
||
5964 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
||
5965 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
||
5966 | else |
||
5967 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
||
5968 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
||
2327 | Serge | 5969 | |
2330 | Serge | 5970 | switch (dpll & DPLL_MODE_MASK) { |
5971 | case DPLLB_MODE_DAC_SERIAL: |
||
5972 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
||
5973 | 5 : 10; |
||
5974 | break; |
||
5975 | case DPLLB_MODE_LVDS: |
||
5976 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
||
5977 | 7 : 14; |
||
5978 | break; |
||
5979 | default: |
||
5980 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
||
5981 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
||
5982 | return 0; |
||
5983 | } |
||
2327 | Serge | 5984 | |
2330 | Serge | 5985 | /* XXX: Handle the 100Mhz refclk */ |
5986 | intel_clock(dev, 96000, &clock); |
||
5987 | } else { |
||
5988 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
||
2327 | Serge | 5989 | |
2330 | Serge | 5990 | if (is_lvds) { |
5991 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
||
5992 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
||
5993 | clock.p2 = 14; |
||
2327 | Serge | 5994 | |
2330 | Serge | 5995 | if ((dpll & PLL_REF_INPUT_MASK) == |
5996 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
||
5997 | /* XXX: might not be 66MHz */ |
||
5998 | intel_clock(dev, 66000, &clock); |
||
5999 | } else |
||
6000 | intel_clock(dev, 48000, &clock); |
||
6001 | } else { |
||
6002 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
||
6003 | clock.p1 = 2; |
||
6004 | else { |
||
6005 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
||
6006 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
||
6007 | } |
||
6008 | if (dpll & PLL_P2_DIVIDE_BY_4) |
||
6009 | clock.p2 = 4; |
||
6010 | else |
||
6011 | clock.p2 = 2; |
||
2327 | Serge | 6012 | |
2330 | Serge | 6013 | intel_clock(dev, 48000, &clock); |
6014 | } |
||
6015 | } |
||
2327 | Serge | 6016 | |
2330 | Serge | 6017 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
6018 | * i830PllIsValid() because it relies on the xf86_config connector |
||
6019 | * configuration being accurate, which it isn't necessarily. |
||
6020 | */ |
||
2327 | Serge | 6021 | |
2330 | Serge | 6022 | return clock.dot; |
6023 | } |
||
2327 | Serge | 6024 | |
2330 | Serge | 6025 | /** Returns the currently programmed mode of the given pipe. */ |
6026 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
||
6027 | struct drm_crtc *crtc) |
||
6028 | { |
||
6029 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6031 | int pipe = intel_crtc->pipe; |
||
6032 | struct drm_display_mode *mode; |
||
6033 | int htot = I915_READ(HTOTAL(pipe)); |
||
6034 | int hsync = I915_READ(HSYNC(pipe)); |
||
6035 | int vtot = I915_READ(VTOTAL(pipe)); |
||
6036 | int vsync = I915_READ(VSYNC(pipe)); |
||
2327 | Serge | 6037 | |
2330 | Serge | 6038 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
6039 | if (!mode) |
||
6040 | return NULL; |
||
6041 | |||
6042 | mode->clock = intel_crtc_clock_get(dev, crtc); |
||
6043 | mode->hdisplay = (htot & 0xffff) + 1; |
||
6044 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
||
6045 | mode->hsync_start = (hsync & 0xffff) + 1; |
||
6046 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
||
6047 | mode->vdisplay = (vtot & 0xffff) + 1; |
||
6048 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
||
6049 | mode->vsync_start = (vsync & 0xffff) + 1; |
||
6050 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
||
6051 | |||
6052 | drm_mode_set_name(mode); |
||
6053 | |||
6054 | return mode; |
||
6055 | } |
||
6056 | |||
2327 | Serge | 6057 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
6058 | { |
||
6059 | struct drm_device *dev = crtc->dev; |
||
6060 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
6061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6062 | int pipe = intel_crtc->pipe; |
||
6063 | int dpll_reg = DPLL(pipe); |
||
6064 | int dpll; |
||
6065 | |||
6066 | if (HAS_PCH_SPLIT(dev)) |
||
6067 | return; |
||
6068 | |||
6069 | if (!dev_priv->lvds_downclock_avail) |
||
6070 | return; |
||
6071 | |||
6072 | dpll = I915_READ(dpll_reg); |
||
6073 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
||
6074 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
||
6075 | |||
3031 | serge | 6076 | assert_panel_unlocked(dev_priv, pipe); |
2327 | Serge | 6077 | |
6078 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
||
6079 | I915_WRITE(dpll_reg, dpll); |
||
6080 | intel_wait_for_vblank(dev, pipe); |
||
6081 | |||
6082 | dpll = I915_READ(dpll_reg); |
||
6083 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
||
6084 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
||
6085 | } |
||
6086 | } |
||
6087 | |||
3031 | serge | 6088 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
6089 | { |
||
6090 | struct drm_device *dev = crtc->dev; |
||
6091 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
6092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2327 | Serge | 6093 | |
3031 | serge | 6094 | if (HAS_PCH_SPLIT(dev)) |
6095 | return; |
||
2327 | Serge | 6096 | |
3031 | serge | 6097 | if (!dev_priv->lvds_downclock_avail) |
6098 | return; |
||
2327 | Serge | 6099 | |
3031 | serge | 6100 | /* |
6101 | * Since this is called by a timer, we should never get here in |
||
6102 | * the manual case. |
||
6103 | */ |
||
6104 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
||
6105 | int pipe = intel_crtc->pipe; |
||
6106 | int dpll_reg = DPLL(pipe); |
||
6107 | int dpll; |
||
2327 | Serge | 6108 | |
3031 | serge | 6109 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
2327 | Serge | 6110 | |
3031 | serge | 6111 | assert_panel_unlocked(dev_priv, pipe); |
2327 | Serge | 6112 | |
3031 | serge | 6113 | dpll = I915_READ(dpll_reg); |
6114 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
||
6115 | I915_WRITE(dpll_reg, dpll); |
||
6116 | intel_wait_for_vblank(dev, pipe); |
||
6117 | dpll = I915_READ(dpll_reg); |
||
6118 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
||
6119 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
||
6120 | } |
||
2327 | Serge | 6121 | |
3031 | serge | 6122 | } |
2327 | Serge | 6123 | |
3031 | serge | 6124 | void intel_mark_busy(struct drm_device *dev) |
6125 | { |
||
6126 | i915_update_gfx_val(dev->dev_private); |
||
6127 | } |
||
2327 | Serge | 6128 | |
3031 | serge | 6129 | void intel_mark_idle(struct drm_device *dev) |
6130 | { |
||
6131 | } |
||
2327 | Serge | 6132 | |
3031 | serge | 6133 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) |
6134 | { |
||
6135 | struct drm_device *dev = obj->base.dev; |
||
6136 | struct drm_crtc *crtc; |
||
2327 | Serge | 6137 | |
3031 | serge | 6138 | if (!i915_powersave) |
6139 | return; |
||
2327 | Serge | 6140 | |
3031 | serge | 6141 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6142 | if (!crtc->fb) |
||
6143 | continue; |
||
2327 | Serge | 6144 | |
3031 | serge | 6145 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6146 | intel_increase_pllclock(crtc); |
||
6147 | } |
||
6148 | } |
||
2327 | Serge | 6149 | |
3031 | serge | 6150 | void intel_mark_fb_idle(struct drm_i915_gem_object *obj) |
6151 | { |
||
6152 | struct drm_device *dev = obj->base.dev; |
||
6153 | struct drm_crtc *crtc; |
||
2327 | Serge | 6154 | |
3031 | serge | 6155 | if (!i915_powersave) |
6156 | return; |
||
2327 | Serge | 6157 | |
3031 | serge | 6158 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6159 | if (!crtc->fb) |
||
6160 | continue; |
||
2327 | Serge | 6161 | |
3031 | serge | 6162 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6163 | intel_decrease_pllclock(crtc); |
||
6164 | } |
||
6165 | } |
||
2327 | Serge | 6166 | |
2330 | Serge | 6167 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6168 | { |
||
6169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6170 | struct drm_device *dev = crtc->dev; |
||
6171 | struct intel_unpin_work *work; |
||
6172 | unsigned long flags; |
||
2327 | Serge | 6173 | |
2330 | Serge | 6174 | spin_lock_irqsave(&dev->event_lock, flags); |
6175 | work = intel_crtc->unpin_work; |
||
6176 | intel_crtc->unpin_work = NULL; |
||
6177 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
2327 | Serge | 6178 | |
2330 | Serge | 6179 | if (work) { |
6180 | // cancel_work_sync(&work->work); |
||
6181 | kfree(work); |
||
6182 | } |
||
2327 | Serge | 6183 | |
2330 | Serge | 6184 | drm_crtc_cleanup(crtc); |
2327 | Serge | 6185 | |
2330 | Serge | 6186 | kfree(intel_crtc); |
6187 | } |
||
2327 | Serge | 6188 | |
3031 | serge | 6189 | #if 0 |
6190 | static void intel_unpin_work_fn(struct work_struct *__work) |
||
6191 | { |
||
6192 | struct intel_unpin_work *work = |
||
6193 | container_of(__work, struct intel_unpin_work, work); |
||
2327 | Serge | 6194 | |
3031 | serge | 6195 | mutex_lock(&work->dev->struct_mutex); |
6196 | intel_unpin_fb_obj(work->old_fb_obj); |
||
6197 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
||
6198 | drm_gem_object_unreference(&work->old_fb_obj->base); |
||
2327 | Serge | 6199 | |
3031 | serge | 6200 | intel_update_fbc(work->dev); |
6201 | mutex_unlock(&work->dev->struct_mutex); |
||
6202 | kfree(work); |
||
6203 | } |
||
2327 | Serge | 6204 | |
3031 | serge | 6205 | static void do_intel_finish_page_flip(struct drm_device *dev, |
6206 | struct drm_crtc *crtc) |
||
6207 | { |
||
6208 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
6209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6210 | struct intel_unpin_work *work; |
||
6211 | struct drm_i915_gem_object *obj; |
||
6212 | struct drm_pending_vblank_event *e; |
||
6213 | struct timeval tvbl; |
||
6214 | unsigned long flags; |
||
2327 | Serge | 6215 | |
3031 | serge | 6216 | /* Ignore early vblank irqs */ |
6217 | if (intel_crtc == NULL) |
||
6218 | return; |
||
2327 | Serge | 6219 | |
3031 | serge | 6220 | spin_lock_irqsave(&dev->event_lock, flags); |
6221 | work = intel_crtc->unpin_work; |
||
6222 | if (work == NULL || !work->pending) { |
||
6223 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
6224 | return; |
||
6225 | } |
||
2327 | Serge | 6226 | |
3031 | serge | 6227 | intel_crtc->unpin_work = NULL; |
2327 | Serge | 6228 | |
3031 | serge | 6229 | if (work->event) { |
6230 | e = work->event; |
||
6231 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
||
2327 | Serge | 6232 | |
3031 | serge | 6233 | e->event.tv_sec = tvbl.tv_sec; |
6234 | e->event.tv_usec = tvbl.tv_usec; |
||
2327 | Serge | 6235 | |
3031 | serge | 6236 | list_add_tail(&e->base.link, |
6237 | &e->base.file_priv->event_list); |
||
6238 | wake_up_interruptible(&e->base.file_priv->event_wait); |
||
6239 | } |
||
2327 | Serge | 6240 | |
3031 | serge | 6241 | drm_vblank_put(dev, intel_crtc->pipe); |
2327 | Serge | 6242 | |
3031 | serge | 6243 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2327 | Serge | 6244 | |
3031 | serge | 6245 | obj = work->old_fb_obj; |
2327 | Serge | 6246 | |
3031 | serge | 6247 | atomic_clear_mask(1 << intel_crtc->plane, |
6248 | &obj->pending_flip.counter); |
||
2327 | Serge | 6249 | |
3031 | serge | 6250 | wake_up(&dev_priv->pending_flip_queue); |
6251 | schedule_work(&work->work); |
||
2327 | Serge | 6252 | |
3031 | serge | 6253 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
6254 | } |
||
2327 | Serge | 6255 | |
3031 | serge | 6256 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6257 | { |
||
6258 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
6259 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
||
2327 | Serge | 6260 | |
3031 | serge | 6261 | do_intel_finish_page_flip(dev, crtc); |
6262 | } |
||
2327 | Serge | 6263 | |
3031 | serge | 6264 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
6265 | { |
||
6266 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
6267 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
||
2327 | Serge | 6268 | |
3031 | serge | 6269 | do_intel_finish_page_flip(dev, crtc); |
6270 | } |
||
2327 | Serge | 6271 | |
3031 | serge | 6272 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6273 | { |
||
6274 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
6275 | struct intel_crtc *intel_crtc = |
||
6276 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
||
6277 | unsigned long flags; |
||
2327 | Serge | 6278 | |
3031 | serge | 6279 | spin_lock_irqsave(&dev->event_lock, flags); |
6280 | if (intel_crtc->unpin_work) { |
||
6281 | if ((++intel_crtc->unpin_work->pending) > 1) |
||
6282 | DRM_ERROR("Prepared flip multiple times\n"); |
||
6283 | } else { |
||
6284 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); |
||
6285 | } |
||
6286 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
6287 | } |
||
2327 | Serge | 6288 | |
3031 | serge | 6289 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6290 | struct drm_crtc *crtc, |
||
6291 | struct drm_framebuffer *fb, |
||
6292 | struct drm_i915_gem_object *obj) |
||
6293 | { |
||
6294 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6295 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6296 | u32 flip_mask; |
||
6297 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
6298 | int ret; |
||
2327 | Serge | 6299 | |
3031 | serge | 6300 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6301 | if (ret) |
||
6302 | goto err; |
||
2327 | Serge | 6303 | |
3031 | serge | 6304 | ret = intel_ring_begin(ring, 6); |
6305 | if (ret) |
||
6306 | goto err_unpin; |
||
2327 | Serge | 6307 | |
3031 | serge | 6308 | /* Can't queue multiple flips, so wait for the previous |
6309 | * one to finish before executing the next. |
||
6310 | */ |
||
6311 | if (intel_crtc->plane) |
||
6312 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
||
6313 | else |
||
6314 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
||
6315 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
||
6316 | intel_ring_emit(ring, MI_NOOP); |
||
6317 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
||
6318 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
||
6319 | intel_ring_emit(ring, fb->pitches[0]); |
||
6320 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
||
6321 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
||
6322 | intel_ring_advance(ring); |
||
6323 | return 0; |
||
2327 | Serge | 6324 | |
3031 | serge | 6325 | err_unpin: |
6326 | intel_unpin_fb_obj(obj); |
||
6327 | err: |
||
6328 | return ret; |
||
6329 | } |
||
2327 | Serge | 6330 | |
3031 | serge | 6331 | static int intel_gen3_queue_flip(struct drm_device *dev, |
6332 | struct drm_crtc *crtc, |
||
6333 | struct drm_framebuffer *fb, |
||
6334 | struct drm_i915_gem_object *obj) |
||
6335 | { |
||
6336 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6338 | u32 flip_mask; |
||
6339 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
6340 | int ret; |
||
2327 | Serge | 6341 | |
3031 | serge | 6342 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6343 | if (ret) |
||
6344 | goto err; |
||
2327 | Serge | 6345 | |
3031 | serge | 6346 | ret = intel_ring_begin(ring, 6); |
6347 | if (ret) |
||
6348 | goto err_unpin; |
||
2327 | Serge | 6349 | |
3031 | serge | 6350 | if (intel_crtc->plane) |
6351 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
||
6352 | else |
||
6353 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
||
6354 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
||
6355 | intel_ring_emit(ring, MI_NOOP); |
||
6356 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
||
6357 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
||
6358 | intel_ring_emit(ring, fb->pitches[0]); |
||
6359 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
||
6360 | intel_ring_emit(ring, MI_NOOP); |
||
2327 | Serge | 6361 | |
3031 | serge | 6362 | intel_ring_advance(ring); |
6363 | return 0; |
||
2327 | Serge | 6364 | |
3031 | serge | 6365 | err_unpin: |
6366 | intel_unpin_fb_obj(obj); |
||
6367 | err: |
||
6368 | return ret; |
||
6369 | } |
||
2327 | Serge | 6370 | |
3031 | serge | 6371 | static int intel_gen4_queue_flip(struct drm_device *dev, |
6372 | struct drm_crtc *crtc, |
||
6373 | struct drm_framebuffer *fb, |
||
6374 | struct drm_i915_gem_object *obj) |
||
6375 | { |
||
6376 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6377 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6378 | uint32_t pf, pipesrc; |
||
6379 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
6380 | int ret; |
||
2327 | Serge | 6381 | |
3031 | serge | 6382 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6383 | if (ret) |
||
6384 | goto err; |
||
2327 | Serge | 6385 | |
3031 | serge | 6386 | ret = intel_ring_begin(ring, 4); |
6387 | if (ret) |
||
6388 | goto err_unpin; |
||
2327 | Serge | 6389 | |
3031 | serge | 6390 | /* i965+ uses the linear or tiled offsets from the |
6391 | * Display Registers (which do not change across a page-flip) |
||
6392 | * so we need only reprogram the base address. |
||
6393 | */ |
||
6394 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
||
6395 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
||
6396 | intel_ring_emit(ring, fb->pitches[0]); |
||
6397 | intel_ring_emit(ring, |
||
6398 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | |
||
6399 | obj->tiling_mode); |
||
2327 | Serge | 6400 | |
3031 | serge | 6401 | /* XXX Enabling the panel-fitter across page-flip is so far |
6402 | * untested on non-native modes, so ignore it for now. |
||
6403 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
||
6404 | */ |
||
6405 | pf = 0; |
||
6406 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
||
6407 | intel_ring_emit(ring, pf | pipesrc); |
||
6408 | intel_ring_advance(ring); |
||
6409 | return 0; |
||
2327 | Serge | 6410 | |
3031 | serge | 6411 | err_unpin: |
6412 | intel_unpin_fb_obj(obj); |
||
6413 | err: |
||
6414 | return ret; |
||
6415 | } |
||
2327 | Serge | 6416 | |
3031 | serge | 6417 | static int intel_gen6_queue_flip(struct drm_device *dev, |
6418 | struct drm_crtc *crtc, |
||
6419 | struct drm_framebuffer *fb, |
||
6420 | struct drm_i915_gem_object *obj) |
||
6421 | { |
||
6422 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6424 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
6425 | uint32_t pf, pipesrc; |
||
6426 | int ret; |
||
2327 | Serge | 6427 | |
3031 | serge | 6428 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6429 | if (ret) |
||
6430 | goto err; |
||
2327 | Serge | 6431 | |
3031 | serge | 6432 | ret = intel_ring_begin(ring, 4); |
6433 | if (ret) |
||
6434 | goto err_unpin; |
||
2327 | Serge | 6435 | |
3031 | serge | 6436 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6437 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
||
6438 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
||
6439 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
||
2327 | Serge | 6440 | |
3031 | serge | 6441 | /* Contrary to the suggestions in the documentation, |
6442 | * "Enable Panel Fitter" does not seem to be required when page |
||
6443 | * flipping with a non-native mode, and worse causes a normal |
||
6444 | * modeset to fail. |
||
6445 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
||
6446 | */ |
||
6447 | pf = 0; |
||
6448 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
||
6449 | intel_ring_emit(ring, pf | pipesrc); |
||
6450 | intel_ring_advance(ring); |
||
6451 | return 0; |
||
2327 | Serge | 6452 | |
3031 | serge | 6453 | err_unpin: |
6454 | intel_unpin_fb_obj(obj); |
||
6455 | err: |
||
6456 | return ret; |
||
6457 | } |
||
2327 | Serge | 6458 | |
3031 | serge | 6459 | /* |
6460 | * On gen7 we currently use the blit ring because (in early silicon at least) |
||
6461 | * the render ring doesn't give us interrpts for page flip completion, which |
||
6462 | * means clients will hang after the first flip is queued. Fortunately the |
||
6463 | * blit ring generates interrupts properly, so use it instead. |
||
6464 | */ |
||
6465 | static int intel_gen7_queue_flip(struct drm_device *dev, |
||
6466 | struct drm_crtc *crtc, |
||
6467 | struct drm_framebuffer *fb, |
||
6468 | struct drm_i915_gem_object *obj) |
||
6469 | { |
||
6470 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6471 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6472 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
||
6473 | uint32_t plane_bit = 0; |
||
6474 | int ret; |
||
2327 | Serge | 6475 | |
3031 | serge | 6476 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6477 | if (ret) |
||
6478 | goto err; |
||
2327 | Serge | 6479 | |
3031 | serge | 6480 | switch(intel_crtc->plane) { |
6481 | case PLANE_A: |
||
6482 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
||
6483 | break; |
||
6484 | case PLANE_B: |
||
6485 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
||
6486 | break; |
||
6487 | case PLANE_C: |
||
6488 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
||
6489 | break; |
||
6490 | default: |
||
6491 | WARN_ONCE(1, "unknown plane in flip command\n"); |
||
6492 | ret = -ENODEV; |
||
6493 | goto err_unpin; |
||
6494 | } |
||
2327 | Serge | 6495 | |
3031 | serge | 6496 | ret = intel_ring_begin(ring, 4); |
6497 | if (ret) |
||
6498 | goto err_unpin; |
||
2327 | Serge | 6499 | |
3031 | serge | 6500 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
6501 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
||
6502 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
||
6503 | intel_ring_emit(ring, (MI_NOOP)); |
||
6504 | intel_ring_advance(ring); |
||
6505 | return 0; |
||
2327 | Serge | 6506 | |
3031 | serge | 6507 | err_unpin: |
6508 | intel_unpin_fb_obj(obj); |
||
6509 | err: |
||
6510 | return ret; |
||
6511 | } |
||
2327 | Serge | 6512 | |
3031 | serge | 6513 | static int intel_default_queue_flip(struct drm_device *dev, |
6514 | struct drm_crtc *crtc, |
||
6515 | struct drm_framebuffer *fb, |
||
6516 | struct drm_i915_gem_object *obj) |
||
6517 | { |
||
6518 | return -ENODEV; |
||
6519 | } |
||
2327 | Serge | 6520 | |
3031 | serge | 6521 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
6522 | struct drm_framebuffer *fb, |
||
6523 | struct drm_pending_vblank_event *event) |
||
6524 | { |
||
6525 | struct drm_device *dev = crtc->dev; |
||
6526 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6527 | struct intel_framebuffer *intel_fb; |
||
6528 | struct drm_i915_gem_object *obj; |
||
6529 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
6530 | struct intel_unpin_work *work; |
||
6531 | unsigned long flags; |
||
6532 | int ret; |
||
2327 | Serge | 6533 | |
3031 | serge | 6534 | /* Can't change pixel format via MI display flips. */ |
6535 | if (fb->pixel_format != crtc->fb->pixel_format) |
||
6536 | return -EINVAL; |
||
2327 | Serge | 6537 | |
3031 | serge | 6538 | /* |
6539 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
||
6540 | * Note that pitch changes could also affect these register. |
||
6541 | */ |
||
6542 | if (INTEL_INFO(dev)->gen > 3 && |
||
6543 | (fb->offsets[0] != crtc->fb->offsets[0] || |
||
6544 | fb->pitches[0] != crtc->fb->pitches[0])) |
||
6545 | return -EINVAL; |
||
2327 | Serge | 6546 | |
3031 | serge | 6547 | work = kzalloc(sizeof *work, GFP_KERNEL); |
6548 | if (work == NULL) |
||
6549 | return -ENOMEM; |
||
2327 | Serge | 6550 | |
3031 | serge | 6551 | work->event = event; |
6552 | work->dev = crtc->dev; |
||
6553 | intel_fb = to_intel_framebuffer(crtc->fb); |
||
6554 | work->old_fb_obj = intel_fb->obj; |
||
6555 | INIT_WORK(&work->work, intel_unpin_work_fn); |
||
2327 | Serge | 6556 | |
3031 | serge | 6557 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
6558 | if (ret) |
||
6559 | goto free_work; |
||
2327 | Serge | 6560 | |
3031 | serge | 6561 | /* We borrow the event spin lock for protecting unpin_work */ |
6562 | spin_lock_irqsave(&dev->event_lock, flags); |
||
6563 | if (intel_crtc->unpin_work) { |
||
6564 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
6565 | kfree(work); |
||
6566 | drm_vblank_put(dev, intel_crtc->pipe); |
||
2327 | Serge | 6567 | |
3031 | serge | 6568 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
6569 | return -EBUSY; |
||
6570 | } |
||
6571 | intel_crtc->unpin_work = work; |
||
6572 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
2327 | Serge | 6573 | |
3031 | serge | 6574 | intel_fb = to_intel_framebuffer(fb); |
6575 | obj = intel_fb->obj; |
||
2327 | Serge | 6576 | |
3031 | serge | 6577 | ret = i915_mutex_lock_interruptible(dev); |
6578 | if (ret) |
||
6579 | goto cleanup; |
||
2327 | Serge | 6580 | |
3031 | serge | 6581 | /* Reference the objects for the scheduled work. */ |
6582 | drm_gem_object_reference(&work->old_fb_obj->base); |
||
6583 | drm_gem_object_reference(&obj->base); |
||
2327 | Serge | 6584 | |
3031 | serge | 6585 | crtc->fb = fb; |
2327 | Serge | 6586 | |
3031 | serge | 6587 | work->pending_flip_obj = obj; |
2327 | Serge | 6588 | |
3031 | serge | 6589 | work->enable_stall_check = true; |
6590 | |||
6591 | /* Block clients from rendering to the new back buffer until |
||
6592 | * the flip occurs and the object is no longer visible. |
||
6593 | */ |
||
6594 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
||
6595 | |||
6596 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
||
6597 | if (ret) |
||
6598 | goto cleanup_pending; |
||
6599 | |||
6600 | intel_disable_fbc(dev); |
||
6601 | intel_mark_fb_busy(obj); |
||
6602 | mutex_unlock(&dev->struct_mutex); |
||
6603 | |||
6604 | trace_i915_flip_request(intel_crtc->plane, obj); |
||
6605 | |||
6606 | return 0; |
||
6607 | |||
6608 | cleanup_pending: |
||
6609 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
||
6610 | drm_gem_object_unreference(&work->old_fb_obj->base); |
||
6611 | drm_gem_object_unreference(&obj->base); |
||
6612 | mutex_unlock(&dev->struct_mutex); |
||
6613 | |||
6614 | cleanup: |
||
6615 | spin_lock_irqsave(&dev->event_lock, flags); |
||
6616 | intel_crtc->unpin_work = NULL; |
||
6617 | spin_unlock_irqrestore(&dev->event_lock, flags); |
||
6618 | |||
6619 | drm_vblank_put(dev, intel_crtc->pipe); |
||
6620 | free_work: |
||
6621 | kfree(work); |
||
6622 | |||
6623 | return ret; |
||
6624 | } |
||
6625 | |||
6626 | #endif |
||
6627 | |||
6628 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
||
6629 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
||
6630 | .load_lut = intel_crtc_load_lut, |
||
6631 | .disable = intel_crtc_noop, |
||
6632 | }; |
||
6633 | |||
6634 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
||
2330 | Serge | 6635 | { |
3031 | serge | 6636 | struct intel_encoder *other_encoder; |
6637 | struct drm_crtc *crtc = &encoder->new_crtc->base; |
||
2327 | Serge | 6638 | |
3031 | serge | 6639 | if (WARN_ON(!crtc)) |
6640 | return false; |
||
2327 | Serge | 6641 | |
3031 | serge | 6642 | list_for_each_entry(other_encoder, |
6643 | &crtc->dev->mode_config.encoder_list, |
||
6644 | base.head) { |
||
6645 | |||
6646 | if (&other_encoder->new_crtc->base != crtc || |
||
6647 | encoder == other_encoder) |
||
6648 | continue; |
||
6649 | else |
||
6650 | return true; |
||
6651 | } |
||
6652 | |||
6653 | return false; |
||
6654 | } |
||
6655 | |||
6656 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
||
6657 | struct drm_crtc *crtc) |
||
6658 | { |
||
6659 | struct drm_device *dev; |
||
6660 | struct drm_crtc *tmp; |
||
6661 | int crtc_mask = 1; |
||
6662 | |||
6663 | WARN(!crtc, "checking null crtc?\n"); |
||
6664 | |||
6665 | dev = crtc->dev; |
||
6666 | |||
6667 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
||
6668 | if (tmp == crtc) |
||
6669 | break; |
||
6670 | crtc_mask <<= 1; |
||
6671 | } |
||
6672 | |||
6673 | if (encoder->possible_crtcs & crtc_mask) |
||
6674 | return true; |
||
6675 | return false; |
||
6676 | } |
||
6677 | |||
6678 | /** |
||
6679 | * intel_modeset_update_staged_output_state |
||
6680 | * |
||
6681 | * Updates the staged output configuration state, e.g. after we've read out the |
||
6682 | * current hw state. |
||
6683 | */ |
||
6684 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
||
6685 | { |
||
6686 | struct intel_encoder *encoder; |
||
6687 | struct intel_connector *connector; |
||
6688 | |||
6689 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
6690 | base.head) { |
||
6691 | connector->new_encoder = |
||
6692 | to_intel_encoder(connector->base.encoder); |
||
6693 | } |
||
6694 | |||
6695 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
6696 | base.head) { |
||
6697 | encoder->new_crtc = |
||
6698 | to_intel_crtc(encoder->base.crtc); |
||
6699 | } |
||
6700 | } |
||
6701 | |||
6702 | /** |
||
6703 | * intel_modeset_commit_output_state |
||
6704 | * |
||
6705 | * This function copies the stage display pipe configuration to the real one. |
||
6706 | */ |
||
6707 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
||
6708 | { |
||
6709 | struct intel_encoder *encoder; |
||
6710 | struct intel_connector *connector; |
||
6711 | |||
6712 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
6713 | base.head) { |
||
6714 | connector->base.encoder = &connector->new_encoder->base; |
||
6715 | } |
||
6716 | |||
6717 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
6718 | base.head) { |
||
6719 | encoder->base.crtc = &encoder->new_crtc->base; |
||
6720 | } |
||
6721 | } |
||
6722 | |||
6723 | static struct drm_display_mode * |
||
6724 | intel_modeset_adjusted_mode(struct drm_crtc *crtc, |
||
6725 | struct drm_display_mode *mode) |
||
6726 | { |
||
6727 | struct drm_device *dev = crtc->dev; |
||
6728 | struct drm_display_mode *adjusted_mode; |
||
6729 | struct drm_encoder_helper_funcs *encoder_funcs; |
||
6730 | struct intel_encoder *encoder; |
||
6731 | |||
6732 | adjusted_mode = drm_mode_duplicate(dev, mode); |
||
6733 | if (!adjusted_mode) |
||
6734 | return ERR_PTR(-ENOMEM); |
||
6735 | |||
6736 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
||
6737 | * adjust it according to limitations or connector properties, and also |
||
6738 | * a chance to reject the mode entirely. |
||
2330 | Serge | 6739 | */ |
3031 | serge | 6740 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6741 | base.head) { |
||
2327 | Serge | 6742 | |
3031 | serge | 6743 | if (&encoder->new_crtc->base != crtc) |
6744 | continue; |
||
6745 | encoder_funcs = encoder->base.helper_private; |
||
6746 | if (!(encoder_funcs->mode_fixup(&encoder->base, mode, |
||
6747 | adjusted_mode))) { |
||
6748 | DRM_DEBUG_KMS("Encoder fixup failed\n"); |
||
6749 | goto fail; |
||
6750 | } |
||
6751 | } |
||
2327 | Serge | 6752 | |
3031 | serge | 6753 | if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { |
6754 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
||
6755 | goto fail; |
||
6756 | } |
||
6757 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
||
2327 | Serge | 6758 | |
3031 | serge | 6759 | return adjusted_mode; |
6760 | fail: |
||
6761 | drm_mode_destroy(dev, adjusted_mode); |
||
6762 | return ERR_PTR(-EINVAL); |
||
6763 | } |
||
2327 | Serge | 6764 | |
3031 | serge | 6765 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
6766 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
||
6767 | static void |
||
6768 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
||
6769 | unsigned *prepare_pipes, unsigned *disable_pipes) |
||
6770 | { |
||
6771 | struct intel_crtc *intel_crtc; |
||
6772 | struct drm_device *dev = crtc->dev; |
||
6773 | struct intel_encoder *encoder; |
||
6774 | struct intel_connector *connector; |
||
6775 | struct drm_crtc *tmp_crtc; |
||
6776 | |||
6777 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
||
6778 | |||
6779 | /* Check which crtcs have changed outputs connected to them, these need |
||
6780 | * to be part of the prepare_pipes mask. We don't (yet) support global |
||
6781 | * modeset across multiple crtcs, so modeset_pipes will only have one |
||
6782 | * bit set at most. */ |
||
6783 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
6784 | base.head) { |
||
6785 | if (connector->base.encoder == &connector->new_encoder->base) |
||
6786 | continue; |
||
6787 | |||
6788 | if (connector->base.encoder) { |
||
6789 | tmp_crtc = connector->base.encoder->crtc; |
||
6790 | |||
6791 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
||
6792 | } |
||
6793 | |||
6794 | if (connector->new_encoder) |
||
6795 | *prepare_pipes |= |
||
6796 | 1 << connector->new_encoder->new_crtc->pipe; |
||
6797 | } |
||
6798 | |||
6799 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
6800 | base.head) { |
||
6801 | if (encoder->base.crtc == &encoder->new_crtc->base) |
||
6802 | continue; |
||
6803 | |||
6804 | if (encoder->base.crtc) { |
||
6805 | tmp_crtc = encoder->base.crtc; |
||
6806 | |||
6807 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
||
6808 | } |
||
6809 | |||
6810 | if (encoder->new_crtc) |
||
6811 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
||
6812 | } |
||
6813 | |||
6814 | /* Check for any pipes that will be fully disabled ... */ |
||
6815 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
||
6816 | base.head) { |
||
6817 | bool used = false; |
||
6818 | |||
6819 | /* Don't try to disable disabled crtcs. */ |
||
6820 | if (!intel_crtc->base.enabled) |
||
6821 | continue; |
||
6822 | |||
6823 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
6824 | base.head) { |
||
6825 | if (encoder->new_crtc == intel_crtc) |
||
6826 | used = true; |
||
6827 | } |
||
6828 | |||
6829 | if (!used) |
||
6830 | *disable_pipes |= 1 << intel_crtc->pipe; |
||
6831 | } |
||
6832 | |||
6833 | |||
6834 | /* set_mode is also used to update properties on life display pipes. */ |
||
6835 | intel_crtc = to_intel_crtc(crtc); |
||
6836 | if (crtc->enabled) |
||
6837 | *prepare_pipes |= 1 << intel_crtc->pipe; |
||
6838 | |||
6839 | /* We only support modeset on one single crtc, hence we need to do that |
||
6840 | * only for the passed in crtc iff we change anything else than just |
||
6841 | * disable crtcs. |
||
6842 | * |
||
6843 | * This is actually not true, to be fully compatible with the old crtc |
||
6844 | * helper we automatically disable _any_ output (i.e. doesn't need to be |
||
6845 | * connected to the crtc we're modesetting on) if it's disconnected. |
||
6846 | * Which is a rather nutty api (since changed the output configuration |
||
6847 | * without userspace's explicit request can lead to confusion), but |
||
6848 | * alas. Hence we currently need to modeset on all pipes we prepare. */ |
||
6849 | if (*prepare_pipes) |
||
6850 | *modeset_pipes = *prepare_pipes; |
||
6851 | |||
6852 | /* ... and mask these out. */ |
||
6853 | *modeset_pipes &= ~(*disable_pipes); |
||
6854 | *prepare_pipes &= ~(*disable_pipes); |
||
2330 | Serge | 6855 | } |
2327 | Serge | 6856 | |
3031 | serge | 6857 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
2330 | Serge | 6858 | { |
3031 | serge | 6859 | struct drm_encoder *encoder; |
2330 | Serge | 6860 | struct drm_device *dev = crtc->dev; |
2327 | Serge | 6861 | |
3031 | serge | 6862 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
6863 | if (encoder->crtc == crtc) |
||
6864 | return true; |
||
6865 | |||
6866 | return false; |
||
6867 | } |
||
6868 | |||
6869 | static void |
||
6870 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
||
6871 | { |
||
6872 | struct intel_encoder *intel_encoder; |
||
6873 | struct intel_crtc *intel_crtc; |
||
6874 | struct drm_connector *connector; |
||
6875 | |||
6876 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
||
6877 | base.head) { |
||
6878 | if (!intel_encoder->base.crtc) |
||
6879 | continue; |
||
6880 | |||
6881 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
||
6882 | |||
6883 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
||
6884 | intel_encoder->connectors_active = false; |
||
6885 | } |
||
6886 | |||
6887 | intel_modeset_commit_output_state(dev); |
||
6888 | |||
6889 | /* Update computed state. */ |
||
6890 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
||
6891 | base.head) { |
||
6892 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
||
6893 | } |
||
6894 | |||
6895 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
6896 | if (!connector->encoder || !connector->encoder->crtc) |
||
6897 | continue; |
||
6898 | |||
6899 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
||
6900 | |||
6901 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
||
6902 | struct drm_property *dpms_property = |
||
6903 | dev->mode_config.dpms_property; |
||
6904 | |||
6905 | connector->dpms = DRM_MODE_DPMS_ON; |
||
6906 | drm_connector_property_set_value(connector, |
||
6907 | dpms_property, |
||
6908 | DRM_MODE_DPMS_ON); |
||
6909 | |||
6910 | intel_encoder = to_intel_encoder(connector->encoder); |
||
6911 | intel_encoder->connectors_active = true; |
||
6912 | } |
||
6913 | } |
||
6914 | |||
6915 | } |
||
6916 | |||
6917 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
||
6918 | list_for_each_entry((intel_crtc), \ |
||
6919 | &(dev)->mode_config.crtc_list, \ |
||
6920 | base.head) \ |
||
6921 | if (mask & (1 <<(intel_crtc)->pipe)) \ |
||
6922 | |||
6923 | void |
||
6924 | intel_modeset_check_state(struct drm_device *dev) |
||
6925 | { |
||
6926 | struct intel_crtc *crtc; |
||
6927 | struct intel_encoder *encoder; |
||
6928 | struct intel_connector *connector; |
||
6929 | |||
6930 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
6931 | base.head) { |
||
6932 | /* This also checks the encoder/connector hw state with the |
||
6933 | * ->get_hw_state callbacks. */ |
||
6934 | intel_connector_check_state(connector); |
||
6935 | |||
6936 | WARN(&connector->new_encoder->base != connector->base.encoder, |
||
6937 | "connector's staged encoder doesn't match current encoder\n"); |
||
6938 | } |
||
6939 | |||
6940 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
6941 | base.head) { |
||
6942 | bool enabled = false; |
||
6943 | bool active = false; |
||
6944 | enum pipe pipe, tracked_pipe; |
||
6945 | |||
6946 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
||
6947 | encoder->base.base.id, |
||
6948 | drm_get_encoder_name(&encoder->base)); |
||
6949 | |||
6950 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
||
6951 | "encoder's stage crtc doesn't match current crtc\n"); |
||
6952 | WARN(encoder->connectors_active && !encoder->base.crtc, |
||
6953 | "encoder's active_connectors set, but no crtc\n"); |
||
6954 | |||
6955 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
6956 | base.head) { |
||
6957 | if (connector->base.encoder != &encoder->base) |
||
6958 | continue; |
||
6959 | enabled = true; |
||
6960 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
||
6961 | active = true; |
||
6962 | } |
||
6963 | WARN(!!encoder->base.crtc != enabled, |
||
6964 | "encoder's enabled state mismatch " |
||
6965 | "(expected %i, found %i)\n", |
||
6966 | !!encoder->base.crtc, enabled); |
||
6967 | WARN(active && !encoder->base.crtc, |
||
6968 | "active encoder with no crtc\n"); |
||
6969 | |||
6970 | WARN(encoder->connectors_active != active, |
||
6971 | "encoder's computed active state doesn't match tracked active state " |
||
6972 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
||
6973 | |||
6974 | active = encoder->get_hw_state(encoder, &pipe); |
||
6975 | WARN(active != encoder->connectors_active, |
||
6976 | "encoder's hw state doesn't match sw tracking " |
||
6977 | "(expected %i, found %i)\n", |
||
6978 | encoder->connectors_active, active); |
||
6979 | |||
6980 | if (!encoder->base.crtc) |
||
6981 | continue; |
||
6982 | |||
6983 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
||
6984 | WARN(active && pipe != tracked_pipe, |
||
6985 | "active encoder's pipe doesn't match" |
||
6986 | "(expected %i, found %i)\n", |
||
6987 | tracked_pipe, pipe); |
||
6988 | |||
6989 | } |
||
6990 | |||
6991 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
||
6992 | base.head) { |
||
6993 | bool enabled = false; |
||
6994 | bool active = false; |
||
6995 | |||
6996 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
||
6997 | crtc->base.base.id); |
||
6998 | |||
6999 | WARN(crtc->active && !crtc->base.enabled, |
||
7000 | "active crtc, but not enabled in sw tracking\n"); |
||
7001 | |||
7002 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
7003 | base.head) { |
||
7004 | if (encoder->base.crtc != &crtc->base) |
||
7005 | continue; |
||
7006 | enabled = true; |
||
7007 | if (encoder->connectors_active) |
||
7008 | active = true; |
||
7009 | } |
||
7010 | WARN(active != crtc->active, |
||
7011 | "crtc's computed active state doesn't match tracked active state " |
||
7012 | "(expected %i, found %i)\n", active, crtc->active); |
||
7013 | WARN(enabled != crtc->base.enabled, |
||
7014 | "crtc's computed enabled state doesn't match tracked enabled state " |
||
7015 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
||
7016 | |||
7017 | assert_pipe(dev->dev_private, crtc->pipe, crtc->active); |
||
7018 | } |
||
7019 | } |
||
7020 | |||
7021 | bool intel_set_mode(struct drm_crtc *crtc, |
||
7022 | struct drm_display_mode *mode, |
||
7023 | int x, int y, struct drm_framebuffer *fb) |
||
7024 | { |
||
7025 | struct drm_device *dev = crtc->dev; |
||
7026 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7027 | struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode; |
||
7028 | struct drm_encoder_helper_funcs *encoder_funcs; |
||
7029 | struct drm_encoder *encoder; |
||
7030 | struct intel_crtc *intel_crtc; |
||
7031 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
||
7032 | bool ret = true; |
||
7033 | |||
7034 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
||
7035 | &prepare_pipes, &disable_pipes); |
||
7036 | |||
7037 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
||
7038 | modeset_pipes, prepare_pipes, disable_pipes); |
||
7039 | |||
7040 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
||
7041 | intel_crtc_disable(&intel_crtc->base); |
||
7042 | |||
7043 | saved_hwmode = crtc->hwmode; |
||
7044 | saved_mode = crtc->mode; |
||
7045 | |||
7046 | /* Hack: Because we don't (yet) support global modeset on multiple |
||
7047 | * crtcs, we don't keep track of the new mode for more than one crtc. |
||
7048 | * Hence simply check whether any bit is set in modeset_pipes in all the |
||
7049 | * pieces of code that are not yet converted to deal with mutliple crtcs |
||
7050 | * changing their mode at the same time. */ |
||
7051 | adjusted_mode = NULL; |
||
7052 | if (modeset_pipes) { |
||
7053 | adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); |
||
7054 | if (IS_ERR(adjusted_mode)) { |
||
7055 | return false; |
||
7056 | } |
||
7057 | } |
||
7058 | |||
7059 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
||
7060 | if (intel_crtc->base.enabled) |
||
7061 | dev_priv->display.crtc_disable(&intel_crtc->base); |
||
7062 | } |
||
7063 | |||
7064 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
||
7065 | * to set it here already despite that we pass it down the callchain. |
||
2330 | Serge | 7066 | */ |
3031 | serge | 7067 | if (modeset_pipes) |
7068 | crtc->mode = *mode; |
||
2327 | Serge | 7069 | |
3031 | serge | 7070 | /* Only after disabling all output pipelines that will be changed can we |
7071 | * update the the output configuration. */ |
||
7072 | intel_modeset_update_state(dev, prepare_pipes); |
||
7073 | |||
7074 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
||
7075 | * on the DPLL. |
||
2330 | Serge | 7076 | */ |
3031 | serge | 7077 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
7078 | ret = !intel_crtc_mode_set(&intel_crtc->base, |
||
7079 | mode, adjusted_mode, |
||
7080 | x, y, fb); |
||
7081 | if (!ret) |
||
7082 | goto done; |
||
7083 | |||
7084 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
7085 | |||
7086 | if (encoder->crtc != &intel_crtc->base) |
||
7087 | continue; |
||
7088 | |||
7089 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
||
7090 | encoder->base.id, drm_get_encoder_name(encoder), |
||
7091 | mode->base.id, mode->name); |
||
7092 | encoder_funcs = encoder->helper_private; |
||
7093 | encoder_funcs->mode_set(encoder, mode, adjusted_mode); |
||
7094 | } |
||
7095 | } |
||
7096 | |||
7097 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
||
7098 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
||
7099 | dev_priv->display.crtc_enable(&intel_crtc->base); |
||
7100 | |||
7101 | if (modeset_pipes) { |
||
7102 | /* Store real post-adjustment hardware mode. */ |
||
7103 | crtc->hwmode = *adjusted_mode; |
||
7104 | |||
7105 | /* Calculate and store various constants which |
||
7106 | * are later needed by vblank and swap-completion |
||
7107 | * timestamping. They are derived from true hwmode. |
||
7108 | */ |
||
7109 | drm_calc_timestamping_constants(crtc); |
||
7110 | } |
||
7111 | |||
7112 | /* FIXME: add subpixel order */ |
||
7113 | done: |
||
7114 | drm_mode_destroy(dev, adjusted_mode); |
||
7115 | if (!ret && crtc->enabled) { |
||
7116 | crtc->hwmode = saved_hwmode; |
||
7117 | crtc->mode = saved_mode; |
||
7118 | } else { |
||
7119 | intel_modeset_check_state(dev); |
||
7120 | } |
||
7121 | |||
7122 | return ret; |
||
2330 | Serge | 7123 | } |
2327 | Serge | 7124 | |
3031 | serge | 7125 | #undef for_each_intel_crtc_masked |
2327 | Serge | 7126 | |
3031 | serge | 7127 | static void intel_set_config_free(struct intel_set_config *config) |
7128 | { |
||
7129 | if (!config) |
||
7130 | return; |
||
7131 | |||
7132 | kfree(config->save_connector_encoders); |
||
7133 | kfree(config->save_encoder_crtcs); |
||
7134 | kfree(config); |
||
7135 | } |
||
7136 | |||
7137 | static int intel_set_config_save_state(struct drm_device *dev, |
||
7138 | struct intel_set_config *config) |
||
7139 | { |
||
7140 | struct drm_encoder *encoder; |
||
7141 | struct drm_connector *connector; |
||
7142 | int count; |
||
7143 | |||
7144 | config->save_encoder_crtcs = |
||
7145 | kcalloc(dev->mode_config.num_encoder, |
||
7146 | sizeof(struct drm_crtc *), GFP_KERNEL); |
||
7147 | if (!config->save_encoder_crtcs) |
||
7148 | return -ENOMEM; |
||
7149 | |||
7150 | config->save_connector_encoders = |
||
7151 | kcalloc(dev->mode_config.num_connector, |
||
7152 | sizeof(struct drm_encoder *), GFP_KERNEL); |
||
7153 | if (!config->save_connector_encoders) |
||
7154 | return -ENOMEM; |
||
7155 | |||
7156 | /* Copy data. Note that driver private data is not affected. |
||
7157 | * Should anything bad happen only the expected state is |
||
7158 | * restored, not the drivers personal bookkeeping. |
||
7159 | */ |
||
7160 | count = 0; |
||
7161 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
7162 | config->save_encoder_crtcs[count++] = encoder->crtc; |
||
7163 | } |
||
7164 | |||
7165 | count = 0; |
||
7166 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
7167 | config->save_connector_encoders[count++] = connector->encoder; |
||
7168 | } |
||
7169 | |||
7170 | return 0; |
||
7171 | } |
||
7172 | |||
7173 | static void intel_set_config_restore_state(struct drm_device *dev, |
||
7174 | struct intel_set_config *config) |
||
7175 | { |
||
7176 | struct intel_encoder *encoder; |
||
7177 | struct intel_connector *connector; |
||
7178 | int count; |
||
7179 | |||
7180 | count = 0; |
||
7181 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
||
7182 | encoder->new_crtc = |
||
7183 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
||
7184 | } |
||
7185 | |||
7186 | count = 0; |
||
7187 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
||
7188 | connector->new_encoder = |
||
7189 | to_intel_encoder(config->save_connector_encoders[count++]); |
||
7190 | } |
||
7191 | } |
||
7192 | |||
7193 | static void |
||
7194 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
||
7195 | struct intel_set_config *config) |
||
7196 | { |
||
7197 | |||
7198 | /* We should be able to check here if the fb has the same properties |
||
7199 | * and then just flip_or_move it */ |
||
7200 | if (set->crtc->fb != set->fb) { |
||
7201 | /* If we have no fb then treat it as a full mode set */ |
||
7202 | if (set->crtc->fb == NULL) { |
||
7203 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); |
||
7204 | config->mode_changed = true; |
||
7205 | } else if (set->fb == NULL) { |
||
7206 | config->mode_changed = true; |
||
7207 | } else if (set->fb->depth != set->crtc->fb->depth) { |
||
7208 | config->mode_changed = true; |
||
7209 | } else if (set->fb->bits_per_pixel != |
||
7210 | set->crtc->fb->bits_per_pixel) { |
||
7211 | config->mode_changed = true; |
||
7212 | } else |
||
7213 | config->fb_changed = true; |
||
7214 | } |
||
7215 | |||
7216 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
||
7217 | config->fb_changed = true; |
||
7218 | |||
7219 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
||
7220 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
||
7221 | drm_mode_debug_printmodeline(&set->crtc->mode); |
||
7222 | drm_mode_debug_printmodeline(set->mode); |
||
7223 | config->mode_changed = true; |
||
7224 | } |
||
7225 | } |
||
7226 | |||
7227 | static int |
||
7228 | intel_modeset_stage_output_state(struct drm_device *dev, |
||
7229 | struct drm_mode_set *set, |
||
7230 | struct intel_set_config *config) |
||
7231 | { |
||
7232 | struct drm_crtc *new_crtc; |
||
7233 | struct intel_connector *connector; |
||
7234 | struct intel_encoder *encoder; |
||
7235 | int count, ro; |
||
7236 | |||
7237 | /* The upper layers ensure that we either disabl a crtc or have a list |
||
7238 | * of connectors. For paranoia, double-check this. */ |
||
7239 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
||
7240 | WARN_ON(set->fb && (set->num_connectors == 0)); |
||
7241 | |||
7242 | count = 0; |
||
7243 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
7244 | base.head) { |
||
7245 | /* Otherwise traverse passed in connector list and get encoders |
||
7246 | * for them. */ |
||
7247 | for (ro = 0; ro < set->num_connectors; ro++) { |
||
7248 | if (set->connectors[ro] == &connector->base) { |
||
7249 | connector->new_encoder = connector->encoder; |
||
7250 | break; |
||
7251 | } |
||
7252 | } |
||
7253 | |||
7254 | /* If we disable the crtc, disable all its connectors. Also, if |
||
7255 | * the connector is on the changing crtc but not on the new |
||
7256 | * connector list, disable it. */ |
||
7257 | if ((!set->fb || ro == set->num_connectors) && |
||
7258 | connector->base.encoder && |
||
7259 | connector->base.encoder->crtc == set->crtc) { |
||
7260 | connector->new_encoder = NULL; |
||
7261 | |||
7262 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
||
7263 | connector->base.base.id, |
||
7264 | drm_get_connector_name(&connector->base)); |
||
7265 | } |
||
7266 | |||
7267 | |||
7268 | if (&connector->new_encoder->base != connector->base.encoder) { |
||
7269 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
||
7270 | config->mode_changed = true; |
||
7271 | } |
||
7272 | |||
7273 | /* Disable all disconnected encoders. */ |
||
7274 | if (connector->base.status == connector_status_disconnected) |
||
7275 | connector->new_encoder = NULL; |
||
7276 | } |
||
7277 | /* connector->new_encoder is now updated for all connectors. */ |
||
7278 | |||
7279 | /* Update crtc of enabled connectors. */ |
||
7280 | count = 0; |
||
7281 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
7282 | base.head) { |
||
7283 | if (!connector->new_encoder) |
||
7284 | continue; |
||
7285 | |||
7286 | new_crtc = connector->new_encoder->base.crtc; |
||
7287 | |||
7288 | for (ro = 0; ro < set->num_connectors; ro++) { |
||
7289 | if (set->connectors[ro] == &connector->base) |
||
7290 | new_crtc = set->crtc; |
||
7291 | } |
||
7292 | |||
7293 | /* Make sure the new CRTC will work with the encoder */ |
||
7294 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
||
7295 | new_crtc)) { |
||
7296 | return -EINVAL; |
||
7297 | } |
||
7298 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
||
7299 | |||
7300 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
||
7301 | connector->base.base.id, |
||
7302 | drm_get_connector_name(&connector->base), |
||
7303 | new_crtc->base.id); |
||
7304 | } |
||
7305 | |||
7306 | /* Check for any encoders that needs to be disabled. */ |
||
7307 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
7308 | base.head) { |
||
7309 | list_for_each_entry(connector, |
||
7310 | &dev->mode_config.connector_list, |
||
7311 | base.head) { |
||
7312 | if (connector->new_encoder == encoder) { |
||
7313 | WARN_ON(!connector->new_encoder->new_crtc); |
||
7314 | |||
7315 | goto next_encoder; |
||
7316 | } |
||
7317 | } |
||
7318 | encoder->new_crtc = NULL; |
||
7319 | next_encoder: |
||
7320 | /* Only now check for crtc changes so we don't miss encoders |
||
7321 | * that will be disabled. */ |
||
7322 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
||
7323 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
||
7324 | config->mode_changed = true; |
||
7325 | } |
||
7326 | } |
||
7327 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
||
7328 | |||
7329 | return 0; |
||
7330 | } |
||
7331 | |||
7332 | static int intel_crtc_set_config(struct drm_mode_set *set) |
||
7333 | { |
||
7334 | struct drm_device *dev; |
||
7335 | struct drm_mode_set save_set; |
||
7336 | struct intel_set_config *config; |
||
7337 | int ret; |
||
7338 | |||
7339 | BUG_ON(!set); |
||
7340 | BUG_ON(!set->crtc); |
||
7341 | BUG_ON(!set->crtc->helper_private); |
||
7342 | |||
7343 | if (!set->mode) |
||
7344 | set->fb = NULL; |
||
7345 | |||
7346 | /* The fb helper likes to play gross jokes with ->mode_set_config. |
||
7347 | * Unfortunately the crtc helper doesn't do much at all for this case, |
||
7348 | * so we have to cope with this madness until the fb helper is fixed up. */ |
||
7349 | if (set->fb && set->num_connectors == 0) |
||
7350 | return 0; |
||
7351 | |||
7352 | if (set->fb) { |
||
7353 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
||
7354 | set->crtc->base.id, set->fb->base.id, |
||
7355 | (int)set->num_connectors, set->x, set->y); |
||
7356 | } else { |
||
7357 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
||
7358 | } |
||
7359 | |||
7360 | dev = set->crtc->dev; |
||
7361 | |||
7362 | ret = -ENOMEM; |
||
7363 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
||
7364 | if (!config) |
||
7365 | goto out_config; |
||
7366 | |||
7367 | ret = intel_set_config_save_state(dev, config); |
||
7368 | if (ret) |
||
7369 | goto out_config; |
||
7370 | |||
7371 | save_set.crtc = set->crtc; |
||
7372 | save_set.mode = &set->crtc->mode; |
||
7373 | save_set.x = set->crtc->x; |
||
7374 | save_set.y = set->crtc->y; |
||
7375 | save_set.fb = set->crtc->fb; |
||
7376 | |||
7377 | /* Compute whether we need a full modeset, only an fb base update or no |
||
7378 | * change at all. In the future we might also check whether only the |
||
7379 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
||
7380 | * such cases. */ |
||
7381 | intel_set_config_compute_mode_changes(set, config); |
||
7382 | |||
7383 | ret = intel_modeset_stage_output_state(dev, set, config); |
||
7384 | if (ret) |
||
7385 | goto fail; |
||
7386 | |||
7387 | if (config->mode_changed) { |
||
7388 | if (set->mode) { |
||
7389 | DRM_DEBUG_KMS("attempting to set mode from" |
||
7390 | " userspace\n"); |
||
7391 | drm_mode_debug_printmodeline(set->mode); |
||
7392 | } |
||
7393 | |||
7394 | if (!intel_set_mode(set->crtc, set->mode, |
||
7395 | set->x, set->y, set->fb)) { |
||
7396 | DRM_ERROR("failed to set mode on [CRTC:%d]\n", |
||
7397 | set->crtc->base.id); |
||
7398 | ret = -EINVAL; |
||
7399 | goto fail; |
||
7400 | } |
||
7401 | } else if (config->fb_changed) { |
||
7402 | ret = intel_pipe_set_base(set->crtc, |
||
7403 | set->x, set->y, set->fb); |
||
7404 | } |
||
7405 | |||
7406 | intel_set_config_free(config); |
||
7407 | |||
7408 | return 0; |
||
7409 | |||
7410 | fail: |
||
7411 | intel_set_config_restore_state(dev, config); |
||
7412 | |||
7413 | /* Try to restore the config */ |
||
7414 | if (config->mode_changed && |
||
7415 | !intel_set_mode(save_set.crtc, save_set.mode, |
||
7416 | save_set.x, save_set.y, save_set.fb)) |
||
7417 | DRM_ERROR("failed to restore config after modeset failure\n"); |
||
7418 | |||
7419 | out_config: |
||
7420 | intel_set_config_free(config); |
||
7421 | return ret; |
||
7422 | } |
||
7423 | |||
2330 | Serge | 7424 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
7425 | // .cursor_set = intel_crtc_cursor_set, |
||
7426 | // .cursor_move = intel_crtc_cursor_move, |
||
7427 | .gamma_set = intel_crtc_gamma_set, |
||
3031 | serge | 7428 | .set_config = intel_crtc_set_config, |
2330 | Serge | 7429 | .destroy = intel_crtc_destroy, |
7430 | // .page_flip = intel_crtc_page_flip, |
||
7431 | }; |
||
2327 | Serge | 7432 | |
3031 | serge | 7433 | static void intel_pch_pll_init(struct drm_device *dev) |
7434 | { |
||
7435 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7436 | int i; |
||
7437 | |||
7438 | if (dev_priv->num_pch_pll == 0) { |
||
7439 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); |
||
7440 | return; |
||
7441 | } |
||
7442 | |||
7443 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
||
7444 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); |
||
7445 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); |
||
7446 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); |
||
7447 | } |
||
7448 | } |
||
7449 | |||
2330 | Serge | 7450 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
7451 | { |
||
7452 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
7453 | struct intel_crtc *intel_crtc; |
||
7454 | int i; |
||
2327 | Serge | 7455 | |
2330 | Serge | 7456 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
7457 | if (intel_crtc == NULL) |
||
7458 | return; |
||
2327 | Serge | 7459 | |
2330 | Serge | 7460 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
2327 | Serge | 7461 | |
2330 | Serge | 7462 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
7463 | for (i = 0; i < 256; i++) { |
||
7464 | intel_crtc->lut_r[i] = i; |
||
7465 | intel_crtc->lut_g[i] = i; |
||
7466 | intel_crtc->lut_b[i] = i; |
||
7467 | } |
||
2327 | Serge | 7468 | |
2330 | Serge | 7469 | /* Swap pipes & planes for FBC on pre-965 */ |
7470 | intel_crtc->pipe = pipe; |
||
7471 | intel_crtc->plane = pipe; |
||
7472 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
||
7473 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
||
7474 | intel_crtc->plane = !pipe; |
||
7475 | } |
||
2327 | Serge | 7476 | |
2330 | Serge | 7477 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7478 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
||
7479 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
||
7480 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
||
2327 | Serge | 7481 | |
2330 | Serge | 7482 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
2327 | Serge | 7483 | |
2330 | Serge | 7484 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
2327 | Serge | 7485 | |
3037 | serge | 7486 | DRM_DEBUG_KMS("CRTC %d mode %x FB %x enable %d\n", |
3031 | serge | 7487 | intel_crtc->base.base.id, intel_crtc->base.mode, |
7488 | intel_crtc->base.fb, intel_crtc->base.enabled); |
||
2327 | Serge | 7489 | |
2330 | Serge | 7490 | } |
2327 | Serge | 7491 | |
3031 | serge | 7492 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
7493 | struct drm_file *file) |
||
7494 | { |
||
7495 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
||
7496 | struct drm_mode_object *drmmode_obj; |
||
7497 | struct intel_crtc *crtc; |
||
2327 | Serge | 7498 | |
3031 | serge | 7499 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7500 | DRM_MODE_OBJECT_CRTC); |
||
2327 | Serge | 7501 | |
3031 | serge | 7502 | if (!drmmode_obj) { |
7503 | DRM_ERROR("no such CRTC id\n"); |
||
7504 | return -EINVAL; |
||
7505 | } |
||
2327 | Serge | 7506 | |
3031 | serge | 7507 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7508 | pipe_from_crtc_id->pipe = crtc->pipe; |
||
2327 | Serge | 7509 | |
3031 | serge | 7510 | return 0; |
7511 | } |
||
2327 | Serge | 7512 | |
3031 | serge | 7513 | static int intel_encoder_clones(struct intel_encoder *encoder) |
2330 | Serge | 7514 | { |
3031 | serge | 7515 | struct drm_device *dev = encoder->base.dev; |
7516 | struct intel_encoder *source_encoder; |
||
2330 | Serge | 7517 | int index_mask = 0; |
7518 | int entry = 0; |
||
2327 | Serge | 7519 | |
3031 | serge | 7520 | list_for_each_entry(source_encoder, |
7521 | &dev->mode_config.encoder_list, base.head) { |
||
7522 | |||
7523 | if (encoder == source_encoder) |
||
2330 | Serge | 7524 | index_mask |= (1 << entry); |
3031 | serge | 7525 | |
7526 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
||
7527 | if (encoder->cloneable && source_encoder->cloneable) |
||
7528 | index_mask |= (1 << entry); |
||
7529 | |||
2330 | Serge | 7530 | entry++; |
7531 | } |
||
2327 | Serge | 7532 | |
2330 | Serge | 7533 | return index_mask; |
7534 | } |
||
2327 | Serge | 7535 | |
2330 | Serge | 7536 | static bool has_edp_a(struct drm_device *dev) |
7537 | { |
||
7538 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 7539 | |
2330 | Serge | 7540 | if (!IS_MOBILE(dev)) |
7541 | return false; |
||
2327 | Serge | 7542 | |
2330 | Serge | 7543 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
7544 | return false; |
||
2327 | Serge | 7545 | |
2330 | Serge | 7546 | if (IS_GEN5(dev) && |
7547 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
||
7548 | return false; |
||
2327 | Serge | 7549 | |
2330 | Serge | 7550 | return true; |
7551 | } |
||
2327 | Serge | 7552 | |
2330 | Serge | 7553 | static void intel_setup_outputs(struct drm_device *dev) |
7554 | { |
||
7555 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7556 | struct intel_encoder *encoder; |
||
7557 | bool dpd_is_edp = false; |
||
3031 | serge | 7558 | bool has_lvds; |
2327 | Serge | 7559 | |
2330 | Serge | 7560 | has_lvds = intel_lvds_init(dev); |
7561 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
||
7562 | /* disable the panel fitter on everything but LVDS */ |
||
7563 | I915_WRITE(PFIT_CONTROL, 0); |
||
7564 | } |
||
2327 | Serge | 7565 | |
2330 | Serge | 7566 | if (HAS_PCH_SPLIT(dev)) { |
7567 | dpd_is_edp = intel_dpd_is_edp(dev); |
||
2327 | Serge | 7568 | |
2330 | Serge | 7569 | if (has_edp_a(dev)) |
3031 | serge | 7570 | intel_dp_init(dev, DP_A, PORT_A); |
2327 | Serge | 7571 | |
2330 | Serge | 7572 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
3031 | serge | 7573 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
2330 | Serge | 7574 | } |
2327 | Serge | 7575 | |
2330 | Serge | 7576 | intel_crt_init(dev); |
2327 | Serge | 7577 | |
3031 | serge | 7578 | if (IS_HASWELL(dev)) { |
2330 | Serge | 7579 | int found; |
2327 | Serge | 7580 | |
3031 | serge | 7581 | /* Haswell uses DDI functions to detect digital outputs */ |
7582 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
||
7583 | /* DDI A only supports eDP */ |
||
7584 | if (found) |
||
7585 | intel_ddi_init(dev, PORT_A); |
||
7586 | |||
7587 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
||
7588 | * register */ |
||
7589 | found = I915_READ(SFUSE_STRAP); |
||
7590 | |||
7591 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
||
7592 | intel_ddi_init(dev, PORT_B); |
||
7593 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
||
7594 | intel_ddi_init(dev, PORT_C); |
||
7595 | if (found & SFUSE_STRAP_DDID_DETECTED) |
||
7596 | intel_ddi_init(dev, PORT_D); |
||
7597 | } else if (HAS_PCH_SPLIT(dev)) { |
||
7598 | int found; |
||
7599 | |||
2330 | Serge | 7600 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
7601 | /* PCH SDVOB multiplex with HDMIB */ |
||
3031 | serge | 7602 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
2330 | Serge | 7603 | if (!found) |
3031 | serge | 7604 | intel_hdmi_init(dev, HDMIB, PORT_B); |
2330 | Serge | 7605 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
3031 | serge | 7606 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
2330 | Serge | 7607 | } |
2327 | Serge | 7608 | |
2330 | Serge | 7609 | if (I915_READ(HDMIC) & PORT_DETECTED) |
3031 | serge | 7610 | intel_hdmi_init(dev, HDMIC, PORT_C); |
2327 | Serge | 7611 | |
3031 | serge | 7612 | if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) |
7613 | intel_hdmi_init(dev, HDMID, PORT_D); |
||
2327 | Serge | 7614 | |
2330 | Serge | 7615 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
3031 | serge | 7616 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
2327 | Serge | 7617 | |
2330 | Serge | 7618 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
3031 | serge | 7619 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
7620 | } else if (IS_VALLEYVIEW(dev)) { |
||
7621 | int found; |
||
2327 | Serge | 7622 | |
3031 | serge | 7623 | if (I915_READ(SDVOB) & PORT_DETECTED) { |
7624 | /* SDVOB multiplex with HDMIB */ |
||
7625 | found = intel_sdvo_init(dev, SDVOB, true); |
||
7626 | if (!found) |
||
7627 | intel_hdmi_init(dev, SDVOB, PORT_B); |
||
7628 | if (!found && (I915_READ(DP_B) & DP_DETECTED)) |
||
7629 | intel_dp_init(dev, DP_B, PORT_B); |
||
7630 | } |
||
7631 | |||
7632 | if (I915_READ(SDVOC) & PORT_DETECTED) |
||
7633 | intel_hdmi_init(dev, SDVOC, PORT_C); |
||
7634 | |||
7635 | /* Shares lanes with HDMI on SDVOC */ |
||
7636 | if (I915_READ(DP_C) & DP_DETECTED) |
||
7637 | intel_dp_init(dev, DP_C, PORT_C); |
||
2330 | Serge | 7638 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
7639 | bool found = false; |
||
2327 | Serge | 7640 | |
2330 | Serge | 7641 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7642 | DRM_DEBUG_KMS("probing SDVOB\n"); |
||
3031 | serge | 7643 | found = intel_sdvo_init(dev, SDVOB, true); |
2330 | Serge | 7644 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7645 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
||
3031 | serge | 7646 | intel_hdmi_init(dev, SDVOB, PORT_B); |
2330 | Serge | 7647 | } |
2327 | Serge | 7648 | |
2330 | Serge | 7649 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7650 | DRM_DEBUG_KMS("probing DP_B\n"); |
||
3031 | serge | 7651 | intel_dp_init(dev, DP_B, PORT_B); |
2330 | Serge | 7652 | } |
7653 | } |
||
2327 | Serge | 7654 | |
2330 | Serge | 7655 | /* Before G4X SDVOC doesn't have its own detect register */ |
2327 | Serge | 7656 | |
2330 | Serge | 7657 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7658 | DRM_DEBUG_KMS("probing SDVOC\n"); |
||
3031 | serge | 7659 | found = intel_sdvo_init(dev, SDVOC, false); |
2330 | Serge | 7660 | } |
2327 | Serge | 7661 | |
2330 | Serge | 7662 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { |
2327 | Serge | 7663 | |
2330 | Serge | 7664 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7665 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
||
3031 | serge | 7666 | intel_hdmi_init(dev, SDVOC, PORT_C); |
2330 | Serge | 7667 | } |
7668 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
||
7669 | DRM_DEBUG_KMS("probing DP_C\n"); |
||
3031 | serge | 7670 | intel_dp_init(dev, DP_C, PORT_C); |
2330 | Serge | 7671 | } |
7672 | } |
||
2327 | Serge | 7673 | |
2330 | Serge | 7674 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7675 | (I915_READ(DP_D) & DP_DETECTED)) { |
||
7676 | DRM_DEBUG_KMS("probing DP_D\n"); |
||
3031 | serge | 7677 | intel_dp_init(dev, DP_D, PORT_D); |
2330 | Serge | 7678 | } |
7679 | } else if (IS_GEN2(dev)) |
||
7680 | intel_dvo_init(dev); |
||
2327 | Serge | 7681 | |
2330 | Serge | 7682 | // if (SUPPORTS_TV(dev)) |
7683 | // intel_tv_init(dev); |
||
2327 | Serge | 7684 | |
2330 | Serge | 7685 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7686 | encoder->base.possible_crtcs = encoder->crtc_mask; |
||
7687 | encoder->base.possible_clones = |
||
3031 | serge | 7688 | intel_encoder_clones(encoder); |
2330 | Serge | 7689 | } |
2327 | Serge | 7690 | |
3031 | serge | 7691 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
2342 | Serge | 7692 | ironlake_init_pch_refclk(dev); |
2330 | Serge | 7693 | } |
7694 | |||
7695 | |||
7696 | |||
2335 | Serge | 7697 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
7698 | // .destroy = intel_user_framebuffer_destroy, |
||
7699 | // .create_handle = intel_user_framebuffer_create_handle, |
||
7700 | }; |
||
2327 | Serge | 7701 | |
2335 | Serge | 7702 | int intel_framebuffer_init(struct drm_device *dev, |
7703 | struct intel_framebuffer *intel_fb, |
||
2342 | Serge | 7704 | struct drm_mode_fb_cmd2 *mode_cmd, |
2335 | Serge | 7705 | struct drm_i915_gem_object *obj) |
7706 | { |
||
7707 | int ret; |
||
2327 | Serge | 7708 | |
2335 | Serge | 7709 | if (obj->tiling_mode == I915_TILING_Y) |
7710 | return -EINVAL; |
||
2327 | Serge | 7711 | |
2342 | Serge | 7712 | if (mode_cmd->pitches[0] & 63) |
2335 | Serge | 7713 | return -EINVAL; |
2327 | Serge | 7714 | |
2342 | Serge | 7715 | switch (mode_cmd->pixel_format) { |
7716 | case DRM_FORMAT_RGB332: |
||
7717 | case DRM_FORMAT_RGB565: |
||
7718 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 7719 | case DRM_FORMAT_XBGR8888: |
2342 | Serge | 7720 | case DRM_FORMAT_ARGB8888: |
7721 | case DRM_FORMAT_XRGB2101010: |
||
7722 | case DRM_FORMAT_ARGB2101010: |
||
7723 | /* RGB formats are common across chipsets */ |
||
2335 | Serge | 7724 | break; |
2342 | Serge | 7725 | case DRM_FORMAT_YUYV: |
7726 | case DRM_FORMAT_UYVY: |
||
7727 | case DRM_FORMAT_YVYU: |
||
7728 | case DRM_FORMAT_VYUY: |
||
7729 | break; |
||
2335 | Serge | 7730 | default: |
3031 | serge | 7731 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
7732 | mode_cmd->pixel_format); |
||
2335 | Serge | 7733 | return -EINVAL; |
7734 | } |
||
2327 | Serge | 7735 | |
2335 | Serge | 7736 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7737 | if (ret) { |
||
7738 | DRM_ERROR("framebuffer init failed %d\n", ret); |
||
7739 | return ret; |
||
7740 | } |
||
2327 | Serge | 7741 | |
2335 | Serge | 7742 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
7743 | intel_fb->obj = obj; |
||
7744 | return 0; |
||
7745 | } |
||
2327 | Serge | 7746 | |
7747 | |||
2360 | Serge | 7748 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
7749 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
||
7750 | .output_poll_changed = NULL /*intel_fb_output_poll_changed*/, |
||
7751 | }; |
||
2327 | Serge | 7752 | |
3031 | serge | 7753 | /* Set up chip specific display functions */ |
7754 | static void intel_init_display(struct drm_device *dev) |
||
7755 | { |
||
7756 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 7757 | |
3031 | serge | 7758 | /* We always want a DPMS function */ |
7759 | if (HAS_PCH_SPLIT(dev)) { |
||
7760 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
||
7761 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
||
7762 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
||
7763 | dev_priv->display.off = ironlake_crtc_off; |
||
7764 | dev_priv->display.update_plane = ironlake_update_plane; |
||
7765 | } else { |
||
7766 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
||
7767 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
||
7768 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
||
7769 | dev_priv->display.off = i9xx_crtc_off; |
||
7770 | dev_priv->display.update_plane = i9xx_update_plane; |
||
7771 | } |
||
2327 | Serge | 7772 | |
3031 | serge | 7773 | /* Returns the core display clock speed */ |
7774 | if (IS_VALLEYVIEW(dev)) |
||
7775 | dev_priv->display.get_display_clock_speed = |
||
7776 | valleyview_get_display_clock_speed; |
||
7777 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
||
7778 | dev_priv->display.get_display_clock_speed = |
||
7779 | i945_get_display_clock_speed; |
||
7780 | else if (IS_I915G(dev)) |
||
7781 | dev_priv->display.get_display_clock_speed = |
||
7782 | i915_get_display_clock_speed; |
||
7783 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
||
7784 | dev_priv->display.get_display_clock_speed = |
||
7785 | i9xx_misc_get_display_clock_speed; |
||
7786 | else if (IS_I915GM(dev)) |
||
7787 | dev_priv->display.get_display_clock_speed = |
||
7788 | i915gm_get_display_clock_speed; |
||
7789 | else if (IS_I865G(dev)) |
||
7790 | dev_priv->display.get_display_clock_speed = |
||
7791 | i865_get_display_clock_speed; |
||
7792 | else if (IS_I85X(dev)) |
||
7793 | dev_priv->display.get_display_clock_speed = |
||
7794 | i855_get_display_clock_speed; |
||
7795 | else /* 852, 830 */ |
||
7796 | dev_priv->display.get_display_clock_speed = |
||
7797 | i830_get_display_clock_speed; |
||
2327 | Serge | 7798 | |
3031 | serge | 7799 | if (HAS_PCH_SPLIT(dev)) { |
7800 | if (IS_GEN5(dev)) { |
||
7801 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
||
7802 | dev_priv->display.write_eld = ironlake_write_eld; |
||
7803 | } else if (IS_GEN6(dev)) { |
||
7804 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
||
7805 | dev_priv->display.write_eld = ironlake_write_eld; |
||
7806 | } else if (IS_IVYBRIDGE(dev)) { |
||
7807 | /* FIXME: detect B0+ stepping and use auto training */ |
||
7808 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
||
7809 | dev_priv->display.write_eld = ironlake_write_eld; |
||
7810 | } else if (IS_HASWELL(dev)) { |
||
7811 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
||
7812 | dev_priv->display.write_eld = haswell_write_eld; |
||
7813 | } else |
||
7814 | dev_priv->display.update_wm = NULL; |
||
7815 | } else if (IS_G4X(dev)) { |
||
7816 | dev_priv->display.write_eld = g4x_write_eld; |
||
7817 | } |
||
2327 | Serge | 7818 | |
3031 | serge | 7819 | /* Default just returns -ENODEV to indicate unsupported */ |
7820 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
||
2327 | Serge | 7821 | |
7822 | |||
7823 | |||
7824 | |||
3031 | serge | 7825 | } |
7826 | |||
7827 | /* |
||
7828 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
||
7829 | * resume, or other times. This quirk makes sure that's the case for |
||
7830 | * affected systems. |
||
7831 | */ |
||
7832 | static void quirk_pipea_force(struct drm_device *dev) |
||
2330 | Serge | 7833 | { |
7834 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2327 | Serge | 7835 | |
3031 | serge | 7836 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
7837 | DRM_INFO("applying pipe a force quirk\n"); |
||
7838 | } |
||
2327 | Serge | 7839 | |
3031 | serge | 7840 | /* |
7841 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
||
7842 | */ |
||
7843 | static void quirk_ssc_force_disable(struct drm_device *dev) |
||
7844 | { |
||
7845 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
7846 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
||
7847 | DRM_INFO("applying lvds SSC disable quirk\n"); |
||
2330 | Serge | 7848 | } |
2327 | Serge | 7849 | |
3031 | serge | 7850 | /* |
7851 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
||
7852 | * brightness value |
||
7853 | */ |
||
7854 | static void quirk_invert_brightness(struct drm_device *dev) |
||
2330 | Serge | 7855 | { |
7856 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 7857 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
7858 | DRM_INFO("applying inverted panel brightness quirk\n"); |
||
7859 | } |
||
2327 | Serge | 7860 | |
3031 | serge | 7861 | struct intel_quirk { |
7862 | int device; |
||
7863 | int subsystem_vendor; |
||
7864 | int subsystem_device; |
||
7865 | void (*hook)(struct drm_device *dev); |
||
7866 | }; |
||
2327 | Serge | 7867 | |
3031 | serge | 7868 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
7869 | struct intel_dmi_quirk { |
||
7870 | void (*hook)(struct drm_device *dev); |
||
7871 | const struct dmi_system_id (*dmi_id_list)[]; |
||
7872 | }; |
||
2327 | Serge | 7873 | |
3031 | serge | 7874 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
7875 | { |
||
7876 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
||
7877 | return 1; |
||
2330 | Serge | 7878 | } |
2327 | Serge | 7879 | |
3031 | serge | 7880 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
7881 | { |
||
7882 | .dmi_id_list = &(const struct dmi_system_id[]) { |
||
7883 | { |
||
7884 | .callback = intel_dmi_reverse_brightness, |
||
7885 | .ident = "NCR Corporation", |
||
7886 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
||
7887 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
||
7888 | }, |
||
7889 | }, |
||
7890 | { } /* terminating entry */ |
||
7891 | }, |
||
7892 | .hook = quirk_invert_brightness, |
||
7893 | }, |
||
7894 | }; |
||
2327 | Serge | 7895 | |
3031 | serge | 7896 | static struct intel_quirk intel_quirks[] = { |
7897 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
||
7898 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
||
2327 | Serge | 7899 | |
3031 | serge | 7900 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
7901 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
||
2327 | Serge | 7902 | |
3031 | serge | 7903 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
7904 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
||
2327 | Serge | 7905 | |
3031 | serge | 7906 | /* 830/845 need to leave pipe A & dpll A up */ |
7907 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
||
7908 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
||
2327 | Serge | 7909 | |
3031 | serge | 7910 | /* Lenovo U160 cannot use SSC on LVDS */ |
7911 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
||
2327 | Serge | 7912 | |
3031 | serge | 7913 | /* Sony Vaio Y cannot use SSC on LVDS */ |
7914 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
||
2327 | Serge | 7915 | |
3031 | serge | 7916 | /* Acer Aspire 5734Z must invert backlight brightness */ |
7917 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
||
7918 | }; |
||
2327 | Serge | 7919 | |
3031 | serge | 7920 | static void intel_init_quirks(struct drm_device *dev) |
2330 | Serge | 7921 | { |
3031 | serge | 7922 | struct pci_dev *d = dev->pdev; |
7923 | int i; |
||
2327 | Serge | 7924 | |
3031 | serge | 7925 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
7926 | struct intel_quirk *q = &intel_quirks[i]; |
||
2327 | Serge | 7927 | |
3031 | serge | 7928 | if (d->device == q->device && |
7929 | (d->subsystem_vendor == q->subsystem_vendor || |
||
7930 | q->subsystem_vendor == PCI_ANY_ID) && |
||
7931 | (d->subsystem_device == q->subsystem_device || |
||
7932 | q->subsystem_device == PCI_ANY_ID)) |
||
7933 | q->hook(dev); |
||
7934 | } |
||
7935 | // for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
||
7936 | // if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
||
7937 | // intel_dmi_quirks[i].hook(dev); |
||
7938 | // } |
||
2330 | Serge | 7939 | } |
2327 | Serge | 7940 | |
3031 | serge | 7941 | /* Disable the VGA plane that we never use */ |
7942 | static void i915_disable_vga(struct drm_device *dev) |
||
2330 | Serge | 7943 | { |
7944 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 7945 | u8 sr1; |
7946 | u32 vga_reg; |
||
2327 | Serge | 7947 | |
3031 | serge | 7948 | if (HAS_PCH_SPLIT(dev)) |
7949 | vga_reg = CPU_VGACNTRL; |
||
7950 | else |
||
7951 | vga_reg = VGACNTRL; |
||
2327 | Serge | 7952 | |
3031 | serge | 7953 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
7954 | out8(SR01, VGA_SR_INDEX); |
||
7955 | sr1 = in8(VGA_SR_DATA); |
||
7956 | out8(sr1 | 1<<5, VGA_SR_DATA); |
||
7957 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
||
7958 | udelay(300); |
||
2327 | Serge | 7959 | |
3031 | serge | 7960 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
7961 | POSTING_READ(vga_reg); |
||
2330 | Serge | 7962 | } |
7963 | |||
3031 | serge | 7964 | void intel_modeset_init_hw(struct drm_device *dev) |
2342 | Serge | 7965 | { |
3031 | serge | 7966 | /* We attempt to init the necessary power wells early in the initialization |
7967 | * time, so the subsystems that expect power to be enabled can work. |
||
2342 | Serge | 7968 | */ |
3031 | serge | 7969 | intel_init_power_wells(dev); |
2342 | Serge | 7970 | |
3031 | serge | 7971 | intel_prepare_ddi(dev); |
2342 | Serge | 7972 | |
3031 | serge | 7973 | intel_init_clock_gating(dev); |
7974 | |||
7975 | // mutex_lock(&dev->struct_mutex); |
||
7976 | // intel_enable_gt_powersave(dev); |
||
7977 | // mutex_unlock(&dev->struct_mutex); |
||
2342 | Serge | 7978 | } |
7979 | |||
3031 | serge | 7980 | void intel_modeset_init(struct drm_device *dev) |
2330 | Serge | 7981 | { |
3031 | serge | 7982 | struct drm_i915_private *dev_priv = dev->dev_private; |
7983 | int i, ret; |
||
2330 | Serge | 7984 | |
3031 | serge | 7985 | drm_mode_config_init(dev); |
2330 | Serge | 7986 | |
3031 | serge | 7987 | dev->mode_config.min_width = 0; |
7988 | dev->mode_config.min_height = 0; |
||
2330 | Serge | 7989 | |
3031 | serge | 7990 | dev->mode_config.preferred_depth = 24; |
7991 | dev->mode_config.prefer_shadow = 1; |
||
2330 | Serge | 7992 | |
3031 | serge | 7993 | dev->mode_config.funcs = &intel_mode_funcs; |
2330 | Serge | 7994 | |
3031 | serge | 7995 | intel_init_quirks(dev); |
2330 | Serge | 7996 | |
3031 | serge | 7997 | intel_init_pm(dev); |
2330 | Serge | 7998 | |
3031 | serge | 7999 | intel_init_display(dev); |
2330 | Serge | 8000 | |
3031 | serge | 8001 | if (IS_GEN2(dev)) { |
8002 | dev->mode_config.max_width = 2048; |
||
8003 | dev->mode_config.max_height = 2048; |
||
8004 | } else if (IS_GEN3(dev)) { |
||
8005 | dev->mode_config.max_width = 4096; |
||
8006 | dev->mode_config.max_height = 4096; |
||
8007 | } else { |
||
8008 | dev->mode_config.max_width = 8192; |
||
8009 | dev->mode_config.max_height = 8192; |
||
8010 | } |
||
8011 | dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr; |
||
2330 | Serge | 8012 | |
3031 | serge | 8013 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
8014 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
||
2330 | Serge | 8015 | |
3031 | serge | 8016 | for (i = 0; i < dev_priv->num_pipe; i++) { |
8017 | intel_crtc_init(dev, i); |
||
8018 | ret = intel_plane_init(dev, i); |
||
8019 | if (ret) |
||
8020 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); |
||
2330 | Serge | 8021 | } |
8022 | |||
3031 | serge | 8023 | intel_pch_pll_init(dev); |
2330 | Serge | 8024 | |
3031 | serge | 8025 | /* Just disable it once at startup */ |
8026 | i915_disable_vga(dev); |
||
8027 | intel_setup_outputs(dev); |
||
8028 | } |
||
2330 | Serge | 8029 | |
3031 | serge | 8030 | static void |
8031 | intel_connector_break_all_links(struct intel_connector *connector) |
||
8032 | { |
||
8033 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
||
8034 | connector->base.encoder = NULL; |
||
8035 | connector->encoder->connectors_active = false; |
||
8036 | connector->encoder->base.crtc = NULL; |
||
2330 | Serge | 8037 | } |
8038 | |||
3031 | serge | 8039 | static void intel_enable_pipe_a(struct drm_device *dev) |
2330 | Serge | 8040 | { |
3031 | serge | 8041 | struct intel_connector *connector; |
8042 | struct drm_connector *crt = NULL; |
||
8043 | struct intel_load_detect_pipe load_detect_temp; |
||
2330 | Serge | 8044 | |
3031 | serge | 8045 | /* We can't just switch on the pipe A, we need to set things up with a |
8046 | * proper mode and output configuration. As a gross hack, enable pipe A |
||
8047 | * by enabling the load detect pipe once. */ |
||
8048 | list_for_each_entry(connector, |
||
8049 | &dev->mode_config.connector_list, |
||
8050 | base.head) { |
||
8051 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
||
8052 | crt = &connector->base; |
||
8053 | break; |
||
2330 | Serge | 8054 | } |
8055 | } |
||
8056 | |||
3031 | serge | 8057 | if (!crt) |
8058 | return; |
||
2330 | Serge | 8059 | |
3031 | serge | 8060 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
8061 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
||
2327 | Serge | 8062 | |
8063 | |||
8064 | } |
||
8065 | |||
3031 | serge | 8066 | static bool |
8067 | intel_check_plane_mapping(struct intel_crtc *crtc) |
||
2327 | Serge | 8068 | { |
3031 | serge | 8069 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8070 | u32 reg, val; |
||
2327 | Serge | 8071 | |
3031 | serge | 8072 | if (dev_priv->num_pipe == 1) |
8073 | return true; |
||
2327 | Serge | 8074 | |
3031 | serge | 8075 | reg = DSPCNTR(!crtc->plane); |
8076 | val = I915_READ(reg); |
||
2327 | Serge | 8077 | |
3031 | serge | 8078 | if ((val & DISPLAY_PLANE_ENABLE) && |
8079 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
||
8080 | return false; |
||
2327 | Serge | 8081 | |
3031 | serge | 8082 | return true; |
2327 | Serge | 8083 | } |
8084 | |||
3031 | serge | 8085 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
2327 | Serge | 8086 | { |
3031 | serge | 8087 | struct drm_device *dev = crtc->base.dev; |
2327 | Serge | 8088 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 8089 | u32 reg; |
2327 | Serge | 8090 | |
3031 | serge | 8091 | /* Clear any frame start delays used for debugging left by the BIOS */ |
8092 | reg = PIPECONF(crtc->pipe); |
||
8093 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
||
2327 | Serge | 8094 | |
3031 | serge | 8095 | /* We need to sanitize the plane -> pipe mapping first because this will |
8096 | * disable the crtc (and hence change the state) if it is wrong. Note |
||
8097 | * that gen4+ has a fixed plane -> pipe mapping. */ |
||
8098 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
||
8099 | struct intel_connector *connector; |
||
8100 | bool plane; |
||
2327 | Serge | 8101 | |
3031 | serge | 8102 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
8103 | crtc->base.base.id); |
||
2327 | Serge | 8104 | |
3031 | serge | 8105 | /* Pipe has the wrong plane attached and the plane is active. |
8106 | * Temporarily change the plane mapping and disable everything |
||
8107 | * ... */ |
||
8108 | plane = crtc->plane; |
||
8109 | crtc->plane = !plane; |
||
8110 | dev_priv->display.crtc_disable(&crtc->base); |
||
8111 | crtc->plane = plane; |
||
2342 | Serge | 8112 | |
3031 | serge | 8113 | /* ... and break all links. */ |
8114 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
||
8115 | base.head) { |
||
8116 | if (connector->encoder->base.crtc != &crtc->base) |
||
8117 | continue; |
||
2327 | Serge | 8118 | |
3031 | serge | 8119 | intel_connector_break_all_links(connector); |
8120 | } |
||
2327 | Serge | 8121 | |
3031 | serge | 8122 | WARN_ON(crtc->active); |
8123 | crtc->base.enabled = false; |
||
8124 | } |
||
2327 | Serge | 8125 | |
3031 | serge | 8126 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
8127 | crtc->pipe == PIPE_A && !crtc->active) { |
||
8128 | /* BIOS forgot to enable pipe A, this mostly happens after |
||
8129 | * resume. Force-enable the pipe to fix this, the update_dpms |
||
8130 | * call below we restore the pipe to the right state, but leave |
||
8131 | * the required bits on. */ |
||
8132 | intel_enable_pipe_a(dev); |
||
8133 | } |
||
2327 | Serge | 8134 | |
3031 | serge | 8135 | /* Adjust the state of the output pipe according to whether we |
8136 | * have active connectors/encoders. */ |
||
8137 | intel_crtc_update_dpms(&crtc->base); |
||
2327 | Serge | 8138 | |
3031 | serge | 8139 | if (crtc->active != crtc->base.enabled) { |
8140 | struct intel_encoder *encoder; |
||
2327 | Serge | 8141 | |
3031 | serge | 8142 | /* This can happen either due to bugs in the get_hw_state |
8143 | * functions or because the pipe is force-enabled due to the |
||
8144 | * pipe A quirk. */ |
||
8145 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
||
8146 | crtc->base.base.id, |
||
8147 | crtc->base.enabled ? "enabled" : "disabled", |
||
8148 | crtc->active ? "enabled" : "disabled"); |
||
2327 | Serge | 8149 | |
3031 | serge | 8150 | crtc->base.enabled = crtc->active; |
2327 | Serge | 8151 | |
3031 | serge | 8152 | /* Because we only establish the connector -> encoder -> |
8153 | * crtc links if something is active, this means the |
||
8154 | * crtc is now deactivated. Break the links. connector |
||
8155 | * -> encoder links are only establish when things are |
||
8156 | * actually up, hence no need to break them. */ |
||
8157 | WARN_ON(crtc->active); |
||
2327 | Serge | 8158 | |
3031 | serge | 8159 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
8160 | WARN_ON(encoder->connectors_active); |
||
8161 | encoder->base.crtc = NULL; |
||
8162 | } |
||
8163 | } |
||
2327 | Serge | 8164 | } |
8165 | |||
3031 | serge | 8166 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
2327 | Serge | 8167 | { |
3031 | serge | 8168 | struct intel_connector *connector; |
8169 | struct drm_device *dev = encoder->base.dev; |
||
2327 | Serge | 8170 | |
3031 | serge | 8171 | /* We need to check both for a crtc link (meaning that the |
8172 | * encoder is active and trying to read from a pipe) and the |
||
8173 | * pipe itself being active. */ |
||
8174 | bool has_active_crtc = encoder->base.crtc && |
||
8175 | to_intel_crtc(encoder->base.crtc)->active; |
||
2327 | Serge | 8176 | |
3031 | serge | 8177 | if (encoder->connectors_active && !has_active_crtc) { |
8178 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
||
8179 | encoder->base.base.id, |
||
8180 | drm_get_encoder_name(&encoder->base)); |
||
2327 | Serge | 8181 | |
3031 | serge | 8182 | /* Connector is active, but has no active pipe. This is |
8183 | * fallout from our resume register restoring. Disable |
||
8184 | * the encoder manually again. */ |
||
8185 | if (encoder->base.crtc) { |
||
8186 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
||
8187 | encoder->base.base.id, |
||
8188 | drm_get_encoder_name(&encoder->base)); |
||
8189 | encoder->disable(encoder); |
||
8190 | } |
||
2327 | Serge | 8191 | |
3031 | serge | 8192 | /* Inconsistent output/port/pipe state happens presumably due to |
8193 | * a bug in one of the get_hw_state functions. Or someplace else |
||
8194 | * in our code, like the register restore mess on resume. Clamp |
||
8195 | * things to off as a safer default. */ |
||
8196 | list_for_each_entry(connector, |
||
8197 | &dev->mode_config.connector_list, |
||
8198 | base.head) { |
||
8199 | if (connector->encoder != encoder) |
||
8200 | continue; |
||
2327 | Serge | 8201 | |
3031 | serge | 8202 | intel_connector_break_all_links(connector); |
8203 | } |
||
8204 | } |
||
8205 | /* Enabled encoders without active connectors will be fixed in |
||
8206 | * the crtc fixup. */ |
||
2327 | Serge | 8207 | } |
8208 | |||
3031 | serge | 8209 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
8210 | * and i915 state tracking structures. */ |
||
8211 | void intel_modeset_setup_hw_state(struct drm_device *dev) |
||
2332 | Serge | 8212 | { |
8213 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 8214 | enum pipe pipe; |
8215 | u32 tmp; |
||
8216 | struct intel_crtc *crtc; |
||
8217 | struct intel_encoder *encoder; |
||
8218 | struct intel_connector *connector; |
||
2327 | Serge | 8219 | |
3031 | serge | 8220 | for_each_pipe(pipe) { |
8221 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
||
2327 | Serge | 8222 | |
3031 | serge | 8223 | tmp = I915_READ(PIPECONF(pipe)); |
8224 | if (tmp & PIPECONF_ENABLE) |
||
8225 | crtc->active = true; |
||
8226 | else |
||
8227 | crtc->active = false; |
||
2327 | Serge | 8228 | |
3031 | serge | 8229 | crtc->base.enabled = crtc->active; |
2330 | Serge | 8230 | |
3031 | serge | 8231 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
8232 | crtc->base.base.id, |
||
8233 | crtc->active ? "enabled" : "disabled"); |
||
2339 | Serge | 8234 | } |
2332 | Serge | 8235 | |
3031 | serge | 8236 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8237 | base.head) { |
||
8238 | pipe = 0; |
||
2332 | Serge | 8239 | |
3031 | serge | 8240 | if (encoder->get_hw_state(encoder, &pipe)) { |
8241 | encoder->base.crtc = |
||
8242 | dev_priv->pipe_to_crtc_mapping[pipe]; |
||
8243 | } else { |
||
8244 | encoder->base.crtc = NULL; |
||
8245 | } |
||
2332 | Serge | 8246 | |
3031 | serge | 8247 | encoder->connectors_active = false; |
8248 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
||
8249 | encoder->base.base.id, |
||
8250 | drm_get_encoder_name(&encoder->base), |
||
8251 | encoder->base.crtc ? "enabled" : "disabled", |
||
8252 | pipe); |
||
8253 | } |
||
2332 | Serge | 8254 | |
3031 | serge | 8255 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8256 | base.head) { |
||
8257 | if (connector->get_hw_state(connector)) { |
||
8258 | connector->base.dpms = DRM_MODE_DPMS_ON; |
||
8259 | connector->encoder->connectors_active = true; |
||
8260 | connector->base.encoder = &connector->encoder->base; |
||
8261 | } else { |
||
8262 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
||
8263 | connector->base.encoder = NULL; |
||
8264 | } |
||
8265 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
||
8266 | connector->base.base.id, |
||
8267 | drm_get_connector_name(&connector->base), |
||
8268 | connector->base.encoder ? "enabled" : "disabled"); |
||
2332 | Serge | 8269 | } |
8270 | |||
3031 | serge | 8271 | /* HW state is read out, now we need to sanitize this mess. */ |
8272 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
||
8273 | base.head) { |
||
8274 | intel_sanitize_encoder(encoder); |
||
2332 | Serge | 8275 | } |
8276 | |||
3031 | serge | 8277 | for_each_pipe(pipe) { |
8278 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
||
8279 | intel_sanitize_crtc(crtc); |
||
2332 | Serge | 8280 | } |
8281 | |||
3031 | serge | 8282 | intel_modeset_update_staged_output_state(dev); |
2332 | Serge | 8283 | |
3031 | serge | 8284 | intel_modeset_check_state(dev); |
2332 | Serge | 8285 | } |
8286 | |||
3031 | serge | 8287 | void intel_modeset_gem_init(struct drm_device *dev) |
2330 | Serge | 8288 | { |
3031 | serge | 8289 | intel_modeset_init_hw(dev); |
2330 | Serge | 8290 | |
3031 | serge | 8291 | // intel_setup_overlay(dev); |
2330 | Serge | 8292 | |
3031 | serge | 8293 | intel_modeset_setup_hw_state(dev); |
2330 | Serge | 8294 | } |
8295 | |||
3031 | serge | 8296 | void intel_modeset_cleanup(struct drm_device *dev) |
2327 | Serge | 8297 | { |
3031 | serge | 8298 | #if 0 |
8299 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
8300 | struct drm_crtc *crtc; |
||
8301 | struct intel_crtc *intel_crtc; |
||
2327 | Serge | 8302 | |
3031 | serge | 8303 | // drm_kms_helper_poll_fini(dev); |
8304 | mutex_lock(&dev->struct_mutex); |
||
2327 | Serge | 8305 | |
3031 | serge | 8306 | // intel_unregister_dsm_handler(); |
2327 | Serge | 8307 | |
8308 | |||
3031 | serge | 8309 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8310 | /* Skip inactive CRTCs */ |
||
8311 | if (!crtc->fb) |
||
8312 | continue; |
||
2342 | Serge | 8313 | |
3031 | serge | 8314 | intel_crtc = to_intel_crtc(crtc); |
8315 | intel_increase_pllclock(crtc); |
||
8316 | } |
||
2342 | Serge | 8317 | |
3031 | serge | 8318 | intel_disable_fbc(dev); |
2342 | Serge | 8319 | |
3031 | serge | 8320 | intel_disable_gt_powersave(dev); |
2342 | Serge | 8321 | |
3031 | serge | 8322 | ironlake_teardown_rc6(dev); |
2327 | Serge | 8323 | |
3031 | serge | 8324 | if (IS_VALLEYVIEW(dev)) |
8325 | vlv_init_dpio(dev); |
||
2327 | Serge | 8326 | |
3031 | serge | 8327 | mutex_unlock(&dev->struct_mutex); |
2327 | Serge | 8328 | |
3031 | serge | 8329 | /* Disable the irq before mode object teardown, for the irq might |
8330 | * enqueue unpin/hotplug work. */ |
||
8331 | // drm_irq_uninstall(dev); |
||
8332 | // cancel_work_sync(&dev_priv->hotplug_work); |
||
8333 | // cancel_work_sync(&dev_priv->rps.work); |
||
2327 | Serge | 8334 | |
3031 | serge | 8335 | /* flush any delayed tasks or pending work */ |
8336 | // flush_scheduled_work(); |
||
2327 | Serge | 8337 | |
3031 | serge | 8338 | drm_mode_config_cleanup(dev); |
2327 | Serge | 8339 | #endif |
8340 | } |
||
8341 | |||
8342 | /* |
||
3031 | serge | 8343 | * Return which encoder is currently attached for connector. |
2327 | Serge | 8344 | */ |
3031 | serge | 8345 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
2327 | Serge | 8346 | { |
3031 | serge | 8347 | return &intel_attached_encoder(connector)->base; |
8348 | } |
||
2327 | Serge | 8349 | |
3031 | serge | 8350 | void intel_connector_attach_encoder(struct intel_connector *connector, |
8351 | struct intel_encoder *encoder) |
||
8352 | { |
||
8353 | connector->encoder = encoder; |
||
8354 | drm_mode_connector_attach_encoder(&connector->base, |
||
8355 | &encoder->base); |
||
2327 | Serge | 8356 | } |
8357 | |||
8358 | /* |
||
3031 | serge | 8359 | * set vga decode state - true == enable VGA decode |
2327 | Serge | 8360 | */ |
3031 | serge | 8361 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
2327 | Serge | 8362 | { |
2330 | Serge | 8363 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 8364 | u16 gmch_ctrl; |
2327 | Serge | 8365 | |
3031 | serge | 8366 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
8367 | if (state) |
||
8368 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
||
2330 | Serge | 8369 | else |
3031 | serge | 8370 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
8371 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
||
8372 | return 0; |
||
2330 | Serge | 8373 | } |
8374 | |||
3031 | serge | 8375 | #ifdef CONFIG_DEBUG_FS |
8376 | #include |
||
2327 | Serge | 8377 | |
3031 | serge | 8378 | struct intel_display_error_state { |
8379 | struct intel_cursor_error_state { |
||
8380 | u32 control; |
||
8381 | u32 position; |
||
8382 | u32 base; |
||
8383 | u32 size; |
||
8384 | } cursor[I915_MAX_PIPES]; |
||
2327 | Serge | 8385 | |
3031 | serge | 8386 | struct intel_pipe_error_state { |
8387 | u32 conf; |
||
8388 | u32 source; |
||
2327 | Serge | 8389 | |
3031 | serge | 8390 | u32 htotal; |
8391 | u32 hblank; |
||
8392 | u32 hsync; |
||
8393 | u32 vtotal; |
||
8394 | u32 vblank; |
||
8395 | u32 vsync; |
||
8396 | } pipe[I915_MAX_PIPES]; |
||
2327 | Serge | 8397 | |
3031 | serge | 8398 | struct intel_plane_error_state { |
8399 | u32 control; |
||
8400 | u32 stride; |
||
8401 | u32 size; |
||
8402 | u32 pos; |
||
8403 | u32 addr; |
||
8404 | u32 surface; |
||
8405 | u32 tile_offset; |
||
8406 | } plane[I915_MAX_PIPES]; |
||
8407 | }; |
||
2327 | Serge | 8408 | |
3031 | serge | 8409 | struct intel_display_error_state * |
8410 | intel_display_capture_error_state(struct drm_device *dev) |
||
8411 | { |
||
8412 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
8413 | struct intel_display_error_state *error; |
||
8414 | int i; |
||
2327 | Serge | 8415 | |
3031 | serge | 8416 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
8417 | if (error == NULL) |
||
8418 | return NULL; |
||
2327 | Serge | 8419 | |
3031 | serge | 8420 | for_each_pipe(i) { |
8421 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
||
8422 | error->cursor[i].position = I915_READ(CURPOS(i)); |
||
8423 | error->cursor[i].base = I915_READ(CURBASE(i)); |
||
2327 | Serge | 8424 | |
3031 | serge | 8425 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
8426 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
||
8427 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
||
8428 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
||
8429 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
||
8430 | if (INTEL_INFO(dev)->gen >= 4) { |
||
8431 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
||
8432 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
||
8433 | } |
||
2327 | Serge | 8434 | |
3031 | serge | 8435 | error->pipe[i].conf = I915_READ(PIPECONF(i)); |
8436 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
||
8437 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); |
||
8438 | error->pipe[i].hblank = I915_READ(HBLANK(i)); |
||
8439 | error->pipe[i].hsync = I915_READ(HSYNC(i)); |
||
8440 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); |
||
8441 | error->pipe[i].vblank = I915_READ(VBLANK(i)); |
||
8442 | error->pipe[i].vsync = I915_READ(VSYNC(i)); |
||
8443 | } |
||
2327 | Serge | 8444 | |
3031 | serge | 8445 | return error; |
2330 | Serge | 8446 | } |
2327 | Serge | 8447 | |
3031 | serge | 8448 | void |
8449 | intel_display_print_error_state(struct seq_file *m, |
||
8450 | struct drm_device *dev, |
||
8451 | struct intel_display_error_state *error) |
||
2332 | Serge | 8452 | { |
3031 | serge | 8453 | drm_i915_private_t *dev_priv = dev->dev_private; |
8454 | int i; |
||
2330 | Serge | 8455 | |
3031 | serge | 8456 | seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe); |
8457 | for_each_pipe(i) { |
||
8458 | seq_printf(m, "Pipe [%d]:\n", i); |
||
8459 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); |
||
8460 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); |
||
8461 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); |
||
8462 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); |
||
8463 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); |
||
8464 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); |
||
8465 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); |
||
8466 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); |
||
2332 | Serge | 8467 | |
3031 | serge | 8468 | seq_printf(m, "Plane [%d]:\n", i); |
8469 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); |
||
8470 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
||
8471 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); |
||
8472 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); |
||
8473 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
||
8474 | if (INTEL_INFO(dev)->gen >= 4) { |
||
8475 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); |
||
8476 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
||
8477 | } |
||
2332 | Serge | 8478 | |
3031 | serge | 8479 | seq_printf(m, "Cursor [%d]:\n", i); |
8480 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
||
8481 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); |
||
8482 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); |
||
8483 | } |
||
2327 | Serge | 8484 | } |
3031 | serge | 8485 | #endif>>5,><5,>>>><>><>>>>>(intel_crtc)-><(intel_crtc)->><>><>><>><>><>><>><>><>=><=>><>><>><>><>>>>>><>><>><>><>>><>><>>>><>><>>>><>><>><>><>>>><>><>><>><>>><>><>><>><>>>><>><>><>><>><>><>><>>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>20)><20)>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=>>>>>>>>><>><>><>><>><>><>><>><>><>>>><>><>>>>>>>><>><>>>><>><>><>>><>><>>>>><>><>><>>>>>=>=>>>>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |