WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
		27	//#include
		28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
2327	Serge	33	//#include
		34	#include "drmP.h"
		35	#include "intel_drv.h"
2330	Serge	36	#include "i915_drm.h"
2327	Serge	37	#include "i915_drv.h"
		38	//#include "i915_trace.h"
		39	#include "drm_dp_helper.h"
		40
		41	#include "drm_crtc_helper.h"
		42
		43	phys_addr_t get_bus_addr(void);
		44
		45	static inline __attribute__((const))
		46	bool is_power_of_2(unsigned long n)
		47	{
		48	return (n != 0 && ((n & (n - 1)) == 0));
		49	}
		50
2330	Serge	51	#define MAX_ERRNO 4095
		52
		53	#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
		54
		55	static inline long IS_ERR(const void *ptr)
		56	{
		57	return IS_ERR_VALUE((unsigned long)ptr);
		58	}
		59
		60	static inline void *ERR_PTR(long error)
		61	{
		62	return (void *) error;
		63	}
		64
		65
2327	Serge	66	static inline int pci_read_config_word(struct pci_dev *dev, int where,
		67	u16 *val)
		68	{
		69	*val = PciRead16(dev->busnr, dev->devfn, where);
		70	return 1;
		71	}
		72
		73
		74	#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
		75
		76	bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
		77	static void intel_update_watermarks(struct drm_device *dev);
		78	static void intel_increase_pllclock(struct drm_crtc *crtc);
		79	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
		80
		81	typedef struct {
		82	/* given values */
		83	int n;
		84	int m1, m2;
		85	int p1, p2;
		86	/* derived values */
		87	int dot;
		88	int vco;
		89	int m;
		90	int p;
		91	} intel_clock_t;
		92
		93	typedef struct {
		94	int min, max;
		95	} intel_range_t;
		96
		97	typedef struct {
		98	int dot_limit;
		99	int p2_slow, p2_fast;
		100	} intel_p2_t;
		101
		102	#define INTEL_P2_NUM 2
		103	typedef struct intel_limit intel_limit_t;
		104	struct intel_limit {
		105	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		106	intel_p2_t p2;
		107	bool (* find_pll)(const intel_limit_t , struct drm_crtc ,
		108	int, int, intel_clock_t *);
		109	};
		110
		111	/* FDI */
		112	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		113
		114	static bool
		115	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
		116	int target, int refclk, intel_clock_t *best_clock);
		117	static bool
		118	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
		119	int target, int refclk, intel_clock_t *best_clock);
		120
		121	static bool
		122	intel_find_pll_g4x_dp(const intel_limit_t , struct drm_crtc crtc,
		123	int target, int refclk, intel_clock_t *best_clock);
		124	static bool
		125	intel_find_pll_ironlake_dp(const intel_limit_t , struct drm_crtc crtc,
		126	int target, int refclk, intel_clock_t *best_clock);
		127
		128	static inline u32 /* units of 100MHz */
		129	intel_fdi_link_freq(struct drm_device *dev)
		130	{
		131	if (IS_GEN5(dev)) {
		132	struct drm_i915_private *dev_priv = dev->dev_private;
		133	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		134	} else
		135	return 27;
		136	}
		137
		138	static const intel_limit_t intel_limits_i8xx_dvo = {
		139	.dot = { .min = 25000, .max = 350000 },
		140	.vco = { .min = 930000, .max = 1400000 },
		141	.n = { .min = 3, .max = 16 },
		142	.m = { .min = 96, .max = 140 },
		143	.m1 = { .min = 18, .max = 26 },
		144	.m2 = { .min = 6, .max = 16 },
		145	.p = { .min = 4, .max = 128 },
		146	.p1 = { .min = 2, .max = 33 },
		147	.p2 = { .dot_limit = 165000,
		148	.p2_slow = 4, .p2_fast = 2 },
		149	.find_pll = intel_find_best_PLL,
		150	};
		151
		152	static const intel_limit_t intel_limits_i8xx_lvds = {
		153	.dot = { .min = 25000, .max = 350000 },
		154	.vco = { .min = 930000, .max = 1400000 },
		155	.n = { .min = 3, .max = 16 },
		156	.m = { .min = 96, .max = 140 },
		157	.m1 = { .min = 18, .max = 26 },
		158	.m2 = { .min = 6, .max = 16 },
		159	.p = { .min = 4, .max = 128 },
		160	.p1 = { .min = 1, .max = 6 },
		161	.p2 = { .dot_limit = 165000,
		162	.p2_slow = 14, .p2_fast = 7 },
		163	.find_pll = intel_find_best_PLL,
		164	};
		165
		166	static const intel_limit_t intel_limits_i9xx_sdvo = {
		167	.dot = { .min = 20000, .max = 400000 },
		168	.vco = { .min = 1400000, .max = 2800000 },
		169	.n = { .min = 1, .max = 6 },
		170	.m = { .min = 70, .max = 120 },
		171	.m1 = { .min = 10, .max = 22 },
		172	.m2 = { .min = 5, .max = 9 },
		173	.p = { .min = 5, .max = 80 },
		174	.p1 = { .min = 1, .max = 8 },
		175	.p2 = { .dot_limit = 200000,
		176	.p2_slow = 10, .p2_fast = 5 },
		177	.find_pll = intel_find_best_PLL,
		178	};
		179
		180	static const intel_limit_t intel_limits_i9xx_lvds = {
		181	.dot = { .min = 20000, .max = 400000 },
		182	.vco = { .min = 1400000, .max = 2800000 },
		183	.n = { .min = 1, .max = 6 },
		184	.m = { .min = 70, .max = 120 },
		185	.m1 = { .min = 10, .max = 22 },
		186	.m2 = { .min = 5, .max = 9 },
		187	.p = { .min = 7, .max = 98 },
		188	.p1 = { .min = 1, .max = 8 },
		189	.p2 = { .dot_limit = 112000,
		190	.p2_slow = 14, .p2_fast = 7 },
		191	.find_pll = intel_find_best_PLL,
		192	};
		193
		194
		195	static const intel_limit_t intel_limits_g4x_sdvo = {
		196	.dot = { .min = 25000, .max = 270000 },
		197	.vco = { .min = 1750000, .max = 3500000},
		198	.n = { .min = 1, .max = 4 },
		199	.m = { .min = 104, .max = 138 },
		200	.m1 = { .min = 17, .max = 23 },
		201	.m2 = { .min = 5, .max = 11 },
		202	.p = { .min = 10, .max = 30 },
		203	.p1 = { .min = 1, .max = 3},
		204	.p2 = { .dot_limit = 270000,
		205	.p2_slow = 10,
		206	.p2_fast = 10
		207	},
		208	.find_pll = intel_g4x_find_best_PLL,
		209	};
		210
		211	static const intel_limit_t intel_limits_g4x_hdmi = {
		212	.dot = { .min = 22000, .max = 400000 },
		213	.vco = { .min = 1750000, .max = 3500000},
		214	.n = { .min = 1, .max = 4 },
		215	.m = { .min = 104, .max = 138 },
		216	.m1 = { .min = 16, .max = 23 },
		217	.m2 = { .min = 5, .max = 11 },
		218	.p = { .min = 5, .max = 80 },
		219	.p1 = { .min = 1, .max = 8},
		220	.p2 = { .dot_limit = 165000,
		221	.p2_slow = 10, .p2_fast = 5 },
		222	.find_pll = intel_g4x_find_best_PLL,
		223	};
		224
		225	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		226	.dot = { .min = 20000, .max = 115000 },
		227	.vco = { .min = 1750000, .max = 3500000 },
		228	.n = { .min = 1, .max = 3 },
		229	.m = { .min = 104, .max = 138 },
		230	.m1 = { .min = 17, .max = 23 },
		231	.m2 = { .min = 5, .max = 11 },
		232	.p = { .min = 28, .max = 112 },
		233	.p1 = { .min = 2, .max = 8 },
		234	.p2 = { .dot_limit = 0,
		235	.p2_slow = 14, .p2_fast = 14
		236	},
		237	.find_pll = intel_g4x_find_best_PLL,
		238	};
		239
		240	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		241	.dot = { .min = 80000, .max = 224000 },
		242	.vco = { .min = 1750000, .max = 3500000 },
		243	.n = { .min = 1, .max = 3 },
		244	.m = { .min = 104, .max = 138 },
		245	.m1 = { .min = 17, .max = 23 },
		246	.m2 = { .min = 5, .max = 11 },
		247	.p = { .min = 14, .max = 42 },
		248	.p1 = { .min = 2, .max = 6 },
		249	.p2 = { .dot_limit = 0,
		250	.p2_slow = 7, .p2_fast = 7
		251	},
		252	.find_pll = intel_g4x_find_best_PLL,
		253	};
		254
		255	static const intel_limit_t intel_limits_g4x_display_port = {
		256	.dot = { .min = 161670, .max = 227000 },
		257	.vco = { .min = 1750000, .max = 3500000},
		258	.n = { .min = 1, .max = 2 },
		259	.m = { .min = 97, .max = 108 },
		260	.m1 = { .min = 0x10, .max = 0x12 },
		261	.m2 = { .min = 0x05, .max = 0x06 },
		262	.p = { .min = 10, .max = 20 },
		263	.p1 = { .min = 1, .max = 2},
		264	.p2 = { .dot_limit = 0,
		265	.p2_slow = 10, .p2_fast = 10 },
		266	.find_pll = intel_find_pll_g4x_dp,
		267	};
		268
		269	static const intel_limit_t intel_limits_pineview_sdvo = {
		270	.dot = { .min = 20000, .max = 400000},
		271	.vco = { .min = 1700000, .max = 3500000 },
		272	/* Pineview's Ncounter is a ring counter */
		273	.n = { .min = 3, .max = 6 },
		274	.m = { .min = 2, .max = 256 },
		275	/* Pineview only has one combined m divider, which we treat as m2. */
		276	.m1 = { .min = 0, .max = 0 },
		277	.m2 = { .min = 0, .max = 254 },
		278	.p = { .min = 5, .max = 80 },
		279	.p1 = { .min = 1, .max = 8 },
		280	.p2 = { .dot_limit = 200000,
		281	.p2_slow = 10, .p2_fast = 5 },
		282	.find_pll = intel_find_best_PLL,
		283	};
		284
		285	static const intel_limit_t intel_limits_pineview_lvds = {
		286	.dot = { .min = 20000, .max = 400000 },
		287	.vco = { .min = 1700000, .max = 3500000 },
		288	.n = { .min = 3, .max = 6 },
		289	.m = { .min = 2, .max = 256 },
		290	.m1 = { .min = 0, .max = 0 },
		291	.m2 = { .min = 0, .max = 254 },
		292	.p = { .min = 7, .max = 112 },
		293	.p1 = { .min = 1, .max = 8 },
		294	.p2 = { .dot_limit = 112000,
		295	.p2_slow = 14, .p2_fast = 14 },
		296	.find_pll = intel_find_best_PLL,
		297	};
		298
		299	/* Ironlake / Sandybridge
		300	*
		301	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		302	* the range value for them is (actual_value - 2).
		303	*/
		304	static const intel_limit_t intel_limits_ironlake_dac = {
		305	.dot = { .min = 25000, .max = 350000 },
		306	.vco = { .min = 1760000, .max = 3510000 },
		307	.n = { .min = 1, .max = 5 },
		308	.m = { .min = 79, .max = 127 },
		309	.m1 = { .min = 12, .max = 22 },
		310	.m2 = { .min = 5, .max = 9 },
		311	.p = { .min = 5, .max = 80 },
		312	.p1 = { .min = 1, .max = 8 },
		313	.p2 = { .dot_limit = 225000,
		314	.p2_slow = 10, .p2_fast = 5 },
		315	.find_pll = intel_g4x_find_best_PLL,
		316	};
		317
		318	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		319	.dot = { .min = 25000, .max = 350000 },
		320	.vco = { .min = 1760000, .max = 3510000 },
		321	.n = { .min = 1, .max = 3 },
		322	.m = { .min = 79, .max = 118 },
		323	.m1 = { .min = 12, .max = 22 },
		324	.m2 = { .min = 5, .max = 9 },
		325	.p = { .min = 28, .max = 112 },
		326	.p1 = { .min = 2, .max = 8 },
		327	.p2 = { .dot_limit = 225000,
		328	.p2_slow = 14, .p2_fast = 14 },
		329	.find_pll = intel_g4x_find_best_PLL,
		330	};
		331
		332	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		333	.dot = { .min = 25000, .max = 350000 },
		334	.vco = { .min = 1760000, .max = 3510000 },
		335	.n = { .min = 1, .max = 3 },
		336	.m = { .min = 79, .max = 127 },
		337	.m1 = { .min = 12, .max = 22 },
		338	.m2 = { .min = 5, .max = 9 },
		339	.p = { .min = 14, .max = 56 },
		340	.p1 = { .min = 2, .max = 8 },
		341	.p2 = { .dot_limit = 225000,
		342	.p2_slow = 7, .p2_fast = 7 },
		343	.find_pll = intel_g4x_find_best_PLL,
		344	};
		345
		346	/* LVDS 100mhz refclk limits. */
		347	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		348	.dot = { .min = 25000, .max = 350000 },
		349	.vco = { .min = 1760000, .max = 3510000 },
		350	.n = { .min = 1, .max = 2 },
		351	.m = { .min = 79, .max = 126 },
		352	.m1 = { .min = 12, .max = 22 },
		353	.m2 = { .min = 5, .max = 9 },
		354	.p = { .min = 28, .max = 112 },
		355	.p1 = { .min = 2,.max = 8 },
		356	.p2 = { .dot_limit = 225000,
		357	.p2_slow = 14, .p2_fast = 14 },
		358	.find_pll = intel_g4x_find_best_PLL,
		359	};
		360
		361	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		362	.dot = { .min = 25000, .max = 350000 },
		363	.vco = { .min = 1760000, .max = 3510000 },
		364	.n = { .min = 1, .max = 3 },
		365	.m = { .min = 79, .max = 126 },
		366	.m1 = { .min = 12, .max = 22 },
		367	.m2 = { .min = 5, .max = 9 },
		368	.p = { .min = 14, .max = 42 },
		369	.p1 = { .min = 2,.max = 6 },
		370	.p2 = { .dot_limit = 225000,
		371	.p2_slow = 7, .p2_fast = 7 },
		372	.find_pll = intel_g4x_find_best_PLL,
		373	};
		374
		375	static const intel_limit_t intel_limits_ironlake_display_port = {
		376	.dot = { .min = 25000, .max = 350000 },
		377	.vco = { .min = 1760000, .max = 3510000},
		378	.n = { .min = 1, .max = 2 },
		379	.m = { .min = 81, .max = 90 },
		380	.m1 = { .min = 12, .max = 22 },
		381	.m2 = { .min = 5, .max = 9 },
		382	.p = { .min = 10, .max = 20 },
		383	.p1 = { .min = 1, .max = 2},
		384	.p2 = { .dot_limit = 0,
		385	.p2_slow = 10, .p2_fast = 10 },
		386	.find_pll = intel_find_pll_ironlake_dp,
		387	};
		388
		389	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		390	int refclk)
		391	{
		392	struct drm_device *dev = crtc->dev;
		393	struct drm_i915_private *dev_priv = dev->dev_private;
		394	const intel_limit_t *limit;
		395
		396	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		397	if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
		398	LVDS_CLKB_POWER_UP) {
		399	/* LVDS dual channel */
		400	if (refclk == 100000)
		401	limit = &intel_limits_ironlake_dual_lvds_100m;
		402	else
		403	limit = &intel_limits_ironlake_dual_lvds;
		404	} else {
		405	if (refclk == 100000)
		406	limit = &intel_limits_ironlake_single_lvds_100m;
		407	else
		408	limit = &intel_limits_ironlake_single_lvds;
		409	}
		410	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		411	HAS_eDP)
		412	limit = &intel_limits_ironlake_display_port;
		413	else
		414	limit = &intel_limits_ironlake_dac;
		415
		416	return limit;
		417	}
		418
		419	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		420	{
		421	struct drm_device *dev = crtc->dev;
		422	struct drm_i915_private *dev_priv = dev->dev_private;
		423	const intel_limit_t *limit;
		424
		425	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		426	if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
		427	LVDS_CLKB_POWER_UP)
		428	/* LVDS with dual channel */
		429	limit = &intel_limits_g4x_dual_channel_lvds;
		430	else
		431	/* LVDS with dual channel */
		432	limit = &intel_limits_g4x_single_channel_lvds;
		433	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		434	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		435	limit = &intel_limits_g4x_hdmi;
		436	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		437	limit = &intel_limits_g4x_sdvo;
		438	} else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		439	limit = &intel_limits_g4x_display_port;
		440	} else /* The option is for other outputs */
		441	limit = &intel_limits_i9xx_sdvo;
		442
		443	return limit;
		444	}
		445
		446	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		447	{
		448	struct drm_device *dev = crtc->dev;
		449	const intel_limit_t *limit;
		450
		451	if (HAS_PCH_SPLIT(dev))
		452	limit = intel_ironlake_limit(crtc, refclk);
		453	else if (IS_G4X(dev)) {
		454	limit = intel_g4x_limit(crtc);
		455	} else if (IS_PINEVIEW(dev)) {
		456	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		457	limit = &intel_limits_pineview_lvds;
		458	else
		459	limit = &intel_limits_pineview_sdvo;
		460	} else if (!IS_GEN2(dev)) {
		461	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		462	limit = &intel_limits_i9xx_lvds;
		463	else
		464	limit = &intel_limits_i9xx_sdvo;
		465	} else {
		466	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		467	limit = &intel_limits_i8xx_lvds;
		468	else
		469	limit = &intel_limits_i8xx_dvo;
		470	}
		471	return limit;
		472	}
		473
		474	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		475	static void pineview_clock(int refclk, intel_clock_t *clock)
		476	{
		477	clock->m = clock->m2 + 2;
		478	clock->p = clock->p1 * clock->p2;
		479	clock->vco = refclk * clock->m / clock->n;
		480	clock->dot = clock->vco / clock->p;
		481	}
		482
		483	static void intel_clock(struct drm_device dev, int refclk, intel_clock_t clock)
		484	{
		485	if (IS_PINEVIEW(dev)) {
		486	pineview_clock(refclk, clock);
		487	return;
		488	}
		489	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
		490	clock->p = clock->p1 * clock->p2;
		491	clock->vco = refclk * clock->m / (clock->n + 2);
		492	clock->dot = clock->vco / clock->p;
		493	}
		494
		495	/**
		496	* Returns whether any output on the specified pipe is of the specified type
		497	*/
		498	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		499	{
		500	struct drm_device *dev = crtc->dev;
		501	struct drm_mode_config *mode_config = &dev->mode_config;
		502	struct intel_encoder *encoder;
		503
		504	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		505	if (encoder->base.crtc == crtc && encoder->type == type)
		506	return true;
		507
		508	return false;
		509	}
		510
		511	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		512	/**
		513	* Returns whether the given set of divisors are valid for a given refclk with
		514	* the given connectors.
		515	*/
		516
		517	static bool intel_PLL_is_valid(struct drm_device *dev,
		518	const intel_limit_t *limit,
		519	const intel_clock_t *clock)
		520	{
		521	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
		522	INTELPllInvalid ("p1 out of range\n");
		523	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
		524	INTELPllInvalid ("p out of range\n");
		525	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
		526	INTELPllInvalid ("m2 out of range\n");
		527	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
		528	INTELPllInvalid ("m1 out of range\n");
		529	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
		530	INTELPllInvalid ("m1 <= m2\n");
		531	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
		532	INTELPllInvalid ("m out of range\n");
		533	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
		534	INTELPllInvalid ("n out of range\n");
		535	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
		536	INTELPllInvalid ("vco out of range\n");
		537	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		538	* connector, etc., rather than just a single range.
		539	*/
		540	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
		541	INTELPllInvalid ("dot out of range\n");
		542
		543	return true;
		544	}
		545
		546	static bool
		547	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
		548	int target, int refclk, intel_clock_t *best_clock)
		549
		550	{
		551	struct drm_device *dev = crtc->dev;
		552	struct drm_i915_private *dev_priv = dev->dev_private;
		553	intel_clock_t clock;
		554	int err = target;
		555
		556	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		557	(I915_READ(LVDS)) != 0) {
		558	/*
		559	* For LVDS, if the panel is on, just rely on its current
		560	* settings for dual-channel. We haven't figured out how to
		561	* reliably set up different single/dual channel state, if we
		562	* even can.
		563	*/
		564	if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
		565	LVDS_CLKB_POWER_UP)
		566	clock.p2 = limit->p2.p2_fast;
		567	else
		568	clock.p2 = limit->p2.p2_slow;
		569	} else {
		570	if (target < limit->p2.dot_limit)
		571	clock.p2 = limit->p2.p2_slow;
		572	else
		573	clock.p2 = limit->p2.p2_fast;
		574	}
		575
		576	memset (best_clock, 0, sizeof (*best_clock));
		577
		578	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		579	clock.m1++) {
		580	for (clock.m2 = limit->m2.min;
		581	clock.m2 <= limit->m2.max; clock.m2++) {
		582	/* m1 is always 0 in Pineview */
		583	if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
		584	break;
		585	for (clock.n = limit->n.min;
		586	clock.n <= limit->n.max; clock.n++) {
		587	for (clock.p1 = limit->p1.min;
		588	clock.p1 <= limit->p1.max; clock.p1++) {
		589	int this_err;
		590
		591	intel_clock(dev, refclk, &clock);
		592	if (!intel_PLL_is_valid(dev, limit,
		593	&clock))
		594	continue;
		595
		596	this_err = abs(clock.dot - target);
		597	if (this_err < err) {
		598	*best_clock = clock;
		599	err = this_err;
		600	}
		601	}
		602	}
		603	}
		604	}
		605
		606	return (err != target);
		607	}
		608
		609	static bool
		610	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
		611	int target, int refclk, intel_clock_t *best_clock)
		612	{
		613	struct drm_device *dev = crtc->dev;
		614	struct drm_i915_private *dev_priv = dev->dev_private;
		615	intel_clock_t clock;
		616	int max_n;
		617	bool found;
		618	/* approximately equals target * 0.00585 */
		619	int err_most = (target >> 8) + (target >> 9);
		620	found = false;
		621
		622	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		623	int lvds_reg;
		624
		625	if (HAS_PCH_SPLIT(dev))
		626	lvds_reg = PCH_LVDS;
		627	else
		628	lvds_reg = LVDS;
		629	if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
		630	LVDS_CLKB_POWER_UP)
		631	clock.p2 = limit->p2.p2_fast;
		632	else
		633	clock.p2 = limit->p2.p2_slow;
		634	} else {
		635	if (target < limit->p2.dot_limit)
		636	clock.p2 = limit->p2.p2_slow;
		637	else
		638	clock.p2 = limit->p2.p2_fast;
		639	}
		640
		641	memset(best_clock, 0, sizeof(*best_clock));
		642	max_n = limit->n.max;
		643	/* based on hardware requirement, prefer smaller n to precision */
		644	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		645	/* based on hardware requirement, prefere larger m1,m2 */
		646	for (clock.m1 = limit->m1.max;
		647	clock.m1 >= limit->m1.min; clock.m1--) {
		648	for (clock.m2 = limit->m2.max;
		649	clock.m2 >= limit->m2.min; clock.m2--) {
		650	for (clock.p1 = limit->p1.max;
		651	clock.p1 >= limit->p1.min; clock.p1--) {
		652	int this_err;
		653
		654	intel_clock(dev, refclk, &clock);
		655	if (!intel_PLL_is_valid(dev, limit,
		656	&clock))
		657	continue;
		658
		659	this_err = abs(clock.dot - target);
		660	if (this_err < err_most) {
		661	*best_clock = clock;
		662	err_most = this_err;
		663	max_n = clock.n;
		664	found = true;
		665	}
		666	}
		667	}
		668	}
		669	}
		670	return found;
		671	}
		672
		673	static bool
		674	intel_find_pll_ironlake_dp(const intel_limit_t limit, struct drm_crtc crtc,
		675	int target, int refclk, intel_clock_t *best_clock)
		676	{
		677	struct drm_device *dev = crtc->dev;
		678	intel_clock_t clock;
		679
		680	if (target < 200000) {
		681	clock.n = 1;
		682	clock.p1 = 2;
		683	clock.p2 = 10;
		684	clock.m1 = 12;
		685	clock.m2 = 9;
		686	} else {
		687	clock.n = 2;
		688	clock.p1 = 1;
		689	clock.p2 = 10;
		690	clock.m1 = 14;
		691	clock.m2 = 8;
		692	}
		693	intel_clock(dev, refclk, &clock);
		694	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		695	return true;
		696	}
		697
		698	/* DisplayPort has only two frequencies, 162MHz and 270MHz */
		699	static bool
		700	intel_find_pll_g4x_dp(const intel_limit_t limit, struct drm_crtc crtc,
		701	int target, int refclk, intel_clock_t *best_clock)
		702	{
		703	intel_clock_t clock;
		704	if (target < 200000) {
		705	clock.p1 = 2;
		706	clock.p2 = 10;
		707	clock.n = 2;
		708	clock.m1 = 23;
		709	clock.m2 = 8;
		710	} else {
		711	clock.p1 = 1;
		712	clock.p2 = 10;
		713	clock.n = 1;
		714	clock.m1 = 14;
		715	clock.m2 = 2;
		716	}
		717	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
		718	clock.p = (clock.p1 * clock.p2);
		719	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
		720	clock.vco = 0;
		721	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		722	return true;
		723	}
		724
		725	/**
		726	* intel_wait_for_vblank - wait for vblank on a given pipe
		727	* @dev: drm device
		728	* @pipe: pipe to wait for
		729	*
		730	* Wait for vblank to occur on a given pipe. Needed for various bits of
		731	* mode setting code.
		732	*/
		733	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		734	{
		735	struct drm_i915_private *dev_priv = dev->dev_private;
		736	int pipestat_reg = PIPESTAT(pipe);
		737
		738	/* Clear existing vblank status. Note this will clear any other
		739	* sticky status fields as well.
		740	*
		741	* This races with i915_driver_irq_handler() with the result
		742	* that either function could miss a vblank event. Here it is not
		743	* fatal, as we will either wait upon the next vblank interrupt or
		744	* timeout. Generally speaking intel_wait_for_vblank() is only
		745	* called during modeset at which time the GPU should be idle and
		746	* should not be performing page flips and thus not waiting on
		747	* vblanks...
		748	* Currently, the result of us stealing a vblank from the irq
		749	* handler is that a single frame will be skipped during swapbuffers.
		750	*/
		751	I915_WRITE(pipestat_reg,
		752	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		753
		754	/* Wait for vblank interrupt bit to set */
		755	if (wait_for(I915_READ(pipestat_reg) &
		756	PIPE_VBLANK_INTERRUPT_STATUS,
		757	50))
		758	DRM_DEBUG_KMS("vblank wait timed out\n");
		759	}
		760
		761	/*
		762	* intel_wait_for_pipe_off - wait for pipe to turn off
		763	* @dev: drm device
		764	* @pipe: pipe to wait for
		765	*
		766	* After disabling a pipe, we can't wait for vblank in the usual way,
		767	* spinning on the vblank interrupt status bit, since we won't actually
		768	* see an interrupt when the pipe is disabled.
		769	*
		770	* On Gen4 and above:
		771	* wait for the pipe register state bit to turn off
		772	*
		773	* Otherwise:
		774	* wait for the display line value to settle (it usually
		775	* ends up stopping at the start of the next frame).
		776	*
		777	*/
		778	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		779	{
		780	struct drm_i915_private *dev_priv = dev->dev_private;
		781
		782	if (INTEL_INFO(dev)->gen >= 4) {
		783	int reg = PIPECONF(pipe);
		784
		785	/* Wait for the Pipe State to go off */
		786	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		787	100))
		788	DRM_DEBUG_KMS("pipe_off wait timed out\n");
		789	} else {
		790	u32 last_line;
		791	int reg = PIPEDSL(pipe);
		792	unsigned long timeout = jiffies + msecs_to_jiffies(100);
		793
		794	/* Wait for the display line to settle */
		795	do {
		796	last_line = I915_READ(reg) & DSL_LINEMASK;
		797	mdelay(5);
		798	} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
		799	time_after(timeout, jiffies));
		800	if (time_after(jiffies, timeout))
		801	DRM_DEBUG_KMS("pipe_off wait timed out\n");
		802	}
		803	}
		804
		805	static const char *state_string(bool enabled)
		806	{
		807	return enabled ? "on" : "off";
		808	}
		809
		810	/* Only for pre-ILK configs */
		811	static void assert_pll(struct drm_i915_private *dev_priv,
		812	enum pipe pipe, bool state)
		813	{
		814	int reg;
		815	u32 val;
		816	bool cur_state;
		817
		818	reg = DPLL(pipe);
		819	val = I915_READ(reg);
		820	cur_state = !!(val & DPLL_VCO_ENABLE);
		821	WARN(cur_state != state,
		822	"PLL state assertion failure (expected %s, current %s)\n",
		823	state_string(state), state_string(cur_state));
		824	}
		825	#define assert_pll_enabled(d, p) assert_pll(d, p, true)
		826	#define assert_pll_disabled(d, p) assert_pll(d, p, false)
		827
		828	/* For ILK+ */
		829	static void assert_pch_pll(struct drm_i915_private *dev_priv,
		830	enum pipe pipe, bool state)
		831	{
		832	int reg;
		833	u32 val;
		834	bool cur_state;
		835
		836	reg = PCH_DPLL(pipe);
		837	val = I915_READ(reg);
		838	cur_state = !!(val & DPLL_VCO_ENABLE);
		839	WARN(cur_state != state,
		840	"PCH PLL state assertion failure (expected %s, current %s)\n",
		841	state_string(state), state_string(cur_state));
		842	}
		843	#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
		844	#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
		845
		846	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		847	enum pipe pipe, bool state)
		848	{
		849	int reg;
		850	u32 val;
		851	bool cur_state;
		852
		853	reg = FDI_TX_CTL(pipe);
		854	val = I915_READ(reg);
		855	cur_state = !!(val & FDI_TX_ENABLE);
		856	WARN(cur_state != state,
		857	"FDI TX state assertion failure (expected %s, current %s)\n",
		858	state_string(state), state_string(cur_state));
		859	}
		860	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		861	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		862
		863	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		864	enum pipe pipe, bool state)
		865	{
		866	int reg;
		867	u32 val;
		868	bool cur_state;
		869
		870	reg = FDI_RX_CTL(pipe);
		871	val = I915_READ(reg);
		872	cur_state = !!(val & FDI_RX_ENABLE);
		873	WARN(cur_state != state,
		874	"FDI RX state assertion failure (expected %s, current %s)\n",
		875	state_string(state), state_string(cur_state));
		876	}
		877	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		878	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		879
		880	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		881	enum pipe pipe)
		882	{
		883	int reg;
		884	u32 val;
		885
		886	/* ILK FDI PLL is always enabled */
		887	if (dev_priv->info->gen == 5)
		888	return;
		889
		890	reg = FDI_TX_CTL(pipe);
		891	val = I915_READ(reg);
		892	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		893	}
		894
		895	static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
		896	enum pipe pipe)
		897	{
		898	int reg;
		899	u32 val;
		900
		901	reg = FDI_RX_CTL(pipe);
		902	val = I915_READ(reg);
		903	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
		904	}
		905
		906	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		907	enum pipe pipe)
		908	{
		909	int pp_reg, lvds_reg;
		910	u32 val;
		911	enum pipe panel_pipe = PIPE_A;
		912	bool locked = true;
		913
		914	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		915	pp_reg = PCH_PP_CONTROL;
		916	lvds_reg = PCH_LVDS;
		917	} else {
		918	pp_reg = PP_CONTROL;
		919	lvds_reg = LVDS;
		920	}
		921
		922	val = I915_READ(pp_reg);
		923	if (!(val & PANEL_POWER_ON) \|\|
		924	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		925	locked = false;
		926
		927	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		928	panel_pipe = PIPE_B;
		929
		930	WARN(panel_pipe == pipe && locked,
		931	"panel assertion failure, pipe %c regs locked\n",
		932	pipe_name(pipe));
		933	}
		934
		935	static void assert_pipe(struct drm_i915_private *dev_priv,
		936	enum pipe pipe, bool state)
		937	{
		938	int reg;
		939	u32 val;
		940	bool cur_state;
		941
		942	reg = PIPECONF(pipe);
		943	val = I915_READ(reg);
		944	cur_state = !!(val & PIPECONF_ENABLE);
		945	WARN(cur_state != state,
		946	"pipe %c assertion failure (expected %s, current %s)\n",
		947	pipe_name(pipe), state_string(state), state_string(cur_state));
		948	}
		949	#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
		950	#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
		951
		952	static void assert_plane_enabled(struct drm_i915_private *dev_priv,
		953	enum plane plane)
		954	{
		955	int reg;
		956	u32 val;
		957
		958	reg = DSPCNTR(plane);
		959	val = I915_READ(reg);
		960	WARN(!(val & DISPLAY_PLANE_ENABLE),
		961	"plane %c assertion failure, should be active but is disabled\n",
		962	plane_name(plane));
		963	}
		964
		965	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		966	enum pipe pipe)
		967	{
		968	int reg, i;
		969	u32 val;
		970	int cur_pipe;
		971
		972	/* Planes are fixed to pipes on ILK+ */
		973	if (HAS_PCH_SPLIT(dev_priv->dev))
		974	return;
		975
		976	/* Need to check both planes against the pipe */
		977	for (i = 0; i < 2; i++) {
		978	reg = DSPCNTR(i);
		979	val = I915_READ(reg);
		980	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		981	DISPPLANE_SEL_PIPE_SHIFT;
		982	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		983	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		984	plane_name(i), pipe_name(pipe));
		985	}
		986	}
		987
		988	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		989	{
		990	u32 val;
		991	bool enabled;
		992
		993	val = I915_READ(PCH_DREF_CONTROL);
		994	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		995	DREF_SUPERSPREAD_SOURCE_MASK));
		996	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		997	}
		998
		999	static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
		1000	enum pipe pipe)
		1001	{
		1002	int reg;
		1003	u32 val;
		1004	bool enabled;
		1005
		1006	reg = TRANSCONF(pipe);
		1007	val = I915_READ(reg);
		1008	enabled = !!(val & TRANS_ENABLE);
		1009	WARN(enabled,
		1010	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1011	pipe_name(pipe));
		1012	}
		1013
		1014	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1015	enum pipe pipe, u32 port_sel, u32 val)
		1016	{
		1017	if ((val & DP_PORT_EN) == 0)
		1018	return false;
		1019
		1020	if (HAS_PCH_CPT(dev_priv->dev)) {
		1021	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1022	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1023	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1024	return false;
		1025	} else {
		1026	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1027	return false;
		1028	}
		1029	return true;
		1030	}
		1031
		1032	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1033	enum pipe pipe, u32 val)
		1034	{
		1035	if ((val & PORT_ENABLE) == 0)
		1036	return false;
		1037
		1038	if (HAS_PCH_CPT(dev_priv->dev)) {
		1039	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1040	return false;
		1041	} else {
		1042	if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
		1043	return false;
		1044	}
		1045	return true;
		1046	}
		1047
		1048	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1049	enum pipe pipe, u32 val)
		1050	{
		1051	if ((val & LVDS_PORT_EN) == 0)
		1052	return false;
		1053
		1054	if (HAS_PCH_CPT(dev_priv->dev)) {
		1055	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1056	return false;
		1057	} else {
		1058	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1059	return false;
		1060	}
		1061	return true;
		1062	}
		1063
		1064	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1065	enum pipe pipe, u32 val)
		1066	{
		1067	if ((val & ADPA_DAC_ENABLE) == 0)
		1068	return false;
		1069	if (HAS_PCH_CPT(dev_priv->dev)) {
		1070	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1071	return false;
		1072	} else {
		1073	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1074	return false;
		1075	}
		1076	return true;
		1077	}
		1078
		1079	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1080	enum pipe pipe, int reg, u32 port_sel)
		1081	{
		1082	u32 val = I915_READ(reg);
		1083	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1084	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1085	reg, pipe_name(pipe));
		1086	}
		1087
		1088	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1089	enum pipe pipe, int reg)
		1090	{
		1091	u32 val = I915_READ(reg);
		1092	WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
		1093	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1094	reg, pipe_name(pipe));
		1095	}
		1096
		1097	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1098	enum pipe pipe)
		1099	{
		1100	int reg;
		1101	u32 val;
		1102
		1103	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1104	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1105	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1106
		1107	reg = PCH_ADPA;
		1108	val = I915_READ(reg);
		1109	WARN(adpa_pipe_enabled(dev_priv, val, pipe),
		1110	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1111	pipe_name(pipe));
		1112
		1113	reg = PCH_LVDS;
		1114	val = I915_READ(reg);
		1115	WARN(lvds_pipe_enabled(dev_priv, val, pipe),
		1116	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1117	pipe_name(pipe));
		1118
		1119	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
		1120	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
		1121	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
		1122	}
		1123
		1124	/**
		1125	* intel_enable_pll - enable a PLL
		1126	* @dev_priv: i915 private structure
		1127	* @pipe: pipe PLL to enable
		1128	*
		1129	* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
		1130	* make sure the PLL reg is writable first though, since the panel write
		1131	* protect mechanism may be enabled.
		1132	*
		1133	* Note! This is for pre-ILK only.
		1134	*/
		1135	static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1136	{
		1137	int reg;
		1138	u32 val;
		1139
		1140	/* No really, not for ILK+ */
		1141	BUG_ON(dev_priv->info->gen >= 5);
		1142
		1143	/* PLL is protected by panel, make sure we can write it */
		1144	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		1145	assert_panel_unlocked(dev_priv, pipe);
		1146
		1147	reg = DPLL(pipe);
		1148	val = I915_READ(reg);
		1149	val \|= DPLL_VCO_ENABLE;
		1150
		1151	/* We do this three times for luck */
		1152	I915_WRITE(reg, val);
		1153	POSTING_READ(reg);
		1154	udelay(150); /* wait for warmup */
		1155	I915_WRITE(reg, val);
		1156	POSTING_READ(reg);
		1157	udelay(150); /* wait for warmup */
		1158	I915_WRITE(reg, val);
		1159	POSTING_READ(reg);
		1160	udelay(150); /* wait for warmup */
		1161	}
		1162
		1163	/**
		1164	* intel_disable_pll - disable a PLL
		1165	* @dev_priv: i915 private structure
		1166	* @pipe: pipe PLL to disable
		1167	*
		1168	* Disable the PLL for @pipe, making sure the pipe is off first.
		1169	*
		1170	* Note! This is for pre-ILK only.
		1171	*/
		1172	static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1173	{
		1174	int reg;
		1175	u32 val;
		1176
		1177	/* Don't disable pipe A or pipe A PLLs if needed */
		1178	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1179	return;
		1180
		1181	/* Make sure the pipe isn't still relying on us */
		1182	assert_pipe_disabled(dev_priv, pipe);
		1183
		1184	reg = DPLL(pipe);
		1185	val = I915_READ(reg);
		1186	val &= ~DPLL_VCO_ENABLE;
		1187	I915_WRITE(reg, val);
		1188	POSTING_READ(reg);
		1189	}
		1190
		1191	/**
		1192	* intel_enable_pch_pll - enable PCH PLL
		1193	* @dev_priv: i915 private structure
		1194	* @pipe: pipe PLL to enable
		1195	*
		1196	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1197	* drives the transcoder clock.
		1198	*/
		1199	static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
		1200	enum pipe pipe)
		1201	{
		1202	int reg;
		1203	u32 val;
		1204
		1205	/* PCH only available on ILK+ */
		1206	BUG_ON(dev_priv->info->gen < 5);
		1207
		1208	/* PCH refclock must be enabled first */
		1209	assert_pch_refclk_enabled(dev_priv);
		1210
		1211	reg = PCH_DPLL(pipe);
		1212	val = I915_READ(reg);
		1213	val \|= DPLL_VCO_ENABLE;
		1214	I915_WRITE(reg, val);
		1215	POSTING_READ(reg);
		1216	udelay(200);
		1217	}
		1218
		1219	static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
		1220	enum pipe pipe)
		1221	{
		1222	int reg;
		1223	u32 val;
		1224
		1225	/* PCH only available on ILK+ */
		1226	BUG_ON(dev_priv->info->gen < 5);
		1227
		1228	/* Make sure transcoder isn't still depending on us */
		1229	assert_transcoder_disabled(dev_priv, pipe);
		1230
		1231	reg = PCH_DPLL(pipe);
		1232	val = I915_READ(reg);
		1233	val &= ~DPLL_VCO_ENABLE;
		1234	I915_WRITE(reg, val);
		1235	POSTING_READ(reg);
		1236	udelay(200);
		1237	}
		1238
		1239	static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
		1240	enum pipe pipe)
		1241	{
		1242	int reg;
		1243	u32 val;
		1244
		1245	/* PCH only available on ILK+ */
		1246	BUG_ON(dev_priv->info->gen < 5);
		1247
		1248	/* Make sure PCH DPLL is enabled */
		1249	assert_pch_pll_enabled(dev_priv, pipe);
		1250
		1251	/* FDI must be feeding us bits for PCH ports */
		1252	assert_fdi_tx_enabled(dev_priv, pipe);
		1253	assert_fdi_rx_enabled(dev_priv, pipe);
		1254
		1255	reg = TRANSCONF(pipe);
		1256	val = I915_READ(reg);
		1257
		1258	if (HAS_PCH_IBX(dev_priv->dev)) {
		1259	/*
		1260	* make the BPC in transcoder be consistent with
		1261	* that in pipeconf reg.
		1262	*/
		1263	val &= ~PIPE_BPC_MASK;
		1264	val \|= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
		1265	}
		1266	I915_WRITE(reg, val \| TRANS_ENABLE);
		1267	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		1268	DRM_ERROR("failed to enable transcoder %d\n", pipe);
		1269	}
		1270
		1271	static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
		1272	enum pipe pipe)
		1273	{
		1274	int reg;
		1275	u32 val;
		1276
		1277	/* FDI relies on the transcoder */
		1278	assert_fdi_tx_disabled(dev_priv, pipe);
		1279	assert_fdi_rx_disabled(dev_priv, pipe);
		1280
		1281	/* Ports must be off as well */
		1282	assert_pch_ports_disabled(dev_priv, pipe);
		1283
		1284	reg = TRANSCONF(pipe);
		1285	val = I915_READ(reg);
		1286	val &= ~TRANS_ENABLE;
		1287	I915_WRITE(reg, val);
		1288	/* wait for PCH transcoder off, transcoder state */
		1289	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
		1290	DRM_ERROR("failed to disable transcoder\n");
		1291	}
		1292
		1293	/**
		1294	* intel_enable_pipe - enable a pipe, asserting requirements
		1295	* @dev_priv: i915 private structure
		1296	* @pipe: pipe to enable
		1297	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1298	*
		1299	* Enable @pipe, making sure that various hardware specific requirements
		1300	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1301	*
		1302	* @pipe should be %PIPE_A or %PIPE_B.
		1303	*
		1304	* Will wait until the pipe is actually running (i.e. first vblank) before
		1305	* returning.
		1306	*/
		1307	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1308	bool pch_port)
		1309	{
		1310	int reg;
		1311	u32 val;
		1312
		1313	/*
		1314	* A pipe without a PLL won't actually be able to drive bits from
		1315	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1316	* need the check.
		1317	*/
		1318	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1319	assert_pll_enabled(dev_priv, pipe);
		1320	else {
		1321	if (pch_port) {
		1322	/* if driving the PCH, we need FDI enabled */
		1323	assert_fdi_rx_pll_enabled(dev_priv, pipe);
		1324	assert_fdi_tx_pll_enabled(dev_priv, pipe);
		1325	}
		1326	/* FIXME: assert CPU port conditions for SNB+ */
		1327	}
		1328
		1329	reg = PIPECONF(pipe);
		1330	val = I915_READ(reg);
		1331	if (val & PIPECONF_ENABLE)
		1332	return;
		1333
		1334	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1335	intel_wait_for_vblank(dev_priv->dev, pipe);
		1336	}
		1337
		1338	/**
		1339	* intel_disable_pipe - disable a pipe, asserting requirements
		1340	* @dev_priv: i915 private structure
		1341	* @pipe: pipe to disable
		1342	*
		1343	* Disable @pipe, making sure that various hardware specific requirements
		1344	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1345	*
		1346	* @pipe should be %PIPE_A or %PIPE_B.
		1347	*
		1348	* Will wait until the pipe has shut down before returning.
		1349	*/
		1350	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1351	enum pipe pipe)
		1352	{
		1353	int reg;
		1354	u32 val;
		1355
		1356	/*
		1357	* Make sure planes won't keep trying to pump pixels to us,
		1358	* or we might hang the display.
		1359	*/
		1360	assert_planes_disabled(dev_priv, pipe);
		1361
		1362	/* Don't disable pipe A or pipe A PLLs if needed */
		1363	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1364	return;
		1365
		1366	reg = PIPECONF(pipe);
		1367	val = I915_READ(reg);
		1368	if ((val & PIPECONF_ENABLE) == 0)
		1369	return;
		1370
		1371	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1372	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		1373	}
		1374
		1375	/*
		1376	* Plane regs are double buffered, going from enabled->disabled needs a
		1377	* trigger in order to latch. The display address reg provides this.
		1378	*/
		1379	static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
		1380	enum plane plane)
		1381	{
		1382	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1383	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1384	}
		1385
		1386	/**
		1387	* intel_enable_plane - enable a display plane on a given pipe
		1388	* @dev_priv: i915 private structure
		1389	* @plane: plane to enable
		1390	* @pipe: pipe being fed
		1391	*
		1392	* Enable @plane on @pipe, making sure that @pipe is running first.
		1393	*/
		1394	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1395	enum plane plane, enum pipe pipe)
		1396	{
		1397	int reg;
		1398	u32 val;
		1399
		1400	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1401	assert_pipe_enabled(dev_priv, pipe);
		1402
		1403	reg = DSPCNTR(plane);
		1404	val = I915_READ(reg);
		1405	if (val & DISPLAY_PLANE_ENABLE)
		1406	return;
		1407
		1408	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1409	intel_flush_display_plane(dev_priv, plane);
		1410	intel_wait_for_vblank(dev_priv->dev, pipe);
		1411	}
		1412
		1413	/**
		1414	* intel_disable_plane - disable a display plane
		1415	* @dev_priv: i915 private structure
		1416	* @plane: plane to disable
		1417	* @pipe: pipe consuming the data
		1418	*
		1419	* Disable @plane; should be an independent operation.
		1420	*/
		1421	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1422	enum plane plane, enum pipe pipe)
		1423	{
		1424	int reg;
		1425	u32 val;
		1426
		1427	reg = DSPCNTR(plane);
		1428	val = I915_READ(reg);
		1429	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1430	return;
		1431
		1432	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1433	intel_flush_display_plane(dev_priv, plane);
		1434	intel_wait_for_vblank(dev_priv->dev, pipe);
		1435	}
		1436
		1437	static void disable_pch_dp(struct drm_i915_private *dev_priv,
		1438	enum pipe pipe, int reg, u32 port_sel)
		1439	{
		1440	u32 val = I915_READ(reg);
		1441	if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
		1442	DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
		1443	I915_WRITE(reg, val & ~DP_PORT_EN);
		1444	}
		1445	}
		1446
		1447	static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
		1448	enum pipe pipe, int reg)
		1449	{
		1450	u32 val = I915_READ(reg);
		1451	if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
		1452	DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
		1453	reg, pipe);
		1454	I915_WRITE(reg, val & ~PORT_ENABLE);
		1455	}
		1456	}
		1457
		1458	/* Disable any ports connected to this transcoder */
		1459	static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
		1460	enum pipe pipe)
		1461	{
		1462	u32 reg, val;
		1463
		1464	val = I915_READ(PCH_PP_CONTROL);
		1465	I915_WRITE(PCH_PP_CONTROL, val \| PANEL_UNLOCK_REGS);
		1466
		1467	disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1468	disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1469	disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1470
		1471	reg = PCH_ADPA;
		1472	val = I915_READ(reg);
		1473	if (adpa_pipe_enabled(dev_priv, val, pipe))
		1474	I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
		1475
		1476	reg = PCH_LVDS;
		1477	val = I915_READ(reg);
		1478	if (lvds_pipe_enabled(dev_priv, val, pipe)) {
		1479	DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
		1480	I915_WRITE(reg, val & ~LVDS_PORT_EN);
		1481	POSTING_READ(reg);
		1482	udelay(100);
		1483	}
		1484
		1485	disable_pch_hdmi(dev_priv, pipe, HDMIB);
		1486	disable_pch_hdmi(dev_priv, pipe, HDMIC);
		1487	disable_pch_hdmi(dev_priv, pipe, HDMID);
		1488	}
		1489
		1490	static void i8xx_disable_fbc(struct drm_device *dev)
		1491	{
		1492	struct drm_i915_private *dev_priv = dev->dev_private;
		1493	u32 fbc_ctl;
		1494
		1495	/* Disable compression */
		1496	fbc_ctl = I915_READ(FBC_CONTROL);
		1497	if ((fbc_ctl & FBC_CTL_EN) == 0)
		1498	return;
		1499
		1500	fbc_ctl &= ~FBC_CTL_EN;
		1501	I915_WRITE(FBC_CONTROL, fbc_ctl);
		1502
		1503	/* Wait for compressing bit to clear */
		1504	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
		1505	DRM_DEBUG_KMS("FBC idle timed out\n");
		1506	return;
		1507	}
		1508
		1509	DRM_DEBUG_KMS("disabled FBC\n");
		1510	}
		1511
		1512	static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
		1513	{
		1514	struct drm_device *dev = crtc->dev;
		1515	struct drm_i915_private *dev_priv = dev->dev_private;
		1516	struct drm_framebuffer *fb = crtc->fb;
		1517	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		1518	struct drm_i915_gem_object *obj = intel_fb->obj;
		1519	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1520	int cfb_pitch;
		1521	int plane, i;
		1522	u32 fbc_ctl, fbc_ctl2;
		1523
		1524	cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
		1525	if (fb->pitch < cfb_pitch)
		1526	cfb_pitch = fb->pitch;
		1527
		1528	/* FBC_CTL wants 64B units */
		1529	cfb_pitch = (cfb_pitch / 64) - 1;
		1530	plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
		1531
		1532	/* Clear old tags */
		1533	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
		1534	I915_WRITE(FBC_TAG + (i * 4), 0);
		1535
		1536	/* Set it up... */
		1537	fbc_ctl2 = FBC_CTL_FENCE_DBL \| FBC_CTL_IDLE_IMM \| FBC_CTL_CPU_FENCE;
		1538	fbc_ctl2 \|= plane;
		1539	I915_WRITE(FBC_CONTROL2, fbc_ctl2);
		1540	I915_WRITE(FBC_FENCE_OFF, crtc->y);
		1541
		1542	/* enable it... */
		1543	fbc_ctl = FBC_CTL_EN \| FBC_CTL_PERIODIC;
		1544	if (IS_I945GM(dev))
		1545	fbc_ctl \|= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
		1546	fbc_ctl \|= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
		1547	fbc_ctl \|= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
		1548	fbc_ctl \|= obj->fence_reg;
		1549	I915_WRITE(FBC_CONTROL, fbc_ctl);
		1550
		1551	DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
		1552	cfb_pitch, crtc->y, intel_crtc->plane);
		1553	}
		1554
		1555	static bool i8xx_fbc_enabled(struct drm_device *dev)
		1556	{
		1557	struct drm_i915_private *dev_priv = dev->dev_private;
		1558
		1559	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
		1560	}
		1561
		1562	static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
		1563	{
		1564	struct drm_device *dev = crtc->dev;
		1565	struct drm_i915_private *dev_priv = dev->dev_private;
		1566	struct drm_framebuffer *fb = crtc->fb;
		1567	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		1568	struct drm_i915_gem_object *obj = intel_fb->obj;
		1569	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1570	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
		1571	unsigned long stall_watermark = 200;
		1572	u32 dpfc_ctl;
		1573
		1574	dpfc_ctl = plane \| DPFC_SR_EN \| DPFC_CTL_LIMIT_1X;
		1575	dpfc_ctl \|= DPFC_CTL_FENCE_EN \| obj->fence_reg;
		1576	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
		1577
		1578	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN \|
		1579	(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) \|
		1580	(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
		1581	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
		1582
		1583	/* enable it... */
		1584	I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) \| DPFC_CTL_EN);
		1585
		1586	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
		1587	}
		1588
		1589	static void g4x_disable_fbc(struct drm_device *dev)
		1590	{
		1591	struct drm_i915_private *dev_priv = dev->dev_private;
		1592	u32 dpfc_ctl;
		1593
		1594	/* Disable compression */
		1595	dpfc_ctl = I915_READ(DPFC_CONTROL);
		1596	if (dpfc_ctl & DPFC_CTL_EN) {
		1597	dpfc_ctl &= ~DPFC_CTL_EN;
		1598	I915_WRITE(DPFC_CONTROL, dpfc_ctl);
		1599
		1600	DRM_DEBUG_KMS("disabled FBC\n");
		1601	}
		1602	}
		1603
		1604	static bool g4x_fbc_enabled(struct drm_device *dev)
		1605	{
		1606	struct drm_i915_private *dev_priv = dev->dev_private;
		1607
		1608	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
		1609	}
		1610
		1611	static void sandybridge_blit_fbc_update(struct drm_device *dev)
		1612	{
		1613	struct drm_i915_private *dev_priv = dev->dev_private;
		1614	u32 blt_ecoskpd;
		1615
		1616	/* Make sure blitter notifies FBC of writes */
		1617	gen6_gt_force_wake_get(dev_priv);
		1618	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
		1619	blt_ecoskpd \|= GEN6_BLITTER_FBC_NOTIFY <<
		1620	GEN6_BLITTER_LOCK_SHIFT;
		1621	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
		1622	blt_ecoskpd \|= GEN6_BLITTER_FBC_NOTIFY;
		1623	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
		1624	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
		1625	GEN6_BLITTER_LOCK_SHIFT);
		1626	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
		1627	POSTING_READ(GEN6_BLITTER_ECOSKPD);
		1628	gen6_gt_force_wake_put(dev_priv);
		1629	}
		1630
		1631	static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
		1632	{
		1633	struct drm_device *dev = crtc->dev;
		1634	struct drm_i915_private *dev_priv = dev->dev_private;
		1635	struct drm_framebuffer *fb = crtc->fb;
		1636	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		1637	struct drm_i915_gem_object *obj = intel_fb->obj;
		1638	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1639	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
		1640	unsigned long stall_watermark = 200;
		1641	u32 dpfc_ctl;
		1642
		1643	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
		1644	dpfc_ctl &= DPFC_RESERVED;
		1645	dpfc_ctl \|= (plane \| DPFC_CTL_LIMIT_1X);
		1646	/* Set persistent mode for front-buffer rendering, ala X. */
		1647	dpfc_ctl \|= DPFC_CTL_PERSISTENT_MODE;
		1648	dpfc_ctl \|= (DPFC_CTL_FENCE_EN \| obj->fence_reg);
		1649	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
		1650
		1651	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN \|
		1652	(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) \|
		1653	(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
		1654	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
		1655	I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset \| ILK_FBC_RT_VALID);
		1656	/* enable it... */
		1657	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl \| DPFC_CTL_EN);
		1658
		1659	if (IS_GEN6(dev)) {
		1660	I915_WRITE(SNB_DPFC_CTL_SA,
		1661	SNB_CPU_FENCE_ENABLE \| obj->fence_reg);
		1662	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
		1663	sandybridge_blit_fbc_update(dev);
		1664	}
		1665
		1666	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
		1667	}
		1668
		1669	static void ironlake_disable_fbc(struct drm_device *dev)
		1670	{
		1671	struct drm_i915_private *dev_priv = dev->dev_private;
		1672	u32 dpfc_ctl;
		1673
		1674	/* Disable compression */
		1675	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
		1676	if (dpfc_ctl & DPFC_CTL_EN) {
		1677	dpfc_ctl &= ~DPFC_CTL_EN;
		1678	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
		1679
		1680	DRM_DEBUG_KMS("disabled FBC\n");
		1681	}
		1682	}
		1683
		1684	static bool ironlake_fbc_enabled(struct drm_device *dev)
		1685	{
		1686	struct drm_i915_private *dev_priv = dev->dev_private;
		1687
		1688	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
		1689	}
		1690
		1691	bool intel_fbc_enabled(struct drm_device *dev)
		1692	{
		1693	struct drm_i915_private *dev_priv = dev->dev_private;
		1694
		1695	if (!dev_priv->display.fbc_enabled)
		1696	return false;
		1697
		1698	return dev_priv->display.fbc_enabled(dev);
		1699	}
		1700
		1701
		1702
		1703
		1704
		1705
		1706
		1707
		1708
		1709
		1710	static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
		1711	{
		1712	struct intel_fbc_work *work;
		1713	struct drm_device *dev = crtc->dev;
		1714	struct drm_i915_private *dev_priv = dev->dev_private;
		1715
		1716	if (!dev_priv->display.enable_fbc)
		1717	return;
		1718
		1719	// intel_cancel_fbc_work(dev_priv);
		1720
		1721	// work = kzalloc(sizeof *work, GFP_KERNEL);
		1722	// if (work == NULL) {
		1723	// dev_priv->display.enable_fbc(crtc, interval);
		1724	// return;
		1725	// }
		1726
		1727	// work->crtc = crtc;
		1728	// work->fb = crtc->fb;
		1729	// work->interval = interval;
		1730	// INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
		1731
		1732	// dev_priv->fbc_work = work;
		1733
		1734	DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
		1735
		1736	/* Delay the actual enabling to let pageflipping cease and the
		1737	* display to settle before starting the compression. Note that
		1738	* this delay also serves a second purpose: it allows for a
		1739	* vblank to pass after disabling the FBC before we attempt
		1740	* to modify the control registers.
		1741	*
		1742	* A more complicated solution would involve tracking vblanks
		1743	* following the termination of the page-flipping sequence
		1744	* and indeed performing the enable as a co-routine and not
		1745	* waiting synchronously upon the vblank.
		1746	*/
		1747	// schedule_delayed_work(&work->work, msecs_to_jiffies(50));
		1748	}
		1749
		1750	void intel_disable_fbc(struct drm_device *dev)
		1751	{
		1752	struct drm_i915_private *dev_priv = dev->dev_private;
		1753
		1754	// intel_cancel_fbc_work(dev_priv);
		1755
		1756	if (!dev_priv->display.disable_fbc)
		1757	return;
		1758
		1759	dev_priv->display.disable_fbc(dev);
		1760	dev_priv->cfb_plane = -1;
		1761	}
		1762
		1763	/**
		1764	* intel_update_fbc - enable/disable FBC as needed
		1765	* @dev: the drm_device
		1766	*
		1767	* Set up the framebuffer compression hardware at mode set time. We
		1768	* enable it if possible:
		1769	* - plane A only (on pre-965)
		1770	* - no pixel mulitply/line duplication
		1771	* - no alpha buffer discard
		1772	* - no dual wide
		1773	* - framebuffer <= 2048 in width, 1536 in height
		1774	*
		1775	* We can't assume that any compression will take place (worst case),
		1776	* so the compressed buffer has to be the same size as the uncompressed
		1777	* one. It also must reside (along with the line length buffer) in
		1778	* stolen memory.
		1779	*
		1780	* We need to enable/disable FBC on a global basis.
		1781	*/
		1782	static void intel_update_fbc(struct drm_device *dev)
		1783	{
		1784	struct drm_i915_private *dev_priv = dev->dev_private;
		1785	struct drm_crtc crtc = NULL, tmp_crtc;
		1786	struct intel_crtc *intel_crtc;
		1787	struct drm_framebuffer *fb;
		1788	struct intel_framebuffer *intel_fb;
		1789	struct drm_i915_gem_object *obj;
		1790
		1791	DRM_DEBUG_KMS("\n");
		1792
		1793	if (!i915_powersave)
		1794	return;
		1795
		1796	if (!I915_HAS_FBC(dev))
		1797	return;
		1798
		1799	/*
		1800	* If FBC is already on, we just have to verify that we can
		1801	* keep it that way...
		1802	* Need to disable if:
		1803	* - more than one pipe is active
		1804	* - changing FBC params (stride, fence, mode)
		1805	* - new fb is too large to fit in compressed buffer
		1806	* - going to an unsupported config (interlace, pixel multiply, etc.)
		1807	*/
		1808	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
		1809	if (tmp_crtc->enabled && tmp_crtc->fb) {
		1810	if (crtc) {
		1811	DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
		1812	// dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
		1813	goto out_disable;
		1814	}
		1815	crtc = tmp_crtc;
		1816	}
		1817	}
		1818
		1819	if (!crtc \|\| crtc->fb == NULL) {
		1820	DRM_DEBUG_KMS("no output, disabling\n");
		1821	// dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
		1822	goto out_disable;
		1823	}
		1824
		1825	intel_crtc = to_intel_crtc(crtc);
		1826	fb = crtc->fb;
		1827	intel_fb = to_intel_framebuffer(fb);
		1828	obj = intel_fb->obj;
		1829
		1830	if (!i915_enable_fbc) {
		1831	DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
		1832	// dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
		1833	goto out_disable;
		1834	}
		1835	if (intel_fb->obj->base.size > dev_priv->cfb_size) {
		1836	DRM_DEBUG_KMS("framebuffer too large, disabling "
		1837	"compression\n");
		1838	// dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
		1839	goto out_disable;
		1840	}
		1841	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) \|\|
		1842	(crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
		1843	DRM_DEBUG_KMS("mode incompatible with compression, "
		1844	"disabling\n");
		1845	// dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
		1846	goto out_disable;
		1847	}
		1848	if ((crtc->mode.hdisplay > 2048) \|\|
		1849	(crtc->mode.vdisplay > 1536)) {
		1850	DRM_DEBUG_KMS("mode too large for compression, disabling\n");
		1851	// dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
		1852	goto out_disable;
		1853	}
		1854	if ((IS_I915GM(dev) \|\| IS_I945GM(dev)) && intel_crtc->plane != 0) {
		1855	DRM_DEBUG_KMS("plane not 0, disabling compression\n");
		1856	// dev_priv->no_fbc_reason = FBC_BAD_PLANE;
		1857	goto out_disable;
		1858	}
		1859
		1860	/* The use of a CPU fence is mandatory in order to detect writes
		1861	* by the CPU to the scanout and trigger updates to the FBC.
		1862	*/
		1863	// if (obj->tiling_mode != I915_TILING_X \|\|
		1864	// obj->fence_reg == I915_FENCE_REG_NONE) {
		1865	// DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
		1866	// dev_priv->no_fbc_reason = FBC_NOT_TILED;
		1867	// goto out_disable;
		1868	// }
		1869
		1870	/* If the kernel debugger is active, always disable compression */
		1871	if (in_dbg_master())
		1872	goto out_disable;
		1873
		1874	/* If the scanout has not changed, don't modify the FBC settings.
		1875	* Note that we make the fundamental assumption that the fb->obj
		1876	* cannot be unpinned (and have its GTT offset and fence revoked)
		1877	* without first being decoupled from the scanout and FBC disabled.
		1878	*/
		1879	if (dev_priv->cfb_plane == intel_crtc->plane &&
		1880	dev_priv->cfb_fb == fb->base.id &&
		1881	dev_priv->cfb_y == crtc->y)
		1882	return;
		1883
		1884	if (intel_fbc_enabled(dev)) {
		1885	/* We update FBC along two paths, after changing fb/crtc
		1886	* configuration (modeswitching) and after page-flipping
		1887	* finishes. For the latter, we know that not only did
		1888	* we disable the FBC at the start of the page-flip
		1889	* sequence, but also more than one vblank has passed.
		1890	*
		1891	* For the former case of modeswitching, it is possible
		1892	* to switch between two FBC valid configurations
		1893	* instantaneously so we do need to disable the FBC
		1894	* before we can modify its control registers. We also
		1895	* have to wait for the next vblank for that to take
		1896	* effect. However, since we delay enabling FBC we can
		1897	* assume that a vblank has passed since disabling and
		1898	* that we can safely alter the registers in the deferred
		1899	* callback.
		1900	*
		1901	* In the scenario that we go from a valid to invalid
		1902	* and then back to valid FBC configuration we have
		1903	* no strict enforcement that a vblank occurred since
		1904	* disabling the FBC. However, along all current pipe
		1905	* disabling paths we do need to wait for a vblank at
		1906	* some point. And we wait before enabling FBC anyway.
		1907	*/
		1908	DRM_DEBUG_KMS("disabling active FBC for update\n");
		1909	intel_disable_fbc(dev);
		1910	}
		1911
		1912	intel_enable_fbc(crtc, 500);
		1913	return;
		1914
		1915	out_disable:
		1916	/* Multiple disables should be harmless */
		1917	if (intel_fbc_enabled(dev)) {
		1918	DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
		1919	intel_disable_fbc(dev);
		1920	}
		1921	}
		1922
2335	Serge	1923	int
		1924	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1925	struct drm_i915_gem_object *obj,
		1926	struct intel_ring_buffer *pipelined)
		1927	{
		1928	struct drm_i915_private *dev_priv = dev->dev_private;
		1929	u32 alignment;
		1930	int ret;
2327	Serge	1931
2335	Serge	1932	switch (obj->tiling_mode) {
		1933	case I915_TILING_NONE:
		1934	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		1935	alignment = 128 * 1024;
		1936	else if (INTEL_INFO(dev)->gen >= 4)
		1937	alignment = 4 * 1024;
		1938	else
		1939	alignment = 64 * 1024;
		1940	break;
		1941	case I915_TILING_X:
		1942	/* pin() will align the object as required by fence */
		1943	alignment = 0;
		1944	break;
		1945	case I915_TILING_Y:
		1946	/* FIXME: Is this true? */
		1947	DRM_ERROR("Y tiled not allowed for scan out buffers\n");
		1948	return -EINVAL;
		1949	default:
		1950	BUG();
		1951	}
2327	Serge	1952
2335	Serge	1953	dev_priv->mm.interruptible = false;
		1954	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		1955	if (ret)
		1956	goto err_interruptible;
2327	Serge	1957
2335	Serge	1958	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		1959	* fence, whereas 965+ only requires a fence if using
		1960	* framebuffer compression. For simplicity, we always install
		1961	* a fence as the cost is not that onerous.
		1962	*/
		1963	// if (obj->tiling_mode != I915_TILING_NONE) {
		1964	// ret = i915_gem_object_get_fence(obj, pipelined);
		1965	// if (ret)
		1966	// goto err_unpin;
		1967	// }
2327	Serge	1968
2335	Serge	1969	dev_priv->mm.interruptible = true;
		1970	return 0;
2327	Serge	1971
2335	Serge	1972	err_unpin:
		1973	// i915_gem_object_unpin(obj);
		1974	err_interruptible:
		1975	dev_priv->mm.interruptible = true;
		1976	return ret;
		1977	}
2327	Serge	1978
		1979	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		1980	int x, int y)
		1981	{
		1982	struct drm_device *dev = crtc->dev;
		1983	struct drm_i915_private *dev_priv = dev->dev_private;
		1984	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1985	struct intel_framebuffer *intel_fb;
		1986	struct drm_i915_gem_object *obj;
		1987	int plane = intel_crtc->plane;
		1988	unsigned long Start, Offset;
		1989	u32 dspcntr;
		1990	u32 reg;
		1991
		1992	switch (plane) {
		1993	case 0:
		1994	case 1:
		1995	break;
		1996	default:
		1997	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		1998	return -EINVAL;
		1999	}
		2000
		2001	intel_fb = to_intel_framebuffer(fb);
		2002	obj = intel_fb->obj;
		2003
		2004	reg = DSPCNTR(plane);
		2005	dspcntr = I915_READ(reg);
		2006	/* Mask out pixel format bits in case we change it */
		2007	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
		2008	switch (fb->bits_per_pixel) {
		2009	case 8:
		2010	dspcntr \|= DISPPLANE_8BPP;
		2011	break;
		2012	case 16:
		2013	if (fb->depth == 15)
		2014	dspcntr \|= DISPPLANE_15_16BPP;
		2015	else
		2016	dspcntr \|= DISPPLANE_16BPP;
		2017	break;
		2018	case 24:
		2019	case 32:
		2020	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
		2021	break;
		2022	default:
		2023	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		2024	return -EINVAL;
		2025	}
		2026	if (INTEL_INFO(dev)->gen >= 4) {
		2027	if (obj->tiling_mode != I915_TILING_NONE)
		2028	dspcntr \|= DISPPLANE_TILED;
		2029	else
		2030	dspcntr &= ~DISPPLANE_TILED;
		2031	}
		2032
		2033	I915_WRITE(reg, dspcntr);
		2034
		2035	Start = obj->gtt_offset;
		2036	Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
		2037
		2038	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2039	Start, Offset, x, y, fb->pitch);
		2040	I915_WRITE(DSPSTRIDE(plane), fb->pitch);
		2041	if (INTEL_INFO(dev)->gen >= 4) {
		2042	I915_WRITE(DSPSURF(plane), Start);
		2043	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
		2044	I915_WRITE(DSPADDR(plane), Offset);
		2045	} else
		2046	I915_WRITE(DSPADDR(plane), Start + Offset);
		2047	POSTING_READ(reg);
		2048
		2049	return 0;
		2050	}
		2051
		2052	static int ironlake_update_plane(struct drm_crtc *crtc,
		2053	struct drm_framebuffer *fb, int x, int y)
		2054	{
		2055	struct drm_device *dev = crtc->dev;
		2056	struct drm_i915_private *dev_priv = dev->dev_private;
		2057	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2058	struct intel_framebuffer *intel_fb;
		2059	struct drm_i915_gem_object *obj;
		2060	int plane = intel_crtc->plane;
		2061	unsigned long Start, Offset;
		2062	u32 dspcntr;
		2063	u32 reg;
		2064
		2065	switch (plane) {
		2066	case 0:
		2067	case 1:
		2068	break;
		2069	default:
		2070	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		2071	return -EINVAL;
		2072	}
		2073
		2074	intel_fb = to_intel_framebuffer(fb);
		2075	obj = intel_fb->obj;
		2076
		2077	reg = DSPCNTR(plane);
		2078	dspcntr = I915_READ(reg);
		2079	/* Mask out pixel format bits in case we change it */
		2080	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
		2081	switch (fb->bits_per_pixel) {
		2082	case 8:
		2083	dspcntr \|= DISPPLANE_8BPP;
		2084	break;
		2085	case 16:
		2086	if (fb->depth != 16)
		2087	return -EINVAL;
		2088
		2089	dspcntr \|= DISPPLANE_16BPP;
		2090	break;
		2091	case 24:
		2092	case 32:
		2093	if (fb->depth == 24)
		2094	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
		2095	else if (fb->depth == 30)
		2096	dspcntr \|= DISPPLANE_32BPP_30BIT_NO_ALPHA;
		2097	else
		2098	return -EINVAL;
		2099	break;
		2100	default:
		2101	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		2102	return -EINVAL;
		2103	}
		2104
		2105	// if (obj->tiling_mode != I915_TILING_NONE)
		2106	// dspcntr \|= DISPPLANE_TILED;
		2107	// else
		2108	dspcntr &= ~DISPPLANE_TILED;
		2109
		2110	/* must disable */
		2111	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2112
		2113	I915_WRITE(reg, dspcntr);
		2114
		2115	// Start = obj->gtt_offset;
		2116	// Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
		2117
		2118	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2119	Start, Offset, x, y, fb->pitch);
2330	Serge	2120	I915_WRITE(DSPSTRIDE(plane), fb->pitch);
		2121	I915_WRITE(DSPSURF(plane), Start);
		2122	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
		2123	I915_WRITE(DSPADDR(plane), Offset);
		2124	POSTING_READ(reg);
2327	Serge	2125
		2126	return 0;
		2127	}
		2128
		2129	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2130	static int
		2131	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2132	int x, int y, enum mode_set_atomic state)
		2133	{
		2134	struct drm_device *dev = crtc->dev;
		2135	struct drm_i915_private *dev_priv = dev->dev_private;
		2136	int ret;
		2137
		2138	ret = dev_priv->display.update_plane(crtc, fb, x, y);
		2139	if (ret)
		2140	return ret;
		2141
		2142	intel_update_fbc(dev);
		2143	intel_increase_pllclock(crtc);
		2144
		2145	return 0;
		2146	}
		2147
		2148	static int
		2149	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
		2150	struct drm_framebuffer *old_fb)
		2151	{
		2152	struct drm_device *dev = crtc->dev;
		2153	struct drm_i915_master_private *master_priv;
		2154	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2155	int ret;
		2156
		2157	/* no fb bound */
		2158	if (!crtc->fb) {
		2159	DRM_ERROR("No FB bound\n");
		2160	return 0;
		2161	}
		2162
		2163	switch (intel_crtc->plane) {
		2164	case 0:
		2165	case 1:
		2166	break;
		2167	default:
		2168	DRM_ERROR("no plane for crtc\n");
		2169	return -EINVAL;
		2170	}
		2171
		2172	mutex_lock(&dev->struct_mutex);
		2173	// ret = intel_pin_and_fence_fb_obj(dev,
		2174	// to_intel_framebuffer(crtc->fb)->obj,
		2175	// NULL);
		2176	if (ret != 0) {
		2177	mutex_unlock(&dev->struct_mutex);
		2178	DRM_ERROR("pin & fence failed\n");
		2179	return ret;
		2180	}
		2181
		2182	if (old_fb) {
		2183	struct drm_i915_private *dev_priv = dev->dev_private;
		2184	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
		2185
		2186	// wait_event(dev_priv->pending_flip_queue,
		2187	// atomic_read(&dev_priv->mm.wedged) \|\|
		2188	// atomic_read(&obj->pending_flip) == 0);
		2189
		2190	/* Big Hammer, we also need to ensure that any pending
		2191	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2192	* current scanout is retired before unpinning the old
		2193	* framebuffer.
		2194	*
		2195	* This should only fail upon a hung GPU, in which case we
		2196	* can safely continue.
		2197	*/
		2198	// ret = i915_gem_object_finish_gpu(obj);
		2199	(void) ret;
		2200	}
		2201
		2202	ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
		2203	LEAVE_ATOMIC_MODE_SET);
		2204	if (ret) {
		2205	// i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
		2206	mutex_unlock(&dev->struct_mutex);
		2207	DRM_ERROR("failed to update base address\n");
		2208	return ret;
		2209	}
		2210
		2211	if (old_fb) {
		2212	// intel_wait_for_vblank(dev, intel_crtc->pipe);
		2213	// i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
		2214	}
		2215
		2216	mutex_unlock(&dev->struct_mutex);
2330	Serge	2217	#if 0
		2218	if (!dev->primary->master)
		2219	return 0;
2327	Serge	2220
2330	Serge	2221	master_priv = dev->primary->master->driver_priv;
		2222	if (!master_priv->sarea_priv)
		2223	return 0;
2327	Serge	2224
2330	Serge	2225	if (intel_crtc->pipe) {
		2226	master_priv->sarea_priv->pipeB_x = x;
		2227	master_priv->sarea_priv->pipeB_y = y;
		2228	} else {
		2229	master_priv->sarea_priv->pipeA_x = x;
		2230	master_priv->sarea_priv->pipeA_y = y;
		2231	}
		2232	#endif
2327	Serge	2233	return 0;
		2234	}
		2235
		2236	static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
		2237	{
		2238	struct drm_device *dev = crtc->dev;
		2239	struct drm_i915_private *dev_priv = dev->dev_private;
		2240	u32 dpa_ctl;
		2241
		2242	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
		2243	dpa_ctl = I915_READ(DP_A);
		2244	dpa_ctl &= ~DP_PLL_FREQ_MASK;
		2245
		2246	if (clock < 200000) {
		2247	u32 temp;
		2248	dpa_ctl \|= DP_PLL_FREQ_160MHZ;
		2249	/* workaround for 160Mhz:
		2250	1) program 0x4600c bits 15:0 = 0x8124
		2251	2) program 0x46010 bit 0 = 1
		2252	3) program 0x46034 bit 24 = 1
		2253	4) program 0x64000 bit 14 = 1
		2254	*/
		2255	temp = I915_READ(0x4600c);
		2256	temp &= 0xffff0000;
		2257	I915_WRITE(0x4600c, temp \| 0x8124);
		2258
		2259	temp = I915_READ(0x46010);
		2260	I915_WRITE(0x46010, temp \| 1);
		2261
		2262	temp = I915_READ(0x46034);
		2263	I915_WRITE(0x46034, temp \| (1 << 24));
		2264	} else {
		2265	dpa_ctl \|= DP_PLL_FREQ_270MHZ;
		2266	}
		2267	I915_WRITE(DP_A, dpa_ctl);
		2268
		2269	POSTING_READ(DP_A);
		2270	udelay(500);
		2271	}
		2272
		2273	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2274	{
		2275	struct drm_device *dev = crtc->dev;
		2276	struct drm_i915_private *dev_priv = dev->dev_private;
		2277	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2278	int pipe = intel_crtc->pipe;
		2279	u32 reg, temp;
		2280
		2281	/* enable normal train */
		2282	reg = FDI_TX_CTL(pipe);
		2283	temp = I915_READ(reg);
		2284	if (IS_IVYBRIDGE(dev)) {
		2285	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2286	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2287	} else {
		2288	temp &= ~FDI_LINK_TRAIN_NONE;
		2289	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2290	}
		2291	I915_WRITE(reg, temp);
		2292
		2293	reg = FDI_RX_CTL(pipe);
		2294	temp = I915_READ(reg);
		2295	if (HAS_PCH_CPT(dev)) {
		2296	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2297	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2298	} else {
		2299	temp &= ~FDI_LINK_TRAIN_NONE;
		2300	temp \|= FDI_LINK_TRAIN_NONE;
		2301	}
		2302	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2303
		2304	/* wait one idle pattern time */
		2305	POSTING_READ(reg);
		2306	udelay(1000);
		2307
		2308	/* IVB wants error correction enabled */
		2309	if (IS_IVYBRIDGE(dev))
		2310	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2311	FDI_FE_ERRC_ENABLE);
		2312	}
		2313
		2314	static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
		2315	{
		2316	struct drm_i915_private *dev_priv = dev->dev_private;
		2317	u32 flags = I915_READ(SOUTH_CHICKEN1);
		2318
		2319	flags \|= FDI_PHASE_SYNC_OVR(pipe);
		2320	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
		2321	flags \|= FDI_PHASE_SYNC_EN(pipe);
		2322	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
		2323	POSTING_READ(SOUTH_CHICKEN1);
		2324	}
		2325
		2326	/* The FDI link training functions for ILK/Ibexpeak. */
		2327	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2328	{
		2329	struct drm_device *dev = crtc->dev;
		2330	struct drm_i915_private *dev_priv = dev->dev_private;
		2331	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2332	int pipe = intel_crtc->pipe;
		2333	int plane = intel_crtc->plane;
		2334	u32 reg, temp, tries;
		2335
		2336	/* FDI needs bits from pipe & plane first */
		2337	assert_pipe_enabled(dev_priv, pipe);
		2338	assert_plane_enabled(dev_priv, plane);
		2339
		2340	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2341	for train result */
		2342	reg = FDI_RX_IMR(pipe);
		2343	temp = I915_READ(reg);
		2344	temp &= ~FDI_RX_SYMBOL_LOCK;
		2345	temp &= ~FDI_RX_BIT_LOCK;
		2346	I915_WRITE(reg, temp);
		2347	I915_READ(reg);
		2348	udelay(150);
		2349
		2350	/* enable CPU FDI TX and PCH FDI RX */
		2351	reg = FDI_TX_CTL(pipe);
		2352	temp = I915_READ(reg);
		2353	temp &= ~(7 << 19);
		2354	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2355	temp &= ~FDI_LINK_TRAIN_NONE;
		2356	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2357	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2358
		2359	reg = FDI_RX_CTL(pipe);
		2360	temp = I915_READ(reg);
		2361	temp &= ~FDI_LINK_TRAIN_NONE;
		2362	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2363	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2364
		2365	POSTING_READ(reg);
		2366	udelay(150);
		2367
		2368	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2369	if (HAS_PCH_IBX(dev)) {
		2370	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2371	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2372	FDI_RX_PHASE_SYNC_POINTER_EN);
		2373	}
		2374
		2375	reg = FDI_RX_IIR(pipe);
		2376	for (tries = 0; tries < 5; tries++) {
		2377	temp = I915_READ(reg);
		2378	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2379
		2380	if ((temp & FDI_RX_BIT_LOCK)) {
		2381	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2382	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2383	break;
		2384	}
		2385	}
		2386	if (tries == 5)
		2387	DRM_ERROR("FDI train 1 fail!\n");
		2388
		2389	/* Train 2 */
		2390	reg = FDI_TX_CTL(pipe);
		2391	temp = I915_READ(reg);
		2392	temp &= ~FDI_LINK_TRAIN_NONE;
		2393	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2394	I915_WRITE(reg, temp);
		2395
		2396	reg = FDI_RX_CTL(pipe);
		2397	temp = I915_READ(reg);
		2398	temp &= ~FDI_LINK_TRAIN_NONE;
		2399	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2400	I915_WRITE(reg, temp);
		2401
		2402	POSTING_READ(reg);
		2403	udelay(150);
		2404
		2405	reg = FDI_RX_IIR(pipe);
		2406	for (tries = 0; tries < 5; tries++) {
		2407	temp = I915_READ(reg);
		2408	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2409
		2410	if (temp & FDI_RX_SYMBOL_LOCK) {
		2411	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2412	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2413	break;
		2414	}
		2415	}
		2416	if (tries == 5)
		2417	DRM_ERROR("FDI train 2 fail!\n");
		2418
		2419	DRM_DEBUG_KMS("FDI train done\n");
		2420
		2421	}
		2422
		2423	static const int snb_b_fdi_train_param [] = {
		2424	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2425	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2426	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2427	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2428	};
		2429
		2430	/* The FDI link training functions for SNB/Cougarpoint. */
		2431	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2432	{
		2433	struct drm_device *dev = crtc->dev;
		2434	struct drm_i915_private *dev_priv = dev->dev_private;
		2435	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2436	int pipe = intel_crtc->pipe;
		2437	u32 reg, temp, i;
		2438
		2439	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2440	for train result */
		2441	reg = FDI_RX_IMR(pipe);
		2442	temp = I915_READ(reg);
		2443	temp &= ~FDI_RX_SYMBOL_LOCK;
		2444	temp &= ~FDI_RX_BIT_LOCK;
		2445	I915_WRITE(reg, temp);
		2446
		2447	POSTING_READ(reg);
		2448	udelay(150);
		2449
		2450	/* enable CPU FDI TX and PCH FDI RX */
		2451	reg = FDI_TX_CTL(pipe);
		2452	temp = I915_READ(reg);
		2453	temp &= ~(7 << 19);
		2454	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2455	temp &= ~FDI_LINK_TRAIN_NONE;
		2456	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2457	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2458	/* SNB-B */
		2459	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2460	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2461
		2462	reg = FDI_RX_CTL(pipe);
		2463	temp = I915_READ(reg);
		2464	if (HAS_PCH_CPT(dev)) {
		2465	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2466	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2467	} else {
		2468	temp &= ~FDI_LINK_TRAIN_NONE;
		2469	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2470	}
		2471	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2472
		2473	POSTING_READ(reg);
		2474	udelay(150);
		2475
		2476	if (HAS_PCH_CPT(dev))
		2477	cpt_phase_pointer_enable(dev, pipe);
		2478
		2479	for (i = 0; i < 4; i++ ) {
		2480	reg = FDI_TX_CTL(pipe);
		2481	temp = I915_READ(reg);
		2482	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2483	temp \|= snb_b_fdi_train_param[i];
		2484	I915_WRITE(reg, temp);
		2485
		2486	POSTING_READ(reg);
		2487	udelay(500);
		2488
		2489	reg = FDI_RX_IIR(pipe);
		2490	temp = I915_READ(reg);
		2491	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2492
		2493	if (temp & FDI_RX_BIT_LOCK) {
		2494	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2495	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2496	break;
		2497	}
		2498	}
		2499	if (i == 4)
		2500	DRM_ERROR("FDI train 1 fail!\n");
		2501
		2502	/* Train 2 */
		2503	reg = FDI_TX_CTL(pipe);
		2504	temp = I915_READ(reg);
		2505	temp &= ~FDI_LINK_TRAIN_NONE;
		2506	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2507	if (IS_GEN6(dev)) {
		2508	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2509	/* SNB-B */
		2510	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2511	}
		2512	I915_WRITE(reg, temp);
		2513
		2514	reg = FDI_RX_CTL(pipe);
		2515	temp = I915_READ(reg);
		2516	if (HAS_PCH_CPT(dev)) {
		2517	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2518	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2519	} else {
		2520	temp &= ~FDI_LINK_TRAIN_NONE;
		2521	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2522	}
		2523	I915_WRITE(reg, temp);
		2524
		2525	POSTING_READ(reg);
		2526	udelay(150);
		2527
		2528	for (i = 0; i < 4; i++ ) {
		2529	reg = FDI_TX_CTL(pipe);
		2530	temp = I915_READ(reg);
		2531	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2532	temp \|= snb_b_fdi_train_param[i];
		2533	I915_WRITE(reg, temp);
		2534
		2535	POSTING_READ(reg);
		2536	udelay(500);
		2537
		2538	reg = FDI_RX_IIR(pipe);
		2539	temp = I915_READ(reg);
		2540	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2541
		2542	if (temp & FDI_RX_SYMBOL_LOCK) {
		2543	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2544	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2545	break;
		2546	}
		2547	}
		2548	if (i == 4)
		2549	DRM_ERROR("FDI train 2 fail!\n");
		2550
		2551	DRM_DEBUG_KMS("FDI train done.\n");
		2552	}
		2553
		2554	/* Manual link training for Ivy Bridge A0 parts */
		2555	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2556	{
		2557	struct drm_device *dev = crtc->dev;
		2558	struct drm_i915_private *dev_priv = dev->dev_private;
		2559	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2560	int pipe = intel_crtc->pipe;
		2561	u32 reg, temp, i;
		2562
		2563	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2564	for train result */
		2565	reg = FDI_RX_IMR(pipe);
		2566	temp = I915_READ(reg);
		2567	temp &= ~FDI_RX_SYMBOL_LOCK;
		2568	temp &= ~FDI_RX_BIT_LOCK;
		2569	I915_WRITE(reg, temp);
		2570
		2571	POSTING_READ(reg);
		2572	udelay(150);
		2573
		2574	/* enable CPU FDI TX and PCH FDI RX */
		2575	reg = FDI_TX_CTL(pipe);
		2576	temp = I915_READ(reg);
		2577	temp &= ~(7 << 19);
		2578	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2579	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2580	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2581	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2582	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2583	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2584
		2585	reg = FDI_RX_CTL(pipe);
		2586	temp = I915_READ(reg);
		2587	temp &= ~FDI_LINK_TRAIN_AUTO;
		2588	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2589	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2590	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2591
		2592	POSTING_READ(reg);
		2593	udelay(150);
		2594
		2595	if (HAS_PCH_CPT(dev))
		2596	cpt_phase_pointer_enable(dev, pipe);
		2597
		2598	for (i = 0; i < 4; i++ ) {
		2599	reg = FDI_TX_CTL(pipe);
		2600	temp = I915_READ(reg);
		2601	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2602	temp \|= snb_b_fdi_train_param[i];
		2603	I915_WRITE(reg, temp);
		2604
		2605	POSTING_READ(reg);
		2606	udelay(500);
		2607
		2608	reg = FDI_RX_IIR(pipe);
		2609	temp = I915_READ(reg);
		2610	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2611
		2612	if (temp & FDI_RX_BIT_LOCK \|\|
		2613	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2614	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2615	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2616	break;
		2617	}
		2618	}
		2619	if (i == 4)
		2620	DRM_ERROR("FDI train 1 fail!\n");
		2621
		2622	/* Train 2 */
		2623	reg = FDI_TX_CTL(pipe);
		2624	temp = I915_READ(reg);
		2625	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2626	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2627	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2628	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2629	I915_WRITE(reg, temp);
		2630
		2631	reg = FDI_RX_CTL(pipe);
		2632	temp = I915_READ(reg);
		2633	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2634	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2635	I915_WRITE(reg, temp);
		2636
		2637	POSTING_READ(reg);
		2638	udelay(150);
		2639
		2640	for (i = 0; i < 4; i++ ) {
		2641	reg = FDI_TX_CTL(pipe);
		2642	temp = I915_READ(reg);
		2643	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2644	temp \|= snb_b_fdi_train_param[i];
		2645	I915_WRITE(reg, temp);
		2646
		2647	POSTING_READ(reg);
		2648	udelay(500);
		2649
		2650	reg = FDI_RX_IIR(pipe);
		2651	temp = I915_READ(reg);
		2652	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2653
		2654	if (temp & FDI_RX_SYMBOL_LOCK) {
		2655	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2656	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2657	break;
		2658	}
		2659	}
		2660	if (i == 4)
		2661	DRM_ERROR("FDI train 2 fail!\n");
		2662
		2663	DRM_DEBUG_KMS("FDI train done.\n");
		2664	}
		2665
		2666	static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
		2667	{
		2668	struct drm_device *dev = crtc->dev;
		2669	struct drm_i915_private *dev_priv = dev->dev_private;
		2670	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2671	int pipe = intel_crtc->pipe;
		2672	u32 reg, temp;
		2673
		2674	/* Write the TU size bits so error detection works */
		2675	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		2676	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		2677
		2678	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2679	reg = FDI_RX_CTL(pipe);
		2680	temp = I915_READ(reg);
		2681	temp &= ~((0x7 << 19) \| (0x7 << 16));
		2682	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2683	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2684	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2685
		2686	POSTING_READ(reg);
		2687	udelay(200);
		2688
		2689	/* Switch from Rawclk to PCDclk */
		2690	temp = I915_READ(reg);
		2691	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2692
		2693	POSTING_READ(reg);
		2694	udelay(200);
		2695
		2696	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2697	reg = FDI_TX_CTL(pipe);
		2698	temp = I915_READ(reg);
		2699	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2700	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2701
		2702	POSTING_READ(reg);
		2703	udelay(100);
		2704	}
		2705	}
		2706
		2707	static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
		2708	{
		2709	struct drm_i915_private *dev_priv = dev->dev_private;
		2710	u32 flags = I915_READ(SOUTH_CHICKEN1);
		2711
		2712	flags &= ~(FDI_PHASE_SYNC_EN(pipe));
		2713	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
		2714	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
		2715	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
		2716	POSTING_READ(SOUTH_CHICKEN1);
		2717	}
		2718	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2719	{
		2720	struct drm_device *dev = crtc->dev;
		2721	struct drm_i915_private *dev_priv = dev->dev_private;
		2722	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2723	int pipe = intel_crtc->pipe;
		2724	u32 reg, temp;
		2725
		2726	/* disable CPU FDI tx and PCH FDI rx */
		2727	reg = FDI_TX_CTL(pipe);
		2728	temp = I915_READ(reg);
		2729	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2730	POSTING_READ(reg);
		2731
		2732	reg = FDI_RX_CTL(pipe);
		2733	temp = I915_READ(reg);
		2734	temp &= ~(0x7 << 16);
		2735	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2736	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2737
		2738	POSTING_READ(reg);
		2739	udelay(100);
		2740
		2741	/* Ironlake workaround, disable clock pointer after downing FDI */
		2742	if (HAS_PCH_IBX(dev)) {
		2743	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2744	I915_WRITE(FDI_RX_CHICKEN(pipe),
		2745	I915_READ(FDI_RX_CHICKEN(pipe) &
		2746	~FDI_RX_PHASE_SYNC_POINTER_EN));
		2747	} else if (HAS_PCH_CPT(dev)) {
		2748	cpt_phase_pointer_disable(dev, pipe);
		2749	}
		2750
		2751	/* still set train pattern 1 */
		2752	reg = FDI_TX_CTL(pipe);
		2753	temp = I915_READ(reg);
		2754	temp &= ~FDI_LINK_TRAIN_NONE;
		2755	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2756	I915_WRITE(reg, temp);
		2757
		2758	reg = FDI_RX_CTL(pipe);
		2759	temp = I915_READ(reg);
		2760	if (HAS_PCH_CPT(dev)) {
		2761	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2762	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2763	} else {
		2764	temp &= ~FDI_LINK_TRAIN_NONE;
		2765	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2766	}
		2767	/* BPC in FDI rx is consistent with that in PIPECONF */
		2768	temp &= ~(0x07 << 16);
		2769	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2770	I915_WRITE(reg, temp);
		2771
		2772	POSTING_READ(reg);
		2773	udelay(100);
		2774	}
		2775
		2776	/*
		2777	* When we disable a pipe, we need to clear any pending scanline wait events
		2778	* to avoid hanging the ring, which we assume we are waiting on.
		2779	*/
		2780	static void intel_clear_scanline_wait(struct drm_device *dev)
		2781	{
		2782	struct drm_i915_private *dev_priv = dev->dev_private;
		2783	struct intel_ring_buffer *ring;
		2784	u32 tmp;
		2785
		2786	if (IS_GEN2(dev))
		2787	/* Can't break the hang on i8xx */
		2788	return;
		2789
		2790	ring = LP_RING(dev_priv);
		2791	tmp = I915_READ_CTL(ring);
		2792	if (tmp & RING_WAIT)
		2793	I915_WRITE_CTL(ring, tmp);
		2794	}
		2795
		2796	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2797	{
		2798	struct drm_i915_gem_object *obj;
		2799	struct drm_i915_private *dev_priv;
		2800
		2801	if (crtc->fb == NULL)
		2802	return;
		2803
		2804	obj = to_intel_framebuffer(crtc->fb)->obj;
		2805	dev_priv = crtc->dev->dev_private;
		2806	// wait_event(dev_priv->pending_flip_queue,
		2807	// atomic_read(&obj->pending_flip) == 0);
		2808	}
		2809
		2810	static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
		2811	{
		2812	struct drm_device *dev = crtc->dev;
		2813	struct drm_mode_config *mode_config = &dev->mode_config;
		2814	struct intel_encoder *encoder;
		2815
		2816	/*
		2817	* If there's a non-PCH eDP on this crtc, it must be DP_A, and that
		2818	* must be driven by its own crtc; no sharing is possible.
		2819	*/
		2820	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		2821	if (encoder->base.crtc != crtc)
		2822	continue;
		2823
		2824	switch (encoder->type) {
		2825	case INTEL_OUTPUT_EDP:
		2826	if (!intel_encoder_is_pch_edp(&encoder->base))
		2827	return false;
		2828	continue;
		2829	}
		2830	}
		2831
		2832	return true;
		2833	}
		2834
		2835	/*
		2836	* Enable PCH resources required for PCH ports:
		2837	* - PCH PLLs
		2838	* - FDI training & RX/TX
		2839	* - update transcoder timings
		2840	* - DP transcoding bits
		2841	* - transcoder
		2842	*/
		2843	static void ironlake_pch_enable(struct drm_crtc *crtc)
		2844	{
		2845	struct drm_device *dev = crtc->dev;
		2846	struct drm_i915_private *dev_priv = dev->dev_private;
		2847	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2848	int pipe = intel_crtc->pipe;
		2849	u32 reg, temp;
		2850
		2851	/* For PCH output, training FDI link */
		2852	dev_priv->display.fdi_link_train(crtc);
		2853
		2854	intel_enable_pch_pll(dev_priv, pipe);
		2855
		2856	if (HAS_PCH_CPT(dev)) {
		2857	/* Be sure PCH DPLL SEL is set */
		2858	temp = I915_READ(PCH_DPLL_SEL);
		2859	if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
		2860	temp \|= (TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL);
		2861	else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
		2862	temp \|= (TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
		2863	I915_WRITE(PCH_DPLL_SEL, temp);
		2864	}
		2865
		2866	/* set transcoder timing, panel must allow it */
		2867	assert_panel_unlocked(dev_priv, pipe);
		2868	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
		2869	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
		2870	I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
		2871
		2872	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
		2873	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
		2874	I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
		2875
		2876	intel_fdi_normal_train(crtc);
		2877
		2878	/* For PCH DP, enable TRANS_DP_CTL */
		2879	if (HAS_PCH_CPT(dev) &&
		2880	intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		2881	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
		2882	reg = TRANS_DP_CTL(pipe);
		2883	temp = I915_READ(reg);
		2884	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		2885	TRANS_DP_SYNC_MASK \|
		2886	TRANS_DP_BPC_MASK);
		2887	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		2888	TRANS_DP_ENH_FRAMING);
		2889	temp \|= bpc << 9; /* same format but at 11:9 */
		2890
		2891	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		2892	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		2893	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		2894	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		2895
		2896	switch (intel_trans_dp_port_sel(crtc)) {
		2897	case PCH_DP_B:
		2898	temp \|= TRANS_DP_PORT_SEL_B;
		2899	break;
		2900	case PCH_DP_C:
		2901	temp \|= TRANS_DP_PORT_SEL_C;
		2902	break;
		2903	case PCH_DP_D:
		2904	temp \|= TRANS_DP_PORT_SEL_D;
		2905	break;
		2906	default:
		2907	DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
		2908	temp \|= TRANS_DP_PORT_SEL_B;
		2909	break;
		2910	}
		2911
		2912	I915_WRITE(reg, temp);
		2913	}
		2914
		2915	intel_enable_transcoder(dev_priv, pipe);
		2916	}
		2917
		2918	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		2919	{
		2920	struct drm_device *dev = crtc->dev;
		2921	struct drm_i915_private *dev_priv = dev->dev_private;
		2922	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2923	int pipe = intel_crtc->pipe;
		2924	int plane = intel_crtc->plane;
		2925	u32 temp;
		2926	bool is_pch_port;
		2927
		2928	if (intel_crtc->active)
		2929	return;
		2930
		2931	intel_crtc->active = true;
		2932	intel_update_watermarks(dev);
		2933
		2934	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		2935	temp = I915_READ(PCH_LVDS);
		2936	if ((temp & LVDS_PORT_EN) == 0)
		2937	I915_WRITE(PCH_LVDS, temp \| LVDS_PORT_EN);
		2938	}
		2939
		2940	is_pch_port = intel_crtc_driving_pch(crtc);
		2941
		2942	if (is_pch_port)
		2943	ironlake_fdi_pll_enable(crtc);
		2944	else
		2945	ironlake_fdi_disable(crtc);
		2946
		2947	/* Enable panel fitting for LVDS */
		2948	if (dev_priv->pch_pf_size &&
		2949	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\| HAS_eDP)) {
		2950	/* Force use of hard-coded filter coefficients
		2951	* as some pre-programmed values are broken,
		2952	* e.g. x201.
		2953	*/
		2954	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		2955	I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		2956	I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
		2957	}
		2958
		2959	/*
		2960	* On ILK+ LUT must be loaded before the pipe is running but with
		2961	* clocks enabled
		2962	*/
		2963	intel_crtc_load_lut(crtc);
		2964
		2965	intel_enable_pipe(dev_priv, pipe, is_pch_port);
		2966	intel_enable_plane(dev_priv, plane, pipe);
		2967
		2968	if (is_pch_port)
		2969	ironlake_pch_enable(crtc);
		2970
		2971	mutex_lock(&dev->struct_mutex);
		2972	intel_update_fbc(dev);
		2973	mutex_unlock(&dev->struct_mutex);
		2974
		2975	// intel_crtc_update_cursor(crtc, true);
		2976	}
		2977
		2978	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		2979	{
		2980	struct drm_device *dev = crtc->dev;
		2981	struct drm_i915_private *dev_priv = dev->dev_private;
		2982	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2983	int pipe = intel_crtc->pipe;
		2984	int plane = intel_crtc->plane;
		2985	u32 reg, temp;
		2986
		2987	if (!intel_crtc->active)
		2988	return;
		2989
		2990	intel_crtc_wait_for_pending_flips(crtc);
		2991	// drm_vblank_off(dev, pipe);
		2992	// intel_crtc_update_cursor(crtc, false);
		2993
		2994	intel_disable_plane(dev_priv, plane, pipe);
		2995
		2996	if (dev_priv->cfb_plane == plane)
		2997	intel_disable_fbc(dev);
		2998
		2999	intel_disable_pipe(dev_priv, pipe);
		3000
		3001	/* Disable PF */
		3002	I915_WRITE(PF_CTL(pipe), 0);
		3003	I915_WRITE(PF_WIN_SZ(pipe), 0);
		3004
		3005	ironlake_fdi_disable(crtc);
		3006
		3007	/* This is a horrible layering violation; we should be doing this in
		3008	* the connector/encoder ->prepare instead, but we don't always have
		3009	* enough information there about the config to know whether it will
		3010	* actually be necessary or just cause undesired flicker.
		3011	*/
		3012	intel_disable_pch_ports(dev_priv, pipe);
		3013
		3014	intel_disable_transcoder(dev_priv, pipe);
		3015
		3016	if (HAS_PCH_CPT(dev)) {
		3017	/* disable TRANS_DP_CTL */
		3018	reg = TRANS_DP_CTL(pipe);
		3019	temp = I915_READ(reg);
		3020	temp &= ~(TRANS_DP_OUTPUT_ENABLE \| TRANS_DP_PORT_SEL_MASK);
		3021	temp \|= TRANS_DP_PORT_SEL_NONE;
		3022	I915_WRITE(reg, temp);
		3023
		3024	/* disable DPLL_SEL */
		3025	temp = I915_READ(PCH_DPLL_SEL);
		3026	switch (pipe) {
		3027	case 0:
		3028	temp &= ~(TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL);
		3029	break;
		3030	case 1:
		3031	temp &= ~(TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
		3032	break;
		3033	case 2:
		3034	/* FIXME: manage transcoder PLLs? */
		3035	temp &= ~(TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL);
		3036	break;
		3037	default:
		3038	BUG(); /* wtf */
		3039	}
		3040	I915_WRITE(PCH_DPLL_SEL, temp);
		3041	}
		3042
		3043	/* disable PCH DPLL */
		3044	intel_disable_pch_pll(dev_priv, pipe);
		3045
		3046	/* Switch from PCDclk to Rawclk */
		3047	reg = FDI_RX_CTL(pipe);
		3048	temp = I915_READ(reg);
		3049	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		3050
		3051	/* Disable CPU FDI TX PLL */
		3052	reg = FDI_TX_CTL(pipe);
		3053	temp = I915_READ(reg);
		3054	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		3055
		3056	POSTING_READ(reg);
		3057	udelay(100);
		3058
		3059	reg = FDI_RX_CTL(pipe);
		3060	temp = I915_READ(reg);
		3061	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		3062
		3063	/* Wait for the clocks to turn off. */
		3064	POSTING_READ(reg);
		3065	udelay(100);
		3066
		3067	intel_crtc->active = false;
		3068	intel_update_watermarks(dev);
		3069
		3070	mutex_lock(&dev->struct_mutex);
		3071	intel_update_fbc(dev);
		3072	intel_clear_scanline_wait(dev);
		3073	mutex_unlock(&dev->struct_mutex);
		3074	}
		3075
		3076	static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
		3077	{
		3078	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3079	int pipe = intel_crtc->pipe;
		3080	int plane = intel_crtc->plane;
		3081
		3082	/* XXX: When our outputs are all unaware of DPMS modes other than off
		3083	* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
		3084	*/
		3085	switch (mode) {
		3086	case DRM_MODE_DPMS_ON:
		3087	case DRM_MODE_DPMS_STANDBY:
		3088	case DRM_MODE_DPMS_SUSPEND:
		3089	DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
		3090	ironlake_crtc_enable(crtc);
		3091	break;
		3092
		3093	case DRM_MODE_DPMS_OFF:
		3094	DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
		3095	ironlake_crtc_disable(crtc);
		3096	break;
		3097	}
		3098	}
		3099
		3100	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3101	{
		3102	if (!enable && intel_crtc->overlay) {
		3103	struct drm_device *dev = intel_crtc->base.dev;
		3104	struct drm_i915_private *dev_priv = dev->dev_private;
		3105
		3106	mutex_lock(&dev->struct_mutex);
		3107	dev_priv->mm.interruptible = false;
		3108	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3109	dev_priv->mm.interruptible = true;
		3110	mutex_unlock(&dev->struct_mutex);
		3111	}
		3112
		3113	/* Let userspace switch the overlay on again. In most cases userspace
		3114	* has to recompute where to put it anyway.
		3115	*/
		3116	}
		3117
		3118	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3119	{
		3120	struct drm_device *dev = crtc->dev;
		3121	struct drm_i915_private *dev_priv = dev->dev_private;
		3122	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3123	int pipe = intel_crtc->pipe;
		3124	int plane = intel_crtc->plane;
		3125
		3126	if (intel_crtc->active)
		3127	return;
		3128
		3129	intel_crtc->active = true;
		3130	intel_update_watermarks(dev);
		3131
		3132	intel_enable_pll(dev_priv, pipe);
		3133	intel_enable_pipe(dev_priv, pipe, false);
		3134	intel_enable_plane(dev_priv, plane, pipe);
		3135
		3136	intel_crtc_load_lut(crtc);
		3137	intel_update_fbc(dev);
		3138
		3139	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3140	intel_crtc_dpms_overlay(intel_crtc, true);
		3141	// intel_crtc_update_cursor(crtc, true);
		3142	}
		3143
		3144	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3145	{
		3146	struct drm_device *dev = crtc->dev;
		3147	struct drm_i915_private *dev_priv = dev->dev_private;
		3148	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3149	int pipe = intel_crtc->pipe;
		3150	int plane = intel_crtc->plane;
		3151
		3152	if (!intel_crtc->active)
		3153	return;
		3154
		3155	/* Give the overlay scaler a chance to disable if it's on this pipe */
		3156	intel_crtc_wait_for_pending_flips(crtc);
		3157	// drm_vblank_off(dev, pipe);
		3158	intel_crtc_dpms_overlay(intel_crtc, false);
		3159	// intel_crtc_update_cursor(crtc, false);
		3160
		3161	if (dev_priv->cfb_plane == plane)
		3162	intel_disable_fbc(dev);
		3163
		3164	intel_disable_plane(dev_priv, plane, pipe);
		3165	intel_disable_pipe(dev_priv, pipe);
		3166	intel_disable_pll(dev_priv, pipe);
		3167
		3168	intel_crtc->active = false;
		3169	intel_update_fbc(dev);
		3170	intel_update_watermarks(dev);
		3171	intel_clear_scanline_wait(dev);
		3172	}
		3173
		3174	static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
		3175	{
		3176	/* XXX: When our outputs are all unaware of DPMS modes other than off
		3177	* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
		3178	*/
		3179	switch (mode) {
		3180	case DRM_MODE_DPMS_ON:
		3181	case DRM_MODE_DPMS_STANDBY:
		3182	case DRM_MODE_DPMS_SUSPEND:
		3183	i9xx_crtc_enable(crtc);
		3184	break;
		3185	case DRM_MODE_DPMS_OFF:
		3186	i9xx_crtc_disable(crtc);
		3187	break;
		3188	}
		3189	}
		3190
2330	Serge	3191	/**
		3192	* Sets the power management mode of the pipe and plane.
		3193	*/
		3194	static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
		3195	{
		3196	struct drm_device *dev = crtc->dev;
		3197	struct drm_i915_private *dev_priv = dev->dev_private;
		3198	struct drm_i915_master_private *master_priv;
		3199	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3200	int pipe = intel_crtc->pipe;
		3201	bool enabled;
2327	Serge	3202
2330	Serge	3203	if (intel_crtc->dpms_mode == mode)
		3204	return;
2327	Serge	3205
2330	Serge	3206	intel_crtc->dpms_mode = mode;
2327	Serge	3207
2330	Serge	3208	dev_priv->display.dpms(crtc, mode);
2327	Serge	3209
2330	Serge	3210	if (!dev->primary->master)
		3211	return;
2327	Serge	3212
2330	Serge	3213	master_priv = dev->primary->master->driver_priv;
		3214	if (!master_priv->sarea_priv)
		3215	return;
2327	Serge	3216
2330	Serge	3217	enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2327	Serge	3218
2330	Serge	3219	switch (pipe) {
		3220	case 0:
		3221	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3222	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3223	break;
		3224	case 1:
		3225	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3226	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3227	break;
		3228	default:
		3229	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3230	break;
		3231	}
		3232	}
2327	Serge	3233
2330	Serge	3234	static void intel_crtc_disable(struct drm_crtc *crtc)
		3235	{
		3236	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
		3237	struct drm_device *dev = crtc->dev;
2327	Serge	3238
2330	Serge	3239	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2327	Serge	3240
2330	Serge	3241	if (crtc->fb) {
		3242	mutex_lock(&dev->struct_mutex);
		3243	// i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
		3244	mutex_unlock(&dev->struct_mutex);
		3245	}
		3246	}
2327	Serge	3247
2330	Serge	3248	/* Prepare for a mode set.
		3249	*
		3250	* Note we could be a lot smarter here. We need to figure out which outputs
		3251	* will be enabled, which disabled (in short, how the config will changes)
		3252	* and perform the minimum necessary steps to accomplish that, e.g. updating
		3253	* watermarks, FBC configuration, making sure PLLs are programmed correctly,
		3254	* panel fitting is in the proper state, etc.
		3255	*/
		3256	static void i9xx_crtc_prepare(struct drm_crtc *crtc)
		3257	{
		3258	i9xx_crtc_disable(crtc);
		3259	}
2327	Serge	3260
2330	Serge	3261	static void i9xx_crtc_commit(struct drm_crtc *crtc)
		3262	{
		3263	i9xx_crtc_enable(crtc);
		3264	}
2327	Serge	3265
2330	Serge	3266	static void ironlake_crtc_prepare(struct drm_crtc *crtc)
		3267	{
		3268	ironlake_crtc_disable(crtc);
		3269	}
2327	Serge	3270
2330	Serge	3271	static void ironlake_crtc_commit(struct drm_crtc *crtc)
		3272	{
		3273	ironlake_crtc_enable(crtc);
		3274	}
2327	Serge	3275
2330	Serge	3276	void intel_encoder_prepare (struct drm_encoder *encoder)
		3277	{
		3278	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
		3279	/* lvds has its own version of prepare see intel_lvds_prepare */
		3280	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
		3281	}
2327	Serge	3282
2330	Serge	3283	void intel_encoder_commit (struct drm_encoder *encoder)
		3284	{
		3285	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
		3286	/* lvds has its own version of commit see intel_lvds_commit */
		3287	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
		3288	}
2327	Serge	3289
2330	Serge	3290	void intel_encoder_destroy(struct drm_encoder *encoder)
		3291	{
		3292	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3293
		3294	drm_encoder_cleanup(encoder);
		3295	kfree(intel_encoder);
		3296	}
		3297
		3298	static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
		3299	struct drm_display_mode *mode,
		3300	struct drm_display_mode *adjusted_mode)
		3301	{
		3302	struct drm_device *dev = crtc->dev;
		3303
		3304	if (HAS_PCH_SPLIT(dev)) {
		3305	/* FDI link clock is fixed at 2.7G */
		3306	if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
		3307	return false;
		3308	}
		3309
		3310	/* XXX some encoders set the crtcinfo, others don't.
		3311	* Obviously we need some form of conflict resolution here...
		3312	*/
		3313	if (adjusted_mode->crtc_htotal == 0)
		3314	drm_mode_set_crtcinfo(adjusted_mode, 0);
		3315
		3316	return true;
		3317	}
		3318
2327	Serge	3319	static int i945_get_display_clock_speed(struct drm_device *dev)
		3320	{
		3321	return 400000;
		3322	}
		3323
		3324	static int i915_get_display_clock_speed(struct drm_device *dev)
		3325	{
		3326	return 333000;
		3327	}
		3328
		3329	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		3330	{
		3331	return 200000;
		3332	}
		3333
		3334	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		3335	{
		3336	u16 gcfgc = 0;
		3337
		3338	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		3339
		3340	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		3341	return 133000;
		3342	else {
		3343	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		3344	case GC_DISPLAY_CLOCK_333_MHZ:
		3345	return 333000;
		3346	default:
		3347	case GC_DISPLAY_CLOCK_190_200_MHZ:
		3348	return 190000;
		3349	}
		3350	}
		3351	}
		3352
		3353	static int i865_get_display_clock_speed(struct drm_device *dev)
		3354	{
		3355	return 266000;
		3356	}
		3357
		3358	static int i855_get_display_clock_speed(struct drm_device *dev)
		3359	{
		3360	u16 hpllcc = 0;
		3361	/* Assume that the hardware is in the high speed state. This
		3362	* should be the default.
		3363	*/
		3364	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		3365	case GC_CLOCK_133_200:
		3366	case GC_CLOCK_100_200:
		3367	return 200000;
		3368	case GC_CLOCK_166_250:
		3369	return 250000;
		3370	case GC_CLOCK_100_133:
		3371	return 133000;
		3372	}
		3373
		3374	/* Shouldn't happen */
		3375	return 0;
		3376	}
		3377
		3378	static int i830_get_display_clock_speed(struct drm_device *dev)
		3379	{
		3380	return 133000;
		3381	}
		3382
		3383	struct fdi_m_n {
		3384	u32 tu;
		3385	u32 gmch_m;
		3386	u32 gmch_n;
		3387	u32 link_m;
		3388	u32 link_n;
		3389	};
		3390
		3391	static void
		3392	fdi_reduce_ratio(u32 num, u32 den)
		3393	{
		3394	while (num > 0xffffff \|\| den > 0xffffff) {
		3395	*num >>= 1;
		3396	*den >>= 1;
		3397	}
		3398	}
		3399
		3400	static void
		3401	ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
		3402	int link_clock, struct fdi_m_n *m_n)
		3403	{
		3404	m_n->tu = 64; /* default size */
		3405
		3406	/* BUG_ON(pixel_clock > INT_MAX / 36); */
		3407	m_n->gmch_m = bits_per_pixel * pixel_clock;
		3408	m_n->gmch_n = link_clock * nlanes * 8;
		3409	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
		3410
		3411	m_n->link_m = pixel_clock;
		3412	m_n->link_n = link_clock;
		3413	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
		3414	}
		3415
		3416
		3417	struct intel_watermark_params {
		3418	unsigned long fifo_size;
		3419	unsigned long max_wm;
		3420	unsigned long default_wm;
		3421	unsigned long guard_size;
		3422	unsigned long cacheline_size;
		3423	};
		3424
		3425	/* Pineview has different values for various configs */
		3426	static const struct intel_watermark_params pineview_display_wm = {
		3427	PINEVIEW_DISPLAY_FIFO,
		3428	PINEVIEW_MAX_WM,
		3429	PINEVIEW_DFT_WM,
		3430	PINEVIEW_GUARD_WM,
		3431	PINEVIEW_FIFO_LINE_SIZE
		3432	};
		3433	static const struct intel_watermark_params pineview_display_hplloff_wm = {
		3434	PINEVIEW_DISPLAY_FIFO,
		3435	PINEVIEW_MAX_WM,
		3436	PINEVIEW_DFT_HPLLOFF_WM,
		3437	PINEVIEW_GUARD_WM,
		3438	PINEVIEW_FIFO_LINE_SIZE
		3439	};
		3440	static const struct intel_watermark_params pineview_cursor_wm = {
		3441	PINEVIEW_CURSOR_FIFO,
		3442	PINEVIEW_CURSOR_MAX_WM,
		3443	PINEVIEW_CURSOR_DFT_WM,
		3444	PINEVIEW_CURSOR_GUARD_WM,
		3445	PINEVIEW_FIFO_LINE_SIZE,
		3446	};
		3447	static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
		3448	PINEVIEW_CURSOR_FIFO,
		3449	PINEVIEW_CURSOR_MAX_WM,
		3450	PINEVIEW_CURSOR_DFT_WM,
		3451	PINEVIEW_CURSOR_GUARD_WM,
		3452	PINEVIEW_FIFO_LINE_SIZE
		3453	};
		3454	static const struct intel_watermark_params g4x_wm_info = {
		3455	G4X_FIFO_SIZE,
		3456	G4X_MAX_WM,
		3457	G4X_MAX_WM,
		3458	2,
		3459	G4X_FIFO_LINE_SIZE,
		3460	};
		3461	static const struct intel_watermark_params g4x_cursor_wm_info = {
		3462	I965_CURSOR_FIFO,
		3463	I965_CURSOR_MAX_WM,
		3464	I965_CURSOR_DFT_WM,
		3465	2,
		3466	G4X_FIFO_LINE_SIZE,
		3467	};
		3468	static const struct intel_watermark_params i965_cursor_wm_info = {
		3469	I965_CURSOR_FIFO,
		3470	I965_CURSOR_MAX_WM,
		3471	I965_CURSOR_DFT_WM,
		3472	2,
		3473	I915_FIFO_LINE_SIZE,
		3474	};
		3475	static const struct intel_watermark_params i945_wm_info = {
		3476	I945_FIFO_SIZE,
		3477	I915_MAX_WM,
		3478	1,
		3479	2,
		3480	I915_FIFO_LINE_SIZE
		3481	};
		3482	static const struct intel_watermark_params i915_wm_info = {
		3483	I915_FIFO_SIZE,
		3484	I915_MAX_WM,
		3485	1,
		3486	2,
		3487	I915_FIFO_LINE_SIZE
		3488	};
		3489	static const struct intel_watermark_params i855_wm_info = {
		3490	I855GM_FIFO_SIZE,
		3491	I915_MAX_WM,
		3492	1,
		3493	2,
		3494	I830_FIFO_LINE_SIZE
		3495	};
		3496	static const struct intel_watermark_params i830_wm_info = {
		3497	I830_FIFO_SIZE,
		3498	I915_MAX_WM,
		3499	1,
		3500	2,
		3501	I830_FIFO_LINE_SIZE
		3502	};
		3503
		3504	static const struct intel_watermark_params ironlake_display_wm_info = {
		3505	ILK_DISPLAY_FIFO,
		3506	ILK_DISPLAY_MAXWM,
		3507	ILK_DISPLAY_DFTWM,
		3508	2,
		3509	ILK_FIFO_LINE_SIZE
		3510	};
		3511	static const struct intel_watermark_params ironlake_cursor_wm_info = {
		3512	ILK_CURSOR_FIFO,
		3513	ILK_CURSOR_MAXWM,
		3514	ILK_CURSOR_DFTWM,
		3515	2,
		3516	ILK_FIFO_LINE_SIZE
		3517	};
		3518	static const struct intel_watermark_params ironlake_display_srwm_info = {
		3519	ILK_DISPLAY_SR_FIFO,
		3520	ILK_DISPLAY_MAX_SRWM,
		3521	ILK_DISPLAY_DFT_SRWM,
		3522	2,
		3523	ILK_FIFO_LINE_SIZE
		3524	};
		3525	static const struct intel_watermark_params ironlake_cursor_srwm_info = {
		3526	ILK_CURSOR_SR_FIFO,
		3527	ILK_CURSOR_MAX_SRWM,
		3528	ILK_CURSOR_DFT_SRWM,
		3529	2,
		3530	ILK_FIFO_LINE_SIZE
		3531	};
		3532
		3533	static const struct intel_watermark_params sandybridge_display_wm_info = {
		3534	SNB_DISPLAY_FIFO,
		3535	SNB_DISPLAY_MAXWM,
		3536	SNB_DISPLAY_DFTWM,
		3537	2,
		3538	SNB_FIFO_LINE_SIZE
		3539	};
		3540	static const struct intel_watermark_params sandybridge_cursor_wm_info = {
		3541	SNB_CURSOR_FIFO,
		3542	SNB_CURSOR_MAXWM,
		3543	SNB_CURSOR_DFTWM,
		3544	2,
		3545	SNB_FIFO_LINE_SIZE
		3546	};
		3547	static const struct intel_watermark_params sandybridge_display_srwm_info = {
		3548	SNB_DISPLAY_SR_FIFO,
		3549	SNB_DISPLAY_MAX_SRWM,
		3550	SNB_DISPLAY_DFT_SRWM,
		3551	2,
		3552	SNB_FIFO_LINE_SIZE
		3553	};
		3554	static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
		3555	SNB_CURSOR_SR_FIFO,
		3556	SNB_CURSOR_MAX_SRWM,
		3557	SNB_CURSOR_DFT_SRWM,
		3558	2,
		3559	SNB_FIFO_LINE_SIZE
		3560	};
		3561
		3562
		3563	/**
		3564	* intel_calculate_wm - calculate watermark level
		3565	* @clock_in_khz: pixel clock
		3566	* @wm: chip FIFO params
		3567	* @pixel_size: display pixel size
		3568	* @latency_ns: memory latency for the platform
		3569	*
		3570	* Calculate the watermark level (the level at which the display plane will
		3571	* start fetching from memory again). Each chip has a different display
		3572	* FIFO size and allocation, so the caller needs to figure that out and pass
		3573	* in the correct intel_watermark_params structure.
		3574	*
		3575	* As the pixel clock runs, the FIFO will be drained at a rate that depends
		3576	* on the pixel size. When it reaches the watermark level, it'll start
		3577	* fetching FIFO line sized based chunks from memory until the FIFO fills
		3578	* past the watermark point. If the FIFO drains completely, a FIFO underrun
		3579	* will occur, and a display engine hang could result.
		3580	*/
		3581	static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
		3582	const struct intel_watermark_params *wm,
		3583	int fifo_size,
		3584	int pixel_size,
		3585	unsigned long latency_ns)
		3586	{
		3587	long entries_required, wm_size;
		3588
		3589	/*
		3590	* Note: we need to make sure we don't overflow for various clock &
		3591	* latency values.
		3592	* clocks go from a few thousand to several hundred thousand.
		3593	* latency is usually a few thousand
		3594	*/
		3595	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
		3596	1000;
		3597	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
		3598
		3599	DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
		3600
		3601	wm_size = fifo_size - (entries_required + wm->guard_size);
		3602
		3603	DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
		3604
		3605	/* Don't promote wm_size to unsigned... */
		3606	if (wm_size > (long)wm->max_wm)
		3607	wm_size = wm->max_wm;
		3608	if (wm_size <= 0)
		3609	wm_size = wm->default_wm;
		3610	return wm_size;
		3611	}
		3612
		3613	struct cxsr_latency {
		3614	int is_desktop;
		3615	int is_ddr3;
		3616	unsigned long fsb_freq;
		3617	unsigned long mem_freq;
		3618	unsigned long display_sr;
		3619	unsigned long display_hpll_disable;
		3620	unsigned long cursor_sr;
		3621	unsigned long cursor_hpll_disable;
		3622	};
		3623
		3624	static const struct cxsr_latency cxsr_latency_table[] = {
		3625	{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
		3626	{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
		3627	{1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
		3628	{1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
		3629	{1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
		3630
		3631	{1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
		3632	{1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
		3633	{1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
		3634	{1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
		3635	{1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
		3636
		3637	{1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
		3638	{1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
		3639	{1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
		3640	{1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
		3641	{1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
		3642
		3643	{0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
		3644	{0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
		3645	{0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
		3646	{0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
		3647	{0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
		3648
		3649	{0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
		3650	{0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
		3651	{0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
		3652	{0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
		3653	{0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
		3654
		3655	{0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
		3656	{0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
		3657	{0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
		3658	{0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
		3659	{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
		3660	};
		3661
		3662	static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
		3663	int is_ddr3,
		3664	int fsb,
		3665	int mem)
		3666	{
		3667	const struct cxsr_latency *latency;
		3668	int i;
		3669
		3670	if (fsb == 0 \|\| mem == 0)
		3671	return NULL;
		3672
		3673	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
		3674	latency = &cxsr_latency_table[i];
		3675	if (is_desktop == latency->is_desktop &&
		3676	is_ddr3 == latency->is_ddr3 &&
		3677	fsb == latency->fsb_freq && mem == latency->mem_freq)
		3678	return latency;
		3679	}
		3680
		3681	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
		3682
		3683	return NULL;
		3684	}
		3685
		3686	static void pineview_disable_cxsr(struct drm_device *dev)
		3687	{
		3688	struct drm_i915_private *dev_priv = dev->dev_private;
		3689
		3690	/* deactivate cxsr */
		3691	I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
		3692	}
		3693
		3694	/*
		3695	* Latency for FIFO fetches is dependent on several factors:
		3696	* - memory configuration (speed, channels)
		3697	* - chipset
		3698	* - current MCH state
		3699	* It can be fairly high in some situations, so here we assume a fairly
		3700	* pessimal value. It's a tradeoff between extra memory fetches (if we
		3701	* set this value too high, the FIFO will fetch frequently to stay full)
		3702	* and power consumption (set it too low to save power and we might see
		3703	* FIFO underruns and display "flicker").
		3704	*
		3705	* A value of 5us seems to be a good balance; safe for very low end
		3706	* platforms but not overly aggressive on lower latency configs.
		3707	*/
		3708	static const int latency_ns = 5000;
		3709
		3710	static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
		3711	{
		3712	struct drm_i915_private *dev_priv = dev->dev_private;
		3713	uint32_t dsparb = I915_READ(DSPARB);
		3714	int size;
		3715
		3716	size = dsparb & 0x7f;
		3717	if (plane)
		3718	size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
		3719
		3720	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		3721	plane ? "B" : "A", size);
		3722
		3723	return size;
		3724	}
		3725
		3726	static int i85x_get_fifo_size(struct drm_device *dev, int plane)
		3727	{
		3728	struct drm_i915_private *dev_priv = dev->dev_private;
		3729	uint32_t dsparb = I915_READ(DSPARB);
		3730	int size;
		3731
		3732	size = dsparb & 0x1ff;
		3733	if (plane)
		3734	size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
		3735	size >>= 1; /* Convert to cachelines */
		3736
		3737	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		3738	plane ? "B" : "A", size);
		3739
		3740	return size;
		3741	}
		3742
		3743	static int i845_get_fifo_size(struct drm_device *dev, int plane)
		3744	{
		3745	struct drm_i915_private *dev_priv = dev->dev_private;
		3746	uint32_t dsparb = I915_READ(DSPARB);
		3747	int size;
		3748
		3749	size = dsparb & 0x7f;
		3750	size >>= 2; /* Convert to cachelines */
		3751
		3752	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		3753	plane ? "B" : "A",
		3754	size);
		3755
		3756	return size;
		3757	}
		3758
		3759	static int i830_get_fifo_size(struct drm_device *dev, int plane)
		3760	{
		3761	struct drm_i915_private *dev_priv = dev->dev_private;
		3762	uint32_t dsparb = I915_READ(DSPARB);
		3763	int size;
		3764
		3765	size = dsparb & 0x7f;
		3766	size >>= 1; /* Convert to cachelines */
		3767
		3768	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		3769	plane ? "B" : "A", size);
		3770
		3771	return size;
		3772	}
		3773
		3774	static struct drm_crtc single_enabled_crtc(struct drm_device dev)
		3775	{
		3776	struct drm_crtc crtc, enabled = NULL;
		3777
		3778	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		3779	if (crtc->enabled && crtc->fb) {
		3780	if (enabled)
		3781	return NULL;
		3782	enabled = crtc;
		3783	}
		3784	}
		3785
		3786	return enabled;
		3787	}
		3788
		3789	static void pineview_update_wm(struct drm_device *dev)
		3790	{
		3791	struct drm_i915_private *dev_priv = dev->dev_private;
		3792	struct drm_crtc *crtc;
		3793	const struct cxsr_latency *latency;
		3794	u32 reg;
		3795	unsigned long wm;
		3796
		3797	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
		3798	dev_priv->fsb_freq, dev_priv->mem_freq);
		3799	if (!latency) {
		3800	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
		3801	pineview_disable_cxsr(dev);
		3802	return;
		3803	}
		3804
		3805	crtc = single_enabled_crtc(dev);
		3806	if (crtc) {
		3807	int clock = crtc->mode.clock;
		3808	int pixel_size = crtc->fb->bits_per_pixel / 8;
		3809
		3810	/* Display SR */
		3811	wm = intel_calculate_wm(clock, &pineview_display_wm,
		3812	pineview_display_wm.fifo_size,
		3813	pixel_size, latency->display_sr);
		3814	reg = I915_READ(DSPFW1);
		3815	reg &= ~DSPFW_SR_MASK;
		3816	reg \|= wm << DSPFW_SR_SHIFT;
		3817	I915_WRITE(DSPFW1, reg);
		3818	DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
		3819
		3820	/* cursor SR */
		3821	wm = intel_calculate_wm(clock, &pineview_cursor_wm,
		3822	pineview_display_wm.fifo_size,
		3823	pixel_size, latency->cursor_sr);
		3824	reg = I915_READ(DSPFW3);
		3825	reg &= ~DSPFW_CURSOR_SR_MASK;
		3826	reg \|= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
		3827	I915_WRITE(DSPFW3, reg);
		3828
		3829	/* Display HPLL off SR */
		3830	wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
		3831	pineview_display_hplloff_wm.fifo_size,
		3832	pixel_size, latency->display_hpll_disable);
		3833	reg = I915_READ(DSPFW3);
		3834	reg &= ~DSPFW_HPLL_SR_MASK;
		3835	reg \|= wm & DSPFW_HPLL_SR_MASK;
		3836	I915_WRITE(DSPFW3, reg);
		3837
		3838	/* cursor HPLL off SR */
		3839	wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
		3840	pineview_display_hplloff_wm.fifo_size,
		3841	pixel_size, latency->cursor_hpll_disable);
		3842	reg = I915_READ(DSPFW3);
		3843	reg &= ~DSPFW_HPLL_CURSOR_MASK;
		3844	reg \|= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
		3845	I915_WRITE(DSPFW3, reg);
		3846	DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
		3847
		3848	/* activate cxsr */
		3849	I915_WRITE(DSPFW3,
		3850	I915_READ(DSPFW3) \| PINEVIEW_SELF_REFRESH_EN);
		3851	DRM_DEBUG_KMS("Self-refresh is enabled\n");
		3852	} else {
		3853	pineview_disable_cxsr(dev);
		3854	DRM_DEBUG_KMS("Self-refresh is disabled\n");
		3855	}
		3856	}
		3857
		3858	static bool g4x_compute_wm0(struct drm_device *dev,
		3859	int plane,
		3860	const struct intel_watermark_params *display,
		3861	int display_latency_ns,
		3862	const struct intel_watermark_params *cursor,
		3863	int cursor_latency_ns,
		3864	int *plane_wm,
		3865	int *cursor_wm)
		3866	{
		3867	struct drm_crtc *crtc;
		3868	int htotal, hdisplay, clock, pixel_size;
		3869	int line_time_us, line_count;
		3870	int entries, tlb_miss;
		3871
		3872	crtc = intel_get_crtc_for_plane(dev, plane);
		3873	if (crtc->fb == NULL \|\| !crtc->enabled) {
		3874	*cursor_wm = cursor->guard_size;
		3875	*plane_wm = display->guard_size;
		3876	return false;
		3877	}
		3878
		3879	htotal = crtc->mode.htotal;
		3880	hdisplay = crtc->mode.hdisplay;
		3881	clock = crtc->mode.clock;
		3882	pixel_size = crtc->fb->bits_per_pixel / 8;
		3883
		3884	/* Use the small buffer method to calculate plane watermark */
		3885	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
		3886	tlb_miss = display->fifo_sizedisplay->cacheline_size - hdisplay 8;
		3887	if (tlb_miss > 0)
		3888	entries += tlb_miss;
		3889	entries = DIV_ROUND_UP(entries, display->cacheline_size);
		3890	*plane_wm = entries + display->guard_size;
		3891	if (*plane_wm > (int)display->max_wm)
		3892	*plane_wm = display->max_wm;
		3893
		3894	/* Use the large buffer method to calculate cursor watermark */
		3895	line_time_us = ((htotal * 1000) / clock);
		3896	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
		3897	entries = line_count * 64 * pixel_size;
		3898	tlb_miss = cursor->fifo_sizecursor->cacheline_size - hdisplay 8;
		3899	if (tlb_miss > 0)
		3900	entries += tlb_miss;
		3901	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
		3902	*cursor_wm = entries + cursor->guard_size;
		3903	if (*cursor_wm > (int)cursor->max_wm)
		3904	*cursor_wm = (int)cursor->max_wm;
		3905
		3906	return true;
		3907	}
		3908
		3909	/*
		3910	* Check the wm result.
		3911	*
		3912	* If any calculated watermark values is larger than the maximum value that
		3913	* can be programmed into the associated watermark register, that watermark
		3914	* must be disabled.
		3915	*/
		3916	static bool g4x_check_srwm(struct drm_device *dev,
		3917	int display_wm, int cursor_wm,
		3918	const struct intel_watermark_params *display,
		3919	const struct intel_watermark_params *cursor)
		3920	{
		3921	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
		3922	display_wm, cursor_wm);
		3923
		3924	if (display_wm > display->max_wm) {
		3925	DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
		3926	display_wm, display->max_wm);
		3927	return false;
		3928	}
		3929
		3930	if (cursor_wm > cursor->max_wm) {
		3931	DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
		3932	cursor_wm, cursor->max_wm);
		3933	return false;
		3934	}
		3935
		3936	if (!(display_wm \|\| cursor_wm)) {
		3937	DRM_DEBUG_KMS("SR latency is 0, disabling\n");
		3938	return false;
		3939	}
		3940
		3941	return true;
		3942	}
		3943
		3944	static bool g4x_compute_srwm(struct drm_device *dev,
		3945	int plane,
		3946	int latency_ns,
		3947	const struct intel_watermark_params *display,
		3948	const struct intel_watermark_params *cursor,
		3949	int display_wm, int cursor_wm)
		3950	{
		3951	struct drm_crtc *crtc;
		3952	int hdisplay, htotal, pixel_size, clock;
		3953	unsigned long line_time_us;
		3954	int line_count, line_size;
		3955	int small, large;
		3956	int entries;
		3957
		3958	if (!latency_ns) {
		3959	display_wm = cursor_wm = 0;
		3960	return false;
		3961	}
		3962
		3963	crtc = intel_get_crtc_for_plane(dev, plane);
		3964	hdisplay = crtc->mode.hdisplay;
		3965	htotal = crtc->mode.htotal;
		3966	clock = crtc->mode.clock;
		3967	pixel_size = crtc->fb->bits_per_pixel / 8;
		3968
		3969	line_time_us = (htotal * 1000) / clock;
		3970	line_count = (latency_ns / line_time_us + 1000) / 1000;
		3971	line_size = hdisplay * pixel_size;
		3972
		3973	/* Use the minimum of the small and large buffer method for primary */
		3974	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
		3975	large = line_count * line_size;
		3976
		3977	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
		3978	*display_wm = entries + display->guard_size;
		3979
		3980	/* calculate the self-refresh watermark for display cursor */
		3981	entries = line_count * pixel_size * 64;
		3982	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
		3983	*cursor_wm = entries + cursor->guard_size;
		3984
		3985	return g4x_check_srwm(dev,
		3986	display_wm, cursor_wm,
		3987	display, cursor);
		3988	}
		3989
		3990	#define single_plane_enabled(mask) is_power_of_2(mask)
		3991
		3992	static void g4x_update_wm(struct drm_device *dev)
		3993	{
		3994	static const int sr_latency_ns = 12000;
		3995	struct drm_i915_private *dev_priv = dev->dev_private;
		3996	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
		3997	int plane_sr, cursor_sr;
		3998	unsigned int enabled = 0;
		3999
		4000	if (g4x_compute_wm0(dev, 0,
		4001	&g4x_wm_info, latency_ns,
		4002	&g4x_cursor_wm_info, latency_ns,
		4003	&planea_wm, &cursora_wm))
		4004	enabled \|= 1;
		4005
		4006	if (g4x_compute_wm0(dev, 1,
		4007	&g4x_wm_info, latency_ns,
		4008	&g4x_cursor_wm_info, latency_ns,
		4009	&planeb_wm, &cursorb_wm))
		4010	enabled \|= 2;
		4011
		4012	plane_sr = cursor_sr = 0;
		4013	if (single_plane_enabled(enabled) &&
		4014	g4x_compute_srwm(dev, ffs(enabled) - 1,
		4015	sr_latency_ns,
		4016	&g4x_wm_info,
		4017	&g4x_cursor_wm_info,
		4018	&plane_sr, &cursor_sr))
		4019	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
		4020	else
		4021	I915_WRITE(FW_BLC_SELF,
		4022	I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
		4023
		4024	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
		4025	planea_wm, cursora_wm,
		4026	planeb_wm, cursorb_wm,
		4027	plane_sr, cursor_sr);
		4028
		4029	I915_WRITE(DSPFW1,
		4030	(plane_sr << DSPFW_SR_SHIFT) \|
		4031	(cursorb_wm << DSPFW_CURSORB_SHIFT) \|
		4032	(planeb_wm << DSPFW_PLANEB_SHIFT) \|
		4033	planea_wm);
		4034	I915_WRITE(DSPFW2,
		4035	(I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) \|
		4036	(cursora_wm << DSPFW_CURSORA_SHIFT));
		4037	/* HPLL off in SR has some issues on G4x... disable it */
		4038	I915_WRITE(DSPFW3,
		4039	(I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) \|
		4040	(cursor_sr << DSPFW_CURSOR_SR_SHIFT));
		4041	}
		4042
		4043	static void i965_update_wm(struct drm_device *dev)
		4044	{
		4045	struct drm_i915_private *dev_priv = dev->dev_private;
		4046	struct drm_crtc *crtc;
		4047	int srwm = 1;
		4048	int cursor_sr = 16;
		4049
		4050	/* Calc sr entries for one plane configs */
		4051	crtc = single_enabled_crtc(dev);
		4052	if (crtc) {
		4053	/* self-refresh has much higher latency */
		4054	static const int sr_latency_ns = 12000;
		4055	int clock = crtc->mode.clock;
		4056	int htotal = crtc->mode.htotal;
		4057	int hdisplay = crtc->mode.hdisplay;
		4058	int pixel_size = crtc->fb->bits_per_pixel / 8;
		4059	unsigned long line_time_us;
		4060	int entries;
		4061
		4062	line_time_us = ((htotal * 1000) / clock);
		4063
		4064	/* Use ns/us then divide to preserve precision */
		4065	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
		4066	pixel_size * hdisplay;
		4067	entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
		4068	srwm = I965_FIFO_SIZE - entries;
		4069	if (srwm < 0)
		4070	srwm = 1;
		4071	srwm &= 0x1ff;
		4072	DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
		4073	entries, srwm);
		4074
		4075	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
		4076	pixel_size * 64;
		4077	entries = DIV_ROUND_UP(entries,
		4078	i965_cursor_wm_info.cacheline_size);
		4079	cursor_sr = i965_cursor_wm_info.fifo_size -
		4080	(entries + i965_cursor_wm_info.guard_size);
		4081
		4082	if (cursor_sr > i965_cursor_wm_info.max_wm)
		4083	cursor_sr = i965_cursor_wm_info.max_wm;
		4084
		4085	DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
		4086	"cursor %d\n", srwm, cursor_sr);
		4087
		4088	if (IS_CRESTLINE(dev))
		4089	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
		4090	} else {
		4091	/* Turn off self refresh if both pipes are enabled */
		4092	if (IS_CRESTLINE(dev))
		4093	I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
		4094	& ~FW_BLC_SELF_EN);
		4095	}
		4096
		4097	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
		4098	srwm);
		4099
		4100	/* 965 has limitations... */
		4101	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) \|
		4102	(8 << 16) \| (8 << 8) \| (8 << 0));
		4103	I915_WRITE(DSPFW2, (8 << 8) \| (8 << 0));
		4104	/* update cursor SR watermark */
		4105	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
		4106	}
		4107
		4108	static void i9xx_update_wm(struct drm_device *dev)
		4109	{
		4110	struct drm_i915_private *dev_priv = dev->dev_private;
		4111	const struct intel_watermark_params *wm_info;
		4112	uint32_t fwater_lo;
		4113	uint32_t fwater_hi;
		4114	int cwm, srwm = 1;
		4115	int fifo_size;
		4116	int planea_wm, planeb_wm;
		4117	struct drm_crtc crtc, enabled = NULL;
		4118
		4119	if (IS_I945GM(dev))
		4120	wm_info = &i945_wm_info;
		4121	else if (!IS_GEN2(dev))
		4122	wm_info = &i915_wm_info;
		4123	else
		4124	wm_info = &i855_wm_info;
		4125
		4126	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
		4127	crtc = intel_get_crtc_for_plane(dev, 0);
		4128	if (crtc->enabled && crtc->fb) {
		4129	planea_wm = intel_calculate_wm(crtc->mode.clock,
		4130	wm_info, fifo_size,
		4131	crtc->fb->bits_per_pixel / 8,
		4132	latency_ns);
		4133	enabled = crtc;
		4134	} else
		4135	planea_wm = fifo_size - wm_info->guard_size;
		4136
		4137	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
		4138	crtc = intel_get_crtc_for_plane(dev, 1);
		4139	if (crtc->enabled && crtc->fb) {
		4140	planeb_wm = intel_calculate_wm(crtc->mode.clock,
		4141	wm_info, fifo_size,
		4142	crtc->fb->bits_per_pixel / 8,
		4143	latency_ns);
		4144	if (enabled == NULL)
		4145	enabled = crtc;
		4146	else
		4147	enabled = NULL;
		4148	} else
		4149	planeb_wm = fifo_size - wm_info->guard_size;
		4150
		4151	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
		4152
		4153	/*
		4154	* Overlay gets an aggressive default since video jitter is bad.
		4155	*/
		4156	cwm = 2;
		4157
		4158	/* Play safe and disable self-refresh before adjusting watermarks. */
		4159	if (IS_I945G(dev) \|\| IS_I945GM(dev))
		4160	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK \| 0);
		4161	else if (IS_I915GM(dev))
		4162	I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
		4163
		4164	/* Calc sr entries for one plane configs */
		4165	if (HAS_FW_BLC(dev) && enabled) {
		4166	/* self-refresh has much higher latency */
		4167	static const int sr_latency_ns = 6000;
		4168	int clock = enabled->mode.clock;
		4169	int htotal = enabled->mode.htotal;
		4170	int hdisplay = enabled->mode.hdisplay;
		4171	int pixel_size = enabled->fb->bits_per_pixel / 8;
		4172	unsigned long line_time_us;
		4173	int entries;
		4174
		4175	line_time_us = (htotal * 1000) / clock;
		4176
		4177	/* Use ns/us then divide to preserve precision */
		4178	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
		4179	pixel_size * hdisplay;
		4180	entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
		4181	DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
		4182	srwm = wm_info->fifo_size - entries;
		4183	if (srwm < 0)
		4184	srwm = 1;
		4185
		4186	if (IS_I945G(dev) \|\| IS_I945GM(dev))
		4187	I915_WRITE(FW_BLC_SELF,
		4188	FW_BLC_SELF_FIFO_MASK \| (srwm & 0xff));
		4189	else if (IS_I915GM(dev))
		4190	I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
		4191	}
		4192
		4193	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
		4194	planea_wm, planeb_wm, cwm, srwm);
		4195
		4196	fwater_lo = ((planeb_wm & 0x3f) << 16) \| (planea_wm & 0x3f);
		4197	fwater_hi = (cwm & 0x1f);
		4198
		4199	/* Set request length to 8 cachelines per fetch */
		4200	fwater_lo = fwater_lo \| (1 << 24) \| (1 << 8);
		4201	fwater_hi = fwater_hi \| (1 << 8);
		4202
		4203	I915_WRITE(FW_BLC, fwater_lo);
		4204	I915_WRITE(FW_BLC2, fwater_hi);
		4205
		4206	if (HAS_FW_BLC(dev)) {
		4207	if (enabled) {
		4208	if (IS_I945G(dev) \|\| IS_I945GM(dev))
		4209	I915_WRITE(FW_BLC_SELF,
		4210	FW_BLC_SELF_EN_MASK \| FW_BLC_SELF_EN);
		4211	else if (IS_I915GM(dev))
		4212	I915_WRITE(INSTPM, I915_READ(INSTPM) \| INSTPM_SELF_EN);
		4213	DRM_DEBUG_KMS("memory self refresh enabled\n");
		4214	} else
		4215	DRM_DEBUG_KMS("memory self refresh disabled\n");
		4216	}
		4217	}
		4218
		4219	static void i830_update_wm(struct drm_device *dev)
		4220	{
		4221	struct drm_i915_private *dev_priv = dev->dev_private;
		4222	struct drm_crtc *crtc;
		4223	uint32_t fwater_lo;
		4224	int planea_wm;
		4225
		4226	crtc = single_enabled_crtc(dev);
		4227	if (crtc == NULL)
		4228	return;
		4229
		4230	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
		4231	dev_priv->display.get_fifo_size(dev, 0),
		4232	crtc->fb->bits_per_pixel / 8,
		4233	latency_ns);
		4234	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
		4235	fwater_lo \|= (3<<8) \| planea_wm;
		4236
		4237	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
		4238
		4239	I915_WRITE(FW_BLC, fwater_lo);
		4240	}
		4241
		4242	#define ILK_LP0_PLANE_LATENCY 700
		4243	#define ILK_LP0_CURSOR_LATENCY 1300
		4244
		4245	/*
		4246	* Check the wm result.
		4247	*
		4248	* If any calculated watermark values is larger than the maximum value that
		4249	* can be programmed into the associated watermark register, that watermark
		4250	* must be disabled.
		4251	*/
		4252	static bool ironlake_check_srwm(struct drm_device *dev, int level,
		4253	int fbc_wm, int display_wm, int cursor_wm,
		4254	const struct intel_watermark_params *display,
		4255	const struct intel_watermark_params *cursor)
		4256	{
		4257	struct drm_i915_private *dev_priv = dev->dev_private;
		4258
		4259	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
		4260	" cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
		4261
		4262	if (fbc_wm > SNB_FBC_MAX_SRWM) {
		4263	DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
		4264	fbc_wm, SNB_FBC_MAX_SRWM, level);
		4265
		4266	/* fbc has it's own way to disable FBC WM */
		4267	I915_WRITE(DISP_ARB_CTL,
		4268	I915_READ(DISP_ARB_CTL) \| DISP_FBC_WM_DIS);
		4269	return false;
		4270	}
		4271
		4272	if (display_wm > display->max_wm) {
		4273	DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
		4274	display_wm, SNB_DISPLAY_MAX_SRWM, level);
		4275	return false;
		4276	}
		4277
		4278	if (cursor_wm > cursor->max_wm) {
		4279	DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
		4280	cursor_wm, SNB_CURSOR_MAX_SRWM, level);
		4281	return false;
		4282	}
		4283
		4284	if (!(fbc_wm \|\| display_wm \|\| cursor_wm)) {
		4285	DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
		4286	return false;
		4287	}
		4288
		4289	return true;
		4290	}
		4291
		4292	/*
		4293	* Compute watermark values of WM[1-3],
		4294	*/
		4295	static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
		4296	int latency_ns,
		4297	const struct intel_watermark_params *display,
		4298	const struct intel_watermark_params *cursor,
		4299	int fbc_wm, int display_wm, int *cursor_wm)
		4300	{
		4301	struct drm_crtc *crtc;
		4302	unsigned long line_time_us;
		4303	int hdisplay, htotal, pixel_size, clock;
		4304	int line_count, line_size;
		4305	int small, large;
		4306	int entries;
		4307
		4308	if (!latency_ns) {
		4309	fbc_wm = display_wm = *cursor_wm = 0;
		4310	return false;
		4311	}
		4312
		4313	crtc = intel_get_crtc_for_plane(dev, plane);
		4314	hdisplay = crtc->mode.hdisplay;
		4315	htotal = crtc->mode.htotal;
		4316	clock = crtc->mode.clock;
		4317	pixel_size = crtc->fb->bits_per_pixel / 8;
		4318
		4319	line_time_us = (htotal * 1000) / clock;
		4320	line_count = (latency_ns / line_time_us + 1000) / 1000;
		4321	line_size = hdisplay * pixel_size;
		4322
		4323	/* Use the minimum of the small and large buffer method for primary */
		4324	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
		4325	large = line_count * line_size;
		4326
		4327	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
		4328	*display_wm = entries + display->guard_size;
		4329
		4330	/*
		4331	* Spec says:
		4332	* FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
		4333	*/
		4334	fbc_wm = DIV_ROUND_UP(display_wm * 64, line_size) + 2;
		4335
		4336	/* calculate the self-refresh watermark for display cursor */
		4337	entries = line_count * pixel_size * 64;
		4338	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
		4339	*cursor_wm = entries + cursor->guard_size;
		4340
		4341	return ironlake_check_srwm(dev, level,
		4342	fbc_wm, display_wm, *cursor_wm,
		4343	display, cursor);
		4344	}
		4345
		4346	static void ironlake_update_wm(struct drm_device *dev)
		4347	{
		4348	struct drm_i915_private *dev_priv = dev->dev_private;
		4349	int fbc_wm, plane_wm, cursor_wm;
		4350	unsigned int enabled;
		4351
		4352	enabled = 0;
		4353	if (g4x_compute_wm0(dev, 0,
		4354	&ironlake_display_wm_info,
		4355	ILK_LP0_PLANE_LATENCY,
		4356	&ironlake_cursor_wm_info,
		4357	ILK_LP0_CURSOR_LATENCY,
		4358	&plane_wm, &cursor_wm)) {
		4359	I915_WRITE(WM0_PIPEA_ILK,
		4360	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
		4361	DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
		4362	" plane %d, " "cursor: %d\n",
		4363	plane_wm, cursor_wm);
		4364	enabled \|= 1;
		4365	}
		4366
		4367	if (g4x_compute_wm0(dev, 1,
		4368	&ironlake_display_wm_info,
		4369	ILK_LP0_PLANE_LATENCY,
		4370	&ironlake_cursor_wm_info,
		4371	ILK_LP0_CURSOR_LATENCY,
		4372	&plane_wm, &cursor_wm)) {
		4373	I915_WRITE(WM0_PIPEB_ILK,
		4374	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
		4375	DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
		4376	" plane %d, cursor: %d\n",
		4377	plane_wm, cursor_wm);
		4378	enabled \|= 2;
		4379	}
		4380
		4381	/*
		4382	* Calculate and update the self-refresh watermark only when one
		4383	* display plane is used.
		4384	*/
		4385	I915_WRITE(WM3_LP_ILK, 0);
		4386	I915_WRITE(WM2_LP_ILK, 0);
		4387	I915_WRITE(WM1_LP_ILK, 0);
		4388
		4389	if (!single_plane_enabled(enabled))
		4390	return;
		4391	enabled = ffs(enabled) - 1;
		4392
		4393	/* WM1 */
		4394	if (!ironlake_compute_srwm(dev, 1, enabled,
		4395	ILK_READ_WM1_LATENCY() * 500,
		4396	&ironlake_display_srwm_info,
		4397	&ironlake_cursor_srwm_info,
		4398	&fbc_wm, &plane_wm, &cursor_wm))
		4399	return;
		4400
		4401	I915_WRITE(WM1_LP_ILK,
		4402	WM1_LP_SR_EN \|
		4403	(ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4404	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4405	(plane_wm << WM1_LP_SR_SHIFT) \|
		4406	cursor_wm);
		4407
		4408	/* WM2 */
		4409	if (!ironlake_compute_srwm(dev, 2, enabled,
		4410	ILK_READ_WM2_LATENCY() * 500,
		4411	&ironlake_display_srwm_info,
		4412	&ironlake_cursor_srwm_info,
		4413	&fbc_wm, &plane_wm, &cursor_wm))
		4414	return;
		4415
		4416	I915_WRITE(WM2_LP_ILK,
		4417	WM2_LP_EN \|
		4418	(ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4419	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4420	(plane_wm << WM1_LP_SR_SHIFT) \|
		4421	cursor_wm);
		4422
		4423	/*
		4424	* WM3 is unsupported on ILK, probably because we don't have latency
		4425	* data for that power state
		4426	*/
		4427	}
		4428
		4429	static void sandybridge_update_wm(struct drm_device *dev)
		4430	{
		4431	struct drm_i915_private *dev_priv = dev->dev_private;
		4432	int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
		4433	int fbc_wm, plane_wm, cursor_wm;
		4434	unsigned int enabled;
		4435
		4436	enabled = 0;
		4437	if (g4x_compute_wm0(dev, 0,
		4438	&sandybridge_display_wm_info, latency,
		4439	&sandybridge_cursor_wm_info, latency,
		4440	&plane_wm, &cursor_wm)) {
		4441	I915_WRITE(WM0_PIPEA_ILK,
		4442	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
		4443	DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
		4444	" plane %d, " "cursor: %d\n",
		4445	plane_wm, cursor_wm);
		4446	enabled \|= 1;
		4447	}
		4448
		4449	if (g4x_compute_wm0(dev, 1,
		4450	&sandybridge_display_wm_info, latency,
		4451	&sandybridge_cursor_wm_info, latency,
		4452	&plane_wm, &cursor_wm)) {
		4453	I915_WRITE(WM0_PIPEB_ILK,
		4454	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
		4455	DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
		4456	" plane %d, cursor: %d\n",
		4457	plane_wm, cursor_wm);
		4458	enabled \|= 2;
		4459	}
		4460
		4461	/*
		4462	* Calculate and update the self-refresh watermark only when one
		4463	* display plane is used.
		4464	*
		4465	* SNB support 3 levels of watermark.
		4466	*
		4467	* WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
		4468	* and disabled in the descending order
		4469	*
		4470	*/
		4471	I915_WRITE(WM3_LP_ILK, 0);
		4472	I915_WRITE(WM2_LP_ILK, 0);
		4473	I915_WRITE(WM1_LP_ILK, 0);
		4474
		4475	if (!single_plane_enabled(enabled))
		4476	return;
		4477	enabled = ffs(enabled) - 1;
		4478
		4479	/* WM1 */
		4480	if (!ironlake_compute_srwm(dev, 1, enabled,
		4481	SNB_READ_WM1_LATENCY() * 500,
		4482	&sandybridge_display_srwm_info,
		4483	&sandybridge_cursor_srwm_info,
		4484	&fbc_wm, &plane_wm, &cursor_wm))
		4485	return;
		4486
		4487	I915_WRITE(WM1_LP_ILK,
		4488	WM1_LP_SR_EN \|
		4489	(SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4490	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4491	(plane_wm << WM1_LP_SR_SHIFT) \|
		4492	cursor_wm);
		4493
		4494	/* WM2 */
		4495	if (!ironlake_compute_srwm(dev, 2, enabled,
		4496	SNB_READ_WM2_LATENCY() * 500,
		4497	&sandybridge_display_srwm_info,
		4498	&sandybridge_cursor_srwm_info,
		4499	&fbc_wm, &plane_wm, &cursor_wm))
		4500	return;
		4501
		4502	I915_WRITE(WM2_LP_ILK,
		4503	WM2_LP_EN \|
		4504	(SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4505	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4506	(plane_wm << WM1_LP_SR_SHIFT) \|
		4507	cursor_wm);
		4508
		4509	/* WM3 */
		4510	if (!ironlake_compute_srwm(dev, 3, enabled,
		4511	SNB_READ_WM3_LATENCY() * 500,
		4512	&sandybridge_display_srwm_info,
		4513	&sandybridge_cursor_srwm_info,
		4514	&fbc_wm, &plane_wm, &cursor_wm))
		4515	return;
		4516
		4517	I915_WRITE(WM3_LP_ILK,
		4518	WM3_LP_EN \|
		4519	(SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4520	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4521	(plane_wm << WM1_LP_SR_SHIFT) \|
		4522	cursor_wm);
		4523	}
		4524
		4525	/**
		4526	* intel_update_watermarks - update FIFO watermark values based on current modes
		4527	*
		4528	* Calculate watermark values for the various WM regs based on current mode
		4529	* and plane configuration.
		4530	*
		4531	* There are several cases to deal with here:
		4532	* - normal (i.e. non-self-refresh)
		4533	* - self-refresh (SR) mode
		4534	* - lines are large relative to FIFO size (buffer can hold up to 2)
		4535	* - lines are small relative to FIFO size (buffer can hold more than 2
		4536	* lines), so need to account for TLB latency
		4537	*
		4538	* The normal calculation is:
		4539	* watermark = dotclock * bytes per pixel * latency
		4540	* where latency is platform & configuration dependent (we assume pessimal
		4541	* values here).
		4542	*
		4543	* The SR calculation is:
		4544	* watermark = (trunc(latency/line time)+1) * surface width *
		4545	* bytes per pixel
		4546	* where
		4547	* line time = htotal / dotclock
		4548	* surface width = hdisplay for normal plane and 64 for cursor
		4549	* and latency is assumed to be high, as above.
		4550	*
		4551	* The final value programmed to the register should always be rounded up,
		4552	* and include an extra 2 entries to account for clock crossings.
		4553	*
		4554	* We don't use the sprite, so we can ignore that. And on Crestline we have
		4555	* to set the non-SR watermarks to 8.
		4556	*/
		4557	static void intel_update_watermarks(struct drm_device *dev)
		4558	{
		4559	struct drm_i915_private *dev_priv = dev->dev_private;
		4560
		4561	if (dev_priv->display.update_wm)
		4562	dev_priv->display.update_wm(dev);
		4563	}
		4564
		4565	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		4566	{
		4567	return dev_priv->lvds_use_ssc && i915_panel_use_ssc
		4568	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		4569	}
		4570
		4571	/**
		4572	* intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
		4573	* @crtc: CRTC structure
		4574	*
		4575	* A pipe may be connected to one or more outputs. Based on the depth of the
		4576	* attached framebuffer, choose a good color depth to use on the pipe.
		4577	*
		4578	* If possible, match the pipe depth to the fb depth. In some cases, this
		4579	* isn't ideal, because the connected output supports a lesser or restricted
		4580	* set of depths. Resolve that here:
		4581	* LVDS typically supports only 6bpc, so clamp down in that case
		4582	* HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
		4583	* Displays may support a restricted set as well, check EDID and clamp as
		4584	* appropriate.
		4585	*
		4586	* RETURNS:
		4587	* Dithering requirement (i.e. false if display bpc and pipe bpc match,
		4588	* true if they don't match).
		4589	*/
		4590	static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
		4591	unsigned int *pipe_bpp)
		4592	{
		4593	struct drm_device *dev = crtc->dev;
		4594	struct drm_i915_private *dev_priv = dev->dev_private;
		4595	struct drm_encoder *encoder;
		4596	struct drm_connector *connector;
		4597	unsigned int display_bpc = UINT_MAX, bpc;
		4598
		4599	/* Walk the encoders & connectors on this crtc, get min bpc */
		4600	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		4601	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		4602
		4603	if (encoder->crtc != crtc)
		4604	continue;
		4605
		4606	if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
		4607	unsigned int lvds_bpc;
		4608
		4609	if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
		4610	LVDS_A3_POWER_UP)
		4611	lvds_bpc = 8;
		4612	else
		4613	lvds_bpc = 6;
		4614
		4615	if (lvds_bpc < display_bpc) {
		4616	DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
		4617	display_bpc = lvds_bpc;
		4618	}
		4619	continue;
		4620	}
		4621
		4622	if (intel_encoder->type == INTEL_OUTPUT_EDP) {
		4623	/* Use VBT settings if we have an eDP panel */
		4624	unsigned int edp_bpc = dev_priv->edp.bpp / 3;
		4625
		4626	if (edp_bpc < display_bpc) {
		4627	DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
		4628	display_bpc = edp_bpc;
		4629	}
		4630	continue;
		4631	}
		4632
		4633	/* Not one of the known troublemakers, check the EDID */
		4634	list_for_each_entry(connector, &dev->mode_config.connector_list,
		4635	head) {
		4636	if (connector->encoder != encoder)
		4637	continue;
		4638
		4639	/* Don't use an invalid EDID bpc value */
		4640	if (connector->display_info.bpc &&
		4641	connector->display_info.bpc < display_bpc) {
		4642	DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
		4643	display_bpc = connector->display_info.bpc;
		4644	}
		4645	}
		4646
		4647	/*
		4648	* HDMI is either 12 or 8, so if the display lets 10bpc sneak
		4649	* through, clamp it down. (Note: >12bpc will be caught below.)
		4650	*/
		4651	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		4652	if (display_bpc > 8 && display_bpc < 12) {
		4653	DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
		4654	display_bpc = 12;
		4655	} else {
		4656	DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
		4657	display_bpc = 8;
		4658	}
		4659	}
		4660	}
		4661
		4662	/*
		4663	* We could just drive the pipe at the highest bpc all the time and
		4664	* enable dithering as needed, but that costs bandwidth. So choose
		4665	* the minimum value that expresses the full color range of the fb but
		4666	* also stays within the max display bpc discovered above.
		4667	*/
		4668
		4669	switch (crtc->fb->depth) {
		4670	case 8:
		4671	bpc = 8; /* since we go through a colormap */
		4672	break;
		4673	case 15:
		4674	case 16:
		4675	bpc = 6; /* min is 18bpp */
		4676	break;
		4677	case 24:
		4678	bpc = min((unsigned int)8, display_bpc);
		4679	break;
		4680	case 30:
		4681	bpc = min((unsigned int)10, display_bpc);
		4682	break;
		4683	case 48:
		4684	bpc = min((unsigned int)12, display_bpc);
		4685	break;
		4686	default:
		4687	DRM_DEBUG("unsupported depth, assuming 24 bits\n");
		4688	bpc = min((unsigned int)8, display_bpc);
		4689	break;
		4690	}
		4691
		4692	DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
		4693	bpc, display_bpc);
		4694
		4695	pipe_bpp = bpc 3;
		4696
		4697	return display_bpc != bpc;
		4698	}
		4699
		4700	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4701	struct drm_display_mode *mode,
		4702	struct drm_display_mode *adjusted_mode,
		4703	int x, int y,
		4704	struct drm_framebuffer *old_fb)
		4705	{
		4706	struct drm_device *dev = crtc->dev;
		4707	struct drm_i915_private *dev_priv = dev->dev_private;
		4708	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4709	int pipe = intel_crtc->pipe;
		4710	int plane = intel_crtc->plane;
		4711	int refclk, num_connectors = 0;
		4712	intel_clock_t clock, reduced_clock;
		4713	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
		4714	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
		4715	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
		4716	struct drm_mode_config *mode_config = &dev->mode_config;
		4717	struct intel_encoder *encoder;
		4718	const intel_limit_t *limit;
		4719	int ret;
		4720	u32 temp;
		4721	u32 lvds_sync = 0;
		4722
		4723	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		4724	if (encoder->base.crtc != crtc)
		4725	continue;
		4726
		4727	switch (encoder->type) {
		4728	case INTEL_OUTPUT_LVDS:
		4729	is_lvds = true;
		4730	break;
		4731	case INTEL_OUTPUT_SDVO:
		4732	case INTEL_OUTPUT_HDMI:
		4733	is_sdvo = true;
		4734	if (encoder->needs_tv_clock)
		4735	is_tv = true;
		4736	break;
		4737	case INTEL_OUTPUT_DVO:
		4738	is_dvo = true;
		4739	break;
		4740	case INTEL_OUTPUT_TVOUT:
		4741	is_tv = true;
		4742	break;
		4743	case INTEL_OUTPUT_ANALOG:
		4744	is_crt = true;
		4745	break;
		4746	case INTEL_OUTPUT_DISPLAYPORT:
		4747	is_dp = true;
		4748	break;
		4749	}
		4750
		4751	num_connectors++;
		4752	}
		4753
		4754	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		4755	refclk = dev_priv->lvds_ssc_freq * 1000;
		4756	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4757	refclk / 1000);
		4758	} else if (!IS_GEN2(dev)) {
		4759	refclk = 96000;
		4760	} else {
		4761	refclk = 48000;
		4762	}
		4763
		4764	/*
		4765	* Returns a set of divisors for the desired target clock with the given
		4766	* refclk, or FALSE. The returned values represent the clock equation:
		4767	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4768	*/
		4769	limit = intel_limit(crtc, refclk);
		4770	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
		4771	if (!ok) {
		4772	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4773	return -EINVAL;
		4774	}
		4775
		4776	/* Ensure that the cursor is valid for the new mode before changing... */
		4777	// intel_crtc_update_cursor(crtc, true);
		4778
		4779	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4780	has_reduced_clock = limit->find_pll(limit, crtc,
		4781	dev_priv->lvds_downclock,
		4782	refclk,
		4783	&reduced_clock);
		4784	if (has_reduced_clock && (clock.p != reduced_clock.p)) {
		4785	/*
		4786	* If the different P is found, it means that we can't
		4787	* switch the display clock by using the FP0/FP1.
		4788	* In such case we will disable the LVDS downclock
		4789	* feature.
		4790	*/
		4791	DRM_DEBUG_KMS("Different P is found for "
		4792	"LVDS clock/downclock\n");
		4793	has_reduced_clock = 0;
		4794	}
		4795	}
		4796	/* SDVO TV has fixed PLL values depend on its clock range,
		4797	this mirrors vbios setting. */
		4798	if (is_sdvo && is_tv) {
		4799	if (adjusted_mode->clock >= 100000
		4800	&& adjusted_mode->clock < 140500) {
		4801	clock.p1 = 2;
		4802	clock.p2 = 10;
		4803	clock.n = 3;
		4804	clock.m1 = 16;
		4805	clock.m2 = 8;
		4806	} else if (adjusted_mode->clock >= 140500
		4807	&& adjusted_mode->clock <= 200000) {
		4808	clock.p1 = 1;
		4809	clock.p2 = 10;
		4810	clock.n = 6;
		4811	clock.m1 = 12;
		4812	clock.m2 = 8;
		4813	}
		4814	}
		4815
		4816	if (IS_PINEVIEW(dev)) {
		4817	fp = (1 << clock.n) << 16 \| clock.m1 << 8 \| clock.m2;
		4818	if (has_reduced_clock)
		4819	fp2 = (1 << reduced_clock.n) << 16 \|
		4820	reduced_clock.m1 << 8 \| reduced_clock.m2;
		4821	} else {
		4822	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;
		4823	if (has_reduced_clock)
		4824	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|
		4825	reduced_clock.m2;
		4826	}
		4827
		4828	dpll = DPLL_VGA_MODE_DIS;
		4829
		4830	if (!IS_GEN2(dev)) {
		4831	if (is_lvds)
		4832	dpll \|= DPLLB_MODE_LVDS;
		4833	else
		4834	dpll \|= DPLLB_MODE_DAC_SERIAL;
		4835	if (is_sdvo) {
		4836	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		4837	if (pixel_multiplier > 1) {
		4838	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev))
		4839	dpll \|= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
		4840	}
		4841	dpll \|= DPLL_DVO_HIGH_SPEED;
		4842	}
		4843	if (is_dp)
		4844	dpll \|= DPLL_DVO_HIGH_SPEED;
		4845
		4846	/* compute bitmask from p1 value */
		4847	if (IS_PINEVIEW(dev))
		4848	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4849	else {
		4850	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4851	if (IS_G4X(dev) && has_reduced_clock)
		4852	dpll \|= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4853	}
		4854	switch (clock.p2) {
		4855	case 5:
		4856	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4857	break;
		4858	case 7:
		4859	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4860	break;
		4861	case 10:
		4862	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4863	break;
		4864	case 14:
		4865	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4866	break;
		4867	}
		4868	if (INTEL_INFO(dev)->gen >= 4)
		4869	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
		4870	} else {
		4871	if (is_lvds) {
		4872	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4873	} else {
		4874	if (clock.p1 == 2)
		4875	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4876	else
		4877	dpll \|= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4878	if (clock.p2 == 4)
		4879	dpll \|= PLL_P2_DIVIDE_BY_4;
		4880	}
		4881	}
		4882
		4883	if (is_sdvo && is_tv)
		4884	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		4885	else if (is_tv)
		4886	/* XXX: just matching BIOS for now */
		4887	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4888	dpll \|= 3;
		4889	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4890	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4891	else
		4892	dpll \|= PLL_REF_INPUT_DREFCLK;
		4893
		4894	/* setup pipeconf */
		4895	pipeconf = I915_READ(PIPECONF(pipe));
		4896
		4897	/* Set up the display plane register */
		4898	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4899
		4900	/* Ironlake's plane is forced to pipe, bit 24 is to
		4901	enable color space conversion */
		4902	if (pipe == 0)
		4903	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4904	else
		4905	dspcntr \|= DISPPLANE_SEL_PIPE_B;
		4906
		4907	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4908	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4909	* core speed.
		4910	*
		4911	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4912	* pipe == 0 check?
		4913	*/
		4914	if (mode->clock >
		4915	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4916	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4917	else
		4918	pipeconf &= ~PIPECONF_DOUBLE_WIDE;
		4919	}
		4920
		4921	dpll \|= DPLL_VCO_ENABLE;
		4922
		4923	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
		4924	drm_mode_debug_printmodeline(mode);
		4925
		4926	I915_WRITE(FP0(pipe), fp);
		4927	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		4928
		4929	POSTING_READ(DPLL(pipe));
		4930	udelay(150);
		4931
		4932	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		4933	* This is an exception to the general rule that mode_set doesn't turn
		4934	* things on.
		4935	*/
		4936	if (is_lvds) {
		4937	temp = I915_READ(LVDS);
		4938	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
		4939	if (pipe == 1) {
		4940	temp \|= LVDS_PIPEB_SELECT;
		4941	} else {
		4942	temp &= ~LVDS_PIPEB_SELECT;
		4943	}
		4944	/* set the corresponsding LVDS_BORDER bit */
		4945	temp \|= dev_priv->lvds_border_bits;
		4946	/* Set the B0-B3 data pairs corresponding to whether we're going to
		4947	* set the DPLLs for dual-channel mode or not.
		4948	*/
		4949	if (clock.p2 == 7)
		4950	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
		4951	else
		4952	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
		4953
		4954	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		4955	* appropriately here, but we need to look more thoroughly into how
		4956	* panels behave in the two modes.
		4957	*/
		4958	/* set the dithering flag on LVDS as needed */
		4959	if (INTEL_INFO(dev)->gen >= 4) {
		4960	if (dev_priv->lvds_dither)
		4961	temp \|= LVDS_ENABLE_DITHER;
		4962	else
		4963	temp &= ~LVDS_ENABLE_DITHER;
		4964	}
		4965	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
		4966	lvds_sync \|= LVDS_HSYNC_POLARITY;
		4967	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
		4968	lvds_sync \|= LVDS_VSYNC_POLARITY;
		4969	if ((temp & (LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY))
		4970	!= lvds_sync) {
		4971	char flags[2] = "-+";
		4972	DRM_INFO("Changing LVDS panel from "
		4973	"(%chsync, %cvsync) to (%chsync, %cvsync)\n",
		4974	flags[!(temp & LVDS_HSYNC_POLARITY)],
		4975	flags[!(temp & LVDS_VSYNC_POLARITY)],
		4976	flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
		4977	flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
		4978	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
		4979	temp \|= lvds_sync;
		4980	}
		4981	I915_WRITE(LVDS, temp);
		4982	}
		4983
		4984	if (is_dp) {
		4985	intel_dp_set_m_n(crtc, mode, adjusted_mode);
		4986	}
		4987
		4988	I915_WRITE(DPLL(pipe), dpll);
		4989
		4990	/* Wait for the clocks to stabilize. */
		4991	POSTING_READ(DPLL(pipe));
		4992	udelay(150);
		4993
		4994	if (INTEL_INFO(dev)->gen >= 4) {
		4995	temp = 0;
		4996	if (is_sdvo) {
		4997	temp = intel_mode_get_pixel_multiplier(adjusted_mode);
		4998	if (temp > 1)
		4999	temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		5000	else
		5001	temp = 0;
		5002	}
		5003	I915_WRITE(DPLL_MD(pipe), temp);
		5004	} else {
		5005	/* The pixel multiplier can only be updated once the
		5006	* DPLL is enabled and the clocks are stable.
		5007	*
		5008	* So write it again.
		5009	*/
		5010	I915_WRITE(DPLL(pipe), dpll);
		5011	}
		5012
		5013	intel_crtc->lowfreq_avail = false;
		5014	if (is_lvds && has_reduced_clock && i915_powersave) {
		5015	I915_WRITE(FP1(pipe), fp2);
		5016	intel_crtc->lowfreq_avail = true;
		5017	if (HAS_PIPE_CXSR(dev)) {
		5018	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		5019	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		5020	}
		5021	} else {
		5022	I915_WRITE(FP1(pipe), fp);
		5023	if (HAS_PIPE_CXSR(dev)) {
		5024	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		5025	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		5026	}
		5027	}
		5028
		5029	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		5030	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		5031	/* the chip adds 2 halflines automatically */
		5032	adjusted_mode->crtc_vdisplay -= 1;
		5033	adjusted_mode->crtc_vtotal -= 1;
		5034	adjusted_mode->crtc_vblank_start -= 1;
		5035	adjusted_mode->crtc_vblank_end -= 1;
		5036	adjusted_mode->crtc_vsync_end -= 1;
		5037	adjusted_mode->crtc_vsync_start -= 1;
		5038	} else
		5039	pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
		5040
		5041	I915_WRITE(HTOTAL(pipe),
		5042	(adjusted_mode->crtc_hdisplay - 1) \|
		5043	((adjusted_mode->crtc_htotal - 1) << 16));
		5044	I915_WRITE(HBLANK(pipe),
		5045	(adjusted_mode->crtc_hblank_start - 1) \|
		5046	((adjusted_mode->crtc_hblank_end - 1) << 16));
		5047	I915_WRITE(HSYNC(pipe),
		5048	(adjusted_mode->crtc_hsync_start - 1) \|
		5049	((adjusted_mode->crtc_hsync_end - 1) << 16));
		5050
		5051	I915_WRITE(VTOTAL(pipe),
		5052	(adjusted_mode->crtc_vdisplay - 1) \|
		5053	((adjusted_mode->crtc_vtotal - 1) << 16));
		5054	I915_WRITE(VBLANK(pipe),
		5055	(adjusted_mode->crtc_vblank_start - 1) \|
		5056	((adjusted_mode->crtc_vblank_end - 1) << 16));
		5057	I915_WRITE(VSYNC(pipe),
		5058	(adjusted_mode->crtc_vsync_start - 1) \|
		5059	((adjusted_mode->crtc_vsync_end - 1) << 16));
		5060
		5061	/* pipesrc and dspsize control the size that is scaled from,
		5062	* which should always be the user's requested size.
		5063	*/
		5064	I915_WRITE(DSPSIZE(plane),
		5065	((mode->vdisplay - 1) << 16) \|
		5066	(mode->hdisplay - 1));
		5067	I915_WRITE(DSPPOS(plane), 0);
		5068	I915_WRITE(PIPESRC(pipe),
		5069	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		5070
		5071	I915_WRITE(PIPECONF(pipe), pipeconf);
		5072	POSTING_READ(PIPECONF(pipe));
		5073	intel_enable_pipe(dev_priv, pipe, false);
		5074
		5075	intel_wait_for_vblank(dev, pipe);
		5076
		5077	I915_WRITE(DSPCNTR(plane), dspcntr);
		5078	POSTING_READ(DSPCNTR(plane));
		5079	intel_enable_plane(dev_priv, plane, pipe);
		5080
		5081	ret = intel_pipe_set_base(crtc, x, y, old_fb);
		5082
		5083	intel_update_watermarks(dev);
		5084
		5085	return ret;
		5086	}
		5087
		5088	static void ironlake_update_pch_refclk(struct drm_device *dev)
		5089	{
		5090	struct drm_i915_private *dev_priv = dev->dev_private;
		5091	struct drm_mode_config *mode_config = &dev->mode_config;
		5092	struct drm_crtc *crtc;
		5093	struct intel_encoder *encoder;
		5094	struct intel_encoder *has_edp_encoder = NULL;
		5095	u32 temp;
		5096	bool has_lvds = false;
		5097
		5098	/* We need to take the global config into account */
		5099	list_for_each_entry(crtc, &mode_config->crtc_list, head) {
		5100	if (!crtc->enabled)
		5101	continue;
		5102
		5103	list_for_each_entry(encoder, &mode_config->encoder_list,
		5104	base.head) {
		5105	if (encoder->base.crtc != crtc)
		5106	continue;
		5107
		5108	switch (encoder->type) {
		5109	case INTEL_OUTPUT_LVDS:
		5110	has_lvds = true;
		5111	case INTEL_OUTPUT_EDP:
		5112	has_edp_encoder = encoder;
		5113	break;
		5114	}
		5115	}
		5116	}
		5117
		5118	/* Ironlake: try to setup display ref clock before DPLL
		5119	* enabling. This is only under driver's control after
		5120	* PCH B stepping, previous chipset stepping should be
		5121	* ignoring this setting.
		5122	*/
		5123	temp = I915_READ(PCH_DREF_CONTROL);
		5124	/* Always enable nonspread source */
		5125	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
		5126	temp \|= DREF_NONSPREAD_SOURCE_ENABLE;
		5127	temp &= ~DREF_SSC_SOURCE_MASK;
		5128	temp \|= DREF_SSC_SOURCE_ENABLE;
		5129	I915_WRITE(PCH_DREF_CONTROL, temp);
		5130
		5131	POSTING_READ(PCH_DREF_CONTROL);
		5132	udelay(200);
		5133
		5134	if (has_edp_encoder) {
		5135	if (intel_panel_use_ssc(dev_priv)) {
		5136	temp \|= DREF_SSC1_ENABLE;
		5137	I915_WRITE(PCH_DREF_CONTROL, temp);
		5138
		5139	POSTING_READ(PCH_DREF_CONTROL);
		5140	udelay(200);
		5141	}
		5142	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		5143
		5144	/* Enable CPU source on CPU attached eDP */
		5145	if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5146	if (intel_panel_use_ssc(dev_priv))
		5147	temp \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		5148	else
		5149	temp \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		5150	} else {
		5151	/* Enable SSC on PCH eDP if needed */
		5152	if (intel_panel_use_ssc(dev_priv)) {
		5153	DRM_ERROR("enabling SSC on PCH\n");
		5154	temp \|= DREF_SUPERSPREAD_SOURCE_ENABLE;
		5155	}
		5156	}
		5157	I915_WRITE(PCH_DREF_CONTROL, temp);
		5158	POSTING_READ(PCH_DREF_CONTROL);
		5159	udelay(200);
		5160	}
		5161	}
		5162
		5163	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		5164	struct drm_display_mode *mode,
		5165	struct drm_display_mode *adjusted_mode,
		5166	int x, int y,
		5167	struct drm_framebuffer *old_fb)
		5168	{
		5169	struct drm_device *dev = crtc->dev;
		5170	struct drm_i915_private *dev_priv = dev->dev_private;
		5171	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5172	int pipe = intel_crtc->pipe;
		5173	int plane = intel_crtc->plane;
		5174	int refclk, num_connectors = 0;
		5175	intel_clock_t clock, reduced_clock;
		5176	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
		5177	bool ok, has_reduced_clock = false, is_sdvo = false;
		5178	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
		5179	struct intel_encoder *has_edp_encoder = NULL;
		5180	struct drm_mode_config *mode_config = &dev->mode_config;
		5181	struct intel_encoder *encoder;
		5182	const intel_limit_t *limit;
		5183	int ret;
		5184	struct fdi_m_n m_n = {0};
		5185	u32 temp;
		5186	u32 lvds_sync = 0;
		5187	int target_clock, pixel_multiplier, lane, link_bw, factor;
		5188	unsigned int pipe_bpp;
		5189	bool dither;
		5190
		5191	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		5192	if (encoder->base.crtc != crtc)
		5193	continue;
		5194
		5195	switch (encoder->type) {
		5196	case INTEL_OUTPUT_LVDS:
		5197	is_lvds = true;
		5198	break;
		5199	case INTEL_OUTPUT_SDVO:
		5200	case INTEL_OUTPUT_HDMI:
		5201	is_sdvo = true;
		5202	if (encoder->needs_tv_clock)
		5203	is_tv = true;
		5204	break;
		5205	case INTEL_OUTPUT_TVOUT:
		5206	is_tv = true;
		5207	break;
		5208	case INTEL_OUTPUT_ANALOG:
		5209	is_crt = true;
		5210	break;
		5211	case INTEL_OUTPUT_DISPLAYPORT:
		5212	is_dp = true;
		5213	break;
		5214	case INTEL_OUTPUT_EDP:
		5215	has_edp_encoder = encoder;
		5216	break;
		5217	}
		5218
		5219	num_connectors++;
		5220	}
		5221
		5222	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		5223	refclk = dev_priv->lvds_ssc_freq * 1000;
		5224	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		5225	refclk / 1000);
		5226	} else {
		5227	refclk = 96000;
		5228	if (!has_edp_encoder \|\|
		5229	intel_encoder_is_pch_edp(&has_edp_encoder->base))
		5230	refclk = 120000; /* 120Mhz refclk */
		5231	}
		5232
		5233	/*
		5234	* Returns a set of divisors for the desired target clock with the given
		5235	* refclk, or FALSE. The returned values represent the clock equation:
		5236	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		5237	*/
		5238	limit = intel_limit(crtc, refclk);
		5239	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
		5240	if (!ok) {
		5241	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		5242	return -EINVAL;
		5243	}
		5244
		5245	/* Ensure that the cursor is valid for the new mode before changing... */
		5246	// intel_crtc_update_cursor(crtc, true);
		5247
		5248	if (is_lvds && dev_priv->lvds_downclock_avail) {
		5249	has_reduced_clock = limit->find_pll(limit, crtc,
		5250	dev_priv->lvds_downclock,
		5251	refclk,
		5252	&reduced_clock);
		5253	if (has_reduced_clock && (clock.p != reduced_clock.p)) {
		5254	/*
		5255	* If the different P is found, it means that we can't
		5256	* switch the display clock by using the FP0/FP1.
		5257	* In such case we will disable the LVDS downclock
		5258	* feature.
		5259	*/
		5260	DRM_DEBUG_KMS("Different P is found for "
		5261	"LVDS clock/downclock\n");
		5262	has_reduced_clock = 0;
		5263	}
		5264	}
		5265	/* SDVO TV has fixed PLL values depend on its clock range,
		5266	this mirrors vbios setting. */
		5267	if (is_sdvo && is_tv) {
		5268	if (adjusted_mode->clock >= 100000
		5269	&& adjusted_mode->clock < 140500) {
		5270	clock.p1 = 2;
		5271	clock.p2 = 10;
		5272	clock.n = 3;
		5273	clock.m1 = 16;
		5274	clock.m2 = 8;
		5275	} else if (adjusted_mode->clock >= 140500
		5276	&& adjusted_mode->clock <= 200000) {
		5277	clock.p1 = 1;
		5278	clock.p2 = 10;
		5279	clock.n = 6;
		5280	clock.m1 = 12;
		5281	clock.m2 = 8;
		5282	}
		5283	}
		5284
		5285	/* FDI link */
		5286	pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		5287	lane = 0;
		5288	/* CPU eDP doesn't require FDI link, so just set DP M/N
		5289	according to current link config */
		5290	if (has_edp_encoder &&
		5291	!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5292	target_clock = mode->clock;
		5293	intel_edp_link_config(has_edp_encoder,
		5294	&lane, &link_bw);
		5295	} else {
		5296	/* [e]DP over FDI requires target mode clock
		5297	instead of link clock */
		5298	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base))
		5299	target_clock = mode->clock;
		5300	else
		5301	target_clock = adjusted_mode->clock;
		5302
		5303	/* FDI is a binary signal running at ~2.7GHz, encoding
		5304	* each output octet as 10 bits. The actual frequency
		5305	* is stored as a divider into a 100MHz clock, and the
		5306	* mode pixel clock is stored in units of 1KHz.
		5307	* Hence the bw of each lane in terms of the mode signal
		5308	* is:
		5309	*/
		5310	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		5311	}
		5312
		5313	/* determine panel color depth */
		5314	temp = I915_READ(PIPECONF(pipe));
		5315	temp &= ~PIPE_BPC_MASK;
		5316	dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
		5317	switch (pipe_bpp) {
		5318	case 18:
		5319	temp \|= PIPE_6BPC;
		5320	break;
		5321	case 24:
		5322	temp \|= PIPE_8BPC;
		5323	break;
		5324	case 30:
		5325	temp \|= PIPE_10BPC;
		5326	break;
		5327	case 36:
		5328	temp \|= PIPE_12BPC;
		5329	break;
		5330	default:
		5331	WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
		5332	pipe_bpp);
		5333	temp \|= PIPE_8BPC;
		5334	pipe_bpp = 24;
		5335	break;
		5336	}
		5337
		5338	intel_crtc->bpp = pipe_bpp;
		5339	I915_WRITE(PIPECONF(pipe), temp);
		5340
		5341	if (!lane) {
		5342	/*
		5343	* Account for spread spectrum to avoid
		5344	* oversubscribing the link. Max center spread
		5345	* is 2.5%; use 5% for safety's sake.
		5346	*/
		5347	u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
		5348	lane = bps / (link_bw * 8) + 1;
		5349	}
		5350
		5351	intel_crtc->fdi_lanes = lane;
		5352
		5353	if (pixel_multiplier > 1)
		5354	link_bw *= pixel_multiplier;
		5355	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
		5356	&m_n);
		5357
		5358	ironlake_update_pch_refclk(dev);
		5359
		5360	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;
		5361	if (has_reduced_clock)
		5362	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|
		5363	reduced_clock.m2;
		5364
		5365	/* Enable autotuning of the PLL clock (if permissible) */
		5366	factor = 21;
		5367	if (is_lvds) {
		5368	if ((intel_panel_use_ssc(dev_priv) &&
		5369	dev_priv->lvds_ssc_freq == 100) \|\|
		5370	(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
		5371	factor = 25;
		5372	} else if (is_sdvo && is_tv)
		5373	factor = 20;
		5374
		5375	if (clock.m < factor * clock.n)
		5376	fp \|= FP_CB_TUNE;
		5377
		5378	dpll = 0;
		5379
		5380	if (is_lvds)
		5381	dpll \|= DPLLB_MODE_LVDS;
		5382	else
		5383	dpll \|= DPLLB_MODE_DAC_SERIAL;
		5384	if (is_sdvo) {
		5385	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		5386	if (pixel_multiplier > 1) {
		5387	dpll \|= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
		5388	}
		5389	dpll \|= DPLL_DVO_HIGH_SPEED;
		5390	}
		5391	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base))
		5392	dpll \|= DPLL_DVO_HIGH_SPEED;
		5393
		5394	/* compute bitmask from p1 value */
		5395	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		5396	/* also FPA1 */
		5397	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		5398
		5399	switch (clock.p2) {
		5400	case 5:
		5401	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		5402	break;
		5403	case 7:
		5404	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		5405	break;
		5406	case 10:
		5407	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		5408	break;
		5409	case 14:
		5410	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		5411	break;
		5412	}
		5413
		5414	if (is_sdvo && is_tv)
		5415	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		5416	else if (is_tv)
		5417	/* XXX: just matching BIOS for now */
		5418	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		5419	dpll \|= 3;
		5420	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		5421	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5422	else
		5423	dpll \|= PLL_REF_INPUT_DREFCLK;
		5424
		5425	/* setup pipeconf */
		5426	pipeconf = I915_READ(PIPECONF(pipe));
		5427
		5428	/* Set up the display plane register */
		5429	dspcntr = DISPPLANE_GAMMA_ENABLE;
		5430
		5431	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
		5432	drm_mode_debug_printmodeline(mode);
		5433
		5434	/* PCH eDP needs FDI, but CPU eDP does not */
		5435	if (!has_edp_encoder \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5436	I915_WRITE(PCH_FP0(pipe), fp);
		5437	I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		5438
		5439	POSTING_READ(PCH_DPLL(pipe));
		5440	udelay(150);
		5441	}
		5442
		5443	/* enable transcoder DPLL */
		5444	if (HAS_PCH_CPT(dev)) {
		5445	temp = I915_READ(PCH_DPLL_SEL);
		5446	switch (pipe) {
		5447	case 0:
		5448	temp \|= TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL;
		5449	break;
		5450	case 1:
		5451	temp \|= TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL;
		5452	break;
		5453	case 2:
		5454	/* FIXME: manage transcoder PLLs? */
		5455	temp \|= TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL;
		5456	break;
		5457	default:
		5458	BUG();
		5459	}
		5460	I915_WRITE(PCH_DPLL_SEL, temp);
		5461
		5462	POSTING_READ(PCH_DPLL_SEL);
		5463	udelay(150);
		5464	}
		5465
		5466	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		5467	* This is an exception to the general rule that mode_set doesn't turn
		5468	* things on.
		5469	*/
		5470	if (is_lvds) {
		5471	temp = I915_READ(PCH_LVDS);
		5472	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
		5473	if (pipe == 1) {
		5474	if (HAS_PCH_CPT(dev))
		5475	temp \|= PORT_TRANS_B_SEL_CPT;
		5476	else
		5477	temp \|= LVDS_PIPEB_SELECT;
		5478	} else {
		5479	if (HAS_PCH_CPT(dev))
		5480	temp &= ~PORT_TRANS_SEL_MASK;
		5481	else
		5482	temp &= ~LVDS_PIPEB_SELECT;
		5483	}
		5484	/* set the corresponsding LVDS_BORDER bit */
		5485	temp \|= dev_priv->lvds_border_bits;
		5486	/* Set the B0-B3 data pairs corresponding to whether we're going to
		5487	* set the DPLLs for dual-channel mode or not.
		5488	*/
		5489	if (clock.p2 == 7)
		5490	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
		5491	else
		5492	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
		5493
		5494	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		5495	* appropriately here, but we need to look more thoroughly into how
		5496	* panels behave in the two modes.
		5497	*/
		5498	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
		5499	lvds_sync \|= LVDS_HSYNC_POLARITY;
		5500	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
		5501	lvds_sync \|= LVDS_VSYNC_POLARITY;
		5502	if ((temp & (LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY))
		5503	!= lvds_sync) {
		5504	char flags[2] = "-+";
		5505	DRM_INFO("Changing LVDS panel from "
		5506	"(%chsync, %cvsync) to (%chsync, %cvsync)\n",
		5507	flags[!(temp & LVDS_HSYNC_POLARITY)],
		5508	flags[!(temp & LVDS_VSYNC_POLARITY)],
		5509	flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
		5510	flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
		5511	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
		5512	temp \|= lvds_sync;
		5513	}
		5514	I915_WRITE(PCH_LVDS, temp);
		5515	}
		5516
		5517	pipeconf &= ~PIPECONF_DITHER_EN;
		5518	pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
		5519	if ((is_lvds && dev_priv->lvds_dither) \|\| dither) {
		5520	pipeconf \|= PIPECONF_DITHER_EN;
		5521	pipeconf \|= PIPECONF_DITHER_TYPE_ST1;
		5522	}
		5523	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5524	intel_dp_set_m_n(crtc, mode, adjusted_mode);
		5525	} else {
		5526	/* For non-DP output, clear any trans DP clock recovery setting.*/
		5527	I915_WRITE(TRANSDATA_M1(pipe), 0);
		5528	I915_WRITE(TRANSDATA_N1(pipe), 0);
		5529	I915_WRITE(TRANSDPLINK_M1(pipe), 0);
		5530	I915_WRITE(TRANSDPLINK_N1(pipe), 0);
		5531	}
		5532
		5533	if (!has_edp_encoder \|\|
		5534	intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5535	I915_WRITE(PCH_DPLL(pipe), dpll);
		5536
		5537	/* Wait for the clocks to stabilize. */
		5538	POSTING_READ(PCH_DPLL(pipe));
		5539	udelay(150);
		5540
		5541	/* The pixel multiplier can only be updated once the
		5542	* DPLL is enabled and the clocks are stable.
		5543	*
		5544	* So write it again.
		5545	*/
		5546	I915_WRITE(PCH_DPLL(pipe), dpll);
		5547	}
		5548
		5549	intel_crtc->lowfreq_avail = false;
		5550	if (is_lvds && has_reduced_clock && i915_powersave) {
		5551	I915_WRITE(PCH_FP1(pipe), fp2);
		5552	intel_crtc->lowfreq_avail = true;
		5553	if (HAS_PIPE_CXSR(dev)) {
		5554	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		5555	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		5556	}
		5557	} else {
		5558	I915_WRITE(PCH_FP1(pipe), fp);
		5559	if (HAS_PIPE_CXSR(dev)) {
		5560	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		5561	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		5562	}
		5563	}
		5564
		5565	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		5566	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		5567	/* the chip adds 2 halflines automatically */
		5568	adjusted_mode->crtc_vdisplay -= 1;
		5569	adjusted_mode->crtc_vtotal -= 1;
		5570	adjusted_mode->crtc_vblank_start -= 1;
		5571	adjusted_mode->crtc_vblank_end -= 1;
		5572	adjusted_mode->crtc_vsync_end -= 1;
		5573	adjusted_mode->crtc_vsync_start -= 1;
		5574	} else
		5575	pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
		5576
		5577	I915_WRITE(HTOTAL(pipe),
		5578	(adjusted_mode->crtc_hdisplay - 1) \|
		5579	((adjusted_mode->crtc_htotal - 1) << 16));
		5580	I915_WRITE(HBLANK(pipe),
		5581	(adjusted_mode->crtc_hblank_start - 1) \|
		5582	((adjusted_mode->crtc_hblank_end - 1) << 16));
		5583	I915_WRITE(HSYNC(pipe),
		5584	(adjusted_mode->crtc_hsync_start - 1) \|
		5585	((adjusted_mode->crtc_hsync_end - 1) << 16));
		5586
		5587	I915_WRITE(VTOTAL(pipe),
		5588	(adjusted_mode->crtc_vdisplay - 1) \|
		5589	((adjusted_mode->crtc_vtotal - 1) << 16));
		5590	I915_WRITE(VBLANK(pipe),
		5591	(adjusted_mode->crtc_vblank_start - 1) \|
		5592	((adjusted_mode->crtc_vblank_end - 1) << 16));
		5593	I915_WRITE(VSYNC(pipe),
		5594	(adjusted_mode->crtc_vsync_start - 1) \|
		5595	((adjusted_mode->crtc_vsync_end - 1) << 16));
		5596
		5597	/* pipesrc controls the size that is scaled from, which should
		5598	* always be the user's requested size.
		5599	*/
		5600	I915_WRITE(PIPESRC(pipe),
		5601	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		5602
		5603	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) \| m_n.gmch_m);
		5604	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
		5605	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
		5606	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
		5607
		5608	if (has_edp_encoder &&
		5609	!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5610	ironlake_set_pll_edp(crtc, adjusted_mode->clock);
		5611	}
		5612
		5613	I915_WRITE(PIPECONF(pipe), pipeconf);
		5614	POSTING_READ(PIPECONF(pipe));
		5615
		5616	intel_wait_for_vblank(dev, pipe);
		5617
		5618	if (IS_GEN5(dev)) {
		5619	/* enable address swizzle for tiling buffer */
		5620	temp = I915_READ(DISP_ARB_CTL);
		5621	I915_WRITE(DISP_ARB_CTL, temp \| DISP_TILE_SURFACE_SWIZZLING);
		5622	}
		5623
		5624	I915_WRITE(DSPCNTR(plane), dspcntr);
		5625	POSTING_READ(DSPCNTR(plane));
		5626
		5627	ret = intel_pipe_set_base(crtc, x, y, old_fb);
		5628
		5629	intel_update_watermarks(dev);
		5630
		5631	return ret;
		5632	}
		5633
2330	Serge	5634	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		5635	struct drm_display_mode *mode,
		5636	struct drm_display_mode *adjusted_mode,
		5637	int x, int y,
		5638	struct drm_framebuffer *old_fb)
		5639	{
		5640	struct drm_device *dev = crtc->dev;
		5641	struct drm_i915_private *dev_priv = dev->dev_private;
		5642	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5643	int pipe = intel_crtc->pipe;
		5644	int ret;
2327	Serge	5645
2330	Serge	5646	// drm_vblank_pre_modeset(dev, pipe);
2327	Serge	5647
2330	Serge	5648	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
		5649	x, y, old_fb);
2327	Serge	5650
2330	Serge	5651	// drm_vblank_post_modeset(dev, pipe);
2327	Serge	5652
2330	Serge	5653	intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
2327	Serge	5654
2330	Serge	5655	return ret;
		5656	}
2327	Serge	5657
		5658	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		5659	void intel_crtc_load_lut(struct drm_crtc *crtc)
		5660	{
		5661	struct drm_device *dev = crtc->dev;
		5662	struct drm_i915_private *dev_priv = dev->dev_private;
		5663	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5664	int palreg = PALETTE(intel_crtc->pipe);
		5665	int i;
		5666
		5667	/* The clocks have to be on to load the palette. */
		5668	if (!crtc->enabled)
		5669	return;
		5670
		5671	/* use legacy palette for Ironlake */
		5672	if (HAS_PCH_SPLIT(dev))
		5673	palreg = LGC_PALETTE(intel_crtc->pipe);
		5674
		5675	for (i = 0; i < 256; i++) {
		5676	I915_WRITE(palreg + 4 * i,
		5677	(intel_crtc->lut_r[i] << 16) \|
		5678	(intel_crtc->lut_g[i] << 8) \|
		5679	intel_crtc->lut_b[i]);
		5680	}
		5681	}
		5682
		5683
		5684
		5685
		5686
		5687
		5688
		5689
		5690
		5691
		5692
		5693
		5694
		5695
		5696
		5697
		5698
		5699
		5700
		5701
		5702
		5703
		5704
		5705
		5706
		5707
		5708
		5709
		5710
		5711
		5712
		5713
		5714
		5715
		5716
		5717
		5718
2332	Serge	5719	/** Sets the color ramps on behalf of RandR */
		5720	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		5721	u16 blue, int regno)
		5722	{
		5723	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5724
2332	Serge	5725	intel_crtc->lut_r[regno] = red >> 8;
		5726	intel_crtc->lut_g[regno] = green >> 8;
		5727	intel_crtc->lut_b[regno] = blue >> 8;
		5728	}
2327	Serge	5729
2332	Serge	5730	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		5731	u16 *blue, int regno)
		5732	{
		5733	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5734
2332	Serge	5735	*red = intel_crtc->lut_r[regno] << 8;
		5736	*green = intel_crtc->lut_g[regno] << 8;
		5737	*blue = intel_crtc->lut_b[regno] << 8;
		5738	}
2327	Serge	5739
2330	Serge	5740	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		5741	u16 *blue, uint32_t start, uint32_t size)
		5742	{
		5743	int end = (start + size > 256) ? 256 : start + size, i;
		5744	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5745
2330	Serge	5746	for (i = start; i < end; i++) {
		5747	intel_crtc->lut_r[i] = red[i] >> 8;
		5748	intel_crtc->lut_g[i] = green[i] >> 8;
		5749	intel_crtc->lut_b[i] = blue[i] >> 8;
		5750	}
2327	Serge	5751
2330	Serge	5752	intel_crtc_load_lut(crtc);
		5753	}
2327	Serge	5754
2330	Serge	5755	/**
		5756	* Get a pipe with a simple mode set on it for doing load-based monitor
		5757	* detection.
		5758	*
		5759	* It will be up to the load-detect code to adjust the pipe as appropriate for
		5760	* its requirements. The pipe will be connected to no other encoders.
		5761	*
		5762	* Currently this code will only succeed if there is a pipe with no encoders
		5763	* configured for it. In the future, it could choose to temporarily disable
		5764	* some outputs to free up a pipe for its use.
		5765	*
		5766	* \return crtc, or NULL if no pipes are available.
		5767	*/
2327	Serge	5768
2330	Serge	5769	/* VESA 640x480x72Hz mode to set on the pipe */
		5770	static struct drm_display_mode load_detect_mode = {
		5771	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		5772	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		5773	};
2327	Serge	5774
		5775
		5776
		5777
		5778
2330	Serge	5779	static u32
		5780	intel_framebuffer_pitch_for_width(int width, int bpp)
		5781	{
		5782	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		5783	return ALIGN(pitch, 64);
		5784	}
2327	Serge	5785
2330	Serge	5786	static u32
		5787	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		5788	{
		5789	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		5790	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		5791	}
2327	Serge	5792
2330	Serge	5793	static struct drm_framebuffer *
		5794	intel_framebuffer_create_for_mode(struct drm_device *dev,
		5795	struct drm_display_mode *mode,
		5796	int depth, int bpp)
		5797	{
		5798	struct drm_i915_gem_object *obj;
		5799	struct drm_mode_fb_cmd mode_cmd;
2327	Serge	5800
2330	Serge	5801	// obj = i915_gem_alloc_object(dev,
		5802	// intel_framebuffer_size_for_mode(mode, bpp));
		5803	// if (obj == NULL)
		5804	return ERR_PTR(-ENOMEM);
2327	Serge	5805
2330	Serge	5806	// mode_cmd.width = mode->hdisplay;
		5807	// mode_cmd.height = mode->vdisplay;
		5808	// mode_cmd.depth = depth;
		5809	// mode_cmd.bpp = bpp;
		5810	// mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
2327	Serge	5811
2330	Serge	5812	// return intel_framebuffer_create(dev, &mode_cmd, obj);
		5813	}
2327	Serge	5814
2330	Serge	5815	static struct drm_framebuffer *
		5816	mode_fits_in_fbdev(struct drm_device *dev,
		5817	struct drm_display_mode *mode)
		5818	{
		5819	struct drm_i915_private *dev_priv = dev->dev_private;
		5820	struct drm_i915_gem_object *obj;
		5821	struct drm_framebuffer *fb;
2327	Serge	5822
2330	Serge	5823	// if (dev_priv->fbdev == NULL)
		5824	// return NULL;
2327	Serge	5825
2330	Serge	5826	// obj = dev_priv->fbdev->ifb.obj;
		5827	// if (obj == NULL)
		5828	// return NULL;
2327	Serge	5829
2330	Serge	5830	// fb = &dev_priv->fbdev->ifb.base;
		5831	// if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
		5832	// fb->bits_per_pixel))
		5833	return NULL;
2327	Serge	5834
2330	Serge	5835	// if (obj->base.size < mode->vdisplay * fb->pitch)
		5836	// return NULL;
2327	Serge	5837
2330	Serge	5838	// return fb;
		5839	}
2327	Serge	5840
2330	Serge	5841	bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
		5842	struct drm_connector *connector,
		5843	struct drm_display_mode *mode,
		5844	struct intel_load_detect_pipe *old)
		5845	{
		5846	struct intel_crtc *intel_crtc;
		5847	struct drm_crtc *possible_crtc;
		5848	struct drm_encoder *encoder = &intel_encoder->base;
		5849	struct drm_crtc *crtc = NULL;
		5850	struct drm_device *dev = encoder->dev;
		5851	struct drm_framebuffer *old_fb;
		5852	int i = -1;
2327	Serge	5853
2330	Serge	5854	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5855	connector->base.id, drm_get_connector_name(connector),
		5856	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	5857
2330	Serge	5858	/*
		5859	* Algorithm gets a little messy:
		5860	*
		5861	* - if the connector already has an assigned crtc, use it (but make
		5862	* sure it's on first)
		5863	*
		5864	* - try to find the first unused crtc that can drive this connector,
		5865	* and use that if we find one
		5866	*/
2327	Serge	5867
2330	Serge	5868	/* See if we already have a CRTC for this connector */
		5869	if (encoder->crtc) {
		5870	crtc = encoder->crtc;
2327	Serge	5871
2330	Serge	5872	intel_crtc = to_intel_crtc(crtc);
		5873	old->dpms_mode = intel_crtc->dpms_mode;
		5874	old->load_detect_temp = false;
2327	Serge	5875
2330	Serge	5876	/* Make sure the crtc and connector are running */
		5877	if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
		5878	struct drm_encoder_helper_funcs *encoder_funcs;
		5879	struct drm_crtc_helper_funcs *crtc_funcs;
2327	Serge	5880
2330	Serge	5881	crtc_funcs = crtc->helper_private;
		5882	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2327	Serge	5883
2330	Serge	5884	encoder_funcs = encoder->helper_private;
		5885	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
		5886	}
2327	Serge	5887
2330	Serge	5888	return true;
		5889	}
2327	Serge	5890
2330	Serge	5891	/* Find an unused one (if possible) */
		5892	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		5893	i++;
		5894	if (!(encoder->possible_crtcs & (1 << i)))
		5895	continue;
		5896	if (!possible_crtc->enabled) {
		5897	crtc = possible_crtc;
		5898	break;
		5899	}
		5900	}
2327	Serge	5901
2330	Serge	5902	/*
		5903	* If we didn't find an unused CRTC, don't use any.
		5904	*/
		5905	if (!crtc) {
		5906	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		5907	return false;
		5908	}
2327	Serge	5909
2330	Serge	5910	encoder->crtc = crtc;
		5911	connector->encoder = encoder;
2327	Serge	5912
2330	Serge	5913	intel_crtc = to_intel_crtc(crtc);
		5914	old->dpms_mode = intel_crtc->dpms_mode;
		5915	old->load_detect_temp = true;
		5916	old->release_fb = NULL;
2327	Serge	5917
2330	Serge	5918	if (!mode)
		5919	mode = &load_detect_mode;
2327	Serge	5920
2330	Serge	5921	old_fb = crtc->fb;
2327	Serge	5922
2330	Serge	5923	/* We need a framebuffer large enough to accommodate all accesses
		5924	* that the plane may generate whilst we perform load detection.
		5925	* We can not rely on the fbcon either being present (we get called
		5926	* during its initialisation to detect all boot displays, or it may
		5927	* not even exist) or that it is large enough to satisfy the
		5928	* requested mode.
		5929	*/
		5930	crtc->fb = mode_fits_in_fbdev(dev, mode);
		5931	if (crtc->fb == NULL) {
		5932	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
		5933	crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		5934	old->release_fb = crtc->fb;
		5935	} else
		5936	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
		5937	if (IS_ERR(crtc->fb)) {
		5938	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
		5939	crtc->fb = old_fb;
		5940	return false;
		5941	}
2327	Serge	5942
2330	Serge	5943	if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
		5944	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		5945	if (old->release_fb)
		5946	old->release_fb->funcs->destroy(old->release_fb);
		5947	crtc->fb = old_fb;
		5948	return false;
		5949	}
2327	Serge	5950
2330	Serge	5951	/* let the connector get through one full cycle before testing */
		5952	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	5953
2330	Serge	5954	return true;
		5955	}
2327	Serge	5956
2330	Serge	5957	void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
		5958	struct drm_connector *connector,
		5959	struct intel_load_detect_pipe *old)
		5960	{
		5961	struct drm_encoder *encoder = &intel_encoder->base;
		5962	struct drm_device *dev = encoder->dev;
		5963	struct drm_crtc *crtc = encoder->crtc;
		5964	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
		5965	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2327	Serge	5966
2330	Serge	5967	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5968	connector->base.id, drm_get_connector_name(connector),
		5969	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	5970
2330	Serge	5971	if (old->load_detect_temp) {
		5972	connector->encoder = NULL;
		5973	drm_helper_disable_unused_functions(dev);
2327	Serge	5974
2330	Serge	5975	if (old->release_fb)
		5976	old->release_fb->funcs->destroy(old->release_fb);
2327	Serge	5977
2330	Serge	5978	return;
		5979	}
2327	Serge	5980
2330	Serge	5981	/* Switch crtc and encoder back off if necessary */
		5982	if (old->dpms_mode != DRM_MODE_DPMS_ON) {
		5983	encoder_funcs->dpms(encoder, old->dpms_mode);
		5984	crtc_funcs->dpms(crtc, old->dpms_mode);
		5985	}
		5986	}
2327	Serge	5987
2330	Serge	5988	/* Returns the clock of the currently programmed mode of the given pipe. */
		5989	static int intel_crtc_clock_get(struct drm_device dev, struct drm_crtc crtc)
		5990	{
		5991	struct drm_i915_private *dev_priv = dev->dev_private;
		5992	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5993	int pipe = intel_crtc->pipe;
		5994	u32 dpll = I915_READ(DPLL(pipe));
		5995	u32 fp;
		5996	intel_clock_t clock;
2327	Serge	5997
2330	Serge	5998	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		5999	fp = I915_READ(FP0(pipe));
		6000	else
		6001	fp = I915_READ(FP1(pipe));
2327	Serge	6002
2330	Serge	6003	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		6004	if (IS_PINEVIEW(dev)) {
		6005	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		6006	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		6007	} else {
		6008	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		6009	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		6010	}
2327	Serge	6011
2330	Serge	6012	if (!IS_GEN2(dev)) {
		6013	if (IS_PINEVIEW(dev))
		6014	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		6015	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		6016	else
		6017	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		6018	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	6019
2330	Serge	6020	switch (dpll & DPLL_MODE_MASK) {
		6021	case DPLLB_MODE_DAC_SERIAL:
		6022	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		6023	5 : 10;
		6024	break;
		6025	case DPLLB_MODE_LVDS:
		6026	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		6027	7 : 14;
		6028	break;
		6029	default:
		6030	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		6031	"mode\n", (int)(dpll & DPLL_MODE_MASK));
		6032	return 0;
		6033	}
2327	Serge	6034
2330	Serge	6035	/* XXX: Handle the 100Mhz refclk */
		6036	intel_clock(dev, 96000, &clock);
		6037	} else {
		6038	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	6039
2330	Serge	6040	if (is_lvds) {
		6041	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		6042	DPLL_FPA01_P1_POST_DIV_SHIFT);
		6043	clock.p2 = 14;
2327	Serge	6044
2330	Serge	6045	if ((dpll & PLL_REF_INPUT_MASK) ==
		6046	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		6047	/* XXX: might not be 66MHz */
		6048	intel_clock(dev, 66000, &clock);
		6049	} else
		6050	intel_clock(dev, 48000, &clock);
		6051	} else {
		6052	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		6053	clock.p1 = 2;
		6054	else {
		6055	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		6056	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		6057	}
		6058	if (dpll & PLL_P2_DIVIDE_BY_4)
		6059	clock.p2 = 4;
		6060	else
		6061	clock.p2 = 2;
2327	Serge	6062
2330	Serge	6063	intel_clock(dev, 48000, &clock);
		6064	}
		6065	}
2327	Serge	6066
2330	Serge	6067	/* XXX: It would be nice to validate the clocks, but we can't reuse
		6068	* i830PllIsValid() because it relies on the xf86_config connector
		6069	* configuration being accurate, which it isn't necessarily.
		6070	*/
2327	Serge	6071
2330	Serge	6072	return clock.dot;
		6073	}
2327	Serge	6074
2330	Serge	6075	/** Returns the currently programmed mode of the given pipe. */
		6076	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		6077	struct drm_crtc *crtc)
		6078	{
		6079	struct drm_i915_private *dev_priv = dev->dev_private;
		6080	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6081	int pipe = intel_crtc->pipe;
		6082	struct drm_display_mode *mode;
		6083	int htot = I915_READ(HTOTAL(pipe));
		6084	int hsync = I915_READ(HSYNC(pipe));
		6085	int vtot = I915_READ(VTOTAL(pipe));
		6086	int vsync = I915_READ(VSYNC(pipe));
2327	Serge	6087
2330	Serge	6088	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		6089	if (!mode)
		6090	return NULL;
		6091
		6092	mode->clock = intel_crtc_clock_get(dev, crtc);
		6093	mode->hdisplay = (htot & 0xffff) + 1;
		6094	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		6095	mode->hsync_start = (hsync & 0xffff) + 1;
		6096	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		6097	mode->vdisplay = (vtot & 0xffff) + 1;
		6098	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		6099	mode->vsync_start = (vsync & 0xffff) + 1;
		6100	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		6101
		6102	drm_mode_set_name(mode);
		6103	drm_mode_set_crtcinfo(mode, 0);
		6104
		6105	return mode;
		6106	}
		6107
		6108	#define GPU_IDLE_TIMEOUT 500 /* ms */
		6109
		6110
		6111
		6112
		6113	#define CRTC_IDLE_TIMEOUT 1000 /* ms */
		6114
		6115
		6116
		6117
2327	Serge	6118	static void intel_increase_pllclock(struct drm_crtc *crtc)
		6119	{
		6120	struct drm_device *dev = crtc->dev;
		6121	drm_i915_private_t *dev_priv = dev->dev_private;
		6122	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6123	int pipe = intel_crtc->pipe;
		6124	int dpll_reg = DPLL(pipe);
		6125	int dpll;
		6126
		6127	if (HAS_PCH_SPLIT(dev))
		6128	return;
		6129
		6130	if (!dev_priv->lvds_downclock_avail)
		6131	return;
		6132
		6133	dpll = I915_READ(dpll_reg);
		6134	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		6135	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		6136
		6137	/* Unlock panel regs */
		6138	I915_WRITE(PP_CONTROL,
		6139	I915_READ(PP_CONTROL) \| PANEL_UNLOCK_REGS);
		6140
		6141	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		6142	I915_WRITE(dpll_reg, dpll);
		6143	intel_wait_for_vblank(dev, pipe);
		6144
		6145	dpll = I915_READ(dpll_reg);
		6146	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		6147	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		6148
		6149	/* ...and lock them again */
		6150	I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
		6151	}
		6152
		6153	/* Schedule downclock */
		6154	// mod_timer(&intel_crtc->idle_timer, jiffies +
		6155	// msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
		6156	}
		6157
		6158
		6159
		6160
		6161
		6162
		6163
		6164
		6165
		6166
		6167
		6168
		6169
		6170
		6171
		6172
		6173
		6174
		6175
		6176
		6177
		6178
2330	Serge	6179	static void intel_crtc_destroy(struct drm_crtc *crtc)
		6180	{
		6181	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6182	struct drm_device *dev = crtc->dev;
		6183	struct intel_unpin_work *work;
		6184	unsigned long flags;
2327	Serge	6185
2330	Serge	6186	spin_lock_irqsave(&dev->event_lock, flags);
		6187	work = intel_crtc->unpin_work;
		6188	intel_crtc->unpin_work = NULL;
		6189	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6190
2330	Serge	6191	if (work) {
		6192	// cancel_work_sync(&work->work);
		6193	kfree(work);
		6194	}
2327	Serge	6195
2330	Serge	6196	drm_crtc_cleanup(crtc);
2327	Serge	6197
2330	Serge	6198	kfree(intel_crtc);
		6199	}
2327	Serge	6200
		6201
		6202
		6203
		6204
		6205
		6206
		6207
		6208
		6209
		6210
		6211
		6212
		6213
		6214
		6215
		6216
		6217
		6218
		6219
		6220
		6221
		6222
		6223
		6224
		6225
		6226
		6227
		6228
		6229
		6230
		6231
		6232
		6233
		6234
		6235
		6236
		6237
		6238
		6239
		6240
		6241
		6242
		6243
		6244
		6245
		6246
		6247
		6248
		6249
		6250
		6251
		6252
		6253
		6254
		6255
		6256
		6257
		6258
		6259
		6260
		6261
		6262
		6263
		6264
		6265
2330	Serge	6266	static void intel_sanitize_modesetting(struct drm_device *dev,
		6267	int pipe, int plane)
		6268	{
		6269	struct drm_i915_private *dev_priv = dev->dev_private;
		6270	u32 reg, val;
2327	Serge	6271
2330	Serge	6272	if (HAS_PCH_SPLIT(dev))
		6273	return;
2327	Serge	6274
2330	Serge	6275	/* Who knows what state these registers were left in by the BIOS or
		6276	* grub?
		6277	*
		6278	* If we leave the registers in a conflicting state (e.g. with the
		6279	* display plane reading from the other pipe than the one we intend
		6280	* to use) then when we attempt to teardown the active mode, we will
		6281	* not disable the pipes and planes in the correct order -- leaving
		6282	* a plane reading from a disabled pipe and possibly leading to
		6283	* undefined behaviour.
		6284	*/
2327	Serge	6285
2330	Serge	6286	reg = DSPCNTR(plane);
		6287	val = I915_READ(reg);
2327	Serge	6288
2330	Serge	6289	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		6290	return;
		6291	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
		6292	return;
2327	Serge	6293
2330	Serge	6294	/* This display plane is active and attached to the other CPU pipe. */
		6295	pipe = !pipe;
2327	Serge	6296
2330	Serge	6297	/* Disable the plane and wait for it to stop reading from the pipe. */
		6298	intel_disable_plane(dev_priv, plane, pipe);
		6299	intel_disable_pipe(dev_priv, pipe);
		6300	}
2327	Serge	6301
2330	Serge	6302	static void intel_crtc_reset(struct drm_crtc *crtc)
		6303	{
		6304	struct drm_device *dev = crtc->dev;
		6305	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6306
2330	Serge	6307	/* Reset flags back to the 'unknown' status so that they
		6308	* will be correctly set on the initial modeset.
		6309	*/
		6310	intel_crtc->dpms_mode = -1;
2327	Serge	6311
2330	Serge	6312	/* We need to fix up any BIOS configuration that conflicts with
		6313	* our expectations.
		6314	*/
		6315	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
		6316	}
2327	Serge	6317
2330	Serge	6318	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		6319	.dpms = intel_crtc_dpms,
		6320	.mode_fixup = intel_crtc_mode_fixup,
		6321	.mode_set = intel_crtc_mode_set,
		6322	.mode_set_base = intel_pipe_set_base,
		6323	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		6324	.load_lut = intel_crtc_load_lut,
		6325	.disable = intel_crtc_disable,
		6326	};
2327	Serge	6327
2330	Serge	6328	static const struct drm_crtc_funcs intel_crtc_funcs = {
		6329	.reset = intel_crtc_reset,
		6330	// .cursor_set = intel_crtc_cursor_set,
		6331	// .cursor_move = intel_crtc_cursor_move,
		6332	.gamma_set = intel_crtc_gamma_set,
		6333	.set_config = drm_crtc_helper_set_config,
		6334	.destroy = intel_crtc_destroy,
		6335	// .page_flip = intel_crtc_page_flip,
		6336	};
2327	Serge	6337
2330	Serge	6338	static void intel_crtc_init(struct drm_device *dev, int pipe)
		6339	{
		6340	drm_i915_private_t *dev_priv = dev->dev_private;
		6341	struct intel_crtc *intel_crtc;
		6342	int i;
2327	Serge	6343
2330	Serge	6344	ENTER();
2327	Serge	6345
2330	Serge	6346	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		6347	if (intel_crtc == NULL)
		6348	return;
2327	Serge	6349
2330	Serge	6350	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	6351
2330	Serge	6352	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		6353	for (i = 0; i < 256; i++) {
		6354	intel_crtc->lut_r[i] = i;
		6355	intel_crtc->lut_g[i] = i;
		6356	intel_crtc->lut_b[i] = i;
		6357	}
2327	Serge	6358
2330	Serge	6359	/* Swap pipes & planes for FBC on pre-965 */
		6360	intel_crtc->pipe = pipe;
		6361	intel_crtc->plane = pipe;
		6362	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		6363	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		6364	intel_crtc->plane = !pipe;
		6365	}
2327	Serge	6366
2330	Serge	6367	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		6368	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		6369	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		6370	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	6371
2330	Serge	6372	intel_crtc_reset(&intel_crtc->base);
		6373	intel_crtc->active = true; /* force the pipe off on setup_init_config */
		6374	intel_crtc->bpp = 24; /* default for pre-Ironlake */
2327	Serge	6375
2330	Serge	6376	if (HAS_PCH_SPLIT(dev)) {
		6377	intel_helper_funcs.prepare = ironlake_crtc_prepare;
		6378	intel_helper_funcs.commit = ironlake_crtc_commit;
		6379	} else {
		6380	intel_helper_funcs.prepare = i9xx_crtc_prepare;
		6381	intel_helper_funcs.commit = i9xx_crtc_commit;
		6382	}
2327	Serge	6383
2330	Serge	6384	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2327	Serge	6385
2330	Serge	6386	intel_crtc->busy = false;
2327	Serge	6387
2330	Serge	6388	LEAVE();
2327	Serge	6389
2330	Serge	6390	// setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
		6391	// (unsigned long)intel_crtc);
		6392	}
2327	Serge	6393
		6394
		6395
		6396
		6397
		6398
		6399
2330	Serge	6400	static int intel_encoder_clones(struct drm_device *dev, int type_mask)
		6401	{
		6402	struct intel_encoder *encoder;
		6403	int index_mask = 0;
		6404	int entry = 0;
2327	Serge	6405
2330	Serge	6406	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		6407	if (type_mask & encoder->clone_mask)
		6408	index_mask \|= (1 << entry);
		6409	entry++;
		6410	}
2327	Serge	6411
2330	Serge	6412	return index_mask;
		6413	}
2327	Serge	6414
2330	Serge	6415	static bool has_edp_a(struct drm_device *dev)
		6416	{
		6417	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	6418
2330	Serge	6419	if (!IS_MOBILE(dev))
		6420	return false;
2327	Serge	6421
2330	Serge	6422	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		6423	return false;
2327	Serge	6424
2330	Serge	6425	if (IS_GEN5(dev) &&
		6426	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		6427	return false;
2327	Serge	6428
2330	Serge	6429	return true;
		6430	}
2327	Serge	6431
2330	Serge	6432	static void intel_setup_outputs(struct drm_device *dev)
		6433	{
		6434	struct drm_i915_private *dev_priv = dev->dev_private;
		6435	struct intel_encoder *encoder;
		6436	bool dpd_is_edp = false;
		6437	bool has_lvds = false;
2327	Serge	6438
2330	Serge	6439	if (IS_MOBILE(dev) && !IS_I830(dev))
		6440	has_lvds = intel_lvds_init(dev);
		6441	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		6442	/* disable the panel fitter on everything but LVDS */
		6443	I915_WRITE(PFIT_CONTROL, 0);
		6444	}
2327	Serge	6445
2330	Serge	6446	if (HAS_PCH_SPLIT(dev)) {
		6447	dpd_is_edp = intel_dpd_is_edp(dev);
2327	Serge	6448
2330	Serge	6449	if (has_edp_a(dev))
		6450	intel_dp_init(dev, DP_A);
2327	Serge	6451
2330	Serge	6452	if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
		6453	intel_dp_init(dev, PCH_DP_D);
		6454	}
2327	Serge	6455
2330	Serge	6456	intel_crt_init(dev);
2327	Serge	6457
2330	Serge	6458	if (HAS_PCH_SPLIT(dev)) {
		6459	int found;
2327	Serge	6460
2330	Serge	6461	if (I915_READ(HDMIB) & PORT_DETECTED) {
		6462	/* PCH SDVOB multiplex with HDMIB */
		6463	found = intel_sdvo_init(dev, PCH_SDVOB);
		6464	if (!found)
		6465	intel_hdmi_init(dev, HDMIB);
		6466	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
		6467	intel_dp_init(dev, PCH_DP_B);
		6468	}
2327	Serge	6469
2330	Serge	6470	if (I915_READ(HDMIC) & PORT_DETECTED)
		6471	intel_hdmi_init(dev, HDMIC);
2327	Serge	6472
2330	Serge	6473	if (I915_READ(HDMID) & PORT_DETECTED)
		6474	intel_hdmi_init(dev, HDMID);
2327	Serge	6475
2330	Serge	6476	if (I915_READ(PCH_DP_C) & DP_DETECTED)
		6477	intel_dp_init(dev, PCH_DP_C);
2327	Serge	6478
2330	Serge	6479	if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
		6480	intel_dp_init(dev, PCH_DP_D);
2327	Serge	6481
2330	Serge	6482	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		6483	bool found = false;
2327	Serge	6484
2330	Serge	6485	if (I915_READ(SDVOB) & SDVO_DETECTED) {
		6486	DRM_DEBUG_KMS("probing SDVOB\n");
		6487	found = intel_sdvo_init(dev, SDVOB);
		6488	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		6489	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
		6490	intel_hdmi_init(dev, SDVOB);
		6491	}
2327	Serge	6492
2330	Serge	6493	if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
		6494	DRM_DEBUG_KMS("probing DP_B\n");
		6495	intel_dp_init(dev, DP_B);
		6496	}
		6497	}
2327	Serge	6498
2330	Serge	6499	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	6500
2330	Serge	6501	if (I915_READ(SDVOB) & SDVO_DETECTED) {
		6502	DRM_DEBUG_KMS("probing SDVOC\n");
		6503	found = intel_sdvo_init(dev, SDVOC);
		6504	}
2327	Serge	6505
2330	Serge	6506	if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
2327	Serge	6507
2330	Serge	6508	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		6509	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
		6510	intel_hdmi_init(dev, SDVOC);
		6511	}
		6512	if (SUPPORTS_INTEGRATED_DP(dev)) {
		6513	DRM_DEBUG_KMS("probing DP_C\n");
		6514	intel_dp_init(dev, DP_C);
		6515	}
		6516	}
2327	Serge	6517
2330	Serge	6518	if (SUPPORTS_INTEGRATED_DP(dev) &&
		6519	(I915_READ(DP_D) & DP_DETECTED)) {
		6520	DRM_DEBUG_KMS("probing DP_D\n");
		6521	intel_dp_init(dev, DP_D);
		6522	}
		6523	} else if (IS_GEN2(dev))
		6524	intel_dvo_init(dev);
2327	Serge	6525
2330	Serge	6526	// if (SUPPORTS_TV(dev))
		6527	// intel_tv_init(dev);
2327	Serge	6528
2330	Serge	6529	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		6530	encoder->base.possible_crtcs = encoder->crtc_mask;
		6531	encoder->base.possible_clones =
		6532	intel_encoder_clones(dev, encoder->clone_mask);
		6533	}
2327	Serge	6534
2330	Serge	6535	/* disable all the possible outputs/crtcs before entering KMS mode */
		6536	// drm_helper_disable_unused_functions(dev);
		6537	}
		6538
		6539
		6540
		6541
2327	Serge	6542	static const struct drm_mode_config_funcs intel_mode_funcs = {
		6543	.fb_create = NULL /intel_user_framebuffer_create/,
		6544	.output_poll_changed = NULL /intel_fb_output_poll_changed/,
		6545	};
		6546
		6547
		6548
		6549
		6550
		6551
		6552
		6553
		6554
		6555
		6556
		6557
		6558
2335	Serge	6559	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		6560	// .destroy = intel_user_framebuffer_destroy,
		6561	// .create_handle = intel_user_framebuffer_create_handle,
		6562	};
2327	Serge	6563
2335	Serge	6564	int intel_framebuffer_init(struct drm_device *dev,
		6565	struct intel_framebuffer *intel_fb,
		6566	struct drm_mode_fb_cmd *mode_cmd,
		6567	struct drm_i915_gem_object *obj)
		6568	{
		6569	int ret;
2327	Serge	6570
2335	Serge	6571	if (obj->tiling_mode == I915_TILING_Y)
		6572	return -EINVAL;
2327	Serge	6573
2335	Serge	6574	if (mode_cmd->pitch & 63)
		6575	return -EINVAL;
2327	Serge	6576
2335	Serge	6577	switch (mode_cmd->bpp) {
		6578	case 8:
		6579	case 16:
		6580	/* Only pre-ILK can handle 5:5:5 */
		6581	if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
		6582	return -EINVAL;
		6583	break;
2327	Serge	6584
2335	Serge	6585	case 24:
		6586	case 32:
		6587	break;
		6588	default:
		6589	return -EINVAL;
		6590	}
2327	Serge	6591
2335	Serge	6592	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		6593	if (ret) {
		6594	DRM_ERROR("framebuffer init failed %d\n", ret);
		6595	return ret;
		6596	}
2327	Serge	6597
2335	Serge	6598	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		6599	intel_fb->obj = obj;
		6600	return 0;
		6601	}
2327	Serge	6602
		6603
		6604
		6605
		6606
		6607
		6608
		6609
		6610
		6611
		6612
		6613
2330	Serge	6614	bool ironlake_set_drps(struct drm_device *dev, u8 val)
		6615	{
		6616	struct drm_i915_private *dev_priv = dev->dev_private;
		6617	u16 rgvswctl;
2327	Serge	6618
2330	Serge	6619	rgvswctl = I915_READ16(MEMSWCTL);
		6620	if (rgvswctl & MEMCTL_CMD_STS) {
		6621	DRM_DEBUG("gpu busy, RCS change rejected\n");
		6622	return false; /* still busy with another command */
		6623	}
2327	Serge	6624
2330	Serge	6625	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) \|
		6626	(val << MEMCTL_FREQ_SHIFT) \| MEMCTL_SFCAVM;
		6627	I915_WRITE16(MEMSWCTL, rgvswctl);
		6628	POSTING_READ16(MEMSWCTL);
2327	Serge	6629
2330	Serge	6630	rgvswctl \|= MEMCTL_CMD_STS;
		6631	I915_WRITE16(MEMSWCTL, rgvswctl);
2327	Serge	6632
2330	Serge	6633	return true;
		6634	}
2327	Serge	6635
2330	Serge	6636	void ironlake_enable_drps(struct drm_device *dev)
		6637	{
		6638	struct drm_i915_private *dev_priv = dev->dev_private;
		6639	u32 rgvmodectl = I915_READ(MEMMODECTL);
		6640	u8 fmax, fmin, fstart, vstart;
2327	Serge	6641
2330	Serge	6642	/* Enable temp reporting */
		6643	I915_WRITE16(PMMISC, I915_READ(PMMISC) \| MCPPCE_EN);
		6644	I915_WRITE16(TSC1, I915_READ(TSC1) \| TSE);
2327	Serge	6645
2330	Serge	6646	/* 100ms RC evaluation intervals */
		6647	I915_WRITE(RCUPEI, 100000);
		6648	I915_WRITE(RCDNEI, 100000);
2327	Serge	6649
2330	Serge	6650	/* Set max/min thresholds to 90ms and 80ms respectively */
		6651	I915_WRITE(RCBMAXAVG, 90000);
		6652	I915_WRITE(RCBMINAVG, 80000);
2327	Serge	6653
2330	Serge	6654	I915_WRITE(MEMIHYST, 1);
2327	Serge	6655
2330	Serge	6656	/* Set up min, max, and cur for interrupt handling */
		6657	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
		6658	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
		6659	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
		6660	MEMMODE_FSTART_SHIFT;
2327	Serge	6661
2330	Serge	6662	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
		6663	PXVFREQ_PX_SHIFT;
2327	Serge	6664
2330	Serge	6665	dev_priv->fmax = fmax; /* IPS callback will increase this */
		6666	dev_priv->fstart = fstart;
2327	Serge	6667
2330	Serge	6668	dev_priv->max_delay = fstart;
		6669	dev_priv->min_delay = fmin;
		6670	dev_priv->cur_delay = fstart;
2327	Serge	6671
2330	Serge	6672	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
		6673	fmax, fmin, fstart);
2327	Serge	6674
2330	Serge	6675	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN \| MEMINT_EVAL_CHG_EN);
2327	Serge	6676
2330	Serge	6677	/*
		6678	* Interrupts will be enabled in ironlake_irq_postinstall
		6679	*/
2327	Serge	6680
2330	Serge	6681	I915_WRITE(VIDSTART, vstart);
		6682	POSTING_READ(VIDSTART);
2327	Serge	6683
2330	Serge	6684	rgvmodectl \|= MEMMODE_SWMODE_EN;
		6685	I915_WRITE(MEMMODECTL, rgvmodectl);
2327	Serge	6686
2330	Serge	6687	if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
		6688	DRM_ERROR("stuck trying to change perf mode\n");
		6689	msleep(1);
2327	Serge	6690
2330	Serge	6691	ironlake_set_drps(dev, fstart);
2327	Serge	6692
2330	Serge	6693	dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
		6694	I915_READ(0x112e0);
		6695	// dev_priv->last_time1 = jiffies_to_msecs(jiffies);
		6696	dev_priv->last_count2 = I915_READ(0x112f4);
		6697	// getrawmonotonic(&dev_priv->last_time2);
		6698	}
2327	Serge	6699
		6700
		6701
		6702
		6703
		6704
		6705
		6706
		6707
		6708
		6709
		6710
		6711
		6712
		6713
2330	Serge	6714	static unsigned long intel_pxfreq(u32 vidfreq)
		6715	{
		6716	unsigned long freq;
		6717	int div = (vidfreq & 0x3f0000) >> 16;
		6718	int post = (vidfreq & 0x3000) >> 12;
		6719	int pre = (vidfreq & 0x7);
2327	Serge	6720
2330	Serge	6721	if (!pre)
		6722	return 0;
2327	Serge	6723
2330	Serge	6724	freq = ((div * 133333) / ((1<
2327	Serge	6725
2330	Serge	6726	return freq;
		6727	}
2327	Serge	6728
2330	Serge	6729	void intel_init_emon(struct drm_device *dev)
		6730	{
		6731	struct drm_i915_private *dev_priv = dev->dev_private;
		6732	u32 lcfuse;
		6733	u8 pxw[16];
		6734	int i;
2327	Serge	6735
2330	Serge	6736	/* Disable to program */
		6737	I915_WRITE(ECR, 0);
		6738	POSTING_READ(ECR);
2327	Serge	6739
2330	Serge	6740	/* Program energy weights for various events */
		6741	I915_WRITE(SDEW, 0x15040d00);
		6742	I915_WRITE(CSIEW0, 0x007f0000);
		6743	I915_WRITE(CSIEW1, 0x1e220004);
		6744	I915_WRITE(CSIEW2, 0x04000004);
2327	Serge	6745
2330	Serge	6746	for (i = 0; i < 5; i++)
		6747	I915_WRITE(PEW + (i * 4), 0);
		6748	for (i = 0; i < 3; i++)
		6749	I915_WRITE(DEW + (i * 4), 0);
2327	Serge	6750
2330	Serge	6751	/* Program P-state weights to account for frequency power adjustment */
		6752	for (i = 0; i < 16; i++) {
		6753	u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
		6754	unsigned long freq = intel_pxfreq(pxvidfreq);
		6755	unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
		6756	PXVFREQ_PX_SHIFT;
		6757	unsigned long val;
2327	Serge	6758
2330	Serge	6759	val = vid * vid;
		6760	val *= (freq / 1000);
		6761	val *= 255;
		6762	val /= (127127900);
		6763	if (val > 0xff)
		6764	DRM_ERROR("bad pxval: %ld\n", val);
		6765	pxw[i] = val;
		6766	}
		6767	/* Render standby states get 0 weight */
		6768	pxw[14] = 0;
		6769	pxw[15] = 0;
2327	Serge	6770
2330	Serge	6771	for (i = 0; i < 4; i++) {
		6772	u32 val = (pxw[i4] << 24) \| (pxw[(i4)+1] << 16) \|
		6773	(pxw[(i4)+2] << 8) \| (pxw[(i4)+3]);
		6774	I915_WRITE(PXW + (i * 4), val);
		6775	}
2327	Serge	6776
2330	Serge	6777	/* Adjust magic regs to magic values (more experimental results) */
		6778	I915_WRITE(OGW0, 0);
		6779	I915_WRITE(OGW1, 0);
		6780	I915_WRITE(EG0, 0x00007f00);
		6781	I915_WRITE(EG1, 0x0000000e);
		6782	I915_WRITE(EG2, 0x000e0000);
		6783	I915_WRITE(EG3, 0x68000300);
		6784	I915_WRITE(EG4, 0x42000000);
		6785	I915_WRITE(EG5, 0x00140031);
		6786	I915_WRITE(EG6, 0);
		6787	I915_WRITE(EG7, 0);
2327	Serge	6788
2330	Serge	6789	for (i = 0; i < 8; i++)
		6790	I915_WRITE(PXWL + (i * 4), 0);
2327	Serge	6791
2330	Serge	6792	/* Enable PMON + select events */
		6793	I915_WRITE(ECR, 0x80000019);
2327	Serge	6794
2330	Serge	6795	lcfuse = I915_READ(LCFUSE02);
		6796
		6797	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
		6798	}
		6799
		6800	void gen6_enable_rps(struct drm_i915_private *dev_priv)
		6801	{
		6802	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
		6803	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
		6804	u32 pcu_mbox, rc6_mask = 0;
		6805	int cur_freq, min_freq, max_freq;
		6806	int i;
		6807
		6808	/* Here begins a magic sequence of register writes to enable
		6809	* auto-downclocking.
		6810	*
		6811	* Perhaps there might be some value in exposing these to
		6812	* userspace...
		6813	*/
		6814	I915_WRITE(GEN6_RC_STATE, 0);
		6815	mutex_lock(&dev_priv->dev->struct_mutex);
		6816	gen6_gt_force_wake_get(dev_priv);
		6817
		6818	/* disable the counters and set deterministic thresholds */
		6819	I915_WRITE(GEN6_RC_CONTROL, 0);
		6820
		6821	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
		6822	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 \| 30);
		6823	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
		6824	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
		6825	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
		6826
		6827	for (i = 0; i < I915_NUM_RINGS; i++)
		6828	I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
		6829
		6830	I915_WRITE(GEN6_RC_SLEEP, 0);
		6831	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
		6832	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
		6833	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
		6834	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
		6835
		6836	if (i915_enable_rc6)
		6837	rc6_mask = GEN6_RC_CTL_RC6p_ENABLE \|
		6838	GEN6_RC_CTL_RC6_ENABLE;
		6839
		6840	I915_WRITE(GEN6_RC_CONTROL,
		6841	rc6_mask \|
		6842	GEN6_RC_CTL_EI_MODE(1) \|
		6843	GEN6_RC_CTL_HW_ENABLE);
		6844
		6845	I915_WRITE(GEN6_RPNSWREQ,
		6846	GEN6_FREQUENCY(10) \|
		6847	GEN6_OFFSET(0) \|
		6848	GEN6_AGGRESSIVE_TURBO);
		6849	I915_WRITE(GEN6_RC_VIDEO_FREQ,
		6850	GEN6_FREQUENCY(12));
		6851
		6852	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
		6853	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
		6854	18 << 24 \|
		6855	6 << 16);
		6856	I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
		6857	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
		6858	I915_WRITE(GEN6_RP_UP_EI, 100000);
		6859	I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
		6860	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
		6861	I915_WRITE(GEN6_RP_CONTROL,
		6862	GEN6_RP_MEDIA_TURBO \|
		6863	GEN6_RP_USE_NORMAL_FREQ \|
		6864	GEN6_RP_MEDIA_IS_GFX \|
		6865	GEN6_RP_ENABLE \|
		6866	GEN6_RP_UP_BUSY_AVG \|
		6867	GEN6_RP_DOWN_IDLE_CONT);
		6868
		6869	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		6870	500))
		6871	DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
		6872
		6873	I915_WRITE(GEN6_PCODE_DATA, 0);
		6874	I915_WRITE(GEN6_PCODE_MAILBOX,
		6875	GEN6_PCODE_READY \|
		6876	GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
		6877	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		6878	500))
		6879	DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
		6880
		6881	min_freq = (rp_state_cap & 0xff0000) >> 16;
		6882	max_freq = rp_state_cap & 0xff;
		6883	cur_freq = (gt_perf_status & 0xff00) >> 8;
		6884
		6885	/* Check for overclock support */
		6886	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		6887	500))
		6888	DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
		6889	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
		6890	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
		6891	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		6892	500))
		6893	DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
		6894	if (pcu_mbox & (1<<31)) { /* OC supported */
		6895	max_freq = pcu_mbox & 0xff;
		6896	DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
		6897	}
		6898
		6899	/* In units of 100MHz */
		6900	dev_priv->max_delay = max_freq;
		6901	dev_priv->min_delay = min_freq;
		6902	dev_priv->cur_delay = cur_freq;
		6903
		6904	/* requires MSI enabled */
		6905	I915_WRITE(GEN6_PMIER,
		6906	GEN6_PM_MBOX_EVENT \|
		6907	GEN6_PM_THERMAL_EVENT \|
		6908	GEN6_PM_RP_DOWN_TIMEOUT \|
		6909	GEN6_PM_RP_UP_THRESHOLD \|
		6910	GEN6_PM_RP_DOWN_THRESHOLD \|
		6911	GEN6_PM_RP_UP_EI_EXPIRED \|
		6912	GEN6_PM_RP_DOWN_EI_EXPIRED);
		6913	// spin_lock_irq(&dev_priv->rps_lock);
		6914	// WARN_ON(dev_priv->pm_iir != 0);
		6915	I915_WRITE(GEN6_PMIMR, 0);
		6916	// spin_unlock_irq(&dev_priv->rps_lock);
		6917	/* enable all PM interrupts */
		6918	I915_WRITE(GEN6_PMINTRMSK, 0);
		6919
		6920	gen6_gt_force_wake_put(dev_priv);
		6921	mutex_unlock(&dev_priv->dev->struct_mutex);
		6922	}
		6923
		6924	void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
		6925	{
		6926	int min_freq = 15;
		6927	int gpu_freq, ia_freq, max_ia_freq;
		6928	int scaling_factor = 180;
		6929
		6930	// max_ia_freq = cpufreq_quick_get_max(0);
		6931	/*
		6932	* Default to measured freq if none found, PCU will ensure we don't go
		6933	* over
		6934	*/
		6935	// if (!max_ia_freq)
		6936	max_ia_freq = 3000000; //tsc_khz;
		6937
		6938	/* Convert from kHz to MHz */
		6939	max_ia_freq /= 1000;
		6940
		6941	mutex_lock(&dev_priv->dev->struct_mutex);
		6942
		6943	/*
		6944	* For each potential GPU frequency, load a ring frequency we'd like
		6945	* to use for memory access. We do this by specifying the IA frequency
		6946	* the PCU should use as a reference to determine the ring frequency.
		6947	*/
		6948	for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
		6949	gpu_freq--) {
		6950	int diff = dev_priv->max_delay - gpu_freq;
		6951
		6952	/*
		6953	* For GPU frequencies less than 750MHz, just use the lowest
		6954	* ring freq.
		6955	*/
		6956	if (gpu_freq < min_freq)
		6957	ia_freq = 800;
		6958	else
		6959	ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
		6960	ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
		6961
		6962	I915_WRITE(GEN6_PCODE_DATA,
		6963	(ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) \|
		6964	gpu_freq);
		6965	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY \|
		6966	GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
		6967	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
		6968	GEN6_PCODE_READY) == 0, 10)) {
		6969	DRM_ERROR("pcode write of freq table timed out\n");
		6970	continue;
		6971	}
		6972	}
		6973
		6974	mutex_unlock(&dev_priv->dev->struct_mutex);
		6975	}
		6976
2327	Serge	6977	static void ironlake_init_clock_gating(struct drm_device *dev)
		6978	{
		6979	struct drm_i915_private *dev_priv = dev->dev_private;
		6980	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
		6981
		6982	/* Required for FBC */
		6983	dspclk_gate \|= DPFCUNIT_CLOCK_GATE_DISABLE \|
		6984	DPFCRUNIT_CLOCK_GATE_DISABLE \|
		6985	DPFDUNIT_CLOCK_GATE_DISABLE;
		6986	/* Required for CxSR */
		6987	dspclk_gate \|= DPARBUNIT_CLOCK_GATE_DISABLE;
		6988
		6989	I915_WRITE(PCH_3DCGDIS0,
		6990	MARIUNIT_CLOCK_GATE_DISABLE \|
		6991	SVSMUNIT_CLOCK_GATE_DISABLE);
		6992	I915_WRITE(PCH_3DCGDIS1,
		6993	VFMUNIT_CLOCK_GATE_DISABLE);
		6994
		6995	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
		6996
		6997	/*
		6998	* According to the spec the following bits should be set in
		6999	* order to enable memory self-refresh
		7000	* The bit 22/21 of 0x42004
		7001	* The bit 5 of 0x42020
		7002	* The bit 15 of 0x45000
		7003	*/
		7004	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7005	(I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7006	ILK_DPARB_GATE \| ILK_VSDPFD_FULL));
		7007	I915_WRITE(ILK_DSPCLK_GATE,
		7008	(I915_READ(ILK_DSPCLK_GATE) \|
		7009	ILK_DPARB_CLK_GATE));
		7010	I915_WRITE(DISP_ARB_CTL,
		7011	(I915_READ(DISP_ARB_CTL) \|
		7012	DISP_FBC_WM_DIS));
		7013	I915_WRITE(WM3_LP_ILK, 0);
		7014	I915_WRITE(WM2_LP_ILK, 0);
		7015	I915_WRITE(WM1_LP_ILK, 0);
		7016
		7017	/*
		7018	* Based on the document from hardware guys the following bits
		7019	* should be set unconditionally in order to enable FBC.
		7020	* The bit 22 of 0x42000
		7021	* The bit 22 of 0x42004
		7022	* The bit 7,8,9 of 0x42020.
		7023	*/
		7024	if (IS_IRONLAKE_M(dev)) {
		7025	I915_WRITE(ILK_DISPLAY_CHICKEN1,
		7026	I915_READ(ILK_DISPLAY_CHICKEN1) \|
		7027	ILK_FBCQ_DIS);
		7028	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7029	I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7030	ILK_DPARB_GATE);
		7031	I915_WRITE(ILK_DSPCLK_GATE,
		7032	I915_READ(ILK_DSPCLK_GATE) \|
		7033	ILK_DPFC_DIS1 \|
		7034	ILK_DPFC_DIS2 \|
		7035	ILK_CLK_FBC);
		7036	}
		7037
		7038	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7039	I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7040	ILK_ELPIN_409_SELECT);
		7041	I915_WRITE(_3D_CHICKEN2,
		7042	_3D_CHICKEN2_WM_READ_PIPELINED << 16 \|
		7043	_3D_CHICKEN2_WM_READ_PIPELINED);
		7044	}
		7045
		7046	static void gen6_init_clock_gating(struct drm_device *dev)
		7047	{
		7048	struct drm_i915_private *dev_priv = dev->dev_private;
		7049	int pipe;
		7050	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
		7051
		7052	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
		7053
		7054	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7055	I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7056	ILK_ELPIN_409_SELECT);
		7057
		7058	I915_WRITE(WM3_LP_ILK, 0);
		7059	I915_WRITE(WM2_LP_ILK, 0);
		7060	I915_WRITE(WM1_LP_ILK, 0);
		7061
		7062	/*
		7063	* According to the spec the following bits should be
		7064	* set in order to enable memory self-refresh and fbc:
		7065	* The bit21 and bit22 of 0x42000
		7066	* The bit21 and bit22 of 0x42004
		7067	* The bit5 and bit7 of 0x42020
		7068	* The bit14 of 0x70180
		7069	* The bit14 of 0x71180
		7070	*/
		7071	I915_WRITE(ILK_DISPLAY_CHICKEN1,
		7072	I915_READ(ILK_DISPLAY_CHICKEN1) \|
		7073	ILK_FBCQ_DIS \| ILK_PABSTRETCH_DIS);
		7074	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7075	I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7076	ILK_DPARB_GATE \| ILK_VSDPFD_FULL);
		7077	I915_WRITE(ILK_DSPCLK_GATE,
		7078	I915_READ(ILK_DSPCLK_GATE) \|
		7079	ILK_DPARB_CLK_GATE \|
		7080	ILK_DPFD_CLK_GATE);
		7081
		7082	for_each_pipe(pipe) {
		7083	I915_WRITE(DSPCNTR(pipe),
		7084	I915_READ(DSPCNTR(pipe)) \|
		7085	DISPPLANE_TRICKLE_FEED_DISABLE);
		7086	intel_flush_display_plane(dev_priv, pipe);
		7087	}
		7088	}
		7089
		7090	static void ivybridge_init_clock_gating(struct drm_device *dev)
		7091	{
		7092	struct drm_i915_private *dev_priv = dev->dev_private;
		7093	int pipe;
		7094	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
		7095
		7096	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
		7097
		7098	I915_WRITE(WM3_LP_ILK, 0);
		7099	I915_WRITE(WM2_LP_ILK, 0);
		7100	I915_WRITE(WM1_LP_ILK, 0);
		7101
		7102	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
		7103
		7104	for_each_pipe(pipe) {
		7105	I915_WRITE(DSPCNTR(pipe),
		7106	I915_READ(DSPCNTR(pipe)) \|
		7107	DISPPLANE_TRICKLE_FEED_DISABLE);
		7108	intel_flush_display_plane(dev_priv, pipe);
		7109	}
		7110	}
		7111
		7112	static void g4x_init_clock_gating(struct drm_device *dev)
		7113	{
		7114	struct drm_i915_private *dev_priv = dev->dev_private;
		7115	uint32_t dspclk_gate;
		7116
		7117	I915_WRITE(RENCLK_GATE_D1, 0);
		7118	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE \|
		7119	GS_UNIT_CLOCK_GATE_DISABLE \|
		7120	CL_UNIT_CLOCK_GATE_DISABLE);
		7121	I915_WRITE(RAMCLK_GATE_D, 0);
		7122	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE \|
		7123	OVRUNIT_CLOCK_GATE_DISABLE \|
		7124	OVCUNIT_CLOCK_GATE_DISABLE;
		7125	if (IS_GM45(dev))
		7126	dspclk_gate \|= DSSUNIT_CLOCK_GATE_DISABLE;
		7127	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
		7128	}
		7129
		7130	static void crestline_init_clock_gating(struct drm_device *dev)
		7131	{
		7132	struct drm_i915_private *dev_priv = dev->dev_private;
		7133
		7134	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
		7135	I915_WRITE(RENCLK_GATE_D2, 0);
		7136	I915_WRITE(DSPCLK_GATE_D, 0);
		7137	I915_WRITE(RAMCLK_GATE_D, 0);
		7138	I915_WRITE16(DEUC, 0);
		7139	}
		7140
		7141	static void broadwater_init_clock_gating(struct drm_device *dev)
		7142	{
		7143	struct drm_i915_private *dev_priv = dev->dev_private;
		7144
		7145	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE \|
		7146	I965_RCC_CLOCK_GATE_DISABLE \|
		7147	I965_RCPB_CLOCK_GATE_DISABLE \|
		7148	I965_ISC_CLOCK_GATE_DISABLE \|
		7149	I965_FBC_CLOCK_GATE_DISABLE);
		7150	I915_WRITE(RENCLK_GATE_D2, 0);
		7151	}
		7152
		7153	static void gen3_init_clock_gating(struct drm_device *dev)
		7154	{
		7155	struct drm_i915_private *dev_priv = dev->dev_private;
		7156	u32 dstate = I915_READ(D_STATE);
		7157
		7158	dstate \|= DSTATE_PLL_D3_OFF \| DSTATE_GFX_CLOCK_GATING \|
		7159	DSTATE_DOT_CLOCK_GATING;
		7160	I915_WRITE(D_STATE, dstate);
		7161	}
		7162
		7163	static void i85x_init_clock_gating(struct drm_device *dev)
		7164	{
		7165	struct drm_i915_private *dev_priv = dev->dev_private;
		7166
		7167	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
		7168	}
		7169
		7170	static void i830_init_clock_gating(struct drm_device *dev)
		7171	{
		7172	struct drm_i915_private *dev_priv = dev->dev_private;
		7173
		7174	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
		7175	}
		7176
		7177	static void ibx_init_clock_gating(struct drm_device *dev)
		7178	{
		7179	struct drm_i915_private *dev_priv = dev->dev_private;
		7180
		7181	/*
		7182	* On Ibex Peak and Cougar Point, we need to disable clock
		7183	* gating for the panel power sequencer or it will fail to
		7184	* start up when no ports are active.
		7185	*/
		7186	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
		7187	}
		7188
		7189	static void cpt_init_clock_gating(struct drm_device *dev)
		7190	{
		7191	struct drm_i915_private *dev_priv = dev->dev_private;
		7192	int pipe;
		7193
		7194	/*
		7195	* On Ibex Peak and Cougar Point, we need to disable clock
		7196	* gating for the panel power sequencer or it will fail to
		7197	* start up when no ports are active.
		7198	*/
		7199	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
		7200	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) \|
		7201	DPLS_EDP_PPS_FIX_DIS);
		7202	/* Without this, mode sets may fail silently on FDI */
		7203	for_each_pipe(pipe)
		7204	I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
		7205	}
		7206
2332	Serge	7207	static void ironlake_teardown_rc6(struct drm_device *dev)
		7208	{
		7209	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	7210
2332	Serge	7211	if (dev_priv->renderctx) {
		7212	// i915_gem_object_unpin(dev_priv->renderctx);
		7213	// drm_gem_object_unreference(&dev_priv->renderctx->base);
		7214	dev_priv->renderctx = NULL;
		7215	}
2327	Serge	7216
2332	Serge	7217	if (dev_priv->pwrctx) {
		7218	// i915_gem_object_unpin(dev_priv->pwrctx);
		7219	// drm_gem_object_unreference(&dev_priv->pwrctx->base);
		7220	dev_priv->pwrctx = NULL;
		7221	}
		7222	}
2327	Serge	7223
2330	Serge	7224
2332	Serge	7225
		7226
		7227
		7228
		7229
		7230	static int ironlake_setup_rc6(struct drm_device *dev)
		7231	{
		7232	struct drm_i915_private *dev_priv = dev->dev_private;
		7233
		7234	if (dev_priv->renderctx == NULL)
		7235	// dev_priv->renderctx = intel_alloc_context_page(dev);
		7236	if (!dev_priv->renderctx)
		7237	return -ENOMEM;
		7238
		7239	if (dev_priv->pwrctx == NULL)
		7240	// dev_priv->pwrctx = intel_alloc_context_page(dev);
		7241	if (!dev_priv->pwrctx) {
		7242	ironlake_teardown_rc6(dev);
		7243	return -ENOMEM;
		7244	}
		7245
		7246	return 0;
		7247	}
		7248
		7249	void ironlake_enable_rc6(struct drm_device *dev)
		7250	{
		7251	struct drm_i915_private *dev_priv = dev->dev_private;
		7252	int ret;
		7253
		7254	/* rc6 disabled by default due to repeated reports of hanging during
		7255	* boot and resume.
		7256	*/
		7257	if (!i915_enable_rc6)
		7258	return;
		7259
		7260	mutex_lock(&dev->struct_mutex);
		7261	ret = ironlake_setup_rc6(dev);
		7262	if (ret) {
		7263	mutex_unlock(&dev->struct_mutex);
		7264	return;
		7265	}
		7266
		7267	/*
		7268	* GPU can automatically power down the render unit if given a page
		7269	* to save state.
		7270	*/
		7271	#if 0
		7272	ret = BEGIN_LP_RING(6);
		7273	if (ret) {
		7274	ironlake_teardown_rc6(dev);
		7275	mutex_unlock(&dev->struct_mutex);
		7276	return;
		7277	}
		7278
		7279	OUT_RING(MI_SUSPEND_FLUSH \| MI_SUSPEND_FLUSH_EN);
		7280	OUT_RING(MI_SET_CONTEXT);
		7281	OUT_RING(dev_priv->renderctx->gtt_offset \|
		7282	MI_MM_SPACE_GTT \|
		7283	MI_SAVE_EXT_STATE_EN \|
		7284	MI_RESTORE_EXT_STATE_EN \|
		7285	MI_RESTORE_INHIBIT);
		7286	OUT_RING(MI_SUSPEND_FLUSH);
		7287	OUT_RING(MI_NOOP);
		7288	OUT_RING(MI_FLUSH);
		7289	ADVANCE_LP_RING();
		7290
		7291	/*
		7292	* Wait for the command parser to advance past MI_SET_CONTEXT. The HW
		7293	* does an implicit flush, combined with MI_FLUSH above, it should be
		7294	* safe to assume that renderctx is valid
		7295	*/
		7296	ret = intel_wait_ring_idle(LP_RING(dev_priv));
		7297	if (ret) {
		7298	DRM_ERROR("failed to enable ironlake power power savings\n");
		7299	ironlake_teardown_rc6(dev);
		7300	mutex_unlock(&dev->struct_mutex);
		7301	return;
		7302	}
		7303	#endif
		7304
		7305	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset \| PWRCTX_EN);
		7306	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
		7307	mutex_unlock(&dev->struct_mutex);
		7308	}
		7309
2330	Serge	7310	void intel_init_clock_gating(struct drm_device *dev)
		7311	{
		7312	struct drm_i915_private *dev_priv = dev->dev_private;
		7313
		7314	dev_priv->display.init_clock_gating(dev);
		7315
		7316	if (dev_priv->display.init_pch_clock_gating)
		7317	dev_priv->display.init_pch_clock_gating(dev);
		7318	}
		7319
2327	Serge	7320	/* Set up chip specific display functions */
		7321	static void intel_init_display(struct drm_device *dev)
		7322	{
		7323	struct drm_i915_private *dev_priv = dev->dev_private;
		7324
		7325	/* We always want a DPMS function */
		7326	if (HAS_PCH_SPLIT(dev)) {
		7327	dev_priv->display.dpms = ironlake_crtc_dpms;
		7328	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		7329	dev_priv->display.update_plane = ironlake_update_plane;
		7330	} else {
		7331	dev_priv->display.dpms = i9xx_crtc_dpms;
		7332	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		7333	dev_priv->display.update_plane = i9xx_update_plane;
		7334	}
		7335
		7336	if (I915_HAS_FBC(dev)) {
		7337	if (HAS_PCH_SPLIT(dev)) {
		7338	dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
		7339	dev_priv->display.enable_fbc = ironlake_enable_fbc;
		7340	dev_priv->display.disable_fbc = ironlake_disable_fbc;
		7341	} else if (IS_GM45(dev)) {
		7342	dev_priv->display.fbc_enabled = g4x_fbc_enabled;
		7343	dev_priv->display.enable_fbc = g4x_enable_fbc;
		7344	dev_priv->display.disable_fbc = g4x_disable_fbc;
		7345	} else if (IS_CRESTLINE(dev)) {
		7346	dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
		7347	dev_priv->display.enable_fbc = i8xx_enable_fbc;
		7348	dev_priv->display.disable_fbc = i8xx_disable_fbc;
		7349	}
		7350	/* 855GM needs testing */
		7351	}
		7352
		7353	/* Returns the core display clock speed */
		7354	if (IS_I945G(dev) \|\| (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
		7355	dev_priv->display.get_display_clock_speed =
		7356	i945_get_display_clock_speed;
		7357	else if (IS_I915G(dev))
		7358	dev_priv->display.get_display_clock_speed =
		7359	i915_get_display_clock_speed;
		7360	else if (IS_I945GM(dev) \|\| IS_845G(dev) \|\| IS_PINEVIEW_M(dev))
		7361	dev_priv->display.get_display_clock_speed =
		7362	i9xx_misc_get_display_clock_speed;
		7363	else if (IS_I915GM(dev))
		7364	dev_priv->display.get_display_clock_speed =
		7365	i915gm_get_display_clock_speed;
		7366	else if (IS_I865G(dev))
		7367	dev_priv->display.get_display_clock_speed =
		7368	i865_get_display_clock_speed;
		7369	else if (IS_I85X(dev))
		7370	dev_priv->display.get_display_clock_speed =
		7371	i855_get_display_clock_speed;
		7372	else /* 852, 830 */
		7373	dev_priv->display.get_display_clock_speed =
		7374	i830_get_display_clock_speed;
		7375
		7376	/* For FIFO watermark updates */
		7377	if (HAS_PCH_SPLIT(dev)) {
		7378	if (HAS_PCH_IBX(dev))
		7379	dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
		7380	else if (HAS_PCH_CPT(dev))
		7381	dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
		7382
		7383	if (IS_GEN5(dev)) {
		7384	if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
		7385	dev_priv->display.update_wm = ironlake_update_wm;
		7386	else {
		7387	DRM_DEBUG_KMS("Failed to get proper latency. "
		7388	"Disable CxSR\n");
		7389	dev_priv->display.update_wm = NULL;
		7390	}
		7391	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		7392	dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
		7393	} else if (IS_GEN6(dev)) {
		7394	if (SNB_READ_WM0_LATENCY()) {
		7395	dev_priv->display.update_wm = sandybridge_update_wm;
		7396	} else {
		7397	DRM_DEBUG_KMS("Failed to read display plane latency. "
		7398	"Disable CxSR\n");
		7399	dev_priv->display.update_wm = NULL;
		7400	}
		7401	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		7402	dev_priv->display.init_clock_gating = gen6_init_clock_gating;
		7403	} else if (IS_IVYBRIDGE(dev)) {
		7404	/* FIXME: detect B0+ stepping and use auto training */
		7405	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		7406	if (SNB_READ_WM0_LATENCY()) {
		7407	dev_priv->display.update_wm = sandybridge_update_wm;
		7408	} else {
		7409	DRM_DEBUG_KMS("Failed to read display plane latency. "
		7410	"Disable CxSR\n");
		7411	dev_priv->display.update_wm = NULL;
		7412	}
		7413	dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
		7414
		7415	} else
		7416	dev_priv->display.update_wm = NULL;
		7417	} else if (IS_PINEVIEW(dev)) {
		7418	if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
		7419	dev_priv->is_ddr3,
		7420	dev_priv->fsb_freq,
		7421	dev_priv->mem_freq)) {
		7422	DRM_INFO("failed to find known CxSR latency "
		7423	"(found ddr%s fsb freq %d, mem freq %d), "
		7424	"disabling CxSR\n",
		7425	(dev_priv->is_ddr3 == 1) ? "3": "2",
		7426	dev_priv->fsb_freq, dev_priv->mem_freq);
		7427	/* Disable CxSR and never update its watermark again */
		7428	pineview_disable_cxsr(dev);
		7429	dev_priv->display.update_wm = NULL;
		7430	} else
		7431	dev_priv->display.update_wm = pineview_update_wm;
		7432	dev_priv->display.init_clock_gating = gen3_init_clock_gating;
		7433	} else if (IS_G4X(dev)) {
		7434	dev_priv->display.update_wm = g4x_update_wm;
		7435	dev_priv->display.init_clock_gating = g4x_init_clock_gating;
		7436	} else if (IS_GEN4(dev)) {
		7437	dev_priv->display.update_wm = i965_update_wm;
		7438	if (IS_CRESTLINE(dev))
		7439	dev_priv->display.init_clock_gating = crestline_init_clock_gating;
		7440	else if (IS_BROADWATER(dev))
		7441	dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
		7442	} else if (IS_GEN3(dev)) {
		7443	dev_priv->display.update_wm = i9xx_update_wm;
		7444	dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
		7445	dev_priv->display.init_clock_gating = gen3_init_clock_gating;
		7446	} else if (IS_I865G(dev)) {
		7447	dev_priv->display.update_wm = i830_update_wm;
		7448	dev_priv->display.init_clock_gating = i85x_init_clock_gating;
		7449	dev_priv->display.get_fifo_size = i830_get_fifo_size;
		7450	} else if (IS_I85X(dev)) {
		7451	dev_priv->display.update_wm = i9xx_update_wm;
		7452	dev_priv->display.get_fifo_size = i85x_get_fifo_size;
		7453	dev_priv->display.init_clock_gating = i85x_init_clock_gating;
		7454	} else {
		7455	dev_priv->display.update_wm = i830_update_wm;
		7456	dev_priv->display.init_clock_gating = i830_init_clock_gating;
		7457	if (IS_845G(dev))
		7458	dev_priv->display.get_fifo_size = i845_get_fifo_size;
		7459	else
		7460	dev_priv->display.get_fifo_size = i830_get_fifo_size;
		7461	}
		7462
		7463	/* Default just returns -ENODEV to indicate unsupported */
		7464	// dev_priv->display.queue_flip = intel_default_queue_flip;
		7465
		7466	#if 0
		7467	switch (INTEL_INFO(dev)->gen) {
		7468	case 2:
		7469	dev_priv->display.queue_flip = intel_gen2_queue_flip;
		7470	break;
		7471
		7472	case 3:
		7473	dev_priv->display.queue_flip = intel_gen3_queue_flip;
		7474	break;
		7475
		7476	case 4:
		7477	case 5:
		7478	dev_priv->display.queue_flip = intel_gen4_queue_flip;
		7479	break;
		7480
		7481	case 6:
		7482	dev_priv->display.queue_flip = intel_gen6_queue_flip;
		7483	break;
		7484	case 7:
		7485	dev_priv->display.queue_flip = intel_gen7_queue_flip;
		7486	break;
		7487	}
		7488	#endif
		7489	}
		7490
		7491	/*
		7492	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		7493	* resume, or other times. This quirk makes sure that's the case for
		7494	* affected systems.
		7495	*/
		7496	static void quirk_pipea_force (struct drm_device *dev)
		7497	{
		7498	struct drm_i915_private *dev_priv = dev->dev_private;
		7499
		7500	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		7501	DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
		7502	}
		7503
		7504	/*
		7505	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		7506	*/
		7507	static void quirk_ssc_force_disable(struct drm_device *dev)
		7508	{
		7509	struct drm_i915_private *dev_priv = dev->dev_private;
		7510	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		7511	}
		7512
		7513	struct intel_quirk {
		7514	int device;
		7515	int subsystem_vendor;
		7516	int subsystem_device;
		7517	void (hook)(struct drm_device dev);
		7518	};
		7519
		7520	struct intel_quirk intel_quirks[] = {
		7521	/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
		7522	{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
		7523	/* HP Mini needs pipe A force quirk (LP: #322104) */
		7524	{ 0x27ae,0x103c, 0x361a, quirk_pipea_force },
		7525
		7526	/* Thinkpad R31 needs pipe A force quirk */
		7527	{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },
		7528	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		7529	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
		7530
		7531	/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
		7532	{ 0x3577, 0x1014, 0x0513, quirk_pipea_force },
		7533	/* ThinkPad X40 needs pipe A force quirk */
		7534
		7535	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		7536	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
		7537
		7538	/* 855 & before need to leave pipe A & dpll A up */
		7539	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		7540	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		7541
		7542	/* Lenovo U160 cannot use SSC on LVDS */
		7543	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
		7544
		7545	/* Sony Vaio Y cannot use SSC on LVDS */
		7546	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
		7547	};
		7548
		7549	static void intel_init_quirks(struct drm_device *dev)
		7550	{
		7551	struct pci_dev *d = dev->pdev;
		7552	int i;
		7553
		7554	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		7555	struct intel_quirk *q = &intel_quirks[i];
		7556
		7557	if (d->device == q->device &&
		7558	(d->subsystem_vendor == q->subsystem_vendor \|\|
		7559	q->subsystem_vendor == PCI_ANY_ID) &&
		7560	(d->subsystem_device == q->subsystem_device \|\|
		7561	q->subsystem_device == PCI_ANY_ID))
		7562	q->hook(dev);
		7563	}
		7564	}
		7565
2330	Serge	7566	/* Disable the VGA plane that we never use */
		7567	static void i915_disable_vga(struct drm_device *dev)
		7568	{
		7569	struct drm_i915_private *dev_priv = dev->dev_private;
		7570	u8 sr1;
		7571	u32 vga_reg;
2327	Serge	7572
2330	Serge	7573	if (HAS_PCH_SPLIT(dev))
		7574	vga_reg = CPU_VGACNTRL;
		7575	else
		7576	vga_reg = VGACNTRL;
		7577
		7578	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		7579	out8(VGA_SR_INDEX, 1);
		7580	sr1 = in8(VGA_SR_DATA);
		7581	out8(VGA_SR_DATA,sr1 \| 1<<5);
		7582	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		7583	udelay(300);
		7584
		7585	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		7586	POSTING_READ(vga_reg);
		7587	}
		7588
2327	Serge	7589	void intel_modeset_init(struct drm_device *dev)
		7590	{
		7591	struct drm_i915_private *dev_priv = dev->dev_private;
		7592	int i;
		7593
		7594	drm_mode_config_init(dev);
		7595
		7596	dev->mode_config.min_width = 0;
		7597	dev->mode_config.min_height = 0;
		7598
		7599	dev->mode_config.funcs = (void *)&intel_mode_funcs;
		7600
		7601	intel_init_quirks(dev);
		7602
		7603	intel_init_display(dev);
		7604
		7605	if (IS_GEN2(dev)) {
		7606	dev->mode_config.max_width = 2048;
		7607	dev->mode_config.max_height = 2048;
		7608	} else if (IS_GEN3(dev)) {
		7609	dev->mode_config.max_width = 4096;
		7610	dev->mode_config.max_height = 4096;
		7611	} else {
		7612	dev->mode_config.max_width = 8192;
		7613	dev->mode_config.max_height = 8192;
		7614	}
		7615	dev->mode_config.fb_base = get_bus_addr();
		7616
		7617	DRM_DEBUG_KMS("%d display pipe%s available.\n",
		7618	dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
		7619
		7620	for (i = 0; i < dev_priv->num_pipe; i++) {
		7621	intel_crtc_init(dev, i);
		7622	}
		7623
		7624	/* Just disable it once at startup */
		7625	i915_disable_vga(dev);
		7626	intel_setup_outputs(dev);
		7627
		7628	intel_init_clock_gating(dev);
		7629
		7630	if (IS_IRONLAKE_M(dev)) {
		7631	ironlake_enable_drps(dev);
		7632	intel_init_emon(dev);
		7633	}
		7634
		7635	if (IS_GEN6(dev) \|\| IS_GEN7(dev)) {
		7636	gen6_enable_rps(dev_priv);
		7637	gen6_update_ring_freq(dev_priv);
		7638	}
		7639
2332	Serge	7640	// INIT_WORK(&dev_priv->idle_work, intel_idle_update);
		7641	// setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
		7642	// (unsigned long)dev);
2330	Serge	7643	}
2327	Serge	7644
2332	Serge	7645	void intel_modeset_gem_init(struct drm_device *dev)
		7646	{
		7647	if (IS_IRONLAKE_M(dev))
		7648	ironlake_enable_rc6(dev);
2330	Serge	7649
2332	Serge	7650	// intel_setup_overlay(dev);
		7651	}
		7652
		7653
2330	Serge	7654	/*
		7655	* Return which encoder is currently attached for connector.
		7656	*/
		7657	struct drm_encoder intel_best_encoder(struct drm_connector connector)
		7658	{
		7659	return &intel_attached_encoder(connector)->base;
2327	Serge	7660	}
		7661
2330	Serge	7662	void intel_connector_attach_encoder(struct intel_connector *connector,
		7663	struct intel_encoder *encoder)
		7664	{
		7665	connector->encoder = encoder;
		7666	drm_mode_connector_attach_encoder(&connector->base,
		7667	&encoder->base);
		7668	}
2327	Serge	7669
2330	Serge	7670

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c @ 6283 – Rev 2335