WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_ddi.c

Rev	Author	Line No.	Line
3031	serge	1	/*
		2	* Copyright © 2012 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eugeni Dodonov
		25	*
		26	*/
		27
		28	#include "i915_drv.h"
		29	#include "intel_drv.h"
		30
		31	/* HDMI/DVI modes ignore everything but the last 2 items. So we share
		32	* them for both DP and FDI transports, allowing those ports to
		33	* automatically adapt to HDMI connections as well
		34	*/
		35	static const u32 hsw_ddi_translations_dp[] = {
		36	0x00FFFFFF, 0x0006000E, /* DP parameters */
		37	0x00D75FFF, 0x0005000A,
		38	0x00C30FFF, 0x00040006,
		39	0x80AAAFFF, 0x000B0000,
		40	0x00FFFFFF, 0x0005000A,
		41	0x00D75FFF, 0x000C0004,
		42	0x80C30FFF, 0x000B0000,
		43	0x00FFFFFF, 0x00040006,
		44	0x80D75FFF, 0x000B0000,
		45	};
		46
		47	static const u32 hsw_ddi_translations_fdi[] = {
		48	0x00FFFFFF, 0x0007000E, /* FDI parameters */
		49	0x00D75FFF, 0x000F000A,
		50	0x00C30FFF, 0x00060006,
		51	0x00AAAFFF, 0x001E0000,
		52	0x00FFFFFF, 0x000F000A,
		53	0x00D75FFF, 0x00160004,
		54	0x00C30FFF, 0x001E0000,
		55	0x00FFFFFF, 0x00060006,
		56	0x00D75FFF, 0x001E0000,
		57	};
		58
4560	Serge	59	static const u32 hsw_ddi_translations_hdmi[] = {
		60	/* Idx NT mV diff T mV diff db */
		61	0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
		62	0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
		63	0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
		64	0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
		65	0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
		66	0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
		67	0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
		68	0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
		69	0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
		70	0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
		71	0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
		72	0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
		73	};
		74
		75	static const u32 bdw_ddi_translations_edp[] = {
		76	0x00FFFFFF, 0x00000012, /* eDP parameters */
		77	0x00EBAFFF, 0x00020011,
		78	0x00C71FFF, 0x0006000F,
		79	0x00FFFFFF, 0x00020011,
		80	0x00DB6FFF, 0x0005000F,
		81	0x00BEEFFF, 0x000A000C,
		82	0x00FFFFFF, 0x0005000F,
		83	0x00DB6FFF, 0x000A000C,
		84	0x00FFFFFF, 0x000A000C,
		85	0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
		86	};
		87
		88	static const u32 bdw_ddi_translations_dp[] = {
		89	0x00FFFFFF, 0x0007000E, /* DP parameters */
		90	0x00D75FFF, 0x000E000A,
		91	0x00BEFFFF, 0x00140006,
		92	0x00FFFFFF, 0x000E000A,
		93	0x00D75FFF, 0x00180004,
		94	0x80CB2FFF, 0x001B0002,
		95	0x00F7DFFF, 0x00180004,
		96	0x80D75FFF, 0x001B0002,
		97	0x80FFFFFF, 0x001B0002,
		98	0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
		99	};
		100
		101	static const u32 bdw_ddi_translations_fdi[] = {
		102	0x00FFFFFF, 0x0001000E, /* FDI parameters */
		103	0x00D75FFF, 0x0004000A,
		104	0x00C30FFF, 0x00070006,
		105	0x00AAAFFF, 0x000C0000,
		106	0x00FFFFFF, 0x0004000A,
		107	0x00D75FFF, 0x00090004,
		108	0x00C30FFF, 0x000C0000,
		109	0x00FFFFFF, 0x00070006,
		110	0x00D75FFF, 0x000C0000,
		111	0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
		112	};
		113
		114	enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
3243	Serge	115	{
		116	struct drm_encoder *encoder = &intel_encoder->base;
		117	int type = intel_encoder->type;
		118
		119	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP \|\|
		120	type == INTEL_OUTPUT_HDMI \|\| type == INTEL_OUTPUT_UNKNOWN) {
		121	struct intel_digital_port *intel_dig_port =
		122	enc_to_dig_port(encoder);
		123	return intel_dig_port->port;
		124
		125	} else if (type == INTEL_OUTPUT_ANALOG) {
		126	return PORT_E;
		127
		128	} else {
		129	DRM_ERROR("Invalid DDI encoder type %d\n", type);
		130	BUG();
		131	}
		132	}
		133
4560	Serge	134	/*
		135	* Starting with Haswell, DDI port buffers must be programmed with correct
		136	* values in advance. The buffer values are different for FDI and DP modes,
3031	serge	137	* but the HDMI/DVI fields are shared among those. So we program the DDI
		138	* in either FDI or DP modes only, as HDMI connections will work with both
		139	* of those
		140	*/
4104	Serge	141	static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
3031	serge	142	{
		143	struct drm_i915_private *dev_priv = dev->dev_private;
		144	u32 reg;
		145	int i;
4560	Serge	146	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
		147	const u32 *ddi_translations_fdi;
		148	const u32 *ddi_translations_dp;
		149	const u32 *ddi_translations_edp;
		150	const u32 *ddi_translations;
3031	serge	151
4560	Serge	152	if (IS_BROADWELL(dev)) {
		153	ddi_translations_fdi = bdw_ddi_translations_fdi;
		154	ddi_translations_dp = bdw_ddi_translations_dp;
		155	ddi_translations_edp = bdw_ddi_translations_edp;
		156	} else if (IS_HASWELL(dev)) {
		157	ddi_translations_fdi = hsw_ddi_translations_fdi;
		158	ddi_translations_dp = hsw_ddi_translations_dp;
		159	ddi_translations_edp = hsw_ddi_translations_dp;
		160	} else {
		161	WARN(1, "ddi translation table missing\n");
		162	ddi_translations_edp = bdw_ddi_translations_dp;
		163	ddi_translations_fdi = bdw_ddi_translations_fdi;
		164	ddi_translations_dp = bdw_ddi_translations_dp;
		165	}
		166
		167	switch (port) {
		168	case PORT_A:
		169	ddi_translations = ddi_translations_edp;
		170	break;
		171	case PORT_B:
		172	case PORT_C:
		173	ddi_translations = ddi_translations_dp;
		174	break;
		175	case PORT_D:
		176	if (intel_dp_is_edp(dev, PORT_D))
		177	ddi_translations = ddi_translations_edp;
		178	else
		179	ddi_translations = ddi_translations_dp;
		180	break;
		181	case PORT_E:
		182	ddi_translations = ddi_translations_fdi;
		183	break;
		184	default:
		185	BUG();
		186	}
		187
4104	Serge	188	for (i = 0, reg = DDI_BUF_TRANS(port);
		189	i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
3031	serge	190	I915_WRITE(reg, ddi_translations[i]);
		191	reg += 4;
		192	}
4560	Serge	193	/* Entry 9 is for HDMI: */
		194	for (i = 0; i < 2; i++) {
		195	I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
		196	reg += 4;
		197	}
3031	serge	198	}
		199
		200	/* Program DDI buffers translations for DP. By default, program ports A-D in DP
		201	* mode and port E for FDI.
		202	*/
		203	void intel_prepare_ddi(struct drm_device *dev)
		204	{
		205	int port;
		206
3480	Serge	207	if (!HAS_DDI(dev))
		208	return;
		209
4104	Serge	210	for (port = PORT_A; port <= PORT_E; port++)
		211	intel_prepare_ddi_buffers(dev, port);
3031	serge	212	}
		213
		214	static const long hsw_ddi_buf_ctl_values[] = {
		215	DDI_BUF_EMP_400MV_0DB_HSW,
		216	DDI_BUF_EMP_400MV_3_5DB_HSW,
		217	DDI_BUF_EMP_400MV_6DB_HSW,
		218	DDI_BUF_EMP_400MV_9_5DB_HSW,
		219	DDI_BUF_EMP_600MV_0DB_HSW,
		220	DDI_BUF_EMP_600MV_3_5DB_HSW,
		221	DDI_BUF_EMP_600MV_6DB_HSW,
		222	DDI_BUF_EMP_800MV_0DB_HSW,
		223	DDI_BUF_EMP_800MV_3_5DB_HSW
		224	};
		225
3243	Serge	226	static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
		227	enum port port)
		228	{
		229	uint32_t reg = DDI_BUF_CTL(port);
		230	int i;
3031	serge	231
3243	Serge	232	for (i = 0; i < 8; i++) {
		233	udelay(1);
		234	if (I915_READ(reg) & DDI_BUF_IS_IDLE)
		235	return;
		236	}
		237	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
		238	}
		239
3031	serge	240	/* Starting with Haswell, different DDI ports can work in FDI mode for
		241	* connection to the PCH-located connectors. For this, it is necessary to train
		242	* both the DDI port and PCH receiver for the desired DDI buffer settings.
		243	*
		244	* The recommended port to work in FDI mode is DDI E, which we use here. Also,
		245	* please note that when FDI mode is active on DDI E, it shares 2 lines with
		246	* DDI A (which is used for eDP)
		247	*/
		248
		249	void hsw_fdi_link_train(struct drm_crtc *crtc)
		250	{
		251	struct drm_device *dev = crtc->dev;
		252	struct drm_i915_private *dev_priv = dev->dev_private;
		253	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	254	u32 temp, i, rx_ctl_val;
3031	serge	255
3243	Serge	256	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
		257	* mode set "sequence for CRT port" document:
		258	* - TP1 to TP2 time with the default value
		259	* - FDI delay to 90h
4104	Serge	260	*
		261	* WaFDIAutoLinkSetTimingOverrride:hsw
3243	Serge	262	*/
		263	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) \|
		264	FDI_RX_PWRDN_LANE0_VAL(2) \|
		265	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
3031	serge	266
3243	Serge	267	/* Enable the PCH Receiver FDI PLL */
3480	Serge	268	rx_ctl_val = dev_priv->fdi_rx_config \| FDI_RX_ENHANCE_FRAME_ENABLE \|
4104	Serge	269	FDI_RX_PLL_ENABLE \|
		270	FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3243	Serge	271	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
		272	POSTING_READ(_FDI_RXA_CTL);
		273	udelay(220);
3031	serge	274
3243	Serge	275	/* Switch from Rawclk to PCDclk */
		276	rx_ctl_val \|= FDI_PCDCLK;
		277	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
3031	serge	278
3243	Serge	279	/* Configure Port Clock Select */
		280	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
		281
		282	/* Start the training iterating through available voltages and emphasis,
		283	* testing each value twice. */
		284	for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
3031	serge	285	/* Configure DP_TP_CTL with auto-training */
		286	I915_WRITE(DP_TP_CTL(PORT_E),
		287	DP_TP_CTL_FDI_AUTOTRAIN \|
		288	DP_TP_CTL_ENHANCED_FRAME_ENABLE \|
		289	DP_TP_CTL_LINK_TRAIN_PAT1 \|
		290	DP_TP_CTL_ENABLE);
		291
3480	Serge	292	/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
		293	* DDI E does not support port reversal, the functionality is
		294	* achieved on the PCH side in FDI_RX_CTL, so no need to set the
		295	* port reversal bit */
3031	serge	296	I915_WRITE(DDI_BUF_CTL(PORT_E),
		297	DDI_BUF_CTL_ENABLE \|
4104	Serge	298	((intel_crtc->config.fdi_lanes - 1) << 1) \|
3243	Serge	299	hsw_ddi_buf_ctl_values[i / 2]);
		300	POSTING_READ(DDI_BUF_CTL(PORT_E));
3031	serge	301
		302	udelay(600);
		303
3243	Serge	304	/* Program PCH FDI Receiver TU */
		305	I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
3031	serge	306
3243	Serge	307	/* Enable PCH FDI Receiver with auto-training */
		308	rx_ctl_val \|= FDI_RX_ENABLE \| FDI_LINK_TRAIN_AUTO;
		309	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
		310	POSTING_READ(_FDI_RXA_CTL);
3031	serge	311
3243	Serge	312	/* Wait for FDI receiver lane calibration */
		313	udelay(30);
		314
		315	/* Unset FDI_RX_MISC pwrdn lanes */
		316	temp = I915_READ(_FDI_RXA_MISC);
		317	temp &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
		318	I915_WRITE(_FDI_RXA_MISC, temp);
		319	POSTING_READ(_FDI_RXA_MISC);
		320
		321	/* Wait for FDI auto training time */
		322	udelay(5);
		323
3031	serge	324	temp = I915_READ(DP_TP_STATUS(PORT_E));
		325	if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
3243	Serge	326	DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
3031	serge	327
		328	/* Enable normal pixel sending for FDI */
		329	I915_WRITE(DP_TP_CTL(PORT_E),
		330	DP_TP_CTL_FDI_AUTOTRAIN \|
		331	DP_TP_CTL_LINK_TRAIN_NORMAL \|
		332	DP_TP_CTL_ENHANCED_FRAME_ENABLE \|
		333	DP_TP_CTL_ENABLE);
		334
3243	Serge	335	return;
3031	serge	336	}
		337
3243	Serge	338	temp = I915_READ(DDI_BUF_CTL(PORT_E));
		339	temp &= ~DDI_BUF_CTL_ENABLE;
		340	I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
		341	POSTING_READ(DDI_BUF_CTL(PORT_E));
3031	serge	342
3243	Serge	343	/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
		344	temp = I915_READ(DP_TP_CTL(PORT_E));
		345	temp &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		346	temp \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		347	I915_WRITE(DP_TP_CTL(PORT_E), temp);
		348	POSTING_READ(DP_TP_CTL(PORT_E));
3031	serge	349
3243	Serge	350	intel_wait_ddi_buf_idle(dev_priv, PORT_E);
		351
		352	rx_ctl_val &= ~FDI_RX_ENABLE;
		353	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
		354	POSTING_READ(_FDI_RXA_CTL);
		355
		356	/* Reset FDI_RX_MISC pwrdn lanes */
		357	temp = I915_READ(_FDI_RXA_MISC);
		358	temp &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
		359	temp \|= FDI_RX_PWRDN_LANE1_VAL(2) \| FDI_RX_PWRDN_LANE0_VAL(2);
		360	I915_WRITE(_FDI_RXA_MISC, temp);
		361	POSTING_READ(_FDI_RXA_MISC);
3031	serge	362	}
3243	Serge	363
		364	DRM_ERROR("FDI link training failed!\n");
3031	serge	365	}
		366
4104	Serge	367	static void intel_ddi_mode_set(struct intel_encoder *encoder)
3031	serge	368	{
4104	Serge	369	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		370	int port = intel_ddi_get_encoder_port(encoder);
		371	int pipe = crtc->pipe;
		372	int type = encoder->type;
		373	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
3031	serge	374
4104	Serge	375	DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
3243	Serge	376	port_name(port), pipe_name(pipe));
3031	serge	377
4104	Serge	378	crtc->eld_vld = false;
3243	Serge	379	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
4104	Serge	380	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3480	Serge	381	struct intel_digital_port *intel_dig_port =
4104	Serge	382	enc_to_dig_port(&encoder->base);
3243	Serge	383
4104	Serge	384	intel_dp->DP = intel_dig_port->saved_port_bits \|
3480	Serge	385	DDI_BUF_CTL_ENABLE \| DDI_BUF_EMP_400MV_0DB_HSW;
4104	Serge	386	intel_dp->DP \|= DDI_PORT_WIDTH(intel_dp->lane_count);
3243	Serge	387
		388	if (intel_dp->has_audio) {
		389	DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
4104	Serge	390	pipe_name(crtc->pipe));
3243	Serge	391
		392	/* write eld */
		393	DRM_DEBUG_DRIVER("DP audio: write eld information\n");
4104	Serge	394	intel_write_eld(&encoder->base, adjusted_mode);
3243	Serge	395	}
		396	} else if (type == INTEL_OUTPUT_HDMI) {
4104	Serge	397	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3243	Serge	398
		399	if (intel_hdmi->has_audio) {
		400	/* Proper support for digital audio needs a new logic
		401	* and a new set of registers, so we leave it for future
		402	* patch bombing.
		403	*/
		404	DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
4104	Serge	405	pipe_name(crtc->pipe));
3243	Serge	406
		407	/* write eld */
		408	DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
4104	Serge	409	intel_write_eld(&encoder->base, adjusted_mode);
3243	Serge	410	}
		411
4104	Serge	412	intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
3243	Serge	413	}
		414	}
		415
		416	static struct intel_encoder *
		417	intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
		418	{
		419	struct drm_device *dev = crtc->dev;
		420	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		421	struct intel_encoder intel_encoder, ret = NULL;
		422	int num_encoders = 0;
		423
		424	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		425	ret = intel_encoder;
		426	num_encoders++;
		427	}
		428
		429	if (num_encoders != 1)
4104	Serge	430	WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
		431	pipe_name(intel_crtc->pipe));
3243	Serge	432
		433	BUG_ON(ret == NULL);
		434	return ret;
		435	}
		436
		437	void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
		438	{
		439	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		440	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
		441	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		442	uint32_t val;
		443
		444	switch (intel_crtc->ddi_pll_sel) {
		445	case PORT_CLK_SEL_SPLL:
		446	plls->spll_refcount--;
		447	if (plls->spll_refcount == 0) {
		448	DRM_DEBUG_KMS("Disabling SPLL\n");
		449	val = I915_READ(SPLL_CTL);
		450	WARN_ON(!(val & SPLL_PLL_ENABLE));
		451	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
		452	POSTING_READ(SPLL_CTL);
		453	}
		454	break;
		455	case PORT_CLK_SEL_WRPLL1:
		456	plls->wrpll1_refcount--;
		457	if (plls->wrpll1_refcount == 0) {
		458	DRM_DEBUG_KMS("Disabling WRPLL 1\n");
		459	val = I915_READ(WRPLL_CTL1);
		460	WARN_ON(!(val & WRPLL_PLL_ENABLE));
		461	I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
		462	POSTING_READ(WRPLL_CTL1);
		463	}
		464	break;
		465	case PORT_CLK_SEL_WRPLL2:
		466	plls->wrpll2_refcount--;
		467	if (plls->wrpll2_refcount == 0) {
		468	DRM_DEBUG_KMS("Disabling WRPLL 2\n");
		469	val = I915_READ(WRPLL_CTL2);
		470	WARN_ON(!(val & WRPLL_PLL_ENABLE));
		471	I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
		472	POSTING_READ(WRPLL_CTL2);
		473	}
		474	break;
		475	}
		476
		477	WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
		478	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
		479	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
		480
		481	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
		482	}
		483
4104	Serge	484	#define LC_FREQ 2700
		485	#define LC_FREQ_2K (LC_FREQ * 2000)
		486
		487	#define P_MIN 2
		488	#define P_MAX 64
		489	#define P_INC 2
		490
		491	/* Constraints for PLL good behavior */
		492	#define REF_MIN 48
		493	#define REF_MAX 400
		494	#define VCO_MIN 2400
		495	#define VCO_MAX 4800
		496
		497	#define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
		498
		499	struct wrpll_rnp {
		500	unsigned p, n2, r2;
		501	};
		502
		503	static unsigned wrpll_get_budget_for_freq(int clock)
3243	Serge	504	{
4104	Serge	505	unsigned budget;
3243	Serge	506
4104	Serge	507	switch (clock) {
		508	case 25175000:
		509	case 25200000:
		510	case 27000000:
		511	case 27027000:
		512	case 37762500:
		513	case 37800000:
		514	case 40500000:
		515	case 40541000:
		516	case 54000000:
		517	case 54054000:
		518	case 59341000:
		519	case 59400000:
		520	case 72000000:
		521	case 74176000:
		522	case 74250000:
		523	case 81000000:
		524	case 81081000:
		525	case 89012000:
		526	case 89100000:
		527	case 108000000:
		528	case 108108000:
		529	case 111264000:
		530	case 111375000:
		531	case 148352000:
		532	case 148500000:
		533	case 162000000:
		534	case 162162000:
		535	case 222525000:
		536	case 222750000:
		537	case 296703000:
		538	case 297000000:
		539	budget = 0;
		540	break;
		541	case 233500000:
		542	case 245250000:
		543	case 247750000:
		544	case 253250000:
		545	case 298000000:
		546	budget = 1500;
		547	break;
		548	case 169128000:
		549	case 169500000:
		550	case 179500000:
		551	case 202000000:
		552	budget = 2000;
		553	break;
		554	case 256250000:
		555	case 262500000:
		556	case 270000000:
		557	case 272500000:
		558	case 273750000:
		559	case 280750000:
		560	case 281250000:
		561	case 286000000:
		562	case 291750000:
		563	budget = 4000;
		564	break;
		565	case 267250000:
		566	case 268500000:
		567	budget = 5000;
3031	serge	568	break;
4104	Serge	569	default:
		570	budget = 1000;
		571	break;
		572	}
3031	serge	573
4104	Serge	574	return budget;
		575	}
3031	serge	576
4104	Serge	577	static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
		578	unsigned r2, unsigned n2, unsigned p,
		579	struct wrpll_rnp *best)
		580	{
		581	uint64_t a, b, c, d, diff, diff_best;
3031	serge	582
4104	Serge	583	/* No best (r,n,p) yet */
		584	if (best->p == 0) {
		585	best->p = p;
		586	best->n2 = n2;
		587	best->r2 = r2;
		588	return;
		589	}
3031	serge	590
4104	Serge	591	/*
		592	* Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
		593	* freq2k.
		594	*
		595	* delta = 1e6 *
		596	* abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
		597	* freq2k;
		598	*
		599	* and we would like delta <= budget.
		600	*
		601	* If the discrepancy is above the PPM-based budget, always prefer to
		602	* improve upon the previous solution. However, if you're within the
		603	* budget, try to maximize Ref * VCO, that is N / (P * R^2).
		604	*/
		605	a = freq2k * budget * p * r2;
		606	b = freq2k * budget * best->p * best->r2;
		607	diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
		608	diff_best = ABS_DIFF((freq2k * best->p * best->r2),
		609	(LC_FREQ_2K * best->n2));
		610	c = 1000000 * diff;
		611	d = 1000000 * diff_best;
		612
		613	if (a < c && b < d) {
		614	/* If both are above the budget, pick the closer */
		615	if (best->p * best->r2 * diff < p * r2 * diff_best) {
		616	best->p = p;
		617	best->n2 = n2;
		618	best->r2 = r2;
		619	}
		620	} else if (a >= c && b < d) {
		621	/* If A is below the threshold but B is above it? Update. */
		622	best->p = p;
		623	best->n2 = n2;
		624	best->r2 = r2;
		625	} else if (a >= c && b >= d) {
		626	/* Both are below the limit, so pick the higher n2/(r2r2) /
		627	if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
		628	best->p = p;
		629	best->n2 = n2;
		630	best->r2 = r2;
		631	}
		632	}
		633	/* Otherwise a < c && b >= d, do nothing */
3243	Serge	634	}
3031	serge	635
4104	Serge	636	static void
		637	intel_ddi_calculate_wrpll(int clock /* in Hz */,
		638	unsigned r2_out, unsigned n2_out, unsigned *p_out)
3243	Serge	639	{
4104	Serge	640	uint64_t freq2k;
		641	unsigned p, n2, r2;
		642	struct wrpll_rnp best = { 0, 0, 0 };
		643	unsigned budget;
		644
		645	freq2k = clock / 100;
		646
		647	budget = wrpll_get_budget_for_freq(clock);
		648
		649	/* Special case handling for 540 pixel clock: bypass WR PLL entirely
		650	* and directly pass the LC PLL to it. */
		651	if (freq2k == 5400000) {
		652	*n2_out = 2;
		653	*p_out = 1;
		654	*r2_out = 2;
		655	return;
		656	}
		657
		658	/*
		659	* Ref = LC_FREQ / R, where Ref is the actual reference input seen by
		660	* the WR PLL.
		661	*
		662	* We want R so that REF_MIN <= Ref <= REF_MAX.
		663	* Injecting R2 = 2 * R gives:
		664	* REF_MAX * r2 > LC_FREQ * 2 and
		665	* REF_MIN * r2 < LC_FREQ * 2
		666	*
		667	* Which means the desired boundaries for r2 are:
		668	* LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
		669	*
		670	*/
		671	for (r2 = LC_FREQ * 2 / REF_MAX + 1;
		672	r2 <= LC_FREQ * 2 / REF_MIN;
		673	r2++) {
		674
		675	/*
		676	* VCO = N * Ref, that is: VCO = N * LC_FREQ / R
		677	*
		678	* Once again we want VCO_MIN <= VCO <= VCO_MAX.
		679	* Injecting R2 = 2 * R and N2 = 2 * N, we get:
		680	* VCO_MAX * r2 > n2 * LC_FREQ and
		681	* VCO_MIN * r2 < n2 * LC_FREQ)
		682	*
		683	* Which means the desired boundaries for n2 are:
		684	* VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
		685	*/
		686	for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
		687	n2 <= VCO_MAX * r2 / LC_FREQ;
		688	n2++) {
		689
		690	for (p = P_MIN; p <= P_MAX; p += P_INC)
		691	wrpll_update_rnp(freq2k, budget,
		692	r2, n2, p, &best);
		693	}
		694	}
		695
		696	*n2_out = best.n2;
		697	*p_out = best.p;
		698	*r2_out = best.r2;
		699	}
		700
4560	Serge	701	/*
		702	* Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
		703	* stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
		704	* steal the selected PLL. You need to call intel_ddi_pll_enable to actually
		705	* enable the PLL.
		706	*/
		707	bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
4104	Serge	708	{
4560	Serge	709	struct drm_crtc *crtc = &intel_crtc->base;
3243	Serge	710	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		711	struct drm_encoder *encoder = &intel_encoder->base;
		712	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		713	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
		714	int type = intel_encoder->type;
		715	enum pipe pipe = intel_crtc->pipe;
4104	Serge	716	int clock = intel_crtc->config.port_clock;
3031	serge	717
3243	Serge	718	intel_ddi_put_crtc_pll(crtc);
3031	serge	719
3243	Serge	720	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
		721	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3031	serge	722
3243	Serge	723	switch (intel_dp->link_bw) {
		724	case DP_LINK_BW_1_62:
		725	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
		726	break;
		727	case DP_LINK_BW_2_7:
		728	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
		729	break;
		730	case DP_LINK_BW_5_4:
		731	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
		732	break;
		733	default:
		734	DRM_ERROR("Link bandwidth %d unsupported\n",
		735	intel_dp->link_bw);
		736	return false;
		737	}
		738
		739	} else if (type == INTEL_OUTPUT_HDMI) {
4560	Serge	740	uint32_t reg, val;
4104	Serge	741	unsigned p, n2, r2;
3243	Serge	742
4560	Serge	743	intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
		744
		745	val = WRPLL_PLL_ENABLE \| WRPLL_PLL_SELECT_LCPLL_2700 \|
		746	WRPLL_DIVIDER_REFERENCE(r2) \| WRPLL_DIVIDER_FEEDBACK(n2) \|
		747	WRPLL_DIVIDER_POST(p);
		748
		749	if (val == I915_READ(WRPLL_CTL1)) {
		750	DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
		751	pipe_name(pipe));
		752	reg = WRPLL_CTL1;
		753	} else if (val == I915_READ(WRPLL_CTL2)) {
		754	DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
		755	pipe_name(pipe));
		756	reg = WRPLL_CTL2;
		757	} else if (plls->wrpll1_refcount == 0) {
3243	Serge	758	DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
		759	pipe_name(pipe));
		760	reg = WRPLL_CTL1;
		761	} else if (plls->wrpll2_refcount == 0) {
		762	DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
		763	pipe_name(pipe));
		764	reg = WRPLL_CTL2;
		765	} else {
		766	DRM_ERROR("No WRPLLs available!\n");
		767	return false;
		768	}
		769
4560	Serge	770	DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
		771	clock, p, n2, r2);
3243	Serge	772
4560	Serge	773	if (reg == WRPLL_CTL1) {
		774	plls->wrpll1_refcount++;
		775	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
		776	} else {
		777	plls->wrpll2_refcount++;
		778	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
		779	}
3243	Serge	780
		781	} else if (type == INTEL_OUTPUT_ANALOG) {
		782	if (plls->spll_refcount == 0) {
		783	DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
		784	pipe_name(pipe));
		785	plls->spll_refcount++;
		786	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
3746	Serge	787	} else {
		788	DRM_ERROR("SPLL already in use\n");
		789	return false;
3243	Serge	790	}
		791
		792	} else {
		793	WARN(1, "Invalid DDI encoder type %d\n", type);
		794	return false;
		795	}
		796
		797	return true;
		798	}
3031	serge	799
4560	Serge	800	/*
		801	* To be called after intel_ddi_pll_select(). That one selects the PLL to be
		802	* used, this one actually enables the PLL.
		803	*/
		804	void intel_ddi_pll_enable(struct intel_crtc *crtc)
		805	{
		806	struct drm_device *dev = crtc->base.dev;
		807	struct drm_i915_private *dev_priv = dev->dev_private;
		808	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
		809	int clock = crtc->config.port_clock;
		810	uint32_t reg, cur_val, new_val;
		811	int refcount;
		812	const char *pll_name;
		813	uint32_t enable_bit = (1 << 31);
		814	unsigned int p, n2, r2;
		815
		816	BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
		817	BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
		818
		819	switch (crtc->ddi_pll_sel) {
		820	case PORT_CLK_SEL_LCPLL_2700:
		821	case PORT_CLK_SEL_LCPLL_1350:
		822	case PORT_CLK_SEL_LCPLL_810:
		823	/*
		824	* LCPLL should always be enabled at this point of the mode set
		825	* sequence, so nothing to do.
		826	*/
		827	return;
		828
		829	case PORT_CLK_SEL_SPLL:
		830	pll_name = "SPLL";
		831	reg = SPLL_CTL;
		832	refcount = plls->spll_refcount;
		833	new_val = SPLL_PLL_ENABLE \| SPLL_PLL_FREQ_1350MHz \|
		834	SPLL_PLL_SSC;
		835	break;
		836
		837	case PORT_CLK_SEL_WRPLL1:
		838	case PORT_CLK_SEL_WRPLL2:
		839	if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
		840	pll_name = "WRPLL1";
		841	reg = WRPLL_CTL1;
		842	refcount = plls->wrpll1_refcount;
		843	} else {
		844	pll_name = "WRPLL2";
		845	reg = WRPLL_CTL2;
		846	refcount = plls->wrpll2_refcount;
		847	}
		848
		849	intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
		850
		851	new_val = WRPLL_PLL_ENABLE \| WRPLL_PLL_SELECT_LCPLL_2700 \|
		852	WRPLL_DIVIDER_REFERENCE(r2) \|
		853	WRPLL_DIVIDER_FEEDBACK(n2) \| WRPLL_DIVIDER_POST(p);
		854
		855	break;
		856
		857	case PORT_CLK_SEL_NONE:
		858	WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
		859	return;
		860	default:
		861	WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
		862	return;
		863	}
		864
		865	cur_val = I915_READ(reg);
		866
		867	WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
		868	if (refcount == 1) {
		869	WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
		870	I915_WRITE(reg, new_val);
		871	POSTING_READ(reg);
		872	udelay(20);
		873	} else {
		874	WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
		875	}
		876	}
		877
3243	Serge	878	void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
		879	{
		880	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		881	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		882	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3746	Serge	883	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	884	int type = intel_encoder->type;
		885	uint32_t temp;
		886
		887	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
		888
		889	temp = TRANS_MSA_SYNC_CLK;
3746	Serge	890	switch (intel_crtc->config.pipe_bpp) {
3243	Serge	891	case 18:
		892	temp \|= TRANS_MSA_6_BPC;
		893	break;
		894	case 24:
		895	temp \|= TRANS_MSA_8_BPC;
		896	break;
		897	case 30:
		898	temp \|= TRANS_MSA_10_BPC;
		899	break;
		900	case 36:
		901	temp \|= TRANS_MSA_12_BPC;
		902	break;
		903	default:
3746	Serge	904	BUG();
3031	serge	905	}
3243	Serge	906	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
		907	}
		908	}
3031	serge	909
3746	Serge	910	void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
3243	Serge	911	{
		912	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		913	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		914	struct drm_encoder *encoder = &intel_encoder->base;
4560	Serge	915	struct drm_device *dev = crtc->dev;
		916	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	917	enum pipe pipe = intel_crtc->pipe;
3746	Serge	918	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	919	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		920	int type = intel_encoder->type;
		921	uint32_t temp;
3031	serge	922
3243	Serge	923	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
		924	temp = TRANS_DDI_FUNC_ENABLE;
		925	temp \|= TRANS_DDI_SELECT_PORT(port);
		926
3746	Serge	927	switch (intel_crtc->config.pipe_bpp) {
3031	serge	928	case 18:
3243	Serge	929	temp \|= TRANS_DDI_BPC_6;
3031	serge	930	break;
		931	case 24:
3243	Serge	932	temp \|= TRANS_DDI_BPC_8;
3031	serge	933	break;
		934	case 30:
3243	Serge	935	temp \|= TRANS_DDI_BPC_10;
3031	serge	936	break;
		937	case 36:
3243	Serge	938	temp \|= TRANS_DDI_BPC_12;
3031	serge	939	break;
		940	default:
3746	Serge	941	BUG();
3031	serge	942	}
		943
4560	Serge	944	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
3243	Serge	945	temp \|= TRANS_DDI_PVSYNC;
4560	Serge	946	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
3243	Serge	947	temp \|= TRANS_DDI_PHSYNC;
		948
		949	if (cpu_transcoder == TRANSCODER_EDP) {
		950	switch (pipe) {
		951	case PIPE_A:
4560	Serge	952	/* On Haswell, can only use the always-on power well for
		953	* eDP when not using the panel fitter, and when not
		954	* using motion blur mitigation (which we don't
		955	* support). */
		956	if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
3243	Serge	957	temp \|= TRANS_DDI_EDP_INPUT_A_ONOFF;
3480	Serge	958	else
		959	temp \|= TRANS_DDI_EDP_INPUT_A_ON;
3243	Serge	960	break;
		961	case PIPE_B:
		962	temp \|= TRANS_DDI_EDP_INPUT_B_ONOFF;
		963	break;
		964	case PIPE_C:
		965	temp \|= TRANS_DDI_EDP_INPUT_C_ONOFF;
		966	break;
		967	default:
		968	BUG();
		969	break;
		970	}
		971	}
		972
		973	if (type == INTEL_OUTPUT_HDMI) {
		974	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
		975
3031	serge	976	if (intel_hdmi->has_hdmi_sink)
3243	Serge	977	temp \|= TRANS_DDI_MODE_SELECT_HDMI;
3031	serge	978	else
3243	Serge	979	temp \|= TRANS_DDI_MODE_SELECT_DVI;
3031	serge	980
3243	Serge	981	} else if (type == INTEL_OUTPUT_ANALOG) {
		982	temp \|= TRANS_DDI_MODE_SELECT_FDI;
4104	Serge	983	temp \|= (intel_crtc->config.fdi_lanes - 1) << 1;
3031	serge	984
3243	Serge	985	} else if (type == INTEL_OUTPUT_DISPLAYPORT \|\|
		986	type == INTEL_OUTPUT_EDP) {
		987	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3031	serge	988
3243	Serge	989	temp \|= TRANS_DDI_MODE_SELECT_DP_SST;
		990
4104	Serge	991	temp \|= DDI_PORT_WIDTH(intel_dp->lane_count);
3243	Serge	992	} else {
4104	Serge	993	WARN(1, "Invalid encoder type %d for pipe %c\n",
		994	intel_encoder->type, pipe_name(pipe));
3243	Serge	995	}
		996
		997	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
3031	serge	998	}
		999
3243	Serge	1000	void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
		1001	enum transcoder cpu_transcoder)
		1002	{
		1003	uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
		1004	uint32_t val = I915_READ(reg);
		1005
		1006	val &= ~(TRANS_DDI_FUNC_ENABLE \| TRANS_DDI_PORT_MASK);
		1007	val \|= TRANS_DDI_PORT_NONE;
		1008	I915_WRITE(reg, val);
		1009	}
		1010
		1011	bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
		1012	{
		1013	struct drm_device *dev = intel_connector->base.dev;
		1014	struct drm_i915_private *dev_priv = dev->dev_private;
		1015	struct intel_encoder *intel_encoder = intel_connector->encoder;
		1016	int type = intel_connector->base.connector_type;
		1017	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		1018	enum pipe pipe = 0;
		1019	enum transcoder cpu_transcoder;
		1020	uint32_t tmp;
		1021
		1022	if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
		1023	return false;
		1024
		1025	if (port == PORT_A)
		1026	cpu_transcoder = TRANSCODER_EDP;
		1027	else
3480	Serge	1028	cpu_transcoder = (enum transcoder) pipe;
3243	Serge	1029
		1030	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		1031
		1032	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
		1033	case TRANS_DDI_MODE_SELECT_HDMI:
		1034	case TRANS_DDI_MODE_SELECT_DVI:
		1035	return (type == DRM_MODE_CONNECTOR_HDMIA);
		1036
		1037	case TRANS_DDI_MODE_SELECT_DP_SST:
		1038	if (type == DRM_MODE_CONNECTOR_eDP)
		1039	return true;
		1040	case TRANS_DDI_MODE_SELECT_DP_MST:
		1041	return (type == DRM_MODE_CONNECTOR_DisplayPort);
		1042
		1043	case TRANS_DDI_MODE_SELECT_FDI:
		1044	return (type == DRM_MODE_CONNECTOR_VGA);
		1045
		1046	default:
		1047	return false;
		1048	}
		1049	}
		1050
3031	serge	1051	bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
		1052	enum pipe *pipe)
		1053	{
		1054	struct drm_device *dev = encoder->base.dev;
		1055	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	1056	enum port port = intel_ddi_get_encoder_port(encoder);
3031	serge	1057	u32 tmp;
		1058	int i;
		1059
3243	Serge	1060	tmp = I915_READ(DDI_BUF_CTL(port));
3031	serge	1061
		1062	if (!(tmp & DDI_BUF_CTL_ENABLE))
		1063	return false;
		1064
3243	Serge	1065	if (port == PORT_A) {
		1066	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
3031	serge	1067
3243	Serge	1068	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		1069	case TRANS_DDI_EDP_INPUT_A_ON:
		1070	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		1071	*pipe = PIPE_A;
		1072	break;
		1073	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		1074	*pipe = PIPE_B;
		1075	break;
		1076	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		1077	*pipe = PIPE_C;
		1078	break;
		1079	}
		1080
		1081	return true;
		1082	} else {
		1083	for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
		1084	tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
		1085
		1086	if ((tmp & TRANS_DDI_PORT_MASK)
		1087	== TRANS_DDI_SELECT_PORT(port)) {
3031	serge	1088	*pipe = i;
		1089	return true;
		1090	}
		1091	}
3243	Serge	1092	}
3031	serge	1093
4104	Serge	1094	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
3031	serge	1095
3746	Serge	1096	return false;
3031	serge	1097	}
		1098
3243	Serge	1099	static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
		1100	enum pipe pipe)
3031	serge	1101	{
3243	Serge	1102	uint32_t temp, ret;
3746	Serge	1103	enum port port = I915_MAX_PORTS;
3243	Serge	1104	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1105	pipe);
		1106	int i;
		1107
		1108	if (cpu_transcoder == TRANSCODER_EDP) {
		1109	port = PORT_A;
		1110	} else {
		1111	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		1112	temp &= TRANS_DDI_PORT_MASK;
		1113
		1114	for (i = PORT_B; i <= PORT_E; i++)
		1115	if (temp == TRANS_DDI_SELECT_PORT(i))
		1116	port = i;
		1117	}
		1118
3746	Serge	1119	if (port == I915_MAX_PORTS) {
		1120	WARN(1, "Pipe %c enabled on an unknown port\n",
		1121	pipe_name(pipe));
		1122	ret = PORT_CLK_SEL_NONE;
		1123	} else {
3243	Serge	1124	ret = I915_READ(PORT_CLK_SEL(port));
3746	Serge	1125	DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
		1126	"0x%08x\n", pipe_name(pipe), port_name(port),
		1127	ret);
		1128	}
3243	Serge	1129
		1130	return ret;
		1131	}
		1132
		1133	void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
		1134	{
3031	serge	1135	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	1136	enum pipe pipe;
		1137	struct intel_crtc *intel_crtc;
3031	serge	1138
4539	Serge	1139	dev_priv->ddi_plls.spll_refcount = 0;
		1140	dev_priv->ddi_plls.wrpll1_refcount = 0;
		1141	dev_priv->ddi_plls.wrpll2_refcount = 0;
		1142
3243	Serge	1143	for_each_pipe(pipe) {
		1144	intel_crtc =
		1145	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3031	serge	1146
4539	Serge	1147	if (!intel_crtc->active) {
		1148	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
3243	Serge	1149	continue;
4539	Serge	1150	}
3243	Serge	1151
		1152	intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
		1153	pipe);
		1154
		1155	switch (intel_crtc->ddi_pll_sel) {
		1156	case PORT_CLK_SEL_SPLL:
		1157	dev_priv->ddi_plls.spll_refcount++;
		1158	break;
		1159	case PORT_CLK_SEL_WRPLL1:
		1160	dev_priv->ddi_plls.wrpll1_refcount++;
		1161	break;
		1162	case PORT_CLK_SEL_WRPLL2:
		1163	dev_priv->ddi_plls.wrpll2_refcount++;
		1164	break;
		1165	}
		1166	}
3031	serge	1167	}
		1168
3243	Serge	1169	void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
3031	serge	1170	{
3243	Serge	1171	struct drm_crtc *crtc = &intel_crtc->base;
		1172	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		1173	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		1174	enum port port = intel_ddi_get_encoder_port(intel_encoder);
3746	Serge	1175	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	1176
		1177	if (cpu_transcoder != TRANSCODER_EDP)
		1178	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		1179	TRANS_CLK_SEL_PORT(port));
		1180	}
		1181
		1182	void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
		1183	{
		1184	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3746	Serge	1185	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	1186
		1187	if (cpu_transcoder != TRANSCODER_EDP)
		1188	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		1189	TRANS_CLK_SEL_DISABLED);
		1190	}
		1191
		1192	static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
		1193	{
		1194	struct drm_encoder *encoder = &intel_encoder->base;
		1195	struct drm_crtc *crtc = encoder->crtc;
		1196	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		1197	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1198	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		1199	int type = intel_encoder->type;
		1200
		1201	if (type == INTEL_OUTPUT_EDP) {
		1202	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1203	ironlake_edp_panel_on(intel_dp);
		1204	}
		1205
		1206	WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
		1207	I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
		1208
		1209	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
		1210	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1211
		1212	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
		1213	intel_dp_start_link_train(intel_dp);
		1214	intel_dp_complete_link_train(intel_dp);
3746	Serge	1215	if (port != PORT_A)
		1216	intel_dp_stop_link_train(intel_dp);
3243	Serge	1217	}
		1218	}
		1219
		1220	static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
		1221	{
		1222	struct drm_encoder *encoder = &intel_encoder->base;
		1223	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		1224	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		1225	int type = intel_encoder->type;
		1226	uint32_t val;
		1227	bool wait = false;
		1228
		1229	val = I915_READ(DDI_BUF_CTL(port));
		1230	if (val & DDI_BUF_CTL_ENABLE) {
		1231	val &= ~DDI_BUF_CTL_ENABLE;
		1232	I915_WRITE(DDI_BUF_CTL(port), val);
		1233	wait = true;
		1234	}
		1235
		1236	val = I915_READ(DP_TP_CTL(port));
		1237	val &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		1238	val \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		1239	I915_WRITE(DP_TP_CTL(port), val);
		1240
		1241	if (wait)
		1242	intel_wait_ddi_buf_idle(dev_priv, port);
		1243
4560	Serge	1244	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
3243	Serge	1245	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4560	Serge	1246	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3243	Serge	1247	ironlake_edp_panel_off(intel_dp);
		1248	}
		1249
		1250	I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
		1251	}
		1252
		1253	static void intel_enable_ddi(struct intel_encoder *intel_encoder)
		1254	{
		1255	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	1256	struct drm_crtc *crtc = encoder->crtc;
		1257	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1258	int pipe = intel_crtc->pipe;
3243	Serge	1259	struct drm_device *dev = encoder->dev;
3031	serge	1260	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	1261	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		1262	int type = intel_encoder->type;
3480	Serge	1263	uint32_t tmp;
3031	serge	1264
3243	Serge	1265	if (type == INTEL_OUTPUT_HDMI) {
3480	Serge	1266	struct intel_digital_port *intel_dig_port =
		1267	enc_to_dig_port(encoder);
		1268
3243	Serge	1269	/* In HDMI/DVI mode, the port width, and swing/emphasis values
		1270	* are ignored so nothing special needs to be done besides
		1271	* enabling the port.
		1272	*/
3480	Serge	1273	I915_WRITE(DDI_BUF_CTL(port),
4104	Serge	1274	intel_dig_port->saved_port_bits \|
		1275	DDI_BUF_CTL_ENABLE);
3243	Serge	1276	} else if (type == INTEL_OUTPUT_EDP) {
		1277	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3031	serge	1278
3746	Serge	1279	if (port == PORT_A)
		1280	intel_dp_stop_link_train(intel_dp);
		1281
3243	Serge	1282	ironlake_edp_backlight_on(intel_dp);
4104	Serge	1283	intel_edp_psr_enable(intel_dp);
3243	Serge	1284	}
3480	Serge	1285
4104	Serge	1286	if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
3480	Serge	1287	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
		1288	tmp \|= ((AUDIO_OUTPUT_ENABLE_A \| AUDIO_ELD_VALID_A) << (pipe * 4));
		1289	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
		1290	}
3031	serge	1291	}
3243	Serge	1292
		1293	static void intel_disable_ddi(struct intel_encoder *intel_encoder)
		1294	{
		1295	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	1296	struct drm_crtc *crtc = encoder->crtc;
		1297	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1298	int pipe = intel_crtc->pipe;
3243	Serge	1299	int type = intel_encoder->type;
3480	Serge	1300	struct drm_device *dev = encoder->dev;
		1301	struct drm_i915_private *dev_priv = dev->dev_private;
		1302	uint32_t tmp;
3243	Serge	1303
4104	Serge	1304	if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
3746	Serge	1305	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
4104	Serge	1306	tmp &= ~((AUDIO_OUTPUT_ENABLE_A \| AUDIO_ELD_VALID_A) <<
		1307	(pipe * 4));
3746	Serge	1308	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
4104	Serge	1309	}
3746	Serge	1310
3243	Serge	1311	if (type == INTEL_OUTPUT_EDP) {
		1312	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1313
4104	Serge	1314	intel_edp_psr_disable(intel_dp);
3243	Serge	1315	ironlake_edp_backlight_off(intel_dp);
		1316	}
		1317	}
		1318
		1319	int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
		1320	{
4560	Serge	1321	struct drm_device *dev = dev_priv->dev;
4104	Serge	1322	uint32_t lcpll = I915_READ(LCPLL_CTL);
4560	Serge	1323	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
4104	Serge	1324
4560	Serge	1325	if (lcpll & LCPLL_CD_SOURCE_FCLK) {
4104	Serge	1326	return 800000;
4560	Serge	1327	} else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
4104	Serge	1328	return 450000;
4560	Serge	1329	} else if (freq == LCPLL_CLK_FREQ_450) {
4104	Serge	1330	return 450000;
4560	Serge	1331	} else if (IS_HASWELL(dev)) {
		1332	if (IS_ULT(dev))
4104	Serge	1333	return 337500;
3243	Serge	1334	else
4104	Serge	1335	return 540000;
4560	Serge	1336	} else {
		1337	if (freq == LCPLL_CLK_FREQ_54O_BDW)
		1338	return 540000;
		1339	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
		1340	return 337500;
		1341	else
		1342	return 675000;
		1343	}
3243	Serge	1344	}
		1345
		1346	void intel_ddi_pll_init(struct drm_device *dev)
		1347	{
		1348	struct drm_i915_private *dev_priv = dev->dev_private;
		1349	uint32_t val = I915_READ(LCPLL_CTL);
		1350
		1351	/* The LCPLL register should be turned on by the BIOS. For now let's
		1352	* just check its state and print errors in case something is wrong.
		1353	* Don't even try to turn it on.
		1354	*/
		1355
4104	Serge	1356	DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
3243	Serge	1357	intel_ddi_get_cdclk_freq(dev_priv));
		1358
		1359	if (val & LCPLL_CD_SOURCE_FCLK)
		1360	DRM_ERROR("CDCLK source is not LCPLL\n");
		1361
		1362	if (val & LCPLL_PLL_DISABLE)
		1363	DRM_ERROR("LCPLL is disabled\n");
		1364	}
		1365
		1366	void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
		1367	{
		1368	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		1369	struct intel_dp *intel_dp = &intel_dig_port->dp;
		1370	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		1371	enum port port = intel_dig_port->port;
		1372	uint32_t val;
3480	Serge	1373	bool wait = false;
3243	Serge	1374
		1375	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
		1376	val = I915_READ(DDI_BUF_CTL(port));
		1377	if (val & DDI_BUF_CTL_ENABLE) {
		1378	val &= ~DDI_BUF_CTL_ENABLE;
		1379	I915_WRITE(DDI_BUF_CTL(port), val);
		1380	wait = true;
		1381	}
		1382
		1383	val = I915_READ(DP_TP_CTL(port));
		1384	val &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		1385	val \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		1386	I915_WRITE(DP_TP_CTL(port), val);
		1387	POSTING_READ(DP_TP_CTL(port));
		1388
		1389	if (wait)
		1390	intel_wait_ddi_buf_idle(dev_priv, port);
		1391	}
		1392
		1393	val = DP_TP_CTL_ENABLE \| DP_TP_CTL_MODE_SST \|
		1394	DP_TP_CTL_LINK_TRAIN_PAT1 \| DP_TP_CTL_SCRAMBLE_DISABLE;
4560	Serge	1395	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3243	Serge	1396	val \|= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
		1397	I915_WRITE(DP_TP_CTL(port), val);
		1398	POSTING_READ(DP_TP_CTL(port));
		1399
		1400	intel_dp->DP \|= DDI_BUF_CTL_ENABLE;
		1401	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
		1402	POSTING_READ(DDI_BUF_CTL(port));
		1403
		1404	udelay(600);
		1405	}
		1406
		1407	void intel_ddi_fdi_disable(struct drm_crtc *crtc)
		1408	{
		1409	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		1410	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		1411	uint32_t val;
		1412
		1413	intel_ddi_post_disable(intel_encoder);
		1414
		1415	val = I915_READ(_FDI_RXA_CTL);
		1416	val &= ~FDI_RX_ENABLE;
		1417	I915_WRITE(_FDI_RXA_CTL, val);
		1418
		1419	val = I915_READ(_FDI_RXA_MISC);
		1420	val &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
		1421	val \|= FDI_RX_PWRDN_LANE1_VAL(2) \| FDI_RX_PWRDN_LANE0_VAL(2);
		1422	I915_WRITE(_FDI_RXA_MISC, val);
		1423
		1424	val = I915_READ(_FDI_RXA_CTL);
		1425	val &= ~FDI_PCDCLK;
		1426	I915_WRITE(_FDI_RXA_CTL, val);
		1427
		1428	val = I915_READ(_FDI_RXA_CTL);
		1429	val &= ~FDI_RX_PLL_ENABLE;
		1430	I915_WRITE(_FDI_RXA_CTL, val);
		1431	}
		1432
		1433	static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
		1434	{
		1435	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
		1436	int type = intel_encoder->type;
		1437
		1438	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP)
		1439	intel_dp_check_link_status(intel_dp);
		1440	}
		1441
4280	Serge	1442	void intel_ddi_get_config(struct intel_encoder *encoder,
4104	Serge	1443	struct intel_crtc_config *pipe_config)
		1444	{
		1445	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		1446	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
		1447	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
		1448	u32 temp, flags = 0;
		1449
		1450	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		1451	if (temp & TRANS_DDI_PHSYNC)
		1452	flags \|= DRM_MODE_FLAG_PHSYNC;
		1453	else
		1454	flags \|= DRM_MODE_FLAG_NHSYNC;
		1455	if (temp & TRANS_DDI_PVSYNC)
		1456	flags \|= DRM_MODE_FLAG_PVSYNC;
		1457	else
		1458	flags \|= DRM_MODE_FLAG_NVSYNC;
		1459
		1460	pipe_config->adjusted_mode.flags \|= flags;
4280	Serge	1461
		1462	switch (temp & TRANS_DDI_BPC_MASK) {
		1463	case TRANS_DDI_BPC_6:
		1464	pipe_config->pipe_bpp = 18;
		1465	break;
		1466	case TRANS_DDI_BPC_8:
		1467	pipe_config->pipe_bpp = 24;
		1468	break;
		1469	case TRANS_DDI_BPC_10:
		1470	pipe_config->pipe_bpp = 30;
		1471	break;
		1472	case TRANS_DDI_BPC_12:
		1473	pipe_config->pipe_bpp = 36;
		1474	break;
		1475	default:
		1476	break;
		1477	}
4371	Serge	1478
4560	Serge	1479	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
		1480	case TRANS_DDI_MODE_SELECT_HDMI:
		1481	case TRANS_DDI_MODE_SELECT_DVI:
		1482	case TRANS_DDI_MODE_SELECT_FDI:
		1483	break;
		1484	case TRANS_DDI_MODE_SELECT_DP_SST:
		1485	case TRANS_DDI_MODE_SELECT_DP_MST:
		1486	pipe_config->has_dp_encoder = true;
		1487	intel_dp_get_m_n(intel_crtc, pipe_config);
		1488	break;
		1489	default:
		1490	break;
		1491	}
		1492
4371	Serge	1493	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
		1494	pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		1495	/*
		1496	* This is a big fat ugly hack.
		1497	*
		1498	* Some machines in UEFI boot mode provide us a VBT that has 18
		1499	* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		1500	* unknown we fail to light up. Yet the same BIOS boots up with
		1501	* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		1502	* max, not what it tells us to use.
		1503	*
		1504	* Note: This will still be broken if the eDP panel is not lit
		1505	* up by the BIOS, and thus we can't get the mode at module
		1506	* load.
		1507	*/
		1508	DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
		1509	pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		1510	dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
		1511	}
4104	Serge	1512	}
		1513
3243	Serge	1514	static void intel_ddi_destroy(struct drm_encoder *encoder)
		1515	{
		1516	/* HDMI has nothing special to destroy, so we can go with this. */
		1517	intel_dp_encoder_destroy(encoder);
		1518	}
		1519
3746	Serge	1520	static bool intel_ddi_compute_config(struct intel_encoder *encoder,
		1521	struct intel_crtc_config *pipe_config)
3243	Serge	1522	{
3746	Serge	1523	int type = encoder->type;
4104	Serge	1524	int port = intel_ddi_get_encoder_port(encoder);
3243	Serge	1525
3746	Serge	1526	WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3243	Serge	1527
4104	Serge	1528	if (port == PORT_A)
		1529	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		1530
3243	Serge	1531	if (type == INTEL_OUTPUT_HDMI)
3746	Serge	1532	return intel_hdmi_compute_config(encoder, pipe_config);
3243	Serge	1533	else
3746	Serge	1534	return intel_dp_compute_config(encoder, pipe_config);
3243	Serge	1535	}
		1536
		1537	static const struct drm_encoder_funcs intel_ddi_funcs = {
		1538	.destroy = intel_ddi_destroy,
		1539	};
		1540
4560	Serge	1541	static struct intel_connector *
		1542	intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
		1543	{
		1544	struct intel_connector *connector;
		1545	enum port port = intel_dig_port->port;
		1546
		1547	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
		1548	if (!connector)
		1549	return NULL;
		1550
		1551	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
		1552	if (!intel_dp_init_connector(intel_dig_port, connector)) {
		1553	kfree(connector);
		1554	return NULL;
		1555	}
		1556
		1557	return connector;
		1558	}
		1559
		1560	static struct intel_connector *
		1561	intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
		1562	{
		1563	struct intel_connector *connector;
		1564	enum port port = intel_dig_port->port;
		1565
		1566	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
		1567	if (!connector)
		1568	return NULL;
		1569
		1570	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
		1571	intel_hdmi_init_connector(intel_dig_port, connector);
		1572
		1573	return connector;
		1574	}
		1575
3243	Serge	1576	void intel_ddi_init(struct drm_device *dev, enum port port)
		1577	{
3480	Serge	1578	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	1579	struct intel_digital_port *intel_dig_port;
		1580	struct intel_encoder *intel_encoder;
		1581	struct drm_encoder *encoder;
		1582	struct intel_connector *hdmi_connector = NULL;
		1583	struct intel_connector *dp_connector = NULL;
4560	Serge	1584	bool init_hdmi, init_dp;
3243	Serge	1585
4560	Serge	1586	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi \|\|
		1587	dev_priv->vbt.ddi_port_info[port].supports_hdmi);
		1588	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
		1589	if (!init_dp && !init_hdmi) {
		1590	DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
		1591	port_name(port));
		1592	init_hdmi = true;
		1593	init_dp = true;
		1594	}
		1595
		1596	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3243	Serge	1597	if (!intel_dig_port)
		1598	return;
		1599
		1600	intel_encoder = &intel_dig_port->base;
		1601	encoder = &intel_encoder->base;
		1602
		1603	drm_encoder_init(dev, encoder, &intel_ddi_funcs,
		1604	DRM_MODE_ENCODER_TMDS);
		1605
3746	Serge	1606	intel_encoder->compute_config = intel_ddi_compute_config;
4104	Serge	1607	intel_encoder->mode_set = intel_ddi_mode_set;
3243	Serge	1608	intel_encoder->enable = intel_enable_ddi;
		1609	intel_encoder->pre_enable = intel_ddi_pre_enable;
		1610	intel_encoder->disable = intel_disable_ddi;
		1611	intel_encoder->post_disable = intel_ddi_post_disable;
		1612	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4104	Serge	1613	intel_encoder->get_config = intel_ddi_get_config;
3243	Serge	1614
		1615	intel_dig_port->port = port;
4104	Serge	1616	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
		1617	(DDI_BUF_PORT_REVERSAL \|
		1618	DDI_A_4_LANES);
3243	Serge	1619
		1620	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
		1621	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
		1622	intel_encoder->cloneable = false;
		1623	intel_encoder->hot_plug = intel_ddi_hot_plug;
		1624
4560	Serge	1625	if (init_dp)
		1626	dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
		1627
		1628	/* In theory we don't need the encoder->type check, but leave it just in
		1629	* case we have some really bad VBTs... */
		1630	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
		1631	hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
		1632
		1633	if (!dp_connector && !hdmi_connector) {
4104	Serge	1634	drm_encoder_cleanup(encoder);
		1635	kfree(intel_dig_port);
		1636	}
3243	Serge	1637	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ddi.c – Rev 4560