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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | */ |
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26 | |||
5097 | serge | 27 | #include |
2330 | Serge | 28 | #include |
29 | #include |
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3031 | serge | 30 | #include |
6084 | serge | 31 | #include |
3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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2330 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2330 | Serge | 37 | #include "i915_drv.h" |
38 | |||
39 | /* Here's the desired hotplug mode */ |
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40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
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41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
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42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
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43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
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44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
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45 | ADPA_CRT_HOTPLUG_ENABLE) |
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46 | |||
47 | struct intel_crt { |
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48 | struct intel_encoder base; |
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3480 | Serge | 49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ |
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51 | struct intel_connector *connector; |
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2330 | Serge | 52 | bool force_hotplug_required; |
6937 | serge | 53 | i915_reg_t adpa_reg; |
2330 | Serge | 54 | }; |
55 | |||
4104 | Serge | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
2330 | Serge | 57 | { |
4104 | Serge | 58 | return container_of(encoder, struct intel_crt, base); |
2330 | Serge | 59 | } |
60 | |||
4104 | Serge | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
2330 | Serge | 62 | { |
4104 | Serge | 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
3031 | serge | 64 | } |
65 | |||
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
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67 | enum pipe *pipe) |
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68 | { |
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69 | struct drm_device *dev = encoder->base.dev; |
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2330 | Serge | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
5060 | serge | 72 | enum intel_display_power_domain power_domain; |
3031 | serge | 73 | u32 tmp; |
6937 | serge | 74 | bool ret; |
2330 | Serge | 75 | |
5060 | serge | 76 | power_domain = intel_display_port_power_domain(encoder); |
6937 | serge | 77 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
5060 | serge | 78 | return false; |
79 | |||
6937 | serge | 80 | ret = false; |
81 | |||
3031 | serge | 82 | tmp = I915_READ(crt->adpa_reg); |
83 | |||
84 | if (!(tmp & ADPA_DAC_ENABLE)) |
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6937 | serge | 85 | goto out; |
3031 | serge | 86 | |
87 | if (HAS_PCH_CPT(dev)) |
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88 | *pipe = PORT_TO_PIPE_CPT(tmp); |
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2330 | Serge | 89 | else |
3031 | serge | 90 | *pipe = PORT_TO_PIPE(tmp); |
2330 | Serge | 91 | |
6937 | serge | 92 | ret = true; |
93 | out: |
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94 | intel_display_power_put(dev_priv, power_domain); |
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95 | |||
96 | return ret; |
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3031 | serge | 97 | } |
98 | |||
4280 | Serge | 99 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
4104 | Serge | 100 | { |
101 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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102 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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103 | u32 tmp, flags = 0; |
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104 | |||
105 | tmp = I915_READ(crt->adpa_reg); |
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106 | |||
107 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
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108 | flags |= DRM_MODE_FLAG_PHSYNC; |
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109 | else |
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110 | flags |= DRM_MODE_FLAG_NHSYNC; |
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111 | |||
112 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
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113 | flags |= DRM_MODE_FLAG_PVSYNC; |
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114 | else |
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115 | flags |= DRM_MODE_FLAG_NVSYNC; |
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116 | |||
4280 | Serge | 117 | return flags; |
4104 | Serge | 118 | } |
119 | |||
4280 | Serge | 120 | static void intel_crt_get_config(struct intel_encoder *encoder, |
6084 | serge | 121 | struct intel_crtc_state *pipe_config) |
4280 | Serge | 122 | { |
4560 | Serge | 123 | struct drm_device *dev = encoder->base.dev; |
124 | int dotclock; |
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125 | |||
6084 | serge | 126 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
4560 | Serge | 127 | |
128 | dotclock = pipe_config->port_clock; |
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129 | |||
130 | if (HAS_PCH_SPLIT(dev)) |
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131 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
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132 | |||
6084 | serge | 133 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
4280 | Serge | 134 | } |
135 | |||
136 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
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6084 | serge | 137 | struct intel_crtc_state *pipe_config) |
4280 | Serge | 138 | { |
139 | intel_ddi_get_config(encoder, pipe_config); |
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140 | |||
6084 | serge | 141 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
4280 | Serge | 142 | DRM_MODE_FLAG_NHSYNC | |
143 | DRM_MODE_FLAG_PVSYNC | |
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144 | DRM_MODE_FLAG_NVSYNC); |
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6084 | serge | 145 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
4280 | Serge | 146 | } |
147 | |||
3031 | serge | 148 | /* Note: The caller is required to filter out dpms modes not supported by the |
149 | * platform. */ |
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150 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
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151 | { |
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152 | struct drm_device *dev = encoder->base.dev; |
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153 | struct drm_i915_private *dev_priv = dev->dev_private; |
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154 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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5060 | serge | 155 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
6084 | serge | 156 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
5060 | serge | 157 | u32 adpa; |
3031 | serge | 158 | |
5060 | serge | 159 | if (INTEL_INFO(dev)->gen >= 5) |
160 | adpa = ADPA_HOTPLUG_BITS; |
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161 | else |
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162 | adpa = 0; |
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3031 | serge | 163 | |
5060 | serge | 164 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
165 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
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166 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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167 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
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168 | |||
169 | /* For CPT allow 3 pipe config, for others just use A or B */ |
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170 | if (HAS_PCH_LPT(dev)) |
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171 | ; /* Those bits don't exist here */ |
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172 | else if (HAS_PCH_CPT(dev)) |
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173 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
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174 | else if (crtc->pipe == 0) |
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175 | adpa |= ADPA_PIPE_A_SELECT; |
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176 | else |
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177 | adpa |= ADPA_PIPE_B_SELECT; |
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178 | |||
179 | if (!HAS_PCH_SPLIT(dev)) |
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180 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
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181 | |||
2342 | Serge | 182 | switch (mode) { |
2330 | Serge | 183 | case DRM_MODE_DPMS_ON: |
5060 | serge | 184 | adpa |= ADPA_DAC_ENABLE; |
2330 | Serge | 185 | break; |
186 | case DRM_MODE_DPMS_STANDBY: |
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5060 | serge | 187 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
2330 | Serge | 188 | break; |
189 | case DRM_MODE_DPMS_SUSPEND: |
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5060 | serge | 190 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
2330 | Serge | 191 | break; |
192 | case DRM_MODE_DPMS_OFF: |
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5060 | serge | 193 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
2330 | Serge | 194 | break; |
195 | } |
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196 | |||
5060 | serge | 197 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 198 | } |
199 | |||
3480 | Serge | 200 | static void intel_disable_crt(struct intel_encoder *encoder) |
201 | { |
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202 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
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203 | } |
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204 | |||
6084 | serge | 205 | static void pch_disable_crt(struct intel_encoder *encoder) |
206 | { |
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207 | } |
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5060 | serge | 208 | |
6084 | serge | 209 | static void pch_post_disable_crt(struct intel_encoder *encoder) |
5060 | serge | 210 | { |
6084 | serge | 211 | intel_disable_crt(encoder); |
5060 | serge | 212 | } |
213 | |||
3480 | Serge | 214 | static void intel_enable_crt(struct intel_encoder *encoder) |
215 | { |
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216 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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217 | |||
218 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
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219 | } |
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220 | |||
4560 | Serge | 221 | static enum drm_mode_status |
222 | intel_crt_mode_valid(struct drm_connector *connector, |
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5060 | serge | 223 | struct drm_display_mode *mode) |
2330 | Serge | 224 | { |
225 | struct drm_device *dev = connector->dev; |
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226 | |||
227 | int max_clock = 0; |
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228 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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229 | return MODE_NO_DBLESCAN; |
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230 | |||
231 | if (mode->clock < 25000) |
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232 | return MODE_CLOCK_LOW; |
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233 | |||
234 | if (IS_GEN2(dev)) |
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235 | max_clock = 350000; |
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236 | else |
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237 | max_clock = 400000; |
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238 | if (mode->clock > max_clock) |
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239 | return MODE_CLOCK_HIGH; |
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240 | |||
3243 | Serge | 241 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
242 | if (HAS_PCH_LPT(dev) && |
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243 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
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244 | return MODE_CLOCK_HIGH; |
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245 | |||
2330 | Serge | 246 | return MODE_OK; |
247 | } |
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248 | |||
3746 | Serge | 249 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
6084 | serge | 250 | struct intel_crtc_state *pipe_config) |
2330 | Serge | 251 | { |
3746 | Serge | 252 | struct drm_device *dev = encoder->base.dev; |
253 | |||
254 | if (HAS_PCH_SPLIT(dev)) |
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255 | pipe_config->has_pch_encoder = true; |
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256 | |||
4104 | Serge | 257 | /* LPT FDI RX only supports 8bpc. */ |
6660 | serge | 258 | if (HAS_PCH_LPT(dev)) { |
259 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
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260 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); |
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261 | return false; |
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262 | } |
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263 | |||
4104 | Serge | 264 | pipe_config->pipe_bpp = 24; |
6660 | serge | 265 | } |
4104 | Serge | 266 | |
5060 | serge | 267 | /* FDI must always be 2.7 GHz */ |
268 | if (HAS_DDI(dev)) { |
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269 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
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270 | pipe_config->port_clock = 135000 * 2; |
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6084 | serge | 271 | |
272 | pipe_config->dpll_hw_state.wrpll = 0; |
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273 | pipe_config->dpll_hw_state.spll = |
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274 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
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5060 | serge | 275 | } |
276 | |||
2330 | Serge | 277 | return true; |
278 | } |
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279 | |||
280 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
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281 | { |
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282 | struct drm_device *dev = connector->dev; |
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283 | struct intel_crt *crt = intel_attached_crt(connector); |
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284 | struct drm_i915_private *dev_priv = dev->dev_private; |
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285 | u32 adpa; |
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286 | bool ret; |
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287 | |||
288 | /* The first time through, trigger an explicit detection cycle */ |
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289 | if (crt->force_hotplug_required) { |
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290 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
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291 | u32 save_adpa; |
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292 | |||
293 | crt->force_hotplug_required = 0; |
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294 | |||
3480 | Serge | 295 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 296 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
297 | |||
298 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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299 | if (turn_off_dac) |
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300 | adpa &= ~ADPA_DAC_ENABLE; |
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301 | |||
3480 | Serge | 302 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 303 | |
3480 | Serge | 304 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
2330 | Serge | 305 | 1000)) |
306 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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307 | |||
308 | if (turn_off_dac) { |
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3480 | Serge | 309 | I915_WRITE(crt->adpa_reg, save_adpa); |
310 | POSTING_READ(crt->adpa_reg); |
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2330 | Serge | 311 | } |
312 | } |
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313 | |||
314 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 315 | adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 316 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
317 | ret = true; |
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318 | else |
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319 | ret = false; |
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320 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
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321 | |||
322 | return ret; |
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323 | } |
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324 | |||
3031 | serge | 325 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
326 | { |
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327 | struct drm_device *dev = connector->dev; |
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3480 | Serge | 328 | struct intel_crt *crt = intel_attached_crt(connector); |
3031 | serge | 329 | struct drm_i915_private *dev_priv = dev->dev_private; |
330 | u32 adpa; |
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331 | bool ret; |
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332 | u32 save_adpa; |
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333 | |||
3480 | Serge | 334 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 335 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
336 | |||
337 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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338 | |||
3480 | Serge | 339 | I915_WRITE(crt->adpa_reg, adpa); |
3031 | serge | 340 | |
3480 | Serge | 341 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
3031 | serge | 342 | 1000)) { |
343 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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3480 | Serge | 344 | I915_WRITE(crt->adpa_reg, save_adpa); |
3031 | serge | 345 | } |
346 | |||
347 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 348 | adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 349 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
350 | ret = true; |
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351 | else |
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352 | ret = false; |
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353 | |||
354 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
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355 | |||
356 | return ret; |
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357 | } |
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358 | |||
2330 | Serge | 359 | /** |
360 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
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361 | * |
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362 | * Not for i915G/i915GM |
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363 | * |
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364 | * \return true if CRT is connected. |
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365 | * \return false if CRT is disconnected. |
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366 | */ |
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367 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
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368 | { |
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369 | struct drm_device *dev = connector->dev; |
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370 | struct drm_i915_private *dev_priv = dev->dev_private; |
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6084 | serge | 371 | u32 stat; |
2330 | Serge | 372 | bool ret = false; |
373 | int i, tries = 0; |
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374 | |||
375 | if (HAS_PCH_SPLIT(dev)) |
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376 | return intel_ironlake_crt_detect_hotplug(connector); |
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377 | |||
3031 | serge | 378 | if (IS_VALLEYVIEW(dev)) |
379 | return valleyview_crt_detect_hotplug(connector); |
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380 | |||
2330 | Serge | 381 | /* |
382 | * On 4 series desktop, CRT detect sequence need to be done twice |
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383 | * to get a reliable result. |
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384 | */ |
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385 | |||
386 | if (IS_G4X(dev) && !IS_GM45(dev)) |
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387 | tries = 2; |
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388 | else |
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389 | tries = 1; |
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390 | |||
391 | for (i = 0; i < tries ; i++) { |
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392 | /* turn on the FORCE_DETECT */ |
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6084 | serge | 393 | i915_hotplug_interrupt_update(dev_priv, |
394 | CRT_HOTPLUG_FORCE_DETECT, |
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395 | CRT_HOTPLUG_FORCE_DETECT); |
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2330 | Serge | 396 | /* wait for FORCE_DETECT to go off */ |
397 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
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398 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
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399 | 1000)) |
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400 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
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401 | } |
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402 | |||
403 | stat = I915_READ(PORT_HOTPLUG_STAT); |
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404 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
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405 | ret = true; |
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406 | |||
407 | /* clear the interrupt we just generated, if any */ |
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408 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
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409 | |||
6084 | serge | 410 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
2330 | Serge | 411 | |
412 | return ret; |
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413 | } |
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414 | |||
3031 | serge | 415 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
416 | struct i2c_adapter *i2c) |
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417 | { |
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418 | struct edid *edid; |
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419 | |||
420 | edid = drm_get_edid(connector, i2c); |
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421 | |||
422 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
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423 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
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424 | intel_gmbus_force_bit(i2c, true); |
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425 | edid = drm_get_edid(connector, i2c); |
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426 | intel_gmbus_force_bit(i2c, false); |
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427 | } |
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428 | |||
429 | return edid; |
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430 | } |
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431 | |||
432 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
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433 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
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434 | struct i2c_adapter *adapter) |
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435 | { |
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436 | struct edid *edid; |
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3243 | Serge | 437 | int ret; |
3031 | serge | 438 | |
439 | edid = intel_crt_get_edid(connector, adapter); |
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440 | if (!edid) |
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441 | return 0; |
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442 | |||
3243 | Serge | 443 | ret = intel_connector_update_modes(connector, edid); |
444 | kfree(edid); |
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445 | |||
446 | return ret; |
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3031 | serge | 447 | } |
448 | |||
2330 | Serge | 449 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
450 | { |
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451 | struct intel_crt *crt = intel_attached_crt(connector); |
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452 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
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3031 | serge | 453 | struct edid *edid; |
454 | struct i2c_adapter *i2c; |
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2330 | Serge | 455 | |
3031 | serge | 456 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
2330 | Serge | 457 | |
4104 | Serge | 458 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 459 | edid = intel_crt_get_edid(connector, i2c); |
2330 | Serge | 460 | |
3031 | serge | 461 | if (edid) { |
462 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
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463 | |||
2330 | Serge | 464 | /* |
465 | * This may be a DVI-I connector with a shared DDC |
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466 | * link between analog and digital outputs, so we |
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467 | * have to check the EDID input spec of the attached device. |
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468 | */ |
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469 | if (!is_digital) { |
||
470 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
||
6937 | serge | 471 | return true; |
472 | } |
||
473 | |||
6935 | serge | 474 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
5060 | serge | 475 | } else { |
3031 | serge | 476 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
5060 | serge | 477 | } |
2330 | Serge | 478 | |
3031 | serge | 479 | kfree(edid); |
480 | |||
6937 | serge | 481 | return false; |
2330 | Serge | 482 | } |
483 | |||
484 | static enum drm_connector_status |
||
485 | intel_crt_load_detect(struct intel_crt *crt) |
||
486 | { |
||
487 | struct drm_device *dev = crt->base.base.dev; |
||
488 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
489 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
||
490 | uint32_t save_bclrpat; |
||
491 | uint32_t save_vtotal; |
||
492 | uint32_t vtotal, vactive; |
||
493 | uint32_t vsample; |
||
494 | uint32_t vblank, vblank_start, vblank_end; |
||
495 | uint32_t dsl; |
||
6937 | serge | 496 | i915_reg_t bclrpat_reg, vtotal_reg, |
497 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; |
||
2330 | Serge | 498 | uint8_t st00; |
499 | enum drm_connector_status status; |
||
500 | |||
501 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
||
502 | |||
503 | bclrpat_reg = BCLRPAT(pipe); |
||
504 | vtotal_reg = VTOTAL(pipe); |
||
505 | vblank_reg = VBLANK(pipe); |
||
506 | vsync_reg = VSYNC(pipe); |
||
507 | pipeconf_reg = PIPECONF(pipe); |
||
508 | pipe_dsl_reg = PIPEDSL(pipe); |
||
509 | |||
510 | save_bclrpat = I915_READ(bclrpat_reg); |
||
511 | save_vtotal = I915_READ(vtotal_reg); |
||
512 | vblank = I915_READ(vblank_reg); |
||
513 | |||
514 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
||
515 | vactive = (save_vtotal & 0x7ff) + 1; |
||
516 | |||
517 | vblank_start = (vblank & 0xfff) + 1; |
||
518 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
||
519 | |||
520 | /* Set the border color to purple. */ |
||
521 | I915_WRITE(bclrpat_reg, 0x500050); |
||
522 | |||
523 | if (!IS_GEN2(dev)) { |
||
524 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
||
525 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
||
526 | POSTING_READ(pipeconf_reg); |
||
527 | /* Wait for next Vblank to substitue |
||
528 | * border color for Color info */ |
||
529 | intel_wait_for_vblank(dev, pipe); |
||
6937 | serge | 530 | st00 = I915_READ8(_VGA_MSR_WRITE); |
2330 | Serge | 531 | status = ((st00 & (1 << 4)) != 0) ? |
532 | connector_status_connected : |
||
533 | connector_status_disconnected; |
||
534 | |||
535 | I915_WRITE(pipeconf_reg, pipeconf); |
||
536 | } else { |
||
537 | bool restore_vblank = false; |
||
538 | int count, detect; |
||
539 | |||
540 | /* |
||
541 | * If there isn't any border, add some. |
||
542 | * Yes, this will flicker |
||
543 | */ |
||
544 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
||
545 | uint32_t vsync = I915_READ(vsync_reg); |
||
546 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
||
547 | |||
548 | vblank_start = vsync_start; |
||
549 | I915_WRITE(vblank_reg, |
||
550 | (vblank_start - 1) | |
||
551 | ((vblank_end - 1) << 16)); |
||
552 | restore_vblank = true; |
||
553 | } |
||
554 | /* sample in the vertical border, selecting the larger one */ |
||
555 | if (vblank_start - vactive >= vtotal - vblank_end) |
||
556 | vsample = (vblank_start + vactive) >> 1; |
||
557 | else |
||
558 | vsample = (vtotal + vblank_end) >> 1; |
||
559 | |||
560 | /* |
||
561 | * Wait for the border to be displayed |
||
562 | */ |
||
563 | while (I915_READ(pipe_dsl_reg) >= vactive) |
||
564 | ; |
||
565 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
||
566 | ; |
||
567 | /* |
||
568 | * Watch ST00 for an entire scanline |
||
569 | */ |
||
570 | detect = 0; |
||
571 | count = 0; |
||
572 | do { |
||
573 | count++; |
||
574 | /* Read the ST00 VGA status register */ |
||
6937 | serge | 575 | st00 = I915_READ8(_VGA_MSR_WRITE); |
2330 | Serge | 576 | if (st00 & (1 << 4)) |
577 | detect++; |
||
578 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
||
579 | |||
580 | /* restore vblank if necessary */ |
||
581 | if (restore_vblank) |
||
582 | I915_WRITE(vblank_reg, vblank); |
||
583 | /* |
||
584 | * If more than 3/4 of the scanline detected a monitor, |
||
585 | * then it is assumed to be present. This works even on i830, |
||
586 | * where there isn't any way to force the border color across |
||
587 | * the screen |
||
588 | */ |
||
589 | status = detect * 4 > count * 3 ? |
||
590 | connector_status_connected : |
||
591 | connector_status_disconnected; |
||
592 | } |
||
593 | |||
594 | /* Restore previous settings */ |
||
595 | I915_WRITE(bclrpat_reg, save_bclrpat); |
||
596 | |||
597 | return status; |
||
598 | } |
||
599 | |||
600 | static enum drm_connector_status |
||
601 | intel_crt_detect(struct drm_connector *connector, bool force) |
||
602 | { |
||
603 | struct drm_device *dev = connector->dev; |
||
5060 | serge | 604 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 605 | struct intel_crt *crt = intel_attached_crt(connector); |
5060 | serge | 606 | struct intel_encoder *intel_encoder = &crt->base; |
607 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 608 | enum drm_connector_status status; |
3031 | serge | 609 | struct intel_load_detect_pipe tmp; |
5060 | serge | 610 | struct drm_modeset_acquire_ctx ctx; |
2330 | Serge | 611 | |
4104 | Serge | 612 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
5060 | serge | 613 | connector->base.id, connector->name, |
4104 | Serge | 614 | force); |
615 | |||
5060 | serge | 616 | power_domain = intel_display_port_power_domain(intel_encoder); |
617 | intel_display_power_get(dev_priv, power_domain); |
||
618 | |||
2330 | Serge | 619 | if (I915_HAS_HOTPLUG(dev)) { |
3031 | serge | 620 | /* We can not rely on the HPD pin always being correctly wired |
621 | * up, for example many KVM do not pass it through, and so |
||
622 | * only trust an assertion that the monitor is connected. |
||
623 | */ |
||
2330 | Serge | 624 | if (intel_crt_detect_hotplug(connector)) { |
625 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
||
5060 | serge | 626 | status = connector_status_connected; |
627 | goto out; |
||
3031 | serge | 628 | } else |
2330 | Serge | 629 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
630 | } |
||
631 | |||
5060 | serge | 632 | if (intel_crt_detect_ddc(connector)) { |
633 | status = connector_status_connected; |
||
634 | goto out; |
||
635 | } |
||
2330 | Serge | 636 | |
3031 | serge | 637 | /* Load detection is broken on HPD capable machines. Whoever wants a |
638 | * broken monitor (without edid) to work behind a broken kvm (that fails |
||
639 | * to have the right resistors for HP detection) needs to fix this up. |
||
640 | * For now just bail out. */ |
||
6084 | serge | 641 | if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { |
5060 | serge | 642 | status = connector_status_disconnected; |
643 | goto out; |
||
644 | } |
||
3031 | serge | 645 | |
5060 | serge | 646 | if (!force) { |
647 | status = connector->status; |
||
648 | goto out; |
||
649 | } |
||
2330 | Serge | 650 | |
5060 | serge | 651 | drm_modeset_acquire_init(&ctx, 0); |
652 | |||
2330 | Serge | 653 | /* for pre-945g platforms use load detect */ |
5060 | serge | 654 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
655 | if (intel_crt_detect_ddc(connector)) |
||
656 | status = connector_status_connected; |
||
6084 | serge | 657 | else if (INTEL_INFO(dev)->gen < 4) |
658 | status = intel_crt_load_detect(crt); |
||
5060 | serge | 659 | else |
6084 | serge | 660 | status = connector_status_unknown; |
661 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
||
5060 | serge | 662 | } else |
663 | status = connector_status_unknown; |
||
2330 | Serge | 664 | |
5060 | serge | 665 | drm_modeset_drop_locks(&ctx); |
666 | drm_modeset_acquire_fini(&ctx); |
||
667 | |||
668 | out: |
||
669 | intel_display_power_put(dev_priv, power_domain); |
||
2330 | Serge | 670 | return status; |
671 | } |
||
672 | |||
673 | static void intel_crt_destroy(struct drm_connector *connector) |
||
674 | { |
||
675 | drm_connector_cleanup(connector); |
||
676 | kfree(connector); |
||
677 | } |
||
678 | |||
679 | static int intel_crt_get_modes(struct drm_connector *connector) |
||
680 | { |
||
681 | struct drm_device *dev = connector->dev; |
||
682 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5060 | serge | 683 | struct intel_crt *crt = intel_attached_crt(connector); |
684 | struct intel_encoder *intel_encoder = &crt->base; |
||
685 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 686 | int ret; |
3031 | serge | 687 | struct i2c_adapter *i2c; |
2330 | Serge | 688 | |
5060 | serge | 689 | power_domain = intel_display_port_power_domain(intel_encoder); |
690 | intel_display_power_get(dev_priv, power_domain); |
||
691 | |||
4104 | Serge | 692 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 693 | ret = intel_crt_ddc_get_modes(connector, i2c); |
2330 | Serge | 694 | if (ret || !IS_G4X(dev)) |
5060 | serge | 695 | goto out; |
2330 | Serge | 696 | |
697 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
||
6084 | serge | 698 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
5060 | serge | 699 | ret = intel_crt_ddc_get_modes(connector, i2c); |
700 | |||
701 | out: |
||
702 | intel_display_power_put(dev_priv, power_domain); |
||
703 | |||
704 | return ret; |
||
2330 | Serge | 705 | } |
706 | |||
707 | static int intel_crt_set_property(struct drm_connector *connector, |
||
708 | struct drm_property *property, |
||
709 | uint64_t value) |
||
710 | { |
||
711 | return 0; |
||
712 | } |
||
713 | |||
714 | static void intel_crt_reset(struct drm_connector *connector) |
||
715 | { |
||
716 | struct drm_device *dev = connector->dev; |
||
3243 | Serge | 717 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 718 | struct intel_crt *crt = intel_attached_crt(connector); |
719 | |||
4104 | Serge | 720 | if (INTEL_INFO(dev)->gen >= 5) { |
3243 | Serge | 721 | u32 adpa; |
722 | |||
3480 | Serge | 723 | adpa = I915_READ(crt->adpa_reg); |
3243 | Serge | 724 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
725 | adpa |= ADPA_HOTPLUG_BITS; |
||
3480 | Serge | 726 | I915_WRITE(crt->adpa_reg, adpa); |
727 | POSTING_READ(crt->adpa_reg); |
||
3243 | Serge | 728 | |
5354 | serge | 729 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
2330 | Serge | 730 | crt->force_hotplug_required = 1; |
3243 | Serge | 731 | } |
732 | |||
2330 | Serge | 733 | } |
734 | |||
735 | /* |
||
736 | * Routines for controlling stuff on the analog port |
||
737 | */ |
||
738 | |||
739 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
||
740 | .reset = intel_crt_reset, |
||
6084 | serge | 741 | .dpms = drm_atomic_helper_connector_dpms, |
2330 | Serge | 742 | .detect = intel_crt_detect, |
743 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
744 | .destroy = intel_crt_destroy, |
||
745 | .set_property = intel_crt_set_property, |
||
6084 | serge | 746 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
747 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
||
748 | .atomic_get_property = intel_connector_atomic_get_property, |
||
2330 | Serge | 749 | }; |
750 | |||
751 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
||
752 | .mode_valid = intel_crt_mode_valid, |
||
753 | .get_modes = intel_crt_get_modes, |
||
754 | .best_encoder = intel_best_encoder, |
||
755 | }; |
||
756 | |||
757 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
||
758 | .destroy = intel_encoder_destroy, |
||
759 | }; |
||
760 | |||
5097 | serge | 761 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
762 | { |
||
763 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
||
764 | return 1; |
||
765 | } |
||
766 | |||
767 | static const struct dmi_system_id intel_no_crt[] = { |
||
768 | { |
||
769 | .callback = intel_no_crt_dmi_callback, |
||
770 | .ident = "ACER ZGB", |
||
771 | .matches = { |
||
772 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
||
773 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
||
774 | }, |
||
775 | }, |
||
776 | { |
||
777 | .callback = intel_no_crt_dmi_callback, |
||
778 | .ident = "DELL XPS 8700", |
||
779 | .matches = { |
||
780 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
||
781 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), |
||
782 | }, |
||
783 | }, |
||
784 | { } |
||
785 | }; |
||
786 | |||
2330 | Serge | 787 | void intel_crt_init(struct drm_device *dev) |
788 | { |
||
789 | struct drm_connector *connector; |
||
790 | struct intel_crt *crt; |
||
791 | struct intel_connector *intel_connector; |
||
792 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6937 | serge | 793 | i915_reg_t adpa_reg; |
794 | u32 adpa; |
||
2330 | Serge | 795 | |
5097 | serge | 796 | /* Skip machines without VGA that falsely report hotplug events */ |
797 | if (dmi_check_system(intel_no_crt)) |
||
798 | return; |
||
799 | |||
6937 | serge | 800 | if (HAS_PCH_SPLIT(dev)) |
801 | adpa_reg = PCH_ADPA; |
||
802 | else if (IS_VALLEYVIEW(dev)) |
||
803 | adpa_reg = VLV_ADPA; |
||
804 | else |
||
805 | adpa_reg = ADPA; |
||
806 | |||
807 | adpa = I915_READ(adpa_reg); |
||
808 | if ((adpa & ADPA_DAC_ENABLE) == 0) { |
||
809 | /* |
||
810 | * On some machines (some IVB at least) CRT can be |
||
811 | * fused off, but there's no known fuse bit to |
||
812 | * indicate that. On these machine the ADPA register |
||
813 | * works normally, except the DAC enable bit won't |
||
814 | * take. So the only way to tell is attempt to enable |
||
815 | * it and see what happens. |
||
816 | */ |
||
817 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | |
||
818 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
||
819 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) |
||
820 | return; |
||
821 | I915_WRITE(adpa_reg, adpa); |
||
822 | } |
||
823 | |||
2330 | Serge | 824 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
825 | if (!crt) |
||
826 | return; |
||
827 | |||
6084 | serge | 828 | intel_connector = intel_connector_alloc(); |
2330 | Serge | 829 | if (!intel_connector) { |
830 | kfree(crt); |
||
831 | return; |
||
832 | } |
||
833 | |||
834 | connector = &intel_connector->base; |
||
3480 | Serge | 835 | crt->connector = intel_connector; |
2330 | Serge | 836 | drm_connector_init(dev, &intel_connector->base, |
837 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
||
838 | |||
839 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
||
6937 | serge | 840 | DRM_MODE_ENCODER_DAC, NULL); |
2330 | Serge | 841 | |
842 | intel_connector_attach_encoder(intel_connector, &crt->base); |
||
843 | |||
844 | crt->base.type = INTEL_OUTPUT_ANALOG; |
||
5060 | serge | 845 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
3243 | Serge | 846 | if (IS_I830(dev)) |
3031 | serge | 847 | crt->base.crtc_mask = (1 << 0); |
848 | else |
||
849 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
850 | |||
851 | if (IS_GEN2(dev)) |
||
852 | connector->interlace_allowed = 0; |
||
853 | else |
||
6084 | serge | 854 | connector->interlace_allowed = 1; |
2330 | Serge | 855 | connector->doublescan_allowed = 0; |
856 | |||
6937 | serge | 857 | crt->adpa_reg = adpa_reg; |
3031 | serge | 858 | |
3746 | Serge | 859 | crt->base.compute_config = intel_crt_compute_config; |
6937 | serge | 860 | if (HAS_PCH_SPLIT(dev)) { |
6084 | serge | 861 | crt->base.disable = pch_disable_crt; |
862 | crt->base.post_disable = pch_post_disable_crt; |
||
863 | } else { |
||
864 | crt->base.disable = intel_disable_crt; |
||
865 | } |
||
3031 | serge | 866 | crt->base.enable = intel_enable_crt; |
3746 | Serge | 867 | if (I915_HAS_HOTPLUG(dev)) |
868 | crt->base.hpd_pin = HPD_CRT; |
||
4560 | Serge | 869 | if (HAS_DDI(dev)) { |
870 | crt->base.get_config = hsw_crt_get_config; |
||
3243 | Serge | 871 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
4560 | Serge | 872 | } else { |
873 | crt->base.get_config = intel_crt_get_config; |
||
6084 | serge | 874 | crt->base.get_hw_state = intel_crt_get_hw_state; |
4560 | Serge | 875 | } |
3031 | serge | 876 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5060 | serge | 877 | intel_connector->unregister = intel_connector_unregister; |
3031 | serge | 878 | |
2330 | Serge | 879 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
880 | |||
5060 | serge | 881 | drm_connector_register(connector); |
2330 | Serge | 882 | |
3746 | Serge | 883 | if (!I915_HAS_HOTPLUG(dev)) |
884 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
||
2330 | Serge | 885 | |
886 | /* |
||
887 | * Configure the automatic hotplug detection stuff |
||
888 | */ |
||
889 | crt->force_hotplug_required = 0; |
||
890 | |||
3243 | Serge | 891 | /* |
3480 | Serge | 892 | * TODO: find a proper way to discover whether we need to set the the |
893 | * polarity and link reversal bits or not, instead of relying on the |
||
894 | * BIOS. |
||
3243 | Serge | 895 | */ |
3480 | Serge | 896 | if (HAS_PCH_LPT(dev)) { |
897 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
||
898 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
||
899 | |||
6084 | serge | 900 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3480 | Serge | 901 | } |
5060 | serge | 902 | |
903 | intel_crt_reset(connector); |
||
2330 | Serge | 904 | }><>><>><>><>><>><>>><>=>><>=>><>>>> |