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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | */ |
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26 | |||
5097 | serge | 27 | #include |
2330 | Serge | 28 | #include |
29 | #include |
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3031 | serge | 30 | #include |
31 | #include |
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32 | #include |
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33 | #include |
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2330 | Serge | 34 | #include "intel_drv.h" |
3031 | serge | 35 | #include |
2330 | Serge | 36 | #include "i915_drv.h" |
37 | |||
38 | /* Here's the desired hotplug mode */ |
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39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
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40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
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41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
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42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
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43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
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44 | ADPA_CRT_HOTPLUG_ENABLE) |
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45 | |||
46 | struct intel_crt { |
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47 | struct intel_encoder base; |
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3480 | Serge | 48 | /* DPMS state is stored in the connector, which we need in the |
49 | * encoder's enable/disable callbacks */ |
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50 | struct intel_connector *connector; |
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2330 | Serge | 51 | bool force_hotplug_required; |
3031 | serge | 52 | u32 adpa_reg; |
2330 | Serge | 53 | }; |
54 | |||
4104 | Serge | 55 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
2330 | Serge | 56 | { |
4104 | Serge | 57 | return container_of(encoder, struct intel_crt, base); |
2330 | Serge | 58 | } |
59 | |||
4104 | Serge | 60 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
2330 | Serge | 61 | { |
4104 | Serge | 62 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
3031 | serge | 63 | } |
64 | |||
65 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
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66 | enum pipe *pipe) |
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67 | { |
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68 | struct drm_device *dev = encoder->base.dev; |
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2330 | Serge | 69 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 70 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
5060 | serge | 71 | enum intel_display_power_domain power_domain; |
3031 | serge | 72 | u32 tmp; |
2330 | Serge | 73 | |
5060 | serge | 74 | power_domain = intel_display_port_power_domain(encoder); |
75 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
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76 | return false; |
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77 | |||
3031 | serge | 78 | tmp = I915_READ(crt->adpa_reg); |
79 | |||
80 | if (!(tmp & ADPA_DAC_ENABLE)) |
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81 | return false; |
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82 | |||
83 | if (HAS_PCH_CPT(dev)) |
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84 | *pipe = PORT_TO_PIPE_CPT(tmp); |
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2330 | Serge | 85 | else |
3031 | serge | 86 | *pipe = PORT_TO_PIPE(tmp); |
2330 | Serge | 87 | |
3031 | serge | 88 | return true; |
89 | } |
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90 | |||
4280 | Serge | 91 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
4104 | Serge | 92 | { |
93 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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94 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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95 | u32 tmp, flags = 0; |
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96 | |||
97 | tmp = I915_READ(crt->adpa_reg); |
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98 | |||
99 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
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100 | flags |= DRM_MODE_FLAG_PHSYNC; |
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101 | else |
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102 | flags |= DRM_MODE_FLAG_NHSYNC; |
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103 | |||
104 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
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105 | flags |= DRM_MODE_FLAG_PVSYNC; |
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106 | else |
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107 | flags |= DRM_MODE_FLAG_NVSYNC; |
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108 | |||
4280 | Serge | 109 | return flags; |
4104 | Serge | 110 | } |
111 | |||
4280 | Serge | 112 | static void intel_crt_get_config(struct intel_encoder *encoder, |
113 | struct intel_crtc_config *pipe_config) |
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114 | { |
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4560 | Serge | 115 | struct drm_device *dev = encoder->base.dev; |
116 | int dotclock; |
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117 | |||
4280 | Serge | 118 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
4560 | Serge | 119 | |
120 | dotclock = pipe_config->port_clock; |
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121 | |||
122 | if (HAS_PCH_SPLIT(dev)) |
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123 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
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124 | |||
125 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
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4280 | Serge | 126 | } |
127 | |||
128 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
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129 | struct intel_crtc_config *pipe_config) |
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130 | { |
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131 | intel_ddi_get_config(encoder, pipe_config); |
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132 | |||
133 | pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
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134 | DRM_MODE_FLAG_NHSYNC | |
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135 | DRM_MODE_FLAG_PVSYNC | |
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136 | DRM_MODE_FLAG_NVSYNC); |
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137 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
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138 | } |
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139 | |||
5060 | serge | 140 | static void hsw_crt_pre_enable(struct intel_encoder *encoder) |
141 | { |
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142 | struct drm_device *dev = encoder->base.dev; |
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143 | struct drm_i915_private *dev_priv = dev->dev_private; |
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144 | |||
145 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); |
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146 | I915_WRITE(SPLL_CTL, |
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147 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); |
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148 | POSTING_READ(SPLL_CTL); |
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149 | udelay(20); |
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150 | } |
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151 | |||
3031 | serge | 152 | /* Note: The caller is required to filter out dpms modes not supported by the |
153 | * platform. */ |
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154 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
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155 | { |
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156 | struct drm_device *dev = encoder->base.dev; |
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157 | struct drm_i915_private *dev_priv = dev->dev_private; |
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158 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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5060 | serge | 159 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
160 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
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161 | u32 adpa; |
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3031 | serge | 162 | |
5060 | serge | 163 | if (INTEL_INFO(dev)->gen >= 5) |
164 | adpa = ADPA_HOTPLUG_BITS; |
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165 | else |
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166 | adpa = 0; |
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3031 | serge | 167 | |
5060 | serge | 168 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
169 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
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170 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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171 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
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172 | |||
173 | /* For CPT allow 3 pipe config, for others just use A or B */ |
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174 | if (HAS_PCH_LPT(dev)) |
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175 | ; /* Those bits don't exist here */ |
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176 | else if (HAS_PCH_CPT(dev)) |
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177 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
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178 | else if (crtc->pipe == 0) |
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179 | adpa |= ADPA_PIPE_A_SELECT; |
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180 | else |
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181 | adpa |= ADPA_PIPE_B_SELECT; |
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182 | |||
183 | if (!HAS_PCH_SPLIT(dev)) |
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184 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
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185 | |||
2342 | Serge | 186 | switch (mode) { |
2330 | Serge | 187 | case DRM_MODE_DPMS_ON: |
5060 | serge | 188 | adpa |= ADPA_DAC_ENABLE; |
2330 | Serge | 189 | break; |
190 | case DRM_MODE_DPMS_STANDBY: |
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5060 | serge | 191 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
2330 | Serge | 192 | break; |
193 | case DRM_MODE_DPMS_SUSPEND: |
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5060 | serge | 194 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
2330 | Serge | 195 | break; |
196 | case DRM_MODE_DPMS_OFF: |
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5060 | serge | 197 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
2330 | Serge | 198 | break; |
199 | } |
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200 | |||
5060 | serge | 201 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 202 | } |
203 | |||
3480 | Serge | 204 | static void intel_disable_crt(struct intel_encoder *encoder) |
205 | { |
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206 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
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207 | } |
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208 | |||
5060 | serge | 209 | |
210 | static void hsw_crt_post_disable(struct intel_encoder *encoder) |
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211 | { |
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212 | struct drm_device *dev = encoder->base.dev; |
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213 | struct drm_i915_private *dev_priv = dev->dev_private; |
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214 | uint32_t val; |
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215 | |||
216 | DRM_DEBUG_KMS("Disabling SPLL\n"); |
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217 | val = I915_READ(SPLL_CTL); |
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218 | WARN_ON(!(val & SPLL_PLL_ENABLE)); |
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219 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
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220 | POSTING_READ(SPLL_CTL); |
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221 | } |
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222 | |||
3480 | Serge | 223 | static void intel_enable_crt(struct intel_encoder *encoder) |
224 | { |
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225 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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226 | |||
227 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
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228 | } |
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229 | |||
4104 | Serge | 230 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
3031 | serge | 231 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
232 | { |
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233 | struct drm_device *dev = connector->dev; |
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234 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
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235 | struct drm_crtc *crtc; |
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236 | int old_dpms; |
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237 | |||
238 | /* PCH platforms and VLV only support on/off. */ |
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3120 | serge | 239 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
3031 | serge | 240 | mode = DRM_MODE_DPMS_OFF; |
241 | |||
242 | if (mode == connector->dpms) |
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243 | return; |
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244 | |||
245 | old_dpms = connector->dpms; |
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246 | connector->dpms = mode; |
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247 | |||
248 | /* Only need to change hw state when actually enabled */ |
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249 | crtc = encoder->base.crtc; |
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250 | if (!crtc) { |
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251 | encoder->connectors_active = false; |
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252 | return; |
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253 | } |
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254 | |||
255 | /* We need the pipe to run for anything but OFF. */ |
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256 | if (mode == DRM_MODE_DPMS_OFF) |
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257 | encoder->connectors_active = false; |
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258 | else |
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259 | encoder->connectors_active = true; |
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260 | |||
4104 | Serge | 261 | /* We call connector dpms manually below in case pipe dpms doesn't |
262 | * change due to cloning. */ |
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3031 | serge | 263 | if (mode < old_dpms) { |
264 | /* From off to on, enable the pipe first. */ |
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265 | intel_crtc_update_dpms(crtc); |
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266 | |||
267 | intel_crt_set_dpms(encoder, mode); |
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268 | } else { |
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269 | intel_crt_set_dpms(encoder, mode); |
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270 | |||
271 | intel_crtc_update_dpms(crtc); |
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272 | } |
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273 | |||
274 | intel_modeset_check_state(connector->dev); |
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275 | } |
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276 | |||
4560 | Serge | 277 | static enum drm_mode_status |
278 | intel_crt_mode_valid(struct drm_connector *connector, |
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5060 | serge | 279 | struct drm_display_mode *mode) |
2330 | Serge | 280 | { |
281 | struct drm_device *dev = connector->dev; |
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282 | |||
283 | int max_clock = 0; |
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284 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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285 | return MODE_NO_DBLESCAN; |
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286 | |||
287 | if (mode->clock < 25000) |
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288 | return MODE_CLOCK_LOW; |
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289 | |||
290 | if (IS_GEN2(dev)) |
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291 | max_clock = 350000; |
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292 | else |
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293 | max_clock = 400000; |
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294 | if (mode->clock > max_clock) |
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295 | return MODE_CLOCK_HIGH; |
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296 | |||
3243 | Serge | 297 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
298 | if (HAS_PCH_LPT(dev) && |
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299 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
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300 | return MODE_CLOCK_HIGH; |
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301 | |||
2330 | Serge | 302 | return MODE_OK; |
303 | } |
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304 | |||
3746 | Serge | 305 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
306 | struct intel_crtc_config *pipe_config) |
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2330 | Serge | 307 | { |
3746 | Serge | 308 | struct drm_device *dev = encoder->base.dev; |
309 | |||
310 | if (HAS_PCH_SPLIT(dev)) |
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311 | pipe_config->has_pch_encoder = true; |
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312 | |||
4104 | Serge | 313 | /* LPT FDI RX only supports 8bpc. */ |
314 | if (HAS_PCH_LPT(dev)) |
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315 | pipe_config->pipe_bpp = 24; |
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316 | |||
5060 | serge | 317 | /* FDI must always be 2.7 GHz */ |
318 | if (HAS_DDI(dev)) { |
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319 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
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320 | pipe_config->port_clock = 135000 * 2; |
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321 | } |
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322 | |||
2330 | Serge | 323 | return true; |
324 | } |
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325 | |||
326 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
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327 | { |
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328 | struct drm_device *dev = connector->dev; |
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329 | struct intel_crt *crt = intel_attached_crt(connector); |
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330 | struct drm_i915_private *dev_priv = dev->dev_private; |
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331 | u32 adpa; |
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332 | bool ret; |
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333 | |||
334 | /* The first time through, trigger an explicit detection cycle */ |
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335 | if (crt->force_hotplug_required) { |
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336 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
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337 | u32 save_adpa; |
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338 | |||
339 | crt->force_hotplug_required = 0; |
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340 | |||
3480 | Serge | 341 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 342 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
343 | |||
344 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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345 | if (turn_off_dac) |
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346 | adpa &= ~ADPA_DAC_ENABLE; |
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347 | |||
3480 | Serge | 348 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 349 | |
3480 | Serge | 350 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
2330 | Serge | 351 | 1000)) |
352 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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353 | |||
354 | if (turn_off_dac) { |
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3480 | Serge | 355 | I915_WRITE(crt->adpa_reg, save_adpa); |
356 | POSTING_READ(crt->adpa_reg); |
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2330 | Serge | 357 | } |
358 | } |
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359 | |||
360 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 361 | adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 362 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
363 | ret = true; |
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364 | else |
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365 | ret = false; |
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366 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
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367 | |||
368 | return ret; |
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369 | } |
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370 | |||
3031 | serge | 371 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
372 | { |
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373 | struct drm_device *dev = connector->dev; |
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3480 | Serge | 374 | struct intel_crt *crt = intel_attached_crt(connector); |
3031 | serge | 375 | struct drm_i915_private *dev_priv = dev->dev_private; |
376 | u32 adpa; |
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377 | bool ret; |
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378 | u32 save_adpa; |
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379 | |||
3480 | Serge | 380 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 381 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
382 | |||
383 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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384 | |||
3480 | Serge | 385 | I915_WRITE(crt->adpa_reg, adpa); |
3031 | serge | 386 | |
3480 | Serge | 387 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
3031 | serge | 388 | 1000)) { |
389 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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3480 | Serge | 390 | I915_WRITE(crt->adpa_reg, save_adpa); |
3031 | serge | 391 | } |
392 | |||
393 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 394 | adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 395 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
396 | ret = true; |
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397 | else |
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398 | ret = false; |
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399 | |||
400 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
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401 | |||
402 | return ret; |
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403 | } |
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404 | |||
2330 | Serge | 405 | /** |
406 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
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407 | * |
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408 | * Not for i915G/i915GM |
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409 | * |
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410 | * \return true if CRT is connected. |
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411 | * \return false if CRT is disconnected. |
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412 | */ |
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413 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
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414 | { |
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415 | struct drm_device *dev = connector->dev; |
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416 | struct drm_i915_private *dev_priv = dev->dev_private; |
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417 | u32 hotplug_en, orig, stat; |
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418 | bool ret = false; |
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419 | int i, tries = 0; |
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420 | |||
421 | if (HAS_PCH_SPLIT(dev)) |
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422 | return intel_ironlake_crt_detect_hotplug(connector); |
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423 | |||
3031 | serge | 424 | if (IS_VALLEYVIEW(dev)) |
425 | return valleyview_crt_detect_hotplug(connector); |
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426 | |||
2330 | Serge | 427 | /* |
428 | * On 4 series desktop, CRT detect sequence need to be done twice |
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429 | * to get a reliable result. |
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430 | */ |
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431 | |||
432 | if (IS_G4X(dev) && !IS_GM45(dev)) |
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433 | tries = 2; |
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434 | else |
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435 | tries = 1; |
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436 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
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437 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
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438 | |||
439 | for (i = 0; i < tries ; i++) { |
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440 | /* turn on the FORCE_DETECT */ |
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441 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
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442 | /* wait for FORCE_DETECT to go off */ |
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443 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
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444 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
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445 | 1000)) |
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446 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
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447 | } |
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448 | |||
449 | stat = I915_READ(PORT_HOTPLUG_STAT); |
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450 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
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451 | ret = true; |
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452 | |||
453 | /* clear the interrupt we just generated, if any */ |
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454 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
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455 | |||
456 | /* and put the bits back */ |
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457 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
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458 | |||
459 | return ret; |
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460 | } |
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461 | |||
3031 | serge | 462 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
463 | struct i2c_adapter *i2c) |
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464 | { |
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465 | struct edid *edid; |
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466 | |||
467 | edid = drm_get_edid(connector, i2c); |
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468 | |||
469 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
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470 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
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471 | intel_gmbus_force_bit(i2c, true); |
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472 | edid = drm_get_edid(connector, i2c); |
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473 | intel_gmbus_force_bit(i2c, false); |
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474 | } |
||
475 | |||
476 | return edid; |
||
477 | } |
||
478 | |||
479 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
||
480 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
||
481 | struct i2c_adapter *adapter) |
||
482 | { |
||
483 | struct edid *edid; |
||
3243 | Serge | 484 | int ret; |
3031 | serge | 485 | |
486 | edid = intel_crt_get_edid(connector, adapter); |
||
487 | if (!edid) |
||
488 | return 0; |
||
489 | |||
3243 | Serge | 490 | ret = intel_connector_update_modes(connector, edid); |
491 | kfree(edid); |
||
492 | |||
493 | return ret; |
||
3031 | serge | 494 | } |
495 | |||
2330 | Serge | 496 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
497 | { |
||
498 | struct intel_crt *crt = intel_attached_crt(connector); |
||
499 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
||
3031 | serge | 500 | struct edid *edid; |
501 | struct i2c_adapter *i2c; |
||
2330 | Serge | 502 | |
3031 | serge | 503 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
2330 | Serge | 504 | |
4104 | Serge | 505 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 506 | edid = intel_crt_get_edid(connector, i2c); |
2330 | Serge | 507 | |
3031 | serge | 508 | if (edid) { |
509 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
||
510 | |||
2330 | Serge | 511 | /* |
512 | * This may be a DVI-I connector with a shared DDC |
||
513 | * link between analog and digital outputs, so we |
||
514 | * have to check the EDID input spec of the attached device. |
||
515 | */ |
||
516 | if (!is_digital) { |
||
517 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
||
518 | return true; |
||
3031 | serge | 519 | } |
520 | |||
521 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
||
5060 | serge | 522 | } else { |
3031 | serge | 523 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
5060 | serge | 524 | } |
2330 | Serge | 525 | |
3031 | serge | 526 | kfree(edid); |
527 | |||
2330 | Serge | 528 | return false; |
529 | } |
||
530 | |||
531 | static enum drm_connector_status |
||
532 | intel_crt_load_detect(struct intel_crt *crt) |
||
533 | { |
||
534 | struct drm_device *dev = crt->base.base.dev; |
||
535 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
536 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
||
537 | uint32_t save_bclrpat; |
||
538 | uint32_t save_vtotal; |
||
539 | uint32_t vtotal, vactive; |
||
540 | uint32_t vsample; |
||
541 | uint32_t vblank, vblank_start, vblank_end; |
||
542 | uint32_t dsl; |
||
543 | uint32_t bclrpat_reg; |
||
544 | uint32_t vtotal_reg; |
||
545 | uint32_t vblank_reg; |
||
546 | uint32_t vsync_reg; |
||
547 | uint32_t pipeconf_reg; |
||
548 | uint32_t pipe_dsl_reg; |
||
549 | uint8_t st00; |
||
550 | enum drm_connector_status status; |
||
551 | |||
552 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
||
553 | |||
554 | bclrpat_reg = BCLRPAT(pipe); |
||
555 | vtotal_reg = VTOTAL(pipe); |
||
556 | vblank_reg = VBLANK(pipe); |
||
557 | vsync_reg = VSYNC(pipe); |
||
558 | pipeconf_reg = PIPECONF(pipe); |
||
559 | pipe_dsl_reg = PIPEDSL(pipe); |
||
560 | |||
561 | save_bclrpat = I915_READ(bclrpat_reg); |
||
562 | save_vtotal = I915_READ(vtotal_reg); |
||
563 | vblank = I915_READ(vblank_reg); |
||
564 | |||
565 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
||
566 | vactive = (save_vtotal & 0x7ff) + 1; |
||
567 | |||
568 | vblank_start = (vblank & 0xfff) + 1; |
||
569 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
||
570 | |||
571 | /* Set the border color to purple. */ |
||
572 | I915_WRITE(bclrpat_reg, 0x500050); |
||
573 | |||
574 | if (!IS_GEN2(dev)) { |
||
575 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
||
576 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
||
577 | POSTING_READ(pipeconf_reg); |
||
578 | /* Wait for next Vblank to substitue |
||
579 | * border color for Color info */ |
||
580 | intel_wait_for_vblank(dev, pipe); |
||
581 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
582 | status = ((st00 & (1 << 4)) != 0) ? |
||
583 | connector_status_connected : |
||
584 | connector_status_disconnected; |
||
585 | |||
586 | I915_WRITE(pipeconf_reg, pipeconf); |
||
587 | } else { |
||
588 | bool restore_vblank = false; |
||
589 | int count, detect; |
||
590 | |||
591 | /* |
||
592 | * If there isn't any border, add some. |
||
593 | * Yes, this will flicker |
||
594 | */ |
||
595 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
||
596 | uint32_t vsync = I915_READ(vsync_reg); |
||
597 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
||
598 | |||
599 | vblank_start = vsync_start; |
||
600 | I915_WRITE(vblank_reg, |
||
601 | (vblank_start - 1) | |
||
602 | ((vblank_end - 1) << 16)); |
||
603 | restore_vblank = true; |
||
604 | } |
||
605 | /* sample in the vertical border, selecting the larger one */ |
||
606 | if (vblank_start - vactive >= vtotal - vblank_end) |
||
607 | vsample = (vblank_start + vactive) >> 1; |
||
608 | else |
||
609 | vsample = (vtotal + vblank_end) >> 1; |
||
610 | |||
611 | /* |
||
612 | * Wait for the border to be displayed |
||
613 | */ |
||
614 | while (I915_READ(pipe_dsl_reg) >= vactive) |
||
615 | ; |
||
616 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
||
617 | ; |
||
618 | /* |
||
619 | * Watch ST00 for an entire scanline |
||
620 | */ |
||
621 | detect = 0; |
||
622 | count = 0; |
||
623 | do { |
||
624 | count++; |
||
625 | /* Read the ST00 VGA status register */ |
||
626 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
627 | if (st00 & (1 << 4)) |
||
628 | detect++; |
||
629 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
||
630 | |||
631 | /* restore vblank if necessary */ |
||
632 | if (restore_vblank) |
||
633 | I915_WRITE(vblank_reg, vblank); |
||
634 | /* |
||
635 | * If more than 3/4 of the scanline detected a monitor, |
||
636 | * then it is assumed to be present. This works even on i830, |
||
637 | * where there isn't any way to force the border color across |
||
638 | * the screen |
||
639 | */ |
||
640 | status = detect * 4 > count * 3 ? |
||
641 | connector_status_connected : |
||
642 | connector_status_disconnected; |
||
643 | } |
||
644 | |||
645 | /* Restore previous settings */ |
||
646 | I915_WRITE(bclrpat_reg, save_bclrpat); |
||
647 | |||
648 | return status; |
||
649 | } |
||
650 | |||
651 | static enum drm_connector_status |
||
652 | intel_crt_detect(struct drm_connector *connector, bool force) |
||
653 | { |
||
654 | struct drm_device *dev = connector->dev; |
||
5060 | serge | 655 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 656 | struct intel_crt *crt = intel_attached_crt(connector); |
5060 | serge | 657 | struct intel_encoder *intel_encoder = &crt->base; |
658 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 659 | enum drm_connector_status status; |
3031 | serge | 660 | struct intel_load_detect_pipe tmp; |
5060 | serge | 661 | struct drm_modeset_acquire_ctx ctx; |
2330 | Serge | 662 | |
4104 | Serge | 663 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
5060 | serge | 664 | connector->base.id, connector->name, |
4104 | Serge | 665 | force); |
666 | |||
5060 | serge | 667 | power_domain = intel_display_port_power_domain(intel_encoder); |
668 | intel_display_power_get(dev_priv, power_domain); |
||
669 | |||
2330 | Serge | 670 | if (I915_HAS_HOTPLUG(dev)) { |
3031 | serge | 671 | /* We can not rely on the HPD pin always being correctly wired |
672 | * up, for example many KVM do not pass it through, and so |
||
673 | * only trust an assertion that the monitor is connected. |
||
674 | */ |
||
2330 | Serge | 675 | if (intel_crt_detect_hotplug(connector)) { |
676 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
||
5060 | serge | 677 | status = connector_status_connected; |
678 | goto out; |
||
3031 | serge | 679 | } else |
2330 | Serge | 680 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
681 | } |
||
682 | |||
5060 | serge | 683 | if (intel_crt_detect_ddc(connector)) { |
684 | status = connector_status_connected; |
||
685 | goto out; |
||
686 | } |
||
2330 | Serge | 687 | |
3031 | serge | 688 | /* Load detection is broken on HPD capable machines. Whoever wants a |
689 | * broken monitor (without edid) to work behind a broken kvm (that fails |
||
690 | * to have the right resistors for HP detection) needs to fix this up. |
||
691 | * For now just bail out. */ |
||
5060 | serge | 692 | if (I915_HAS_HOTPLUG(dev)) { |
693 | status = connector_status_disconnected; |
||
694 | goto out; |
||
695 | } |
||
3031 | serge | 696 | |
5060 | serge | 697 | if (!force) { |
698 | status = connector->status; |
||
699 | goto out; |
||
700 | } |
||
2330 | Serge | 701 | |
5060 | serge | 702 | drm_modeset_acquire_init(&ctx, 0); |
703 | |||
2330 | Serge | 704 | /* for pre-945g platforms use load detect */ |
5060 | serge | 705 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
706 | if (intel_crt_detect_ddc(connector)) |
||
707 | status = connector_status_connected; |
||
708 | else |
||
709 | status = intel_crt_load_detect(crt); |
||
3031 | serge | 710 | intel_release_load_detect_pipe(connector, &tmp); |
5060 | serge | 711 | } else |
712 | status = connector_status_unknown; |
||
2330 | Serge | 713 | |
5060 | serge | 714 | drm_modeset_drop_locks(&ctx); |
715 | drm_modeset_acquire_fini(&ctx); |
||
716 | |||
717 | out: |
||
718 | intel_display_power_put(dev_priv, power_domain); |
||
2330 | Serge | 719 | return status; |
720 | } |
||
721 | |||
722 | static void intel_crt_destroy(struct drm_connector *connector) |
||
723 | { |
||
724 | drm_connector_cleanup(connector); |
||
725 | kfree(connector); |
||
726 | } |
||
727 | |||
728 | static int intel_crt_get_modes(struct drm_connector *connector) |
||
729 | { |
||
730 | struct drm_device *dev = connector->dev; |
||
731 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5060 | serge | 732 | struct intel_crt *crt = intel_attached_crt(connector); |
733 | struct intel_encoder *intel_encoder = &crt->base; |
||
734 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 735 | int ret; |
3031 | serge | 736 | struct i2c_adapter *i2c; |
2330 | Serge | 737 | |
5060 | serge | 738 | power_domain = intel_display_port_power_domain(intel_encoder); |
739 | intel_display_power_get(dev_priv, power_domain); |
||
740 | |||
4104 | Serge | 741 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 742 | ret = intel_crt_ddc_get_modes(connector, i2c); |
2330 | Serge | 743 | if (ret || !IS_G4X(dev)) |
5060 | serge | 744 | goto out; |
2330 | Serge | 745 | |
746 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
||
3031 | serge | 747 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
5060 | serge | 748 | ret = intel_crt_ddc_get_modes(connector, i2c); |
749 | |||
750 | out: |
||
751 | intel_display_power_put(dev_priv, power_domain); |
||
752 | |||
753 | return ret; |
||
2330 | Serge | 754 | } |
755 | |||
756 | static int intel_crt_set_property(struct drm_connector *connector, |
||
757 | struct drm_property *property, |
||
758 | uint64_t value) |
||
759 | { |
||
760 | return 0; |
||
761 | } |
||
762 | |||
763 | static void intel_crt_reset(struct drm_connector *connector) |
||
764 | { |
||
765 | struct drm_device *dev = connector->dev; |
||
3243 | Serge | 766 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 767 | struct intel_crt *crt = intel_attached_crt(connector); |
768 | |||
4104 | Serge | 769 | if (INTEL_INFO(dev)->gen >= 5) { |
3243 | Serge | 770 | u32 adpa; |
771 | |||
3480 | Serge | 772 | adpa = I915_READ(crt->adpa_reg); |
3243 | Serge | 773 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
774 | adpa |= ADPA_HOTPLUG_BITS; |
||
3480 | Serge | 775 | I915_WRITE(crt->adpa_reg, adpa); |
776 | POSTING_READ(crt->adpa_reg); |
||
3243 | Serge | 777 | |
778 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
||
2330 | Serge | 779 | crt->force_hotplug_required = 1; |
3243 | Serge | 780 | } |
781 | |||
2330 | Serge | 782 | } |
783 | |||
784 | /* |
||
785 | * Routines for controlling stuff on the analog port |
||
786 | */ |
||
787 | |||
788 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
||
789 | .reset = intel_crt_reset, |
||
3031 | serge | 790 | .dpms = intel_crt_dpms, |
2330 | Serge | 791 | .detect = intel_crt_detect, |
792 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
793 | .destroy = intel_crt_destroy, |
||
794 | .set_property = intel_crt_set_property, |
||
795 | }; |
||
796 | |||
797 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
||
798 | .mode_valid = intel_crt_mode_valid, |
||
799 | .get_modes = intel_crt_get_modes, |
||
800 | .best_encoder = intel_best_encoder, |
||
801 | }; |
||
802 | |||
803 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
||
804 | .destroy = intel_encoder_destroy, |
||
805 | }; |
||
806 | |||
5097 | serge | 807 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
808 | { |
||
809 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
||
810 | return 1; |
||
811 | } |
||
812 | |||
813 | static const struct dmi_system_id intel_no_crt[] = { |
||
814 | { |
||
815 | .callback = intel_no_crt_dmi_callback, |
||
816 | .ident = "ACER ZGB", |
||
817 | .matches = { |
||
818 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
||
819 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
||
820 | }, |
||
821 | }, |
||
822 | { |
||
823 | .callback = intel_no_crt_dmi_callback, |
||
824 | .ident = "DELL XPS 8700", |
||
825 | .matches = { |
||
826 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
||
827 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), |
||
828 | }, |
||
829 | }, |
||
830 | { } |
||
831 | }; |
||
832 | |||
2330 | Serge | 833 | void intel_crt_init(struct drm_device *dev) |
834 | { |
||
835 | struct drm_connector *connector; |
||
836 | struct intel_crt *crt; |
||
837 | struct intel_connector *intel_connector; |
||
838 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
839 | |||
5097 | serge | 840 | /* Skip machines without VGA that falsely report hotplug events */ |
841 | if (dmi_check_system(intel_no_crt)) |
||
842 | return; |
||
843 | |||
2330 | Serge | 844 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
845 | if (!crt) |
||
846 | return; |
||
847 | |||
4560 | Serge | 848 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
2330 | Serge | 849 | if (!intel_connector) { |
850 | kfree(crt); |
||
851 | return; |
||
852 | } |
||
853 | |||
854 | connector = &intel_connector->base; |
||
3480 | Serge | 855 | crt->connector = intel_connector; |
2330 | Serge | 856 | drm_connector_init(dev, &intel_connector->base, |
857 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
||
858 | |||
859 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
||
860 | DRM_MODE_ENCODER_DAC); |
||
861 | |||
862 | intel_connector_attach_encoder(intel_connector, &crt->base); |
||
863 | |||
864 | crt->base.type = INTEL_OUTPUT_ANALOG; |
||
5060 | serge | 865 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
3243 | Serge | 866 | if (IS_I830(dev)) |
3031 | serge | 867 | crt->base.crtc_mask = (1 << 0); |
868 | else |
||
869 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
870 | |||
871 | if (IS_GEN2(dev)) |
||
872 | connector->interlace_allowed = 0; |
||
873 | else |
||
2330 | Serge | 874 | connector->interlace_allowed = 1; |
875 | connector->doublescan_allowed = 0; |
||
876 | |||
3031 | serge | 877 | if (HAS_PCH_SPLIT(dev)) |
878 | crt->adpa_reg = PCH_ADPA; |
||
879 | else if (IS_VALLEYVIEW(dev)) |
||
880 | crt->adpa_reg = VLV_ADPA; |
||
881 | else |
||
882 | crt->adpa_reg = ADPA; |
||
883 | |||
3746 | Serge | 884 | crt->base.compute_config = intel_crt_compute_config; |
3031 | serge | 885 | crt->base.disable = intel_disable_crt; |
886 | crt->base.enable = intel_enable_crt; |
||
3746 | Serge | 887 | if (I915_HAS_HOTPLUG(dev)) |
888 | crt->base.hpd_pin = HPD_CRT; |
||
4560 | Serge | 889 | if (HAS_DDI(dev)) { |
890 | crt->base.get_config = hsw_crt_get_config; |
||
3243 | Serge | 891 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
5060 | serge | 892 | crt->base.pre_enable = hsw_crt_pre_enable; |
893 | crt->base.post_disable = hsw_crt_post_disable; |
||
4560 | Serge | 894 | } else { |
895 | crt->base.get_config = intel_crt_get_config; |
||
3031 | serge | 896 | crt->base.get_hw_state = intel_crt_get_hw_state; |
4560 | Serge | 897 | } |
3031 | serge | 898 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5060 | serge | 899 | intel_connector->unregister = intel_connector_unregister; |
3031 | serge | 900 | |
2330 | Serge | 901 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
902 | |||
5060 | serge | 903 | drm_connector_register(connector); |
2330 | Serge | 904 | |
3746 | Serge | 905 | if (!I915_HAS_HOTPLUG(dev)) |
906 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
||
2330 | Serge | 907 | |
908 | /* |
||
909 | * Configure the automatic hotplug detection stuff |
||
910 | */ |
||
911 | crt->force_hotplug_required = 0; |
||
912 | |||
3243 | Serge | 913 | /* |
3480 | Serge | 914 | * TODO: find a proper way to discover whether we need to set the the |
915 | * polarity and link reversal bits or not, instead of relying on the |
||
916 | * BIOS. |
||
3243 | Serge | 917 | */ |
3480 | Serge | 918 | if (HAS_PCH_LPT(dev)) { |
919 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
||
920 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
||
921 | |||
922 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; |
||
923 | } |
||
5060 | serge | 924 | |
925 | intel_crt_reset(connector); |
||
2330 | Serge | 926 | }><>><>><>><>><>><>><>=>><>=>><>>>> |