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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | */ |
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26 | |||
27 | #include |
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28 | #include |
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3031 | serge | 29 | #include |
30 | #include |
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31 | #include |
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32 | #include |
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2330 | Serge | 33 | #include "intel_drv.h" |
3031 | serge | 34 | #include |
2330 | Serge | 35 | #include "i915_drv.h" |
36 | |||
37 | /* Here's the desired hotplug mode */ |
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38 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
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39 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
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40 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
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41 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
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42 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
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43 | ADPA_CRT_HOTPLUG_ENABLE) |
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44 | |||
45 | struct intel_crt { |
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46 | struct intel_encoder base; |
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3480 | Serge | 47 | /* DPMS state is stored in the connector, which we need in the |
48 | * encoder's enable/disable callbacks */ |
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49 | struct intel_connector *connector; |
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2330 | Serge | 50 | bool force_hotplug_required; |
3031 | serge | 51 | u32 adpa_reg; |
2330 | Serge | 52 | }; |
53 | |||
4104 | Serge | 54 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
2330 | Serge | 55 | { |
4104 | Serge | 56 | return container_of(encoder, struct intel_crt, base); |
2330 | Serge | 57 | } |
58 | |||
4104 | Serge | 59 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
2330 | Serge | 60 | { |
4104 | Serge | 61 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
3031 | serge | 62 | } |
63 | |||
64 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
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65 | enum pipe *pipe) |
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66 | { |
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67 | struct drm_device *dev = encoder->base.dev; |
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2330 | Serge | 68 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 69 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
70 | u32 tmp; |
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2330 | Serge | 71 | |
3031 | serge | 72 | tmp = I915_READ(crt->adpa_reg); |
73 | |||
74 | if (!(tmp & ADPA_DAC_ENABLE)) |
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75 | return false; |
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76 | |||
77 | if (HAS_PCH_CPT(dev)) |
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78 | *pipe = PORT_TO_PIPE_CPT(tmp); |
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2330 | Serge | 79 | else |
3031 | serge | 80 | *pipe = PORT_TO_PIPE(tmp); |
2330 | Serge | 81 | |
3031 | serge | 82 | return true; |
83 | } |
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84 | |||
4104 | Serge | 85 | static void intel_crt_get_config(struct intel_encoder *encoder, |
86 | struct intel_crtc_config *pipe_config) |
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87 | { |
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88 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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89 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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90 | u32 tmp, flags = 0; |
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91 | |||
92 | tmp = I915_READ(crt->adpa_reg); |
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93 | |||
94 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
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95 | flags |= DRM_MODE_FLAG_PHSYNC; |
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96 | else |
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97 | flags |= DRM_MODE_FLAG_NHSYNC; |
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98 | |||
99 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
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100 | flags |= DRM_MODE_FLAG_PVSYNC; |
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101 | else |
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102 | flags |= DRM_MODE_FLAG_NVSYNC; |
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103 | |||
104 | pipe_config->adjusted_mode.flags |= flags; |
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105 | } |
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106 | |||
3031 | serge | 107 | /* Note: The caller is required to filter out dpms modes not supported by the |
108 | * platform. */ |
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109 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
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110 | { |
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111 | struct drm_device *dev = encoder->base.dev; |
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112 | struct drm_i915_private *dev_priv = dev->dev_private; |
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113 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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114 | u32 temp; |
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115 | |||
116 | temp = I915_READ(crt->adpa_reg); |
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117 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
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118 | temp &= ~ADPA_DAC_ENABLE; |
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119 | |||
2342 | Serge | 120 | switch (mode) { |
2330 | Serge | 121 | case DRM_MODE_DPMS_ON: |
122 | temp |= ADPA_DAC_ENABLE; |
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123 | break; |
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124 | case DRM_MODE_DPMS_STANDBY: |
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125 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
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126 | break; |
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127 | case DRM_MODE_DPMS_SUSPEND: |
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128 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
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129 | break; |
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130 | case DRM_MODE_DPMS_OFF: |
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131 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
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132 | break; |
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133 | } |
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134 | |||
3031 | serge | 135 | I915_WRITE(crt->adpa_reg, temp); |
2330 | Serge | 136 | } |
137 | |||
3480 | Serge | 138 | static void intel_disable_crt(struct intel_encoder *encoder) |
139 | { |
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140 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
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141 | } |
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142 | |||
143 | static void intel_enable_crt(struct intel_encoder *encoder) |
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144 | { |
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145 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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146 | |||
147 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
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148 | } |
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149 | |||
4104 | Serge | 150 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
3031 | serge | 151 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
152 | { |
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153 | struct drm_device *dev = connector->dev; |
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154 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
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155 | struct drm_crtc *crtc; |
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156 | int old_dpms; |
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157 | |||
158 | /* PCH platforms and VLV only support on/off. */ |
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3120 | serge | 159 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
3031 | serge | 160 | mode = DRM_MODE_DPMS_OFF; |
161 | |||
162 | if (mode == connector->dpms) |
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163 | return; |
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164 | |||
165 | old_dpms = connector->dpms; |
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166 | connector->dpms = mode; |
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167 | |||
168 | /* Only need to change hw state when actually enabled */ |
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169 | crtc = encoder->base.crtc; |
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170 | if (!crtc) { |
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171 | encoder->connectors_active = false; |
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172 | return; |
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173 | } |
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174 | |||
175 | /* We need the pipe to run for anything but OFF. */ |
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176 | if (mode == DRM_MODE_DPMS_OFF) |
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177 | encoder->connectors_active = false; |
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178 | else |
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179 | encoder->connectors_active = true; |
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180 | |||
4104 | Serge | 181 | /* We call connector dpms manually below in case pipe dpms doesn't |
182 | * change due to cloning. */ |
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3031 | serge | 183 | if (mode < old_dpms) { |
184 | /* From off to on, enable the pipe first. */ |
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185 | intel_crtc_update_dpms(crtc); |
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186 | |||
187 | intel_crt_set_dpms(encoder, mode); |
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188 | } else { |
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189 | intel_crt_set_dpms(encoder, mode); |
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190 | |||
191 | intel_crtc_update_dpms(crtc); |
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192 | } |
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193 | |||
194 | intel_modeset_check_state(connector->dev); |
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195 | } |
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196 | |||
2330 | Serge | 197 | static int intel_crt_mode_valid(struct drm_connector *connector, |
198 | struct drm_display_mode *mode) |
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199 | { |
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200 | struct drm_device *dev = connector->dev; |
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201 | |||
202 | int max_clock = 0; |
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203 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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204 | return MODE_NO_DBLESCAN; |
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205 | |||
206 | if (mode->clock < 25000) |
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207 | return MODE_CLOCK_LOW; |
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208 | |||
209 | if (IS_GEN2(dev)) |
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210 | max_clock = 350000; |
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211 | else |
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212 | max_clock = 400000; |
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213 | if (mode->clock > max_clock) |
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214 | return MODE_CLOCK_HIGH; |
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215 | |||
3243 | Serge | 216 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
217 | if (HAS_PCH_LPT(dev) && |
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218 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
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219 | return MODE_CLOCK_HIGH; |
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220 | |||
2330 | Serge | 221 | return MODE_OK; |
222 | } |
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223 | |||
3746 | Serge | 224 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
225 | struct intel_crtc_config *pipe_config) |
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2330 | Serge | 226 | { |
3746 | Serge | 227 | struct drm_device *dev = encoder->base.dev; |
228 | |||
229 | if (HAS_PCH_SPLIT(dev)) |
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230 | pipe_config->has_pch_encoder = true; |
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231 | |||
4104 | Serge | 232 | /* LPT FDI RX only supports 8bpc. */ |
233 | if (HAS_PCH_LPT(dev)) |
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234 | pipe_config->pipe_bpp = 24; |
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235 | |||
2330 | Serge | 236 | return true; |
237 | } |
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238 | |||
4104 | Serge | 239 | static void intel_crt_mode_set(struct intel_encoder *encoder) |
2330 | Serge | 240 | { |
241 | |||
4104 | Serge | 242 | struct drm_device *dev = encoder->base.dev; |
243 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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244 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
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2330 | Serge | 245 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 246 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
3031 | serge | 247 | u32 adpa; |
2330 | Serge | 248 | |
3243 | Serge | 249 | if (HAS_PCH_SPLIT(dev)) |
2330 | Serge | 250 | adpa = ADPA_HOTPLUG_BITS; |
3243 | Serge | 251 | else |
252 | adpa = 0; |
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253 | |||
2330 | Serge | 254 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
255 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
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256 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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257 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
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258 | |||
2342 | Serge | 259 | /* For CPT allow 3 pipe config, for others just use A or B */ |
3243 | Serge | 260 | if (HAS_PCH_LPT(dev)) |
261 | ; /* Those bits don't exist here */ |
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262 | else if (HAS_PCH_CPT(dev)) |
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4104 | Serge | 263 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
264 | else if (crtc->pipe == 0) |
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2330 | Serge | 265 | adpa |= ADPA_PIPE_A_SELECT; |
266 | else |
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267 | adpa |= ADPA_PIPE_B_SELECT; |
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268 | |||
269 | if (!HAS_PCH_SPLIT(dev)) |
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4104 | Serge | 270 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
2330 | Serge | 271 | |
3031 | serge | 272 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 273 | } |
274 | |||
275 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
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276 | { |
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277 | struct drm_device *dev = connector->dev; |
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278 | struct intel_crt *crt = intel_attached_crt(connector); |
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279 | struct drm_i915_private *dev_priv = dev->dev_private; |
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280 | u32 adpa; |
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281 | bool ret; |
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282 | |||
283 | /* The first time through, trigger an explicit detection cycle */ |
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284 | if (crt->force_hotplug_required) { |
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285 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
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286 | u32 save_adpa; |
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287 | |||
288 | crt->force_hotplug_required = 0; |
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289 | |||
3480 | Serge | 290 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 291 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
292 | |||
293 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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294 | if (turn_off_dac) |
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295 | adpa &= ~ADPA_DAC_ENABLE; |
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296 | |||
3480 | Serge | 297 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 298 | |
3480 | Serge | 299 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
2330 | Serge | 300 | 1000)) |
301 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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302 | |||
303 | if (turn_off_dac) { |
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3480 | Serge | 304 | I915_WRITE(crt->adpa_reg, save_adpa); |
305 | POSTING_READ(crt->adpa_reg); |
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2330 | Serge | 306 | } |
307 | } |
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308 | |||
309 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 310 | adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 311 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
312 | ret = true; |
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313 | else |
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314 | ret = false; |
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315 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
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316 | |||
317 | return ret; |
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318 | } |
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319 | |||
3031 | serge | 320 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
321 | { |
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322 | struct drm_device *dev = connector->dev; |
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3480 | Serge | 323 | struct intel_crt *crt = intel_attached_crt(connector); |
3031 | serge | 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
325 | u32 adpa; |
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326 | bool ret; |
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327 | u32 save_adpa; |
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328 | |||
3480 | Serge | 329 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 330 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
331 | |||
332 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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333 | |||
3480 | Serge | 334 | I915_WRITE(crt->adpa_reg, adpa); |
3031 | serge | 335 | |
3480 | Serge | 336 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
3031 | serge | 337 | 1000)) { |
338 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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3480 | Serge | 339 | I915_WRITE(crt->adpa_reg, save_adpa); |
3031 | serge | 340 | } |
341 | |||
342 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 343 | adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 344 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
345 | ret = true; |
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346 | else |
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347 | ret = false; |
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348 | |||
349 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
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350 | |||
351 | /* FIXME: debug force function and remove */ |
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352 | ret = true; |
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353 | |||
354 | return ret; |
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355 | } |
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356 | |||
2330 | Serge | 357 | /** |
358 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
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359 | * |
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360 | * Not for i915G/i915GM |
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361 | * |
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362 | * \return true if CRT is connected. |
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363 | * \return false if CRT is disconnected. |
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364 | */ |
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365 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
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366 | { |
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367 | struct drm_device *dev = connector->dev; |
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368 | struct drm_i915_private *dev_priv = dev->dev_private; |
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369 | u32 hotplug_en, orig, stat; |
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370 | bool ret = false; |
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371 | int i, tries = 0; |
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372 | |||
373 | if (HAS_PCH_SPLIT(dev)) |
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374 | return intel_ironlake_crt_detect_hotplug(connector); |
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375 | |||
3031 | serge | 376 | if (IS_VALLEYVIEW(dev)) |
377 | return valleyview_crt_detect_hotplug(connector); |
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378 | |||
2330 | Serge | 379 | /* |
380 | * On 4 series desktop, CRT detect sequence need to be done twice |
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381 | * to get a reliable result. |
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382 | */ |
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383 | |||
384 | if (IS_G4X(dev) && !IS_GM45(dev)) |
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385 | tries = 2; |
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386 | else |
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387 | tries = 1; |
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388 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
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389 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
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390 | |||
391 | for (i = 0; i < tries ; i++) { |
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392 | /* turn on the FORCE_DETECT */ |
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393 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
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394 | /* wait for FORCE_DETECT to go off */ |
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395 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
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396 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
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397 | 1000)) |
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398 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
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399 | } |
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400 | |||
401 | stat = I915_READ(PORT_HOTPLUG_STAT); |
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402 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
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403 | ret = true; |
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404 | |||
405 | /* clear the interrupt we just generated, if any */ |
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406 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
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407 | |||
408 | /* and put the bits back */ |
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409 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
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410 | |||
411 | return ret; |
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412 | } |
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413 | |||
3031 | serge | 414 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
415 | struct i2c_adapter *i2c) |
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416 | { |
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417 | struct edid *edid; |
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418 | |||
419 | edid = drm_get_edid(connector, i2c); |
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420 | |||
421 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
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422 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
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423 | intel_gmbus_force_bit(i2c, true); |
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424 | edid = drm_get_edid(connector, i2c); |
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425 | intel_gmbus_force_bit(i2c, false); |
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426 | } |
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427 | |||
428 | return edid; |
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429 | } |
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430 | |||
431 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
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432 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
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433 | struct i2c_adapter *adapter) |
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434 | { |
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435 | struct edid *edid; |
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3243 | Serge | 436 | int ret; |
3031 | serge | 437 | |
438 | edid = intel_crt_get_edid(connector, adapter); |
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439 | if (!edid) |
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440 | return 0; |
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441 | |||
3243 | Serge | 442 | ret = intel_connector_update_modes(connector, edid); |
443 | kfree(edid); |
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444 | |||
445 | return ret; |
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3031 | serge | 446 | } |
447 | |||
2330 | Serge | 448 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
449 | { |
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450 | struct intel_crt *crt = intel_attached_crt(connector); |
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451 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
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3031 | serge | 452 | struct edid *edid; |
453 | struct i2c_adapter *i2c; |
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2330 | Serge | 454 | |
3031 | serge | 455 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
2330 | Serge | 456 | |
4104 | Serge | 457 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 458 | edid = intel_crt_get_edid(connector, i2c); |
2330 | Serge | 459 | |
3031 | serge | 460 | if (edid) { |
461 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
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462 | |||
2330 | Serge | 463 | /* |
464 | * This may be a DVI-I connector with a shared DDC |
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465 | * link between analog and digital outputs, so we |
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466 | * have to check the EDID input spec of the attached device. |
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467 | */ |
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468 | if (!is_digital) { |
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469 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
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470 | return true; |
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3031 | serge | 471 | } |
472 | |||
473 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
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2330 | Serge | 474 | } else { |
3031 | serge | 475 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
2330 | Serge | 476 | } |
477 | |||
3031 | serge | 478 | kfree(edid); |
479 | |||
2330 | Serge | 480 | return false; |
481 | } |
||
482 | |||
483 | static enum drm_connector_status |
||
484 | intel_crt_load_detect(struct intel_crt *crt) |
||
485 | { |
||
486 | struct drm_device *dev = crt->base.base.dev; |
||
487 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
488 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
||
489 | uint32_t save_bclrpat; |
||
490 | uint32_t save_vtotal; |
||
491 | uint32_t vtotal, vactive; |
||
492 | uint32_t vsample; |
||
493 | uint32_t vblank, vblank_start, vblank_end; |
||
494 | uint32_t dsl; |
||
495 | uint32_t bclrpat_reg; |
||
496 | uint32_t vtotal_reg; |
||
497 | uint32_t vblank_reg; |
||
498 | uint32_t vsync_reg; |
||
499 | uint32_t pipeconf_reg; |
||
500 | uint32_t pipe_dsl_reg; |
||
501 | uint8_t st00; |
||
502 | enum drm_connector_status status; |
||
503 | |||
504 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
||
505 | |||
506 | bclrpat_reg = BCLRPAT(pipe); |
||
507 | vtotal_reg = VTOTAL(pipe); |
||
508 | vblank_reg = VBLANK(pipe); |
||
509 | vsync_reg = VSYNC(pipe); |
||
510 | pipeconf_reg = PIPECONF(pipe); |
||
511 | pipe_dsl_reg = PIPEDSL(pipe); |
||
512 | |||
513 | save_bclrpat = I915_READ(bclrpat_reg); |
||
514 | save_vtotal = I915_READ(vtotal_reg); |
||
515 | vblank = I915_READ(vblank_reg); |
||
516 | |||
517 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
||
518 | vactive = (save_vtotal & 0x7ff) + 1; |
||
519 | |||
520 | vblank_start = (vblank & 0xfff) + 1; |
||
521 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
||
522 | |||
523 | /* Set the border color to purple. */ |
||
524 | I915_WRITE(bclrpat_reg, 0x500050); |
||
525 | |||
526 | if (!IS_GEN2(dev)) { |
||
527 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
||
528 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
||
529 | POSTING_READ(pipeconf_reg); |
||
530 | /* Wait for next Vblank to substitue |
||
531 | * border color for Color info */ |
||
532 | intel_wait_for_vblank(dev, pipe); |
||
533 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
534 | status = ((st00 & (1 << 4)) != 0) ? |
||
535 | connector_status_connected : |
||
536 | connector_status_disconnected; |
||
537 | |||
538 | I915_WRITE(pipeconf_reg, pipeconf); |
||
539 | } else { |
||
540 | bool restore_vblank = false; |
||
541 | int count, detect; |
||
542 | |||
543 | /* |
||
544 | * If there isn't any border, add some. |
||
545 | * Yes, this will flicker |
||
546 | */ |
||
547 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
||
548 | uint32_t vsync = I915_READ(vsync_reg); |
||
549 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
||
550 | |||
551 | vblank_start = vsync_start; |
||
552 | I915_WRITE(vblank_reg, |
||
553 | (vblank_start - 1) | |
||
554 | ((vblank_end - 1) << 16)); |
||
555 | restore_vblank = true; |
||
556 | } |
||
557 | /* sample in the vertical border, selecting the larger one */ |
||
558 | if (vblank_start - vactive >= vtotal - vblank_end) |
||
559 | vsample = (vblank_start + vactive) >> 1; |
||
560 | else |
||
561 | vsample = (vtotal + vblank_end) >> 1; |
||
562 | |||
563 | /* |
||
564 | * Wait for the border to be displayed |
||
565 | */ |
||
566 | while (I915_READ(pipe_dsl_reg) >= vactive) |
||
567 | ; |
||
568 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
||
569 | ; |
||
570 | /* |
||
571 | * Watch ST00 for an entire scanline |
||
572 | */ |
||
573 | detect = 0; |
||
574 | count = 0; |
||
575 | do { |
||
576 | count++; |
||
577 | /* Read the ST00 VGA status register */ |
||
578 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
579 | if (st00 & (1 << 4)) |
||
580 | detect++; |
||
581 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
||
582 | |||
583 | /* restore vblank if necessary */ |
||
584 | if (restore_vblank) |
||
585 | I915_WRITE(vblank_reg, vblank); |
||
586 | /* |
||
587 | * If more than 3/4 of the scanline detected a monitor, |
||
588 | * then it is assumed to be present. This works even on i830, |
||
589 | * where there isn't any way to force the border color across |
||
590 | * the screen |
||
591 | */ |
||
592 | status = detect * 4 > count * 3 ? |
||
593 | connector_status_connected : |
||
594 | connector_status_disconnected; |
||
595 | } |
||
596 | |||
597 | /* Restore previous settings */ |
||
598 | I915_WRITE(bclrpat_reg, save_bclrpat); |
||
599 | |||
600 | return status; |
||
601 | } |
||
602 | |||
603 | static enum drm_connector_status |
||
604 | intel_crt_detect(struct drm_connector *connector, bool force) |
||
605 | { |
||
606 | struct drm_device *dev = connector->dev; |
||
607 | struct intel_crt *crt = intel_attached_crt(connector); |
||
608 | enum drm_connector_status status; |
||
3031 | serge | 609 | struct intel_load_detect_pipe tmp; |
2330 | Serge | 610 | |
4104 | Serge | 611 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
612 | connector->base.id, drm_get_connector_name(connector), |
||
613 | force); |
||
614 | |||
2330 | Serge | 615 | if (I915_HAS_HOTPLUG(dev)) { |
3031 | serge | 616 | /* We can not rely on the HPD pin always being correctly wired |
617 | * up, for example many KVM do not pass it through, and so |
||
618 | * only trust an assertion that the monitor is connected. |
||
619 | */ |
||
2330 | Serge | 620 | if (intel_crt_detect_hotplug(connector)) { |
621 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
||
622 | return connector_status_connected; |
||
3031 | serge | 623 | } else |
2330 | Serge | 624 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
625 | } |
||
626 | |||
627 | if (intel_crt_detect_ddc(connector)) |
||
628 | return connector_status_connected; |
||
629 | |||
3031 | serge | 630 | /* Load detection is broken on HPD capable machines. Whoever wants a |
631 | * broken monitor (without edid) to work behind a broken kvm (that fails |
||
632 | * to have the right resistors for HP detection) needs to fix this up. |
||
633 | * For now just bail out. */ |
||
634 | if (I915_HAS_HOTPLUG(dev)) |
||
635 | return connector_status_disconnected; |
||
636 | |||
2330 | Serge | 637 | if (!force) |
638 | return connector->status; |
||
639 | |||
640 | /* for pre-945g platforms use load detect */ |
||
3031 | serge | 641 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
2330 | Serge | 642 | if (intel_crt_detect_ddc(connector)) |
643 | status = connector_status_connected; |
||
644 | else |
||
645 | status = intel_crt_load_detect(crt); |
||
3031 | serge | 646 | intel_release_load_detect_pipe(connector, &tmp); |
2330 | Serge | 647 | } else |
648 | status = connector_status_unknown; |
||
649 | |||
650 | return status; |
||
651 | } |
||
652 | |||
653 | static void intel_crt_destroy(struct drm_connector *connector) |
||
654 | { |
||
655 | drm_sysfs_connector_remove(connector); |
||
656 | drm_connector_cleanup(connector); |
||
657 | kfree(connector); |
||
658 | } |
||
659 | |||
660 | static int intel_crt_get_modes(struct drm_connector *connector) |
||
661 | { |
||
662 | struct drm_device *dev = connector->dev; |
||
663 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
664 | int ret; |
||
3031 | serge | 665 | struct i2c_adapter *i2c; |
2330 | Serge | 666 | |
4104 | Serge | 667 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 668 | ret = intel_crt_ddc_get_modes(connector, i2c); |
2330 | Serge | 669 | if (ret || !IS_G4X(dev)) |
670 | return ret; |
||
671 | |||
672 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
||
3031 | serge | 673 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
674 | return intel_crt_ddc_get_modes(connector, i2c); |
||
2330 | Serge | 675 | } |
676 | |||
677 | static int intel_crt_set_property(struct drm_connector *connector, |
||
678 | struct drm_property *property, |
||
679 | uint64_t value) |
||
680 | { |
||
681 | return 0; |
||
682 | } |
||
683 | |||
684 | static void intel_crt_reset(struct drm_connector *connector) |
||
685 | { |
||
686 | struct drm_device *dev = connector->dev; |
||
3243 | Serge | 687 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 688 | struct intel_crt *crt = intel_attached_crt(connector); |
689 | |||
4104 | Serge | 690 | if (INTEL_INFO(dev)->gen >= 5) { |
3243 | Serge | 691 | u32 adpa; |
692 | |||
3480 | Serge | 693 | adpa = I915_READ(crt->adpa_reg); |
3243 | Serge | 694 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
695 | adpa |= ADPA_HOTPLUG_BITS; |
||
3480 | Serge | 696 | I915_WRITE(crt->adpa_reg, adpa); |
697 | POSTING_READ(crt->adpa_reg); |
||
3243 | Serge | 698 | |
699 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
||
2330 | Serge | 700 | crt->force_hotplug_required = 1; |
3243 | Serge | 701 | } |
702 | |||
2330 | Serge | 703 | } |
704 | |||
705 | /* |
||
706 | * Routines for controlling stuff on the analog port |
||
707 | */ |
||
708 | |||
709 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
||
710 | .reset = intel_crt_reset, |
||
3031 | serge | 711 | .dpms = intel_crt_dpms, |
2330 | Serge | 712 | .detect = intel_crt_detect, |
713 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
714 | .destroy = intel_crt_destroy, |
||
715 | .set_property = intel_crt_set_property, |
||
716 | }; |
||
717 | |||
718 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
||
719 | .mode_valid = intel_crt_mode_valid, |
||
720 | .get_modes = intel_crt_get_modes, |
||
721 | .best_encoder = intel_best_encoder, |
||
722 | }; |
||
723 | |||
724 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
||
725 | .destroy = intel_encoder_destroy, |
||
726 | }; |
||
727 | |||
728 | void intel_crt_init(struct drm_device *dev) |
||
729 | { |
||
730 | struct drm_connector *connector; |
||
731 | struct intel_crt *crt; |
||
732 | struct intel_connector *intel_connector; |
||
733 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
734 | |||
735 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
||
736 | if (!crt) |
||
737 | return; |
||
738 | |||
739 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
||
740 | if (!intel_connector) { |
||
741 | kfree(crt); |
||
742 | return; |
||
743 | } |
||
744 | |||
745 | connector = &intel_connector->base; |
||
3480 | Serge | 746 | crt->connector = intel_connector; |
2330 | Serge | 747 | drm_connector_init(dev, &intel_connector->base, |
748 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
||
749 | |||
750 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
||
751 | DRM_MODE_ENCODER_DAC); |
||
752 | |||
753 | intel_connector_attach_encoder(intel_connector, &crt->base); |
||
754 | |||
755 | crt->base.type = INTEL_OUTPUT_ANALOG; |
||
3031 | serge | 756 | crt->base.cloneable = true; |
3243 | Serge | 757 | if (IS_I830(dev)) |
3031 | serge | 758 | crt->base.crtc_mask = (1 << 0); |
759 | else |
||
760 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
761 | |||
762 | if (IS_GEN2(dev)) |
||
763 | connector->interlace_allowed = 0; |
||
764 | else |
||
2330 | Serge | 765 | connector->interlace_allowed = 1; |
766 | connector->doublescan_allowed = 0; |
||
767 | |||
3031 | serge | 768 | if (HAS_PCH_SPLIT(dev)) |
769 | crt->adpa_reg = PCH_ADPA; |
||
770 | else if (IS_VALLEYVIEW(dev)) |
||
771 | crt->adpa_reg = VLV_ADPA; |
||
772 | else |
||
773 | crt->adpa_reg = ADPA; |
||
774 | |||
3746 | Serge | 775 | crt->base.compute_config = intel_crt_compute_config; |
4104 | Serge | 776 | crt->base.mode_set = intel_crt_mode_set; |
3031 | serge | 777 | crt->base.disable = intel_disable_crt; |
778 | crt->base.enable = intel_enable_crt; |
||
4104 | Serge | 779 | crt->base.get_config = intel_crt_get_config; |
3746 | Serge | 780 | if (I915_HAS_HOTPLUG(dev)) |
781 | crt->base.hpd_pin = HPD_CRT; |
||
3480 | Serge | 782 | if (HAS_DDI(dev)) |
3243 | Serge | 783 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
784 | else |
||
3031 | serge | 785 | crt->base.get_hw_state = intel_crt_get_hw_state; |
786 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
||
787 | |||
2330 | Serge | 788 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
789 | |||
790 | drm_sysfs_connector_add(connector); |
||
791 | |||
3746 | Serge | 792 | if (!I915_HAS_HOTPLUG(dev)) |
793 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
||
2330 | Serge | 794 | |
795 | /* |
||
796 | * Configure the automatic hotplug detection stuff |
||
797 | */ |
||
798 | crt->force_hotplug_required = 0; |
||
799 | |||
3243 | Serge | 800 | /* |
3480 | Serge | 801 | * TODO: find a proper way to discover whether we need to set the the |
802 | * polarity and link reversal bits or not, instead of relying on the |
||
803 | * BIOS. |
||
3243 | Serge | 804 | */ |
3480 | Serge | 805 | if (HAS_PCH_LPT(dev)) { |
806 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
||
807 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
||
808 | |||
809 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; |
||
810 | } |
||
2330 | Serge | 811 | }><>><>><>><>><>=>><>=>><>>>> |