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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | */ |
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26 | |||
27 | #include |
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28 | #include |
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3031 | serge | 29 | #include |
30 | #include |
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31 | #include |
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32 | #include |
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2330 | Serge | 33 | #include "intel_drv.h" |
3031 | serge | 34 | #include |
2330 | Serge | 35 | #include "i915_drv.h" |
36 | |||
37 | /* Here's the desired hotplug mode */ |
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38 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
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39 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
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40 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
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41 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
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42 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
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43 | ADPA_CRT_HOTPLUG_ENABLE) |
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44 | |||
45 | struct intel_crt { |
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46 | struct intel_encoder base; |
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3480 | Serge | 47 | /* DPMS state is stored in the connector, which we need in the |
48 | * encoder's enable/disable callbacks */ |
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49 | struct intel_connector *connector; |
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2330 | Serge | 50 | bool force_hotplug_required; |
3031 | serge | 51 | u32 adpa_reg; |
2330 | Serge | 52 | }; |
53 | |||
54 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
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55 | { |
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56 | return container_of(intel_attached_encoder(connector), |
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57 | struct intel_crt, base); |
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58 | } |
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59 | |||
3031 | serge | 60 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
2330 | Serge | 61 | { |
3031 | serge | 62 | return container_of(encoder, struct intel_crt, base); |
63 | } |
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64 | |||
65 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
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66 | enum pipe *pipe) |
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67 | { |
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68 | struct drm_device *dev = encoder->base.dev; |
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2330 | Serge | 69 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 70 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
71 | u32 tmp; |
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2330 | Serge | 72 | |
3031 | serge | 73 | tmp = I915_READ(crt->adpa_reg); |
74 | |||
75 | if (!(tmp & ADPA_DAC_ENABLE)) |
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76 | return false; |
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77 | |||
78 | if (HAS_PCH_CPT(dev)) |
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79 | *pipe = PORT_TO_PIPE_CPT(tmp); |
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2330 | Serge | 80 | else |
3031 | serge | 81 | *pipe = PORT_TO_PIPE(tmp); |
2330 | Serge | 82 | |
3031 | serge | 83 | return true; |
84 | } |
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85 | |||
86 | /* Note: The caller is required to filter out dpms modes not supported by the |
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87 | * platform. */ |
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88 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
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89 | { |
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90 | struct drm_device *dev = encoder->base.dev; |
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91 | struct drm_i915_private *dev_priv = dev->dev_private; |
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92 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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93 | u32 temp; |
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94 | |||
95 | temp = I915_READ(crt->adpa_reg); |
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96 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
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97 | temp &= ~ADPA_DAC_ENABLE; |
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98 | |||
2342 | Serge | 99 | switch (mode) { |
2330 | Serge | 100 | case DRM_MODE_DPMS_ON: |
101 | temp |= ADPA_DAC_ENABLE; |
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102 | break; |
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103 | case DRM_MODE_DPMS_STANDBY: |
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104 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
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105 | break; |
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106 | case DRM_MODE_DPMS_SUSPEND: |
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107 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
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108 | break; |
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109 | case DRM_MODE_DPMS_OFF: |
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110 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
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111 | break; |
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112 | } |
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113 | |||
3031 | serge | 114 | I915_WRITE(crt->adpa_reg, temp); |
2330 | Serge | 115 | } |
116 | |||
3480 | Serge | 117 | static void intel_disable_crt(struct intel_encoder *encoder) |
118 | { |
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119 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
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120 | } |
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121 | |||
122 | static void intel_enable_crt(struct intel_encoder *encoder) |
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123 | { |
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124 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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125 | |||
126 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
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127 | } |
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128 | |||
129 | |||
3031 | serge | 130 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
131 | { |
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132 | struct drm_device *dev = connector->dev; |
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133 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
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134 | struct drm_crtc *crtc; |
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135 | int old_dpms; |
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136 | |||
137 | /* PCH platforms and VLV only support on/off. */ |
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3120 | serge | 138 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
3031 | serge | 139 | mode = DRM_MODE_DPMS_OFF; |
140 | |||
141 | if (mode == connector->dpms) |
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142 | return; |
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143 | |||
144 | old_dpms = connector->dpms; |
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145 | connector->dpms = mode; |
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146 | |||
147 | /* Only need to change hw state when actually enabled */ |
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148 | crtc = encoder->base.crtc; |
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149 | if (!crtc) { |
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150 | encoder->connectors_active = false; |
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151 | return; |
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152 | } |
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153 | |||
154 | /* We need the pipe to run for anything but OFF. */ |
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155 | if (mode == DRM_MODE_DPMS_OFF) |
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156 | encoder->connectors_active = false; |
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157 | else |
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158 | encoder->connectors_active = true; |
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159 | |||
160 | if (mode < old_dpms) { |
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161 | /* From off to on, enable the pipe first. */ |
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162 | intel_crtc_update_dpms(crtc); |
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163 | |||
164 | intel_crt_set_dpms(encoder, mode); |
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165 | } else { |
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166 | intel_crt_set_dpms(encoder, mode); |
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167 | |||
168 | intel_crtc_update_dpms(crtc); |
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169 | } |
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170 | |||
171 | intel_modeset_check_state(connector->dev); |
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172 | } |
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173 | |||
2330 | Serge | 174 | static int intel_crt_mode_valid(struct drm_connector *connector, |
175 | struct drm_display_mode *mode) |
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176 | { |
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177 | struct drm_device *dev = connector->dev; |
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178 | |||
179 | int max_clock = 0; |
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180 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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181 | return MODE_NO_DBLESCAN; |
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182 | |||
183 | if (mode->clock < 25000) |
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184 | return MODE_CLOCK_LOW; |
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185 | |||
186 | if (IS_GEN2(dev)) |
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187 | max_clock = 350000; |
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188 | else |
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189 | max_clock = 400000; |
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190 | if (mode->clock > max_clock) |
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191 | return MODE_CLOCK_HIGH; |
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192 | |||
3243 | Serge | 193 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
194 | if (HAS_PCH_LPT(dev) && |
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195 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
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196 | return MODE_CLOCK_HIGH; |
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197 | |||
2330 | Serge | 198 | return MODE_OK; |
199 | } |
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200 | |||
3746 | Serge | 201 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
202 | struct intel_crtc_config *pipe_config) |
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2330 | Serge | 203 | { |
3746 | Serge | 204 | struct drm_device *dev = encoder->base.dev; |
205 | |||
206 | if (HAS_PCH_SPLIT(dev)) |
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207 | pipe_config->has_pch_encoder = true; |
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208 | |||
2330 | Serge | 209 | return true; |
210 | } |
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211 | |||
212 | static void intel_crt_mode_set(struct drm_encoder *encoder, |
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213 | struct drm_display_mode *mode, |
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214 | struct drm_display_mode *adjusted_mode) |
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215 | { |
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216 | |||
217 | struct drm_device *dev = encoder->dev; |
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218 | struct drm_crtc *crtc = encoder->crtc; |
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3031 | serge | 219 | struct intel_crt *crt = |
220 | intel_encoder_to_crt(to_intel_encoder(encoder)); |
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2330 | Serge | 221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
222 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 223 | u32 adpa; |
2330 | Serge | 224 | |
3243 | Serge | 225 | if (HAS_PCH_SPLIT(dev)) |
2330 | Serge | 226 | adpa = ADPA_HOTPLUG_BITS; |
3243 | Serge | 227 | else |
228 | adpa = 0; |
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229 | |||
2330 | Serge | 230 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
231 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
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232 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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233 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
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234 | |||
2342 | Serge | 235 | /* For CPT allow 3 pipe config, for others just use A or B */ |
3243 | Serge | 236 | if (HAS_PCH_LPT(dev)) |
237 | ; /* Those bits don't exist here */ |
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238 | else if (HAS_PCH_CPT(dev)) |
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2342 | Serge | 239 | adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
240 | else if (intel_crtc->pipe == 0) |
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2330 | Serge | 241 | adpa |= ADPA_PIPE_A_SELECT; |
242 | else |
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243 | adpa |= ADPA_PIPE_B_SELECT; |
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244 | |||
245 | if (!HAS_PCH_SPLIT(dev)) |
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246 | I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); |
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247 | |||
3031 | serge | 248 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 249 | } |
250 | |||
251 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
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252 | { |
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253 | struct drm_device *dev = connector->dev; |
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254 | struct intel_crt *crt = intel_attached_crt(connector); |
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255 | struct drm_i915_private *dev_priv = dev->dev_private; |
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256 | u32 adpa; |
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257 | bool ret; |
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258 | |||
259 | /* The first time through, trigger an explicit detection cycle */ |
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260 | if (crt->force_hotplug_required) { |
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261 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
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262 | u32 save_adpa; |
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263 | |||
264 | crt->force_hotplug_required = 0; |
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265 | |||
3480 | Serge | 266 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 267 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
268 | |||
269 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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270 | if (turn_off_dac) |
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271 | adpa &= ~ADPA_DAC_ENABLE; |
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272 | |||
3480 | Serge | 273 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 274 | |
3480 | Serge | 275 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
2330 | Serge | 276 | 1000)) |
277 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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278 | |||
279 | if (turn_off_dac) { |
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3480 | Serge | 280 | I915_WRITE(crt->adpa_reg, save_adpa); |
281 | POSTING_READ(crt->adpa_reg); |
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2330 | Serge | 282 | } |
283 | } |
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284 | |||
285 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 286 | adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 287 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
288 | ret = true; |
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289 | else |
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290 | ret = false; |
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291 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
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292 | |||
293 | return ret; |
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294 | } |
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295 | |||
3031 | serge | 296 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
297 | { |
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298 | struct drm_device *dev = connector->dev; |
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3480 | Serge | 299 | struct intel_crt *crt = intel_attached_crt(connector); |
3031 | serge | 300 | struct drm_i915_private *dev_priv = dev->dev_private; |
301 | u32 adpa; |
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302 | bool ret; |
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303 | u32 save_adpa; |
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304 | |||
3480 | Serge | 305 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 306 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
307 | |||
308 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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309 | |||
3480 | Serge | 310 | I915_WRITE(crt->adpa_reg, adpa); |
3031 | serge | 311 | |
3480 | Serge | 312 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
3031 | serge | 313 | 1000)) { |
314 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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3480 | Serge | 315 | I915_WRITE(crt->adpa_reg, save_adpa); |
3031 | serge | 316 | } |
317 | |||
318 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 319 | adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 320 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
321 | ret = true; |
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322 | else |
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323 | ret = false; |
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324 | |||
325 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
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326 | |||
327 | /* FIXME: debug force function and remove */ |
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328 | ret = true; |
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329 | |||
330 | return ret; |
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331 | } |
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332 | |||
2330 | Serge | 333 | /** |
334 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
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335 | * |
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336 | * Not for i915G/i915GM |
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337 | * |
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338 | * \return true if CRT is connected. |
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339 | * \return false if CRT is disconnected. |
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340 | */ |
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341 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
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342 | { |
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343 | struct drm_device *dev = connector->dev; |
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344 | struct drm_i915_private *dev_priv = dev->dev_private; |
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345 | u32 hotplug_en, orig, stat; |
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346 | bool ret = false; |
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347 | int i, tries = 0; |
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348 | |||
349 | if (HAS_PCH_SPLIT(dev)) |
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350 | return intel_ironlake_crt_detect_hotplug(connector); |
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351 | |||
3031 | serge | 352 | if (IS_VALLEYVIEW(dev)) |
353 | return valleyview_crt_detect_hotplug(connector); |
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354 | |||
2330 | Serge | 355 | /* |
356 | * On 4 series desktop, CRT detect sequence need to be done twice |
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357 | * to get a reliable result. |
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358 | */ |
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359 | |||
360 | if (IS_G4X(dev) && !IS_GM45(dev)) |
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361 | tries = 2; |
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362 | else |
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363 | tries = 1; |
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364 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
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365 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
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366 | |||
367 | for (i = 0; i < tries ; i++) { |
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368 | /* turn on the FORCE_DETECT */ |
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369 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
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370 | /* wait for FORCE_DETECT to go off */ |
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371 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
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372 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
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373 | 1000)) |
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374 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
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375 | } |
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376 | |||
377 | stat = I915_READ(PORT_HOTPLUG_STAT); |
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378 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
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379 | ret = true; |
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380 | |||
381 | /* clear the interrupt we just generated, if any */ |
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382 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
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383 | |||
384 | /* and put the bits back */ |
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385 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
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386 | |||
387 | return ret; |
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388 | } |
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389 | |||
3031 | serge | 390 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
391 | struct i2c_adapter *i2c) |
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392 | { |
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393 | struct edid *edid; |
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394 | |||
395 | edid = drm_get_edid(connector, i2c); |
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396 | |||
397 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
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398 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
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399 | intel_gmbus_force_bit(i2c, true); |
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400 | edid = drm_get_edid(connector, i2c); |
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401 | intel_gmbus_force_bit(i2c, false); |
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402 | } |
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403 | |||
404 | return edid; |
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405 | } |
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406 | |||
407 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
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408 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
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409 | struct i2c_adapter *adapter) |
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410 | { |
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411 | struct edid *edid; |
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3243 | Serge | 412 | int ret; |
3031 | serge | 413 | |
414 | edid = intel_crt_get_edid(connector, adapter); |
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415 | if (!edid) |
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416 | return 0; |
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417 | |||
3243 | Serge | 418 | ret = intel_connector_update_modes(connector, edid); |
419 | kfree(edid); |
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420 | |||
421 | return ret; |
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3031 | serge | 422 | } |
423 | |||
2330 | Serge | 424 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
425 | { |
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426 | struct intel_crt *crt = intel_attached_crt(connector); |
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427 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
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3031 | serge | 428 | struct edid *edid; |
429 | struct i2c_adapter *i2c; |
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2330 | Serge | 430 | |
3031 | serge | 431 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
2330 | Serge | 432 | |
3031 | serge | 433 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
434 | edid = intel_crt_get_edid(connector, i2c); |
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2330 | Serge | 435 | |
3031 | serge | 436 | if (edid) { |
437 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
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438 | |||
2330 | Serge | 439 | /* |
440 | * This may be a DVI-I connector with a shared DDC |
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441 | * link between analog and digital outputs, so we |
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442 | * have to check the EDID input spec of the attached device. |
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443 | */ |
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444 | if (!is_digital) { |
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445 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
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446 | return true; |
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3031 | serge | 447 | } |
448 | |||
449 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
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2330 | Serge | 450 | } else { |
3031 | serge | 451 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
2330 | Serge | 452 | } |
453 | |||
3031 | serge | 454 | kfree(edid); |
455 | |||
2330 | Serge | 456 | return false; |
457 | } |
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458 | |||
459 | static enum drm_connector_status |
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460 | intel_crt_load_detect(struct intel_crt *crt) |
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461 | { |
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462 | struct drm_device *dev = crt->base.base.dev; |
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463 | struct drm_i915_private *dev_priv = dev->dev_private; |
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464 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
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465 | uint32_t save_bclrpat; |
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466 | uint32_t save_vtotal; |
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467 | uint32_t vtotal, vactive; |
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468 | uint32_t vsample; |
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469 | uint32_t vblank, vblank_start, vblank_end; |
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470 | uint32_t dsl; |
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471 | uint32_t bclrpat_reg; |
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472 | uint32_t vtotal_reg; |
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473 | uint32_t vblank_reg; |
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474 | uint32_t vsync_reg; |
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475 | uint32_t pipeconf_reg; |
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476 | uint32_t pipe_dsl_reg; |
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477 | uint8_t st00; |
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478 | enum drm_connector_status status; |
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479 | |||
480 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
||
481 | |||
482 | bclrpat_reg = BCLRPAT(pipe); |
||
483 | vtotal_reg = VTOTAL(pipe); |
||
484 | vblank_reg = VBLANK(pipe); |
||
485 | vsync_reg = VSYNC(pipe); |
||
486 | pipeconf_reg = PIPECONF(pipe); |
||
487 | pipe_dsl_reg = PIPEDSL(pipe); |
||
488 | |||
489 | save_bclrpat = I915_READ(bclrpat_reg); |
||
490 | save_vtotal = I915_READ(vtotal_reg); |
||
491 | vblank = I915_READ(vblank_reg); |
||
492 | |||
493 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
||
494 | vactive = (save_vtotal & 0x7ff) + 1; |
||
495 | |||
496 | vblank_start = (vblank & 0xfff) + 1; |
||
497 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
||
498 | |||
499 | /* Set the border color to purple. */ |
||
500 | I915_WRITE(bclrpat_reg, 0x500050); |
||
501 | |||
502 | if (!IS_GEN2(dev)) { |
||
503 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
||
504 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
||
505 | POSTING_READ(pipeconf_reg); |
||
506 | /* Wait for next Vblank to substitue |
||
507 | * border color for Color info */ |
||
508 | intel_wait_for_vblank(dev, pipe); |
||
509 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
510 | status = ((st00 & (1 << 4)) != 0) ? |
||
511 | connector_status_connected : |
||
512 | connector_status_disconnected; |
||
513 | |||
514 | I915_WRITE(pipeconf_reg, pipeconf); |
||
515 | } else { |
||
516 | bool restore_vblank = false; |
||
517 | int count, detect; |
||
518 | |||
519 | /* |
||
520 | * If there isn't any border, add some. |
||
521 | * Yes, this will flicker |
||
522 | */ |
||
523 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
||
524 | uint32_t vsync = I915_READ(vsync_reg); |
||
525 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
||
526 | |||
527 | vblank_start = vsync_start; |
||
528 | I915_WRITE(vblank_reg, |
||
529 | (vblank_start - 1) | |
||
530 | ((vblank_end - 1) << 16)); |
||
531 | restore_vblank = true; |
||
532 | } |
||
533 | /* sample in the vertical border, selecting the larger one */ |
||
534 | if (vblank_start - vactive >= vtotal - vblank_end) |
||
535 | vsample = (vblank_start + vactive) >> 1; |
||
536 | else |
||
537 | vsample = (vtotal + vblank_end) >> 1; |
||
538 | |||
539 | /* |
||
540 | * Wait for the border to be displayed |
||
541 | */ |
||
542 | while (I915_READ(pipe_dsl_reg) >= vactive) |
||
543 | ; |
||
544 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
||
545 | ; |
||
546 | /* |
||
547 | * Watch ST00 for an entire scanline |
||
548 | */ |
||
549 | detect = 0; |
||
550 | count = 0; |
||
551 | do { |
||
552 | count++; |
||
553 | /* Read the ST00 VGA status register */ |
||
554 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
555 | if (st00 & (1 << 4)) |
||
556 | detect++; |
||
557 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
||
558 | |||
559 | /* restore vblank if necessary */ |
||
560 | if (restore_vblank) |
||
561 | I915_WRITE(vblank_reg, vblank); |
||
562 | /* |
||
563 | * If more than 3/4 of the scanline detected a monitor, |
||
564 | * then it is assumed to be present. This works even on i830, |
||
565 | * where there isn't any way to force the border color across |
||
566 | * the screen |
||
567 | */ |
||
568 | status = detect * 4 > count * 3 ? |
||
569 | connector_status_connected : |
||
570 | connector_status_disconnected; |
||
571 | } |
||
572 | |||
573 | /* Restore previous settings */ |
||
574 | I915_WRITE(bclrpat_reg, save_bclrpat); |
||
575 | |||
576 | return status; |
||
577 | } |
||
578 | |||
579 | static enum drm_connector_status |
||
580 | intel_crt_detect(struct drm_connector *connector, bool force) |
||
581 | { |
||
582 | struct drm_device *dev = connector->dev; |
||
583 | struct intel_crt *crt = intel_attached_crt(connector); |
||
584 | enum drm_connector_status status; |
||
3031 | serge | 585 | struct intel_load_detect_pipe tmp; |
2330 | Serge | 586 | |
587 | if (I915_HAS_HOTPLUG(dev)) { |
||
3031 | serge | 588 | /* We can not rely on the HPD pin always being correctly wired |
589 | * up, for example many KVM do not pass it through, and so |
||
590 | * only trust an assertion that the monitor is connected. |
||
591 | */ |
||
2330 | Serge | 592 | if (intel_crt_detect_hotplug(connector)) { |
593 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
||
594 | return connector_status_connected; |
||
3031 | serge | 595 | } else |
2330 | Serge | 596 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
597 | } |
||
598 | |||
599 | if (intel_crt_detect_ddc(connector)) |
||
600 | return connector_status_connected; |
||
601 | |||
3031 | serge | 602 | /* Load detection is broken on HPD capable machines. Whoever wants a |
603 | * broken monitor (without edid) to work behind a broken kvm (that fails |
||
604 | * to have the right resistors for HP detection) needs to fix this up. |
||
605 | * For now just bail out. */ |
||
606 | if (I915_HAS_HOTPLUG(dev)) |
||
607 | return connector_status_disconnected; |
||
608 | |||
2330 | Serge | 609 | if (!force) |
610 | return connector->status; |
||
611 | |||
612 | /* for pre-945g platforms use load detect */ |
||
3031 | serge | 613 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
2330 | Serge | 614 | if (intel_crt_detect_ddc(connector)) |
615 | status = connector_status_connected; |
||
616 | else |
||
617 | status = intel_crt_load_detect(crt); |
||
3031 | serge | 618 | intel_release_load_detect_pipe(connector, &tmp); |
2330 | Serge | 619 | } else |
620 | status = connector_status_unknown; |
||
621 | |||
622 | return status; |
||
623 | } |
||
624 | |||
625 | static void intel_crt_destroy(struct drm_connector *connector) |
||
626 | { |
||
627 | drm_sysfs_connector_remove(connector); |
||
628 | drm_connector_cleanup(connector); |
||
629 | kfree(connector); |
||
630 | } |
||
631 | |||
632 | static int intel_crt_get_modes(struct drm_connector *connector) |
||
633 | { |
||
634 | struct drm_device *dev = connector->dev; |
||
635 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
636 | int ret; |
||
3031 | serge | 637 | struct i2c_adapter *i2c; |
2330 | Serge | 638 | |
3031 | serge | 639 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
640 | ret = intel_crt_ddc_get_modes(connector, i2c); |
||
2330 | Serge | 641 | if (ret || !IS_G4X(dev)) |
642 | return ret; |
||
643 | |||
644 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
||
3031 | serge | 645 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
646 | return intel_crt_ddc_get_modes(connector, i2c); |
||
2330 | Serge | 647 | } |
648 | |||
649 | static int intel_crt_set_property(struct drm_connector *connector, |
||
650 | struct drm_property *property, |
||
651 | uint64_t value) |
||
652 | { |
||
653 | return 0; |
||
654 | } |
||
655 | |||
656 | static void intel_crt_reset(struct drm_connector *connector) |
||
657 | { |
||
658 | struct drm_device *dev = connector->dev; |
||
3243 | Serge | 659 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 660 | struct intel_crt *crt = intel_attached_crt(connector); |
661 | |||
3243 | Serge | 662 | if (HAS_PCH_SPLIT(dev)) { |
663 | u32 adpa; |
||
664 | |||
3480 | Serge | 665 | adpa = I915_READ(crt->adpa_reg); |
3243 | Serge | 666 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
667 | adpa |= ADPA_HOTPLUG_BITS; |
||
3480 | Serge | 668 | I915_WRITE(crt->adpa_reg, adpa); |
669 | POSTING_READ(crt->adpa_reg); |
||
3243 | Serge | 670 | |
671 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
||
2330 | Serge | 672 | crt->force_hotplug_required = 1; |
3243 | Serge | 673 | } |
674 | |||
2330 | Serge | 675 | } |
676 | |||
677 | /* |
||
678 | * Routines for controlling stuff on the analog port |
||
679 | */ |
||
680 | |||
3031 | serge | 681 | static const struct drm_encoder_helper_funcs crt_encoder_funcs = { |
2330 | Serge | 682 | .mode_set = intel_crt_mode_set, |
683 | }; |
||
684 | |||
685 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
||
686 | .reset = intel_crt_reset, |
||
3031 | serge | 687 | .dpms = intel_crt_dpms, |
2330 | Serge | 688 | .detect = intel_crt_detect, |
689 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
690 | .destroy = intel_crt_destroy, |
||
691 | .set_property = intel_crt_set_property, |
||
692 | }; |
||
693 | |||
694 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
||
695 | .mode_valid = intel_crt_mode_valid, |
||
696 | .get_modes = intel_crt_get_modes, |
||
697 | .best_encoder = intel_best_encoder, |
||
698 | }; |
||
699 | |||
700 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
||
701 | .destroy = intel_encoder_destroy, |
||
702 | }; |
||
703 | |||
704 | void intel_crt_init(struct drm_device *dev) |
||
705 | { |
||
706 | struct drm_connector *connector; |
||
707 | struct intel_crt *crt; |
||
708 | struct intel_connector *intel_connector; |
||
709 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
710 | |||
711 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
||
712 | if (!crt) |
||
713 | return; |
||
714 | |||
715 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
||
716 | if (!intel_connector) { |
||
717 | kfree(crt); |
||
718 | return; |
||
719 | } |
||
720 | |||
721 | connector = &intel_connector->base; |
||
3480 | Serge | 722 | crt->connector = intel_connector; |
2330 | Serge | 723 | drm_connector_init(dev, &intel_connector->base, |
724 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
||
725 | |||
726 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
||
727 | DRM_MODE_ENCODER_DAC); |
||
728 | |||
729 | intel_connector_attach_encoder(intel_connector, &crt->base); |
||
730 | |||
731 | crt->base.type = INTEL_OUTPUT_ANALOG; |
||
3031 | serge | 732 | crt->base.cloneable = true; |
3243 | Serge | 733 | if (IS_I830(dev)) |
3031 | serge | 734 | crt->base.crtc_mask = (1 << 0); |
735 | else |
||
736 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
737 | |||
738 | if (IS_GEN2(dev)) |
||
739 | connector->interlace_allowed = 0; |
||
740 | else |
||
2330 | Serge | 741 | connector->interlace_allowed = 1; |
742 | connector->doublescan_allowed = 0; |
||
743 | |||
3031 | serge | 744 | if (HAS_PCH_SPLIT(dev)) |
745 | crt->adpa_reg = PCH_ADPA; |
||
746 | else if (IS_VALLEYVIEW(dev)) |
||
747 | crt->adpa_reg = VLV_ADPA; |
||
748 | else |
||
749 | crt->adpa_reg = ADPA; |
||
750 | |||
3746 | Serge | 751 | crt->base.compute_config = intel_crt_compute_config; |
3031 | serge | 752 | crt->base.disable = intel_disable_crt; |
753 | crt->base.enable = intel_enable_crt; |
||
3746 | Serge | 754 | if (I915_HAS_HOTPLUG(dev)) |
755 | crt->base.hpd_pin = HPD_CRT; |
||
3480 | Serge | 756 | if (HAS_DDI(dev)) |
3243 | Serge | 757 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
758 | else |
||
3031 | serge | 759 | crt->base.get_hw_state = intel_crt_get_hw_state; |
760 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
||
761 | |||
762 | drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs); |
||
2330 | Serge | 763 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
764 | |||
765 | drm_sysfs_connector_add(connector); |
||
766 | |||
3746 | Serge | 767 | if (!I915_HAS_HOTPLUG(dev)) |
768 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
||
2330 | Serge | 769 | |
770 | /* |
||
771 | * Configure the automatic hotplug detection stuff |
||
772 | */ |
||
773 | crt->force_hotplug_required = 0; |
||
774 | |||
3243 | Serge | 775 | /* |
3480 | Serge | 776 | * TODO: find a proper way to discover whether we need to set the the |
777 | * polarity and link reversal bits or not, instead of relying on the |
||
778 | * BIOS. |
||
3243 | Serge | 779 | */ |
3480 | Serge | 780 | if (HAS_PCH_LPT(dev)) { |
781 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
||
782 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
||
783 | |||
784 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; |
||
785 | } |
||
2330 | Serge | 786 | }><>><>><>><>><>=>><>=>><>>>> |