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2342 | Serge | 1 | /* |
2 | * Copyright © 2006 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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21 | * SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
28 | #ifndef _I830_BIOS_H_ |
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29 | #define _I830_BIOS_H_ |
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30 | |||
31 | #include "drmP.h" |
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32 | |||
33 | struct vbt_header { |
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34 | u8 signature[20]; /**< Always starts with 'VBT$' */ |
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35 | u16 version; /**< decimal */ |
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36 | u16 header_size; /**< in bytes */ |
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37 | u16 vbt_size; /**< in bytes */ |
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38 | u8 vbt_checksum; |
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39 | u8 reserved0; |
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40 | u32 bdb_offset; /**< from beginning of VBT */ |
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41 | u32 aim_offset[4]; /**< from beginning of VBT */ |
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42 | } __attribute__((packed)); |
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43 | |||
44 | struct bdb_header { |
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45 | u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ |
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46 | u16 version; /**< decimal */ |
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47 | u16 header_size; /**< in bytes */ |
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48 | u16 bdb_size; /**< in bytes */ |
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49 | }; |
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50 | |||
51 | /* strictly speaking, this is a "skip" block, but it has interesting info */ |
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52 | struct vbios_data { |
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53 | u8 type; /* 0 == desktop, 1 == mobile */ |
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54 | u8 relstage; |
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55 | u8 chipset; |
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56 | u8 lvds_present:1; |
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57 | u8 tv_present:1; |
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58 | u8 rsvd2:6; /* finish byte */ |
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59 | u8 rsvd3[4]; |
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60 | u8 signon[155]; |
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61 | u8 copyright[61]; |
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62 | u16 code_segment; |
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63 | u8 dos_boot_mode; |
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64 | u8 bandwidth_percent; |
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65 | u8 rsvd4; /* popup memory size */ |
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66 | u8 resize_pci_bios; |
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67 | u8 rsvd5; /* is crt already on ddc2 */ |
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68 | } __attribute__((packed)); |
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69 | |||
70 | /* |
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71 | * There are several types of BIOS data blocks (BDBs), each block has |
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72 | * an ID and size in the first 3 bytes (ID in first, size in next 2). |
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73 | * Known types are listed below. |
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74 | */ |
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75 | #define BDB_GENERAL_FEATURES 1 |
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76 | #define BDB_GENERAL_DEFINITIONS 2 |
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77 | #define BDB_OLD_TOGGLE_LIST 3 |
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78 | #define BDB_MODE_SUPPORT_LIST 4 |
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79 | #define BDB_GENERIC_MODE_TABLE 5 |
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80 | #define BDB_EXT_MMIO_REGS 6 |
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81 | #define BDB_SWF_IO 7 |
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82 | #define BDB_SWF_MMIO 8 |
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83 | #define BDB_DOT_CLOCK_TABLE 9 |
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84 | #define BDB_MODE_REMOVAL_TABLE 10 |
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85 | #define BDB_CHILD_DEVICE_TABLE 11 |
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86 | #define BDB_DRIVER_FEATURES 12 |
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87 | #define BDB_DRIVER_PERSISTENCE 13 |
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88 | #define BDB_EXT_TABLE_PTRS 14 |
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89 | #define BDB_DOT_CLOCK_OVERRIDE 15 |
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90 | #define BDB_DISPLAY_SELECT 16 |
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91 | /* 17 rsvd */ |
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92 | #define BDB_DRIVER_ROTATION 18 |
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93 | #define BDB_DISPLAY_REMOVE 19 |
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94 | #define BDB_OEM_CUSTOM 20 |
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95 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ |
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96 | #define BDB_SDVO_LVDS_OPTIONS 22 |
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97 | #define BDB_SDVO_PANEL_DTDS 23 |
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98 | #define BDB_SDVO_LVDS_PNP_IDS 24 |
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99 | #define BDB_SDVO_LVDS_POWER_SEQ 25 |
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100 | #define BDB_TV_OPTIONS 26 |
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101 | #define BDB_EDP 27 |
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102 | #define BDB_LVDS_OPTIONS 40 |
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103 | #define BDB_LVDS_LFP_DATA_PTRS 41 |
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104 | #define BDB_LVDS_LFP_DATA 42 |
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105 | #define BDB_LVDS_BACKLIGHT 43 |
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106 | #define BDB_LVDS_POWER 44 |
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107 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ |
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108 | |||
109 | struct bdb_general_features { |
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110 | /* bits 1 */ |
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111 | u8 panel_fitting:2; |
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112 | u8 flexaim:1; |
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113 | u8 msg_enable:1; |
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114 | u8 clear_screen:3; |
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115 | u8 color_flip:1; |
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116 | |||
117 | /* bits 2 */ |
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118 | u8 download_ext_vbt:1; |
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119 | u8 enable_ssc:1; |
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120 | u8 ssc_freq:1; |
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121 | u8 enable_lfp_on_override:1; |
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122 | u8 disable_ssc_ddt:1; |
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123 | u8 rsvd7:1; |
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124 | u8 display_clock_mode:1; |
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125 | u8 rsvd8:1; /* finish byte */ |
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126 | |||
127 | /* bits 3 */ |
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128 | u8 disable_smooth_vision:1; |
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129 | u8 single_dvi:1; |
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130 | u8 rsvd9:6; /* finish byte */ |
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131 | |||
132 | /* bits 4 */ |
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133 | u8 legacy_monitor_detect; |
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134 | |||
135 | /* bits 5 */ |
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136 | u8 int_crt_support:1; |
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137 | u8 int_tv_support:1; |
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138 | u8 int_efp_support:1; |
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139 | u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ |
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140 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ |
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141 | u8 rsvd11:3; /* finish byte */ |
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142 | } __attribute__((packed)); |
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143 | |||
144 | /* pre-915 */ |
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145 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ |
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146 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ |
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147 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ |
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148 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ |
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149 | |||
150 | /* Pre 915 */ |
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151 | #define DEVICE_TYPE_NONE 0x00 |
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152 | #define DEVICE_TYPE_CRT 0x01 |
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153 | #define DEVICE_TYPE_TV 0x09 |
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154 | #define DEVICE_TYPE_EFP 0x12 |
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155 | #define DEVICE_TYPE_LFP 0x22 |
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156 | /* On 915+ */ |
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157 | #define DEVICE_TYPE_CRT_DPMS 0x6001 |
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158 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 |
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159 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 |
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160 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 |
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161 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c |
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162 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 |
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163 | #define DEVICE_TYPE_TV_SCART 0x0209 |
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164 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 |
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165 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 |
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166 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 |
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167 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 |
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168 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 |
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169 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 |
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170 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 |
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171 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 |
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172 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 |
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173 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 |
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174 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 |
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175 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 |
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176 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 |
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177 | |||
178 | #define DEVICE_CFG_NONE 0x00 |
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179 | #define DEVICE_CFG_12BIT_DVOB 0x01 |
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180 | #define DEVICE_CFG_12BIT_DVOC 0x02 |
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181 | #define DEVICE_CFG_24BIT_DVOBC 0x09 |
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182 | #define DEVICE_CFG_24BIT_DVOCB 0x0a |
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183 | #define DEVICE_CFG_DUAL_DVOB 0x11 |
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184 | #define DEVICE_CFG_DUAL_DVOC 0x12 |
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185 | #define DEVICE_CFG_DUAL_DVOBC 0x13 |
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186 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 |
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187 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a |
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188 | |||
189 | #define DEVICE_WIRE_NONE 0x00 |
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190 | #define DEVICE_WIRE_DVOB 0x01 |
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191 | #define DEVICE_WIRE_DVOC 0x02 |
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192 | #define DEVICE_WIRE_DVOBC 0x03 |
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193 | #define DEVICE_WIRE_DVOBB 0x05 |
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194 | #define DEVICE_WIRE_DVOCC 0x06 |
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195 | #define DEVICE_WIRE_DVOB_MASTER 0x0d |
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196 | #define DEVICE_WIRE_DVOC_MASTER 0x0e |
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197 | |||
198 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
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199 | #define DEVICE_PORT_DVOB 0x01 |
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200 | #define DEVICE_PORT_DVOC 0x02 |
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201 | |||
202 | struct child_device_config { |
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203 | u16 handle; |
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204 | u16 device_type; |
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205 | u8 device_id[10]; /* ascii string */ |
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206 | u16 addin_offset; |
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207 | u8 dvo_port; /* See Device_PORT_* above */ |
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208 | u8 i2c_pin; |
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209 | u8 slave_addr; |
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210 | u8 ddc_pin; |
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211 | u16 edid_ptr; |
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212 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
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213 | u8 dvo2_port; |
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214 | u8 i2c2_pin; |
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215 | u8 slave2_addr; |
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216 | u8 ddc2_pin; |
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217 | u8 capabilities; |
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218 | u8 dvo_wiring;/* See DEVICE_WIRE_* above */ |
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219 | u8 dvo2_wiring; |
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220 | u16 extended_type; |
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221 | u8 dvo_function; |
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222 | } __attribute__((packed)); |
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223 | |||
224 | struct bdb_general_definitions { |
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225 | /* DDC GPIO */ |
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226 | u8 crt_ddc_gmbus_pin; |
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227 | |||
228 | /* DPMS bits */ |
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229 | u8 dpms_acpi:1; |
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230 | u8 skip_boot_crt_detect:1; |
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231 | u8 dpms_aim:1; |
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232 | u8 rsvd1:5; /* finish byte */ |
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233 | |||
234 | /* boot device bits */ |
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235 | u8 boot_display[2]; |
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236 | u8 child_dev_size; |
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237 | |||
238 | /* |
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239 | * Device info: |
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240 | * If TV is present, it'll be at devices[0]. |
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241 | * LVDS will be next, either devices[0] or [1], if present. |
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242 | * On some platforms the number of device is 6. But could be as few as |
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243 | * 4 if both TV and LVDS are missing. |
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244 | * And the device num is related with the size of general definition |
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245 | * block. It is obtained by using the following formula: |
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246 | * number = (block_size - sizeof(bdb_general_definitions))/ |
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247 | * sizeof(child_device_config); |
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248 | */ |
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249 | struct child_device_config devices[0]; |
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250 | } __attribute__((packed)); |
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251 | |||
252 | struct bdb_lvds_options { |
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253 | u8 panel_type; |
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254 | u8 rsvd1; |
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255 | /* LVDS capabilities, stored in a dword */ |
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256 | u8 pfit_mode:2; |
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257 | u8 pfit_text_mode_enhanced:1; |
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258 | u8 pfit_gfx_mode_enhanced:1; |
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259 | u8 pfit_ratio_auto:1; |
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260 | u8 pixel_dither:1; |
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261 | u8 lvds_edid:1; |
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262 | u8 rsvd2:1; |
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263 | u8 rsvd4; |
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264 | } __attribute__((packed)); |
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265 | |||
266 | /* LFP pointer table contains entries to the struct below */ |
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267 | struct bdb_lvds_lfp_data_ptr { |
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268 | u16 fp_timing_offset; /* offsets are from start of bdb */ |
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269 | u8 fp_table_size; |
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270 | u16 dvo_timing_offset; |
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271 | u8 dvo_table_size; |
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272 | u16 panel_pnp_id_offset; |
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273 | u8 pnp_table_size; |
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274 | } __attribute__((packed)); |
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275 | |||
276 | struct bdb_lvds_lfp_data_ptrs { |
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277 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ |
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278 | struct bdb_lvds_lfp_data_ptr ptr[16]; |
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279 | } __attribute__((packed)); |
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280 | |||
281 | /* LFP data has 3 blocks per entry */ |
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282 | struct lvds_fp_timing { |
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283 | u16 x_res; |
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284 | u16 y_res; |
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285 | u32 lvds_reg; |
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286 | u32 lvds_reg_val; |
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287 | u32 pp_on_reg; |
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288 | u32 pp_on_reg_val; |
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289 | u32 pp_off_reg; |
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290 | u32 pp_off_reg_val; |
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291 | u32 pp_cycle_reg; |
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292 | u32 pp_cycle_reg_val; |
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293 | u32 pfit_reg; |
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294 | u32 pfit_reg_val; |
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295 | u16 terminator; |
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296 | } __attribute__((packed)); |
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297 | |||
298 | struct lvds_dvo_timing { |
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299 | u16 clock; /**< In 10khz */ |
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300 | u8 hactive_lo; |
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301 | u8 hblank_lo; |
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302 | u8 hblank_hi:4; |
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303 | u8 hactive_hi:4; |
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304 | u8 vactive_lo; |
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305 | u8 vblank_lo; |
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306 | u8 vblank_hi:4; |
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307 | u8 vactive_hi:4; |
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308 | u8 hsync_off_lo; |
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309 | u8 hsync_pulse_width; |
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310 | u8 vsync_pulse_width:4; |
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311 | u8 vsync_off:4; |
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312 | u8 rsvd0:6; |
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313 | u8 hsync_off_hi:2; |
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314 | u8 h_image; |
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315 | u8 v_image; |
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316 | u8 max_hv; |
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317 | u8 h_border; |
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318 | u8 v_border; |
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319 | u8 rsvd1:3; |
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320 | u8 digital:2; |
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321 | u8 vsync_positive:1; |
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322 | u8 hsync_positive:1; |
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323 | u8 rsvd2:1; |
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324 | } __attribute__((packed)); |
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325 | |||
326 | struct lvds_pnp_id { |
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327 | u16 mfg_name; |
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328 | u16 product_code; |
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329 | u32 serial; |
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330 | u8 mfg_week; |
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331 | u8 mfg_year; |
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332 | } __attribute__((packed)); |
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333 | |||
334 | struct bdb_lvds_lfp_data_entry { |
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335 | struct lvds_fp_timing fp_timing; |
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336 | struct lvds_dvo_timing dvo_timing; |
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337 | struct lvds_pnp_id pnp_id; |
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338 | } __attribute__((packed)); |
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339 | |||
340 | struct bdb_lvds_lfp_data { |
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341 | struct bdb_lvds_lfp_data_entry data[16]; |
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342 | } __attribute__((packed)); |
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343 | |||
344 | struct aimdb_header { |
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345 | char signature[16]; |
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346 | char oem_device[20]; |
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347 | u16 aimdb_version; |
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348 | u16 aimdb_header_size; |
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349 | u16 aimdb_size; |
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350 | } __attribute__((packed)); |
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351 | |||
352 | struct aimdb_block { |
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353 | u8 aimdb_id; |
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354 | u16 aimdb_size; |
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355 | } __attribute__((packed)); |
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356 | |||
357 | struct vch_panel_data { |
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358 | u16 fp_timing_offset; |
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359 | u8 fp_timing_size; |
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360 | u16 dvo_timing_offset; |
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361 | u8 dvo_timing_size; |
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362 | u16 text_fitting_offset; |
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363 | u8 text_fitting_size; |
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364 | u16 graphics_fitting_offset; |
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365 | u8 graphics_fitting_size; |
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366 | } __attribute__((packed)); |
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367 | |||
368 | struct vch_bdb_22 { |
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369 | struct aimdb_block aimdb_block; |
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370 | struct vch_panel_data panels[16]; |
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371 | } __attribute__((packed)); |
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372 | |||
373 | struct bdb_sdvo_lvds_options { |
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374 | u8 panel_backlight; |
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375 | u8 h40_set_panel_type; |
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376 | u8 panel_type; |
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377 | u8 ssc_clk_freq; |
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378 | u16 als_low_trip; |
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379 | u16 als_high_trip; |
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380 | u8 sclalarcoeff_tab_row_num; |
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381 | u8 sclalarcoeff_tab_row_size; |
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382 | u8 coefficient[8]; |
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383 | u8 panel_misc_bits_1; |
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384 | u8 panel_misc_bits_2; |
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385 | u8 panel_misc_bits_3; |
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386 | u8 panel_misc_bits_4; |
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387 | } __attribute__((packed)); |
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388 | |||
389 | |||
390 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
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391 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 |
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392 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 |
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393 | #define BDB_DRIVER_FEATURE_EDP 3 |
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394 | |||
395 | struct bdb_driver_features { |
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396 | u8 boot_dev_algorithm:1; |
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397 | u8 block_display_switch:1; |
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398 | u8 allow_display_switch:1; |
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399 | u8 hotplug_dvo:1; |
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400 | u8 dual_view_zoom:1; |
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401 | u8 int15h_hook:1; |
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402 | u8 sprite_in_clone:1; |
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403 | u8 primary_lfp_id:1; |
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404 | |||
405 | u16 boot_mode_x; |
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406 | u16 boot_mode_y; |
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407 | u8 boot_mode_bpp; |
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408 | u8 boot_mode_refresh; |
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409 | |||
410 | u16 enable_lfp_primary:1; |
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411 | u16 selective_mode_pruning:1; |
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412 | u16 dual_frequency:1; |
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413 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ |
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414 | u16 nt_clone_support:1; |
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415 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ |
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416 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ |
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417 | u16 cui_aspect_scaling:1; |
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418 | u16 preserve_aspect_ratio:1; |
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419 | u16 sdvo_device_power_down:1; |
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420 | u16 crt_hotplug:1; |
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421 | u16 lvds_config:2; |
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422 | u16 tv_hotplug:1; |
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423 | u16 hdmi_config:2; |
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424 | |||
425 | u8 static_display:1; |
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426 | u8 reserved2:7; |
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427 | u16 legacy_crt_max_x; |
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428 | u16 legacy_crt_max_y; |
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429 | u8 legacy_crt_max_refresh; |
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430 | |||
431 | u8 hdmi_termination; |
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432 | u8 custom_vbt_version; |
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433 | } __attribute__((packed)); |
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434 | |||
435 | #define EDP_18BPP 0 |
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436 | #define EDP_24BPP 1 |
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437 | #define EDP_30BPP 2 |
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438 | #define EDP_RATE_1_62 0 |
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439 | #define EDP_RATE_2_7 1 |
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440 | #define EDP_LANE_1 0 |
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441 | #define EDP_LANE_2 1 |
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442 | #define EDP_LANE_4 3 |
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443 | #define EDP_PREEMPHASIS_NONE 0 |
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444 | #define EDP_PREEMPHASIS_3_5dB 1 |
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445 | #define EDP_PREEMPHASIS_6dB 2 |
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446 | #define EDP_PREEMPHASIS_9_5dB 3 |
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447 | #define EDP_VSWING_0_4V 0 |
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448 | #define EDP_VSWING_0_6V 1 |
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449 | #define EDP_VSWING_0_8V 2 |
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450 | #define EDP_VSWING_1_2V 3 |
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451 | |||
452 | struct edp_power_seq { |
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453 | u16 t1_t3; |
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454 | u16 t8; |
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455 | u16 t9; |
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456 | u16 t10; |
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457 | u16 t11_t12; |
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458 | } __attribute__ ((packed)); |
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459 | |||
460 | struct edp_link_params { |
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461 | u8 rate:4; |
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462 | u8 lanes:4; |
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463 | u8 preemphasis:4; |
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464 | u8 vswing:4; |
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465 | } __attribute__ ((packed)); |
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466 | |||
467 | struct bdb_edp { |
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468 | struct edp_power_seq power_seqs[16]; |
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469 | u32 color_depth; |
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470 | struct edp_link_params link_params[16]; |
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471 | u32 sdrrs_msa_timing_delay; |
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472 | |||
473 | /* ith bit indicates enabled/disabled for (i+1)th panel */ |
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474 | u16 edp_s3d_feature; |
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475 | u16 edp_t3_optimization; |
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476 | } __attribute__ ((packed)); |
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477 | |||
478 | void intel_setup_bios(struct drm_device *dev); |
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479 | bool intel_parse_bios(struct drm_device *dev); |
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480 | |||
481 | /* |
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482 | * Driver<->VBIOS interaction occurs through scratch bits in |
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483 | * GR18 & SWF*. |
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484 | */ |
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485 | |||
486 | /* GR18 bits are set on display switch and hotkey events */ |
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487 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ |
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488 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ |
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489 | #define GR18_HK_NONE (0x0<<3) |
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490 | #define GR18_HK_LFP_STRETCH (0x1<<3) |
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491 | #define GR18_HK_TOGGLE_DISP (0x2<<3) |
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492 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ |
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493 | #define GR18_HK_POPUP_DISABLED (0x6<<3) |
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494 | #define GR18_HK_POPUP_ENABLED (0x7<<3) |
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495 | #define GR18_HK_PFIT (0x8<<3) |
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496 | #define GR18_HK_APM_CHANGE (0xa<<3) |
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497 | #define GR18_HK_MULTIPLE (0xc<<3) |
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498 | #define GR18_USER_INT_EN (1<<2) |
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499 | #define GR18_A0000_FLUSH_EN (1<<1) |
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500 | #define GR18_SMM_EN (1<<0) |
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501 | |||
502 | /* Set by driver, cleared by VBIOS */ |
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503 | #define SWF00_YRES_SHIFT 16 |
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504 | #define SWF00_XRES_SHIFT 0 |
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505 | #define SWF00_RES_MASK 0xffff |
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506 | |||
507 | /* Set by VBIOS at boot time and driver at runtime */ |
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508 | #define SWF01_TV2_FORMAT_SHIFT 8 |
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509 | #define SWF01_TV1_FORMAT_SHIFT 0 |
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510 | #define SWF01_TV_FORMAT_MASK 0xffff |
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511 | |||
512 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) |
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513 | #define SWF10_GTT_OVERRIDE_EN (1<<28) |
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514 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ |
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515 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) |
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516 | #define SWF10_OLD_TOGGLE 0x0 |
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517 | #define SWF10_TOGGLE_LIST_1 0x1 |
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518 | #define SWF10_TOGGLE_LIST_2 0x2 |
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519 | #define SWF10_TOGGLE_LIST_3 0x3 |
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520 | #define SWF10_TOGGLE_LIST_4 0x4 |
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521 | #define SWF10_PANNING_EN (1<<23) |
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522 | #define SWF10_DRIVER_LOADED (1<<22) |
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523 | #define SWF10_EXTENDED_DESKTOP (1<<21) |
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524 | #define SWF10_EXCLUSIVE_MODE (1<<20) |
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525 | #define SWF10_OVERLAY_EN (1<<19) |
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526 | #define SWF10_PLANEB_HOLDOFF (1<<18) |
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527 | #define SWF10_PLANEA_HOLDOFF (1<<17) |
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528 | #define SWF10_VGA_HOLDOFF (1<<16) |
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529 | #define SWF10_ACTIVE_DISP_MASK 0xffff |
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530 | #define SWF10_PIPEB_LFP2 (1<<15) |
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531 | #define SWF10_PIPEB_EFP2 (1<<14) |
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532 | #define SWF10_PIPEB_TV2 (1<<13) |
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533 | #define SWF10_PIPEB_CRT2 (1<<12) |
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534 | #define SWF10_PIPEB_LFP (1<<11) |
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535 | #define SWF10_PIPEB_EFP (1<<10) |
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536 | #define SWF10_PIPEB_TV (1<<9) |
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537 | #define SWF10_PIPEB_CRT (1<<8) |
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538 | #define SWF10_PIPEA_LFP2 (1<<7) |
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539 | #define SWF10_PIPEA_EFP2 (1<<6) |
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540 | #define SWF10_PIPEA_TV2 (1<<5) |
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541 | #define SWF10_PIPEA_CRT2 (1<<4) |
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542 | #define SWF10_PIPEA_LFP (1<<3) |
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543 | #define SWF10_PIPEA_EFP (1<<2) |
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544 | #define SWF10_PIPEA_TV (1<<1) |
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545 | #define SWF10_PIPEA_CRT (1<<0) |
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546 | |||
547 | #define SWF11_MEMORY_SIZE_SHIFT 16 |
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548 | #define SWF11_SV_TEST_EN (1<<15) |
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549 | #define SWF11_IS_AGP (1<<14) |
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550 | #define SWF11_DISPLAY_HOLDOFF (1<<13) |
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551 | #define SWF11_DPMS_REDUCED (1<<12) |
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552 | #define SWF11_IS_VBE_MODE (1<<11) |
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553 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ |
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554 | #define SWF11_DPMS_MASK 0x07 |
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555 | #define SWF11_DPMS_OFF (1<<2) |
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556 | #define SWF11_DPMS_SUSPEND (1<<1) |
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557 | #define SWF11_DPMS_STANDBY (1<<0) |
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558 | #define SWF11_DPMS_ON 0 |
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559 | |||
560 | #define SWF14_GFX_PFIT_EN (1<<31) |
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561 | #define SWF14_TEXT_PFIT_EN (1<<30) |
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562 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ |
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563 | #define SWF14_POPUP_EN (1<<28) |
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564 | #define SWF14_DISPLAY_HOLDOFF (1<<27) |
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565 | #define SWF14_DISP_DETECT_EN (1<<26) |
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566 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ |
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567 | #define SWF14_DRIVER_STATUS (1<<24) |
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568 | #define SWF14_OS_TYPE_WIN9X (1<<23) |
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569 | #define SWF14_OS_TYPE_WINNT (1<<22) |
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570 | /* 21:19 rsvd */ |
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571 | #define SWF14_PM_TYPE_MASK 0x00070000 |
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572 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) |
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573 | #define SWF14_PM_ACPI (0x3 << 16) |
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574 | #define SWF14_PM_APM_12 (0x2 << 16) |
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575 | #define SWF14_PM_APM_11 (0x1 << 16) |
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576 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ |
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577 | /* if GR18 indicates a display switch */ |
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578 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) |
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579 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) |
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580 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) |
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581 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) |
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582 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) |
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583 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) |
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584 | #define SWF14_DS_PIPEB_TV_EN (1<<9) |
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585 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) |
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586 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) |
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587 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) |
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588 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) |
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589 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) |
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590 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) |
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591 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) |
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592 | #define SWF14_DS_PIPEA_TV_EN (1<<1) |
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593 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) |
||
594 | /* if GR18 indicates a panel fitting request */ |
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595 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ |
||
596 | /* if GR18 indicates an APM change request */ |
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597 | #define SWF14_APM_HIBERNATE 0x4 |
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598 | #define SWF14_APM_SUSPEND 0x3 |
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599 | #define SWF14_APM_STANDBY 0x1 |
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600 | #define SWF14_APM_RESTORE 0x0 |
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601 | |||
602 | /* Add the device class for LFP, TV, HDMI */ |
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603 | #define DEVICE_TYPE_INT_LFP 0x1022 |
||
604 | #define DEVICE_TYPE_INT_TV 0x1009 |
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605 | #define DEVICE_TYPE_HDMI 0x60D2 |
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606 | #define DEVICE_TYPE_DP 0x68C6 |
||
607 | #define DEVICE_TYPE_eDP 0x78C6 |
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608 | |||
609 | /* define the DVO port for HDMI output type */ |
||
610 | #define DVO_B 1 |
||
611 | #define DVO_C 2 |
||
612 | #define DVO_D 3 |
||
613 | |||
614 | /* define the PORT for DP output type */ |
||
615 | #define PORT_IDPB 7 |
||
616 | #define PORT_IDPC 8 |
||
617 | #define PORT_IDPD 9 |
||
618 | |||
619 | #endif /* _I830_BIOS_H_ */0)><0)>0) |