Rev 6084 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
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| 6084 | serge | 1 | /* |
| 2 | * Copyright(c) 2011-2015 Intel Corporation. All rights reserved. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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| 21 | * SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | #ifndef _I915_VGPU_H_ |
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| 25 | #define _I915_VGPU_H_ |
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| 26 | |||
| 27 | /* The MMIO offset of the shared info between guest and host emulator */ |
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| 28 | #define VGT_PVINFO_PAGE 0x78000 |
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| 29 | #define VGT_PVINFO_SIZE 0x1000 |
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| 30 | |||
| 31 | /* |
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| 32 | * The following structure pages are defined in GEN MMIO space |
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| 33 | * for virtualization. (One page for now) |
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| 34 | */ |
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| 35 | #define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */ |
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| 36 | #define VGT_VERSION_MAJOR 1 |
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| 37 | #define VGT_VERSION_MINOR 0 |
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| 38 | |||
| 39 | #define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor)) |
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| 40 | #define INTEL_VGT_IF_VERSION \ |
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| 41 | INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR) |
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| 42 | |||
| 43 | /* |
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| 44 | * notifications from guest to vgpu device model |
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| 45 | */ |
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| 46 | enum vgt_g2v_type { |
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| 47 | VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2, |
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| 48 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY, |
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| 49 | VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE, |
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| 50 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY, |
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| 51 | VGT_G2V_EXECLIST_CONTEXT_CREATE, |
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| 52 | VGT_G2V_EXECLIST_CONTEXT_DESTROY, |
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| 53 | VGT_G2V_MAX, |
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| 54 | }; |
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| 55 | |||
| 56 | struct vgt_if { |
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| 57 | uint64_t magic; /* VGT_MAGIC */ |
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| 58 | uint16_t version_major; |
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| 59 | uint16_t version_minor; |
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| 60 | uint32_t vgt_id; /* ID of vGT instance */ |
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| 61 | uint32_t rsv1[12]; /* pad to offset 0x40 */ |
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| 62 | /* |
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| 63 | * Data structure to describe the balooning info of resources. |
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| 64 | * Each VM can only have one portion of continuous area for now. |
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| 65 | * (May support scattered resource in future) |
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| 66 | * (starting from offset 0x40) |
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| 67 | */ |
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| 68 | struct { |
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| 69 | /* Aperture register balooning */ |
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| 70 | struct { |
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| 71 | uint32_t base; |
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| 72 | uint32_t size; |
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| 73 | } mappable_gmadr; /* aperture */ |
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| 74 | /* GMADR register balooning */ |
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| 75 | struct { |
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| 76 | uint32_t base; |
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| 77 | uint32_t size; |
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| 78 | } nonmappable_gmadr; /* non aperture */ |
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| 79 | /* allowed fence registers */ |
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| 80 | uint32_t fence_num; |
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| 81 | uint32_t rsv2[3]; |
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| 82 | } avail_rs; /* available/assigned resource */ |
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| 83 | uint32_t rsv3[0x200 - 24]; /* pad to half page */ |
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| 84 | /* |
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| 85 | * The bottom half page is for response from Gfx driver to hypervisor. |
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| 86 | */ |
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| 87 | uint32_t rsv4; |
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| 88 | uint32_t display_ready; /* ready for display owner switch */ |
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| 89 | |||
| 90 | uint32_t rsv5[4]; |
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| 91 | |||
| 92 | uint32_t g2v_notify; |
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| 93 | uint32_t rsv6[7]; |
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| 94 | |||
| 6937 | serge | 95 | struct { |
| 96 | uint32_t lo; |
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| 97 | uint32_t hi; |
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| 98 | } pdp[4]; |
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| 6084 | serge | 99 | |
| 100 | uint32_t execlist_context_descriptor_lo; |
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| 101 | uint32_t execlist_context_descriptor_hi; |
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| 102 | |||
| 103 | uint32_t rsv7[0x200 - 24]; /* pad to one page */ |
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| 104 | } __packed; |
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| 105 | |||
| 106 | #define vgtif_reg(x) \ |
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| 6937 | serge | 107 | _MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)) |
| 6084 | serge | 108 | |
| 109 | /* vGPU display status to be used by the host side */ |
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| 110 | #define VGT_DRV_DISPLAY_NOT_READY 0 |
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| 111 | #define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */ |
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| 112 | |||
| 113 | extern void i915_check_vgpu(struct drm_device *dev); |
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| 114 | extern int intel_vgt_balloon(struct drm_device *dev); |
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| 115 | extern void intel_vgt_deballoon(void); |
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| 116 | |||
| 117 | #endif /* _I915_VGPU_H_ */ |