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2325 Serge 1 
/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 
 * All Rights Reserved.
3 
 *
4 
 * Permission is hereby granted, free of charge, to any person obtaining a
5 
 * copy of this software and associated documentation files (the
6 
 * "Software"), to deal in the Software without restriction, including
7 
 * without limitation the rights to use, copy, modify, merge, publish,
8 
 * distribute, sub license, and/or sell copies of the Software, and to
9 
 * permit persons to whom the Software is furnished to do so, subject to
10 
 * the following conditions:
11 
 *
12 
 * The above copyright notice and this permission notice (including the
13 
 * next paragraph) shall be included in all copies or substantial portions
14 
 * of the Software.
15 
 *
16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 
 */
24 
 
25 
#ifndef _I915_REG_H_
26 
#define _I915_REG_H_
27 
 
28 
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
3243 Serge 29 
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
2325 Serge 30 
 
3031 serge 31 
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32 
 
33 
#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
34 
#define _MASKED_BIT_DISABLE(a) ((a) << 16)
35 
 
2325 Serge 36 
/* PCI config space */
37 
 
38 
#define HPLLCC	0xc0 /* 855 only */
39 
#define   GC_CLOCK_CONTROL_MASK		(0xf << 0)
40 
#define   GC_CLOCK_133_200		(0 << 0)
41 
#define   GC_CLOCK_100_200		(1 << 0)
42 
#define   GC_CLOCK_100_133		(2 << 0)
43 
#define   GC_CLOCK_166_250		(3 << 0)
44 
#define GCFGC2	0xda
45 
#define GCFGC	0xf0 /* 915+ only */
46 
#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
47 
#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
48 
#define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
4104 Serge 49 
#define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
50 
#define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
51 
#define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
52 
#define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
53 
#define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
54 
#define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
2325 Serge 55 
#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
56 
#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
57 
#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
58 
#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
59 
#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
60 
#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
61 
#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
62 
#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
63 
#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
64 
#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
65 
#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
66 
#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
67 
#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
68 
#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
69 
#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
70 
#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
71 
#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
72 
#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
73 
#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
74 
#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
75 
#define LBB	0xf4
76 
 
77 
/* Graphics reset regs */
78 
#define I965_GDRST 0xc0 /* PCI config register */
79 
#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
80 
#define  GRDOM_FULL	(0<<2)
81 
#define  GRDOM_RENDER	(1<<2)
82 
#define  GRDOM_MEDIA	(3<<2)
3746 Serge 83 
#define  GRDOM_MASK	(3<<2)
3031 serge 84 
#define  GRDOM_RESET_ENABLE (1<<0)
2325 Serge 85 
 
86 
#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
87 
#define   GEN6_MBC_SNPCR_SHIFT	21
88 
#define   GEN6_MBC_SNPCR_MASK	(3<<21)
89 
#define   GEN6_MBC_SNPCR_MAX	(0<<21)
90 
#define   GEN6_MBC_SNPCR_MED	(1<<21)
91 
#define   GEN6_MBC_SNPCR_LOW	(2<<21)
92 
#define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
93 
 
3031 serge 94 
#define GEN6_MBCTL		0x0907c
95 
#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
96 
#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
97 
#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
98 
#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
99 
#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
100 
 
2325 Serge 101 
#define GEN6_GDRST	0x941c
102 
#define  GEN6_GRDOM_FULL		(1 << 0)
103 
#define  GEN6_GRDOM_RENDER		(1 << 1)
104 
#define  GEN6_GRDOM_MEDIA		(1 << 2)
105 
#define  GEN6_GRDOM_BLT			(1 << 3)
106 
 
3031 serge 107 
#define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
108 
#define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
109 
#define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
110 
#define   PP_DIR_DCLV_2G		0xffffffff
111 
 
112 
#define GAM_ECOCHK			0x4090
113 
#define   ECOCHK_SNB_BIT		(1<<10)
3746 Serge 114 
#define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
3031 serge 115 
#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
116 
#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
3746 Serge 117 
#define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)
118 
#define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)
119 
#define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)
120 
#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
121 
#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
3031 serge 122 
 
123 
#define GAC_ECO_BITS			0x14090
3746 Serge 124 
#define   ECOBITS_SNB_BIT		(1<<13)
3031 serge 125 
#define   ECOBITS_PPGTT_CACHE64B	(3<<8)
126 
#define   ECOBITS_PPGTT_CACHE4B		(0<<8)
127 
 
128 
#define GAB_CTL				0x24000
129 
#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
130 
 
2325 Serge 131 
/* VGA stuff */
132 
 
133 
#define VGA_ST01_MDA 0x3ba
134 
#define VGA_ST01_CGA 0x3da
135 
 
136 
#define VGA_MSR_WRITE 0x3c2
137 
#define VGA_MSR_READ 0x3cc
138 
#define   VGA_MSR_MEM_EN (1<<1)
139 
#define   VGA_MSR_CGA_MODE (1<<0)
140 
 
4104 Serge 141 
#define VGA_SR_INDEX 0x3c4
3480 Serge 142 
#define SR01			1
4104 Serge 143 
#define VGA_SR_DATA 0x3c5
2325 Serge 144 
 
145 
#define VGA_AR_INDEX 0x3c0
146 
#define   VGA_AR_VID_EN (1<<5)
147 
#define VGA_AR_DATA_WRITE 0x3c0
148 
#define VGA_AR_DATA_READ 0x3c1
149 
 
150 
#define VGA_GR_INDEX 0x3ce
151 
#define VGA_GR_DATA 0x3cf
152 
/* GR05 */
153 
#define   VGA_GR_MEM_READ_MODE_SHIFT 3
154 
#define     VGA_GR_MEM_READ_MODE_PLANE 1
155 
/* GR06 */
156 
#define   VGA_GR_MEM_MODE_MASK 0xc
157 
#define   VGA_GR_MEM_MODE_SHIFT 2
158 
#define   VGA_GR_MEM_A0000_AFFFF 0
159 
#define   VGA_GR_MEM_A0000_BFFFF 1
160 
#define   VGA_GR_MEM_B0000_B7FFF 2
161 
#define   VGA_GR_MEM_B0000_BFFFF 3
162 
 
163 
#define VGA_DACMASK 0x3c6
164 
#define VGA_DACRX 0x3c7
165 
#define VGA_DACWX 0x3c8
166 
#define VGA_DACDATA 0x3c9
167 
 
168 
#define VGA_CR_INDEX_MDA 0x3b4
169 
#define VGA_CR_DATA_MDA 0x3b5
170 
#define VGA_CR_INDEX_CGA 0x3d4
171 
#define VGA_CR_DATA_CGA 0x3d5
172 
 
173 
/*
174 
 * Memory interface instructions used by the kernel
175 
 */
176 
#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
177 
 
178 
#define MI_NOOP			MI_INSTR(0, 0)
179 
#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
180 
#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
181 
#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
182 
#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
183 
#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
184 
#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
185 
#define MI_FLUSH		MI_INSTR(0x04, 0)
186 
#define   MI_READ_FLUSH		(1 << 0)
187 
#define   MI_EXE_FLUSH		(1 << 1)
188 
#define   MI_NO_WRITE_FLUSH	(1 << 2)
189 
#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
190 
#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
191 
#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
192 
#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
193 
#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
194 
#define   MI_SUSPEND_FLUSH_EN	(1<<0)
195 
#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
2342 Serge 196 
#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
2325 Serge 197 
#define   MI_OVERLAY_CONTINUE	(0x0<<21)
198 
#define   MI_OVERLAY_ON		(0x1<<21)
199 
#define   MI_OVERLAY_OFF	(0x2<<21)
200 
#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
201 
#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
202 
#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
203 
#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
3031 serge 204 
/* IVB has funny definitions for which plane to flip. */
205 
#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
206 
#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
207 
#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
208 
#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
209 
#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
210 
#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
211 
#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
212 
#define   MI_ARB_ENABLE			(1<<0)
213 
#define   MI_ARB_DISABLE		(0<<0)
214 
 
2325 Serge 215 
#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
216 
#define   MI_MM_SPACE_GTT		(1<<8)
217 
#define   MI_MM_SPACE_PHYSICAL		(0<<8)
218 
#define   MI_SAVE_EXT_STATE_EN		(1<<3)
219 
#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
220 
#define   MI_FORCE_RESTORE		(1<<1)
221 
#define   MI_RESTORE_INHIBIT		(1<<0)
222 
#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
223 
#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
224 
#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
225 
#define   MI_STORE_DWORD_INDEX_SHIFT 2
226 
/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
227 
 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
228 
 *   simply ignores the register load under certain conditions.
229 
 * - One can actually load arbitrary many arbitrary registers: Simply issue x
230 
 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
231 
 */
232 
#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
4104 Serge 233 
#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
2325 Serge 234 
#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
3243 Serge 235 
#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
2325 Serge 236 
#define   MI_INVALIDATE_TLB	(1<<18)
3243 Serge 237 
#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
2325 Serge 238 
#define   MI_INVALIDATE_BSD	(1<<7)
3243 Serge 239 
#define   MI_FLUSH_DW_USE_GTT		(1<<2)
240 
#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
2325 Serge 241 
#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
242 
#define   MI_BATCH_NON_SECURE	(1)
3243 Serge 243 
/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
2325 Serge 244 
#define   MI_BATCH_NON_SECURE_I965 (1<<8)
3243 Serge 245 
#define   MI_BATCH_PPGTT_HSW		(1<<8)
246 
#define   MI_BATCH_NON_SECURE_HSW 	(1<<13)
2325 Serge 247 
#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
3031 serge 248 
#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
2325 Serge 249 
#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */
250 
#define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
251 
#define  MI_SEMAPHORE_UPDATE	    (1<<21)
252 
#define  MI_SEMAPHORE_COMPARE	    (1<<20)
253 
#define  MI_SEMAPHORE_REGISTER	    (1<<18)
4104 Serge 254 
#define  MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
255 
#define  MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */
256 
#define  MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */
257 
#define  MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
258 
#define  MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */
259 
#define  MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */
260 
#define  MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
261 
#define  MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */
262 
#define  MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */
263 
#define  MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
264 
#define  MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */
265 
#define  MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */
266 
#define  MI_SEMAPHORE_SYNC_INVALID  (3<<16)
2325 Serge 267 
/*
268 
 * 3D instructions used by the kernel
269 
 */
270 
#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
271 
 
272 
#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
273 
#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
274 
#define   SC_UPDATE_SCISSOR       (0x1<<1)
275 
#define   SC_ENABLE_MASK          (0x1<<0)
276 
#define   SC_ENABLE               (0x1<<0)
277 
#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
278 
#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
279 
#define   SCI_YMIN_MASK      (0xffff<<16)
280 
#define   SCI_XMIN_MASK      (0xffff<<0)
281 
#define   SCI_YMAX_MASK      (0xffff<<16)
282 
#define   SCI_XMAX_MASK      (0xffff<<0)
283 
#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
284 
#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
285 
#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
286 
#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
287 
#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
288 
#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
289 
#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
290 
#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
291 
#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
292 
#define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
293 
#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
294 
#define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
295 
#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
296 
#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
297 
#define   BLT_DEPTH_8			(0<<24)
298 
#define   BLT_DEPTH_16_565		(1<<24)
299 
#define   BLT_DEPTH_16_1555		(2<<24)
300 
#define   BLT_DEPTH_32			(3<<24)
301 
#define   BLT_ROP_GXCOPY		(0xcc<<16)
302 
#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
303 
#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
304 
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
305 
#define   ASYNC_FLIP                (1<<22)
306 
#define   DISPLAY_PLANE_A           (0<<20)
307 
#define   DISPLAY_PLANE_B           (1<<20)
2342 Serge 308 
#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
3480 Serge 309 
#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
2342 Serge 310 
#define   PIPE_CONTROL_CS_STALL				(1<<20)
3031 serge 311 
#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
2325 Serge 312 
#define   PIPE_CONTROL_QW_WRITE	(1<<14)
313 
#define   PIPE_CONTROL_DEPTH_STALL (1<<13)
2342 Serge 314 
#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
315 
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
316 
#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
317 
#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
318 
#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
2325 Serge 319 
#define   PIPE_CONTROL_NOTIFY	(1<<8)
2342 Serge 320 
#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
321 
#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
322 
#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
323 
#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
324 
#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
2325 Serge 325 
#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
326 
 
327 
 
328 
/*
329 
 * Reset registers
330 
 */
331 
#define DEBUG_RESET_I830		0x6070
332 
#define  DEBUG_RESET_FULL		(1<<7)
333 
#define  DEBUG_RESET_RENDER		(1<<8)
334 
#define  DEBUG_RESET_DISPLAY		(1<<9)
335 
 
3031 serge 336 
/*
4104 Serge 337 
 * IOSF sideband
338 
 */
339 
#define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)
340 
#define   IOSF_DEVFN_SHIFT			24
341 
#define   IOSF_OPCODE_SHIFT			16
342 
#define   IOSF_PORT_SHIFT			8
343 
#define   IOSF_BYTE_ENABLES_SHIFT		4
344 
#define   IOSF_BAR_SHIFT			1
345 
#define   IOSF_SB_BUSY				(1<<0)
346 
#define   IOSF_PORT_PUNIT			0x4
347 
#define   IOSF_PORT_NC				0x11
348 
#define   IOSF_PORT_DPIO			0x12
349 
#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
350 
#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
351 
 
352 
#define PUNIT_OPCODE_REG_READ			6
353 
#define PUNIT_OPCODE_REG_WRITE			7
354 
 
355 
#define PUNIT_REG_GPU_LFM			0xd3
356 
#define PUNIT_REG_GPU_FREQ_REQ			0xd4
357 
#define PUNIT_REG_GPU_FREQ_STS			0xd8
358 
#define   GENFREQSTATUS				(1<<0)
359 
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
360 
 
361 
#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
362 
#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
363 
 
364 
#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
365 
#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
366 
#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
367 
#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
368 
#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
369 
#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
370 
#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
371 
#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
372 
#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
373 
#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
374 
 
375 
/*
376 
 * DPIO - a special bus for various display related registers to hide behind
3480 Serge 377 
 *
378 
 * DPIO is VLV only.
4104 Serge 379 
 *
380 
 * Note: digital port B is DDI0, digital pot C is DDI1
3031 serge 381 
 */
4104 Serge 382 
#define DPIO_DEVFN			0
383 
#define DPIO_OPCODE_REG_WRITE		1
384 
#define DPIO_OPCODE_REG_READ		0
385 
 
3480 Serge 386 
#define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
3031 serge 387 
#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
388 
#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
389 
#define  DPIO_SFR_BYPASS		(1<<1)
390 
#define  DPIO_RESET			(1<<0)
2325 Serge 391 
 
4104 Serge 392 
#define _DPIO_TX3_SWING_CTL4_A		0x690
393 
#define _DPIO_TX3_SWING_CTL4_B		0x2a90
394 
#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
395 
					_DPIO_TX3_SWING_CTL4_B)
396 
 
397 
/*
398 
 * Per pipe/PLL DPIO regs
399 
 */
3031 serge 400 
#define _DPIO_DIV_A			0x800c
401 
#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
4104 Serge 402 
#define   DPIO_POST_DIV_DAC		0
403 
#define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
404 
#define   DPIO_POST_DIV_LVDS1		2
405 
#define   DPIO_POST_DIV_LVDS2		3
3031 serge 406 
#define   DPIO_K_SHIFT			(24) /* 4 bits */
407 
#define   DPIO_P1_SHIFT			(21) /* 3 bits */
408 
#define   DPIO_P2_SHIFT			(16) /* 5 bits */
409 
#define   DPIO_N_SHIFT			(12) /* 4 bits */
410 
#define   DPIO_ENABLE_CALIBRATION	(1<<11)
411 
#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
412 
#define   DPIO_M2DIV_MASK		0xff
413 
#define _DPIO_DIV_B			0x802c
414 
#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
415 
 
416 
#define _DPIO_REFSFR_A			0x8014
417 
#define   DPIO_REFSEL_OVERRIDE		27
418 
#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
419 
#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
420 
#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
3243 Serge 421 
#define   DPIO_PLL_REFCLK_SEL_MASK	3
3031 serge 422 
#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
423 
#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
424 
#define _DPIO_REFSFR_B			0x8034
425 
#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
426 
 
427 
#define _DPIO_CORE_CLK_A		0x801c
428 
#define _DPIO_CORE_CLK_B		0x803c
429 
#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
430 
 
4104 Serge 431 
#define _DPIO_IREF_CTL_A		0x8040
432 
#define _DPIO_IREF_CTL_B		0x8060
433 
#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
3031 serge 434 
 
4104 Serge 435 
#define DPIO_IREF_BCAST			0xc044
436 
#define _DPIO_IREF_A			0x8044
437 
#define _DPIO_IREF_B			0x8064
438 
#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
439 
 
440 
#define _DPIO_PLL_CML_A			0x804c
441 
#define _DPIO_PLL_CML_B			0x806c
442 
#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
443 
 
444 
#define _DPIO_LPF_COEFF_A		0x8048
445 
#define _DPIO_LPF_COEFF_B		0x8068
446 
#define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B)
447 
 
448 
#define DPIO_CALIBRATION		0x80ac
449 
 
3031 serge 450 
#define DPIO_FASTCLK_DISABLE		0x8100
451 
 
4104 Serge 452 
/*
453 
 * Per DDI channel DPIO regs
454 
 */
455 
 
456 
#define _DPIO_PCS_TX_0			0x8200
457 
#define _DPIO_PCS_TX_1			0x8400
458 
#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
459 
#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
460 
#define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
461 
 
462 
#define _DPIO_PCS_CLK_0			0x8204
463 
#define _DPIO_PCS_CLK_1			0x8404
464 
#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)
465 
#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
466 
#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
467 
#define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
468 
#define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
469 
 
470 
#define _DPIO_PCS_CTL_OVR1_A		0x8224
471 
#define _DPIO_PCS_CTL_OVR1_B		0x8424
472 
#define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \
473 
				       _DPIO_PCS_CTL_OVR1_B)
474 
 
475 
#define _DPIO_PCS_STAGGER0_A		0x822c
476 
#define _DPIO_PCS_STAGGER0_B		0x842c
477 
#define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \
478 
				      _DPIO_PCS_STAGGER0_B)
479 
 
480 
#define _DPIO_PCS_STAGGER1_A		0x8230
481 
#define _DPIO_PCS_STAGGER1_B		0x8430
482 
#define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \
483 
				      _DPIO_PCS_STAGGER1_B)
484 
 
485 
#define _DPIO_PCS_CLOCKBUF0_A		0x8238
486 
#define _DPIO_PCS_CLOCKBUF0_B		0x8438
487 
#define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \
488 
				       _DPIO_PCS_CLOCKBUF0_B)
489 
 
490 
#define _DPIO_PCS_CLOCKBUF8_A		0x825c
491 
#define _DPIO_PCS_CLOCKBUF8_B		0x845c
492 
#define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \
493 
				       _DPIO_PCS_CLOCKBUF8_B)
494 
 
495 
#define _DPIO_TX_SWING_CTL2_A		0x8288
496 
#define _DPIO_TX_SWING_CTL2_B		0x8488
497 
#define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \
498 
				       _DPIO_TX_SWING_CTL2_B)
499 
 
500 
#define _DPIO_TX_SWING_CTL3_A		0x828c
501 
#define _DPIO_TX_SWING_CTL3_B		0x848c
502 
#define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \
503 
				       _DPIO_TX_SWING_CTL3_B)
504 
 
505 
#define _DPIO_TX_SWING_CTL4_A		0x8290
506 
#define _DPIO_TX_SWING_CTL4_B		0x8490
507 
#define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \
508 
				       _DPIO_TX_SWING_CTL4_B)
509 
 
510 
#define _DPIO_TX_OCALINIT_0		0x8294
511 
#define _DPIO_TX_OCALINIT_1		0x8494
512 
#define   DPIO_TX_OCALINIT_EN		(1<<31)
513 
#define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \
514 
				     _DPIO_TX_OCALINIT_1)
515 
 
516 
#define _DPIO_TX_CTL_0			0x82ac
517 
#define _DPIO_TX_CTL_1			0x84ac
518 
#define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
519 
 
520 
#define _DPIO_TX_LANE_0			0x82b8
521 
#define _DPIO_TX_LANE_1			0x84b8
522 
#define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
523 
 
524 
#define _DPIO_DATA_CHANNEL1		0x8220
525 
#define _DPIO_DATA_CHANNEL2		0x8420
526 
#define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
527 
 
528 
#define _DPIO_PORT0_PCS0		0x0220
529 
#define _DPIO_PORT0_PCS1		0x0420
530 
#define _DPIO_PORT1_PCS2		0x2620
531 
#define _DPIO_PORT1_PCS3		0x2820
532 
#define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2)
533 
#define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3)
3243 Serge 534 
#define DPIO_DATA_CHANNEL1		0x8220
535 
#define DPIO_DATA_CHANNEL2		0x8420
536 
 
2325 Serge 537 
/*
538 
 * Fence registers
539 
 */
540 
#define FENCE_REG_830_0			0x2000
541 
#define FENCE_REG_945_8			0x3000
542 
#define   I830_FENCE_START_MASK		0x07f80000
543 
#define   I830_FENCE_TILING_Y_SHIFT	12
544 
#define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
545 
#define   I830_FENCE_PITCH_SHIFT	4
546 
#define   I830_FENCE_REG_VALID		(1<<0)
547 
#define   I915_FENCE_MAX_PITCH_VAL	4
548 
#define   I830_FENCE_MAX_PITCH_VAL	6
549 
#define   I830_FENCE_MAX_SIZE_VAL	(1<<8)
550 
 
551 
#define   I915_FENCE_START_MASK		0x0ff00000
552 
#define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
553 
 
554 
#define FENCE_REG_965_0			0x03000
555 
#define   I965_FENCE_PITCH_SHIFT	2
556 
#define   I965_FENCE_TILING_Y_SHIFT	1
557 
#define   I965_FENCE_REG_VALID		(1<<0)
558 
#define   I965_FENCE_MAX_PITCH_VAL	0x0400
559 
 
560 
#define FENCE_REG_SANDYBRIDGE_0		0x100000
561 
#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
3746 Serge 562 
#define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
2325 Serge 563 
 
3031 serge 564 
/* control register for cpu gtt access */
565 
#define TILECTL				0x101000
566 
#define   TILECTL_SWZCTL			(1 << 0)
567 
#define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
568 
#define   TILECTL_BACKSNOOP_DIS		(1 << 3)
569 
 
2325 Serge 570 
/*
571 
 * Instruction and interrupt control regs
572 
 */
573 
#define PGTBL_ER	0x02024
574 
#define RENDER_RING_BASE	0x02000
575 
#define BSD_RING_BASE		0x04000
576 
#define GEN6_BSD_RING_BASE	0x12000
4104 Serge 577 
#define VEBOX_RING_BASE		0x1a000
2325 Serge 578 
#define BLT_RING_BASE		0x22000
579 
#define RING_TAIL(base)		((base)+0x30)
580 
#define RING_HEAD(base)		((base)+0x34)
581 
#define RING_START(base)	((base)+0x38)
582 
#define RING_CTL(base)		((base)+0x3c)
583 
#define RING_SYNC_0(base)	((base)+0x40)
584 
#define RING_SYNC_1(base)	((base)+0x44)
4104 Serge 585 
#define RING_SYNC_2(base)	((base)+0x48)
2342 Serge 586 
#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
587 
#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
4104 Serge 588 
#define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
589 
#define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
2342 Serge 590 
#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
4104 Serge 591 
#define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
2342 Serge 592 
#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
593 
#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
4104 Serge 594 
#define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
595 
#define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
596 
#define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
597 
#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
598 
#define GEN6_NOSYNC 0
2325 Serge 599 
#define RING_MAX_IDLE(base)	((base)+0x54)
600 
#define RING_HWS_PGA(base)	((base)+0x80)
601 
#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
3031 serge 602 
#define ARB_MODE		0x04030
603 
#define   ARB_MODE_SWIZZLE_SNB	(1<<4)
604 
#define   ARB_MODE_SWIZZLE_IVB	(1<<5)
2325 Serge 605 
#define RENDER_HWS_PGA_GEN7	(0x04080)
3031 serge 606 
#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
4280 Serge 607 
#define   RING_FAULT_GTTSEL_MASK (1<<11)
608 
#define   RING_FAULT_SRCID(x)	((x >> 3) & 0xff)
609 
#define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
610 
#define   RING_FAULT_VALID	(1<<0)
3031 serge 611 
#define DONE_REG		0x40b0
2325 Serge 612 
#define BSD_HWS_PGA_GEN7	(0x04180)
613 
#define BLT_HWS_PGA_GEN7	(0x04280)
4104 Serge 614 
#define VEBOX_HWS_PGA_GEN7	(0x04380)
2325 Serge 615 
#define RING_ACTHD(base)	((base)+0x74)
616 
#define RING_NOPID(base)	((base)+0x94)
617 
#define RING_IMR(base)		((base)+0xa8)
3031 serge 618 
#define RING_TIMESTAMP(base)	((base)+0x358)
2325 Serge 619 
#define   TAIL_ADDR		0x001FFFF8
620 
#define   HEAD_WRAP_COUNT	0xFFE00000
621 
#define   HEAD_WRAP_ONE		0x00200000
622 
#define   HEAD_ADDR		0x001FFFFC
623 
#define   RING_NR_PAGES		0x001FF000
624 
#define   RING_REPORT_MASK	0x00000006
625 
#define   RING_REPORT_64K	0x00000002
626 
#define   RING_REPORT_128K	0x00000004
627 
#define   RING_NO_REPORT	0x00000000
628 
#define   RING_VALID_MASK	0x00000001
629 
#define   RING_VALID		0x00000001
630 
#define   RING_INVALID		0x00000000
631 
#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
632 
#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
633 
#define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
634 
#if 0
635 
#define PRB0_TAIL	0x02030
636 
#define PRB0_HEAD	0x02034
637 
#define PRB0_START	0x02038
638 
#define PRB0_CTL	0x0203c
639 
#define PRB1_TAIL	0x02040 /* 915+ only */
640 
#define PRB1_HEAD	0x02044 /* 915+ only */
641 
#define PRB1_START	0x02048 /* 915+ only */
642 
#define PRB1_CTL	0x0204c /* 915+ only */
643 
#endif
644 
#define IPEIR_I965	0x02064
645 
#define IPEHR_I965	0x02068
646 
#define INSTDONE_I965	0x0206c
3031 serge 647 
#define GEN7_INSTDONE_1		0x0206c
648 
#define GEN7_SC_INSTDONE	0x07100
649 
#define GEN7_SAMPLER_INSTDONE	0x0e160
650 
#define GEN7_ROW_INSTDONE	0x0e164
651 
#define I915_NUM_INSTDONE_REG	4
652 
#define RING_IPEIR(base)	((base)+0x64)
653 
#define RING_IPEHR(base)	((base)+0x68)
654 
#define RING_INSTDONE(base)	((base)+0x6c)
655 
#define RING_INSTPS(base)	((base)+0x70)
656 
#define RING_DMA_FADD(base)	((base)+0x78)
657 
#define RING_INSTPM(base)	((base)+0xc0)
2325 Serge 658 
#define INSTPS		0x02070 /* 965+ only */
659 
#define INSTDONE1	0x0207c /* 965+ only */
660 
#define ACTHD_I965	0x02074
661 
#define HWS_PGA		0x02080
662 
#define HWS_ADDRESS_MASK	0xfffff000
663 
#define HWS_START_ADDRESS_SHIFT	4
664 
#define PWRCTXA		0x2088 /* 965GM+ only */
665 
#define   PWRCTX_EN	(1<<0)
666 
#define IPEIR		0x02088
667 
#define IPEHR		0x0208c
668 
#define INSTDONE	0x02090
669 
#define NOPID		0x02094
670 
#define HWSTAM		0x02098
3031 serge 671 
#define DMA_FADD_I8XX	0x020d0
2325 Serge 672 
 
673 
#define ERROR_GEN6	0x040a0
3031 serge 674 
#define GEN7_ERR_INT	0x44040
4104 Serge 675 
#define   ERR_INT_POISON		(1<<31)
3031 serge 676 
#define   ERR_INT_MMIO_UNCLAIMED (1<<13)
4104 Serge 677 
#define   ERR_INT_FIFO_UNDERRUN_C	(1<<6)
678 
#define   ERR_INT_FIFO_UNDERRUN_B	(1<<3)
679 
#define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
680 
#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))
2325 Serge 681 
 
3746 Serge 682 
#define FPGA_DBG		0x42300
683 
#define   FPGA_DBG_RM_NOCLAIM	(1<<31)
684 
 
3243 Serge 685 
#define DERRMR		0x44050
4104 Serge 686 
#define   DERRMR_PIPEA_SCANLINE		(1<<0)
687 
#define   DERRMR_PIPEA_PRI_FLIP_DONE	(1<<1)
688 
#define   DERRMR_PIPEA_SPR_FLIP_DONE	(1<<2)
689 
#define   DERRMR_PIPEA_VBLANK		(1<<3)
690 
#define   DERRMR_PIPEA_HBLANK		(1<<5)
691 
#define   DERRMR_PIPEB_SCANLINE 	(1<<8)
692 
#define   DERRMR_PIPEB_PRI_FLIP_DONE	(1<<9)
693 
#define   DERRMR_PIPEB_SPR_FLIP_DONE	(1<<10)
694 
#define   DERRMR_PIPEB_VBLANK		(1<<11)
695 
#define   DERRMR_PIPEB_HBLANK		(1<<13)
696 
/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
697 
#define   DERRMR_PIPEC_SCANLINE		(1<<14)
698 
#define   DERRMR_PIPEC_PRI_FLIP_DONE	(1<<15)
699 
#define   DERRMR_PIPEC_SPR_FLIP_DONE	(1<<20)
700 
#define   DERRMR_PIPEC_VBLANK		(1<<21)
701 
#define   DERRMR_PIPEC_HBLANK		(1<<22)
3243 Serge 702 
 
4104 Serge 703 
 
2325 Serge 704 
/* GM45+ chicken bits -- debug workaround bits that may be required
705 
 * for various sorts of correct behavior.  The top 16 bits of each are
706 
 * the enables for writing to the corresponding low bit.
707 
 */
708 
#define _3D_CHICKEN	0x02084
3243 Serge 709 
#define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
2325 Serge 710 
#define _3D_CHICKEN2	0x0208c
711 
/* Disables pipelining of read flushes past the SF-WIZ interface.
712 
 * Required on all Ironlake steppings according to the B-Spec, but the
713 
 * particular danger of not doing so is not specified.
714 
 */
715 
# define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
716 
#define _3D_CHICKEN3	0x02090
3243 Serge 717 
#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
3031 serge 718 
#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
2325 Serge 719 
 
720 
#define MI_MODE		0x0209c
721 
# define VS_TIMER_DISPATCH				(1 << 6)
3031 serge 722 
# define MI_FLUSH_ENABLE				(1 << 12)
3243 Serge 723 
# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
2325 Serge 724 
 
3031 serge 725 
#define GEN6_GT_MODE	0x20d0
726 
#define   GEN6_GT_MODE_HI	(1 << 9)
3243 Serge 727 
#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
3031 serge 728 
 
2325 Serge 729 
#define GFX_MODE	0x02520
730 
#define GFX_MODE_GEN7	0x0229c
3031 serge 731 
#define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
2325 Serge 732 
#define   GFX_RUN_LIST_ENABLE		(1<<15)
733 
#define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)
734 
#define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
735 
#define   GFX_REPLAY_MODE		(1<<11)
736 
#define   GFX_PSMI_GRANULARITY		(1<<10)
737 
#define   GFX_PPGTT_ENABLE		(1<<9)
738 
 
3031 serge 739 
#define VLV_DISPLAY_BASE 0x180000
2325 Serge 740 
 
741 
#define SCPD0		0x0209c /* 915+ only */
742 
#define IER		0x020a0
743 
#define IIR		0x020a4
744 
#define IMR		0x020a8
745 
#define ISR		0x020ac
3480 Serge 746 
#define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
3243 Serge 747 
#define   GCFG_DIS		(1<<8)
3480 Serge 748 
#define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
749 
#define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
750 
#define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
751 
#define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
752 
#define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
4104 Serge 753 
#define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)
3746 Serge 754 
#define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
2325 Serge 755 
#define EIR		0x020b0
756 
#define EMR		0x020b4
757 
#define ESR		0x020b8
758 
#define   GM45_ERROR_PAGE_TABLE				(1<<5)
759 
#define   GM45_ERROR_MEM_PRIV				(1<<4)
760 
#define   I915_ERROR_PAGE_TABLE				(1<<4)
761 
#define   GM45_ERROR_CP_PRIV				(1<<3)
762 
#define   I915_ERROR_MEMORY_REFRESH			(1<<1)
763 
#define   I915_ERROR_INSTRUCTION			(1<<0)
764 
#define INSTPM	        0x020c0
765 
#define   INSTPM_SELF_EN (1<<12) /* 915GM only */
766 
#define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
767 
					will not assert AGPBUSY# and will only
768 
					be delivered when out of C3. */
2342 Serge 769 
#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
4104 Serge 770 
#define   INSTPM_TLB_INVALIDATE	(1<<9)
771 
#define   INSTPM_SYNC_FLUSH	(1<<5)
2325 Serge 772 
#define ACTHD	        0x020c8
773 
#define FW_BLC		0x020d8
774 
#define FW_BLC2		0x020dc
775 
#define FW_BLC_SELF	0x020e0 /* 915+ only */
776 
#define   FW_BLC_SELF_EN_MASK      (1<<31)
777 
#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
778 
#define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
779 
#define MM_BURST_LENGTH     0x00700000
780 
#define MM_FIFO_WATERMARK   0x0001F000
781 
#define LM_BURST_LENGTH     0x00000700
782 
#define LM_FIFO_WATERMARK   0x0000001F
783 
#define MI_ARB_STATE	0x020e4 /* 915+ only */
784 
 
785 
/* Make render/texture TLB fetches lower priorty than associated data
786 
 *   fetches. This is not turned on by default
787 
 */
788 
#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
789 
 
790 
/* Isoch request wait on GTT enable (Display A/B/C streams).
791 
 * Make isoch requests stall on the TLB update. May cause
792 
 * display underruns (test mode only)
793 
 */
794 
#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
795 
 
796 
/* Block grant count for isoch requests when block count is
797 
 * set to a finite value.
798 
 */
799 
#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
800 
#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
801 
#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
802 
#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
803 
#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
804 
 
805 
/* Enable render writes to complete in C2/C3/C4 power states.
806 
 * If this isn't enabled, render writes are prevented in low
807 
 * power states. That seems bad to me.
808 
 */
809 
#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
810 
 
811 
/* This acknowledges an async flip immediately instead
812 
 * of waiting for 2TLB fetches.
813 
 */
814 
#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
815 
 
816 
/* Enables non-sequential data reads through arbiter
817 
 */
818 
#define   MI_ARB_DUAL_DATA_PHASE_DISABLE       	(1 << 9)
819 
 
820 
/* Disable FSB snooping of cacheable write cycles from binner/render
821 
 * command stream
822 
 */
823 
#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
824 
 
825 
/* Arbiter time slice for non-isoch streams */
826 
#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
827 
#define   MI_ARB_TIME_SLICE_1			(0 << 5)
828 
#define   MI_ARB_TIME_SLICE_2			(1 << 5)
829 
#define   MI_ARB_TIME_SLICE_4			(2 << 5)
830 
#define   MI_ARB_TIME_SLICE_6			(3 << 5)
831 
#define   MI_ARB_TIME_SLICE_8			(4 << 5)
832 
#define   MI_ARB_TIME_SLICE_10			(5 << 5)
833 
#define   MI_ARB_TIME_SLICE_14			(6 << 5)
834 
#define   MI_ARB_TIME_SLICE_16			(7 << 5)
835 
 
836 
/* Low priority grace period page size */
837 
#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
838 
#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
839 
 
840 
/* Disable display A/B trickle feed */
841 
#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
842 
 
843 
/* Set display plane priority */
844 
#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
845 
#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
846 
 
847 
#define CACHE_MODE_0	0x02120 /* 915+ only */
3243 Serge 848 
#define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
2325 Serge 849 
#define   CM0_IZ_OPT_DISABLE      (1<<6)
850 
#define   CM0_ZR_OPT_DISABLE      (1<<5)
3031 serge 851 
#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
2325 Serge 852 
#define   CM0_DEPTH_EVICT_DISABLE (1<<4)
853 
#define   CM0_COLOR_EVICT_DISABLE (1<<3)
854 
#define   CM0_DEPTH_WRITE_DISABLE (1<<1)
855 
#define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
856 
#define BB_ADDR		0x02140 /* 8 bytes */
857 
#define GFX_FLSH_CNTL	0x02170 /* 915+ only */
3243 Serge 858 
#define GFX_FLSH_CNTL_GEN6	0x101008
859 
#define   GFX_FLSH_CNTL_EN	(1<<0)
2325 Serge 860 
#define ECOSKPD		0x021d0
861 
#define   ECO_GATING_CX_ONLY	(1<<3)
862 
#define   ECO_FLIP_DONE		(1<<0)
863 
 
3031 serge 864 
#define CACHE_MODE_1		0x7004 /* IVB+ */
865 
#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
866 
 
2325 Serge 867 
#define GEN6_BLITTER_ECOSKPD	0x221d0
868 
#define   GEN6_BLITTER_LOCK_SHIFT			16
869 
#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
870 
 
871 
#define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
3031 serge 872 
#define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
873 
#define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
874 
#define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
875 
#define   GEN6_BSD_GO_INDICATOR		(1 << 4)
2325 Serge 876 
 
4104 Serge 877 
/* On modern GEN architectures interrupt control consists of two sets
878 
 * of registers. The first set pertains to the ring generating the
879 
 * interrupt. The second control is for the functional block generating the
880 
 * interrupt. These are PM, GT, DE, etc.
881 
 *
882 
 * Luckily *knocks on wood* all the ring interrupt bits match up with the
883 
 * GT interrupt bits, so we don't need to duplicate the defines.
884 
 *
885 
 * These defines should cover us well from SNB->HSW with minor exceptions
886 
 * it can also work on ILK.
887 
 */
888 
#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
889 
#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
890 
#define GT_BLT_USER_INTERRUPT			(1 << 22)
891 
#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
892 
#define GT_BSD_USER_INTERRUPT			(1 << 12)
893 
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
894 
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
895 
#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
896 
#define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
897 
#define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
898 
#define GT_RENDER_USER_INTERRUPT		(1 <<  0)
2325 Serge 899 
 
4104 Serge 900 
#define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
901 
#define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */
902 
 
903 
/* These are all the "old" interrupts */
904 
#define ILK_BSD_USER_INTERRUPT				(1<<5)
905 
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
906 
#define I915_DISPLAY_PORT_INTERRUPT			(1<<17)
907 
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
908 
#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
909 
#define I915_HWB_OOM_INTERRUPT				(1<<13)
910 
#define I915_SYNC_STATUS_INTERRUPT			(1<<12)
911 
#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
912 
#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
913 
#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
914 
#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
915 
#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
916 
#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
917 
#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
918 
#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
919 
#define I915_DEBUG_INTERRUPT				(1<<2)
920 
#define I915_USER_INTERRUPT				(1<<1)
921 
#define I915_ASLE_INTERRUPT				(1<<0)
922 
#define I915_BSD_USER_INTERRUPT				(1 << 25)
923 
 
2325 Serge 924 
#define GEN6_BSD_RNCID			0x12198
925 
 
3031 serge 926 
#define GEN7_FF_THREAD_MODE		0x20a0
927 
#define   GEN7_FF_SCHED_MASK		0x0077070
928 
#define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
929 
#define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
930 
#define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
931 
#define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */
3480 Serge 932 
#define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
3031 serge 933 
#define   GEN7_FF_VS_SCHED_HS1		(0x5<<12)
934 
#define   GEN7_FF_VS_SCHED_HS0		(0x3<<12)
935 
#define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1<<12) /* Default */
936 
#define   GEN7_FF_VS_SCHED_HW		(0x0<<12)
937 
#define   GEN7_FF_DS_SCHED_HS1		(0x5<<4)
938 
#define   GEN7_FF_DS_SCHED_HS0		(0x3<<4)
939 
#define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1<<4)  /* Default */
940 
#define   GEN7_FF_DS_SCHED_HW		(0x0<<4)
941 
 
2325 Serge 942 
/*
943 
 * Framebuffer compression (915+ only)
944 
 */
945 
 
946 
#define FBC_CFB_BASE		0x03200 /* 4k page aligned */
947 
#define FBC_LL_BASE		0x03204 /* 4k page aligned */
948 
#define FBC_CONTROL		0x03208
949 
#define   FBC_CTL_EN		(1<<31)
950 
#define   FBC_CTL_PERIODIC	(1<<30)
951 
#define   FBC_CTL_INTERVAL_SHIFT (16)
952 
#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
953 
#define   FBC_CTL_C3_IDLE	(1<<13)
954 
#define   FBC_CTL_STRIDE_SHIFT	(5)
955 
#define   FBC_CTL_FENCENO	(1<<0)
956 
#define FBC_COMMAND		0x0320c
957 
#define   FBC_CMD_COMPRESS	(1<<0)
958 
#define FBC_STATUS		0x03210
959 
#define   FBC_STAT_COMPRESSING	(1<<31)
960 
#define   FBC_STAT_COMPRESSED	(1<<30)
961 
#define   FBC_STAT_MODIFIED	(1<<29)
962 
#define   FBC_STAT_CURRENT_LINE	(1<<0)
963 
#define FBC_CONTROL2		0x03214
964 
#define   FBC_CTL_FENCE_DBL	(0<<4)
965 
#define   FBC_CTL_IDLE_IMM	(0<<2)
966 
#define   FBC_CTL_IDLE_FULL	(1<<2)
967 
#define   FBC_CTL_IDLE_LINE	(2<<2)
968 
#define   FBC_CTL_IDLE_DEBUG	(3<<2)
969 
#define   FBC_CTL_CPU_FENCE	(1<<1)
970 
#define   FBC_CTL_PLANEA	(0<<0)
971 
#define   FBC_CTL_PLANEB	(1<<0)
972 
#define FBC_FENCE_OFF		0x0321b
973 
#define FBC_TAG			0x03300
974 
 
975 
#define FBC_LL_SIZE		(1536)
976 
 
977 
/* Framebuffer compression for GM45+ */
978 
#define DPFC_CB_BASE		0x3200
979 
#define DPFC_CONTROL		0x3208
980 
#define   DPFC_CTL_EN		(1<<31)
981 
#define   DPFC_CTL_PLANEA	(0<<30)
982 
#define   DPFC_CTL_PLANEB	(1<<30)
4104 Serge 983 
#define   IVB_DPFC_CTL_PLANE_SHIFT	(29)
2325 Serge 984 
#define   DPFC_CTL_FENCE_EN	(1<<29)
4104 Serge 985 
#define   IVB_DPFC_CTL_FENCE_EN	(1<<28)
2325 Serge 986 
#define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
987 
#define   DPFC_SR_EN		(1<<10)
988 
#define   DPFC_CTL_LIMIT_1X	(0<<6)
989 
#define   DPFC_CTL_LIMIT_2X	(1<<6)
990 
#define   DPFC_CTL_LIMIT_4X	(2<<6)
991 
#define DPFC_RECOMP_CTL		0x320c
992 
#define   DPFC_RECOMP_STALL_EN	(1<<27)
993 
#define   DPFC_RECOMP_STALL_WM_SHIFT (16)
994 
#define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
995 
#define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
996 
#define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
997 
#define DPFC_STATUS		0x3210
998 
#define   DPFC_INVAL_SEG_SHIFT  (16)
999 
#define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
1000 
#define   DPFC_COMP_SEG_SHIFT	(0)
1001 
#define   DPFC_COMP_SEG_MASK	(0x000003ff)
1002 
#define DPFC_STATUS2		0x3214
1003 
#define DPFC_FENCE_YOFF		0x3218
1004 
#define DPFC_CHICKEN		0x3224
1005 
#define   DPFC_HT_MODIFY	(1<<31)
1006 
 
1007 
/* Framebuffer compression for Ironlake */
1008 
#define ILK_DPFC_CB_BASE	0x43200
1009 
#define ILK_DPFC_CONTROL	0x43208
1010 
/* The bit 28-8 is reserved */
1011 
#define   DPFC_RESERVED		(0x1FFFFF00)
1012 
#define ILK_DPFC_RECOMP_CTL	0x4320c
1013 
#define ILK_DPFC_STATUS		0x43210
1014 
#define ILK_DPFC_FENCE_YOFF	0x43218
1015 
#define ILK_DPFC_CHICKEN	0x43224
1016 
#define ILK_FBC_RT_BASE		0x2128
1017 
#define   ILK_FBC_RT_VALID	(1<<0)
4104 Serge 1018 
#define   SNB_FBC_FRONT_BUFFER	(1<<1)
2325 Serge 1019 
 
1020 
#define ILK_DISPLAY_CHICKEN1	0x42000
1021 
#define   ILK_FBCQ_DIS		(1<<22)
1022 
#define   ILK_PABSTRETCH_DIS 	(1<<21)
1023 
 
1024 
 
1025 
/*
1026 
 * Framebuffer compression for Sandybridge
1027 
 *
1028 
 * The following two registers are of type GTTMMADR
1029 
 */
1030 
#define SNB_DPFC_CTL_SA		0x100100
1031 
#define   SNB_CPU_FENCE_ENABLE	(1<<29)
1032 
#define DPFC_CPU_FENCE_OFFSET	0x100104
1033 
 
4104 Serge 1034 
/* Framebuffer compression for Ivybridge */
1035 
#define IVB_FBC_RT_BASE			0x7020
2325 Serge 1036 
 
4104 Serge 1037 
#define IPS_CTL		0x43408
1038 
#define   IPS_ENABLE	(1 << 31)
1039 
 
1040 
#define MSG_FBC_REND_STATE	0x50380
1041 
#define   FBC_REND_NUKE		(1<<2)
1042 
#define   FBC_REND_CACHE_CLEAN	(1<<1)
1043 
 
1044 
#define _HSW_PIPE_SLICE_CHICKEN_1_A	0x420B0
1045 
#define _HSW_PIPE_SLICE_CHICKEN_1_B	0x420B4
1046 
#define   HSW_BYPASS_FBC_QUEUE		(1<<22)
1047 
#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
1048 
					     _HSW_PIPE_SLICE_CHICKEN_1_A, + \
1049 
					     _HSW_PIPE_SLICE_CHICKEN_1_B)
1050 
 
1051 
#define HSW_CLKGATE_DISABLE_PART_1	0x46500
1052 
#define   HSW_DPFC_GATING_DISABLE	(1<<23)
1053 
 
2325 Serge 1054 
/*
1055 
 * GPIO regs
1056 
 */
1057 
#define GPIOA			0x5010
1058 
#define GPIOB			0x5014
1059 
#define GPIOC			0x5018
1060 
#define GPIOD			0x501c
1061 
#define GPIOE			0x5020
1062 
#define GPIOF			0x5024
1063 
#define GPIOG			0x5028
1064 
#define GPIOH			0x502c
1065 
# define GPIO_CLOCK_DIR_MASK		(1 << 0)
1066 
# define GPIO_CLOCK_DIR_IN		(0 << 1)
1067 
# define GPIO_CLOCK_DIR_OUT		(1 << 1)
1068 
# define GPIO_CLOCK_VAL_MASK		(1 << 2)
1069 
# define GPIO_CLOCK_VAL_OUT		(1 << 3)
1070 
# define GPIO_CLOCK_VAL_IN		(1 << 4)
1071 
# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
1072 
# define GPIO_DATA_DIR_MASK		(1 << 8)
1073 
# define GPIO_DATA_DIR_IN		(0 << 9)
1074 
# define GPIO_DATA_DIR_OUT		(1 << 9)
1075 
# define GPIO_DATA_VAL_MASK		(1 << 10)
1076 
# define GPIO_DATA_VAL_OUT		(1 << 11)
1077 
# define GPIO_DATA_VAL_IN		(1 << 12)
1078 
# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
1079 
 
1080 
#define GMBUS0			0x5100 /* clock/port select */
1081 
#define   GMBUS_RATE_100KHZ	(0<<8)
1082 
#define   GMBUS_RATE_50KHZ	(1<<8)
1083 
#define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
1084 
#define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
1085 
#define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
1086 
#define   GMBUS_PORT_DISABLED	0
1087 
#define   GMBUS_PORT_SSC	1
1088 
#define   GMBUS_PORT_VGADDC	2
1089 
#define   GMBUS_PORT_PANEL	3
1090 
#define   GMBUS_PORT_DPC	4 /* HDMIC */
1091 
#define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
3031 serge 1092 
#define   GMBUS_PORT_DPD	6 /* HDMID */
1093 
#define   GMBUS_PORT_RESERVED	7 /* 7 reserved */
1094 
#define   GMBUS_NUM_PORTS	(GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
2325 Serge 1095 
#define GMBUS1			0x5104 /* command/status */
1096 
#define   GMBUS_SW_CLR_INT	(1<<31)
1097 
#define   GMBUS_SW_RDY		(1<<30)
1098 
#define   GMBUS_ENT		(1<<29) /* enable timeout */
1099 
#define   GMBUS_CYCLE_NONE	(0<<25)
1100 
#define   GMBUS_CYCLE_WAIT	(1<<25)
1101 
#define   GMBUS_CYCLE_INDEX	(2<<25)
1102 
#define   GMBUS_CYCLE_STOP	(4<<25)
1103 
#define   GMBUS_BYTE_COUNT_SHIFT 16
1104 
#define   GMBUS_SLAVE_INDEX_SHIFT 8
1105 
#define   GMBUS_SLAVE_ADDR_SHIFT 1
1106 
#define   GMBUS_SLAVE_READ	(1<<0)
1107 
#define   GMBUS_SLAVE_WRITE	(0<<0)
1108 
#define GMBUS2			0x5108 /* status */
1109 
#define   GMBUS_INUSE		(1<<15)
1110 
#define   GMBUS_HW_WAIT_PHASE	(1<<14)
1111 
#define   GMBUS_STALL_TIMEOUT	(1<<13)
1112 
#define   GMBUS_INT		(1<<12)
1113 
#define   GMBUS_HW_RDY		(1<<11)
1114 
#define   GMBUS_SATOER		(1<<10)
1115 
#define   GMBUS_ACTIVE		(1<<9)
1116 
#define GMBUS3			0x510c /* data buffer bytes 3-0 */
1117 
#define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
1118 
#define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1119 
#define   GMBUS_NAK_EN		(1<<3)
1120 
#define   GMBUS_IDLE_EN		(1<<2)
1121 
#define   GMBUS_HW_WAIT_EN	(1<<1)
1122 
#define   GMBUS_HW_RDY_EN	(1<<0)
1123 
#define GMBUS5			0x5120 /* byte index */
1124 
#define   GMBUS_2BYTE_INDEX_EN	(1<<31)
1125 
 
1126 
/*
1127 
 * Clock control & power management
1128 
 */
1129 
 
1130 
#define VGA0	0x6000
1131 
#define VGA1	0x6004
1132 
#define VGA_PD	0x6010
1133 
#define   VGA0_PD_P2_DIV_4	(1 << 7)
1134 
#define   VGA0_PD_P1_DIV_2	(1 << 5)
1135 
#define   VGA0_PD_P1_SHIFT	0
1136 
#define   VGA0_PD_P1_MASK	(0x1f << 0)
1137 
#define   VGA1_PD_P2_DIV_4	(1 << 15)
1138 
#define   VGA1_PD_P1_DIV_2	(1 << 13)
1139 
#define   VGA1_PD_P1_SHIFT	8
1140 
#define   VGA1_PD_P1_MASK	(0x1f << 8)
3480 Serge 1141 
#define _DPLL_A	(dev_priv->info->display_mmio_offset + 0x6014)
1142 
#define _DPLL_B	(dev_priv->info->display_mmio_offset + 0x6018)
2325 Serge 1143 
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
1144 
#define   DPLL_VCO_ENABLE		(1 << 31)
4104 Serge 1145 
#define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
1146 
#define   DPLL_DVO_2X_MODE		(1 << 30)
3031 serge 1147 
#define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
2325 Serge 1148 
#define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
3031 serge 1149 
#define   DPLL_REFA_CLK_ENABLE_VLV	(1 << 29)
2325 Serge 1150 
#define   DPLL_VGA_MODE_DIS		(1 << 28)
1151 
#define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
1152 
#define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
1153 
#define   DPLL_MODE_MASK		(3 << 26)
1154 
#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1155 
#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1156 
#define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
1157 
#define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
1158 
#define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
1159 
#define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
1160 
#define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
3031 serge 1161 
#define   DPLL_LOCK_VLV			(1<<15)
4104 Serge 1162 
#define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)
3031 serge 1163 
#define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
4104 Serge 1164 
#define   DPLL_PORTC_READY_MASK		(0xf << 4)
1165 
#define   DPLL_PORTB_READY_MASK		(0xf)
2325 Serge 1166 
 
1167 
#define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
1168 
/*
1169 
 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1170 
 * this field (only one bit may be set).
1171 
 */
1172 
#define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
1173 
#define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
1174 
#define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1175 
/* i830, required in DVO non-gang */
1176 
#define   PLL_P2_DIVIDE_BY_4		(1 << 23)
1177 
#define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
1178 
#define   PLL_REF_INPUT_DREFCLK		(0 << 13)
1179 
#define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
1180 
#define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
1181 
#define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1182 
#define   PLL_REF_INPUT_MASK		(3 << 13)
1183 
#define   PLL_LOAD_PULSE_PHASE_SHIFT		9
1184 
/* Ironlake */
1185 
# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
1186 
# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
1187 
# define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
1188 
# define DPLL_FPA1_P1_POST_DIV_SHIFT            0
1189 
# define DPLL_FPA1_P1_POST_DIV_MASK             0xff
1190 
 
1191 
/*
1192 
 * Parallel to Serial Load Pulse phase selection.
1193 
 * Selects the phase for the 10X DPLL clock for the PCIe
1194 
 * digital display port. The range is 4 to 13; 10 or more
1195 
 * is just a flip delay. The default is 6
1196 
 */
1197 
#define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1198 
#define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
1199 
/*
1200 
 * SDVO multiplier for 945G/GM. Not used on 965.
1201 
 */
1202 
#define   SDVO_MULTIPLIER_MASK			0x000000ff
1203 
#define   SDVO_MULTIPLIER_SHIFT_HIRES		4
1204 
#define   SDVO_MULTIPLIER_SHIFT_VGA		0
3480 Serge 1205 
#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
2325 Serge 1206 
/*
1207 
 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1208 
 *
1209 
 * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
1210 
 */
1211 
#define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
1212 
#define   DPLL_MD_UDI_DIVIDER_SHIFT		24
1213 
/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1214 
#define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
1215 
#define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
1216 
/*
1217 
 * SDVO/UDI pixel multiplier.
1218 
 *
1219 
 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1220 
 * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
1221 
 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1222 
 * dummy bytes in the datastream at an increased clock rate, with both sides of
1223 
 * the link knowing how many bytes are fill.
1224 
 *
1225 
 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1226 
 * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
1227 
 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1228 
 * through an SDVO command.
1229 
 *
1230 
 * This register field has values of multiplication factor minus 1, with
1231 
 * a maximum multiplier of 5 for SDVO.
1232 
 */
1233 
#define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
1234 
#define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
1235 
/*
1236 
 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1237 
 * This best be set to the default value (3) or the CRT won't work. No,
1238 
 * I don't entirely understand what this does...
1239 
 */
1240 
#define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
1241 
#define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
3480 Serge 1242 
#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
2325 Serge 1243 
#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
3031 serge 1244 
 
2325 Serge 1245 
#define _FPA0	0x06040
1246 
#define _FPA1	0x06044
1247 
#define _FPB0	0x06048
1248 
#define _FPB1	0x0604c
1249 
#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1250 
#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1251 
#define   FP_N_DIV_MASK		0x003f0000
1252 
#define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
1253 
#define   FP_N_DIV_SHIFT		16
1254 
#define   FP_M1_DIV_MASK	0x00003f00
1255 
#define   FP_M1_DIV_SHIFT		 8
1256 
#define   FP_M2_DIV_MASK	0x0000003f
1257 
#define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
1258 
#define   FP_M2_DIV_SHIFT		 0
1259 
#define DPLL_TEST	0x606c
1260 
#define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
1261 
#define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
1262 
#define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
1263 
#define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
1264 
#define   DPLLB_TEST_N_BYPASS		(1 << 19)
1265 
#define   DPLLB_TEST_M_BYPASS		(1 << 18)
1266 
#define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
1267 
#define   DPLLA_TEST_N_BYPASS		(1 << 3)
1268 
#define   DPLLA_TEST_M_BYPASS		(1 << 2)
1269 
#define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
1270 
#define D_STATE		0x6104
1271 
#define  DSTATE_GFX_RESET_I830			(1<<6)
1272 
#define  DSTATE_PLL_D3_OFF			(1<<3)
1273 
#define  DSTATE_GFX_CLOCK_GATING		(1<<1)
1274 
#define  DSTATE_DOT_CLOCK_GATING		(1<<0)
4104 Serge 1275 
#define DSPCLK_GATE_D	(dev_priv->info->display_mmio_offset + 0x6200)
2325 Serge 1276 
# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
1277 
# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
1278 
# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
1279 
# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
1280 
# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
1281 
# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
1282 
# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
1283 
# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
1284 
# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
1285 
# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
1286 
# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
1287 
# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
1288 
# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
1289 
# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
1290 
# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
1291 
# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
1292 
# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
1293 
# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
1294 
# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
1295 
# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
1296 
# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
1297 
# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
1298 
# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
1299 
# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
1300 
# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
1301 
# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
1302 
# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
1303 
# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
1304 
/**
1305 
 * This bit must be set on the 830 to prevent hangs when turning off the
1306 
 * overlay scaler.
1307 
 */
1308 
# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
1309 
# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
1310 
# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
1311 
# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
1312 
# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
1313 
 
1314 
#define RENCLK_GATE_D1		0x6204
1315 
# define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
1316 
# define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
1317 
# define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
1318 
# define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
1319 
# define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
1320 
# define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
1321 
# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
1322 
# define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
1323 
# define MAG_CLOCK_GATE_DISABLE			(1 << 5)
1324 
/** This bit must be unset on 855,865 */
1325 
# define MECI_CLOCK_GATE_DISABLE		(1 << 4)
1326 
# define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
1327 
# define MEC_CLOCK_GATE_DISABLE			(1 << 2)
1328 
# define MECO_CLOCK_GATE_DISABLE		(1 << 1)
1329 
/** This bit must be set on 855,865. */
1330 
# define SV_CLOCK_GATE_DISABLE			(1 << 0)
1331 
# define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
1332 
# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
1333 
# define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
1334 
# define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
1335 
# define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
1336 
# define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
1337 
# define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
1338 
# define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
1339 
# define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
1340 
# define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
1341 
# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
1342 
# define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
1343 
# define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
1344 
# define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
1345 
# define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
1346 
# define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
1347 
# define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
1348 
 
1349 
# define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
1350 
/** This bit must always be set on 965G/965GM */
1351 
# define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
1352 
# define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
1353 
# define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
1354 
# define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
1355 
# define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
1356 
# define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
1357 
/** This bit must always be set on 965G */
1358 
# define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
1359 
# define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
1360 
# define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
1361 
# define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
1362 
# define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
1363 
# define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
1364 
# define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
1365 
# define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
1366 
# define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
1367 
# define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
1368 
# define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
1369 
# define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
1370 
# define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
1371 
# define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
1372 
# define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
1373 
# define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
1374 
# define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
1375 
# define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
1376 
# define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
1377 
 
1378 
#define RENCLK_GATE_D2		0x6208
1379 
#define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
1380 
#define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
1381 
#define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
1382 
#define RAMCLK_GATE_D		0x6210		/* CRL only */
1383 
#define DEUC			0x6214          /* CRL only */
1384 
 
3480 Serge 1385 
#define FW_BLC_SELF_VLV		(VLV_DISPLAY_BASE + 0x6500)
3031 serge 1386 
#define  FW_CSPWRDWNEN		(1<<15)
1387 
 
4104 Serge 1388 
#define MI_ARB_VLV		(VLV_DISPLAY_BASE + 0x6504)
1389 
 
2325 Serge 1390 
/*
1391 
 * Palette regs
1392 
 */
1393 
 
3480 Serge 1394 
#define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
1395 
#define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
2325 Serge 1396 
#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1397 
 
1398 
/* MCH MMIO space */
1399 
 
1400 
/*
1401 
 * MCHBAR mirror.
1402 
 *
1403 
 * This mirrors the MCHBAR MMIO space whose location is determined by
1404 
 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1405 
 * every way.  It is not accessible from the CP register read instructions.
1406 
 *
1407 
 */
1408 
#define MCHBAR_MIRROR_BASE	0x10000
1409 
 
1410 
#define MCHBAR_MIRROR_BASE_SNB	0x140000
1411 
 
3746 Serge 1412 
/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
1413 
#define DCLK 0x5e04
1414 
 
2325 Serge 1415 
/** 915-945 and GM965 MCH register controlling DRAM channel access */
1416 
#define DCC			0x10200
1417 
#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
1418 
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
1419 
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
1420 
#define DCC_ADDRESSING_MODE_MASK			(3 << 0)
1421 
#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
1422 
#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
1423 
 
1424 
/** Pineview MCH register contains DDR3 setting */
1425 
#define CSHRDDR3CTL            0x101a8
1426 
#define CSHRDDR3CTL_DDR3       (1 << 2)
1427 
 
1428 
/** 965 MCH register controlling DRAM channel configuration */
1429 
#define C0DRB3			0x10206
1430 
#define C1DRB3			0x10606
1431 
 
3031 serge 1432 
/** snb MCH registers for reading the DRAM channel configuration */
1433 
#define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
1434 
#define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
1435 
#define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
1436 
#define   MAD_DIMM_ECC_MASK		(0x3 << 24)
1437 
#define   MAD_DIMM_ECC_OFF		(0x0 << 24)
1438 
#define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
1439 
#define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
1440 
#define   MAD_DIMM_ECC_ON		(0x3 << 24)
1441 
#define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
1442 
#define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
1443 
#define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
1444 
#define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
1445 
#define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
1446 
#define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
1447 
#define   MAD_DIMM_A_SELECT		(0x1 << 16)
1448 
/* DIMM sizes are in multiples of 256mb. */
1449 
#define   MAD_DIMM_B_SIZE_SHIFT		8
1450 
#define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
1451 
#define   MAD_DIMM_A_SIZE_SHIFT		0
1452 
#define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
1453 
 
3480 Serge 1454 
/** snb MCH registers for priority tuning */
1455 
#define MCH_SSKPD			(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1456 
#define   MCH_SSKPD_WM0_MASK		0x3f
1457 
#define   MCH_SSKPD_WM0_VAL		0xc
3031 serge 1458 
 
4104 Serge 1459 
#define MCH_SECP_NRG_STTS		(MCHBAR_MIRROR_BASE_SNB + 0x592c)
1460 
 
2325 Serge 1461 
/* Clocking configuration register */
1462 
#define CLKCFG			0x10c00
1463 
#define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
1464 
#define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
1465 
#define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
1466 
#define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
1467 
#define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
1468 
#define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
1469 
/* Note, below two are guess */
1470 
#define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */
1471 
#define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */
1472 
#define CLKCFG_FSB_MASK					(7 << 0)
1473 
#define CLKCFG_MEM_533					(1 << 4)
1474 
#define CLKCFG_MEM_667					(2 << 4)
1475 
#define CLKCFG_MEM_800					(3 << 4)
1476 
#define CLKCFG_MEM_MASK					(7 << 4)
1477 
 
1478 
#define TSC1			0x11001
1479 
#define   TSE			(1<<0)
1480 
#define TR1			0x11006
1481 
#define TSFS			0x11020
1482 
#define   TSFS_SLOPE_MASK	0x0000ff00
1483 
#define   TSFS_SLOPE_SHIFT	8
1484 
#define   TSFS_INTR_MASK	0x000000ff
1485 
 
1486 
#define CRSTANDVID		0x11100
1487 
#define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1488 
#define   PXVFREQ_PX_MASK	0x7f000000
1489 
#define   PXVFREQ_PX_SHIFT	24
1490 
#define VIDFREQ_BASE		0x11110
1491 
#define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1492 
#define VIDFREQ2		0x11114
1493 
#define VIDFREQ3		0x11118
1494 
#define VIDFREQ4		0x1111c
1495 
#define   VIDFREQ_P0_MASK	0x1f000000
1496 
#define   VIDFREQ_P0_SHIFT	24
1497 
#define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
1498 
#define   VIDFREQ_P0_CSCLK_SHIFT 20
1499 
#define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
1500 
#define   VIDFREQ_P0_CRCLK_SHIFT 16
1501 
#define   VIDFREQ_P1_MASK	0x00001f00
1502 
#define   VIDFREQ_P1_SHIFT	8
1503 
#define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
1504 
#define   VIDFREQ_P1_CSCLK_SHIFT 4
1505 
#define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
1506 
#define INTTOEXT_BASE_ILK	0x11300
1507 
#define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
1508 
#define   INTTOEXT_MAP3_SHIFT	24
1509 
#define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
1510 
#define   INTTOEXT_MAP2_SHIFT	16
1511 
#define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
1512 
#define   INTTOEXT_MAP1_SHIFT	8
1513 
#define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
1514 
#define   INTTOEXT_MAP0_SHIFT	0
1515 
#define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
1516 
#define MEMSWCTL		0x11170 /* Ironlake only */
1517 
#define   MEMCTL_CMD_MASK	0xe000
1518 
#define   MEMCTL_CMD_SHIFT	13
1519 
#define   MEMCTL_CMD_RCLK_OFF	0
1520 
#define   MEMCTL_CMD_RCLK_ON	1
1521 
#define   MEMCTL_CMD_CHFREQ	2
1522 
#define   MEMCTL_CMD_CHVID	3
1523 
#define   MEMCTL_CMD_VMMOFF	4
1524 
#define   MEMCTL_CMD_VMMON	5
1525 
#define   MEMCTL_CMD_STS	(1<<12) /* write 1 triggers command, clears
1526 
					   when command complete */
1527 
#define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
1528 
#define   MEMCTL_FREQ_SHIFT	8
1529 
#define   MEMCTL_SFCAVM		(1<<7)
1530 
#define   MEMCTL_TGT_VID_MASK	0x007f
1531 
#define MEMIHYST		0x1117c
1532 
#define MEMINTREN		0x11180 /* 16 bits */
1533 
#define   MEMINT_RSEXIT_EN	(1<<8)
1534 
#define   MEMINT_CX_SUPR_EN	(1<<7)
1535 
#define   MEMINT_CONT_BUSY_EN	(1<<6)
1536 
#define   MEMINT_AVG_BUSY_EN	(1<<5)
1537 
#define   MEMINT_EVAL_CHG_EN	(1<<4)
1538 
#define   MEMINT_MON_IDLE_EN	(1<<3)
1539 
#define   MEMINT_UP_EVAL_EN	(1<<2)
1540 
#define   MEMINT_DOWN_EVAL_EN	(1<<1)
1541 
#define   MEMINT_SW_CMD_EN	(1<<0)
1542 
#define MEMINTRSTR		0x11182 /* 16 bits */
1543 
#define   MEM_RSEXIT_MASK	0xc000
1544 
#define   MEM_RSEXIT_SHIFT	14
1545 
#define   MEM_CONT_BUSY_MASK	0x3000
1546 
#define   MEM_CONT_BUSY_SHIFT	12
1547 
#define   MEM_AVG_BUSY_MASK	0x0c00
1548 
#define   MEM_AVG_BUSY_SHIFT	10
1549 
#define   MEM_EVAL_CHG_MASK	0x0300
1550 
#define   MEM_EVAL_BUSY_SHIFT	8
1551 
#define   MEM_MON_IDLE_MASK	0x00c0
1552 
#define   MEM_MON_IDLE_SHIFT	6
1553 
#define   MEM_UP_EVAL_MASK	0x0030
1554 
#define   MEM_UP_EVAL_SHIFT	4
1555 
#define   MEM_DOWN_EVAL_MASK	0x000c
1556 
#define   MEM_DOWN_EVAL_SHIFT	2
1557 
#define   MEM_SW_CMD_MASK	0x0003
1558 
#define   MEM_INT_STEER_GFX	0
1559 
#define   MEM_INT_STEER_CMR	1
1560 
#define   MEM_INT_STEER_SMI	2
1561 
#define   MEM_INT_STEER_SCI	3
1562 
#define MEMINTRSTS		0x11184
1563 
#define   MEMINT_RSEXIT		(1<<7)
1564 
#define   MEMINT_CONT_BUSY	(1<<6)
1565 
#define   MEMINT_AVG_BUSY	(1<<5)
1566 
#define   MEMINT_EVAL_CHG	(1<<4)
1567 
#define   MEMINT_MON_IDLE	(1<<3)
1568 
#define   MEMINT_UP_EVAL	(1<<2)
1569 
#define   MEMINT_DOWN_EVAL	(1<<1)
1570 
#define   MEMINT_SW_CMD		(1<<0)
1571 
#define MEMMODECTL		0x11190
1572 
#define   MEMMODE_BOOST_EN	(1<<31)
1573 
#define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1574 
#define   MEMMODE_BOOST_FREQ_SHIFT 24
1575 
#define   MEMMODE_IDLE_MODE_MASK 0x00030000
1576 
#define   MEMMODE_IDLE_MODE_SHIFT 16
1577 
#define   MEMMODE_IDLE_MODE_EVAL 0
1578 
#define   MEMMODE_IDLE_MODE_CONT 1
1579 
#define   MEMMODE_HWIDLE_EN	(1<<15)
1580 
#define   MEMMODE_SWMODE_EN	(1<<14)
1581 
#define   MEMMODE_RCLK_GATE	(1<<13)
1582 
#define   MEMMODE_HW_UPDATE	(1<<12)
1583 
#define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
1584 
#define   MEMMODE_FSTART_SHIFT	8
1585 
#define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
1586 
#define   MEMMODE_FMAX_SHIFT	4
1587 
#define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
1588 
#define RCBMAXAVG		0x1119c
1589 
#define MEMSWCTL2		0x1119e /* Cantiga only */
1590 
#define   SWMEMCMD_RENDER_OFF	(0 << 13)
1591 
#define   SWMEMCMD_RENDER_ON	(1 << 13)
1592 
#define   SWMEMCMD_SWFREQ	(2 << 13)
1593 
#define   SWMEMCMD_TARVID	(3 << 13)
1594 
#define   SWMEMCMD_VRM_OFF	(4 << 13)
1595 
#define   SWMEMCMD_VRM_ON	(5 << 13)
1596 
#define   CMDSTS		(1<<12)
1597 
#define   SFCAVM		(1<<11)
1598 
#define   SWFREQ_MASK		0x0380 /* P0-7 */
1599 
#define   SWFREQ_SHIFT		7
1600 
#define   TARVID_MASK		0x001f
1601 
#define MEMSTAT_CTG		0x111a0
1602 
#define RCBMINAVG		0x111a0
1603 
#define RCUPEI			0x111b0
1604 
#define RCDNEI			0x111b4
1605 
#define RSTDBYCTL		0x111b8
1606 
#define   RS1EN			(1<<31)
1607 
#define   RS2EN			(1<<30)
1608 
#define   RS3EN			(1<<29)
1609 
#define   D3RS3EN		(1<<28) /* Display D3 imlies RS3 */
1610 
#define   SWPROMORSX		(1<<27) /* RSx promotion timers ignored */
1611 
#define   RCWAKERW		(1<<26) /* Resetwarn from PCH causes wakeup */
1612 
#define   DPRSLPVREN		(1<<25) /* Fast voltage ramp enable */
1613 
#define   GFXTGHYST		(1<<24) /* Hysteresis to allow trunk gating */
1614 
#define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
1615 
#define   RSX_STATUS_MASK	(7<<20)
1616 
#define   RSX_STATUS_ON		(0<<20)
1617 
#define   RSX_STATUS_RC1	(1<<20)
1618 
#define   RSX_STATUS_RC1E	(2<<20)
1619 
#define   RSX_STATUS_RS1	(3<<20)
1620 
#define   RSX_STATUS_RS2	(4<<20) /* aka rc6 */
1621 
#define   RSX_STATUS_RSVD	(5<<20) /* deep rc6 unsupported on ilk */
1622 
#define   RSX_STATUS_RS3	(6<<20) /* rs3 unsupported on ilk */
1623 
#define   RSX_STATUS_RSVD2	(7<<20)
1624 
#define   UWRCRSXE		(1<<19) /* wake counter limit prevents rsx */
1625 
#define   RSCRP			(1<<18) /* rs requests control on rs1/2 reqs */
1626 
#define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
1627 
#define   RS2INC0		(1<<16) /* allow rs2 in cpu c0 */
1628 
#define   RS1CONTSAV_MASK	(3<<14)
1629 
#define   RS1CONTSAV_NO_RS1	(0<<14) /* rs1 doesn't save/restore context */
1630 
#define   RS1CONTSAV_RSVD	(1<<14)
1631 
#define   RS1CONTSAV_SAVE_RS1	(2<<14) /* rs1 saves context */
1632 
#define   RS1CONTSAV_FULL_RS1	(3<<14) /* rs1 saves and restores context */
1633 
#define   NORMSLEXLAT_MASK	(3<<12)
1634 
#define   SLOW_RS123		(0<<12)
1635 
#define   SLOW_RS23		(1<<12)
1636 
#define   SLOW_RS3		(2<<12)
1637 
#define   NORMAL_RS123		(3<<12)
1638 
#define   RCMODE_TIMEOUT	(1<<11) /* 0 is eval interval method */
1639 
#define   IMPROMOEN		(1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1640 
#define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
1641 
#define   STATELOCK		(1<<7) /* locked to rs_cstate if 0 */
1642 
#define   RS_CSTATE_MASK	(3<<4)
1643 
#define   RS_CSTATE_C367_RS1	(0<<4)
1644 
#define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1645 
#define   RS_CSTATE_RSVD	(2<<4)
1646 
#define   RS_CSTATE_C367_RS2	(3<<4)
1647 
#define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
1648 
#define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
1649 
#define VIDCTL			0x111c0
1650 
#define VIDSTS			0x111c8
1651 
#define VIDSTART		0x111cc /* 8 bits */
1652 
#define MEMSTAT_ILK			0x111f8
1653 
#define   MEMSTAT_VID_MASK	0x7f00
1654 
#define   MEMSTAT_VID_SHIFT	8
1655 
#define   MEMSTAT_PSTATE_MASK	0x00f8
1656 
#define   MEMSTAT_PSTATE_SHIFT  3
1657 
#define   MEMSTAT_MON_ACTV	(1<<2)
1658 
#define   MEMSTAT_SRC_CTL_MASK	0x0003
1659 
#define   MEMSTAT_SRC_CTL_CORE	0
1660 
#define   MEMSTAT_SRC_CTL_TRB	1
1661 
#define   MEMSTAT_SRC_CTL_THM	2
1662 
#define   MEMSTAT_SRC_CTL_STDBY 3
1663 
#define RCPREVBSYTUPAVG		0x113b8
1664 
#define RCPREVBSYTDNAVG		0x113bc
1665 
#define PMMISC			0x11214
1666 
#define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
1667 
#define SDEW			0x1124c
1668 
#define CSIEW0			0x11250
1669 
#define CSIEW1			0x11254
1670 
#define CSIEW2			0x11258
1671 
#define PEW			0x1125c
1672 
#define DEW			0x11270
1673 
#define MCHAFE			0x112c0
1674 
#define CSIEC			0x112e0
1675 
#define DMIEC			0x112e4
1676 
#define DDREC			0x112e8
1677 
#define PEG0EC			0x112ec
1678 
#define PEG1EC			0x112f0
1679 
#define GFXEC			0x112f4
1680 
#define RPPREVBSYTUPAVG		0x113b8
1681 
#define RPPREVBSYTDNAVG		0x113bc
1682 
#define ECR			0x11600
1683 
#define   ECR_GPFE		(1<<31)
1684 
#define   ECR_IMONE		(1<<30)
1685 
#define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
1686 
#define OGW0			0x11608
1687 
#define OGW1			0x1160c
1688 
#define EG0			0x11610
1689 
#define EG1			0x11614
1690 
#define EG2			0x11618
1691 
#define EG3			0x1161c
1692 
#define EG4			0x11620
1693 
#define EG5			0x11624
1694 
#define EG6			0x11628
1695 
#define EG7			0x1162c
1696 
#define PXW			0x11664
1697 
#define PXWL			0x11680
1698 
#define LCFUSE02		0x116c0
1699 
#define   LCFUSE_HIV_MASK	0x000000ff
1700 
#define CSIPLL0			0x12c10
1701 
#define DDRMPLL1		0X12c20
1702 
#define PEG_BAND_GAP_DATA	0x14d68
1703 
 
3031 serge 1704 
#define GEN6_GT_THREAD_STATUS_REG 0x13805c
1705 
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1706 
#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1707 
 
2325 Serge 1708 
#define GEN6_GT_PERF_STATUS	0x145948
1709 
#define GEN6_RP_STATE_LIMITS	0x145994
1710 
#define GEN6_RP_STATE_CAP	0x145998
1711 
 
1712 
/*
1713 
 * Logical Context regs
1714 
 */
1715 
#define CCID			0x2180
1716 
#define   CCID_EN		(1<<0)
4104 Serge 1717 
/*
1718 
 * Notes on SNB/IVB/VLV context size:
1719 
 * - Power context is saved elsewhere (LLC or stolen)
1720 
 * - Ring/execlist context is saved on SNB, not on IVB
1721 
 * - Extended context size already includes render context size
1722 
 * - We always need to follow the extended context size.
1723 
 *   SNB BSpec has comments indicating that we should use the
1724 
 *   render context size instead if execlists are disabled, but
1725 
 *   based on empirical testing that's just nonsense.
1726 
 * - Pipelined/VF state is saved on SNB/IVB respectively
1727 
 * - GT1 size just indicates how much of render context
1728 
 *   doesn't need saving on GT1
1729 
 */
3031 serge 1730 
#define CXT_SIZE		0x21a0
1731 
#define GEN6_CXT_POWER_SIZE(cxt_reg)	((cxt_reg >> 24) & 0x3f)
1732 
#define GEN6_CXT_RING_SIZE(cxt_reg)	((cxt_reg >> 18) & 0x3f)
1733 
#define GEN6_CXT_RENDER_SIZE(cxt_reg)	((cxt_reg >> 12) & 0x3f)
1734 
#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	((cxt_reg >> 6) & 0x3f)
1735 
#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	((cxt_reg >> 0) & 0x3f)
4104 Serge 1736 
#define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
3031 serge 1737 
					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1738 
					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1739 
#define GEN7_CXT_SIZE		0x21a8
1740 
#define GEN7_CXT_POWER_SIZE(ctx_reg)	((ctx_reg >> 25) & 0x7f)
1741 
#define GEN7_CXT_RING_SIZE(ctx_reg)	((ctx_reg >> 22) & 0x7)
1742 
#define GEN7_CXT_RENDER_SIZE(ctx_reg)	((ctx_reg >> 16) & 0x3f)
1743 
#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	((ctx_reg >> 9) & 0x7f)
1744 
#define GEN7_CXT_GT1_SIZE(ctx_reg)	((ctx_reg >> 6) & 0x7)
1745 
#define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	((ctx_reg >> 0) & 0x3f)
4104 Serge 1746 
#define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3031 serge 1747 
					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4104 Serge 1748 
/* Haswell does have the CXT_SIZE register however it does not appear to be
1749 
 * valid. Now, docs explain in dwords what is in the context object. The full
1750 
 * size is 70720 bytes, however, the power context and execlist context will
1751 
 * never be saved (power context is stored elsewhere, and execlists don't work
1752 
 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
1753 
 */
1754 
#define HSW_CXT_TOTAL_SIZE		(17 * PAGE_SIZE)
3031 serge 1755 
 
2325 Serge 1756 
/*
1757 
 * Overlay regs
1758 
 */
1759 
 
1760 
#define OVADD			0x30000
1761 
#define DOVSTA			0x30008
1762 
#define OC_BUF			(0x3<<20)
1763 
#define OGAMC5			0x30010
1764 
#define OGAMC4			0x30014
1765 
#define OGAMC3			0x30018
1766 
#define OGAMC2			0x3001c
1767 
#define OGAMC1			0x30020
1768 
#define OGAMC0			0x30024
1769 
 
1770 
/*
1771 
 * Display engine regs
1772 
 */
1773 
 
1774 
/* Pipe A timing regs */
3480 Serge 1775 
#define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)
1776 
#define _HBLANK_A	(dev_priv->info->display_mmio_offset + 0x60004)
1777 
#define _HSYNC_A	(dev_priv->info->display_mmio_offset + 0x60008)
1778 
#define _VTOTAL_A	(dev_priv->info->display_mmio_offset + 0x6000c)
1779 
#define _VBLANK_A	(dev_priv->info->display_mmio_offset + 0x60010)
1780 
#define _VSYNC_A	(dev_priv->info->display_mmio_offset + 0x60014)
1781 
#define _PIPEASRC	(dev_priv->info->display_mmio_offset + 0x6001c)
1782 
#define _BCLRPAT_A	(dev_priv->info->display_mmio_offset + 0x60020)
1783 
#define _VSYNCSHIFT_A	(dev_priv->info->display_mmio_offset + 0x60028)
2325 Serge 1784 
 
1785 
/* Pipe B timing regs */
3480 Serge 1786 
#define _HTOTAL_B	(dev_priv->info->display_mmio_offset + 0x61000)
1787 
#define _HBLANK_B	(dev_priv->info->display_mmio_offset + 0x61004)
1788 
#define _HSYNC_B	(dev_priv->info->display_mmio_offset + 0x61008)
1789 
#define _VTOTAL_B	(dev_priv->info->display_mmio_offset + 0x6100c)
1790 
#define _VBLANK_B	(dev_priv->info->display_mmio_offset + 0x61010)
1791 
#define _VSYNC_B	(dev_priv->info->display_mmio_offset + 0x61014)
1792 
#define _PIPEBSRC	(dev_priv->info->display_mmio_offset + 0x6101c)
1793 
#define _BCLRPAT_B	(dev_priv->info->display_mmio_offset + 0x61020)
1794 
#define _VSYNCSHIFT_B	(dev_priv->info->display_mmio_offset + 0x61028)
2325 Serge 1795 
 
3031 serge 1796 
 
3243 Serge 1797 
#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1798 
#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1799 
#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1800 
#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1801 
#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1802 
#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
2325 Serge 1803 
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
3243 Serge 1804 
#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
2325 Serge 1805 
 
4104 Serge 1806 
/* HSW eDP PSR registers */
1807 
#define EDP_PSR_CTL				0x64800
1808 
#define   EDP_PSR_ENABLE			(1<<31)
1809 
#define   EDP_PSR_LINK_DISABLE			(0<<27)
1810 
#define   EDP_PSR_LINK_STANDBY			(1<<27)
1811 
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3<<25)
1812 
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0<<25)
1813 
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES	(1<<25)
1814 
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES	(2<<25)
1815 
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES	(3<<25)
1816 
#define   EDP_PSR_MAX_SLEEP_TIME_SHIFT		20
1817 
#define   EDP_PSR_SKIP_AUX_EXIT			(1<<12)
1818 
#define   EDP_PSR_TP1_TP2_SEL			(0<<11)
1819 
#define   EDP_PSR_TP1_TP3_SEL			(1<<11)
1820 
#define   EDP_PSR_TP2_TP3_TIME_500us		(0<<8)
1821 
#define   EDP_PSR_TP2_TP3_TIME_100us		(1<<8)
1822 
#define   EDP_PSR_TP2_TP3_TIME_2500us		(2<<8)
1823 
#define   EDP_PSR_TP2_TP3_TIME_0us		(3<<8)
1824 
#define   EDP_PSR_TP1_TIME_500us		(0<<4)
1825 
#define   EDP_PSR_TP1_TIME_100us		(1<<4)
1826 
#define   EDP_PSR_TP1_TIME_2500us		(2<<4)
1827 
#define   EDP_PSR_TP1_TIME_0us			(3<<4)
1828 
#define   EDP_PSR_IDLE_FRAME_SHIFT		0
1829 
 
1830 
#define EDP_PSR_AUX_CTL			0x64810
1831 
#define EDP_PSR_AUX_DATA1		0x64814
1832 
#define   EDP_PSR_DPCD_COMMAND		0x80060000
1833 
#define EDP_PSR_AUX_DATA2		0x64818
1834 
#define   EDP_PSR_DPCD_NORMAL_OPERATION	(1<<24)
1835 
#define EDP_PSR_AUX_DATA3		0x6481c
1836 
#define EDP_PSR_AUX_DATA4		0x64820
1837 
#define EDP_PSR_AUX_DATA5		0x64824
1838 
 
1839 
#define EDP_PSR_STATUS_CTL			0x64840
1840 
#define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
1841 
#define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
1842 
#define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
1843 
#define   EDP_PSR_STATUS_STATE_SRDENT		(2<<29)
1844 
#define   EDP_PSR_STATUS_STATE_BUFOFF		(3<<29)
1845 
#define   EDP_PSR_STATUS_STATE_BUFON		(4<<29)
1846 
#define   EDP_PSR_STATUS_STATE_AUXACK		(5<<29)
1847 
#define   EDP_PSR_STATUS_STATE_SRDOFFACK	(6<<29)
1848 
#define   EDP_PSR_STATUS_LINK_MASK		(3<<26)
1849 
#define   EDP_PSR_STATUS_LINK_FULL_OFF		(0<<26)
1850 
#define   EDP_PSR_STATUS_LINK_FULL_ON		(1<<26)
1851 
#define   EDP_PSR_STATUS_LINK_STANDBY		(2<<26)
1852 
#define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT	20
1853 
#define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
1854 
#define   EDP_PSR_STATUS_COUNT_SHIFT		16
1855 
#define   EDP_PSR_STATUS_COUNT_MASK		0xf
1856 
#define   EDP_PSR_STATUS_AUX_ERROR		(1<<15)
1857 
#define   EDP_PSR_STATUS_AUX_SENDING		(1<<12)
1858 
#define   EDP_PSR_STATUS_SENDING_IDLE		(1<<9)
1859 
#define   EDP_PSR_STATUS_SENDING_TP2_TP3	(1<<8)
1860 
#define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
1861 
#define   EDP_PSR_STATUS_IDLE_MASK		0xf
1862 
 
1863 
#define EDP_PSR_PERF_CNT		0x64844
1864 
#define   EDP_PSR_PERF_CNT_MASK		0xffffff
1865 
 
1866 
#define EDP_PSR_DEBUG_CTL		0x64860
1867 
#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
1868 
#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
1869 
#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
1870 
 
2325 Serge 1871 
/* VGA port control */
1872 
#define ADPA			0x61100
3031 serge 1873 
#define PCH_ADPA                0xe1100
1874 
#define VLV_ADPA		(VLV_DISPLAY_BASE + ADPA)
1875 
 
2325 Serge 1876 
#define   ADPA_DAC_ENABLE	(1<<31)
1877 
#define   ADPA_DAC_DISABLE	0
1878 
#define   ADPA_PIPE_SELECT_MASK	(1<<30)
1879 
#define   ADPA_PIPE_A_SELECT	0
1880 
#define   ADPA_PIPE_B_SELECT	(1<<30)
1881 
#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
3031 serge 1882 
/* CPT uses bits 29:30 for pch transcoder select */
1883 
#define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
1884 
#define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
1885 
#define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
1886 
#define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
1887 
#define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
1888 
#define   ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
1889 
#define   ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
1890 
#define   ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
1891 
#define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
1892 
#define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
1893 
#define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
1894 
#define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
1895 
#define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
1896 
#define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
1897 
#define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
1898 
#define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
1899 
#define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
1900 
#define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
1901 
#define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2325 Serge 1902 
#define   ADPA_USE_VGA_HVPOLARITY (1<<15)
1903 
#define   ADPA_SETS_HVPOLARITY	0
3480 Serge 1904 
#define   ADPA_VSYNC_CNTL_DISABLE (1<<10)
2325 Serge 1905 
#define   ADPA_VSYNC_CNTL_ENABLE 0
3480 Serge 1906 
#define   ADPA_HSYNC_CNTL_DISABLE (1<<11)
2325 Serge 1907 
#define   ADPA_HSYNC_CNTL_ENABLE 0
1908 
#define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1909 
#define   ADPA_VSYNC_ACTIVE_LOW	0
1910 
#define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1911 
#define   ADPA_HSYNC_ACTIVE_LOW	0
1912 
#define   ADPA_DPMS_MASK	(~(3<<10))
1913 
#define   ADPA_DPMS_ON		(0<<10)
1914 
#define   ADPA_DPMS_SUSPEND	(1<<10)
1915 
#define   ADPA_DPMS_STANDBY	(2<<10)
1916 
#define   ADPA_DPMS_OFF		(3<<10)
1917 
 
1918 
 
1919 
/* Hotplug control (945+ only) */
3480 Serge 1920 
#define PORT_HOTPLUG_EN		(dev_priv->info->display_mmio_offset + 0x61110)
1921 
#define   PORTB_HOTPLUG_INT_EN			(1 << 29)
1922 
#define   PORTC_HOTPLUG_INT_EN			(1 << 28)
1923 
#define   PORTD_HOTPLUG_INT_EN			(1 << 27)
2325 Serge 1924 
#define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
1925 
#define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
1926 
#define   TV_HOTPLUG_INT_EN			(1 << 18)
1927 
#define   CRT_HOTPLUG_INT_EN			(1 << 9)
3746 Serge 1928 
#define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
1929 
						 PORTC_HOTPLUG_INT_EN | \
1930 
						 PORTD_HOTPLUG_INT_EN | \
1931 
						 SDVOC_HOTPLUG_INT_EN | \
1932 
						 SDVOB_HOTPLUG_INT_EN | \
1933 
						 CRT_HOTPLUG_INT_EN)
2325 Serge 1934 
#define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
1935 
#define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
1936 
/* must use period 64 on GM45 according to docs */
1937 
#define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
1938 
#define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
1939 
#define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
1940 
#define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
1941 
#define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
1942 
#define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
1943 
#define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
1944 
#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
1945 
#define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
1946 
#define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
1947 
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
1948 
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
1949 
 
3480 Serge 1950 
#define PORT_HOTPLUG_STAT	(dev_priv->info->display_mmio_offset + 0x61114)
4104 Serge 1951 
/*
1952 
 * HDMI/DP bits are gen4+
1953 
 *
1954 
 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
1955 
 * Please check the detailed lore in the commit message for for experimental
1956 
 * evidence.
1957 
 */
1958 
#define   PORTD_HOTPLUG_LIVE_STATUS               (1 << 29)
3480 Serge 1959 
#define   PORTC_HOTPLUG_LIVE_STATUS               (1 << 28)
4104 Serge 1960 
#define   PORTB_HOTPLUG_LIVE_STATUS               (1 << 27)
3480 Serge 1961 
#define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
1962 
#define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
1963 
#define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
3031 serge 1964 
/* CRT/TV common between gen3+ */
2325 Serge 1965 
#define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
1966 
#define   TV_HOTPLUG_INT_STATUS			(1 << 10)
1967 
#define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
1968 
#define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
1969 
#define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
1970 
#define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
3031 serge 1971 
/* SDVO is different across gen3/4 */
1972 
#define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
1973 
#define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
4104 Serge 1974 
/*
1975 
 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
1976 
 * since reality corrobates that they're the same as on gen3. But keep these
1977 
 * bits here (and the comment!) to help any other lost wanderers back onto the
1978 
 * right tracks.
1979 
 */
3031 serge 1980 
#define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
1981 
#define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
1982 
#define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
1983 
#define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
3746 Serge 1984 
#define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
1985 
						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
1986 
						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
1987 
						 PORTB_HOTPLUG_INT_STATUS | \
1988 
						 PORTC_HOTPLUG_INT_STATUS | \
1989 
						 PORTD_HOTPLUG_INT_STATUS)
2325 Serge 1990 
 
3746 Serge 1991 
#define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
1992 
						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
1993 
						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
1994 
						 PORTB_HOTPLUG_INT_STATUS | \
1995 
						 PORTC_HOTPLUG_INT_STATUS | \
1996 
						 PORTD_HOTPLUG_INT_STATUS)
1997 
 
1998 
/* SDVO and HDMI port control.
1999 
 * The same register may be used for SDVO or HDMI */
2000 
#define GEN3_SDVOB	0x61140
2001 
#define GEN3_SDVOC	0x61160
2002 
#define GEN4_HDMIB	GEN3_SDVOB
2003 
#define GEN4_HDMIC	GEN3_SDVOC
2004 
#define PCH_SDVOB	0xe1140
2005 
#define PCH_HDMIB	PCH_SDVOB
2006 
#define PCH_HDMIC	0xe1150
2007 
#define PCH_HDMID	0xe1160
2008 
 
2009 
/* Gen 3 SDVO bits: */
2325 Serge 2010 
#define   SDVO_ENABLE		(1 << 31)
3746 Serge 2011 
#define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
2012 
#define   SDVO_PIPE_SEL_MASK			(1 << 30)
2325 Serge 2013 
#define   SDVO_PIPE_B_SELECT	(1 << 30)
2014 
#define   SDVO_STALL_SELECT	(1 << 29)
2015 
#define   SDVO_INTERRUPT_ENABLE	(1 << 26)
2016 
/**
2017 
 * 915G/GM SDVO pixel multiplier.
2018 
 * Programmed value is multiplier - 1, up to 5x.
2019 
 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2020 
 */
2021 
#define   SDVO_PORT_MULTIPLY_MASK	(7 << 23)
2022 
#define   SDVO_PORT_MULTIPLY_SHIFT		23
2023 
#define   SDVO_PHASE_SELECT_MASK	(15 << 19)
2024 
#define   SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
2025 
#define   SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
3746 Serge 2026 
#define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
2027 
#define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
2028 
#define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
2029 
#define   SDVO_DETECTED				(1 << 2)
2030 
/* Bits to be preserved when writing */
2031 
#define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2032 
			       SDVO_INTERRUPT_ENABLE)
2033 
#define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2034 
 
2035 
/* Gen 4 SDVO/HDMI bits: */
2036 
#define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
2037 
#define   SDVO_ENCODING_SDVO			(0 << 10)
2038 
#define   SDVO_ENCODING_HDMI			(2 << 10)
2039 
#define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
2040 
#define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
2041 
#define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
2325 Serge 2042 
#define   SDVO_AUDIO_ENABLE		(1 << 6)
3746 Serge 2043 
/* VSYNC/HSYNC bits new with 965, default is to be set */
2325 Serge 2044 
#define   SDVO_VSYNC_ACTIVE_HIGH	(1 << 4)
2045 
#define   SDVO_HSYNC_ACTIVE_HIGH	(1 << 3)
2046 
 
3746 Serge 2047 
/* Gen 5 (IBX) SDVO/HDMI bits: */
2048 
#define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
2049 
#define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
2050 
 
2051 
/* Gen 6 (CPT) SDVO/HDMI bits: */
2052 
#define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
2053 
#define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
2054 
 
2055 
 
2325 Serge 2056 
/* DVO port control */
2057 
#define DVOA			0x61120
2058 
#define DVOB			0x61140
2059 
#define DVOC			0x61160
2060 
#define   DVO_ENABLE			(1 << 31)
2061 
#define   DVO_PIPE_B_SELECT		(1 << 30)
2062 
#define   DVO_PIPE_STALL_UNUSED		(0 << 28)
2063 
#define   DVO_PIPE_STALL		(1 << 28)
2064 
#define   DVO_PIPE_STALL_TV		(2 << 28)
2065 
#define   DVO_PIPE_STALL_MASK		(3 << 28)
2066 
#define   DVO_USE_VGA_SYNC		(1 << 15)
2067 
#define   DVO_DATA_ORDER_I740		(0 << 14)
2068 
#define   DVO_DATA_ORDER_FP		(1 << 14)
2069 
#define   DVO_VSYNC_DISABLE		(1 << 11)
2070 
#define   DVO_HSYNC_DISABLE		(1 << 10)
2071 
#define   DVO_VSYNC_TRISTATE		(1 << 9)
2072 
#define   DVO_HSYNC_TRISTATE		(1 << 8)
2073 
#define   DVO_BORDER_ENABLE		(1 << 7)
2074 
#define   DVO_DATA_ORDER_GBRG		(1 << 6)
2075 
#define   DVO_DATA_ORDER_RGGB		(0 << 6)
2076 
#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
2077 
#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
2078 
#define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
2079 
#define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
2080 
#define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
2081 
#define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
2082 
#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
2083 
#define   DVO_PRESERVE_MASK		(0x7<<24)
2084 
#define DVOA_SRCDIM		0x61124
2085 
#define DVOB_SRCDIM		0x61144
2086 
#define DVOC_SRCDIM		0x61164
2087 
#define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
2088 
#define   DVO_SRCDIM_VERTICAL_SHIFT	0
2089 
 
2090 
/* LVDS port control */
2091 
#define LVDS			0x61180
2092 
/*
2093 
 * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
2094 
 * the DPLL semantics change when the LVDS is assigned to that pipe.
2095 
 */
2096 
#define   LVDS_PORT_EN			(1 << 31)
2097 
/* Selects pipe B for LVDS data.  Must be set on pre-965. */
2098 
#define   LVDS_PIPEB_SELECT		(1 << 30)
2099 
#define   LVDS_PIPE_MASK		(1 << 30)
2100 
#define   LVDS_PIPE(pipe)		((pipe) << 30)
2101 
/* LVDS dithering flag on 965/g4x platform */
2102 
#define   LVDS_ENABLE_DITHER		(1 << 25)
2103 
/* LVDS sync polarity flags. Set to invert (i.e. negative) */
2104 
#define   LVDS_VSYNC_POLARITY		(1 << 21)
2105 
#define   LVDS_HSYNC_POLARITY		(1 << 20)
2106 
 
2107 
/* Enable border for unscaled (or aspect-scaled) display */
2108 
#define   LVDS_BORDER_ENABLE		(1 << 15)
2109 
/*
2110 
 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2111 
 * pixel.
2112 
 */
2113 
#define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
2114 
#define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
2115 
#define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
2116 
/*
2117 
 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2118 
 * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2119 
 * on.
2120 
 */
2121 
#define   LVDS_A3_POWER_MASK		(3 << 6)
2122 
#define   LVDS_A3_POWER_DOWN		(0 << 6)
2123 
#define   LVDS_A3_POWER_UP		(3 << 6)
2124 
/*
2125 
 * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
2126 
 * is set.
2127 
 */
2128 
#define   LVDS_CLKB_POWER_MASK		(3 << 4)
2129 
#define   LVDS_CLKB_POWER_DOWN		(0 << 4)
2130 
#define   LVDS_CLKB_POWER_UP		(3 << 4)
2131 
/*
2132 
 * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
2133 
 * setting for whether we are in dual-channel mode.  The B3 pair will
2134 
 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2135 
 */
2136 
#define   LVDS_B0B3_POWER_MASK		(3 << 2)
2137 
#define   LVDS_B0B3_POWER_DOWN		(0 << 2)
2138 
#define   LVDS_B0B3_POWER_UP		(3 << 2)
2139 
 
2140 
/* Video Data Island Packet control */
2141 
#define VIDEO_DIP_DATA		0x61178
3031 serge 2142 
/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2143 
 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2144 
 * of the infoframe structure specified by CEA-861. */
2145 
#define   VIDEO_DIP_DATA_SIZE	32
4104 Serge 2146 
#define   VIDEO_DIP_VSC_DATA_SIZE	36
2325 Serge 2147 
#define VIDEO_DIP_CTL		0x61170
3031 serge 2148 
/* Pre HSW: */
2325 Serge 2149 
#define   VIDEO_DIP_ENABLE		(1 << 31)
2150 
#define   VIDEO_DIP_PORT_B		(1 << 29)
2151 
#define   VIDEO_DIP_PORT_C		(2 << 29)
3031 serge 2152 
#define   VIDEO_DIP_PORT_D		(3 << 29)
2153 
#define   VIDEO_DIP_PORT_MASK		(3 << 29)
2154 
#define   VIDEO_DIP_ENABLE_GCP		(1 << 25)
2325 Serge 2155 
#define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
2156 
#define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
3031 serge 2157 
#define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21)
2325 Serge 2158 
#define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
2159 
#define   VIDEO_DIP_SELECT_AVI		(0 << 19)
2160 
#define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
2161 
#define   VIDEO_DIP_SELECT_SPD		(3 << 19)
2162 
#define   VIDEO_DIP_SELECT_MASK		(3 << 19)
2163 
#define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
2164 
#define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
2165 
#define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
3031 serge 2166 
#define   VIDEO_DIP_FREQ_MASK		(3 << 16)
2167 
/* HSW and later: */
2168 
#define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
2169 
#define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
2170 
#define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
2171 
#define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
2172 
#define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
2173 
#define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
2325 Serge 2174 
 
2175 
/* Panel power sequencing */
2176 
#define PP_STATUS	0x61200
2177 
#define   PP_ON		(1 << 31)
2178 
/*
2179 
 * Indicates that all dependencies of the panel are on:
2180 
 *
2181 
 * - PLL enabled
2182 
 * - pipe enabled
2183 
 * - LVDS/DVOB/DVOC on
2184 
 */
2185 
#define   PP_READY		(1 << 30)
2186 
#define   PP_SEQUENCE_NONE	(0 << 28)
2342 Serge 2187 
#define   PP_SEQUENCE_POWER_UP	(1 << 28)
2188 
#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
2189 
#define   PP_SEQUENCE_MASK	(3 << 28)
2190 
#define   PP_SEQUENCE_SHIFT	28
2325 Serge 2191 
#define   PP_CYCLE_DELAY_ACTIVE	(1 << 27)
2192 
#define   PP_SEQUENCE_STATE_MASK 0x0000000f
2342 Serge 2193 
#define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
2194 
#define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
2195 
#define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
2196 
#define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
2197 
#define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
2198 
#define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
2199 
#define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
2200 
#define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
2201 
#define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
2325 Serge 2202 
#define PP_CONTROL	0x61204
2203 
#define   POWER_TARGET_ON	(1 << 0)
2204 
#define PP_ON_DELAYS	0x61208
2205 
#define PP_OFF_DELAYS	0x6120c
2206 
#define PP_DIVISOR	0x61210
2207 
 
2208 
/* Panel fitting */
3480 Serge 2209 
#define PFIT_CONTROL	(dev_priv->info->display_mmio_offset + 0x61230)
2325 Serge 2210 
#define   PFIT_ENABLE		(1 << 31)
2211 
#define   PFIT_PIPE_MASK	(3 << 29)
2212 
#define   PFIT_PIPE_SHIFT	29
2213 
#define   VERT_INTERP_DISABLE	(0 << 10)
2214 
#define   VERT_INTERP_BILINEAR	(1 << 10)
2215 
#define   VERT_INTERP_MASK	(3 << 10)
2216 
#define   VERT_AUTO_SCALE	(1 << 9)
2217 
#define   HORIZ_INTERP_DISABLE	(0 << 6)
2218 
#define   HORIZ_INTERP_BILINEAR	(1 << 6)
2219 
#define   HORIZ_INTERP_MASK	(3 << 6)
2220 
#define   HORIZ_AUTO_SCALE	(1 << 5)
2221 
#define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
2222 
#define   PFIT_FILTER_FUZZY	(0 << 24)
2223 
#define   PFIT_SCALING_AUTO	(0 << 26)
2224 
#define   PFIT_SCALING_PROGRAMMED (1 << 26)
2225 
#define   PFIT_SCALING_PILLAR	(2 << 26)
2226 
#define   PFIT_SCALING_LETTER	(3 << 26)
3480 Serge 2227 
#define PFIT_PGM_RATIOS	(dev_priv->info->display_mmio_offset + 0x61234)
2325 Serge 2228 
/* Pre-965 */
2229 
#define		PFIT_VERT_SCALE_SHIFT		20
2230 
#define		PFIT_VERT_SCALE_MASK		0xfff00000
2231 
#define		PFIT_HORIZ_SCALE_SHIFT		4
2232 
#define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
2233 
/* 965+ */
2234 
#define		PFIT_VERT_SCALE_SHIFT_965	16
2235 
#define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
2236 
#define		PFIT_HORIZ_SCALE_SHIFT_965	0
2237 
#define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
2238 
 
3480 Serge 2239 
#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
2325 Serge 2240 
 
2241 
/* Backlight control */
3746 Serge 2242 
#define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
3031 serge 2243 
#define   BLM_PWM_ENABLE		(1 << 31)
2244 
#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
2245 
#define   BLM_PIPE_SELECT		(1 << 29)
2246 
#define   BLM_PIPE_SELECT_IVB		(3 << 29)
2247 
#define   BLM_PIPE_A			(0 << 29)
2248 
#define   BLM_PIPE_B			(1 << 29)
2249 
#define   BLM_PIPE_C			(2 << 29) /* ivb + */
4104 Serge 2250 
#define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
2251 
#define   BLM_TRANSCODER_B		BLM_PIPE_B
2252 
#define   BLM_TRANSCODER_C		BLM_PIPE_C
2253 
#define   BLM_TRANSCODER_EDP		(3 << 29)
3031 serge 2254 
#define   BLM_PIPE(pipe)		((pipe) << 29)
2255 
#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
2256 
#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
2257 
#define   BLM_PHASE_IN_ENABLE		(1 << 25)
2258 
#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
2259 
#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
2260 
#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
2261 
#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
2262 
#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
2263 
#define   BLM_PHASE_IN_INCR_SHIFT	(0)
2264 
#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
3746 Serge 2265 
#define BLC_PWM_CTL	(dev_priv->info->display_mmio_offset + 0x61254)
2325 Serge 2266 
/*
2267 
 * This is the most significant 15 bits of the number of backlight cycles in a
2268 
 * complete cycle of the modulated backlight control.
2269 
 *
2270 
 * The actual value is this field multiplied by two.
2271 
 */
3031 serge 2272 
#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
2325 Serge 2273 
#define   BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
3031 serge 2274 
#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
2325 Serge 2275 
/*
2276 
 * This is the number of cycles out of the backlight modulation cycle for which
2277 
 * the backlight is on.
2278 
 *
2279 
 * This field must be no greater than the number of cycles in the complete
2280 
 * backlight modulation cycle.
2281 
 */
2282 
#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
2283 
#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
3031 serge 2284 
#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
2285 
#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
2325 Serge 2286 
 
3746 Serge 2287 
#define BLC_HIST_CTL	(dev_priv->info->display_mmio_offset + 0x61260)
2325 Serge 2288 
 
3031 serge 2289 
/* New registers for PCH-split platforms. Safe where new bits show up, the
2290 
 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2291 
#define BLC_PWM_CPU_CTL2	0x48250
2292 
#define BLC_PWM_CPU_CTL		0x48254
2293 
 
4104 Serge 2294 
#define HSW_BLC_PWM2_CTL	0x48350
2295 
 
3031 serge 2296 
/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2297 
 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2298 
#define BLC_PWM_PCH_CTL1	0xc8250
2299 
#define   BLM_PCH_PWM_ENABLE			(1 << 31)
2300 
#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
2301 
#define   BLM_PCH_POLARITY			(1 << 29)
2302 
#define BLC_PWM_PCH_CTL2	0xc8254
2303 
 
4104 Serge 2304 
#define UTIL_PIN_CTL		0x48400
2305 
#define   UTIL_PIN_ENABLE	(1 << 31)
2306 
 
2307 
#define PCH_GTC_CTL		0xe7000
2308 
#define   PCH_GTC_ENABLE	(1 << 31)
2309 
 
2325 Serge 2310 
/* TV port control */
2311 
#define TV_CTL			0x68000
2312 
/** Enables the TV encoder */
2313 
# define TV_ENC_ENABLE			(1 << 31)
2314 
/** Sources the TV encoder input from pipe B instead of A. */
2315 
# define TV_ENC_PIPEB_SELECT		(1 << 30)
2316 
/** Outputs composite video (DAC A only) */
2317 
# define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
2318 
/** Outputs SVideo video (DAC B/C) */
2319 
# define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
2320 
/** Outputs Component video (DAC A/B/C) */
2321 
# define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
2322 
/** Outputs Composite and SVideo (DAC A/B/C) */
2323 
# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
2324 
# define TV_TRILEVEL_SYNC		(1 << 21)
2325 
/** Enables slow sync generation (945GM only) */
2326 
# define TV_SLOW_SYNC			(1 << 20)
2327 
/** Selects 4x oversampling for 480i and 576p */
2328 
# define TV_OVERSAMPLE_4X		(0 << 18)
2329 
/** Selects 2x oversampling for 720p and 1080i */
2330 
# define TV_OVERSAMPLE_2X		(1 << 18)
2331 
/** Selects no oversampling for 1080p */
2332 
# define TV_OVERSAMPLE_NONE		(2 << 18)
2333 
/** Selects 8x oversampling */
2334 
# define TV_OVERSAMPLE_8X		(3 << 18)
2335 
/** Selects progressive mode rather than interlaced */
2336 
# define TV_PROGRESSIVE			(1 << 17)
2337 
/** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
2338 
# define TV_PAL_BURST			(1 << 16)
2339 
/** Field for setting delay of Y compared to C */
2340 
# define TV_YC_SKEW_MASK		(7 << 12)
2341 
/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2342 
# define TV_ENC_SDP_FIX			(1 << 11)
2343 
/**
2344 
 * Enables a fix for the 915GM only.
2345 
 *
2346 
 * Not sure what it does.
2347 
 */
2348 
# define TV_ENC_C0_FIX			(1 << 10)
2349 
/** Bits that must be preserved by software */
2350 
# define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2351 
# define TV_FUSE_STATE_MASK		(3 << 4)
2352 
/** Read-only state that reports all features enabled */
2353 
# define TV_FUSE_STATE_ENABLED		(0 << 4)
2354 
/** Read-only state that reports that Macrovision is disabled in hardware*/
2355 
# define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
2356 
/** Read-only state that reports that TV-out is disabled in hardware. */
2357 
# define TV_FUSE_STATE_DISABLED		(2 << 4)
2358 
/** Normal operation */
2359 
# define TV_TEST_MODE_NORMAL		(0 << 0)
2360 
/** Encoder test pattern 1 - combo pattern */
2361 
# define TV_TEST_MODE_PATTERN_1		(1 << 0)
2362 
/** Encoder test pattern 2 - full screen vertical 75% color bars */
2363 
# define TV_TEST_MODE_PATTERN_2		(2 << 0)
2364 
/** Encoder test pattern 3 - full screen horizontal 75% color bars */
2365 
# define TV_TEST_MODE_PATTERN_3		(3 << 0)
2366 
/** Encoder test pattern 4 - random noise */
2367 
# define TV_TEST_MODE_PATTERN_4		(4 << 0)
2368 
/** Encoder test pattern 5 - linear color ramps */
2369 
# define TV_TEST_MODE_PATTERN_5		(5 << 0)
2370 
/**
2371 
 * This test mode forces the DACs to 50% of full output.
2372 
 *
2373 
 * This is used for load detection in combination with TVDAC_SENSE_MASK
2374 
 */
2375 
# define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
2376 
# define TV_TEST_MODE_MASK		(7 << 0)
2377 
 
2378 
#define TV_DAC			0x68004
2379 
# define TV_DAC_SAVE		0x00ffff00
2380 
/**
2381 
 * Reports that DAC state change logic has reported change (RO).
2382 
 *
2383 
 * This gets cleared when TV_DAC_STATE_EN is cleared
2384 
*/
2385 
# define TVDAC_STATE_CHG		(1 << 31)
2386 
# define TVDAC_SENSE_MASK		(7 << 28)
2387 
/** Reports that DAC A voltage is above the detect threshold */
2388 
# define TVDAC_A_SENSE			(1 << 30)
2389 
/** Reports that DAC B voltage is above the detect threshold */
2390 
# define TVDAC_B_SENSE			(1 << 29)
2391 
/** Reports that DAC C voltage is above the detect threshold */
2392 
# define TVDAC_C_SENSE			(1 << 28)
2393 
/**
2394 
 * Enables DAC state detection logic, for load-based TV detection.
2395 
 *
2396 
 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2397 
 * to off, for load detection to work.
2398 
 */
2399 
# define TVDAC_STATE_CHG_EN		(1 << 27)
2400 
/** Sets the DAC A sense value to high */
2401 
# define TVDAC_A_SENSE_CTL		(1 << 26)
2402 
/** Sets the DAC B sense value to high */
2403 
# define TVDAC_B_SENSE_CTL		(1 << 25)
2404 
/** Sets the DAC C sense value to high */
2405 
# define TVDAC_C_SENSE_CTL		(1 << 24)
2406 
/** Overrides the ENC_ENABLE and DAC voltage levels */
2407 
# define DAC_CTL_OVERRIDE		(1 << 7)
2408 
/** Sets the slew rate.  Must be preserved in software */
2409 
# define ENC_TVDAC_SLEW_FAST		(1 << 6)
2410 
# define DAC_A_1_3_V			(0 << 4)
2411 
# define DAC_A_1_1_V			(1 << 4)
2412 
# define DAC_A_0_7_V			(2 << 4)
2413 
# define DAC_A_MASK			(3 << 4)
2414 
# define DAC_B_1_3_V			(0 << 2)
2415 
# define DAC_B_1_1_V			(1 << 2)
2416 
# define DAC_B_0_7_V			(2 << 2)
2417 
# define DAC_B_MASK			(3 << 2)
2418 
# define DAC_C_1_3_V			(0 << 0)
2419 
# define DAC_C_1_1_V			(1 << 0)
2420 
# define DAC_C_0_7_V			(2 << 0)
2421 
# define DAC_C_MASK			(3 << 0)
2422 
 
2423 
/**
2424 
 * CSC coefficients are stored in a floating point format with 9 bits of
2425 
 * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
2426 
 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2427 
 * -1 (0x3) being the only legal negative value.
2428 
 */
2429 
#define TV_CSC_Y		0x68010
2430 
# define TV_RY_MASK			0x07ff0000
2431 
# define TV_RY_SHIFT			16
2432 
# define TV_GY_MASK			0x00000fff
2433 
# define TV_GY_SHIFT			0
2434 
 
2435 
#define TV_CSC_Y2		0x68014
2436 
# define TV_BY_MASK			0x07ff0000
2437 
# define TV_BY_SHIFT			16
2438 
/**
2439 
 * Y attenuation for component video.
2440 
 *
2441 
 * Stored in 1.9 fixed point.
2442 
 */
2443 
# define TV_AY_MASK			0x000003ff
2444 
# define TV_AY_SHIFT			0
2445 
 
2446 
#define TV_CSC_U		0x68018
2447 
# define TV_RU_MASK			0x07ff0000
2448 
# define TV_RU_SHIFT			16
2449 
# define TV_GU_MASK			0x000007ff
2450 
# define TV_GU_SHIFT			0
2451 
 
2452 
#define TV_CSC_U2		0x6801c
2453 
# define TV_BU_MASK			0x07ff0000
2454 
# define TV_BU_SHIFT			16
2455 
/**
2456 
 * U attenuation for component video.
2457 
 *
2458 
 * Stored in 1.9 fixed point.
2459 
 */
2460 
# define TV_AU_MASK			0x000003ff
2461 
# define TV_AU_SHIFT			0
2462 
 
2463 
#define TV_CSC_V		0x68020
2464 
# define TV_RV_MASK			0x0fff0000
2465 
# define TV_RV_SHIFT			16
2466 
# define TV_GV_MASK			0x000007ff
2467 
# define TV_GV_SHIFT			0
2468 
 
2469 
#define TV_CSC_V2		0x68024
2470 
# define TV_BV_MASK			0x07ff0000
2471 
# define TV_BV_SHIFT			16
2472 
/**
2473 
 * V attenuation for component video.
2474 
 *
2475 
 * Stored in 1.9 fixed point.
2476 
 */
2477 
# define TV_AV_MASK			0x000007ff
2478 
# define TV_AV_SHIFT			0
2479 
 
2480 
#define TV_CLR_KNOBS		0x68028
2481 
/** 2s-complement brightness adjustment */
2482 
# define TV_BRIGHTNESS_MASK		0xff000000
2483 
# define TV_BRIGHTNESS_SHIFT		24
2484 
/** Contrast adjustment, as a 2.6 unsigned floating point number */
2485 
# define TV_CONTRAST_MASK		0x00ff0000
2486 
# define TV_CONTRAST_SHIFT		16
2487 
/** Saturation adjustment, as a 2.6 unsigned floating point number */
2488 
# define TV_SATURATION_MASK		0x0000ff00
2489 
# define TV_SATURATION_SHIFT		8
2490 
/** Hue adjustment, as an integer phase angle in degrees */
2491 
# define TV_HUE_MASK			0x000000ff
2492 
# define TV_HUE_SHIFT			0
2493 
 
2494 
#define TV_CLR_LEVEL		0x6802c
2495 
/** Controls the DAC level for black */
2496 
# define TV_BLACK_LEVEL_MASK		0x01ff0000
2497 
# define TV_BLACK_LEVEL_SHIFT		16
2498 
/** Controls the DAC level for blanking */
2499 
# define TV_BLANK_LEVEL_MASK		0x000001ff
2500 
# define TV_BLANK_LEVEL_SHIFT		0
2501 
 
2502 
#define TV_H_CTL_1		0x68030
2503 
/** Number of pixels in the hsync. */
2504 
# define TV_HSYNC_END_MASK		0x1fff0000
2505 
# define TV_HSYNC_END_SHIFT		16
2506 
/** Total number of pixels minus one in the line (display and blanking). */
2507 
# define TV_HTOTAL_MASK			0x00001fff
2508 
# define TV_HTOTAL_SHIFT		0
2509 
 
2510 
#define TV_H_CTL_2		0x68034
2511 
/** Enables the colorburst (needed for non-component color) */
2512 
# define TV_BURST_ENA			(1 << 31)
2513 
/** Offset of the colorburst from the start of hsync, in pixels minus one. */
2514 
# define TV_HBURST_START_SHIFT		16
2515 
# define TV_HBURST_START_MASK		0x1fff0000
2516 
/** Length of the colorburst */
2517 
# define TV_HBURST_LEN_SHIFT		0
2518 
# define TV_HBURST_LEN_MASK		0x0001fff
2519 
 
2520 
#define TV_H_CTL_3		0x68038
2521 
/** End of hblank, measured in pixels minus one from start of hsync */
2522 
# define TV_HBLANK_END_SHIFT		16
2523 
# define TV_HBLANK_END_MASK		0x1fff0000
2524 
/** Start of hblank, measured in pixels minus one from start of hsync */
2525 
# define TV_HBLANK_START_SHIFT		0
2526 
# define TV_HBLANK_START_MASK		0x0001fff
2527 
 
2528 
#define TV_V_CTL_1		0x6803c
2529 
/** XXX */
2530 
# define TV_NBR_END_SHIFT		16
2531 
# define TV_NBR_END_MASK		0x07ff0000
2532 
/** XXX */
2533 
# define TV_VI_END_F1_SHIFT		8
2534 
# define TV_VI_END_F1_MASK		0x00003f00
2535 
/** XXX */
2536 
# define TV_VI_END_F2_SHIFT		0
2537 
# define TV_VI_END_F2_MASK		0x0000003f
2538 
 
2539 
#define TV_V_CTL_2		0x68040
2540 
/** Length of vsync, in half lines */
2541 
# define TV_VSYNC_LEN_MASK		0x07ff0000
2542 
# define TV_VSYNC_LEN_SHIFT		16
2543 
/** Offset of the start of vsync in field 1, measured in one less than the
2544 
 * number of half lines.
2545 
 */
2546 
# define TV_VSYNC_START_F1_MASK		0x00007f00
2547 
# define TV_VSYNC_START_F1_SHIFT	8
2548 
/**
2549 
 * Offset of the start of vsync in field 2, measured in one less than the
2550 
 * number of half lines.
2551 
 */
2552 
# define TV_VSYNC_START_F2_MASK		0x0000007f
2553 
# define TV_VSYNC_START_F2_SHIFT	0
2554 
 
2555 
#define TV_V_CTL_3		0x68044
2556 
/** Enables generation of the equalization signal */
2557 
# define TV_EQUAL_ENA			(1 << 31)
2558 
/** Length of vsync, in half lines */
2559 
# define TV_VEQ_LEN_MASK		0x007f0000
2560 
# define TV_VEQ_LEN_SHIFT		16
2561 
/** Offset of the start of equalization in field 1, measured in one less than
2562 
 * the number of half lines.
2563 
 */
2564 
# define TV_VEQ_START_F1_MASK		0x0007f00
2565 
# define TV_VEQ_START_F1_SHIFT		8
2566 
/**
2567 
 * Offset of the start of equalization in field 2, measured in one less than
2568 
 * the number of half lines.
2569 
 */
2570 
# define TV_VEQ_START_F2_MASK		0x000007f
2571 
# define TV_VEQ_START_F2_SHIFT		0
2572 
 
2573 
#define TV_V_CTL_4		0x68048
2574 
/**
2575 
 * Offset to start of vertical colorburst, measured in one less than the
2576 
 * number of lines from vertical start.
2577 
 */
2578 
# define TV_VBURST_START_F1_MASK	0x003f0000
2579 
# define TV_VBURST_START_F1_SHIFT	16
2580 
/**
2581 
 * Offset to the end of vertical colorburst, measured in one less than the
2582 
 * number of lines from the start of NBR.
2583 
 */
2584 
# define TV_VBURST_END_F1_MASK		0x000000ff
2585 
# define TV_VBURST_END_F1_SHIFT		0
2586 
 
2587 
#define TV_V_CTL_5		0x6804c
2588 
/**
2589 
 * Offset to start of vertical colorburst, measured in one less than the
2590 
 * number of lines from vertical start.
2591 
 */
2592 
# define TV_VBURST_START_F2_MASK	0x003f0000
2593 
# define TV_VBURST_START_F2_SHIFT	16
2594 
/**
2595 
 * Offset to the end of vertical colorburst, measured in one less than the
2596 
 * number of lines from the start of NBR.
2597 
 */
2598 
# define TV_VBURST_END_F2_MASK		0x000000ff
2599 
# define TV_VBURST_END_F2_SHIFT		0
2600 
 
2601 
#define TV_V_CTL_6		0x68050
2602 
/**
2603 
 * Offset to start of vertical colorburst, measured in one less than the
2604 
 * number of lines from vertical start.
2605 
 */
2606 
# define TV_VBURST_START_F3_MASK	0x003f0000
2607 
# define TV_VBURST_START_F3_SHIFT	16
2608 
/**
2609 
 * Offset to the end of vertical colorburst, measured in one less than the
2610 
 * number of lines from the start of NBR.
2611 
 */
2612 
# define TV_VBURST_END_F3_MASK		0x000000ff
2613 
# define TV_VBURST_END_F3_SHIFT		0
2614 
 
2615 
#define TV_V_CTL_7		0x68054
2616 
/**
2617 
 * Offset to start of vertical colorburst, measured in one less than the
2618 
 * number of lines from vertical start.
2619 
 */
2620 
# define TV_VBURST_START_F4_MASK	0x003f0000
2621 
# define TV_VBURST_START_F4_SHIFT	16
2622 
/**
2623 
 * Offset to the end of vertical colorburst, measured in one less than the
2624 
 * number of lines from the start of NBR.
2625 
 */
2626 
# define TV_VBURST_END_F4_MASK		0x000000ff
2627 
# define TV_VBURST_END_F4_SHIFT		0
2628 
 
2629 
#define TV_SC_CTL_1		0x68060
2630 
/** Turns on the first subcarrier phase generation DDA */
2631 
# define TV_SC_DDA1_EN			(1 << 31)
2632 
/** Turns on the first subcarrier phase generation DDA */
2633 
# define TV_SC_DDA2_EN			(1 << 30)
2634 
/** Turns on the first subcarrier phase generation DDA */
2635 
# define TV_SC_DDA3_EN			(1 << 29)
2636 
/** Sets the subcarrier DDA to reset frequency every other field */
2637 
# define TV_SC_RESET_EVERY_2		(0 << 24)
2638 
/** Sets the subcarrier DDA to reset frequency every fourth field */
2639 
# define TV_SC_RESET_EVERY_4		(1 << 24)
2640 
/** Sets the subcarrier DDA to reset frequency every eighth field */
2641 
# define TV_SC_RESET_EVERY_8		(2 << 24)
2642 
/** Sets the subcarrier DDA to never reset the frequency */
2643 
# define TV_SC_RESET_NEVER		(3 << 24)
2644 
/** Sets the peak amplitude of the colorburst.*/
2645 
# define TV_BURST_LEVEL_MASK		0x00ff0000
2646 
# define TV_BURST_LEVEL_SHIFT		16
2647 
/** Sets the increment of the first subcarrier phase generation DDA */
2648 
# define TV_SCDDA1_INC_MASK		0x00000fff
2649 
# define TV_SCDDA1_INC_SHIFT		0
2650 
 
2651 
#define TV_SC_CTL_2		0x68064
2652 
/** Sets the rollover for the second subcarrier phase generation DDA */
2653 
# define TV_SCDDA2_SIZE_MASK		0x7fff0000
2654 
# define TV_SCDDA2_SIZE_SHIFT		16
2655 
/** Sets the increent of the second subcarrier phase generation DDA */
2656 
# define TV_SCDDA2_INC_MASK		0x00007fff
2657 
# define TV_SCDDA2_INC_SHIFT		0
2658 
 
2659 
#define TV_SC_CTL_3		0x68068
2660 
/** Sets the rollover for the third subcarrier phase generation DDA */
2661 
# define TV_SCDDA3_SIZE_MASK		0x7fff0000
2662 
# define TV_SCDDA3_SIZE_SHIFT		16
2663 
/** Sets the increent of the third subcarrier phase generation DDA */
2664 
# define TV_SCDDA3_INC_MASK		0x00007fff
2665 
# define TV_SCDDA3_INC_SHIFT		0
2666 
 
2667 
#define TV_WIN_POS		0x68070
2668 
/** X coordinate of the display from the start of horizontal active */
2669 
# define TV_XPOS_MASK			0x1fff0000
2670 
# define TV_XPOS_SHIFT			16
2671 
/** Y coordinate of the display from the start of vertical active (NBR) */
2672 
# define TV_YPOS_MASK			0x00000fff
2673 
# define TV_YPOS_SHIFT			0
2674 
 
2675 
#define TV_WIN_SIZE		0x68074
2676 
/** Horizontal size of the display window, measured in pixels*/
2677 
# define TV_XSIZE_MASK			0x1fff0000
2678 
# define TV_XSIZE_SHIFT			16
2679 
/**
2680 
 * Vertical size of the display window, measured in pixels.
2681 
 *
2682 
 * Must be even for interlaced modes.
2683 
 */
2684 
# define TV_YSIZE_MASK			0x00000fff
2685 
# define TV_YSIZE_SHIFT			0
2686 
 
2687 
#define TV_FILTER_CTL_1		0x68080
2688 
/**
2689 
 * Enables automatic scaling calculation.
2690 
 *
2691 
 * If set, the rest of the registers are ignored, and the calculated values can
2692 
 * be read back from the register.
2693 
 */
2694 
# define TV_AUTO_SCALE			(1 << 31)
2695 
/**
2696 
 * Disables the vertical filter.
2697 
 *
2698 
 * This is required on modes more than 1024 pixels wide */
2699 
# define TV_V_FILTER_BYPASS		(1 << 29)
2700 
/** Enables adaptive vertical filtering */
2701 
# define TV_VADAPT			(1 << 28)
2702 
# define TV_VADAPT_MODE_MASK		(3 << 26)
2703 
/** Selects the least adaptive vertical filtering mode */
2704 
# define TV_VADAPT_MODE_LEAST		(0 << 26)
2705 
/** Selects the moderately adaptive vertical filtering mode */
2706 
# define TV_VADAPT_MODE_MODERATE	(1 << 26)
2707 
/** Selects the most adaptive vertical filtering mode */
2708 
# define TV_VADAPT_MODE_MOST		(3 << 26)
2709 
/**
2710 
 * Sets the horizontal scaling factor.
2711 
 *
2712 
 * This should be the fractional part of the horizontal scaling factor divided
2713 
 * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
2714 
 *
2715 
 * (src width - 1) / ((oversample * dest width) - 1)
2716 
 */
2717 
# define TV_HSCALE_FRAC_MASK		0x00003fff
2718 
# define TV_HSCALE_FRAC_SHIFT		0
2719 
 
2720 
#define TV_FILTER_CTL_2		0x68084
2721 
/**
2722 
 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2723 
 *
2724 
 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2725 
 */
2726 
# define TV_VSCALE_INT_MASK		0x00038000
2727 
# define TV_VSCALE_INT_SHIFT		15
2728 
/**
2729 
 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2730 
 *
2731 
 * \sa TV_VSCALE_INT_MASK
2732 
 */
2733 
# define TV_VSCALE_FRAC_MASK		0x00007fff
2734 
# define TV_VSCALE_FRAC_SHIFT		0
2735 
 
2736 
#define TV_FILTER_CTL_3		0x68088
2737 
/**
2738 
 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2739 
 *
2740 
 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2741 
 *
2742 
 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2743 
 */
2744 
# define TV_VSCALE_IP_INT_MASK		0x00038000
2745 
# define TV_VSCALE_IP_INT_SHIFT		15
2746 
/**
2747 
 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2748 
 *
2749 
 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2750 
 *
2751 
 * \sa TV_VSCALE_IP_INT_MASK
2752 
 */
2753 
# define TV_VSCALE_IP_FRAC_MASK		0x00007fff
2754 
# define TV_VSCALE_IP_FRAC_SHIFT		0
2755 
 
2756 
#define TV_CC_CONTROL		0x68090
2757 
# define TV_CC_ENABLE			(1 << 31)
2758 
/**
2759 
 * Specifies which field to send the CC data in.
2760 
 *
2761 
 * CC data is usually sent in field 0.
2762 
 */
2763 
# define TV_CC_FID_MASK			(1 << 27)
2764 
# define TV_CC_FID_SHIFT		27
2765 
/** Sets the horizontal position of the CC data.  Usually 135. */
2766 
# define TV_CC_HOFF_MASK		0x03ff0000
2767 
# define TV_CC_HOFF_SHIFT		16
2768 
/** Sets the vertical position of the CC data.  Usually 21 */
2769 
# define TV_CC_LINE_MASK		0x0000003f
2770 
# define TV_CC_LINE_SHIFT		0
2771 
 
2772 
#define TV_CC_DATA		0x68094
2773 
# define TV_CC_RDY			(1 << 31)
2774 
/** Second word of CC data to be transmitted. */
2775 
# define TV_CC_DATA_2_MASK		0x007f0000
2776 
# define TV_CC_DATA_2_SHIFT		16
2777 
/** First word of CC data to be transmitted. */
2778 
# define TV_CC_DATA_1_MASK		0x0000007f
2779 
# define TV_CC_DATA_1_SHIFT		0
2780 
 
2781 
#define TV_H_LUMA_0		0x68100
2782 
#define TV_H_LUMA_59		0x681ec
2783 
#define TV_H_CHROMA_0		0x68200
2784 
#define TV_H_CHROMA_59		0x682ec
2785 
#define TV_V_LUMA_0		0x68300
2786 
#define TV_V_LUMA_42		0x683a8
2787 
#define TV_V_CHROMA_0		0x68400
2788 
#define TV_V_CHROMA_42		0x684a8
2789 
 
2790 
/* Display Port */
2791 
#define DP_A				0x64000 /* eDP */
2792 
#define DP_B				0x64100
2793 
#define DP_C				0x64200
2794 
#define DP_D				0x64300
2795 
 
2796 
#define   DP_PORT_EN			(1 << 31)
2797 
#define   DP_PIPEB_SELECT		(1 << 30)
2798 
#define   DP_PIPE_MASK			(1 << 30)
2799 
 
2800 
/* Link training mode - select a suitable mode for each stage */
2801 
#define   DP_LINK_TRAIN_PAT_1		(0 << 28)
2802 
#define   DP_LINK_TRAIN_PAT_2		(1 << 28)
2803 
#define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
2804 
#define   DP_LINK_TRAIN_OFF		(3 << 28)
2805 
#define   DP_LINK_TRAIN_MASK		(3 << 28)
2806 
#define   DP_LINK_TRAIN_SHIFT		28
2807 
 
2808 
/* CPT Link training mode */
2809 
#define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
2810 
#define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
2811 
#define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
2812 
#define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
2813 
#define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
2814 
#define   DP_LINK_TRAIN_SHIFT_CPT	8
2815 
 
2816 
/* Signal voltages. These are mostly controlled by the other end */
2817 
#define   DP_VOLTAGE_0_4		(0 << 25)
2818 
#define   DP_VOLTAGE_0_6		(1 << 25)
2819 
#define   DP_VOLTAGE_0_8		(2 << 25)
2820 
#define   DP_VOLTAGE_1_2		(3 << 25)
2821 
#define   DP_VOLTAGE_MASK		(7 << 25)
2822 
#define   DP_VOLTAGE_SHIFT		25
2823 
 
2824 
/* Signal pre-emphasis levels, like voltages, the other end tells us what
2825 
 * they want
2826 
 */
2827 
#define   DP_PRE_EMPHASIS_0		(0 << 22)
2828 
#define   DP_PRE_EMPHASIS_3_5		(1 << 22)
2829 
#define   DP_PRE_EMPHASIS_6		(2 << 22)
2830 
#define   DP_PRE_EMPHASIS_9_5		(3 << 22)
2831 
#define   DP_PRE_EMPHASIS_MASK		(7 << 22)
2832 
#define   DP_PRE_EMPHASIS_SHIFT		22
2833 
 
2834 
/* How many wires to use. I guess 3 was too hard */
4104 Serge 2835 
#define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
2325 Serge 2836 
#define   DP_PORT_WIDTH_MASK		(7 << 19)
2837 
 
2838 
/* Mystic DPCD version 1.1 special mode */
2839 
#define   DP_ENHANCED_FRAMING		(1 << 18)
2840 
 
2841 
/* eDP */
2842 
#define   DP_PLL_FREQ_270MHZ		(0 << 16)
2843 
#define   DP_PLL_FREQ_160MHZ		(1 << 16)
2844 
#define   DP_PLL_FREQ_MASK		(3 << 16)
2845 
 
2846 
/** locked once port is enabled */
2847 
#define   DP_PORT_REVERSAL		(1 << 15)
2848 
 
2849 
/* eDP */
2850 
#define   DP_PLL_ENABLE			(1 << 14)
2851 
 
2852 
/** sends the clock on lane 15 of the PEG for debug */
2853 
#define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
2854 
 
2855 
#define   DP_SCRAMBLING_DISABLE		(1 << 12)
2856 
#define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
2857 
 
2858 
/** limit RGB values to avoid confusing TVs */
2859 
#define   DP_COLOR_RANGE_16_235		(1 << 8)
2860 
 
2861 
/** Turn on the audio link */
2862 
#define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
2863 
 
2864 
/** vs and hs sync polarity */
2865 
#define   DP_SYNC_VS_HIGH		(1 << 4)
2866 
#define   DP_SYNC_HS_HIGH		(1 << 3)
2867 
 
2868 
/** A fantasy */
2869 
#define   DP_DETECTED			(1 << 2)
2870 
 
2871 
/** The aux channel provides a way to talk to the
2872 
 * signal sink for DDC etc. Max packet size supported
2873 
 * is 20 bytes in each direction, hence the 5 fixed
2874 
 * data registers
2875 
 */
2876 
#define DPA_AUX_CH_CTL			0x64010
2877 
#define DPA_AUX_CH_DATA1		0x64014
2878 
#define DPA_AUX_CH_DATA2		0x64018
2879 
#define DPA_AUX_CH_DATA3		0x6401c
2880 
#define DPA_AUX_CH_DATA4		0x64020
2881 
#define DPA_AUX_CH_DATA5		0x64024
2882 
 
2883 
#define DPB_AUX_CH_CTL			0x64110
2884 
#define DPB_AUX_CH_DATA1		0x64114
2885 
#define DPB_AUX_CH_DATA2		0x64118
2886 
#define DPB_AUX_CH_DATA3		0x6411c
2887 
#define DPB_AUX_CH_DATA4		0x64120
2888 
#define DPB_AUX_CH_DATA5		0x64124
2889 
 
2890 
#define DPC_AUX_CH_CTL			0x64210
2891 
#define DPC_AUX_CH_DATA1		0x64214
2892 
#define DPC_AUX_CH_DATA2		0x64218
2893 
#define DPC_AUX_CH_DATA3		0x6421c
2894 
#define DPC_AUX_CH_DATA4		0x64220
2895 
#define DPC_AUX_CH_DATA5		0x64224
2896 
 
2897 
#define DPD_AUX_CH_CTL			0x64310
2898 
#define DPD_AUX_CH_DATA1		0x64314
2899 
#define DPD_AUX_CH_DATA2		0x64318
2900 
#define DPD_AUX_CH_DATA3		0x6431c
2901 
#define DPD_AUX_CH_DATA4		0x64320
2902 
#define DPD_AUX_CH_DATA5		0x64324
2903 
 
2904 
#define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
2905 
#define   DP_AUX_CH_CTL_DONE		    (1 << 30)
2906 
#define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
2907 
#define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
2908 
#define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
2909 
#define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
2910 
#define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
2911 
#define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
2912 
#define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
2913 
#define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
2914 
#define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
2915 
#define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
2916 
#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
2917 
#define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
2918 
#define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
2919 
#define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
2920 
#define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
2921 
#define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
2922 
#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
2923 
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
2924 
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
2925 
 
2926 
/*
2927 
 * Computing GMCH M and N values for the Display Port link
2928 
 *
2929 
 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2930 
 *
2931 
 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2932 
 *
2933 
 * The GMCH value is used internally
2934 
 *
2935 
 * bytes_per_pixel is the number of bytes coming out of the plane,
2936 
 * which is after the LUTs, so we want the bytes for our color format.
2937 
 * For our current usage, this is always 3, one byte for R, G and B.
2938 
 */
4104 Serge 2939 
#define _PIPEA_DATA_M_G4X	0x70050
2940 
#define _PIPEB_DATA_M_G4X	0x71050
2325 Serge 2941 
 
2942 
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3746 Serge 2943 
#define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
4104 Serge 2944 
#define  TU_SIZE_SHIFT		25
3746 Serge 2945 
#define  TU_SIZE_MASK           (0x3f << 25)
2325 Serge 2946 
 
3746 Serge 2947 
#define  DATA_LINK_M_N_MASK	(0xffffff)
2948 
#define  DATA_LINK_N_MAX	(0x800000)
2325 Serge 2949 
 
4104 Serge 2950 
#define _PIPEA_DATA_N_G4X	0x70054
2951 
#define _PIPEB_DATA_N_G4X	0x71054
2952 
#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
2325 Serge 2953 
 
2954 
/*
2955 
 * Computing Link M and N values for the Display Port link
2956 
 *
2957 
 * Link M / N = pixel_clock / ls_clk
2958 
 *
2959 
 * (the DP spec calls pixel_clock the 'strm_clk')
2960 
 *
2961 
 * The Link value is transmitted in the Main Stream
2962 
 * Attributes and VB-ID.
2963 
 */
2964 
 
4104 Serge 2965 
#define _PIPEA_LINK_M_G4X	0x70060
2966 
#define _PIPEB_LINK_M_G4X	0x71060
2967 
#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
2325 Serge 2968 
 
4104 Serge 2969 
#define _PIPEA_LINK_N_G4X	0x70064
2970 
#define _PIPEB_LINK_N_G4X	0x71064
2971 
#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
2325 Serge 2972 
 
4104 Serge 2973 
#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
2974 
#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
2975 
#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
2976 
#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
2325 Serge 2977 
 
2978 
/* Display & cursor control */
2979 
 
2980 
/* Pipe A */
3480 Serge 2981 
#define _PIPEADSL		(dev_priv->info->display_mmio_offset + 0x70000)
3031 serge 2982 
#define   DSL_LINEMASK_GEN2	0x00000fff
2983 
#define   DSL_LINEMASK_GEN3	0x00001fff
3480 Serge 2984 
#define _PIPEACONF		(dev_priv->info->display_mmio_offset + 0x70008)
2325 Serge 2985 
#define   PIPECONF_ENABLE	(1<<31)
2986 
#define   PIPECONF_DISABLE	0
2987 
#define   PIPECONF_DOUBLE_WIDE	(1<<30)
2988 
#define   I965_PIPECONF_ACTIVE	(1<<30)
3031 serge 2989 
#define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2325 Serge 2990 
#define   PIPECONF_SINGLE_WIDE	0
2991 
#define   PIPECONF_PIPE_UNLOCKED 0
2992 
#define   PIPECONF_PIPE_LOCKED	(1<<25)
2993 
#define   PIPECONF_PALETTE	0
2994 
#define   PIPECONF_GAMMA		(1<<24)
2995 
#define   PIPECONF_FORCE_BORDER	(1<<25)
3031 serge 2996 
#define   PIPECONF_INTERLACE_MASK	(7 << 21)
3243 Serge 2997 
#define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
3031 serge 2998 
/* Note that pre-gen3 does not support interlaced display directly. Panel
2999 
 * fitting must be disabled on pre-ilk for interlaced. */
2325 Serge 3000 
#define   PIPECONF_PROGRESSIVE	(0 << 21)
3031 serge 3001 
#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
3002 
#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
2325 Serge 3003 
#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
3031 serge 3004 
#define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
3005 
/* Ironlake and later have a complete new set of values for interlaced. PFIT
3006 
 * means panel fitter required, PF means progressive fetch, DBL means power
3007 
 * saving pixel doubling. */
3008 
#define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
3009 
#define   PIPECONF_INTERLACED_ILK		(3 << 21)
3010 
#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
3011 
#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
4104 Serge 3012 
#define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
2325 Serge 3013 
#define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
3480 Serge 3014 
#define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
3015 
#define   PIPECONF_BPC_MASK	(0x7 << 5)
3016 
#define   PIPECONF_8BPC		(0<<5)
3017 
#define   PIPECONF_10BPC	(1<<5)
3018 
#define   PIPECONF_6BPC		(2<<5)
3019 
#define   PIPECONF_12BPC	(3<<5)
2325 Serge 3020 
#define   PIPECONF_DITHER_EN	(1<<4)
3021 
#define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3022 
#define   PIPECONF_DITHER_TYPE_SP (0<<2)
3023 
#define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
3024 
#define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
3025 
#define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
3480 Serge 3026 
#define _PIPEASTAT		(dev_priv->info->display_mmio_offset + 0x70024)
2325 Serge 3027 
#define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
3031 serge 3028 
#define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
2325 Serge 3029 
#define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
3030 
#define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
3031 
#define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
3031 serge 3032 
#define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
2325 Serge 3033 
#define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
3034 
#define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
3035 
#define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
3036 
#define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
3480 Serge 3037 
#define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<22)
2325 Serge 3038 
#define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
3039 
#define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
3040 
#define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
3041 
#define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
3042 
#define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
3043 
#define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
3031 serge 3044 
#define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
2325 Serge 3045 
#define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
3031 serge 3046 
#define   SPRITE1_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
3480 Serge 3047 
#define   SPRITE0_FLIPDONE_INT_STATUS_VLV	(1UL<<14)
2325 Serge 3048 
#define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
3049 
#define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
3050 
#define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
3031 serge 3051 
#define   PLANE_FLIPDONE_INT_STATUS_VLV		(1UL<<10)
2325 Serge 3052 
#define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
3053 
#define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
3054 
#define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
3055 
#define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
3056 
#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
3057 
#define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
3058 
#define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
3059 
#define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
3060 
#define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
3061 
#define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
3062 
#define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
3063 
 
3064 
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
3243 Serge 3065 
#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
2325 Serge 3066 
#define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
3067 
#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
3068 
#define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
3069 
#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
3070 
 
3480 Serge 3071 
#define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
3031 serge 3072 
#define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
3073 
#define   PIPEB_HLINE_INT_EN			(1<<28)
3074 
#define   PIPEB_VBLANK_INT_EN			(1<<27)
3075 
#define   SPRITED_FLIPDONE_INT_EN		(1<<26)
3076 
#define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
3077 
#define   PLANEB_FLIPDONE_INT_EN		(1<<24)
3078 
#define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
3079 
#define   PIPEA_HLINE_INT_EN			(1<<20)
3080 
#define   PIPEA_VBLANK_INT_EN			(1<<19)
3081 
#define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
3082 
#define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
3083 
#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
3084 
 
3480 Serge 3085 
#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
3031 serge 3086 
#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
3087 
#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
3088 
#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
3089 
#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
3090 
#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
3091 
#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
3092 
#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
3093 
#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
3094 
#define   DPINVGTT_EN_MASK			0xff0000
3095 
#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
3096 
#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
3097 
#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
3098 
#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
3099 
#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
3100 
#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
3101 
#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
3102 
#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
3103 
#define   DPINVGTT_STATUS_MASK			0xff
3104 
 
2325 Serge 3105 
#define DSPARB			0x70030
3106 
#define   DSPARB_CSTART_MASK	(0x7f << 7)
3107 
#define   DSPARB_CSTART_SHIFT	7
3108 
#define   DSPARB_BSTART_MASK	(0x7f)
3109 
#define   DSPARB_BSTART_SHIFT	0
3110 
#define   DSPARB_BEND_SHIFT	9 /* on 855 */
3111 
#define   DSPARB_AEND_SHIFT	0
3112 
 
3480 Serge 3113 
#define DSPFW1			(dev_priv->info->display_mmio_offset + 0x70034)
2325 Serge 3114 
#define   DSPFW_SR_SHIFT	23
3115 
#define   DSPFW_SR_MASK 	(0x1ff<<23)
3116 
#define   DSPFW_CURSORB_SHIFT	16
3117 
#define   DSPFW_CURSORB_MASK	(0x3f<<16)
3118 
#define   DSPFW_PLANEB_SHIFT	8
3119 
#define   DSPFW_PLANEB_MASK	(0x7f<<8)
3120 
#define   DSPFW_PLANEA_MASK	(0x7f)
3480 Serge 3121 
#define DSPFW2			(dev_priv->info->display_mmio_offset + 0x70038)
2325 Serge 3122 
#define   DSPFW_CURSORA_MASK	0x00003f00
3123 
#define   DSPFW_CURSORA_SHIFT	8
3124 
#define   DSPFW_PLANEC_MASK	(0x7f)
3480 Serge 3125 
#define DSPFW3			(dev_priv->info->display_mmio_offset + 0x7003c)
2325 Serge 3126 
#define   DSPFW_HPLL_SR_EN	(1<<31)
3127 
#define   DSPFW_CURSOR_SR_SHIFT	24
3128 
#define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
3129 
#define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
3130 
#define   DSPFW_HPLL_CURSOR_SHIFT	16
3131 
#define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
3132 
#define   DSPFW_HPLL_SR_MASK		(0x1ff)
3746 Serge 3133 
#define DSPFW4			(dev_priv->info->display_mmio_offset + 0x70070)
3134 
#define DSPFW7			(dev_priv->info->display_mmio_offset + 0x7007c)
2325 Serge 3135 
 
3031 serge 3136 
/* drain latency register values*/
3137 
#define DRAIN_LATENCY_PRECISION_32	32
3138 
#define DRAIN_LATENCY_PRECISION_16	16
3480 Serge 3139 
#define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)
3031 serge 3140 
#define DDL_CURSORA_PRECISION_32	(1<<31)
3141 
#define DDL_CURSORA_PRECISION_16	(0<<31)
3142 
#define DDL_CURSORA_SHIFT		24
3143 
#define DDL_PLANEA_PRECISION_32		(1<<7)
3144 
#define DDL_PLANEA_PRECISION_16		(0<<7)
3480 Serge 3145 
#define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
3031 serge 3146 
#define DDL_CURSORB_PRECISION_32	(1<<31)
3147 
#define DDL_CURSORB_PRECISION_16	(0<<31)
3148 
#define DDL_CURSORB_SHIFT		24
3149 
#define DDL_PLANEB_PRECISION_32		(1<<7)
3150 
#define DDL_PLANEB_PRECISION_16		(0<<7)
3151 
 
2325 Serge 3152 
/* FIFO watermark sizes etc */
3153 
#define G4X_FIFO_LINE_SIZE	64
3154 
#define I915_FIFO_LINE_SIZE	64
3155 
#define I830_FIFO_LINE_SIZE	32
3156 
 
3031 serge 3157 
#define VALLEYVIEW_FIFO_SIZE	255
2325 Serge 3158 
#define G4X_FIFO_SIZE		127
3159 
#define I965_FIFO_SIZE		512
3160 
#define I945_FIFO_SIZE		127
3161 
#define I915_FIFO_SIZE		95
3162 
#define I855GM_FIFO_SIZE	127 /* In cachelines */
3163 
#define I830_FIFO_SIZE		95
3164 
 
3031 serge 3165 
#define VALLEYVIEW_MAX_WM	0xff
2325 Serge 3166 
#define G4X_MAX_WM		0x3f
3167 
#define I915_MAX_WM		0x3f
3168 
 
3169 
#define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
3170 
#define PINEVIEW_FIFO_LINE_SIZE	64
3171 
#define PINEVIEW_MAX_WM		0x1ff
3172 
#define PINEVIEW_DFT_WM		0x3f
3173 
#define PINEVIEW_DFT_HPLLOFF_WM	0
3174 
#define PINEVIEW_GUARD_WM		10
3175 
#define PINEVIEW_CURSOR_FIFO		64
3176 
#define PINEVIEW_CURSOR_MAX_WM	0x3f
3177 
#define PINEVIEW_CURSOR_DFT_WM	0
3178 
#define PINEVIEW_CURSOR_GUARD_WM	5
3179 
 
3031 serge 3180 
#define VALLEYVIEW_CURSOR_MAX_WM 64
2325 Serge 3181 
#define I965_CURSOR_FIFO	64
3182 
#define I965_CURSOR_MAX_WM	32
3183 
#define I965_CURSOR_DFT_WM	8
3184 
 
3185 
/* define the Watermark register on Ironlake */
3186 
#define WM0_PIPEA_ILK		0x45100
3187 
#define  WM0_PIPE_PLANE_MASK	(0x7f<<16)
3188 
#define  WM0_PIPE_PLANE_SHIFT	16
3189 
#define  WM0_PIPE_SPRITE_MASK	(0x3f<<8)
3190 
#define  WM0_PIPE_SPRITE_SHIFT	8
3191 
#define  WM0_PIPE_CURSOR_MASK	(0x1f)
3192 
 
3193 
#define WM0_PIPEB_ILK		0x45104
2342 Serge 3194 
#define WM0_PIPEC_IVB		0x45200
2325 Serge 3195 
#define WM1_LP_ILK		0x45108
3196 
#define  WM1_LP_SR_EN		(1<<31)
3197 
#define  WM1_LP_LATENCY_SHIFT	24
3198 
#define  WM1_LP_LATENCY_MASK	(0x7f<<24)
3199 
#define  WM1_LP_FBC_MASK	(0xf<<20)
3200 
#define  WM1_LP_FBC_SHIFT	20
3201 
#define  WM1_LP_SR_MASK		(0x1ff<<8)
3202 
#define  WM1_LP_SR_SHIFT	8
3203 
#define  WM1_LP_CURSOR_MASK	(0x3f)
3204 
#define WM2_LP_ILK		0x4510c
3205 
#define  WM2_LP_EN		(1<<31)
3206 
#define WM3_LP_ILK		0x45110
3207 
#define  WM3_LP_EN		(1<<31)
3208 
#define WM1S_LP_ILK		0x45120
2342 Serge 3209 
#define WM2S_LP_IVB		0x45124
3210 
#define WM3S_LP_IVB		0x45128
2325 Serge 3211 
#define  WM1S_LP_EN		(1<<31)
3212 
 
4104 Serge 3213 
#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3214 
	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3215 
	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3216 
 
2325 Serge 3217 
/* Memory latency timer register */
3218 
#define MLTR_ILK		0x11222
3219 
#define  MLTR_WM1_SHIFT		0
3220 
#define  MLTR_WM2_SHIFT		8
3221 
/* the unit of memory self-refresh latency time is 0.5us */
3222 
#define  ILK_SRLT_MASK		0x3f
3223 
 
3224 
/* define the fifo size on Ironlake */
3225 
#define ILK_DISPLAY_FIFO	128
3226 
#define ILK_DISPLAY_MAXWM	64
3227 
#define ILK_DISPLAY_DFTWM	8
3228 
#define ILK_CURSOR_FIFO		32
3229 
#define ILK_CURSOR_MAXWM	16
3230 
#define ILK_CURSOR_DFTWM	8
3231 
 
3232 
#define ILK_DISPLAY_SR_FIFO	512
3233 
#define ILK_DISPLAY_MAX_SRWM	0x1ff
3234 
#define ILK_DISPLAY_DFT_SRWM	0x3f
3235 
#define ILK_CURSOR_SR_FIFO	64
3236 
#define ILK_CURSOR_MAX_SRWM	0x3f
3237 
#define ILK_CURSOR_DFT_SRWM	8
3238 
 
3239 
#define ILK_FIFO_LINE_SIZE	64
3240 
 
3241 
/* define the WM info on Sandybridge */
3242 
#define SNB_DISPLAY_FIFO	128
3243 
#define SNB_DISPLAY_MAXWM	0x7f	/* bit 16:22 */
3244 
#define SNB_DISPLAY_DFTWM	8
3245 
#define SNB_CURSOR_FIFO		32
3246 
#define SNB_CURSOR_MAXWM	0x1f	/* bit 4:0 */
3247 
#define SNB_CURSOR_DFTWM	8
3248 
 
3249 
#define SNB_DISPLAY_SR_FIFO	512
3250 
#define SNB_DISPLAY_MAX_SRWM	0x1ff	/* bit 16:8 */
3251 
#define SNB_DISPLAY_DFT_SRWM	0x3f
3252 
#define SNB_CURSOR_SR_FIFO	64
3253 
#define SNB_CURSOR_MAX_SRWM	0x3f	/* bit 5:0 */
3254 
#define SNB_CURSOR_DFT_SRWM	8
3255 
 
3256 
#define SNB_FBC_MAX_SRWM	0xf	/* bit 23:20 */
3257 
 
3258 
#define SNB_FIFO_LINE_SIZE	64
3259 
 
3260 
 
3261 
/* the address where we get all kinds of latency value */
3262 
#define SSKPD			0x5d10
3263 
#define SSKPD_WM_MASK		0x3f
3264 
#define SSKPD_WM0_SHIFT		0
3265 
#define SSKPD_WM1_SHIFT		8
3266 
#define SSKPD_WM2_SHIFT		16
3267 
#define SSKPD_WM3_SHIFT		24
3268 
 
3269 
/*
3270 
 * The two pipe frame counter registers are not synchronized, so
3271 
 * reading a stable value is somewhat tricky. The following code
3272 
 * should work:
3273 
 *
3274 
 *  do {
3275 
 *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3276 
 *             PIPE_FRAME_HIGH_SHIFT;
3277 
 *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3278 
 *             PIPE_FRAME_LOW_SHIFT);
3279 
 *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3280 
 *             PIPE_FRAME_HIGH_SHIFT);
3281 
 *  } while (high1 != high2);
3282 
 *  frame = (high1 << 8) | low1;
3283 
 */
3480 Serge 3284 
#define _PIPEAFRAMEHIGH          (dev_priv->info->display_mmio_offset + 0x70040)
2325 Serge 3285 
#define   PIPE_FRAME_HIGH_MASK    0x0000ffff
3286 
#define   PIPE_FRAME_HIGH_SHIFT   0
3480 Serge 3287 
#define _PIPEAFRAMEPIXEL         (dev_priv->info->display_mmio_offset + 0x70044)
2325 Serge 3288 
#define   PIPE_FRAME_LOW_MASK     0xff000000
3289 
#define   PIPE_FRAME_LOW_SHIFT    24
3290 
#define   PIPE_PIXEL_MASK         0x00ffffff
3291 
#define   PIPE_PIXEL_SHIFT        0
3292 
/* GM45+ just has to be different */
3293 
#define _PIPEA_FRMCOUNT_GM45	0x70040
3294 
#define _PIPEA_FLIPCOUNT_GM45	0x70044
3295 
#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
3296 
 
3297 
/* Cursor A & B regs */
3480 Serge 3298 
#define _CURACNTR		(dev_priv->info->display_mmio_offset + 0x70080)
2325 Serge 3299 
/* Old style CUR*CNTR flags (desktop 8xx) */
3300 
#define   CURSOR_ENABLE		0x80000000
3301 
#define   CURSOR_GAMMA_ENABLE	0x40000000
3302 
#define   CURSOR_STRIDE_MASK	0x30000000
3480 Serge 3303 
#define   CURSOR_PIPE_CSC_ENABLE (1<<24)
2325 Serge 3304 
#define   CURSOR_FORMAT_SHIFT	24
3305 
#define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
3306 
#define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
3307 
#define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
3308 
#define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
3309 
#define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
3310 
#define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
3311 
/* New style CUR*CNTR flags */
3312 
#define   CURSOR_MODE		0x27
3313 
#define   CURSOR_MODE_DISABLE   0x00
3314 
#define   CURSOR_MODE_64_32B_AX 0x07
3315 
#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
3316 
#define   MCURSOR_PIPE_SELECT	(1 << 28)
3317 
#define   MCURSOR_PIPE_A	0x00
3318 
#define   MCURSOR_PIPE_B	(1 << 28)
3319 
#define   MCURSOR_GAMMA_ENABLE  (1 << 26)
4104 Serge 3320 
#define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
3480 Serge 3321 
#define _CURABASE		(dev_priv->info->display_mmio_offset + 0x70084)
3322 
#define _CURAPOS		(dev_priv->info->display_mmio_offset + 0x70088)
2325 Serge 3323 
#define   CURSOR_POS_MASK       0x007FF
3324 
#define   CURSOR_POS_SIGN       0x8000
3325 
#define   CURSOR_X_SHIFT        0
3326 
#define   CURSOR_Y_SHIFT        16
3327 
#define CURSIZE			0x700a0
3480 Serge 3328 
#define _CURBCNTR		(dev_priv->info->display_mmio_offset + 0x700c0)
3329 
#define _CURBBASE		(dev_priv->info->display_mmio_offset + 0x700c4)
3330 
#define _CURBPOS		(dev_priv->info->display_mmio_offset + 0x700c8)
2325 Serge 3331 
 
2342 Serge 3332 
#define _CURBCNTR_IVB		0x71080
3333 
#define _CURBBASE_IVB		0x71084
3334 
#define _CURBPOS_IVB		0x71088
3335 
 
2325 Serge 3336 
#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3337 
#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3338 
#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3339 
 
2342 Serge 3340 
#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3341 
#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3342 
#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3343 
 
2325 Serge 3344 
/* Display A control */
3480 Serge 3345 
#define _DSPACNTR                (dev_priv->info->display_mmio_offset + 0x70180)
2325 Serge 3346 
#define   DISPLAY_PLANE_ENABLE			(1<<31)
3347 
#define   DISPLAY_PLANE_DISABLE			0
3348 
#define   DISPPLANE_GAMMA_ENABLE		(1<<30)
3349 
#define   DISPPLANE_GAMMA_DISABLE		0
3350 
#define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
3243 Serge 3351 
#define   DISPPLANE_YUV422			(0x0<<26)
2325 Serge 3352 
#define   DISPPLANE_8BPP			(0x2<<26)
3243 Serge 3353 
#define   DISPPLANE_BGRA555			(0x3<<26)
3354 
#define   DISPPLANE_BGRX555			(0x4<<26)
3355 
#define   DISPPLANE_BGRX565			(0x5<<26)
3356 
#define   DISPPLANE_BGRX888			(0x6<<26)
3357 
#define   DISPPLANE_BGRA888			(0x7<<26)
3358 
#define   DISPPLANE_RGBX101010			(0x8<<26)
3359 
#define   DISPPLANE_RGBA101010			(0x9<<26)
3360 
#define   DISPPLANE_BGRX101010			(0xa<<26)
3361 
#define   DISPPLANE_RGBX161616			(0xc<<26)
3362 
#define   DISPPLANE_RGBX888			(0xe<<26)
3363 
#define   DISPPLANE_RGBA888			(0xf<<26)
2325 Serge 3364 
#define   DISPPLANE_STEREO_ENABLE		(1<<25)
3365 
#define   DISPPLANE_STEREO_DISABLE		0
3480 Serge 3366 
#define   DISPPLANE_PIPE_CSC_ENABLE		(1<<24)
2325 Serge 3367 
#define   DISPPLANE_SEL_PIPE_SHIFT		24
3368 
#define   DISPPLANE_SEL_PIPE_MASK		(3<
3369 
#define   DISPPLANE_SEL_PIPE_A			0
3370 
#define   DISPPLANE_SEL_PIPE_B			(1<
3371 
#define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
3372 
#define   DISPPLANE_SRC_KEY_DISABLE		0
3373 
#define   DISPPLANE_LINE_DOUBLE			(1<<20)
3374 
#define   DISPPLANE_NO_LINE_DOUBLE		0
3375 
#define   DISPPLANE_STEREO_POLARITY_FIRST	0
3376 
#define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
3377 
#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
3378 
#define   DISPPLANE_TILED			(1<<10)
3480 Serge 3379 
#define _DSPAADDR		(dev_priv->info->display_mmio_offset + 0x70184)
3380 
#define _DSPASTRIDE		(dev_priv->info->display_mmio_offset + 0x70188)
3381 
#define _DSPAPOS		(dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
3382 
#define _DSPASIZE		(dev_priv->info->display_mmio_offset + 0x70190)
3383 
#define _DSPASURF		(dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
3384 
#define _DSPATILEOFF		(dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
3385 
#define _DSPAOFFSET		(dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
3386 
#define _DSPASURFLIVE		(dev_priv->info->display_mmio_offset + 0x701AC)
2325 Serge 3387 
 
3388 
#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3389 
#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3390 
#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3391 
#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3392 
#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3393 
#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3394 
#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3031 serge 3395 
#define DSPLINOFF(plane) DSPADDR(plane)
3243 Serge 3396 
#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
3397 
#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
2325 Serge 3398 
 
3031 serge 3399 
/* Display/Sprite base address macros */
3400 
#define DISP_BASEADDR_MASK	(0xfffff000)
3401 
#define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
3402 
#define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
3403 
#define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3404 
		(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3405 
 
2325 Serge 3406 
/* VBIOS flags */
3480 Serge 3407 
#define SWF00			(dev_priv->info->display_mmio_offset + 0x71410)
3408 
#define SWF01			(dev_priv->info->display_mmio_offset + 0x71414)
3409 
#define SWF02			(dev_priv->info->display_mmio_offset + 0x71418)
3410 
#define SWF03			(dev_priv->info->display_mmio_offset + 0x7141c)
3411 
#define SWF04			(dev_priv->info->display_mmio_offset + 0x71420)
3412 
#define SWF05			(dev_priv->info->display_mmio_offset + 0x71424)
3413 
#define SWF06			(dev_priv->info->display_mmio_offset + 0x71428)
3414 
#define SWF10			(dev_priv->info->display_mmio_offset + 0x70410)
3415 
#define SWF11			(dev_priv->info->display_mmio_offset + 0x70414)
3416 
#define SWF14			(dev_priv->info->display_mmio_offset + 0x71420)
3417 
#define SWF30			(dev_priv->info->display_mmio_offset + 0x72414)
3418 
#define SWF31			(dev_priv->info->display_mmio_offset + 0x72418)
3419 
#define SWF32			(dev_priv->info->display_mmio_offset + 0x7241c)
2325 Serge 3420 
 
3421 
/* Pipe B */
3480 Serge 3422 
#define _PIPEBDSL		(dev_priv->info->display_mmio_offset + 0x71000)
3423 
#define _PIPEBCONF		(dev_priv->info->display_mmio_offset + 0x71008)
3424 
#define _PIPEBSTAT		(dev_priv->info->display_mmio_offset + 0x71024)
3425 
#define _PIPEBFRAMEHIGH		(dev_priv->info->display_mmio_offset + 0x71040)
3426 
#define _PIPEBFRAMEPIXEL	(dev_priv->info->display_mmio_offset + 0x71044)
2325 Serge 3427 
#define _PIPEB_FRMCOUNT_GM45	0x71040
3428 
#define _PIPEB_FLIPCOUNT_GM45	0x71044
3429 
 
3430 
 
3431 
/* Display B control */
3480 Serge 3432 
#define _DSPBCNTR		(dev_priv->info->display_mmio_offset + 0x71180)
2325 Serge 3433 
#define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
3434 
#define   DISPPLANE_ALPHA_TRANS_DISABLE		0
3435 
#define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
3436 
#define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
3480 Serge 3437 
#define _DSPBADDR		(dev_priv->info->display_mmio_offset + 0x71184)
3438 
#define _DSPBSTRIDE		(dev_priv->info->display_mmio_offset + 0x71188)
3439 
#define _DSPBPOS		(dev_priv->info->display_mmio_offset + 0x7118C)
3440 
#define _DSPBSIZE		(dev_priv->info->display_mmio_offset + 0x71190)
3441 
#define _DSPBSURF		(dev_priv->info->display_mmio_offset + 0x7119C)
3442 
#define _DSPBTILEOFF		(dev_priv->info->display_mmio_offset + 0x711A4)
3443 
#define _DSPBOFFSET		(dev_priv->info->display_mmio_offset + 0x711A4)
3444 
#define _DSPBSURFLIVE		(dev_priv->info->display_mmio_offset + 0x711AC)
2325 Serge 3445 
 
2342 Serge 3446 
/* Sprite A control */
3447 
#define _DVSACNTR		0x72180
3448 
#define   DVS_ENABLE		(1<<31)
3449 
#define   DVS_GAMMA_ENABLE	(1<<30)
3450 
#define   DVS_PIXFORMAT_MASK	(3<<25)
3451 
#define   DVS_FORMAT_YUV422	(0<<25)
3452 
#define   DVS_FORMAT_RGBX101010	(1<<25)
3453 
#define   DVS_FORMAT_RGBX888	(2<<25)
3454 
#define   DVS_FORMAT_RGBX161616	(3<<25)
3480 Serge 3455 
#define   DVS_PIPE_CSC_ENABLE   (1<<24)
2342 Serge 3456 
#define   DVS_SOURCE_KEY	(1<<22)
3031 serge 3457 
#define   DVS_RGB_ORDER_XBGR	(1<<20)
2342 Serge 3458 
#define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
3459 
#define   DVS_YUV_ORDER_YUYV	(0<<16)
3460 
#define   DVS_YUV_ORDER_UYVY	(1<<16)
3461 
#define   DVS_YUV_ORDER_YVYU	(2<<16)
3462 
#define   DVS_YUV_ORDER_VYUY	(3<<16)
3463 
#define   DVS_DEST_KEY		(1<<2)
3464 
#define   DVS_TRICKLE_FEED_DISABLE (1<<14)
3465 
#define   DVS_TILED		(1<<10)
3466 
#define _DVSALINOFF		0x72184
3467 
#define _DVSASTRIDE		0x72188
3468 
#define _DVSAPOS		0x7218c
3469 
#define _DVSASIZE		0x72190
3470 
#define _DVSAKEYVAL		0x72194
3471 
#define _DVSAKEYMSK		0x72198
3472 
#define _DVSASURF		0x7219c
3473 
#define _DVSAKEYMAXVAL		0x721a0
3474 
#define _DVSATILEOFF		0x721a4
3475 
#define _DVSASURFLIVE		0x721ac
3476 
#define _DVSASCALE		0x72204
3477 
#define   DVS_SCALE_ENABLE	(1<<31)
3478 
#define   DVS_FILTER_MASK	(3<<29)
3479 
#define   DVS_FILTER_MEDIUM	(0<<29)
3480 
#define   DVS_FILTER_ENHANCING	(1<<29)
3481 
#define   DVS_FILTER_SOFTENING	(2<<29)
3482 
#define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3483 
#define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3484 
#define _DVSAGAMC		0x72300
3485 
 
3486 
#define _DVSBCNTR		0x73180
3487 
#define _DVSBLINOFF		0x73184
3488 
#define _DVSBSTRIDE		0x73188
3489 
#define _DVSBPOS		0x7318c
3490 
#define _DVSBSIZE		0x73190
3491 
#define _DVSBKEYVAL		0x73194
3492 
#define _DVSBKEYMSK		0x73198
3493 
#define _DVSBSURF		0x7319c
3494 
#define _DVSBKEYMAXVAL		0x731a0
3495 
#define _DVSBTILEOFF		0x731a4
3496 
#define _DVSBSURFLIVE		0x731ac
3497 
#define _DVSBSCALE		0x73204
3498 
#define _DVSBGAMC		0x73300
3499 
 
3500 
#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3501 
#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3502 
#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3503 
#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3504 
#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3505 
#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3506 
#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3507 
#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3508 
#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3509 
#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3510 
#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3243 Serge 3511 
#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
2342 Serge 3512 
 
3513 
#define _SPRA_CTL		0x70280
3514 
#define   SPRITE_ENABLE			(1<<31)
3515 
#define   SPRITE_GAMMA_ENABLE		(1<<30)
3516 
#define   SPRITE_PIXFORMAT_MASK		(7<<25)
3517 
#define   SPRITE_FORMAT_YUV422		(0<<25)
3518 
#define   SPRITE_FORMAT_RGBX101010	(1<<25)
3519 
#define   SPRITE_FORMAT_RGBX888		(2<<25)
3520 
#define   SPRITE_FORMAT_RGBX161616	(3<<25)
3521 
#define   SPRITE_FORMAT_YUV444		(4<<25)
3522 
#define   SPRITE_FORMAT_XR_BGR101010	(5<<25) /* Extended range */
3480 Serge 3523 
#define   SPRITE_PIPE_CSC_ENABLE	(1<<24)
2342 Serge 3524 
#define   SPRITE_SOURCE_KEY		(1<<22)
3525 
#define   SPRITE_RGB_ORDER_RGBX		(1<<20) /* only for 888 and 161616 */
3526 
#define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1<<19)
3527 
#define   SPRITE_YUV_CSC_FORMAT_BT709	(1<<18) /* 0 is BT601 */
3528 
#define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
3529 
#define   SPRITE_YUV_ORDER_YUYV		(0<<16)
3530 
#define   SPRITE_YUV_ORDER_UYVY		(1<<16)
3531 
#define   SPRITE_YUV_ORDER_YVYU		(2<<16)
3532 
#define   SPRITE_YUV_ORDER_VYUY		(3<<16)
3533 
#define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
3534 
#define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
3535 
#define   SPRITE_TILED			(1<<10)
3536 
#define   SPRITE_DEST_KEY		(1<<2)
3537 
#define _SPRA_LINOFF		0x70284
3538 
#define _SPRA_STRIDE		0x70288
3539 
#define _SPRA_POS		0x7028c
3540 
#define _SPRA_SIZE		0x70290
3541 
#define _SPRA_KEYVAL		0x70294
3542 
#define _SPRA_KEYMSK		0x70298
3543 
#define _SPRA_SURF		0x7029c
3544 
#define _SPRA_KEYMAX		0x702a0
3545 
#define _SPRA_TILEOFF		0x702a4
3243 Serge 3546 
#define _SPRA_OFFSET		0x702a4
3547 
#define _SPRA_SURFLIVE		0x702ac
2342 Serge 3548 
#define _SPRA_SCALE		0x70304
3549 
#define   SPRITE_SCALE_ENABLE	(1<<31)
3550 
#define   SPRITE_FILTER_MASK	(3<<29)
3551 
#define   SPRITE_FILTER_MEDIUM	(0<<29)
3552 
#define   SPRITE_FILTER_ENHANCING	(1<<29)
3553 
#define   SPRITE_FILTER_SOFTENING	(2<<29)
3554 
#define   SPRITE_VERTICAL_OFFSET_HALF	(1<<28) /* must be enabled below */
3555 
#define   SPRITE_VERTICAL_OFFSET_ENABLE	(1<<27)
3556 
#define _SPRA_GAMC		0x70400
3557 
 
3558 
#define _SPRB_CTL		0x71280
3559 
#define _SPRB_LINOFF		0x71284
3560 
#define _SPRB_STRIDE		0x71288
3561 
#define _SPRB_POS		0x7128c
3562 
#define _SPRB_SIZE		0x71290
3563 
#define _SPRB_KEYVAL		0x71294
3564 
#define _SPRB_KEYMSK		0x71298
3565 
#define _SPRB_SURF		0x7129c
3566 
#define _SPRB_KEYMAX		0x712a0
3567 
#define _SPRB_TILEOFF		0x712a4
3243 Serge 3568 
#define _SPRB_OFFSET		0x712a4
3569 
#define _SPRB_SURFLIVE		0x712ac
2342 Serge 3570 
#define _SPRB_SCALE		0x71304
3571 
#define _SPRB_GAMC		0x71400
3572 
 
3573 
#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3574 
#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3575 
#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3576 
#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3577 
#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3578 
#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3579 
#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3580 
#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3581 
#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3582 
#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3243 Serge 3583 
#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
2342 Serge 3584 
#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3585 
#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3243 Serge 3586 
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
2342 Serge 3587 
 
4104 Serge 3588 
#define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
3746 Serge 3589 
#define   SP_ENABLE			(1<<31)
3590 
#define   SP_GEAMMA_ENABLE		(1<<30)
3591 
#define   SP_PIXFORMAT_MASK		(0xf<<26)
3592 
#define   SP_FORMAT_YUV422		(0<<26)
3593 
#define   SP_FORMAT_BGR565		(5<<26)
3594 
#define   SP_FORMAT_BGRX8888		(6<<26)
3595 
#define   SP_FORMAT_BGRA8888		(7<<26)
3596 
#define   SP_FORMAT_RGBX1010102		(8<<26)
3597 
#define   SP_FORMAT_RGBA1010102		(9<<26)
3598 
#define   SP_FORMAT_RGBX8888		(0xe<<26)
3599 
#define   SP_FORMAT_RGBA8888		(0xf<<26)
3600 
#define   SP_SOURCE_KEY			(1<<22)
3601 
#define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
3602 
#define   SP_YUV_ORDER_YUYV		(0<<16)
3603 
#define   SP_YUV_ORDER_UYVY		(1<<16)
3604 
#define   SP_YUV_ORDER_YVYU		(2<<16)
3605 
#define   SP_YUV_ORDER_VYUY		(3<<16)
3606 
#define   SP_TILED			(1<<10)
4104 Serge 3607 
#define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
3608 
#define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
3609 
#define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
3610 
#define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
3611 
#define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
3612 
#define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
3613 
#define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
3614 
#define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
3615 
#define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
3616 
#define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
3617 
#define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
3746 Serge 3618 
 
4104 Serge 3619 
#define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
3620 
#define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
3621 
#define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
3622 
#define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
3623 
#define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
3624 
#define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
3625 
#define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
3626 
#define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
3627 
#define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
3628 
#define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
3629 
#define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
3630 
#define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
3746 Serge 3631 
 
3632 
#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3633 
#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3634 
#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3635 
#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3636 
#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3637 
#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3638 
#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3639 
#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3640 
#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3641 
#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3642 
#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3643 
#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3644 
 
2325 Serge 3645 
/* VBIOS regs */
3646 
#define VGACNTRL		0x71400
3647 
# define VGA_DISP_DISABLE			(1 << 31)
3648 
# define VGA_2X_MODE				(1 << 30)
3649 
# define VGA_PIPE_B_SELECT			(1 << 29)
3650 
 
3480 Serge 3651 
#define VLV_VGACNTRL		(VLV_DISPLAY_BASE + 0x71400)
3652 
 
2325 Serge 3653 
/* Ironlake */
3654 
 
3655 
#define CPU_VGACNTRL	0x41000
3656 
 
3657 
#define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
3658 
#define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
3659 
#define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
3660 
#define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
3661 
#define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
3662 
#define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
3663 
#define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
3664 
#define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
3665 
#define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
3666 
 
3667 
/* refresh rate hardware control */
3668 
#define RR_HW_CTL       0x45300
3669 
#define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
3670 
#define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
3671 
 
3672 
#define FDI_PLL_BIOS_0  0x46000
3673 
#define  FDI_PLL_FB_CLOCK_MASK  0xff
3674 
#define FDI_PLL_BIOS_1  0x46004
3675 
#define FDI_PLL_BIOS_2  0x46008
3676 
#define DISPLAY_PORT_PLL_BIOS_0         0x4600c
3677 
#define DISPLAY_PORT_PLL_BIOS_1         0x46010
3678 
#define DISPLAY_PORT_PLL_BIOS_2         0x46014
3679 
 
3680 
#define PCH_3DCGDIS0		0x46020
3681 
# define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
3682 
# define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
3683 
 
3684 
#define PCH_3DCGDIS1		0x46024
3685 
# define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
3686 
 
3687 
#define FDI_PLL_FREQ_CTL        0x46030
3688 
#define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
3689 
#define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
3690 
#define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
3691 
 
3692 
 
3480 Serge 3693 
#define _PIPEA_DATA_M1           (dev_priv->info->display_mmio_offset + 0x60030)
2325 Serge 3694 
#define  PIPE_DATA_M1_OFFSET    0
3480 Serge 3695 
#define _PIPEA_DATA_N1           (dev_priv->info->display_mmio_offset + 0x60034)
2325 Serge 3696 
#define  PIPE_DATA_N1_OFFSET    0
3697 
 
3480 Serge 3698 
#define _PIPEA_DATA_M2           (dev_priv->info->display_mmio_offset + 0x60038)
2325 Serge 3699 
#define  PIPE_DATA_M2_OFFSET    0
3480 Serge 3700 
#define _PIPEA_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6003c)
2325 Serge 3701 
#define  PIPE_DATA_N2_OFFSET    0
3702 
 
3480 Serge 3703 
#define _PIPEA_LINK_M1           (dev_priv->info->display_mmio_offset + 0x60040)
2325 Serge 3704 
#define  PIPE_LINK_M1_OFFSET    0
3480 Serge 3705 
#define _PIPEA_LINK_N1           (dev_priv->info->display_mmio_offset + 0x60044)
2325 Serge 3706 
#define  PIPE_LINK_N1_OFFSET    0
3707 
 
3480 Serge 3708 
#define _PIPEA_LINK_M2           (dev_priv->info->display_mmio_offset + 0x60048)
2325 Serge 3709 
#define  PIPE_LINK_M2_OFFSET    0
3480 Serge 3710 
#define _PIPEA_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6004c)
2325 Serge 3711 
#define  PIPE_LINK_N2_OFFSET    0
3712 
 
3713 
/* PIPEB timing regs are same start from 0x61000 */
3714 
 
3480 Serge 3715 
#define _PIPEB_DATA_M1           (dev_priv->info->display_mmio_offset + 0x61030)
3716 
#define _PIPEB_DATA_N1           (dev_priv->info->display_mmio_offset + 0x61034)
2325 Serge 3717 
 
3480 Serge 3718 
#define _PIPEB_DATA_M2           (dev_priv->info->display_mmio_offset + 0x61038)
3719 
#define _PIPEB_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6103c)
2325 Serge 3720 
 
3480 Serge 3721 
#define _PIPEB_LINK_M1           (dev_priv->info->display_mmio_offset + 0x61040)
3722 
#define _PIPEB_LINK_N1           (dev_priv->info->display_mmio_offset + 0x61044)
2325 Serge 3723 
 
3480 Serge 3724 
#define _PIPEB_LINK_M2           (dev_priv->info->display_mmio_offset + 0x61048)
3725 
#define _PIPEB_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6104c)
2325 Serge 3726 
 
3243 Serge 3727 
#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3728 
#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3729 
#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3730 
#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3731 
#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3732 
#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3733 
#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3734 
#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2325 Serge 3735 
 
3736 
/* CPU panel fitter */
3737 
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3738 
#define _PFA_CTL_1               0x68080
3739 
#define _PFB_CTL_1               0x68880
3740 
#define  PF_ENABLE              (1<<31)
3243 Serge 3741 
#define  PF_PIPE_SEL_MASK_IVB	(3<<29)
3742 
#define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)
2325 Serge 3743 
#define  PF_FILTER_MASK		(3<<23)
3744 
#define  PF_FILTER_PROGRAMMED	(0<<23)
3745 
#define  PF_FILTER_MED_3x3	(1<<23)
3746 
#define  PF_FILTER_EDGE_ENHANCE	(2<<23)
3747 
#define  PF_FILTER_EDGE_SOFTEN	(3<<23)
3748 
#define _PFA_WIN_SZ		0x68074
3749 
#define _PFB_WIN_SZ		0x68874
3750 
#define _PFA_WIN_POS		0x68070
3751 
#define _PFB_WIN_POS		0x68870
3752 
#define _PFA_VSCALE		0x68084
3753 
#define _PFB_VSCALE		0x68884
3754 
#define _PFA_HSCALE		0x68090
3755 
#define _PFB_HSCALE		0x68890
3756 
 
3757 
#define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3758 
#define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3759 
#define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3760 
#define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3761 
#define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3762 
 
3763 
/* legacy palette */
3764 
#define _LGC_PALETTE_A           0x4a000
3765 
#define _LGC_PALETTE_B           0x4a800
3766 
#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3767 
 
4104 Serge 3768 
#define _GAMMA_MODE_A		0x4a480
3769 
#define _GAMMA_MODE_B		0x4ac80
3770 
#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
3771 
#define GAMMA_MODE_MODE_MASK	(3 << 0)
3772 
#define GAMMA_MODE_MODE_8BIT	(0 << 0)
3773 
#define GAMMA_MODE_MODE_10BIT	(1 << 0)
3774 
#define GAMMA_MODE_MODE_12BIT	(2 << 0)
3775 
#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
3776 
 
2325 Serge 3777 
/* interrupts */
3778 
#define DE_MASTER_IRQ_CONTROL   (1 << 31)
3779 
#define DE_SPRITEB_FLIP_DONE    (1 << 29)
3780 
#define DE_SPRITEA_FLIP_DONE    (1 << 28)
3781 
#define DE_PLANEB_FLIP_DONE     (1 << 27)
3782 
#define DE_PLANEA_FLIP_DONE     (1 << 26)
3783 
#define DE_PCU_EVENT            (1 << 25)
3784 
#define DE_GTT_FAULT            (1 << 24)
3785 
#define DE_POISON               (1 << 23)
3786 
#define DE_PERFORM_COUNTER      (1 << 22)
3787 
#define DE_PCH_EVENT            (1 << 21)
3788 
#define DE_AUX_CHANNEL_A        (1 << 20)
3789 
#define DE_DP_A_HOTPLUG         (1 << 19)
3790 
#define DE_GSE                  (1 << 18)
3791 
#define DE_PIPEB_VBLANK         (1 << 15)
3792 
#define DE_PIPEB_EVEN_FIELD     (1 << 14)
3793 
#define DE_PIPEB_ODD_FIELD      (1 << 13)
3794 
#define DE_PIPEB_LINE_COMPARE   (1 << 12)
3795 
#define DE_PIPEB_VSYNC          (1 << 11)
3796 
#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
3797 
#define DE_PIPEA_VBLANK         (1 << 7)
3798 
#define DE_PIPEA_EVEN_FIELD     (1 << 6)
3799 
#define DE_PIPEA_ODD_FIELD      (1 << 5)
3800 
#define DE_PIPEA_LINE_COMPARE   (1 << 4)
3801 
#define DE_PIPEA_VSYNC          (1 << 3)
3802 
#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
3803 
 
3804 
/* More Ivybridge lolz */
4104 Serge 3805 
#define DE_ERR_INT_IVB			(1<<30)
2325 Serge 3806 
#define DE_GSE_IVB			(1<<29)
3807 
#define DE_PCH_EVENT_IVB		(1<<28)
3808 
#define DE_DP_A_HOTPLUG_IVB		(1<<27)
3809 
#define DE_AUX_CHANNEL_A_IVB		(1<<26)
3031 serge 3810 
#define DE_SPRITEC_FLIP_DONE_IVB	(1<<14)
3811 
#define DE_PLANEC_FLIP_DONE_IVB		(1<<13)
3812 
#define DE_PIPEC_VBLANK_IVB		(1<<10)
2325 Serge 3813 
#define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
3031 serge 3814 
#define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
3815 
#define DE_PIPEB_VBLANK_IVB		(1<<5)
2325 Serge 3816 
#define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
3817 
#define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
3818 
#define DE_PIPEA_VBLANK_IVB		(1<<0)
3819 
 
4104 Serge 3820 
#define DE_PIPE_VBLANK_ILK(pipe)	(1 << ((pipe * 8) + 7))
3821 
#define DE_PIPE_VBLANK_IVB(pipe)	(1 << (pipe * 5))
3822 
 
3031 serge 3823 
#define VLV_MASTER_IER			0x4400c /* Gunit master IER */
3824 
#define   MASTER_INTERRUPT_ENABLE	(1<<31)
3825 
 
2325 Serge 3826 
#define DEISR   0x44000
3827 
#define DEIMR   0x44004
3828 
#define DEIIR   0x44008
3829 
#define DEIER   0x4400c
3830 
 
3831 
#define GTISR   0x44010
3832 
#define GTIMR   0x44014
3833 
#define GTIIR   0x44018
3834 
#define GTIER   0x4401c
3835 
 
3836 
#define ILK_DISPLAY_CHICKEN2	0x42004
3837 
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
3838 
#define  ILK_ELPIN_409_SELECT	(1 << 25)
3839 
#define  ILK_DPARB_GATE	(1<<22)
3840 
#define  ILK_VSDPFD_FULL	(1<<21)
3841 
#define ILK_DISPLAY_CHICKEN_FUSES	0x42014
3842 
#define  ILK_INTERNAL_GRAPHICS_DISABLE	(1<<31)
3843 
#define  ILK_INTERNAL_DISPLAY_DISABLE	(1<<30)
3844 
#define  ILK_DISPLAY_DEBUG_DISABLE	(1<<29)
3845 
#define  ILK_HDCP_DISABLE		(1<<25)
3846 
#define  ILK_eDP_A_DISABLE		(1<<24)
3847 
#define  ILK_DESKTOP			(1<<23)
3848 
 
3243 Serge 3849 
#define ILK_DSPCLK_GATE_D			0x42020
3850 
#define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
3851 
#define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
3852 
#define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
3853 
#define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
3854 
#define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
2325 Serge 3855 
 
2342 Serge 3856 
#define IVB_CHICKEN3	0x4200c
3857 
# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
3858 
# define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
3859 
 
4104 Serge 3860 
#define CHICKEN_PAR1_1		0x42080
3861 
#define  FORCE_ARB_IDLE_PLANES	(1 << 14)
3862 
 
2325 Serge 3863 
#define DISP_ARB_CTL	0x45000
3864 
#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
3865 
#define  DISP_FBC_WM_DIS		(1<<15)
3746 Serge 3866 
#define GEN7_MSG_CTL	0x45010
3867 
#define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
3868 
#define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
2325 Serge 3869 
 
3031 serge 3870 
/* GEN7 chicken */
3871 
#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
3872 
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
3873 
 
3874 
#define GEN7_L3CNTLREG1				0xB01C
3875 
#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
3243 Serge 3876 
#define  GEN7_L3AGDIS				(1<<19)
3031 serge 3877 
 
3878 
#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
3879 
#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
3880 
 
3243 Serge 3881 
#define GEN7_L3SQCREG4				0xb034
3882 
#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
3883 
 
3031 serge 3884 
/* WaCatErrorRejectionIssue */
3885 
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
3886 
#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
3887 
 
4104 Serge 3888 
#define HSW_SCRATCH1				0xb038
3889 
#define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
3890 
 
3243 Serge 3891 
#define HSW_FUSE_STRAP		0x42014
3892 
#define  HSW_CDCLK_LIMIT	(1 << 24)
3893 
 
2325 Serge 3894 
/* PCH */
3895 
 
3031 serge 3896 
/* south display engine interrupt: IBX */
2325 Serge 3897 
#define SDE_AUDIO_POWER_D	(1 << 27)
3898 
#define SDE_AUDIO_POWER_C	(1 << 26)
3899 
#define SDE_AUDIO_POWER_B	(1 << 25)
3900 
#define SDE_AUDIO_POWER_SHIFT	(25)
3901 
#define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
3902 
#define SDE_GMBUS		(1 << 24)
3903 
#define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
3904 
#define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
3905 
#define SDE_AUDIO_HDCP_MASK	(3 << 22)
3906 
#define SDE_AUDIO_TRANSB	(1 << 21)
3907 
#define SDE_AUDIO_TRANSA	(1 << 20)
3908 
#define SDE_AUDIO_TRANS_MASK	(3 << 20)
3909 
#define SDE_POISON		(1 << 19)
3910 
/* 18 reserved */
3911 
#define SDE_FDI_RXB		(1 << 17)
3912 
#define SDE_FDI_RXA		(1 << 16)
3913 
#define SDE_FDI_MASK		(3 << 16)
3914 
#define SDE_AUXD		(1 << 15)
3915 
#define SDE_AUXC		(1 << 14)
3916 
#define SDE_AUXB		(1 << 13)
3917 
#define SDE_AUX_MASK		(7 << 13)
3918 
/* 12 reserved */
3919 
#define SDE_CRT_HOTPLUG         (1 << 11)
3920 
#define SDE_PORTD_HOTPLUG       (1 << 10)
3921 
#define SDE_PORTC_HOTPLUG       (1 << 9)
3922 
#define SDE_PORTB_HOTPLUG       (1 << 8)
3923 
#define SDE_SDVOB_HOTPLUG       (1 << 6)
3746 Serge 3924 
#define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
3925 
				 SDE_SDVOB_HOTPLUG |	\
3926 
				 SDE_PORTB_HOTPLUG |	\
3927 
				 SDE_PORTC_HOTPLUG |	\
3928 
				 SDE_PORTD_HOTPLUG)
2325 Serge 3929 
#define SDE_TRANSB_CRC_DONE	(1 << 5)
3930 
#define SDE_TRANSB_CRC_ERR	(1 << 4)
3931 
#define SDE_TRANSB_FIFO_UNDER	(1 << 3)
3932 
#define SDE_TRANSA_CRC_DONE	(1 << 2)
3933 
#define SDE_TRANSA_CRC_ERR	(1 << 1)
3934 
#define SDE_TRANSA_FIFO_UNDER	(1 << 0)
3935 
#define SDE_TRANS_MASK		(0x3f)
3031 serge 3936 
 
3937 
/* south display engine interrupt: CPT/PPT */
3938 
#define SDE_AUDIO_POWER_D_CPT	(1 << 31)
3939 
#define SDE_AUDIO_POWER_C_CPT	(1 << 30)
3940 
#define SDE_AUDIO_POWER_B_CPT	(1 << 29)
3941 
#define SDE_AUDIO_POWER_SHIFT_CPT   29
3942 
#define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
3943 
#define SDE_AUXD_CPT		(1 << 27)
3944 
#define SDE_AUXC_CPT		(1 << 26)
3945 
#define SDE_AUXB_CPT		(1 << 25)
3946 
#define SDE_AUX_MASK_CPT	(7 << 25)
2325 Serge 3947 
#define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
3948 
#define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
3949 
#define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
3031 serge 3950 
#define SDE_CRT_HOTPLUG_CPT	(1 << 19)
3746 Serge 3951 
#define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
2325 Serge 3952 
#define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
3746 Serge 3953 
				 SDE_SDVOB_HOTPLUG_CPT |	\
2325 Serge 3954 
				 SDE_PORTD_HOTPLUG_CPT |	\
3955 
				 SDE_PORTC_HOTPLUG_CPT |	\
3956 
				 SDE_PORTB_HOTPLUG_CPT)
3031 serge 3957 
#define SDE_GMBUS_CPT		(1 << 17)
4104 Serge 3958 
#define SDE_ERROR_CPT		(1 << 16)
3031 serge 3959 
#define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
3960 
#define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
3961 
#define SDE_FDI_RXC_CPT		(1 << 8)
3962 
#define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
3963 
#define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
3964 
#define SDE_FDI_RXB_CPT		(1 << 4)
3965 
#define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
3966 
#define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
3967 
#define SDE_FDI_RXA_CPT		(1 << 0)
3968 
#define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
3969 
				 SDE_AUDIO_CP_REQ_B_CPT | \
3970 
				 SDE_AUDIO_CP_REQ_A_CPT)
3971 
#define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
3972 
				 SDE_AUDIO_CP_CHG_B_CPT | \
3973 
				 SDE_AUDIO_CP_CHG_A_CPT)
3974 
#define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
3975 
				 SDE_FDI_RXB_CPT | \
3976 
				 SDE_FDI_RXA_CPT)
2325 Serge 3977 
 
3978 
#define SDEISR  0xc4000
3979 
#define SDEIMR  0xc4004
3980 
#define SDEIIR  0xc4008
3981 
#define SDEIER  0xc400c
3982 
 
4104 Serge 3983 
#define SERR_INT			0xc4040
3984 
#define  SERR_INT_POISON		(1<<31)
3985 
#define  SERR_INT_TRANS_C_FIFO_UNDERRUN	(1<<6)
3986 
#define  SERR_INT_TRANS_B_FIFO_UNDERRUN	(1<<3)
3987 
#define  SERR_INT_TRANS_A_FIFO_UNDERRUN	(1<<0)
3988 
#define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))
3989 
 
2325 Serge 3990 
/* digital port hotplug */
2342 Serge 3991 
#define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
2325 Serge 3992 
#define PORTD_HOTPLUG_ENABLE            (1 << 20)
3993 
#define PORTD_PULSE_DURATION_2ms        (0)
3994 
#define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
3995 
#define PORTD_PULSE_DURATION_6ms        (2 << 18)
3996 
#define PORTD_PULSE_DURATION_100ms      (3 << 18)
2342 Serge 3997 
#define PORTD_PULSE_DURATION_MASK	(3 << 18)
3480 Serge 3998 
#define PORTD_HOTPLUG_STATUS_MASK	(0x3 << 16)
3999 
#define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
2325 Serge 4000 
#define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
3480 Serge 4001 
#define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
2325 Serge 4002 
#define PORTC_HOTPLUG_ENABLE            (1 << 12)
4003 
#define PORTC_PULSE_DURATION_2ms        (0)
4004 
#define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
4005 
#define PORTC_PULSE_DURATION_6ms        (2 << 10)
4006 
#define PORTC_PULSE_DURATION_100ms      (3 << 10)
2342 Serge 4007 
#define PORTC_PULSE_DURATION_MASK	(3 << 10)
3480 Serge 4008 
#define PORTC_HOTPLUG_STATUS_MASK	(0x3 << 8)
4009 
#define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
2325 Serge 4010 
#define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
3480 Serge 4011 
#define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
2325 Serge 4012 
#define PORTB_HOTPLUG_ENABLE            (1 << 4)
4013 
#define PORTB_PULSE_DURATION_2ms        (0)
4014 
#define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
4015 
#define PORTB_PULSE_DURATION_6ms        (2 << 2)
4016 
#define PORTB_PULSE_DURATION_100ms      (3 << 2)
2342 Serge 4017 
#define PORTB_PULSE_DURATION_MASK	(3 << 2)
3480 Serge 4018 
#define PORTB_HOTPLUG_STATUS_MASK	(0x3 << 0)
4019 
#define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
2325 Serge 4020 
#define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
3480 Serge 4021 
#define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
2325 Serge 4022 
 
4023 
#define PCH_GPIOA               0xc5010
4024 
#define PCH_GPIOB               0xc5014
4025 
#define PCH_GPIOC               0xc5018
4026 
#define PCH_GPIOD               0xc501c
4027 
#define PCH_GPIOE               0xc5020
4028 
#define PCH_GPIOF               0xc5024
4029 
 
4030 
#define PCH_GMBUS0		0xc5100
4031 
#define PCH_GMBUS1		0xc5104
4032 
#define PCH_GMBUS2		0xc5108
4033 
#define PCH_GMBUS3		0xc510c
4034 
#define PCH_GMBUS4		0xc5110
4035 
#define PCH_GMBUS5		0xc5120
4036 
 
4037 
#define _PCH_DPLL_A              0xc6014
4038 
#define _PCH_DPLL_B              0xc6018
4104 Serge 4039 
#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
2325 Serge 4040 
 
4041 
#define _PCH_FPA0                0xc6040
4042 
#define  FP_CB_TUNE		(0x3<<22)
4043 
#define _PCH_FPA1                0xc6044
4044 
#define _PCH_FPB0                0xc6048
4045 
#define _PCH_FPB1                0xc604c
4104 Serge 4046 
#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4047 
#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
2325 Serge 4048 
 
4049 
#define PCH_DPLL_TEST           0xc606c
4050 
 
4051 
#define PCH_DREF_CONTROL        0xC6200
4052 
#define  DREF_CONTROL_MASK      0x7fc3
4053 
#define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
4054 
#define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
4055 
#define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
4056 
#define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
4057 
#define  DREF_SSC_SOURCE_DISABLE                (0<<11)
4058 
#define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
4059 
#define  DREF_SSC_SOURCE_MASK			(3<<11)
4060 
#define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
4061 
#define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
4062 
#define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
4063 
#define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
4064 
#define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
4065 
#define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
4066 
#define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
4067 
#define  DREF_SSC4_DOWNSPREAD                   (0<<6)
4068 
#define  DREF_SSC4_CENTERSPREAD                 (1<<6)
4069 
#define  DREF_SSC1_DISABLE                      (0<<1)
4070 
#define  DREF_SSC1_ENABLE                       (1<<1)
4071 
#define  DREF_SSC4_DISABLE                      (0)
4072 
#define  DREF_SSC4_ENABLE                       (1)
4073 
 
4074 
#define PCH_RAWCLK_FREQ         0xc6204
4075 
#define  FDL_TP1_TIMER_SHIFT    12
4076 
#define  FDL_TP1_TIMER_MASK     (3<<12)
4077 
#define  FDL_TP2_TIMER_SHIFT    10
4078 
#define  FDL_TP2_TIMER_MASK     (3<<10)
4079 
#define  RAWCLK_FREQ_MASK       0x3ff
4080 
 
4081 
#define PCH_DPLL_TMR_CFG        0xc6208
4082 
 
4083 
#define PCH_SSC4_PARMS          0xc6210
4084 
#define PCH_SSC4_AUX_PARMS      0xc6214
4085 
 
4086 
#define PCH_DPLL_SEL		0xc7000
4104 Serge 4087 
#define	 TRANS_DPLLB_SEL(pipe)		(1 << (pipe * 4))
4088 
#define	 TRANS_DPLLA_SEL(pipe)		0
4089 
#define  TRANS_DPLL_ENABLE(pipe)	(1 << (pipe * 4 + 3))
2325 Serge 4090 
 
4091 
/* transcoder */
4092 
 
4104 Serge 4093 
#define _PCH_TRANS_HTOTAL_A		0xe0000
2325 Serge 4094 
#define  TRANS_HTOTAL_SHIFT     16
4095 
#define  TRANS_HACTIVE_SHIFT    0
4104 Serge 4096 
#define _PCH_TRANS_HBLANK_A		0xe0004
2325 Serge 4097 
#define  TRANS_HBLANK_END_SHIFT 16
4098 
#define  TRANS_HBLANK_START_SHIFT 0
4104 Serge 4099 
#define _PCH_TRANS_HSYNC_A		0xe0008
2325 Serge 4100 
#define  TRANS_HSYNC_END_SHIFT  16
4101 
#define  TRANS_HSYNC_START_SHIFT 0
4104 Serge 4102 
#define _PCH_TRANS_VTOTAL_A		0xe000c
2325 Serge 4103 
#define  TRANS_VTOTAL_SHIFT     16
4104 
#define  TRANS_VACTIVE_SHIFT    0
4104 Serge 4105 
#define _PCH_TRANS_VBLANK_A		0xe0010
2325 Serge 4106 
#define  TRANS_VBLANK_END_SHIFT 16
4107 
#define  TRANS_VBLANK_START_SHIFT 0
4104 Serge 4108 
#define _PCH_TRANS_VSYNC_A		0xe0014
2325 Serge 4109 
#define  TRANS_VSYNC_END_SHIFT  16
4110 
#define  TRANS_VSYNC_START_SHIFT 0
4104 Serge 4111 
#define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
2325 Serge 4112 
 
4104 Serge 4113 
#define _PCH_TRANSA_DATA_M1	0xe0030
4114 
#define _PCH_TRANSA_DATA_N1	0xe0034
4115 
#define _PCH_TRANSA_DATA_M2	0xe0038
4116 
#define _PCH_TRANSA_DATA_N2	0xe003c
4117 
#define _PCH_TRANSA_LINK_M1	0xe0040
4118 
#define _PCH_TRANSA_LINK_N1	0xe0044
4119 
#define _PCH_TRANSA_LINK_M2	0xe0048
4120 
#define _PCH_TRANSA_LINK_N2	0xe004c
2325 Serge 4121 
 
4122 
/* Per-transcoder DIP controls */
4123 
 
4124 
#define _VIDEO_DIP_CTL_A         0xe0200
4125 
#define _VIDEO_DIP_DATA_A        0xe0208
4126 
#define _VIDEO_DIP_GCP_A         0xe0210
4127 
 
4128 
#define _VIDEO_DIP_CTL_B         0xe1200
4129 
#define _VIDEO_DIP_DATA_B        0xe1208
4130 
#define _VIDEO_DIP_GCP_B         0xe1210
4131 
 
4132 
#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4133 
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4134 
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4135 
 
3480 Serge 4136 
#define VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
4137 
#define VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
4138 
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
3031 serge 4139 
 
3480 Serge 4140 
#define VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
4141 
#define VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
4142 
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
3031 serge 4143 
 
4144 
#define VLV_TVIDEO_DIP_CTL(pipe) \
4145 
	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4146 
#define VLV_TVIDEO_DIP_DATA(pipe) \
4147 
	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4148 
#define VLV_TVIDEO_DIP_GCP(pipe) \
4149 
	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4150 
 
4151 
/* Haswell DIP controls */
4152 
#define HSW_VIDEO_DIP_CTL_A		0x60200
4153 
#define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
4154 
#define HSW_VIDEO_DIP_VS_DATA_A		0x60260
4155 
#define HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
4156 
#define HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
4157 
#define HSW_VIDEO_DIP_VSC_DATA_A	0x60320
4158 
#define HSW_VIDEO_DIP_AVI_ECC_A		0x60240
4159 
#define HSW_VIDEO_DIP_VS_ECC_A		0x60280
4160 
#define HSW_VIDEO_DIP_SPD_ECC_A		0x602C0
4161 
#define HSW_VIDEO_DIP_GMP_ECC_A		0x60300
4162 
#define HSW_VIDEO_DIP_VSC_ECC_A		0x60344
4163 
#define HSW_VIDEO_DIP_GCP_A		0x60210
4164 
 
4165 
#define HSW_VIDEO_DIP_CTL_B		0x61200
4166 
#define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
4167 
#define HSW_VIDEO_DIP_VS_DATA_B		0x61260
4168 
#define HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
4169 
#define HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
4170 
#define HSW_VIDEO_DIP_VSC_DATA_B	0x61320
4171 
#define HSW_VIDEO_DIP_BVI_ECC_B		0x61240
4172 
#define HSW_VIDEO_DIP_VS_ECC_B		0x61280
4173 
#define HSW_VIDEO_DIP_SPD_ECC_B		0x612C0
4174 
#define HSW_VIDEO_DIP_GMP_ECC_B		0x61300
4175 
#define HSW_VIDEO_DIP_VSC_ECC_B		0x61344
4176 
#define HSW_VIDEO_DIP_GCP_B		0x61210
4177 
 
3746 Serge 4178 
#define HSW_TVIDEO_DIP_CTL(trans) \
4179 
	 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
4180 
#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
4181 
	 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
4104 Serge 4182 
#define HSW_TVIDEO_DIP_VS_DATA(trans) \
4183 
	 _TRANSCODER(trans, HSW_VIDEO_DIP_VS_DATA_A, HSW_VIDEO_DIP_VS_DATA_B)
3746 Serge 4184 
#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
4185 
	 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
4186 
#define HSW_TVIDEO_DIP_GCP(trans) \
4187 
	_TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
4188 
#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
4189 
	 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
3031 serge 4190 
 
4104 Serge 4191 
#define HSW_STEREO_3D_CTL_A	0x70020
4192 
#define   S3D_ENABLE		(1<<31)
4193 
#define HSW_STEREO_3D_CTL_B	0x71020
2325 Serge 4194 
 
4104 Serge 4195 
#define HSW_STEREO_3D_CTL(trans) \
4196 
	_TRANSCODER(trans, HSW_STEREO_3D_CTL_A, HSW_STEREO_3D_CTL_A)
2325 Serge 4197 
 
4104 Serge 4198 
#define _PCH_TRANS_HTOTAL_B          0xe1000
4199 
#define _PCH_TRANS_HBLANK_B          0xe1004
4200 
#define _PCH_TRANS_HSYNC_B           0xe1008
4201 
#define _PCH_TRANS_VTOTAL_B          0xe100c
4202 
#define _PCH_TRANS_VBLANK_B          0xe1010
4203 
#define _PCH_TRANS_VSYNC_B           0xe1014
4204 
#define _PCH_TRANS_VSYNCSHIFT_B	 0xe1028
2325 Serge 4205 
 
4104 Serge 4206 
#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4207 
#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
4208 
#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
4209 
#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
4210 
#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
4211 
#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
4212 
#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
4213 
					 _PCH_TRANS_VSYNCSHIFT_B)
2325 Serge 4214 
 
4104 Serge 4215 
#define _PCH_TRANSB_DATA_M1	0xe1030
4216 
#define _PCH_TRANSB_DATA_N1	0xe1034
4217 
#define _PCH_TRANSB_DATA_M2	0xe1038
4218 
#define _PCH_TRANSB_DATA_N2	0xe103c
4219 
#define _PCH_TRANSB_LINK_M1	0xe1040
4220 
#define _PCH_TRANSB_LINK_N1	0xe1044
4221 
#define _PCH_TRANSB_LINK_M2	0xe1048
4222 
#define _PCH_TRANSB_LINK_N2	0xe104c
4223 
 
4224 
#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
4225 
#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
4226 
#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
4227 
#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
4228 
#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
4229 
#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
4230 
#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
4231 
#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
4232 
 
4233 
#define _PCH_TRANSACONF              0xf0008
4234 
#define _PCH_TRANSBCONF              0xf1008
4235 
#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
4236 
#define LPT_TRANSCONF		_PCH_TRANSACONF /* lpt has only one transcoder */
2325 Serge 4237 
#define  TRANS_DISABLE          (0<<31)
4238 
#define  TRANS_ENABLE           (1<<31)
4239 
#define  TRANS_STATE_MASK       (1<<30)
4240 
#define  TRANS_STATE_DISABLE    (0<<30)
4241 
#define  TRANS_STATE_ENABLE     (1<<30)
4242 
#define  TRANS_FSYNC_DELAY_HB1  (0<<27)
4243 
#define  TRANS_FSYNC_DELAY_HB2  (1<<27)
4244 
#define  TRANS_FSYNC_DELAY_HB3  (2<<27)
4245 
#define  TRANS_FSYNC_DELAY_HB4  (3<<27)
3031 serge 4246 
#define  TRANS_INTERLACE_MASK   (7<<21)
2325 Serge 4247 
#define  TRANS_PROGRESSIVE      (0<<21)
3031 serge 4248 
#define  TRANS_INTERLACED       (3<<21)
4249 
#define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
2325 Serge 4250 
#define  TRANS_8BPC             (0<<5)
4251 
#define  TRANS_10BPC            (1<<5)
4252 
#define  TRANS_6BPC             (2<<5)
4253 
#define  TRANS_12BPC            (3<<5)
4254 
 
3243 Serge 4255 
#define _TRANSA_CHICKEN1	 0xf0060
4256 
#define _TRANSB_CHICKEN1	 0xf1060
4257 
#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
4258 
#define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)
2325 Serge 4259 
#define _TRANSA_CHICKEN2	 0xf0064
4260 
#define _TRANSB_CHICKEN2	 0xf1064
4261 
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3243 Serge 4262 
#define  TRANS_CHICKEN2_TIMING_OVERRIDE		(1<<31)
3746 Serge 4263 
#define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1<<29)
4264 
#define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3<<27)
4265 
#define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1<<26)
4266 
#define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1<<25)
2325 Serge 4267 
 
4268 
#define SOUTH_CHICKEN1		0xc2000
4269 
#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
4270 
#define  FDIA_PHASE_SYNC_SHIFT_EN	18
4271 
#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
4272 
#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3243 Serge 4273 
#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
2325 Serge 4274 
#define SOUTH_CHICKEN2		0xc2004
3243 Serge 4275 
#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
4276 
#define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
2325 Serge 4277 
#define  DPLS_EDP_PPS_FIX_DIS	(1<<0)
4278 
 
4279 
#define _FDI_RXA_CHICKEN         0xc200c
4280 
#define _FDI_RXB_CHICKEN         0xc2010
4281 
#define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
4282 
#define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
4283 
#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
4284 
 
4285 
#define SOUTH_DSPCLK_GATE_D	0xc2020
4280 Serge 4286 
#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
2325 Serge 4287 
#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4280 Serge 4288 
#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
3243 Serge 4289 
#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
2325 Serge 4290 
 
4291 
/* CPU: FDI_TX */
4292 
#define _FDI_TXA_CTL             0x60100
4293 
#define _FDI_TXB_CTL             0x61100
4294 
#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
4295 
#define  FDI_TX_DISABLE         (0<<31)
4296 
#define  FDI_TX_ENABLE          (1<<31)
4297 
#define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
4298 
#define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
4299 
#define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
4300 
#define  FDI_LINK_TRAIN_NONE            (3<<28)
4301 
#define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
4302 
#define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
4303 
#define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
4304 
#define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
4305 
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
4306 
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
4307 
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
4308 
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
4309 
/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
4310 
   SNB has different settings. */
4311 
/* SNB A-stepping */
4312 
#define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
4313 
#define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
4314 
#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
4315 
#define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
4316 
/* SNB B-stepping */
4317 
#define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)
4318 
#define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)
4319 
#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
4320 
#define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
4321 
#define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
4104 Serge 4322 
#define  FDI_DP_PORT_WIDTH_SHIFT		19
4323 
#define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
4324 
#define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
2325 Serge 4325 
#define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
4326 
/* Ironlake: hardwired to 1 */
4327 
#define  FDI_TX_PLL_ENABLE              (1<<14)
4328 
 
4329 
/* Ivybridge has different bits for lolz */
4330 
#define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
4331 
#define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
4332 
#define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
4333 
#define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
4334 
 
4335 
/* both Tx and Rx */
2342 Serge 4336 
#define  FDI_COMPOSITE_SYNC		(1<<11)
2325 Serge 4337 
#define  FDI_LINK_TRAIN_AUTO		(1<<10)
4338 
#define  FDI_SCRAMBLING_ENABLE          (0<<7)
4339 
#define  FDI_SCRAMBLING_DISABLE         (1<<7)
4340 
 
4341 
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
4342 
#define _FDI_RXA_CTL             0xf000c
4343 
#define _FDI_RXB_CTL             0xf100c
4344 
#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
4345 
#define  FDI_RX_ENABLE          (1<<31)
4346 
/* train, dp width same as FDI_TX */
4347 
#define  FDI_FS_ERRC_ENABLE		(1<<27)
4348 
#define  FDI_FE_ERRC_ENABLE		(1<<26)
3243 Serge 4349 
#define  FDI_RX_POLARITY_REVERSED_LPT	(1<<16)
2325 Serge 4350 
#define  FDI_8BPC                       (0<<16)
4351 
#define  FDI_10BPC                      (1<<16)
4352 
#define  FDI_6BPC                       (2<<16)
4353 
#define  FDI_12BPC                      (3<<16)
3480 Serge 4354 
#define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1<<15)
2325 Serge 4355 
#define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
4356 
#define  FDI_RX_PLL_ENABLE              (1<<13)
4357 
#define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
4358 
#define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
4359 
#define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
4360 
#define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
4361 
#define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
4362 
#define  FDI_PCDCLK	                (1<<4)
4363 
/* CPT */
4364 
#define  FDI_AUTO_TRAINING			(1<<10)
4365 
#define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0<<8)
4366 
#define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1<<8)
4367 
#define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
4368 
#define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
4369 
#define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
4370 
 
4371 
#define _FDI_RXA_MISC            0xf0010
4372 
#define _FDI_RXB_MISC            0xf1010
3243 Serge 4373 
#define  FDI_RX_PWRDN_LANE1_MASK	(3<<26)
4374 
#define  FDI_RX_PWRDN_LANE1_VAL(x)	((x)<<26)
4375 
#define  FDI_RX_PWRDN_LANE0_MASK	(3<<24)
4376 
#define  FDI_RX_PWRDN_LANE0_VAL(x)	((x)<<24)
4377 
#define  FDI_RX_TP1_TO_TP2_48		(2<<20)
4378 
#define  FDI_RX_TP1_TO_TP2_64		(3<<20)
4379 
#define  FDI_RX_FDI_DELAY_90		(0x90<<0)
4380 
#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4381 
 
2325 Serge 4382 
#define _FDI_RXA_TUSIZE1         0xf0030
4383 
#define _FDI_RXA_TUSIZE2         0xf0038
4384 
#define _FDI_RXB_TUSIZE1         0xf1030
4385 
#define _FDI_RXB_TUSIZE2         0xf1038
4386 
#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4387 
#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
4388 
 
4389 
/* FDI_RX interrupt register format */
4390 
#define FDI_RX_INTER_LANE_ALIGN         (1<<10)
4391 
#define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
4392 
#define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
4393 
#define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
4394 
#define FDI_RX_FS_CODE_ERR              (1<<6)
4395 
#define FDI_RX_FE_CODE_ERR              (1<<5)
4396 
#define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
4397 
#define FDI_RX_HDCP_LINK_FAIL           (1<<3)
4398 
#define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
4399 
#define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
4400 
#define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
4401 
 
4402 
#define _FDI_RXA_IIR             0xf0014
4403 
#define _FDI_RXA_IMR             0xf0018
4404 
#define _FDI_RXB_IIR             0xf1014
4405 
#define _FDI_RXB_IMR             0xf1018
4406 
#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4407 
#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
4408 
 
4409 
#define FDI_PLL_CTL_1           0xfe000
4410 
#define FDI_PLL_CTL_2           0xfe004
4411 
 
4412 
#define PCH_LVDS	0xe1180
4413 
#define  LVDS_DETECTED	(1 << 1)
4414 
 
3031 serge 4415 
/* vlv has 2 sets of panel control regs. */
3480 Serge 4416 
#define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
4417 
#define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
4418 
#define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
4419 
#define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
4420 
#define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
2325 Serge 4421 
 
3480 Serge 4422 
#define PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
4423 
#define PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
4424 
#define PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
4425 
#define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
4426 
#define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
2325 Serge 4427 
 
3746 Serge 4428 
#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4429 
#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4430 
#define VLV_PIPE_PP_ON_DELAYS(pipe) \
4431 
		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4432 
#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4433 
		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4434 
#define VLV_PIPE_PP_DIVISOR(pipe) \
4435 
		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4436 
 
2325 Serge 4437 
#define PCH_PP_STATUS		0xc7200
4438 
#define PCH_PP_CONTROL		0xc7204
4439 
#define  PANEL_UNLOCK_REGS	(0xabcd << 16)
2342 Serge 4440 
#define  PANEL_UNLOCK_MASK	(0xffff << 16)
2325 Serge 4441 
#define  EDP_FORCE_VDD		(1 << 3)
4442 
#define  EDP_BLC_ENABLE		(1 << 2)
4443 
#define  PANEL_POWER_RESET	(1 << 1)
4444 
#define  PANEL_POWER_OFF	(0 << 0)
4445 
#define  PANEL_POWER_ON		(1 << 0)
4446 
#define PCH_PP_ON_DELAYS	0xc7208
2342 Serge 4447 
#define  PANEL_PORT_SELECT_MASK	(3 << 30)
4448 
#define  PANEL_PORT_SELECT_LVDS	(0 << 30)
4449 
#define  PANEL_PORT_SELECT_DPA	(1 << 30)
2325 Serge 4450 
#define  EDP_PANEL		(1 << 30)
2342 Serge 4451 
#define  PANEL_PORT_SELECT_DPC	(2 << 30)
4452 
#define  PANEL_PORT_SELECT_DPD	(3 << 30)
4453 
#define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
4454 
#define  PANEL_POWER_UP_DELAY_SHIFT	16
4455 
#define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
4456 
#define  PANEL_LIGHT_ON_DELAY_SHIFT	0
4457 
 
2325 Serge 4458 
#define PCH_PP_OFF_DELAYS	0xc720c
3243 Serge 4459 
#define  PANEL_POWER_PORT_SELECT_MASK	(0x3 << 30)
4460 
#define  PANEL_POWER_PORT_LVDS		(0 << 30)
4461 
#define  PANEL_POWER_PORT_DP_A		(1 << 30)
4462 
#define  PANEL_POWER_PORT_DP_C		(2 << 30)
4463 
#define  PANEL_POWER_PORT_DP_D		(3 << 30)
2342 Serge 4464 
#define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
4465 
#define  PANEL_POWER_DOWN_DELAY_SHIFT	16
4466 
#define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
4467 
#define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
4468 
 
2325 Serge 4469 
#define PCH_PP_DIVISOR		0xc7210
2342 Serge 4470 
#define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
4471 
#define  PP_REFERENCE_DIVIDER_SHIFT	8
4472 
#define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
4473 
#define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
2325 Serge 4474 
 
4475 
#define PCH_DP_B		0xe4100
4476 
#define PCH_DPB_AUX_CH_CTL	0xe4110
4477 
#define PCH_DPB_AUX_CH_DATA1	0xe4114
4478 
#define PCH_DPB_AUX_CH_DATA2	0xe4118
4479 
#define PCH_DPB_AUX_CH_DATA3	0xe411c
4480 
#define PCH_DPB_AUX_CH_DATA4	0xe4120
4481 
#define PCH_DPB_AUX_CH_DATA5	0xe4124
4482 
 
4483 
#define PCH_DP_C		0xe4200
4484 
#define PCH_DPC_AUX_CH_CTL	0xe4210
4485 
#define PCH_DPC_AUX_CH_DATA1	0xe4214
4486 
#define PCH_DPC_AUX_CH_DATA2	0xe4218
4487 
#define PCH_DPC_AUX_CH_DATA3	0xe421c
4488 
#define PCH_DPC_AUX_CH_DATA4	0xe4220
4489 
#define PCH_DPC_AUX_CH_DATA5	0xe4224
4490 
 
4491 
#define PCH_DP_D		0xe4300
4492 
#define PCH_DPD_AUX_CH_CTL	0xe4310
4493 
#define PCH_DPD_AUX_CH_DATA1	0xe4314
4494 
#define PCH_DPD_AUX_CH_DATA2	0xe4318
4495 
#define PCH_DPD_AUX_CH_DATA3	0xe431c
4496 
#define PCH_DPD_AUX_CH_DATA4	0xe4320
4497 
#define PCH_DPD_AUX_CH_DATA5	0xe4324
4498 
 
4499 
/* CPT */
4500 
#define  PORT_TRANS_A_SEL_CPT	0
4501 
#define  PORT_TRANS_B_SEL_CPT	(1<<29)
4502 
#define  PORT_TRANS_C_SEL_CPT	(2<<29)
4503 
#define  PORT_TRANS_SEL_MASK	(3<<29)
4504 
#define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
3031 serge 4505 
#define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
4506 
#define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
2325 Serge 4507 
 
4508 
#define TRANS_DP_CTL_A		0xe0300
4509 
#define TRANS_DP_CTL_B		0xe1300
4510 
#define TRANS_DP_CTL_C		0xe2300
3243 Serge 4511 
#define TRANS_DP_CTL(pipe)	_PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
2325 Serge 4512 
#define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
4513 
#define  TRANS_DP_PORT_SEL_B	(0<<29)
4514 
#define  TRANS_DP_PORT_SEL_C	(1<<29)
4515 
#define  TRANS_DP_PORT_SEL_D	(2<<29)
4516 
#define  TRANS_DP_PORT_SEL_NONE	(3<<29)
4517 
#define  TRANS_DP_PORT_SEL_MASK	(3<<29)
4518 
#define  TRANS_DP_AUDIO_ONLY	(1<<26)
4519 
#define  TRANS_DP_ENH_FRAMING	(1<<18)
4520 
#define  TRANS_DP_8BPC		(0<<9)
4521 
#define  TRANS_DP_10BPC		(1<<9)
4522 
#define  TRANS_DP_6BPC		(2<<9)
4523 
#define  TRANS_DP_12BPC		(3<<9)
4524 
#define  TRANS_DP_BPC_MASK	(3<<9)
4525 
#define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1<<4)
4526 
#define  TRANS_DP_VSYNC_ACTIVE_LOW	0
4527 
#define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1<<3)
4528 
#define  TRANS_DP_HSYNC_ACTIVE_LOW	0
4529 
#define  TRANS_DP_SYNC_MASK	(3<<3)
4530 
 
4531 
/* SNB eDP training params */
4532 
/* SNB A-stepping */
4533 
#define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
4534 
#define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
4535 
#define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
4536 
#define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
4537 
/* SNB B-stepping */
4538 
#define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)
4539 
#define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)
4540 
#define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)
4541 
#define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)
4542 
#define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)
4543 
#define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)
4544 
 
2342 Serge 4545 
/* IVB */
4546 
#define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
4547 
#define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
4548 
#define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
4549 
#define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
4550 
#define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
4551 
#define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
4104 Serge 4552 
#define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e <<22)
2342 Serge 4553 
 
4554 
/* legacy values */
4555 
#define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
4556 
#define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
4557 
#define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
4558 
#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
4559 
#define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)
4560 
 
4561 
#define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
4562 
 
2325 Serge 4563 
#define  FORCEWAKE				0xA18C
3031 serge 4564 
#define  FORCEWAKE_VLV				0x1300b0
4565 
#define  FORCEWAKE_ACK_VLV			0x1300b4
3746 Serge 4566 
#define  FORCEWAKE_MEDIA_VLV			0x1300b8
4567 
#define  FORCEWAKE_ACK_MEDIA_VLV		0x1300bc
3031 serge 4568 
#define  FORCEWAKE_ACK_HSW			0x130044
2325 Serge 4569 
#define  FORCEWAKE_ACK				0x130090
3746 Serge 4570 
#define  VLV_GTLC_WAKE_CTRL			0x130090
4571 
#define  VLV_GTLC_PW_STATUS			0x130094
2342 Serge 4572 
#define  FORCEWAKE_MT				0xa188 /* multi-threaded */
3243 Serge 4573 
#define   FORCEWAKE_KERNEL			0x1
4574 
#define   FORCEWAKE_USER			0x2
2342 Serge 4575 
#define  FORCEWAKE_MT_ACK			0x130040
4576 
#define  ECOBUS					0xa180
4577 
#define    FORCEWAKE_MT_ENABLE			(1<<5)
2325 Serge 4578 
 
3031 serge 4579 
#define  GTFIFODBG				0x120000
4580 
#define    GT_FIFO_CPU_ERROR_MASK		7
4581 
#define    GT_FIFO_OVFERR			(1<<2)
4582 
#define    GT_FIFO_IAWRERR			(1<<1)
4583 
#define    GT_FIFO_IARDERR			(1<<0)
4584 
 
2325 Serge 4585 
#define  GT_FIFO_FREE_ENTRIES			0x120008
4586 
#define    GT_FIFO_NUM_RESERVED_ENTRIES		20
4587 
 
4104 Serge 4588 
#define  HSW_IDICR				0x9008
4589 
#define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
4590 
#define  HSW_EDRAM_PRESENT			0x120010
4591 
 
3031 serge 4592 
#define GEN6_UCGCTL1				0x9400
4593 
# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
4594 
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
4595 
 
2342 Serge 4596 
#define GEN6_UCGCTL2				0x9404
3031 serge 4597 
# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
4598 
# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
4599 
# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
2342 Serge 4600 
# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
4601 
# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
4602 
 
3031 serge 4603 
#define GEN7_UCGCTL4				0x940c
4604 
#define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
4605 
 
2325 Serge 4606 
#define GEN6_RPNSWREQ				0xA008
4607 
#define   GEN6_TURBO_DISABLE			(1<<31)
4608 
#define   GEN6_FREQUENCY(x)			((x)<<25)
3746 Serge 4609 
#define   HSW_FREQUENCY(x)			((x)<<24)
2325 Serge 4610 
#define   GEN6_OFFSET(x)			((x)<<19)
4611 
#define   GEN6_AGGRESSIVE_TURBO			(0<<15)
4612 
#define GEN6_RC_VIDEO_FREQ			0xA00C
4613 
#define GEN6_RC_CONTROL				0xA090
4614 
#define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
4615 
#define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
4616 
#define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
4617 
#define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)
4618 
#define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)
4104 Serge 4619 
#define   GEN7_RC_CTL_TO_MODE			(1<<28)
2325 Serge 4620 
#define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
4621 
#define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
4622 
#define GEN6_RP_DOWN_TIMEOUT			0xA010
4623 
#define GEN6_RP_INTERRUPT_LIMITS		0xA014
4624 
#define GEN6_RPSTAT1				0xA01C
4625 
#define   GEN6_CAGF_SHIFT			8
3480 Serge 4626 
#define   HSW_CAGF_SHIFT			7
2325 Serge 4627 
#define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
3480 Serge 4628 
#define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
2325 Serge 4629 
#define GEN6_RP_CONTROL				0xA024
4630 
#define   GEN6_RP_MEDIA_TURBO			(1<<11)
2342 Serge 4631 
#define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
4632 
#define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
4633 
#define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2<<9)
4634 
#define   GEN6_RP_MEDIA_HW_MODE			(1<<9)
4635 
#define   GEN6_RP_MEDIA_SW_MODE			(0<<9)
2325 Serge 4636 
#define   GEN6_RP_MEDIA_IS_GFX			(1<<8)
4637 
#define   GEN6_RP_ENABLE			(1<<7)
4638 
#define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
4639 
#define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
4640 
#define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
3031 serge 4641 
#define   GEN7_RP_DOWN_IDLE_AVG			(0x2<<0)
2325 Serge 4642 
#define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
4643 
#define GEN6_RP_UP_THRESHOLD			0xA02C
4644 
#define GEN6_RP_DOWN_THRESHOLD			0xA030
4645 
#define GEN6_RP_CUR_UP_EI			0xA050
4646 
#define   GEN6_CURICONT_MASK			0xffffff
4647 
#define GEN6_RP_CUR_UP				0xA054
4648 
#define   GEN6_CURBSYTAVG_MASK			0xffffff
4649 
#define GEN6_RP_PREV_UP				0xA058
4650 
#define GEN6_RP_CUR_DOWN_EI			0xA05C
4651 
#define   GEN6_CURIAVG_MASK			0xffffff
4652 
#define GEN6_RP_CUR_DOWN			0xA060
4653 
#define GEN6_RP_PREV_DOWN			0xA064
4654 
#define GEN6_RP_UP_EI				0xA068
4655 
#define GEN6_RP_DOWN_EI				0xA06C
4656 
#define GEN6_RP_IDLE_HYSTERSIS			0xA070
4657 
#define GEN6_RC_STATE				0xA094
4658 
#define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
4659 
#define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
4660 
#define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
4661 
#define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
4662 
#define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
4663 
#define GEN6_RC_SLEEP				0xA0B0
4664 
#define GEN6_RC1e_THRESHOLD			0xA0B4
4665 
#define GEN6_RC6_THRESHOLD			0xA0B8
4666 
#define GEN6_RC6p_THRESHOLD			0xA0BC
4667 
#define GEN6_RC6pp_THRESHOLD			0xA0C0
4668 
#define GEN6_PMINTRMSK				0xA168
4669 
 
4670 
#define GEN6_PMISR				0x44020
4671 
#define GEN6_PMIMR				0x44024 /* rps_lock */
4672 
#define GEN6_PMIIR				0x44028
4673 
#define GEN6_PMIER				0x4402C
4674 
#define  GEN6_PM_MBOX_EVENT			(1<<25)
4675 
#define  GEN6_PM_THERMAL_EVENT			(1<<24)
4676 
#define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
4677 
#define  GEN6_PM_RP_UP_THRESHOLD		(1<<5)
4678 
#define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
4679 
#define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
4680 
#define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
4104 Serge 4681 
#define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_THRESHOLD | \
2325 Serge 4682 
						 GEN6_PM_RP_DOWN_THRESHOLD | \
4683 
						 GEN6_PM_RP_DOWN_TIMEOUT)
4684 
 
3031 serge 4685 
#define GEN6_GT_GFX_RC6_LOCKED			0x138104
4686 
#define GEN6_GT_GFX_RC6				0x138108
4687 
#define GEN6_GT_GFX_RC6p			0x13810C
4688 
#define GEN6_GT_GFX_RC6pp			0x138110
4689 
 
2325 Serge 4690 
#define GEN6_PCODE_MAILBOX			0x138124
4691 
#define   GEN6_PCODE_READY			(1<<31)
4692 
#define   GEN6_READ_OC_PARAMS			0xc
4693 
#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
4694 
#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
3243 Serge 4695 
#define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
4696 
#define	  GEN6_PCODE_READ_RC6VIDS		0x5
3480 Serge 4697 
#define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
4698 
#define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
2325 Serge 4699 
#define GEN6_PCODE_DATA				0x138128
4700 
#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
3746 Serge 4701 
#define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
2325 Serge 4702 
 
2342 Serge 4703 
#define GEN6_GT_CORE_STATUS		0x138060
4704 
#define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
4705 
#define   GEN6_RCn_MASK			7
4706 
#define   GEN6_RC0			0
4707 
#define   GEN6_RC3			2
4708 
#define   GEN6_RC6			3
4709 
#define   GEN6_RC7			4
4710 
 
3031 serge 4711 
#define GEN7_MISCCPCTL			(0x9424)
4712 
#define   GEN7_DOP_CLOCK_GATE_ENABLE	(1<<0)
4713 
 
4714 
/* IVYBRIDGE DPF */
4715 
#define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
4716 
#define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
4717 
#define   GEN7_PARITY_ERROR_VALID	(1<<13)
4718 
#define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
4719 
#define   GEN7_L3CDERRST1_SUBBANK_MASK	(7<<8)
4720 
#define GEN7_PARITY_ERROR_ROW(reg) \
4721 
		((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4722 
#define GEN7_PARITY_ERROR_BANK(reg) \
4723 
		((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4724 
#define GEN7_PARITY_ERROR_SUBBANK(reg) \
4725 
		((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4726 
#define   GEN7_L3CDERRST1_ENABLE	(1<<7)
4727 
 
4728 
#define GEN7_L3LOG_BASE			0xB070
4729 
#define GEN7_L3LOG_SIZE			0x80
4730 
 
3243 Serge 4731 
#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
4732 
#define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
4733 
#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
4734 
#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
4735 
 
4736 
#define GEN7_ROW_CHICKEN2		0xe4f4
4737 
#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
4738 
#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
4739 
 
4104 Serge 4740 
#define HSW_ROW_CHICKEN3		0xe49c
4741 
#define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
4742 
 
3480 Serge 4743 
#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
2342 Serge 4744 
#define INTEL_AUDIO_DEVCL		0x808629FB
4745 
#define INTEL_AUDIO_DEVBLC		0x80862801
4746 
#define INTEL_AUDIO_DEVCTG		0x80862802
4747 
 
4748 
#define G4X_AUD_CNTL_ST			0x620B4
4749 
#define G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
4750 
#define G4X_ELDV_DEVCTG			(1 << 14)
4751 
#define G4X_ELD_ADDR			(0xf << 5)
4752 
#define G4X_ELD_ACK			(1 << 4)
4753 
#define G4X_HDMIW_HDMIEDID		0x6210C
4754 
 
4755 
#define IBX_HDMIW_HDMIEDID_A		0xE2050
3031 serge 4756 
#define IBX_HDMIW_HDMIEDID_B		0xE2150
4757 
#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4758 
					IBX_HDMIW_HDMIEDID_A, \
4759 
					IBX_HDMIW_HDMIEDID_B)
2342 Serge 4760 
#define IBX_AUD_CNTL_ST_A		0xE20B4
3031 serge 4761 
#define IBX_AUD_CNTL_ST_B		0xE21B4
4762 
#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4763 
					IBX_AUD_CNTL_ST_A, \
4764 
					IBX_AUD_CNTL_ST_B)
2342 Serge 4765 
#define IBX_ELD_BUFFER_SIZE		(0x1f << 10)
4766 
#define IBX_ELD_ADDRESS			(0x1f << 5)
4767 
#define IBX_ELD_ACK			(1 << 4)
4768 
#define IBX_AUD_CNTL_ST2		0xE20C0
4769 
#define IBX_ELD_VALIDB			(1 << 0)
4770 
#define IBX_CP_READYB			(1 << 1)
4771 
 
4772 
#define CPT_HDMIW_HDMIEDID_A		0xE5050
3031 serge 4773 
#define CPT_HDMIW_HDMIEDID_B		0xE5150
4774 
#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4775 
					CPT_HDMIW_HDMIEDID_A, \
4776 
					CPT_HDMIW_HDMIEDID_B)
2342 Serge 4777 
#define CPT_AUD_CNTL_ST_A		0xE50B4
3031 serge 4778 
#define CPT_AUD_CNTL_ST_B		0xE51B4
4779 
#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4780 
					CPT_AUD_CNTL_ST_A, \
4781 
					CPT_AUD_CNTL_ST_B)
2342 Serge 4782 
#define CPT_AUD_CNTRL_ST2		0xE50C0
4783 
 
4784 
/* These are the 4 32-bit write offset registers for each stream
4785 
 * output buffer.  It determines the offset from the
4786 
 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4787 
 */
4788 
#define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
4789 
 
3031 serge 4790 
#define IBX_AUD_CONFIG_A			0xe2000
4791 
#define IBX_AUD_CONFIG_B			0xe2100
4792 
#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4793 
					IBX_AUD_CONFIG_A, \
4794 
					IBX_AUD_CONFIG_B)
4795 
#define CPT_AUD_CONFIG_A			0xe5000
4796 
#define CPT_AUD_CONFIG_B			0xe5100
4797 
#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4798 
					CPT_AUD_CONFIG_A, \
4799 
					CPT_AUD_CONFIG_B)
4800 
#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
4801 
#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
4802 
#define   AUD_CONFIG_UPPER_N_SHIFT		20
4803 
#define   AUD_CONFIG_UPPER_N_VALUE		(0xff << 20)
4804 
#define   AUD_CONFIG_LOWER_N_SHIFT		4
4805 
#define   AUD_CONFIG_LOWER_N_VALUE		(0xfff << 4)
4806 
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
4807 
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI		(0xf << 16)
4808 
#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
4809 
 
4810 
/* HSW Audio */
4811 
#define   HSW_AUD_CONFIG_A		0x65000 /* Audio Configuration Transcoder A */
4812 
#define   HSW_AUD_CONFIG_B		0x65100 /* Audio Configuration Transcoder B */
4813 
#define   HSW_AUD_CFG(pipe) _PIPE(pipe, \
4814 
					HSW_AUD_CONFIG_A, \
4815 
					HSW_AUD_CONFIG_B)
4816 
 
4817 
#define   HSW_AUD_MISC_CTRL_A		0x65010 /* Audio Misc Control Convert 1 */
4818 
#define   HSW_AUD_MISC_CTRL_B		0x65110 /* Audio Misc Control Convert 2 */
4819 
#define   HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
4820 
					HSW_AUD_MISC_CTRL_A, \
4821 
					HSW_AUD_MISC_CTRL_B)
4822 
 
4823 
#define   HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4 /* Audio DIP and ELD Control State Transcoder A */
4824 
#define   HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4 /* Audio DIP and ELD Control State Transcoder B */
4825 
#define   HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
4826 
					HSW_AUD_DIP_ELD_CTRL_ST_A, \
4827 
					HSW_AUD_DIP_ELD_CTRL_ST_B)
4828 
 
4829 
/* Audio Digital Converter */
4830 
#define   HSW_AUD_DIG_CNVT_1		0x65080 /* Audio Converter 1 */
4831 
#define   HSW_AUD_DIG_CNVT_2		0x65180 /* Audio Converter 1 */
4832 
#define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
4833 
					HSW_AUD_DIG_CNVT_1, \
4834 
					HSW_AUD_DIG_CNVT_2)
4835 
#define   DIP_PORT_SEL_MASK		0x3
4836 
 
4837 
#define   HSW_AUD_EDID_DATA_A		0x65050
4838 
#define   HSW_AUD_EDID_DATA_B		0x65150
4839 
#define   HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
4840 
					HSW_AUD_EDID_DATA_A, \
4841 
					HSW_AUD_EDID_DATA_B)
4842 
 
4843 
#define   HSW_AUD_PIPE_CONV_CFG		0x6507c /* Audio pipe and converter configs */
4844 
#define   HSW_AUD_PIN_ELD_CP_VLD	0x650c0 /* Audio ELD and CP Ready Status */
4845 
#define   AUDIO_INACTIVE_C		(1<<11)
4846 
#define   AUDIO_INACTIVE_B		(1<<7)
4847 
#define   AUDIO_INACTIVE_A		(1<<3)
4848 
#define   AUDIO_OUTPUT_ENABLE_A		(1<<2)
4849 
#define   AUDIO_OUTPUT_ENABLE_B		(1<<6)
4850 
#define   AUDIO_OUTPUT_ENABLE_C		(1<<10)
4851 
#define   AUDIO_ELD_VALID_A		(1<<0)
4852 
#define   AUDIO_ELD_VALID_B		(1<<4)
4853 
#define   AUDIO_ELD_VALID_C		(1<<8)
4854 
#define   AUDIO_CP_READY_A		(1<<1)
4855 
#define   AUDIO_CP_READY_B		(1<<5)
4856 
#define   AUDIO_CP_READY_C		(1<<9)
4857 
 
4858 
/* HSW Power Wells */
3480 Serge 4859 
#define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
4860 
#define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
4861 
#define HSW_PWR_WELL_KVMR			0x45408 /* CTL3 */
4862 
#define HSW_PWR_WELL_DEBUG			0x4540C /* CTL4 */
4104 Serge 4863 
#define   HSW_PWR_WELL_ENABLE_REQUEST		(1<<31)
4864 
#define   HSW_PWR_WELL_STATE_ENABLED		(1<<30)
3031 serge 4865 
#define HSW_PWR_WELL_CTL5		0x45410
4866 
#define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
4867 
#define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
4868 
#define   HSW_PWR_WELL_FORCE_ON				(1<<19)
4869 
#define HSW_PWR_WELL_CTL6		0x45414
4870 
 
4871 
/* Per-pipe DDI Function Control */
3243 Serge 4872 
#define TRANS_DDI_FUNC_CTL_A		0x60400
4873 
#define TRANS_DDI_FUNC_CTL_B		0x61400
4874 
#define TRANS_DDI_FUNC_CTL_C		0x62400
4875 
#define TRANS_DDI_FUNC_CTL_EDP		0x6F400
4876 
#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
4877 
						   TRANS_DDI_FUNC_CTL_B)
4878 
#define  TRANS_DDI_FUNC_ENABLE		(1<<31)
3031 serge 4879 
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
3243 Serge 4880 
#define  TRANS_DDI_PORT_MASK		(7<<28)
4881 
#define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
4882 
#define  TRANS_DDI_PORT_NONE		(0<<28)
4883 
#define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
4884 
#define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
4885 
#define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)
4886 
#define  TRANS_DDI_MODE_SELECT_DP_SST	(2<<24)
4887 
#define  TRANS_DDI_MODE_SELECT_DP_MST	(3<<24)
4888 
#define  TRANS_DDI_MODE_SELECT_FDI	(4<<24)
4889 
#define  TRANS_DDI_BPC_MASK		(7<<20)
4890 
#define  TRANS_DDI_BPC_8		(0<<20)
4891 
#define  TRANS_DDI_BPC_10		(1<<20)
4892 
#define  TRANS_DDI_BPC_6		(2<<20)
4893 
#define  TRANS_DDI_BPC_12		(3<<20)
4894 
#define  TRANS_DDI_PVSYNC		(1<<17)
4895 
#define  TRANS_DDI_PHSYNC		(1<<16)
4896 
#define  TRANS_DDI_EDP_INPUT_MASK	(7<<12)
4897 
#define  TRANS_DDI_EDP_INPUT_A_ON	(0<<12)
4898 
#define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
4899 
#define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
4900 
#define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
4901 
#define  TRANS_DDI_BFI_ENABLE		(1<<4)
3031 serge 4902 
 
4903 
/* DisplayPort Transport Control */
4904 
#define DP_TP_CTL_A			0x64040
4905 
#define DP_TP_CTL_B			0x64140
4906 
#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
4907 
#define  DP_TP_CTL_ENABLE		(1<<31)
4908 
#define  DP_TP_CTL_MODE_SST	(0<<27)
4909 
#define  DP_TP_CTL_MODE_MST	(1<<27)
4910 
#define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
4911 
#define  DP_TP_CTL_FDI_AUTOTRAIN	(1<<15)
4912 
#define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
4913 
#define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
4914 
#define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
3243 Serge 4915 
#define  DP_TP_CTL_LINK_TRAIN_PAT3		(4<<8)
4916 
#define  DP_TP_CTL_LINK_TRAIN_IDLE		(2<<8)
3031 serge 4917 
#define  DP_TP_CTL_LINK_TRAIN_NORMAL	(3<<8)
3243 Serge 4918 
#define  DP_TP_CTL_SCRAMBLE_DISABLE		(1<<7)
3031 serge 4919 
 
4920 
/* DisplayPort Transport Status */
4921 
#define DP_TP_STATUS_A			0x64044
4922 
#define DP_TP_STATUS_B			0x64144
4923 
#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
3243 Serge 4924 
#define  DP_TP_STATUS_IDLE_DONE		(1<<25)
3031 serge 4925 
#define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
4926 
 
4927 
/* DDI Buffer Control */
4928 
#define DDI_BUF_CTL_A				0x64000
4929 
#define DDI_BUF_CTL_B				0x64100
4930 
#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
4931 
#define  DDI_BUF_CTL_ENABLE				(1<<31)
4932 
#define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
4933 
#define  DDI_BUF_EMP_400MV_3_5DB_HSW	(1<<24)   /* Sel1 */
4934 
#define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
4935 
#define  DDI_BUF_EMP_400MV_9_5DB_HSW	(3<<24)   /* Sel3 */
4936 
#define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */
4937 
#define  DDI_BUF_EMP_600MV_3_5DB_HSW	(5<<24)   /* Sel5 */
4938 
#define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
4939 
#define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
4940 
#define  DDI_BUF_EMP_800MV_3_5DB_HSW	(8<<24)   /* Sel8 */
4941 
#define  DDI_BUF_EMP_MASK				(0xf<<24)
3480 Serge 4942 
#define  DDI_BUF_PORT_REVERSAL			(1<<16)
3031 serge 4943 
#define  DDI_BUF_IS_IDLE				(1<<7)
3243 Serge 4944 
#define  DDI_A_4_LANES				(1<<4)
4104 Serge 4945 
#define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
3031 serge 4946 
#define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
4947 
 
4948 
/* DDI Buffer Translations */
4949 
#define DDI_BUF_TRANS_A				0x64E00
4950 
#define DDI_BUF_TRANS_B				0x64E60
4951 
#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
4952 
 
4953 
/* Sideband Interface (SBI) is programmed indirectly, via
4954 
 * SBI_ADDR, which contains the register offset; and SBI_DATA,
4955 
 * which contains the payload */
4956 
#define SBI_ADDR				0xC6000
4957 
#define SBI_DATA				0xC6004
4958 
#define SBI_CTL_STAT			0xC6008
3243 Serge 4959 
#define  SBI_CTL_DEST_ICLK		(0x0<<16)
4960 
#define  SBI_CTL_DEST_MPHY		(0x1<<16)
4961 
#define  SBI_CTL_OP_IORD		(0x2<<8)
4962 
#define  SBI_CTL_OP_IOWR		(0x3<<8)
3031 serge 4963 
#define  SBI_CTL_OP_CRRD		(0x6<<8)
4964 
#define  SBI_CTL_OP_CRWR		(0x7<<8)
4965 
#define  SBI_RESPONSE_FAIL		(0x1<<1)
4966 
#define  SBI_RESPONSE_SUCCESS	(0x0<<1)
4967 
#define  SBI_BUSY				(0x1<<0)
4968 
#define  SBI_READY				(0x0<<0)
4969 
 
4970 
/* SBI offsets */
4971 
#define  SBI_SSCDIVINTPHASE6		0x0600
4972 
#define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	((0x7f)<<1)
4973 
#define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x)<<1)
4974 
#define   SBI_SSCDIVINTPHASE_INCVAL_MASK	((0x7f)<<8)
4975 
#define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x)<<8)
4976 
#define   SBI_SSCDIVINTPHASE_DIR(x)			((x)<<15)
4977 
#define   SBI_SSCDIVINTPHASE_PROPAGATE		(1<<0)
4978 
#define  SBI_SSCCTL					0x020c
4979 
#define  SBI_SSCCTL6				0x060C
3243 Serge 4980 
#define   SBI_SSCCTL_PATHALT			(1<<3)
3031 serge 4981 
#define   SBI_SSCCTL_DISABLE		(1<<0)
4982 
#define  SBI_SSCAUXDIV6				0x0610
4983 
#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)
4984 
#define  SBI_DBUFF0					0x2a00
4104 Serge 4985 
#define  SBI_GEN0				0x1f00
4986 
#define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1<<0)
3031 serge 4987 
 
4988 
/* LPT PIXCLK_GATE */
4989 
#define PIXCLK_GATE				0xC6020
4990 
#define  PIXCLK_GATE_UNGATE		(1<<0)
4991 
#define  PIXCLK_GATE_GATE		(0<<0)
4992 
 
4993 
/* SPLL */
4994 
#define SPLL_CTL				0x46020
4995 
#define  SPLL_PLL_ENABLE		(1<<31)
3243 Serge 4996 
#define  SPLL_PLL_SSC			(1<<28)
4997 
#define  SPLL_PLL_NON_SSC		(2<<28)
3031 serge 4998 
#define  SPLL_PLL_FREQ_810MHz	(0<<26)
4999 
#define  SPLL_PLL_FREQ_1350MHz	(1<<26)
5000 
 
5001 
/* WRPLL */
5002 
#define WRPLL_CTL1				0x46040
5003 
#define WRPLL_CTL2				0x46060
5004 
#define  WRPLL_PLL_ENABLE				(1<<31)
5005 
#define  WRPLL_PLL_SELECT_SSC			(0x01<<28)
3243 Serge 5006 
#define  WRPLL_PLL_SELECT_NON_SSC	(0x02<<28)
3031 serge 5007 
#define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)
5008 
/* WRPLL divider programming */
5009 
#define  WRPLL_DIVIDER_REFERENCE(x)		((x)<<0)
5010 
#define  WRPLL_DIVIDER_POST(x)			((x)<<8)
5011 
#define  WRPLL_DIVIDER_FEEDBACK(x)		((x)<<16)
5012 
 
5013 
/* Port clock selection */
5014 
#define PORT_CLK_SEL_A			0x46100
5015 
#define PORT_CLK_SEL_B			0x46104
5016 
#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
5017 
#define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
5018 
#define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
5019 
#define  PORT_CLK_SEL_LCPLL_810		(2<<29)
5020 
#define  PORT_CLK_SEL_SPLL			(3<<29)
5021 
#define  PORT_CLK_SEL_WRPLL1		(4<<29)
5022 
#define  PORT_CLK_SEL_WRPLL2		(5<<29)
3243 Serge 5023 
#define  PORT_CLK_SEL_NONE		(7<<29)
3031 serge 5024 
 
3243 Serge 5025 
/* Transcoder clock selection */
5026 
#define TRANS_CLK_SEL_A			0x46140
5027 
#define TRANS_CLK_SEL_B			0x46144
5028 
#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
5029 
/* For each transcoder, we need to select the corresponding port clock */
5030 
#define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
5031 
#define  TRANS_CLK_SEL_PORT(x)		((x+1)<<29)
3031 serge 5032 
 
3243 Serge 5033 
#define _TRANSA_MSA_MISC		0x60410
5034 
#define _TRANSB_MSA_MISC		0x61410
5035 
#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
5036 
					       _TRANSB_MSA_MISC)
5037 
#define  TRANS_MSA_SYNC_CLK		(1<<0)
5038 
#define  TRANS_MSA_6_BPC		(0<<5)
5039 
#define  TRANS_MSA_8_BPC		(1<<5)
5040 
#define  TRANS_MSA_10_BPC		(2<<5)
5041 
#define  TRANS_MSA_12_BPC		(3<<5)
5042 
#define  TRANS_MSA_16_BPC		(4<<5)
5043 
 
3031 serge 5044 
/* LCPLL Control */
5045 
#define LCPLL_CTL				0x130040
5046 
#define  LCPLL_PLL_DISABLE		(1<<31)
5047 
#define  LCPLL_PLL_LOCK			(1<<30)
3243 Serge 5048 
#define  LCPLL_CLK_FREQ_MASK		(3<<26)
5049 
#define  LCPLL_CLK_FREQ_450		(0<<26)
3031 serge 5050 
#define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
5051 
#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
4104 Serge 5052 
#define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
3243 Serge 5053 
#define  LCPLL_CD_SOURCE_FCLK		(1<<21)
4104 Serge 5054 
#define  LCPLL_CD_SOURCE_FCLK_DONE	(1<<19)
3031 serge 5055 
 
4104 Serge 5056 
#define D_COMP				(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
5057 
#define  D_COMP_RCOMP_IN_PROGRESS	(1<<9)
5058 
#define  D_COMP_COMP_FORCE		(1<<8)
5059 
#define  D_COMP_COMP_DISABLE		(1<<0)
5060 
 
3031 serge 5061 
/* Pipe WM_LINETIME - watermark line time */
5062 
#define PIPE_WM_LINETIME_A		0x45270
5063 
#define PIPE_WM_LINETIME_B		0x45274
5064 
#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5065 
					PIPE_WM_LINETIME_B)
5066 
#define   PIPE_WM_LINETIME_MASK		(0x1ff)
5067 
#define   PIPE_WM_LINETIME_TIME(x)			((x))
5068 
#define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
5069 
#define   PIPE_WM_LINETIME_IPS_LINETIME(x)		((x)<<16)
5070 
 
5071 
/* SFUSE_STRAP */
5072 
#define SFUSE_STRAP				0xc2014
5073 
#define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
5074 
#define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
5075 
#define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
5076 
 
4104 Serge 5077 
#define WM_MISC				0x45260
5078 
#define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
5079 
 
3031 serge 5080 
#define WM_DBG				0x45280
5081 
#define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
5082 
#define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
5083 
#define  WM_DBG_DISALLOW_SPRITE		(1<<2)
5084 
 
3480 Serge 5085 
/* pipe CSC */
5086 
#define _PIPE_A_CSC_COEFF_RY_GY	0x49010
5087 
#define _PIPE_A_CSC_COEFF_BY	0x49014
5088 
#define _PIPE_A_CSC_COEFF_RU_GU	0x49018
5089 
#define _PIPE_A_CSC_COEFF_BU	0x4901c
5090 
#define _PIPE_A_CSC_COEFF_RV_GV	0x49020
5091 
#define _PIPE_A_CSC_COEFF_BV	0x49024
5092 
#define _PIPE_A_CSC_MODE	0x49028
4104 Serge 5093 
#define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
5094 
#define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
5095 
#define   CSC_MODE_YUV_TO_RGB		(1 << 0)
3480 Serge 5096 
#define _PIPE_A_CSC_PREOFF_HI	0x49030
5097 
#define _PIPE_A_CSC_PREOFF_ME	0x49034
5098 
#define _PIPE_A_CSC_PREOFF_LO	0x49038
5099 
#define _PIPE_A_CSC_POSTOFF_HI	0x49040
5100 
#define _PIPE_A_CSC_POSTOFF_ME	0x49044
5101 
#define _PIPE_A_CSC_POSTOFF_LO	0x49048
5102 
 
5103 
#define _PIPE_B_CSC_COEFF_RY_GY	0x49110
5104 
#define _PIPE_B_CSC_COEFF_BY	0x49114
5105 
#define _PIPE_B_CSC_COEFF_RU_GU	0x49118
5106 
#define _PIPE_B_CSC_COEFF_BU	0x4911c
5107 
#define _PIPE_B_CSC_COEFF_RV_GV	0x49120
5108 
#define _PIPE_B_CSC_COEFF_BV	0x49124
5109 
#define _PIPE_B_CSC_MODE	0x49128
5110 
#define _PIPE_B_CSC_PREOFF_HI	0x49130
5111 
#define _PIPE_B_CSC_PREOFF_ME	0x49134
5112 
#define _PIPE_B_CSC_PREOFF_LO	0x49138
5113 
#define _PIPE_B_CSC_POSTOFF_HI	0x49140
5114 
#define _PIPE_B_CSC_POSTOFF_ME	0x49144
5115 
#define _PIPE_B_CSC_POSTOFF_LO	0x49148
5116 
 
5117 
#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
5118 
#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
5119 
#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
5120 
#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
5121 
#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
5122 
#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
5123 
#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
5124 
#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
5125 
#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
5126 
#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
5127 
#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
5128 
#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
5129 
#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
5130 
 
2325 Serge 5131 
#endif /* _I915_REG_H_ */