Subversion Repositories Kolibri OS

Rev

Rev 3480 | Rev 4104 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
2325 Serge 1
/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2
 * All Rights Reserved.
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the
6
 * "Software"), to deal in the Software without restriction, including
7
 * without limitation the rights to use, copy, modify, merge, publish,
8
 * distribute, sub license, and/or sell copies of the Software, and to
9
 * permit persons to whom the Software is furnished to do so, subject to
10
 * the following conditions:
11
 *
12
 * The above copyright notice and this permission notice (including the
13
 * next paragraph) shall be included in all copies or substantial portions
14
 * of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23
 */
24
 
25
#ifndef _I915_REG_H_
26
#define _I915_REG_H_
27
 
28
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
3243 Serge 29
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
2325 Serge 30
 
3031 serge 31
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32
 
33
#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
34
#define _MASKED_BIT_DISABLE(a) ((a) << 16)
35
 
2325 Serge 36
/*
37
 * The Bridge device's PCI config space has information about the
38
 * fb aperture size and the amount of pre-reserved memory.
39
 * This is all handled in the intel-gtt.ko module. i915.ko only
40
 * cares about the vga bit for the vga rbiter.
41
 */
42
#define INTEL_GMCH_CTRL		0x52
43
#define INTEL_GMCH_VGA_DISABLE  (1 << 1)
3243 Serge 44
#define SNB_GMCH_CTRL		0x50
45
#define    SNB_GMCH_GGMS_SHIFT	8 /* GTT Graphics Memory Size */
46
#define    SNB_GMCH_GGMS_MASK	0x3
47
#define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
48
#define    SNB_GMCH_GMS_MASK    0x1f
2325 Serge 49
 
3243 Serge 50
 
2325 Serge 51
/* PCI config space */
52
 
53
#define HPLLCC	0xc0 /* 855 only */
54
#define   GC_CLOCK_CONTROL_MASK		(0xf << 0)
55
#define   GC_CLOCK_133_200		(0 << 0)
56
#define   GC_CLOCK_100_200		(1 << 0)
57
#define   GC_CLOCK_100_133		(2 << 0)
58
#define   GC_CLOCK_166_250		(3 << 0)
59
#define GCFGC2	0xda
60
#define GCFGC	0xf0 /* 915+ only */
61
#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
62
#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
63
#define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
64
#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
65
#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
66
#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
67
#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
68
#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
69
#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
70
#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
71
#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
72
#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
73
#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
74
#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
75
#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
76
#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
77
#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
78
#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
79
#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
80
#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
81
#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
82
#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
83
#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
84
#define LBB	0xf4
85
 
86
/* Graphics reset regs */
87
#define I965_GDRST 0xc0 /* PCI config register */
88
#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
89
#define  GRDOM_FULL	(0<<2)
90
#define  GRDOM_RENDER	(1<<2)
91
#define  GRDOM_MEDIA	(3<<2)
3746 Serge 92
#define  GRDOM_MASK	(3<<2)
3031 serge 93
#define  GRDOM_RESET_ENABLE (1<<0)
2325 Serge 94
 
95
#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
96
#define   GEN6_MBC_SNPCR_SHIFT	21
97
#define   GEN6_MBC_SNPCR_MASK	(3<<21)
98
#define   GEN6_MBC_SNPCR_MAX	(0<<21)
99
#define   GEN6_MBC_SNPCR_MED	(1<<21)
100
#define   GEN6_MBC_SNPCR_LOW	(2<<21)
101
#define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
102
 
3031 serge 103
#define GEN6_MBCTL		0x0907c
104
#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
105
#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
106
#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
107
#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
108
#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
109
 
2325 Serge 110
#define GEN6_GDRST	0x941c
111
#define  GEN6_GRDOM_FULL		(1 << 0)
112
#define  GEN6_GRDOM_RENDER		(1 << 1)
113
#define  GEN6_GRDOM_MEDIA		(1 << 2)
114
#define  GEN6_GRDOM_BLT			(1 << 3)
115
 
3031 serge 116
#define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
117
#define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
118
#define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
119
#define   PP_DIR_DCLV_2G		0xffffffff
120
 
121
#define GAM_ECOCHK			0x4090
122
#define   ECOCHK_SNB_BIT		(1<<10)
3746 Serge 123
#define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
3031 serge 124
#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
125
#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
3746 Serge 126
#define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)
127
#define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)
128
#define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)
129
#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
130
#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
3031 serge 131
 
132
#define GAC_ECO_BITS			0x14090
3746 Serge 133
#define   ECOBITS_SNB_BIT		(1<<13)
3031 serge 134
#define   ECOBITS_PPGTT_CACHE64B	(3<<8)
135
#define   ECOBITS_PPGTT_CACHE4B		(0<<8)
136
 
137
#define GAB_CTL				0x24000
138
#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
139
 
2325 Serge 140
/* VGA stuff */
141
 
142
#define VGA_ST01_MDA 0x3ba
143
#define VGA_ST01_CGA 0x3da
144
 
145
#define VGA_MSR_WRITE 0x3c2
146
#define VGA_MSR_READ 0x3cc
147
#define   VGA_MSR_MEM_EN (1<<1)
148
#define   VGA_MSR_CGA_MODE (1<<0)
149
 
3480 Serge 150
/*
151
 * SR01 is the only VGA register touched on non-UMS setups.
152
 * VLV doesn't do UMS, so the sequencer index/data registers
153
 * are the only VGA registers which need to include
154
 * display_mmio_offset.
155
 */
156
#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
157
#define SR01			1
158
#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
2325 Serge 159
 
160
#define VGA_AR_INDEX 0x3c0
161
#define   VGA_AR_VID_EN (1<<5)
162
#define VGA_AR_DATA_WRITE 0x3c0
163
#define VGA_AR_DATA_READ 0x3c1
164
 
165
#define VGA_GR_INDEX 0x3ce
166
#define VGA_GR_DATA 0x3cf
167
/* GR05 */
168
#define   VGA_GR_MEM_READ_MODE_SHIFT 3
169
#define     VGA_GR_MEM_READ_MODE_PLANE 1
170
/* GR06 */
171
#define   VGA_GR_MEM_MODE_MASK 0xc
172
#define   VGA_GR_MEM_MODE_SHIFT 2
173
#define   VGA_GR_MEM_A0000_AFFFF 0
174
#define   VGA_GR_MEM_A0000_BFFFF 1
175
#define   VGA_GR_MEM_B0000_B7FFF 2
176
#define   VGA_GR_MEM_B0000_BFFFF 3
177
 
178
#define VGA_DACMASK 0x3c6
179
#define VGA_DACRX 0x3c7
180
#define VGA_DACWX 0x3c8
181
#define VGA_DACDATA 0x3c9
182
 
183
#define VGA_CR_INDEX_MDA 0x3b4
184
#define VGA_CR_DATA_MDA 0x3b5
185
#define VGA_CR_INDEX_CGA 0x3d4
186
#define VGA_CR_DATA_CGA 0x3d5
187
 
188
/*
189
 * Memory interface instructions used by the kernel
190
 */
191
#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
192
 
193
#define MI_NOOP			MI_INSTR(0, 0)
194
#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
195
#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
196
#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
197
#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
198
#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
199
#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
200
#define MI_FLUSH		MI_INSTR(0x04, 0)
201
#define   MI_READ_FLUSH		(1 << 0)
202
#define   MI_EXE_FLUSH		(1 << 1)
203
#define   MI_NO_WRITE_FLUSH	(1 << 2)
204
#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
205
#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
206
#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
207
#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
208
#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
209
#define   MI_SUSPEND_FLUSH_EN	(1<<0)
210
#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
2342 Serge 211
#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
2325 Serge 212
#define   MI_OVERLAY_CONTINUE	(0x0<<21)
213
#define   MI_OVERLAY_ON		(0x1<<21)
214
#define   MI_OVERLAY_OFF	(0x2<<21)
215
#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
216
#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
217
#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
218
#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
3031 serge 219
/* IVB has funny definitions for which plane to flip. */
220
#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
221
#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
222
#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
223
#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
224
#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
225
#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
226
#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
227
#define   MI_ARB_ENABLE			(1<<0)
228
#define   MI_ARB_DISABLE		(0<<0)
229
 
2325 Serge 230
#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
231
#define   MI_MM_SPACE_GTT		(1<<8)
232
#define   MI_MM_SPACE_PHYSICAL		(0<<8)
233
#define   MI_SAVE_EXT_STATE_EN		(1<<3)
234
#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
235
#define   MI_FORCE_RESTORE		(1<<1)
236
#define   MI_RESTORE_INHIBIT		(1<<0)
237
#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
238
#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
239
#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
240
#define   MI_STORE_DWORD_INDEX_SHIFT 2
241
/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
242
 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
243
 *   simply ignores the register load under certain conditions.
244
 * - One can actually load arbitrary many arbitrary registers: Simply issue x
245
 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
246
 */
247
#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
248
#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
3243 Serge 249
#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
2325 Serge 250
#define   MI_INVALIDATE_TLB	(1<<18)
3243 Serge 251
#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
2325 Serge 252
#define   MI_INVALIDATE_BSD	(1<<7)
3243 Serge 253
#define   MI_FLUSH_DW_USE_GTT		(1<<2)
254
#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
2325 Serge 255
#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
256
#define   MI_BATCH_NON_SECURE	(1)
3243 Serge 257
/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
2325 Serge 258
#define   MI_BATCH_NON_SECURE_I965 (1<<8)
3243 Serge 259
#define   MI_BATCH_PPGTT_HSW		(1<<8)
260
#define   MI_BATCH_NON_SECURE_HSW 	(1<<13)
2325 Serge 261
#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
3031 serge 262
#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
2325 Serge 263
#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */
264
#define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
265
#define  MI_SEMAPHORE_UPDATE	    (1<<21)
266
#define  MI_SEMAPHORE_COMPARE	    (1<<20)
267
#define  MI_SEMAPHORE_REGISTER	    (1<<18)
2342 Serge 268
#define  MI_SEMAPHORE_SYNC_RV	    (2<<16)
269
#define  MI_SEMAPHORE_SYNC_RB	    (0<<16)
270
#define  MI_SEMAPHORE_SYNC_VR	    (0<<16)
271
#define  MI_SEMAPHORE_SYNC_VB	    (2<<16)
272
#define  MI_SEMAPHORE_SYNC_BR	    (2<<16)
273
#define  MI_SEMAPHORE_SYNC_BV	    (0<<16)
274
#define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)
2325 Serge 275
/*
276
 * 3D instructions used by the kernel
277
 */
278
#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
279
 
280
#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
281
#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
282
#define   SC_UPDATE_SCISSOR       (0x1<<1)
283
#define   SC_ENABLE_MASK          (0x1<<0)
284
#define   SC_ENABLE               (0x1<<0)
285
#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
286
#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
287
#define   SCI_YMIN_MASK      (0xffff<<16)
288
#define   SCI_XMIN_MASK      (0xffff<<0)
289
#define   SCI_YMAX_MASK      (0xffff<<16)
290
#define   SCI_XMAX_MASK      (0xffff<<0)
291
#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
292
#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
293
#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
294
#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
295
#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
296
#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
297
#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
298
#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
299
#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
300
#define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
301
#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
302
#define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
303
#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
304
#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
305
#define   BLT_DEPTH_8			(0<<24)
306
#define   BLT_DEPTH_16_565		(1<<24)
307
#define   BLT_DEPTH_16_1555		(2<<24)
308
#define   BLT_DEPTH_32			(3<<24)
309
#define   BLT_ROP_GXCOPY		(0xcc<<16)
310
#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
311
#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
312
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
313
#define   ASYNC_FLIP                (1<<22)
314
#define   DISPLAY_PLANE_A           (0<<20)
315
#define   DISPLAY_PLANE_B           (1<<20)
2342 Serge 316
#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
3480 Serge 317
#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
2342 Serge 318
#define   PIPE_CONTROL_CS_STALL				(1<<20)
3031 serge 319
#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
2325 Serge 320
#define   PIPE_CONTROL_QW_WRITE	(1<<14)
321
#define   PIPE_CONTROL_DEPTH_STALL (1<<13)
2342 Serge 322
#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
323
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
324
#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
325
#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
326
#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
2325 Serge 327
#define   PIPE_CONTROL_NOTIFY	(1<<8)
2342 Serge 328
#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
329
#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
330
#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
331
#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
332
#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
2325 Serge 333
#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
334
 
335
 
336
/*
337
 * Reset registers
338
 */
339
#define DEBUG_RESET_I830		0x6070
340
#define  DEBUG_RESET_FULL		(1<<7)
341
#define  DEBUG_RESET_RENDER		(1<<8)
342
#define  DEBUG_RESET_DISPLAY		(1<<9)
343
 
3031 serge 344
/*
345
 * DPIO - a special bus for various display related registers to hide behind:
346
 *  0x800c: m1, m2, n, p1, p2, k dividers
347
 *  0x8014: REF and SFR select
348
 *  0x8014: N divider, VCO select
349
 *  0x801c/3c: core clock bits
350
 *  0x8048/68: low pass filter coefficients
351
 *  0x8100: fast clock controls
3480 Serge 352
 *
353
 * DPIO is VLV only.
3031 serge 354
 */
3480 Serge 355
#define DPIO_PKT			(VLV_DISPLAY_BASE + 0x2100)
3031 serge 356
#define  DPIO_RID			(0<<24)
357
#define  DPIO_OP_WRITE			(1<<16)
358
#define  DPIO_OP_READ			(0<<16)
359
#define  DPIO_PORTID			(0x12<<8)
360
#define  DPIO_BYTE			(0xf<<4)
361
#define  DPIO_BUSY			(1<<0) /* status only */
3480 Serge 362
#define DPIO_DATA			(VLV_DISPLAY_BASE + 0x2104)
363
#define DPIO_REG			(VLV_DISPLAY_BASE + 0x2108)
364
#define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
3031 serge 365
#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
366
#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
367
#define  DPIO_SFR_BYPASS		(1<<1)
368
#define  DPIO_RESET			(1<<0)
2325 Serge 369
 
3031 serge 370
#define _DPIO_DIV_A			0x800c
371
#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
372
#define   DPIO_K_SHIFT			(24) /* 4 bits */
373
#define   DPIO_P1_SHIFT			(21) /* 3 bits */
374
#define   DPIO_P2_SHIFT			(16) /* 5 bits */
375
#define   DPIO_N_SHIFT			(12) /* 4 bits */
376
#define   DPIO_ENABLE_CALIBRATION	(1<<11)
377
#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
378
#define   DPIO_M2DIV_MASK		0xff
379
#define _DPIO_DIV_B			0x802c
380
#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
381
 
382
#define _DPIO_REFSFR_A			0x8014
383
#define   DPIO_REFSEL_OVERRIDE		27
384
#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
385
#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
386
#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
3243 Serge 387
#define   DPIO_PLL_REFCLK_SEL_MASK	3
3031 serge 388
#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
389
#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
390
#define _DPIO_REFSFR_B			0x8034
391
#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
392
 
393
#define _DPIO_CORE_CLK_A		0x801c
394
#define _DPIO_CORE_CLK_B		0x803c
395
#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
396
 
397
#define _DPIO_LFP_COEFF_A		0x8048
398
#define _DPIO_LFP_COEFF_B		0x8068
399
#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
400
 
401
#define DPIO_FASTCLK_DISABLE		0x8100
402
 
3243 Serge 403
#define DPIO_DATA_CHANNEL1		0x8220
404
#define DPIO_DATA_CHANNEL2		0x8420
405
 
2325 Serge 406
/*
407
 * Fence registers
408
 */
409
#define FENCE_REG_830_0			0x2000
410
#define FENCE_REG_945_8			0x3000
411
#define   I830_FENCE_START_MASK		0x07f80000
412
#define   I830_FENCE_TILING_Y_SHIFT	12
413
#define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
414
#define   I830_FENCE_PITCH_SHIFT	4
415
#define   I830_FENCE_REG_VALID		(1<<0)
416
#define   I915_FENCE_MAX_PITCH_VAL	4
417
#define   I830_FENCE_MAX_PITCH_VAL	6
418
#define   I830_FENCE_MAX_SIZE_VAL	(1<<8)
419
 
420
#define   I915_FENCE_START_MASK		0x0ff00000
421
#define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
422
 
423
#define FENCE_REG_965_0			0x03000
424
#define   I965_FENCE_PITCH_SHIFT	2
425
#define   I965_FENCE_TILING_Y_SHIFT	1
426
#define   I965_FENCE_REG_VALID		(1<<0)
427
#define   I965_FENCE_MAX_PITCH_VAL	0x0400
428
 
429
#define FENCE_REG_SANDYBRIDGE_0		0x100000
430
#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
3746 Serge 431
#define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
2325 Serge 432
 
3031 serge 433
/* control register for cpu gtt access */
434
#define TILECTL				0x101000
435
#define   TILECTL_SWZCTL			(1 << 0)
436
#define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
437
#define   TILECTL_BACKSNOOP_DIS		(1 << 3)
438
 
2325 Serge 439
/*
440
 * Instruction and interrupt control regs
441
 */
442
#define PGTBL_ER	0x02024
443
#define RENDER_RING_BASE	0x02000
444
#define BSD_RING_BASE		0x04000
445
#define GEN6_BSD_RING_BASE	0x12000
446
#define BLT_RING_BASE		0x22000
447
#define RING_TAIL(base)		((base)+0x30)
448
#define RING_HEAD(base)		((base)+0x34)
449
#define RING_START(base)	((base)+0x38)
450
#define RING_CTL(base)		((base)+0x3c)
451
#define RING_SYNC_0(base)	((base)+0x40)
452
#define RING_SYNC_1(base)	((base)+0x44)
2342 Serge 453
#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
454
#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
455
#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
456
#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
457
#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
458
#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2325 Serge 459
#define RING_MAX_IDLE(base)	((base)+0x54)
460
#define RING_HWS_PGA(base)	((base)+0x80)
461
#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
3031 serge 462
#define ARB_MODE		0x04030
463
#define   ARB_MODE_SWIZZLE_SNB	(1<<4)
464
#define   ARB_MODE_SWIZZLE_IVB	(1<<5)
2325 Serge 465
#define RENDER_HWS_PGA_GEN7	(0x04080)
3031 serge 466
#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
467
#define DONE_REG		0x40b0
2325 Serge 468
#define BSD_HWS_PGA_GEN7	(0x04180)
469
#define BLT_HWS_PGA_GEN7	(0x04280)
470
#define RING_ACTHD(base)	((base)+0x74)
471
#define RING_NOPID(base)	((base)+0x94)
472
#define RING_IMR(base)		((base)+0xa8)
3031 serge 473
#define RING_TIMESTAMP(base)	((base)+0x358)
2325 Serge 474
#define   TAIL_ADDR		0x001FFFF8
475
#define   HEAD_WRAP_COUNT	0xFFE00000
476
#define   HEAD_WRAP_ONE		0x00200000
477
#define   HEAD_ADDR		0x001FFFFC
478
#define   RING_NR_PAGES		0x001FF000
479
#define   RING_REPORT_MASK	0x00000006
480
#define   RING_REPORT_64K	0x00000002
481
#define   RING_REPORT_128K	0x00000004
482
#define   RING_NO_REPORT	0x00000000
483
#define   RING_VALID_MASK	0x00000001
484
#define   RING_VALID		0x00000001
485
#define   RING_INVALID		0x00000000
486
#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
487
#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
488
#define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
489
#if 0
490
#define PRB0_TAIL	0x02030
491
#define PRB0_HEAD	0x02034
492
#define PRB0_START	0x02038
493
#define PRB0_CTL	0x0203c
494
#define PRB1_TAIL	0x02040 /* 915+ only */
495
#define PRB1_HEAD	0x02044 /* 915+ only */
496
#define PRB1_START	0x02048 /* 915+ only */
497
#define PRB1_CTL	0x0204c /* 915+ only */
498
#endif
499
#define IPEIR_I965	0x02064
500
#define IPEHR_I965	0x02068
501
#define INSTDONE_I965	0x0206c
3031 serge 502
#define GEN7_INSTDONE_1		0x0206c
503
#define GEN7_SC_INSTDONE	0x07100
504
#define GEN7_SAMPLER_INSTDONE	0x0e160
505
#define GEN7_ROW_INSTDONE	0x0e164
506
#define I915_NUM_INSTDONE_REG	4
507
#define RING_IPEIR(base)	((base)+0x64)
508
#define RING_IPEHR(base)	((base)+0x68)
509
#define RING_INSTDONE(base)	((base)+0x6c)
510
#define RING_INSTPS(base)	((base)+0x70)
511
#define RING_DMA_FADD(base)	((base)+0x78)
512
#define RING_INSTPM(base)	((base)+0xc0)
2325 Serge 513
#define INSTPS		0x02070 /* 965+ only */
514
#define INSTDONE1	0x0207c /* 965+ only */
515
#define ACTHD_I965	0x02074
516
#define HWS_PGA		0x02080
517
#define HWS_ADDRESS_MASK	0xfffff000
518
#define HWS_START_ADDRESS_SHIFT	4
519
#define PWRCTXA		0x2088 /* 965GM+ only */
520
#define   PWRCTX_EN	(1<<0)
521
#define IPEIR		0x02088
522
#define IPEHR		0x0208c
523
#define INSTDONE	0x02090
524
#define NOPID		0x02094
525
#define HWSTAM		0x02098
3031 serge 526
#define DMA_FADD_I8XX	0x020d0
2325 Serge 527
 
528
#define ERROR_GEN6	0x040a0
3031 serge 529
#define GEN7_ERR_INT	0x44040
530
#define   ERR_INT_MMIO_UNCLAIMED (1<<13)
2325 Serge 531
 
3746 Serge 532
#define FPGA_DBG		0x42300
533
#define   FPGA_DBG_RM_NOCLAIM	(1<<31)
534
 
3243 Serge 535
#define DERRMR		0x44050
536
 
2325 Serge 537
/* GM45+ chicken bits -- debug workaround bits that may be required
538
 * for various sorts of correct behavior.  The top 16 bits of each are
539
 * the enables for writing to the corresponding low bit.
540
 */
541
#define _3D_CHICKEN	0x02084
3243 Serge 542
#define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
2325 Serge 543
#define _3D_CHICKEN2	0x0208c
544
/* Disables pipelining of read flushes past the SF-WIZ interface.
545
 * Required on all Ironlake steppings according to the B-Spec, but the
546
 * particular danger of not doing so is not specified.
547
 */
548
# define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
549
#define _3D_CHICKEN3	0x02090
3243 Serge 550
#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
3031 serge 551
#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
2325 Serge 552
 
553
#define MI_MODE		0x0209c
554
# define VS_TIMER_DISPATCH				(1 << 6)
3031 serge 555
# define MI_FLUSH_ENABLE				(1 << 12)
3243 Serge 556
# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
2325 Serge 557
 
3031 serge 558
#define GEN6_GT_MODE	0x20d0
559
#define   GEN6_GT_MODE_HI	(1 << 9)
3243 Serge 560
#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
3031 serge 561
 
2325 Serge 562
#define GFX_MODE	0x02520
563
#define GFX_MODE_GEN7	0x0229c
3031 serge 564
#define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
2325 Serge 565
#define   GFX_RUN_LIST_ENABLE		(1<<15)
566
#define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)
567
#define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
568
#define   GFX_REPLAY_MODE		(1<<11)
569
#define   GFX_PSMI_GRANULARITY		(1<<10)
570
#define   GFX_PPGTT_ENABLE		(1<<9)
571
 
3031 serge 572
#define VLV_DISPLAY_BASE 0x180000
2325 Serge 573
 
574
#define SCPD0		0x0209c /* 915+ only */
575
#define IER		0x020a0
576
#define IIR		0x020a4
577
#define IMR		0x020a8
578
#define ISR		0x020ac
3480 Serge 579
#define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
3243 Serge 580
#define   GCFG_DIS		(1<<8)
3480 Serge 581
#define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
582
#define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
583
#define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
584
#define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
585
#define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
2325 Serge 586
#define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
587
#define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
588
#define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
589
#define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
590
#define   I915_HWB_OOM_INTERRUPT			(1<<13)
591
#define   I915_SYNC_STATUS_INTERRUPT			(1<<12)
592
#define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
593
#define   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
594
#define   I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
595
#define   I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
596
#define   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
597
#define   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
598
#define   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
599
#define   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
600
#define   I915_DEBUG_INTERRUPT				(1<<2)
601
#define   I915_USER_INTERRUPT				(1<<1)
602
#define   I915_ASLE_INTERRUPT				(1<<0)
603
#define   I915_BSD_USER_INTERRUPT                      (1<<25)
3746 Serge 604
#define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
2325 Serge 605
#define EIR		0x020b0
606
#define EMR		0x020b4
607
#define ESR		0x020b8
608
#define   GM45_ERROR_PAGE_TABLE				(1<<5)
609
#define   GM45_ERROR_MEM_PRIV				(1<<4)
610
#define   I915_ERROR_PAGE_TABLE				(1<<4)
611
#define   GM45_ERROR_CP_PRIV				(1<<3)
612
#define   I915_ERROR_MEMORY_REFRESH			(1<<1)
613
#define   I915_ERROR_INSTRUCTION			(1<<0)
614
#define INSTPM	        0x020c0
615
#define   INSTPM_SELF_EN (1<<12) /* 915GM only */
616
#define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
617
					will not assert AGPBUSY# and will only
618
					be delivered when out of C3. */
2342 Serge 619
#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
2325 Serge 620
#define ACTHD	        0x020c8
621
#define FW_BLC		0x020d8
622
#define FW_BLC2		0x020dc
623
#define FW_BLC_SELF	0x020e0 /* 915+ only */
624
#define   FW_BLC_SELF_EN_MASK      (1<<31)
625
#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
626
#define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
627
#define MM_BURST_LENGTH     0x00700000
628
#define MM_FIFO_WATERMARK   0x0001F000
629
#define LM_BURST_LENGTH     0x00000700
630
#define LM_FIFO_WATERMARK   0x0000001F
631
#define MI_ARB_STATE	0x020e4 /* 915+ only */
632
 
633
/* Make render/texture TLB fetches lower priorty than associated data
634
 *   fetches. This is not turned on by default
635
 */
636
#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
637
 
638
/* Isoch request wait on GTT enable (Display A/B/C streams).
639
 * Make isoch requests stall on the TLB update. May cause
640
 * display underruns (test mode only)
641
 */
642
#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
643
 
644
/* Block grant count for isoch requests when block count is
645
 * set to a finite value.
646
 */
647
#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
648
#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
649
#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
650
#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
651
#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
652
 
653
/* Enable render writes to complete in C2/C3/C4 power states.
654
 * If this isn't enabled, render writes are prevented in low
655
 * power states. That seems bad to me.
656
 */
657
#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
658
 
659
/* This acknowledges an async flip immediately instead
660
 * of waiting for 2TLB fetches.
661
 */
662
#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
663
 
664
/* Enables non-sequential data reads through arbiter
665
 */
666
#define   MI_ARB_DUAL_DATA_PHASE_DISABLE       	(1 << 9)
667
 
668
/* Disable FSB snooping of cacheable write cycles from binner/render
669
 * command stream
670
 */
671
#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
672
 
673
/* Arbiter time slice for non-isoch streams */
674
#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
675
#define   MI_ARB_TIME_SLICE_1			(0 << 5)
676
#define   MI_ARB_TIME_SLICE_2			(1 << 5)
677
#define   MI_ARB_TIME_SLICE_4			(2 << 5)
678
#define   MI_ARB_TIME_SLICE_6			(3 << 5)
679
#define   MI_ARB_TIME_SLICE_8			(4 << 5)
680
#define   MI_ARB_TIME_SLICE_10			(5 << 5)
681
#define   MI_ARB_TIME_SLICE_14			(6 << 5)
682
#define   MI_ARB_TIME_SLICE_16			(7 << 5)
683
 
684
/* Low priority grace period page size */
685
#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
686
#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
687
 
688
/* Disable display A/B trickle feed */
689
#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
690
 
691
/* Set display plane priority */
692
#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
693
#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
694
 
695
#define CACHE_MODE_0	0x02120 /* 915+ only */
3243 Serge 696
#define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
2325 Serge 697
#define   CM0_IZ_OPT_DISABLE      (1<<6)
698
#define   CM0_ZR_OPT_DISABLE      (1<<5)
3031 serge 699
#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
2325 Serge 700
#define   CM0_DEPTH_EVICT_DISABLE (1<<4)
701
#define   CM0_COLOR_EVICT_DISABLE (1<<3)
702
#define   CM0_DEPTH_WRITE_DISABLE (1<<1)
703
#define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
704
#define BB_ADDR		0x02140 /* 8 bytes */
705
#define GFX_FLSH_CNTL	0x02170 /* 915+ only */
3243 Serge 706
#define GFX_FLSH_CNTL_GEN6	0x101008
707
#define   GFX_FLSH_CNTL_EN	(1<<0)
2325 Serge 708
#define ECOSKPD		0x021d0
709
#define   ECO_GATING_CX_ONLY	(1<<3)
710
#define   ECO_FLIP_DONE		(1<<0)
711
 
3031 serge 712
#define CACHE_MODE_1		0x7004 /* IVB+ */
713
#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
714
 
715
/* GEN6 interrupt control
716
 * Note that the per-ring interrupt bits do alias with the global interrupt bits
717
 * in GTIMR. */
2325 Serge 718
#define GEN6_RENDER_HWSTAM	0x2098
719
#define GEN6_RENDER_IMR		0x20a8
720
#define   GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT		(1 << 8)
721
#define   GEN6_RENDER_PPGTT_PAGE_FAULT			(1 << 7)
722
#define   GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED		(1 << 6)
723
#define   GEN6_RENDER_L3_PARITY_ERROR			(1 << 5)
724
#define   GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT	(1 << 4)
725
#define   GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR	(1 << 3)
726
#define   GEN6_RENDER_SYNC_STATUS			(1 << 2)
727
#define   GEN6_RENDER_DEBUG_INTERRUPT			(1 << 1)
728
#define   GEN6_RENDER_USER_INTERRUPT			(1 << 0)
729
 
730
#define GEN6_BLITTER_HWSTAM	0x22098
731
#define GEN6_BLITTER_IMR	0x220a8
732
#define   GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT	(1 << 26)
733
#define   GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR	(1 << 25)
734
#define   GEN6_BLITTER_SYNC_STATUS			(1 << 24)
735
#define   GEN6_BLITTER_USER_INTERRUPT			(1 << 22)
736
 
737
#define GEN6_BLITTER_ECOSKPD	0x221d0
738
#define   GEN6_BLITTER_LOCK_SHIFT			16
739
#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
740
 
741
#define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
3031 serge 742
#define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
743
#define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
744
#define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
745
#define   GEN6_BSD_GO_INDICATOR		(1 << 4)
2325 Serge 746
 
747
#define GEN6_BSD_HWSTAM			0x12098
748
#define GEN6_BSD_IMR			0x120a8
749
#define   GEN6_BSD_USER_INTERRUPT	(1 << 12)
750
 
751
#define GEN6_BSD_RNCID			0x12198
752
 
3031 serge 753
#define GEN7_FF_THREAD_MODE		0x20a0
754
#define   GEN7_FF_SCHED_MASK		0x0077070
755
#define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
756
#define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
757
#define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
758
#define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */
3480 Serge 759
#define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
3031 serge 760
#define   GEN7_FF_VS_SCHED_HS1		(0x5<<12)
761
#define   GEN7_FF_VS_SCHED_HS0		(0x3<<12)
762
#define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1<<12) /* Default */
763
#define   GEN7_FF_VS_SCHED_HW		(0x0<<12)
764
#define   GEN7_FF_DS_SCHED_HS1		(0x5<<4)
765
#define   GEN7_FF_DS_SCHED_HS0		(0x3<<4)
766
#define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1<<4)  /* Default */
767
#define   GEN7_FF_DS_SCHED_HW		(0x0<<4)
768
 
2325 Serge 769
/*
770
 * Framebuffer compression (915+ only)
771
 */
772
 
773
#define FBC_CFB_BASE		0x03200 /* 4k page aligned */
774
#define FBC_LL_BASE		0x03204 /* 4k page aligned */
775
#define FBC_CONTROL		0x03208
776
#define   FBC_CTL_EN		(1<<31)
777
#define   FBC_CTL_PERIODIC	(1<<30)
778
#define   FBC_CTL_INTERVAL_SHIFT (16)
779
#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
780
#define   FBC_CTL_C3_IDLE	(1<<13)
781
#define   FBC_CTL_STRIDE_SHIFT	(5)
782
#define   FBC_CTL_FENCENO	(1<<0)
783
#define FBC_COMMAND		0x0320c
784
#define   FBC_CMD_COMPRESS	(1<<0)
785
#define FBC_STATUS		0x03210
786
#define   FBC_STAT_COMPRESSING	(1<<31)
787
#define   FBC_STAT_COMPRESSED	(1<<30)
788
#define   FBC_STAT_MODIFIED	(1<<29)
789
#define   FBC_STAT_CURRENT_LINE	(1<<0)
790
#define FBC_CONTROL2		0x03214
791
#define   FBC_CTL_FENCE_DBL	(0<<4)
792
#define   FBC_CTL_IDLE_IMM	(0<<2)
793
#define   FBC_CTL_IDLE_FULL	(1<<2)
794
#define   FBC_CTL_IDLE_LINE	(2<<2)
795
#define   FBC_CTL_IDLE_DEBUG	(3<<2)
796
#define   FBC_CTL_CPU_FENCE	(1<<1)
797
#define   FBC_CTL_PLANEA	(0<<0)
798
#define   FBC_CTL_PLANEB	(1<<0)
799
#define FBC_FENCE_OFF		0x0321b
800
#define FBC_TAG			0x03300
801
 
802
#define FBC_LL_SIZE		(1536)
803
 
804
/* Framebuffer compression for GM45+ */
805
#define DPFC_CB_BASE		0x3200
806
#define DPFC_CONTROL		0x3208
807
#define   DPFC_CTL_EN		(1<<31)
808
#define   DPFC_CTL_PLANEA	(0<<30)
809
#define   DPFC_CTL_PLANEB	(1<<30)
810
#define   DPFC_CTL_FENCE_EN	(1<<29)
811
#define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
812
#define   DPFC_SR_EN		(1<<10)
813
#define   DPFC_CTL_LIMIT_1X	(0<<6)
814
#define   DPFC_CTL_LIMIT_2X	(1<<6)
815
#define   DPFC_CTL_LIMIT_4X	(2<<6)
816
#define DPFC_RECOMP_CTL		0x320c
817
#define   DPFC_RECOMP_STALL_EN	(1<<27)
818
#define   DPFC_RECOMP_STALL_WM_SHIFT (16)
819
#define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
820
#define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
821
#define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
822
#define DPFC_STATUS		0x3210
823
#define   DPFC_INVAL_SEG_SHIFT  (16)
824
#define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
825
#define   DPFC_COMP_SEG_SHIFT	(0)
826
#define   DPFC_COMP_SEG_MASK	(0x000003ff)
827
#define DPFC_STATUS2		0x3214
828
#define DPFC_FENCE_YOFF		0x3218
829
#define DPFC_CHICKEN		0x3224
830
#define   DPFC_HT_MODIFY	(1<<31)
831
 
832
/* Framebuffer compression for Ironlake */
833
#define ILK_DPFC_CB_BASE	0x43200
834
#define ILK_DPFC_CONTROL	0x43208
835
/* The bit 28-8 is reserved */
836
#define   DPFC_RESERVED		(0x1FFFFF00)
837
#define ILK_DPFC_RECOMP_CTL	0x4320c
838
#define ILK_DPFC_STATUS		0x43210
839
#define ILK_DPFC_FENCE_YOFF	0x43218
840
#define ILK_DPFC_CHICKEN	0x43224
841
#define ILK_FBC_RT_BASE		0x2128
842
#define   ILK_FBC_RT_VALID	(1<<0)
843
 
844
#define ILK_DISPLAY_CHICKEN1	0x42000
845
#define   ILK_FBCQ_DIS		(1<<22)
846
#define   ILK_PABSTRETCH_DIS 	(1<<21)
847
 
848
 
849
/*
850
 * Framebuffer compression for Sandybridge
851
 *
852
 * The following two registers are of type GTTMMADR
853
 */
854
#define SNB_DPFC_CTL_SA		0x100100
855
#define   SNB_CPU_FENCE_ENABLE	(1<<29)
856
#define DPFC_CPU_FENCE_OFFSET	0x100104
857
 
858
 
859
/*
860
 * GPIO regs
861
 */
862
#define GPIOA			0x5010
863
#define GPIOB			0x5014
864
#define GPIOC			0x5018
865
#define GPIOD			0x501c
866
#define GPIOE			0x5020
867
#define GPIOF			0x5024
868
#define GPIOG			0x5028
869
#define GPIOH			0x502c
870
# define GPIO_CLOCK_DIR_MASK		(1 << 0)
871
# define GPIO_CLOCK_DIR_IN		(0 << 1)
872
# define GPIO_CLOCK_DIR_OUT		(1 << 1)
873
# define GPIO_CLOCK_VAL_MASK		(1 << 2)
874
# define GPIO_CLOCK_VAL_OUT		(1 << 3)
875
# define GPIO_CLOCK_VAL_IN		(1 << 4)
876
# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
877
# define GPIO_DATA_DIR_MASK		(1 << 8)
878
# define GPIO_DATA_DIR_IN		(0 << 9)
879
# define GPIO_DATA_DIR_OUT		(1 << 9)
880
# define GPIO_DATA_VAL_MASK		(1 << 10)
881
# define GPIO_DATA_VAL_OUT		(1 << 11)
882
# define GPIO_DATA_VAL_IN		(1 << 12)
883
# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
884
 
885
#define GMBUS0			0x5100 /* clock/port select */
886
#define   GMBUS_RATE_100KHZ	(0<<8)
887
#define   GMBUS_RATE_50KHZ	(1<<8)
888
#define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
889
#define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
890
#define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
891
#define   GMBUS_PORT_DISABLED	0
892
#define   GMBUS_PORT_SSC	1
893
#define   GMBUS_PORT_VGADDC	2
894
#define   GMBUS_PORT_PANEL	3
895
#define   GMBUS_PORT_DPC	4 /* HDMIC */
896
#define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
3031 serge 897
#define   GMBUS_PORT_DPD	6 /* HDMID */
898
#define   GMBUS_PORT_RESERVED	7 /* 7 reserved */
899
#define   GMBUS_NUM_PORTS	(GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
2325 Serge 900
#define GMBUS1			0x5104 /* command/status */
901
#define   GMBUS_SW_CLR_INT	(1<<31)
902
#define   GMBUS_SW_RDY		(1<<30)
903
#define   GMBUS_ENT		(1<<29) /* enable timeout */
904
#define   GMBUS_CYCLE_NONE	(0<<25)
905
#define   GMBUS_CYCLE_WAIT	(1<<25)
906
#define   GMBUS_CYCLE_INDEX	(2<<25)
907
#define   GMBUS_CYCLE_STOP	(4<<25)
908
#define   GMBUS_BYTE_COUNT_SHIFT 16
909
#define   GMBUS_SLAVE_INDEX_SHIFT 8
910
#define   GMBUS_SLAVE_ADDR_SHIFT 1
911
#define   GMBUS_SLAVE_READ	(1<<0)
912
#define   GMBUS_SLAVE_WRITE	(0<<0)
913
#define GMBUS2			0x5108 /* status */
914
#define   GMBUS_INUSE		(1<<15)
915
#define   GMBUS_HW_WAIT_PHASE	(1<<14)
916
#define   GMBUS_STALL_TIMEOUT	(1<<13)
917
#define   GMBUS_INT		(1<<12)
918
#define   GMBUS_HW_RDY		(1<<11)
919
#define   GMBUS_SATOER		(1<<10)
920
#define   GMBUS_ACTIVE		(1<<9)
921
#define GMBUS3			0x510c /* data buffer bytes 3-0 */
922
#define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
923
#define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
924
#define   GMBUS_NAK_EN		(1<<3)
925
#define   GMBUS_IDLE_EN		(1<<2)
926
#define   GMBUS_HW_WAIT_EN	(1<<1)
927
#define   GMBUS_HW_RDY_EN	(1<<0)
928
#define GMBUS5			0x5120 /* byte index */
929
#define   GMBUS_2BYTE_INDEX_EN	(1<<31)
930
 
931
/*
932
 * Clock control & power management
933
 */
934
 
935
#define VGA0	0x6000
936
#define VGA1	0x6004
937
#define VGA_PD	0x6010
938
#define   VGA0_PD_P2_DIV_4	(1 << 7)
939
#define   VGA0_PD_P1_DIV_2	(1 << 5)
940
#define   VGA0_PD_P1_SHIFT	0
941
#define   VGA0_PD_P1_MASK	(0x1f << 0)
942
#define   VGA1_PD_P2_DIV_4	(1 << 15)
943
#define   VGA1_PD_P1_DIV_2	(1 << 13)
944
#define   VGA1_PD_P1_SHIFT	8
945
#define   VGA1_PD_P1_MASK	(0x1f << 8)
3480 Serge 946
#define _DPLL_A	(dev_priv->info->display_mmio_offset + 0x6014)
947
#define _DPLL_B	(dev_priv->info->display_mmio_offset + 0x6018)
2325 Serge 948
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
949
#define   DPLL_VCO_ENABLE		(1 << 31)
950
#define   DPLL_DVO_HIGH_SPEED		(1 << 30)
3031 serge 951
#define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
2325 Serge 952
#define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
3031 serge 953
#define   DPLL_REFA_CLK_ENABLE_VLV	(1 << 29)
2325 Serge 954
#define   DPLL_VGA_MODE_DIS		(1 << 28)
955
#define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
956
#define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
957
#define   DPLL_MODE_MASK		(3 << 26)
958
#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
959
#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
960
#define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
961
#define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
962
#define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
963
#define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
964
#define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
3031 serge 965
#define   DPLL_LOCK_VLV			(1<<15)
966
#define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
2325 Serge 967
 
968
#define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
969
/*
970
 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
971
 * this field (only one bit may be set).
972
 */
973
#define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
974
#define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
975
#define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
976
/* i830, required in DVO non-gang */
977
#define   PLL_P2_DIVIDE_BY_4		(1 << 23)
978
#define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
979
#define   PLL_REF_INPUT_DREFCLK		(0 << 13)
980
#define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
981
#define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
982
#define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
983
#define   PLL_REF_INPUT_MASK		(3 << 13)
984
#define   PLL_LOAD_PULSE_PHASE_SHIFT		9
985
/* Ironlake */
986
# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
987
# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
988
# define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
989
# define DPLL_FPA1_P1_POST_DIV_SHIFT            0
990
# define DPLL_FPA1_P1_POST_DIV_MASK             0xff
991
 
992
/*
993
 * Parallel to Serial Load Pulse phase selection.
994
 * Selects the phase for the 10X DPLL clock for the PCIe
995
 * digital display port. The range is 4 to 13; 10 or more
996
 * is just a flip delay. The default is 6
997
 */
998
#define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
999
#define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
1000
/*
1001
 * SDVO multiplier for 945G/GM. Not used on 965.
1002
 */
1003
#define   SDVO_MULTIPLIER_MASK			0x000000ff
1004
#define   SDVO_MULTIPLIER_SHIFT_HIRES		4
1005
#define   SDVO_MULTIPLIER_SHIFT_VGA		0
3480 Serge 1006
#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
2325 Serge 1007
/*
1008
 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1009
 *
1010
 * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
1011
 */
1012
#define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
1013
#define   DPLL_MD_UDI_DIVIDER_SHIFT		24
1014
/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1015
#define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
1016
#define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
1017
/*
1018
 * SDVO/UDI pixel multiplier.
1019
 *
1020
 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1021
 * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
1022
 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1023
 * dummy bytes in the datastream at an increased clock rate, with both sides of
1024
 * the link knowing how many bytes are fill.
1025
 *
1026
 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1027
 * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
1028
 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1029
 * through an SDVO command.
1030
 *
1031
 * This register field has values of multiplication factor minus 1, with
1032
 * a maximum multiplier of 5 for SDVO.
1033
 */
1034
#define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
1035
#define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
1036
/*
1037
 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1038
 * This best be set to the default value (3) or the CRT won't work. No,
1039
 * I don't entirely understand what this does...
1040
 */
1041
#define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
1042
#define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
3480 Serge 1043
#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
2325 Serge 1044
#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
3031 serge 1045
 
2325 Serge 1046
#define _FPA0	0x06040
1047
#define _FPA1	0x06044
1048
#define _FPB0	0x06048
1049
#define _FPB1	0x0604c
1050
#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1051
#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1052
#define   FP_N_DIV_MASK		0x003f0000
1053
#define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
1054
#define   FP_N_DIV_SHIFT		16
1055
#define   FP_M1_DIV_MASK	0x00003f00
1056
#define   FP_M1_DIV_SHIFT		 8
1057
#define   FP_M2_DIV_MASK	0x0000003f
1058
#define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
1059
#define   FP_M2_DIV_SHIFT		 0
1060
#define DPLL_TEST	0x606c
1061
#define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
1062
#define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
1063
#define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
1064
#define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
1065
#define   DPLLB_TEST_N_BYPASS		(1 << 19)
1066
#define   DPLLB_TEST_M_BYPASS		(1 << 18)
1067
#define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
1068
#define   DPLLA_TEST_N_BYPASS		(1 << 3)
1069
#define   DPLLA_TEST_M_BYPASS		(1 << 2)
1070
#define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
1071
#define D_STATE		0x6104
1072
#define  DSTATE_GFX_RESET_I830			(1<<6)
1073
#define  DSTATE_PLL_D3_OFF			(1<<3)
1074
#define  DSTATE_GFX_CLOCK_GATING		(1<<1)
1075
#define  DSTATE_DOT_CLOCK_GATING		(1<<0)
1076
#define DSPCLK_GATE_D		0x6200
1077
# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
1078
# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
1079
# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
1080
# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
1081
# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
1082
# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
1083
# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
1084
# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
1085
# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
1086
# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
1087
# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
1088
# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
1089
# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
1090
# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
1091
# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
1092
# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
1093
# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
1094
# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
1095
# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
1096
# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
1097
# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
1098
# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
1099
# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
1100
# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
1101
# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
1102
# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
1103
# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
1104
# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
1105
/**
1106
 * This bit must be set on the 830 to prevent hangs when turning off the
1107
 * overlay scaler.
1108
 */
1109
# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
1110
# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
1111
# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
1112
# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
1113
# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
1114
 
1115
#define RENCLK_GATE_D1		0x6204
1116
# define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
1117
# define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
1118
# define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
1119
# define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
1120
# define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
1121
# define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
1122
# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
1123
# define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
1124
# define MAG_CLOCK_GATE_DISABLE			(1 << 5)
1125
/** This bit must be unset on 855,865 */
1126
# define MECI_CLOCK_GATE_DISABLE		(1 << 4)
1127
# define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
1128
# define MEC_CLOCK_GATE_DISABLE			(1 << 2)
1129
# define MECO_CLOCK_GATE_DISABLE		(1 << 1)
1130
/** This bit must be set on 855,865. */
1131
# define SV_CLOCK_GATE_DISABLE			(1 << 0)
1132
# define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
1133
# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
1134
# define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
1135
# define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
1136
# define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
1137
# define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
1138
# define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
1139
# define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
1140
# define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
1141
# define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
1142
# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
1143
# define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
1144
# define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
1145
# define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
1146
# define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
1147
# define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
1148
# define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
1149
 
1150
# define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
1151
/** This bit must always be set on 965G/965GM */
1152
# define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
1153
# define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
1154
# define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
1155
# define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
1156
# define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
1157
# define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
1158
/** This bit must always be set on 965G */
1159
# define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
1160
# define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
1161
# define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
1162
# define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
1163
# define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
1164
# define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
1165
# define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
1166
# define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
1167
# define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
1168
# define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
1169
# define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
1170
# define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
1171
# define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
1172
# define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
1173
# define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
1174
# define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
1175
# define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
1176
# define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
1177
# define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
1178
 
1179
#define RENCLK_GATE_D2		0x6208
1180
#define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
1181
#define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
1182
#define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
1183
#define RAMCLK_GATE_D		0x6210		/* CRL only */
1184
#define DEUC			0x6214          /* CRL only */
1185
 
3480 Serge 1186
#define FW_BLC_SELF_VLV		(VLV_DISPLAY_BASE + 0x6500)
3031 serge 1187
#define  FW_CSPWRDWNEN		(1<<15)
1188
 
2325 Serge 1189
/*
1190
 * Palette regs
1191
 */
1192
 
3480 Serge 1193
#define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
1194
#define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
2325 Serge 1195
#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1196
 
1197
/* MCH MMIO space */
1198
 
1199
/*
1200
 * MCHBAR mirror.
1201
 *
1202
 * This mirrors the MCHBAR MMIO space whose location is determined by
1203
 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1204
 * every way.  It is not accessible from the CP register read instructions.
1205
 *
1206
 */
1207
#define MCHBAR_MIRROR_BASE	0x10000
1208
 
1209
#define MCHBAR_MIRROR_BASE_SNB	0x140000
1210
 
3746 Serge 1211
/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
1212
#define DCLK 0x5e04
1213
 
2325 Serge 1214
/** 915-945 and GM965 MCH register controlling DRAM channel access */
1215
#define DCC			0x10200
1216
#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
1217
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
1218
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
1219
#define DCC_ADDRESSING_MODE_MASK			(3 << 0)
1220
#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
1221
#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
1222
 
1223
/** Pineview MCH register contains DDR3 setting */
1224
#define CSHRDDR3CTL            0x101a8
1225
#define CSHRDDR3CTL_DDR3       (1 << 2)
1226
 
1227
/** 965 MCH register controlling DRAM channel configuration */
1228
#define C0DRB3			0x10206
1229
#define C1DRB3			0x10606
1230
 
3031 serge 1231
/** snb MCH registers for reading the DRAM channel configuration */
1232
#define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
1233
#define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
1234
#define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
1235
#define   MAD_DIMM_ECC_MASK		(0x3 << 24)
1236
#define   MAD_DIMM_ECC_OFF		(0x0 << 24)
1237
#define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
1238
#define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
1239
#define   MAD_DIMM_ECC_ON		(0x3 << 24)
1240
#define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
1241
#define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
1242
#define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
1243
#define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
1244
#define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
1245
#define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
1246
#define   MAD_DIMM_A_SELECT		(0x1 << 16)
1247
/* DIMM sizes are in multiples of 256mb. */
1248
#define   MAD_DIMM_B_SIZE_SHIFT		8
1249
#define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
1250
#define   MAD_DIMM_A_SIZE_SHIFT		0
1251
#define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
1252
 
3480 Serge 1253
/** snb MCH registers for priority tuning */
1254
#define MCH_SSKPD			(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1255
#define   MCH_SSKPD_WM0_MASK		0x3f
1256
#define   MCH_SSKPD_WM0_VAL		0xc
3031 serge 1257
 
2325 Serge 1258
/* Clocking configuration register */
1259
#define CLKCFG			0x10c00
1260
#define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
1261
#define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
1262
#define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
1263
#define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
1264
#define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
1265
#define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
1266
/* Note, below two are guess */
1267
#define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */
1268
#define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */
1269
#define CLKCFG_FSB_MASK					(7 << 0)
1270
#define CLKCFG_MEM_533					(1 << 4)
1271
#define CLKCFG_MEM_667					(2 << 4)
1272
#define CLKCFG_MEM_800					(3 << 4)
1273
#define CLKCFG_MEM_MASK					(7 << 4)
1274
 
1275
#define TSC1			0x11001
1276
#define   TSE			(1<<0)
1277
#define TR1			0x11006
1278
#define TSFS			0x11020
1279
#define   TSFS_SLOPE_MASK	0x0000ff00
1280
#define   TSFS_SLOPE_SHIFT	8
1281
#define   TSFS_INTR_MASK	0x000000ff
1282
 
1283
#define CRSTANDVID		0x11100
1284
#define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1285
#define   PXVFREQ_PX_MASK	0x7f000000
1286
#define   PXVFREQ_PX_SHIFT	24
1287
#define VIDFREQ_BASE		0x11110
1288
#define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1289
#define VIDFREQ2		0x11114
1290
#define VIDFREQ3		0x11118
1291
#define VIDFREQ4		0x1111c
1292
#define   VIDFREQ_P0_MASK	0x1f000000
1293
#define   VIDFREQ_P0_SHIFT	24
1294
#define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
1295
#define   VIDFREQ_P0_CSCLK_SHIFT 20
1296
#define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
1297
#define   VIDFREQ_P0_CRCLK_SHIFT 16
1298
#define   VIDFREQ_P1_MASK	0x00001f00
1299
#define   VIDFREQ_P1_SHIFT	8
1300
#define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
1301
#define   VIDFREQ_P1_CSCLK_SHIFT 4
1302
#define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
1303
#define INTTOEXT_BASE_ILK	0x11300
1304
#define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
1305
#define   INTTOEXT_MAP3_SHIFT	24
1306
#define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
1307
#define   INTTOEXT_MAP2_SHIFT	16
1308
#define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
1309
#define   INTTOEXT_MAP1_SHIFT	8
1310
#define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
1311
#define   INTTOEXT_MAP0_SHIFT	0
1312
#define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
1313
#define MEMSWCTL		0x11170 /* Ironlake only */
1314
#define   MEMCTL_CMD_MASK	0xe000
1315
#define   MEMCTL_CMD_SHIFT	13
1316
#define   MEMCTL_CMD_RCLK_OFF	0
1317
#define   MEMCTL_CMD_RCLK_ON	1
1318
#define   MEMCTL_CMD_CHFREQ	2
1319
#define   MEMCTL_CMD_CHVID	3
1320
#define   MEMCTL_CMD_VMMOFF	4
1321
#define   MEMCTL_CMD_VMMON	5
1322
#define   MEMCTL_CMD_STS	(1<<12) /* write 1 triggers command, clears
1323
					   when command complete */
1324
#define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
1325
#define   MEMCTL_FREQ_SHIFT	8
1326
#define   MEMCTL_SFCAVM		(1<<7)
1327
#define   MEMCTL_TGT_VID_MASK	0x007f
1328
#define MEMIHYST		0x1117c
1329
#define MEMINTREN		0x11180 /* 16 bits */
1330
#define   MEMINT_RSEXIT_EN	(1<<8)
1331
#define   MEMINT_CX_SUPR_EN	(1<<7)
1332
#define   MEMINT_CONT_BUSY_EN	(1<<6)
1333
#define   MEMINT_AVG_BUSY_EN	(1<<5)
1334
#define   MEMINT_EVAL_CHG_EN	(1<<4)
1335
#define   MEMINT_MON_IDLE_EN	(1<<3)
1336
#define   MEMINT_UP_EVAL_EN	(1<<2)
1337
#define   MEMINT_DOWN_EVAL_EN	(1<<1)
1338
#define   MEMINT_SW_CMD_EN	(1<<0)
1339
#define MEMINTRSTR		0x11182 /* 16 bits */
1340
#define   MEM_RSEXIT_MASK	0xc000
1341
#define   MEM_RSEXIT_SHIFT	14
1342
#define   MEM_CONT_BUSY_MASK	0x3000
1343
#define   MEM_CONT_BUSY_SHIFT	12
1344
#define   MEM_AVG_BUSY_MASK	0x0c00
1345
#define   MEM_AVG_BUSY_SHIFT	10
1346
#define   MEM_EVAL_CHG_MASK	0x0300
1347
#define   MEM_EVAL_BUSY_SHIFT	8
1348
#define   MEM_MON_IDLE_MASK	0x00c0
1349
#define   MEM_MON_IDLE_SHIFT	6
1350
#define   MEM_UP_EVAL_MASK	0x0030
1351
#define   MEM_UP_EVAL_SHIFT	4
1352
#define   MEM_DOWN_EVAL_MASK	0x000c
1353
#define   MEM_DOWN_EVAL_SHIFT	2
1354
#define   MEM_SW_CMD_MASK	0x0003
1355
#define   MEM_INT_STEER_GFX	0
1356
#define   MEM_INT_STEER_CMR	1
1357
#define   MEM_INT_STEER_SMI	2
1358
#define   MEM_INT_STEER_SCI	3
1359
#define MEMINTRSTS		0x11184
1360
#define   MEMINT_RSEXIT		(1<<7)
1361
#define   MEMINT_CONT_BUSY	(1<<6)
1362
#define   MEMINT_AVG_BUSY	(1<<5)
1363
#define   MEMINT_EVAL_CHG	(1<<4)
1364
#define   MEMINT_MON_IDLE	(1<<3)
1365
#define   MEMINT_UP_EVAL	(1<<2)
1366
#define   MEMINT_DOWN_EVAL	(1<<1)
1367
#define   MEMINT_SW_CMD		(1<<0)
1368
#define MEMMODECTL		0x11190
1369
#define   MEMMODE_BOOST_EN	(1<<31)
1370
#define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1371
#define   MEMMODE_BOOST_FREQ_SHIFT 24
1372
#define   MEMMODE_IDLE_MODE_MASK 0x00030000
1373
#define   MEMMODE_IDLE_MODE_SHIFT 16
1374
#define   MEMMODE_IDLE_MODE_EVAL 0
1375
#define   MEMMODE_IDLE_MODE_CONT 1
1376
#define   MEMMODE_HWIDLE_EN	(1<<15)
1377
#define   MEMMODE_SWMODE_EN	(1<<14)
1378
#define   MEMMODE_RCLK_GATE	(1<<13)
1379
#define   MEMMODE_HW_UPDATE	(1<<12)
1380
#define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
1381
#define   MEMMODE_FSTART_SHIFT	8
1382
#define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
1383
#define   MEMMODE_FMAX_SHIFT	4
1384
#define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
1385
#define RCBMAXAVG		0x1119c
1386
#define MEMSWCTL2		0x1119e /* Cantiga only */
1387
#define   SWMEMCMD_RENDER_OFF	(0 << 13)
1388
#define   SWMEMCMD_RENDER_ON	(1 << 13)
1389
#define   SWMEMCMD_SWFREQ	(2 << 13)
1390
#define   SWMEMCMD_TARVID	(3 << 13)
1391
#define   SWMEMCMD_VRM_OFF	(4 << 13)
1392
#define   SWMEMCMD_VRM_ON	(5 << 13)
1393
#define   CMDSTS		(1<<12)
1394
#define   SFCAVM		(1<<11)
1395
#define   SWFREQ_MASK		0x0380 /* P0-7 */
1396
#define   SWFREQ_SHIFT		7
1397
#define   TARVID_MASK		0x001f
1398
#define MEMSTAT_CTG		0x111a0
1399
#define RCBMINAVG		0x111a0
1400
#define RCUPEI			0x111b0
1401
#define RCDNEI			0x111b4
1402
#define RSTDBYCTL		0x111b8
1403
#define   RS1EN			(1<<31)
1404
#define   RS2EN			(1<<30)
1405
#define   RS3EN			(1<<29)
1406
#define   D3RS3EN		(1<<28) /* Display D3 imlies RS3 */
1407
#define   SWPROMORSX		(1<<27) /* RSx promotion timers ignored */
1408
#define   RCWAKERW		(1<<26) /* Resetwarn from PCH causes wakeup */
1409
#define   DPRSLPVREN		(1<<25) /* Fast voltage ramp enable */
1410
#define   GFXTGHYST		(1<<24) /* Hysteresis to allow trunk gating */
1411
#define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
1412
#define   RSX_STATUS_MASK	(7<<20)
1413
#define   RSX_STATUS_ON		(0<<20)
1414
#define   RSX_STATUS_RC1	(1<<20)
1415
#define   RSX_STATUS_RC1E	(2<<20)
1416
#define   RSX_STATUS_RS1	(3<<20)
1417
#define   RSX_STATUS_RS2	(4<<20) /* aka rc6 */
1418
#define   RSX_STATUS_RSVD	(5<<20) /* deep rc6 unsupported on ilk */
1419
#define   RSX_STATUS_RS3	(6<<20) /* rs3 unsupported on ilk */
1420
#define   RSX_STATUS_RSVD2	(7<<20)
1421
#define   UWRCRSXE		(1<<19) /* wake counter limit prevents rsx */
1422
#define   RSCRP			(1<<18) /* rs requests control on rs1/2 reqs */
1423
#define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
1424
#define   RS2INC0		(1<<16) /* allow rs2 in cpu c0 */
1425
#define   RS1CONTSAV_MASK	(3<<14)
1426
#define   RS1CONTSAV_NO_RS1	(0<<14) /* rs1 doesn't save/restore context */
1427
#define   RS1CONTSAV_RSVD	(1<<14)
1428
#define   RS1CONTSAV_SAVE_RS1	(2<<14) /* rs1 saves context */
1429
#define   RS1CONTSAV_FULL_RS1	(3<<14) /* rs1 saves and restores context */
1430
#define   NORMSLEXLAT_MASK	(3<<12)
1431
#define   SLOW_RS123		(0<<12)
1432
#define   SLOW_RS23		(1<<12)
1433
#define   SLOW_RS3		(2<<12)
1434
#define   NORMAL_RS123		(3<<12)
1435
#define   RCMODE_TIMEOUT	(1<<11) /* 0 is eval interval method */
1436
#define   IMPROMOEN		(1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1437
#define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
1438
#define   STATELOCK		(1<<7) /* locked to rs_cstate if 0 */
1439
#define   RS_CSTATE_MASK	(3<<4)
1440
#define   RS_CSTATE_C367_RS1	(0<<4)
1441
#define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1442
#define   RS_CSTATE_RSVD	(2<<4)
1443
#define   RS_CSTATE_C367_RS2	(3<<4)
1444
#define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
1445
#define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
1446
#define VIDCTL			0x111c0
1447
#define VIDSTS			0x111c8
1448
#define VIDSTART		0x111cc /* 8 bits */
1449
#define MEMSTAT_ILK			0x111f8
1450
#define   MEMSTAT_VID_MASK	0x7f00
1451
#define   MEMSTAT_VID_SHIFT	8
1452
#define   MEMSTAT_PSTATE_MASK	0x00f8
1453
#define   MEMSTAT_PSTATE_SHIFT  3
1454
#define   MEMSTAT_MON_ACTV	(1<<2)
1455
#define   MEMSTAT_SRC_CTL_MASK	0x0003
1456
#define   MEMSTAT_SRC_CTL_CORE	0
1457
#define   MEMSTAT_SRC_CTL_TRB	1
1458
#define   MEMSTAT_SRC_CTL_THM	2
1459
#define   MEMSTAT_SRC_CTL_STDBY 3
1460
#define RCPREVBSYTUPAVG		0x113b8
1461
#define RCPREVBSYTDNAVG		0x113bc
1462
#define PMMISC			0x11214
1463
#define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
1464
#define SDEW			0x1124c
1465
#define CSIEW0			0x11250
1466
#define CSIEW1			0x11254
1467
#define CSIEW2			0x11258
1468
#define PEW			0x1125c
1469
#define DEW			0x11270
1470
#define MCHAFE			0x112c0
1471
#define CSIEC			0x112e0
1472
#define DMIEC			0x112e4
1473
#define DDREC			0x112e8
1474
#define PEG0EC			0x112ec
1475
#define PEG1EC			0x112f0
1476
#define GFXEC			0x112f4
1477
#define RPPREVBSYTUPAVG		0x113b8
1478
#define RPPREVBSYTDNAVG		0x113bc
1479
#define ECR			0x11600
1480
#define   ECR_GPFE		(1<<31)
1481
#define   ECR_IMONE		(1<<30)
1482
#define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
1483
#define OGW0			0x11608
1484
#define OGW1			0x1160c
1485
#define EG0			0x11610
1486
#define EG1			0x11614
1487
#define EG2			0x11618
1488
#define EG3			0x1161c
1489
#define EG4			0x11620
1490
#define EG5			0x11624
1491
#define EG6			0x11628
1492
#define EG7			0x1162c
1493
#define PXW			0x11664
1494
#define PXWL			0x11680
1495
#define LCFUSE02		0x116c0
1496
#define   LCFUSE_HIV_MASK	0x000000ff
1497
#define CSIPLL0			0x12c10
1498
#define DDRMPLL1		0X12c20
1499
#define PEG_BAND_GAP_DATA	0x14d68
1500
 
3031 serge 1501
#define GEN6_GT_THREAD_STATUS_REG 0x13805c
1502
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1503
#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1504
 
2325 Serge 1505
#define GEN6_GT_PERF_STATUS	0x145948
1506
#define GEN6_RP_STATE_LIMITS	0x145994
1507
#define GEN6_RP_STATE_CAP	0x145998
1508
 
1509
/*
1510
 * Logical Context regs
1511
 */
1512
#define CCID			0x2180
1513
#define   CCID_EN		(1<<0)
3031 serge 1514
#define CXT_SIZE		0x21a0
1515
#define GEN6_CXT_POWER_SIZE(cxt_reg)	((cxt_reg >> 24) & 0x3f)
1516
#define GEN6_CXT_RING_SIZE(cxt_reg)	((cxt_reg >> 18) & 0x3f)
1517
#define GEN6_CXT_RENDER_SIZE(cxt_reg)	((cxt_reg >> 12) & 0x3f)
1518
#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	((cxt_reg >> 6) & 0x3f)
1519
#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	((cxt_reg >> 0) & 0x3f)
1520
#define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_POWER_SIZE(cxt_reg) + \
1521
					GEN6_CXT_RING_SIZE(cxt_reg) + \
1522
					GEN6_CXT_RENDER_SIZE(cxt_reg) + \
1523
					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1524
					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1525
#define GEN7_CXT_SIZE		0x21a8
1526
#define GEN7_CXT_POWER_SIZE(ctx_reg)	((ctx_reg >> 25) & 0x7f)
1527
#define GEN7_CXT_RING_SIZE(ctx_reg)	((ctx_reg >> 22) & 0x7)
1528
#define GEN7_CXT_RENDER_SIZE(ctx_reg)	((ctx_reg >> 16) & 0x3f)
1529
#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	((ctx_reg >> 9) & 0x7f)
1530
#define GEN7_CXT_GT1_SIZE(ctx_reg)	((ctx_reg >> 6) & 0x7)
1531
#define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	((ctx_reg >> 0) & 0x3f)
1532
#define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_POWER_SIZE(ctx_reg) + \
1533
					 GEN7_CXT_RING_SIZE(ctx_reg) + \
1534
					 GEN7_CXT_RENDER_SIZE(ctx_reg) + \
1535
					 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1536
					 GEN7_CXT_GT1_SIZE(ctx_reg) + \
1537
					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1538
#define HSW_CXT_POWER_SIZE(ctx_reg)	((ctx_reg >> 26) & 0x3f)
1539
#define HSW_CXT_RING_SIZE(ctx_reg)	((ctx_reg >> 23) & 0x7)
1540
#define HSW_CXT_RENDER_SIZE(ctx_reg)	((ctx_reg >> 15) & 0xff)
1541
#define HSW_CXT_TOTAL_SIZE(ctx_reg)	(HSW_CXT_POWER_SIZE(ctx_reg) + \
1542
					 HSW_CXT_RING_SIZE(ctx_reg) + \
1543
					 HSW_CXT_RENDER_SIZE(ctx_reg) + \
1544
					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1545
 
1546
 
2325 Serge 1547
/*
1548
 * Overlay regs
1549
 */
1550
 
1551
#define OVADD			0x30000
1552
#define DOVSTA			0x30008
1553
#define OC_BUF			(0x3<<20)
1554
#define OGAMC5			0x30010
1555
#define OGAMC4			0x30014
1556
#define OGAMC3			0x30018
1557
#define OGAMC2			0x3001c
1558
#define OGAMC1			0x30020
1559
#define OGAMC0			0x30024
1560
 
1561
/*
1562
 * Display engine regs
1563
 */
1564
 
1565
/* Pipe A timing regs */
3480 Serge 1566
#define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)
1567
#define _HBLANK_A	(dev_priv->info->display_mmio_offset + 0x60004)
1568
#define _HSYNC_A	(dev_priv->info->display_mmio_offset + 0x60008)
1569
#define _VTOTAL_A	(dev_priv->info->display_mmio_offset + 0x6000c)
1570
#define _VBLANK_A	(dev_priv->info->display_mmio_offset + 0x60010)
1571
#define _VSYNC_A	(dev_priv->info->display_mmio_offset + 0x60014)
1572
#define _PIPEASRC	(dev_priv->info->display_mmio_offset + 0x6001c)
1573
#define _BCLRPAT_A	(dev_priv->info->display_mmio_offset + 0x60020)
1574
#define _VSYNCSHIFT_A	(dev_priv->info->display_mmio_offset + 0x60028)
2325 Serge 1575
 
1576
/* Pipe B timing regs */
3480 Serge 1577
#define _HTOTAL_B	(dev_priv->info->display_mmio_offset + 0x61000)
1578
#define _HBLANK_B	(dev_priv->info->display_mmio_offset + 0x61004)
1579
#define _HSYNC_B	(dev_priv->info->display_mmio_offset + 0x61008)
1580
#define _VTOTAL_B	(dev_priv->info->display_mmio_offset + 0x6100c)
1581
#define _VBLANK_B	(dev_priv->info->display_mmio_offset + 0x61010)
1582
#define _VSYNC_B	(dev_priv->info->display_mmio_offset + 0x61014)
1583
#define _PIPEBSRC	(dev_priv->info->display_mmio_offset + 0x6101c)
1584
#define _BCLRPAT_B	(dev_priv->info->display_mmio_offset + 0x61020)
1585
#define _VSYNCSHIFT_B	(dev_priv->info->display_mmio_offset + 0x61028)
2325 Serge 1586
 
3031 serge 1587
 
3243 Serge 1588
#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1589
#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1590
#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1591
#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1592
#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1593
#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
2325 Serge 1594
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
3243 Serge 1595
#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
2325 Serge 1596
 
1597
/* VGA port control */
1598
#define ADPA			0x61100
3031 serge 1599
#define PCH_ADPA                0xe1100
1600
#define VLV_ADPA		(VLV_DISPLAY_BASE + ADPA)
1601
 
2325 Serge 1602
#define   ADPA_DAC_ENABLE	(1<<31)
1603
#define   ADPA_DAC_DISABLE	0
1604
#define   ADPA_PIPE_SELECT_MASK	(1<<30)
1605
#define   ADPA_PIPE_A_SELECT	0
1606
#define   ADPA_PIPE_B_SELECT	(1<<30)
1607
#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
3031 serge 1608
/* CPT uses bits 29:30 for pch transcoder select */
1609
#define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
1610
#define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
1611
#define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
1612
#define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
1613
#define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
1614
#define   ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
1615
#define   ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
1616
#define   ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
1617
#define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
1618
#define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
1619
#define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
1620
#define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
1621
#define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
1622
#define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
1623
#define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
1624
#define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
1625
#define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
1626
#define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
1627
#define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2325 Serge 1628
#define   ADPA_USE_VGA_HVPOLARITY (1<<15)
1629
#define   ADPA_SETS_HVPOLARITY	0
3480 Serge 1630
#define   ADPA_VSYNC_CNTL_DISABLE (1<<10)
2325 Serge 1631
#define   ADPA_VSYNC_CNTL_ENABLE 0
3480 Serge 1632
#define   ADPA_HSYNC_CNTL_DISABLE (1<<11)
2325 Serge 1633
#define   ADPA_HSYNC_CNTL_ENABLE 0
1634
#define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1635
#define   ADPA_VSYNC_ACTIVE_LOW	0
1636
#define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1637
#define   ADPA_HSYNC_ACTIVE_LOW	0
1638
#define   ADPA_DPMS_MASK	(~(3<<10))
1639
#define   ADPA_DPMS_ON		(0<<10)
1640
#define   ADPA_DPMS_SUSPEND	(1<<10)
1641
#define   ADPA_DPMS_STANDBY	(2<<10)
1642
#define   ADPA_DPMS_OFF		(3<<10)
1643
 
1644
 
1645
/* Hotplug control (945+ only) */
3480 Serge 1646
#define PORT_HOTPLUG_EN		(dev_priv->info->display_mmio_offset + 0x61110)
1647
#define   PORTB_HOTPLUG_INT_EN			(1 << 29)
1648
#define   PORTC_HOTPLUG_INT_EN			(1 << 28)
1649
#define   PORTD_HOTPLUG_INT_EN			(1 << 27)
2325 Serge 1650
#define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
1651
#define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
1652
#define   TV_HOTPLUG_INT_EN			(1 << 18)
1653
#define   CRT_HOTPLUG_INT_EN			(1 << 9)
3746 Serge 1654
#define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
1655
						 PORTC_HOTPLUG_INT_EN | \
1656
						 PORTD_HOTPLUG_INT_EN | \
1657
						 SDVOC_HOTPLUG_INT_EN | \
1658
						 SDVOB_HOTPLUG_INT_EN | \
1659
						 CRT_HOTPLUG_INT_EN)
2325 Serge 1660
#define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
1661
#define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
1662
/* must use period 64 on GM45 according to docs */
1663
#define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
1664
#define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
1665
#define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
1666
#define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
1667
#define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
1668
#define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
1669
#define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
1670
#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
1671
#define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
1672
#define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
1673
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
1674
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
1675
 
3480 Serge 1676
#define PORT_HOTPLUG_STAT	(dev_priv->info->display_mmio_offset + 0x61114)
3031 serge 1677
/* HDMI/DP bits are gen4+ */
3480 Serge 1678
#define   PORTB_HOTPLUG_LIVE_STATUS               (1 << 29)
1679
#define   PORTC_HOTPLUG_LIVE_STATUS               (1 << 28)
1680
#define   PORTD_HOTPLUG_LIVE_STATUS               (1 << 27)
1681
#define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
1682
#define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
1683
#define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
3031 serge 1684
/* CRT/TV common between gen3+ */
2325 Serge 1685
#define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
1686
#define   TV_HOTPLUG_INT_STATUS			(1 << 10)
1687
#define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
1688
#define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
1689
#define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
1690
#define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
3031 serge 1691
/* SDVO is different across gen3/4 */
1692
#define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
1693
#define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
1694
#define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
1695
#define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
1696
#define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
1697
#define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
3746 Serge 1698
#define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
1699
						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
1700
						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
1701
						 PORTB_HOTPLUG_INT_STATUS | \
1702
						 PORTC_HOTPLUG_INT_STATUS | \
1703
						 PORTD_HOTPLUG_INT_STATUS)
2325 Serge 1704
 
3746 Serge 1705
#define HOTPLUG_INT_STATUS_I965			(CRT_HOTPLUG_INT_STATUS | \
1706
						 SDVOB_HOTPLUG_INT_STATUS_I965 | \
1707
						 SDVOC_HOTPLUG_INT_STATUS_I965 | \
1708
						 PORTB_HOTPLUG_INT_STATUS | \
1709
						 PORTC_HOTPLUG_INT_STATUS | \
1710
						 PORTD_HOTPLUG_INT_STATUS)
1711
 
1712
#define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
1713
						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
1714
						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
1715
						 PORTB_HOTPLUG_INT_STATUS | \
1716
						 PORTC_HOTPLUG_INT_STATUS | \
1717
						 PORTD_HOTPLUG_INT_STATUS)
1718
 
1719
/* SDVO and HDMI port control.
1720
 * The same register may be used for SDVO or HDMI */
1721
#define GEN3_SDVOB	0x61140
1722
#define GEN3_SDVOC	0x61160
1723
#define GEN4_HDMIB	GEN3_SDVOB
1724
#define GEN4_HDMIC	GEN3_SDVOC
1725
#define PCH_SDVOB	0xe1140
1726
#define PCH_HDMIB	PCH_SDVOB
1727
#define PCH_HDMIC	0xe1150
1728
#define PCH_HDMID	0xe1160
1729
 
1730
/* Gen 3 SDVO bits: */
2325 Serge 1731
#define   SDVO_ENABLE		(1 << 31)
3746 Serge 1732
#define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
1733
#define   SDVO_PIPE_SEL_MASK			(1 << 30)
2325 Serge 1734
#define   SDVO_PIPE_B_SELECT	(1 << 30)
1735
#define   SDVO_STALL_SELECT	(1 << 29)
1736
#define   SDVO_INTERRUPT_ENABLE	(1 << 26)
1737
/**
1738
 * 915G/GM SDVO pixel multiplier.
1739
 * Programmed value is multiplier - 1, up to 5x.
1740
 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1741
 */
1742
#define   SDVO_PORT_MULTIPLY_MASK	(7 << 23)
1743
#define   SDVO_PORT_MULTIPLY_SHIFT		23
1744
#define   SDVO_PHASE_SELECT_MASK	(15 << 19)
1745
#define   SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
1746
#define   SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
3746 Serge 1747
#define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
1748
#define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
1749
#define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
1750
#define   SDVO_DETECTED				(1 << 2)
1751
/* Bits to be preserved when writing */
1752
#define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
1753
			       SDVO_INTERRUPT_ENABLE)
1754
#define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
1755
 
1756
/* Gen 4 SDVO/HDMI bits: */
1757
#define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
1758
#define   SDVO_ENCODING_SDVO			(0 << 10)
1759
#define   SDVO_ENCODING_HDMI			(2 << 10)
1760
#define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
1761
#define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
1762
#define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
2325 Serge 1763
#define   SDVO_AUDIO_ENABLE		(1 << 6)
3746 Serge 1764
/* VSYNC/HSYNC bits new with 965, default is to be set */
2325 Serge 1765
#define   SDVO_VSYNC_ACTIVE_HIGH	(1 << 4)
1766
#define   SDVO_HSYNC_ACTIVE_HIGH	(1 << 3)
1767
 
3746 Serge 1768
/* Gen 5 (IBX) SDVO/HDMI bits: */
1769
#define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
1770
#define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
1771
 
1772
/* Gen 6 (CPT) SDVO/HDMI bits: */
1773
#define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
1774
#define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
1775
 
1776
 
2325 Serge 1777
/* DVO port control */
1778
#define DVOA			0x61120
1779
#define DVOB			0x61140
1780
#define DVOC			0x61160
1781
#define   DVO_ENABLE			(1 << 31)
1782
#define   DVO_PIPE_B_SELECT		(1 << 30)
1783
#define   DVO_PIPE_STALL_UNUSED		(0 << 28)
1784
#define   DVO_PIPE_STALL		(1 << 28)
1785
#define   DVO_PIPE_STALL_TV		(2 << 28)
1786
#define   DVO_PIPE_STALL_MASK		(3 << 28)
1787
#define   DVO_USE_VGA_SYNC		(1 << 15)
1788
#define   DVO_DATA_ORDER_I740		(0 << 14)
1789
#define   DVO_DATA_ORDER_FP		(1 << 14)
1790
#define   DVO_VSYNC_DISABLE		(1 << 11)
1791
#define   DVO_HSYNC_DISABLE		(1 << 10)
1792
#define   DVO_VSYNC_TRISTATE		(1 << 9)
1793
#define   DVO_HSYNC_TRISTATE		(1 << 8)
1794
#define   DVO_BORDER_ENABLE		(1 << 7)
1795
#define   DVO_DATA_ORDER_GBRG		(1 << 6)
1796
#define   DVO_DATA_ORDER_RGGB		(0 << 6)
1797
#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
1798
#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
1799
#define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
1800
#define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
1801
#define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
1802
#define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
1803
#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
1804
#define   DVO_PRESERVE_MASK		(0x7<<24)
1805
#define DVOA_SRCDIM		0x61124
1806
#define DVOB_SRCDIM		0x61144
1807
#define DVOC_SRCDIM		0x61164
1808
#define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
1809
#define   DVO_SRCDIM_VERTICAL_SHIFT	0
1810
 
1811
/* LVDS port control */
1812
#define LVDS			0x61180
1813
/*
1814
 * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
1815
 * the DPLL semantics change when the LVDS is assigned to that pipe.
1816
 */
1817
#define   LVDS_PORT_EN			(1 << 31)
1818
/* Selects pipe B for LVDS data.  Must be set on pre-965. */
1819
#define   LVDS_PIPEB_SELECT		(1 << 30)
1820
#define   LVDS_PIPE_MASK		(1 << 30)
1821
#define   LVDS_PIPE(pipe)		((pipe) << 30)
1822
/* LVDS dithering flag on 965/g4x platform */
1823
#define   LVDS_ENABLE_DITHER		(1 << 25)
1824
/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1825
#define   LVDS_VSYNC_POLARITY		(1 << 21)
1826
#define   LVDS_HSYNC_POLARITY		(1 << 20)
1827
 
1828
/* Enable border for unscaled (or aspect-scaled) display */
1829
#define   LVDS_BORDER_ENABLE		(1 << 15)
1830
/*
1831
 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1832
 * pixel.
1833
 */
1834
#define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
1835
#define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
1836
#define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
1837
/*
1838
 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1839
 * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1840
 * on.
1841
 */
1842
#define   LVDS_A3_POWER_MASK		(3 << 6)
1843
#define   LVDS_A3_POWER_DOWN		(0 << 6)
1844
#define   LVDS_A3_POWER_UP		(3 << 6)
1845
/*
1846
 * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
1847
 * is set.
1848
 */
1849
#define   LVDS_CLKB_POWER_MASK		(3 << 4)
1850
#define   LVDS_CLKB_POWER_DOWN		(0 << 4)
1851
#define   LVDS_CLKB_POWER_UP		(3 << 4)
1852
/*
1853
 * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
1854
 * setting for whether we are in dual-channel mode.  The B3 pair will
1855
 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1856
 */
1857
#define   LVDS_B0B3_POWER_MASK		(3 << 2)
1858
#define   LVDS_B0B3_POWER_DOWN		(0 << 2)
1859
#define   LVDS_B0B3_POWER_UP		(3 << 2)
1860
 
1861
/* Video Data Island Packet control */
1862
#define VIDEO_DIP_DATA		0x61178
3031 serge 1863
/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
1864
 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
1865
 * of the infoframe structure specified by CEA-861. */
1866
#define   VIDEO_DIP_DATA_SIZE	32
2325 Serge 1867
#define VIDEO_DIP_CTL		0x61170
3031 serge 1868
/* Pre HSW: */
2325 Serge 1869
#define   VIDEO_DIP_ENABLE		(1 << 31)
1870
#define   VIDEO_DIP_PORT_B		(1 << 29)
1871
#define   VIDEO_DIP_PORT_C		(2 << 29)
3031 serge 1872
#define   VIDEO_DIP_PORT_D		(3 << 29)
1873
#define   VIDEO_DIP_PORT_MASK		(3 << 29)
1874
#define   VIDEO_DIP_ENABLE_GCP		(1 << 25)
2325 Serge 1875
#define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
1876
#define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
3031 serge 1877
#define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21)
2325 Serge 1878
#define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
1879
#define   VIDEO_DIP_SELECT_AVI		(0 << 19)
1880
#define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
1881
#define   VIDEO_DIP_SELECT_SPD		(3 << 19)
1882
#define   VIDEO_DIP_SELECT_MASK		(3 << 19)
1883
#define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
1884
#define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
1885
#define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
3031 serge 1886
#define   VIDEO_DIP_FREQ_MASK		(3 << 16)
1887
/* HSW and later: */
1888
#define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
1889
#define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
1890
#define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
1891
#define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
1892
#define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
1893
#define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
2325 Serge 1894
 
1895
/* Panel power sequencing */
1896
#define PP_STATUS	0x61200
1897
#define   PP_ON		(1 << 31)
1898
/*
1899
 * Indicates that all dependencies of the panel are on:
1900
 *
1901
 * - PLL enabled
1902
 * - pipe enabled
1903
 * - LVDS/DVOB/DVOC on
1904
 */
1905
#define   PP_READY		(1 << 30)
1906
#define   PP_SEQUENCE_NONE	(0 << 28)
2342 Serge 1907
#define   PP_SEQUENCE_POWER_UP	(1 << 28)
1908
#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
1909
#define   PP_SEQUENCE_MASK	(3 << 28)
1910
#define   PP_SEQUENCE_SHIFT	28
2325 Serge 1911
#define   PP_CYCLE_DELAY_ACTIVE	(1 << 27)
1912
#define   PP_SEQUENCE_STATE_MASK 0x0000000f
2342 Serge 1913
#define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
1914
#define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
1915
#define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
1916
#define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
1917
#define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
1918
#define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
1919
#define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
1920
#define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
1921
#define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
2325 Serge 1922
#define PP_CONTROL	0x61204
1923
#define   POWER_TARGET_ON	(1 << 0)
1924
#define PP_ON_DELAYS	0x61208
1925
#define PP_OFF_DELAYS	0x6120c
1926
#define PP_DIVISOR	0x61210
1927
 
1928
/* Panel fitting */
3480 Serge 1929
#define PFIT_CONTROL	(dev_priv->info->display_mmio_offset + 0x61230)
2325 Serge 1930
#define   PFIT_ENABLE		(1 << 31)
1931
#define   PFIT_PIPE_MASK	(3 << 29)
1932
#define   PFIT_PIPE_SHIFT	29
1933
#define   VERT_INTERP_DISABLE	(0 << 10)
1934
#define   VERT_INTERP_BILINEAR	(1 << 10)
1935
#define   VERT_INTERP_MASK	(3 << 10)
1936
#define   VERT_AUTO_SCALE	(1 << 9)
1937
#define   HORIZ_INTERP_DISABLE	(0 << 6)
1938
#define   HORIZ_INTERP_BILINEAR	(1 << 6)
1939
#define   HORIZ_INTERP_MASK	(3 << 6)
1940
#define   HORIZ_AUTO_SCALE	(1 << 5)
1941
#define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
1942
#define   PFIT_FILTER_FUZZY	(0 << 24)
1943
#define   PFIT_SCALING_AUTO	(0 << 26)
1944
#define   PFIT_SCALING_PROGRAMMED (1 << 26)
1945
#define   PFIT_SCALING_PILLAR	(2 << 26)
1946
#define   PFIT_SCALING_LETTER	(3 << 26)
3480 Serge 1947
#define PFIT_PGM_RATIOS	(dev_priv->info->display_mmio_offset + 0x61234)
2325 Serge 1948
/* Pre-965 */
1949
#define		PFIT_VERT_SCALE_SHIFT		20
1950
#define		PFIT_VERT_SCALE_MASK		0xfff00000
1951
#define		PFIT_HORIZ_SCALE_SHIFT		4
1952
#define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
1953
/* 965+ */
1954
#define		PFIT_VERT_SCALE_SHIFT_965	16
1955
#define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
1956
#define		PFIT_HORIZ_SCALE_SHIFT_965	0
1957
#define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
1958
 
3480 Serge 1959
#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
2325 Serge 1960
 
1961
/* Backlight control */
3746 Serge 1962
#define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
3031 serge 1963
#define   BLM_PWM_ENABLE		(1 << 31)
1964
#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
1965
#define   BLM_PIPE_SELECT		(1 << 29)
1966
#define   BLM_PIPE_SELECT_IVB		(3 << 29)
1967
#define   BLM_PIPE_A			(0 << 29)
1968
#define   BLM_PIPE_B			(1 << 29)
1969
#define   BLM_PIPE_C			(2 << 29) /* ivb + */
1970
#define   BLM_PIPE(pipe)		((pipe) << 29)
1971
#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
1972
#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
1973
#define   BLM_PHASE_IN_ENABLE		(1 << 25)
1974
#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
1975
#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
1976
#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
1977
#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
1978
#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
1979
#define   BLM_PHASE_IN_INCR_SHIFT	(0)
1980
#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
3746 Serge 1981
#define BLC_PWM_CTL	(dev_priv->info->display_mmio_offset + 0x61254)
2325 Serge 1982
/*
1983
 * This is the most significant 15 bits of the number of backlight cycles in a
1984
 * complete cycle of the modulated backlight control.
1985
 *
1986
 * The actual value is this field multiplied by two.
1987
 */
3031 serge 1988
#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
2325 Serge 1989
#define   BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
3031 serge 1990
#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
2325 Serge 1991
/*
1992
 * This is the number of cycles out of the backlight modulation cycle for which
1993
 * the backlight is on.
1994
 *
1995
 * This field must be no greater than the number of cycles in the complete
1996
 * backlight modulation cycle.
1997
 */
1998
#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
1999
#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
3031 serge 2000
#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
2001
#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
2325 Serge 2002
 
3746 Serge 2003
#define BLC_HIST_CTL	(dev_priv->info->display_mmio_offset + 0x61260)
2325 Serge 2004
 
3031 serge 2005
/* New registers for PCH-split platforms. Safe where new bits show up, the
2006
 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2007
#define BLC_PWM_CPU_CTL2	0x48250
2008
#define BLC_PWM_CPU_CTL		0x48254
2009
 
2010
/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2011
 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2012
#define BLC_PWM_PCH_CTL1	0xc8250
2013
#define   BLM_PCH_PWM_ENABLE			(1 << 31)
2014
#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
2015
#define   BLM_PCH_POLARITY			(1 << 29)
2016
#define BLC_PWM_PCH_CTL2	0xc8254
2017
 
2325 Serge 2018
/* TV port control */
2019
#define TV_CTL			0x68000
2020
/** Enables the TV encoder */
2021
# define TV_ENC_ENABLE			(1 << 31)
2022
/** Sources the TV encoder input from pipe B instead of A. */
2023
# define TV_ENC_PIPEB_SELECT		(1 << 30)
2024
/** Outputs composite video (DAC A only) */
2025
# define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
2026
/** Outputs SVideo video (DAC B/C) */
2027
# define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
2028
/** Outputs Component video (DAC A/B/C) */
2029
# define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
2030
/** Outputs Composite and SVideo (DAC A/B/C) */
2031
# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
2032
# define TV_TRILEVEL_SYNC		(1 << 21)
2033
/** Enables slow sync generation (945GM only) */
2034
# define TV_SLOW_SYNC			(1 << 20)
2035
/** Selects 4x oversampling for 480i and 576p */
2036
# define TV_OVERSAMPLE_4X		(0 << 18)
2037
/** Selects 2x oversampling for 720p and 1080i */
2038
# define TV_OVERSAMPLE_2X		(1 << 18)
2039
/** Selects no oversampling for 1080p */
2040
# define TV_OVERSAMPLE_NONE		(2 << 18)
2041
/** Selects 8x oversampling */
2042
# define TV_OVERSAMPLE_8X		(3 << 18)
2043
/** Selects progressive mode rather than interlaced */
2044
# define TV_PROGRESSIVE			(1 << 17)
2045
/** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
2046
# define TV_PAL_BURST			(1 << 16)
2047
/** Field for setting delay of Y compared to C */
2048
# define TV_YC_SKEW_MASK		(7 << 12)
2049
/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2050
# define TV_ENC_SDP_FIX			(1 << 11)
2051
/**
2052
 * Enables a fix for the 915GM only.
2053
 *
2054
 * Not sure what it does.
2055
 */
2056
# define TV_ENC_C0_FIX			(1 << 10)
2057
/** Bits that must be preserved by software */
2058
# define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2059
# define TV_FUSE_STATE_MASK		(3 << 4)
2060
/** Read-only state that reports all features enabled */
2061
# define TV_FUSE_STATE_ENABLED		(0 << 4)
2062
/** Read-only state that reports that Macrovision is disabled in hardware*/
2063
# define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
2064
/** Read-only state that reports that TV-out is disabled in hardware. */
2065
# define TV_FUSE_STATE_DISABLED		(2 << 4)
2066
/** Normal operation */
2067
# define TV_TEST_MODE_NORMAL		(0 << 0)
2068
/** Encoder test pattern 1 - combo pattern */
2069
# define TV_TEST_MODE_PATTERN_1		(1 << 0)
2070
/** Encoder test pattern 2 - full screen vertical 75% color bars */
2071
# define TV_TEST_MODE_PATTERN_2		(2 << 0)
2072
/** Encoder test pattern 3 - full screen horizontal 75% color bars */
2073
# define TV_TEST_MODE_PATTERN_3		(3 << 0)
2074
/** Encoder test pattern 4 - random noise */
2075
# define TV_TEST_MODE_PATTERN_4		(4 << 0)
2076
/** Encoder test pattern 5 - linear color ramps */
2077
# define TV_TEST_MODE_PATTERN_5		(5 << 0)
2078
/**
2079
 * This test mode forces the DACs to 50% of full output.
2080
 *
2081
 * This is used for load detection in combination with TVDAC_SENSE_MASK
2082
 */
2083
# define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
2084
# define TV_TEST_MODE_MASK		(7 << 0)
2085
 
2086
#define TV_DAC			0x68004
2087
# define TV_DAC_SAVE		0x00ffff00
2088
/**
2089
 * Reports that DAC state change logic has reported change (RO).
2090
 *
2091
 * This gets cleared when TV_DAC_STATE_EN is cleared
2092
*/
2093
# define TVDAC_STATE_CHG		(1 << 31)
2094
# define TVDAC_SENSE_MASK		(7 << 28)
2095
/** Reports that DAC A voltage is above the detect threshold */
2096
# define TVDAC_A_SENSE			(1 << 30)
2097
/** Reports that DAC B voltage is above the detect threshold */
2098
# define TVDAC_B_SENSE			(1 << 29)
2099
/** Reports that DAC C voltage is above the detect threshold */
2100
# define TVDAC_C_SENSE			(1 << 28)
2101
/**
2102
 * Enables DAC state detection logic, for load-based TV detection.
2103
 *
2104
 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2105
 * to off, for load detection to work.
2106
 */
2107
# define TVDAC_STATE_CHG_EN		(1 << 27)
2108
/** Sets the DAC A sense value to high */
2109
# define TVDAC_A_SENSE_CTL		(1 << 26)
2110
/** Sets the DAC B sense value to high */
2111
# define TVDAC_B_SENSE_CTL		(1 << 25)
2112
/** Sets the DAC C sense value to high */
2113
# define TVDAC_C_SENSE_CTL		(1 << 24)
2114
/** Overrides the ENC_ENABLE and DAC voltage levels */
2115
# define DAC_CTL_OVERRIDE		(1 << 7)
2116
/** Sets the slew rate.  Must be preserved in software */
2117
# define ENC_TVDAC_SLEW_FAST		(1 << 6)
2118
# define DAC_A_1_3_V			(0 << 4)
2119
# define DAC_A_1_1_V			(1 << 4)
2120
# define DAC_A_0_7_V			(2 << 4)
2121
# define DAC_A_MASK			(3 << 4)
2122
# define DAC_B_1_3_V			(0 << 2)
2123
# define DAC_B_1_1_V			(1 << 2)
2124
# define DAC_B_0_7_V			(2 << 2)
2125
# define DAC_B_MASK			(3 << 2)
2126
# define DAC_C_1_3_V			(0 << 0)
2127
# define DAC_C_1_1_V			(1 << 0)
2128
# define DAC_C_0_7_V			(2 << 0)
2129
# define DAC_C_MASK			(3 << 0)
2130
 
2131
/**
2132
 * CSC coefficients are stored in a floating point format with 9 bits of
2133
 * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
2134
 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2135
 * -1 (0x3) being the only legal negative value.
2136
 */
2137
#define TV_CSC_Y		0x68010
2138
# define TV_RY_MASK			0x07ff0000
2139
# define TV_RY_SHIFT			16
2140
# define TV_GY_MASK			0x00000fff
2141
# define TV_GY_SHIFT			0
2142
 
2143
#define TV_CSC_Y2		0x68014
2144
# define TV_BY_MASK			0x07ff0000
2145
# define TV_BY_SHIFT			16
2146
/**
2147
 * Y attenuation for component video.
2148
 *
2149
 * Stored in 1.9 fixed point.
2150
 */
2151
# define TV_AY_MASK			0x000003ff
2152
# define TV_AY_SHIFT			0
2153
 
2154
#define TV_CSC_U		0x68018
2155
# define TV_RU_MASK			0x07ff0000
2156
# define TV_RU_SHIFT			16
2157
# define TV_GU_MASK			0x000007ff
2158
# define TV_GU_SHIFT			0
2159
 
2160
#define TV_CSC_U2		0x6801c
2161
# define TV_BU_MASK			0x07ff0000
2162
# define TV_BU_SHIFT			16
2163
/**
2164
 * U attenuation for component video.
2165
 *
2166
 * Stored in 1.9 fixed point.
2167
 */
2168
# define TV_AU_MASK			0x000003ff
2169
# define TV_AU_SHIFT			0
2170
 
2171
#define TV_CSC_V		0x68020
2172
# define TV_RV_MASK			0x0fff0000
2173
# define TV_RV_SHIFT			16
2174
# define TV_GV_MASK			0x000007ff
2175
# define TV_GV_SHIFT			0
2176
 
2177
#define TV_CSC_V2		0x68024
2178
# define TV_BV_MASK			0x07ff0000
2179
# define TV_BV_SHIFT			16
2180
/**
2181
 * V attenuation for component video.
2182
 *
2183
 * Stored in 1.9 fixed point.
2184
 */
2185
# define TV_AV_MASK			0x000007ff
2186
# define TV_AV_SHIFT			0
2187
 
2188
#define TV_CLR_KNOBS		0x68028
2189
/** 2s-complement brightness adjustment */
2190
# define TV_BRIGHTNESS_MASK		0xff000000
2191
# define TV_BRIGHTNESS_SHIFT		24
2192
/** Contrast adjustment, as a 2.6 unsigned floating point number */
2193
# define TV_CONTRAST_MASK		0x00ff0000
2194
# define TV_CONTRAST_SHIFT		16
2195
/** Saturation adjustment, as a 2.6 unsigned floating point number */
2196
# define TV_SATURATION_MASK		0x0000ff00
2197
# define TV_SATURATION_SHIFT		8
2198
/** Hue adjustment, as an integer phase angle in degrees */
2199
# define TV_HUE_MASK			0x000000ff
2200
# define TV_HUE_SHIFT			0
2201
 
2202
#define TV_CLR_LEVEL		0x6802c
2203
/** Controls the DAC level for black */
2204
# define TV_BLACK_LEVEL_MASK		0x01ff0000
2205
# define TV_BLACK_LEVEL_SHIFT		16
2206
/** Controls the DAC level for blanking */
2207
# define TV_BLANK_LEVEL_MASK		0x000001ff
2208
# define TV_BLANK_LEVEL_SHIFT		0
2209
 
2210
#define TV_H_CTL_1		0x68030
2211
/** Number of pixels in the hsync. */
2212
# define TV_HSYNC_END_MASK		0x1fff0000
2213
# define TV_HSYNC_END_SHIFT		16
2214
/** Total number of pixels minus one in the line (display and blanking). */
2215
# define TV_HTOTAL_MASK			0x00001fff
2216
# define TV_HTOTAL_SHIFT		0
2217
 
2218
#define TV_H_CTL_2		0x68034
2219
/** Enables the colorburst (needed for non-component color) */
2220
# define TV_BURST_ENA			(1 << 31)
2221
/** Offset of the colorburst from the start of hsync, in pixels minus one. */
2222
# define TV_HBURST_START_SHIFT		16
2223
# define TV_HBURST_START_MASK		0x1fff0000
2224
/** Length of the colorburst */
2225
# define TV_HBURST_LEN_SHIFT		0
2226
# define TV_HBURST_LEN_MASK		0x0001fff
2227
 
2228
#define TV_H_CTL_3		0x68038
2229
/** End of hblank, measured in pixels minus one from start of hsync */
2230
# define TV_HBLANK_END_SHIFT		16
2231
# define TV_HBLANK_END_MASK		0x1fff0000
2232
/** Start of hblank, measured in pixels minus one from start of hsync */
2233
# define TV_HBLANK_START_SHIFT		0
2234
# define TV_HBLANK_START_MASK		0x0001fff
2235
 
2236
#define TV_V_CTL_1		0x6803c
2237
/** XXX */
2238
# define TV_NBR_END_SHIFT		16
2239
# define TV_NBR_END_MASK		0x07ff0000
2240
/** XXX */
2241
# define TV_VI_END_F1_SHIFT		8
2242
# define TV_VI_END_F1_MASK		0x00003f00
2243
/** XXX */
2244
# define TV_VI_END_F2_SHIFT		0
2245
# define TV_VI_END_F2_MASK		0x0000003f
2246
 
2247
#define TV_V_CTL_2		0x68040
2248
/** Length of vsync, in half lines */
2249
# define TV_VSYNC_LEN_MASK		0x07ff0000
2250
# define TV_VSYNC_LEN_SHIFT		16
2251
/** Offset of the start of vsync in field 1, measured in one less than the
2252
 * number of half lines.
2253
 */
2254
# define TV_VSYNC_START_F1_MASK		0x00007f00
2255
# define TV_VSYNC_START_F1_SHIFT	8
2256
/**
2257
 * Offset of the start of vsync in field 2, measured in one less than the
2258
 * number of half lines.
2259
 */
2260
# define TV_VSYNC_START_F2_MASK		0x0000007f
2261
# define TV_VSYNC_START_F2_SHIFT	0
2262
 
2263
#define TV_V_CTL_3		0x68044
2264
/** Enables generation of the equalization signal */
2265
# define TV_EQUAL_ENA			(1 << 31)
2266
/** Length of vsync, in half lines */
2267
# define TV_VEQ_LEN_MASK		0x007f0000
2268
# define TV_VEQ_LEN_SHIFT		16
2269
/** Offset of the start of equalization in field 1, measured in one less than
2270
 * the number of half lines.
2271
 */
2272
# define TV_VEQ_START_F1_MASK		0x0007f00
2273
# define TV_VEQ_START_F1_SHIFT		8
2274
/**
2275
 * Offset of the start of equalization in field 2, measured in one less than
2276
 * the number of half lines.
2277
 */
2278
# define TV_VEQ_START_F2_MASK		0x000007f
2279
# define TV_VEQ_START_F2_SHIFT		0
2280
 
2281
#define TV_V_CTL_4		0x68048
2282
/**
2283
 * Offset to start of vertical colorburst, measured in one less than the
2284
 * number of lines from vertical start.
2285
 */
2286
# define TV_VBURST_START_F1_MASK	0x003f0000
2287
# define TV_VBURST_START_F1_SHIFT	16
2288
/**
2289
 * Offset to the end of vertical colorburst, measured in one less than the
2290
 * number of lines from the start of NBR.
2291
 */
2292
# define TV_VBURST_END_F1_MASK		0x000000ff
2293
# define TV_VBURST_END_F1_SHIFT		0
2294
 
2295
#define TV_V_CTL_5		0x6804c
2296
/**
2297
 * Offset to start of vertical colorburst, measured in one less than the
2298
 * number of lines from vertical start.
2299
 */
2300
# define TV_VBURST_START_F2_MASK	0x003f0000
2301
# define TV_VBURST_START_F2_SHIFT	16
2302
/**
2303
 * Offset to the end of vertical colorburst, measured in one less than the
2304
 * number of lines from the start of NBR.
2305
 */
2306
# define TV_VBURST_END_F2_MASK		0x000000ff
2307
# define TV_VBURST_END_F2_SHIFT		0
2308
 
2309
#define TV_V_CTL_6		0x68050
2310
/**
2311
 * Offset to start of vertical colorburst, measured in one less than the
2312
 * number of lines from vertical start.
2313
 */
2314
# define TV_VBURST_START_F3_MASK	0x003f0000
2315
# define TV_VBURST_START_F3_SHIFT	16
2316
/**
2317
 * Offset to the end of vertical colorburst, measured in one less than the
2318
 * number of lines from the start of NBR.
2319
 */
2320
# define TV_VBURST_END_F3_MASK		0x000000ff
2321
# define TV_VBURST_END_F3_SHIFT		0
2322
 
2323
#define TV_V_CTL_7		0x68054
2324
/**
2325
 * Offset to start of vertical colorburst, measured in one less than the
2326
 * number of lines from vertical start.
2327
 */
2328
# define TV_VBURST_START_F4_MASK	0x003f0000
2329
# define TV_VBURST_START_F4_SHIFT	16
2330
/**
2331
 * Offset to the end of vertical colorburst, measured in one less than the
2332
 * number of lines from the start of NBR.
2333
 */
2334
# define TV_VBURST_END_F4_MASK		0x000000ff
2335
# define TV_VBURST_END_F4_SHIFT		0
2336
 
2337
#define TV_SC_CTL_1		0x68060
2338
/** Turns on the first subcarrier phase generation DDA */
2339
# define TV_SC_DDA1_EN			(1 << 31)
2340
/** Turns on the first subcarrier phase generation DDA */
2341
# define TV_SC_DDA2_EN			(1 << 30)
2342
/** Turns on the first subcarrier phase generation DDA */
2343
# define TV_SC_DDA3_EN			(1 << 29)
2344
/** Sets the subcarrier DDA to reset frequency every other field */
2345
# define TV_SC_RESET_EVERY_2		(0 << 24)
2346
/** Sets the subcarrier DDA to reset frequency every fourth field */
2347
# define TV_SC_RESET_EVERY_4		(1 << 24)
2348
/** Sets the subcarrier DDA to reset frequency every eighth field */
2349
# define TV_SC_RESET_EVERY_8		(2 << 24)
2350
/** Sets the subcarrier DDA to never reset the frequency */
2351
# define TV_SC_RESET_NEVER		(3 << 24)
2352
/** Sets the peak amplitude of the colorburst.*/
2353
# define TV_BURST_LEVEL_MASK		0x00ff0000
2354
# define TV_BURST_LEVEL_SHIFT		16
2355
/** Sets the increment of the first subcarrier phase generation DDA */
2356
# define TV_SCDDA1_INC_MASK		0x00000fff
2357
# define TV_SCDDA1_INC_SHIFT		0
2358
 
2359
#define TV_SC_CTL_2		0x68064
2360
/** Sets the rollover for the second subcarrier phase generation DDA */
2361
# define TV_SCDDA2_SIZE_MASK		0x7fff0000
2362
# define TV_SCDDA2_SIZE_SHIFT		16
2363
/** Sets the increent of the second subcarrier phase generation DDA */
2364
# define TV_SCDDA2_INC_MASK		0x00007fff
2365
# define TV_SCDDA2_INC_SHIFT		0
2366
 
2367
#define TV_SC_CTL_3		0x68068
2368
/** Sets the rollover for the third subcarrier phase generation DDA */
2369
# define TV_SCDDA3_SIZE_MASK		0x7fff0000
2370
# define TV_SCDDA3_SIZE_SHIFT		16
2371
/** Sets the increent of the third subcarrier phase generation DDA */
2372
# define TV_SCDDA3_INC_MASK		0x00007fff
2373
# define TV_SCDDA3_INC_SHIFT		0
2374
 
2375
#define TV_WIN_POS		0x68070
2376
/** X coordinate of the display from the start of horizontal active */
2377
# define TV_XPOS_MASK			0x1fff0000
2378
# define TV_XPOS_SHIFT			16
2379
/** Y coordinate of the display from the start of vertical active (NBR) */
2380
# define TV_YPOS_MASK			0x00000fff
2381
# define TV_YPOS_SHIFT			0
2382
 
2383
#define TV_WIN_SIZE		0x68074
2384
/** Horizontal size of the display window, measured in pixels*/
2385
# define TV_XSIZE_MASK			0x1fff0000
2386
# define TV_XSIZE_SHIFT			16
2387
/**
2388
 * Vertical size of the display window, measured in pixels.
2389
 *
2390
 * Must be even for interlaced modes.
2391
 */
2392
# define TV_YSIZE_MASK			0x00000fff
2393
# define TV_YSIZE_SHIFT			0
2394
 
2395
#define TV_FILTER_CTL_1		0x68080
2396
/**
2397
 * Enables automatic scaling calculation.
2398
 *
2399
 * If set, the rest of the registers are ignored, and the calculated values can
2400
 * be read back from the register.
2401
 */
2402
# define TV_AUTO_SCALE			(1 << 31)
2403
/**
2404
 * Disables the vertical filter.
2405
 *
2406
 * This is required on modes more than 1024 pixels wide */
2407
# define TV_V_FILTER_BYPASS		(1 << 29)
2408
/** Enables adaptive vertical filtering */
2409
# define TV_VADAPT			(1 << 28)
2410
# define TV_VADAPT_MODE_MASK		(3 << 26)
2411
/** Selects the least adaptive vertical filtering mode */
2412
# define TV_VADAPT_MODE_LEAST		(0 << 26)
2413
/** Selects the moderately adaptive vertical filtering mode */
2414
# define TV_VADAPT_MODE_MODERATE	(1 << 26)
2415
/** Selects the most adaptive vertical filtering mode */
2416
# define TV_VADAPT_MODE_MOST		(3 << 26)
2417
/**
2418
 * Sets the horizontal scaling factor.
2419
 *
2420
 * This should be the fractional part of the horizontal scaling factor divided
2421
 * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
2422
 *
2423
 * (src width - 1) / ((oversample * dest width) - 1)
2424
 */
2425
# define TV_HSCALE_FRAC_MASK		0x00003fff
2426
# define TV_HSCALE_FRAC_SHIFT		0
2427
 
2428
#define TV_FILTER_CTL_2		0x68084
2429
/**
2430
 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2431
 *
2432
 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2433
 */
2434
# define TV_VSCALE_INT_MASK		0x00038000
2435
# define TV_VSCALE_INT_SHIFT		15
2436
/**
2437
 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2438
 *
2439
 * \sa TV_VSCALE_INT_MASK
2440
 */
2441
# define TV_VSCALE_FRAC_MASK		0x00007fff
2442
# define TV_VSCALE_FRAC_SHIFT		0
2443
 
2444
#define TV_FILTER_CTL_3		0x68088
2445
/**
2446
 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2447
 *
2448
 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2449
 *
2450
 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2451
 */
2452
# define TV_VSCALE_IP_INT_MASK		0x00038000
2453
# define TV_VSCALE_IP_INT_SHIFT		15
2454
/**
2455
 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2456
 *
2457
 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2458
 *
2459
 * \sa TV_VSCALE_IP_INT_MASK
2460
 */
2461
# define TV_VSCALE_IP_FRAC_MASK		0x00007fff
2462
# define TV_VSCALE_IP_FRAC_SHIFT		0
2463
 
2464
#define TV_CC_CONTROL		0x68090
2465
# define TV_CC_ENABLE			(1 << 31)
2466
/**
2467
 * Specifies which field to send the CC data in.
2468
 *
2469
 * CC data is usually sent in field 0.
2470
 */
2471
# define TV_CC_FID_MASK			(1 << 27)
2472
# define TV_CC_FID_SHIFT		27
2473
/** Sets the horizontal position of the CC data.  Usually 135. */
2474
# define TV_CC_HOFF_MASK		0x03ff0000
2475
# define TV_CC_HOFF_SHIFT		16
2476
/** Sets the vertical position of the CC data.  Usually 21 */
2477
# define TV_CC_LINE_MASK		0x0000003f
2478
# define TV_CC_LINE_SHIFT		0
2479
 
2480
#define TV_CC_DATA		0x68094
2481
# define TV_CC_RDY			(1 << 31)
2482
/** Second word of CC data to be transmitted. */
2483
# define TV_CC_DATA_2_MASK		0x007f0000
2484
# define TV_CC_DATA_2_SHIFT		16
2485
/** First word of CC data to be transmitted. */
2486
# define TV_CC_DATA_1_MASK		0x0000007f
2487
# define TV_CC_DATA_1_SHIFT		0
2488
 
2489
#define TV_H_LUMA_0		0x68100
2490
#define TV_H_LUMA_59		0x681ec
2491
#define TV_H_CHROMA_0		0x68200
2492
#define TV_H_CHROMA_59		0x682ec
2493
#define TV_V_LUMA_0		0x68300
2494
#define TV_V_LUMA_42		0x683a8
2495
#define TV_V_CHROMA_0		0x68400
2496
#define TV_V_CHROMA_42		0x684a8
2497
 
2498
/* Display Port */
2499
#define DP_A				0x64000 /* eDP */
2500
#define DP_B				0x64100
2501
#define DP_C				0x64200
2502
#define DP_D				0x64300
2503
 
2504
#define   DP_PORT_EN			(1 << 31)
2505
#define   DP_PIPEB_SELECT		(1 << 30)
2506
#define   DP_PIPE_MASK			(1 << 30)
2507
 
2508
/* Link training mode - select a suitable mode for each stage */
2509
#define   DP_LINK_TRAIN_PAT_1		(0 << 28)
2510
#define   DP_LINK_TRAIN_PAT_2		(1 << 28)
2511
#define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
2512
#define   DP_LINK_TRAIN_OFF		(3 << 28)
2513
#define   DP_LINK_TRAIN_MASK		(3 << 28)
2514
#define   DP_LINK_TRAIN_SHIFT		28
2515
 
2516
/* CPT Link training mode */
2517
#define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
2518
#define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
2519
#define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
2520
#define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
2521
#define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
2522
#define   DP_LINK_TRAIN_SHIFT_CPT	8
2523
 
2524
/* Signal voltages. These are mostly controlled by the other end */
2525
#define   DP_VOLTAGE_0_4		(0 << 25)
2526
#define   DP_VOLTAGE_0_6		(1 << 25)
2527
#define   DP_VOLTAGE_0_8		(2 << 25)
2528
#define   DP_VOLTAGE_1_2		(3 << 25)
2529
#define   DP_VOLTAGE_MASK		(7 << 25)
2530
#define   DP_VOLTAGE_SHIFT		25
2531
 
2532
/* Signal pre-emphasis levels, like voltages, the other end tells us what
2533
 * they want
2534
 */
2535
#define   DP_PRE_EMPHASIS_0		(0 << 22)
2536
#define   DP_PRE_EMPHASIS_3_5		(1 << 22)
2537
#define   DP_PRE_EMPHASIS_6		(2 << 22)
2538
#define   DP_PRE_EMPHASIS_9_5		(3 << 22)
2539
#define   DP_PRE_EMPHASIS_MASK		(7 << 22)
2540
#define   DP_PRE_EMPHASIS_SHIFT		22
2541
 
2542
/* How many wires to use. I guess 3 was too hard */
2543
#define   DP_PORT_WIDTH_1		(0 << 19)
2544
#define   DP_PORT_WIDTH_2		(1 << 19)
2545
#define   DP_PORT_WIDTH_4		(3 << 19)
2546
#define   DP_PORT_WIDTH_MASK		(7 << 19)
2547
 
2548
/* Mystic DPCD version 1.1 special mode */
2549
#define   DP_ENHANCED_FRAMING		(1 << 18)
2550
 
2551
/* eDP */
2552
#define   DP_PLL_FREQ_270MHZ		(0 << 16)
2553
#define   DP_PLL_FREQ_160MHZ		(1 << 16)
2554
#define   DP_PLL_FREQ_MASK		(3 << 16)
2555
 
2556
/** locked once port is enabled */
2557
#define   DP_PORT_REVERSAL		(1 << 15)
2558
 
2559
/* eDP */
2560
#define   DP_PLL_ENABLE			(1 << 14)
2561
 
2562
/** sends the clock on lane 15 of the PEG for debug */
2563
#define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
2564
 
2565
#define   DP_SCRAMBLING_DISABLE		(1 << 12)
2566
#define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
2567
 
2568
/** limit RGB values to avoid confusing TVs */
2569
#define   DP_COLOR_RANGE_16_235		(1 << 8)
2570
 
2571
/** Turn on the audio link */
2572
#define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
2573
 
2574
/** vs and hs sync polarity */
2575
#define   DP_SYNC_VS_HIGH		(1 << 4)
2576
#define   DP_SYNC_HS_HIGH		(1 << 3)
2577
 
2578
/** A fantasy */
2579
#define   DP_DETECTED			(1 << 2)
2580
 
2581
/** The aux channel provides a way to talk to the
2582
 * signal sink for DDC etc. Max packet size supported
2583
 * is 20 bytes in each direction, hence the 5 fixed
2584
 * data registers
2585
 */
2586
#define DPA_AUX_CH_CTL			0x64010
2587
#define DPA_AUX_CH_DATA1		0x64014
2588
#define DPA_AUX_CH_DATA2		0x64018
2589
#define DPA_AUX_CH_DATA3		0x6401c
2590
#define DPA_AUX_CH_DATA4		0x64020
2591
#define DPA_AUX_CH_DATA5		0x64024
2592
 
2593
#define DPB_AUX_CH_CTL			0x64110
2594
#define DPB_AUX_CH_DATA1		0x64114
2595
#define DPB_AUX_CH_DATA2		0x64118
2596
#define DPB_AUX_CH_DATA3		0x6411c
2597
#define DPB_AUX_CH_DATA4		0x64120
2598
#define DPB_AUX_CH_DATA5		0x64124
2599
 
2600
#define DPC_AUX_CH_CTL			0x64210
2601
#define DPC_AUX_CH_DATA1		0x64214
2602
#define DPC_AUX_CH_DATA2		0x64218
2603
#define DPC_AUX_CH_DATA3		0x6421c
2604
#define DPC_AUX_CH_DATA4		0x64220
2605
#define DPC_AUX_CH_DATA5		0x64224
2606
 
2607
#define DPD_AUX_CH_CTL			0x64310
2608
#define DPD_AUX_CH_DATA1		0x64314
2609
#define DPD_AUX_CH_DATA2		0x64318
2610
#define DPD_AUX_CH_DATA3		0x6431c
2611
#define DPD_AUX_CH_DATA4		0x64320
2612
#define DPD_AUX_CH_DATA5		0x64324
2613
 
2614
#define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
2615
#define   DP_AUX_CH_CTL_DONE		    (1 << 30)
2616
#define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
2617
#define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
2618
#define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
2619
#define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
2620
#define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
2621
#define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
2622
#define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
2623
#define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
2624
#define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
2625
#define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
2626
#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
2627
#define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
2628
#define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
2629
#define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
2630
#define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
2631
#define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
2632
#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
2633
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
2634
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
2635
 
2636
/*
2637
 * Computing GMCH M and N values for the Display Port link
2638
 *
2639
 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2640
 *
2641
 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2642
 *
2643
 * The GMCH value is used internally
2644
 *
2645
 * bytes_per_pixel is the number of bytes coming out of the plane,
2646
 * which is after the LUTs, so we want the bytes for our color format.
2647
 * For our current usage, this is always 3, one byte for R, G and B.
2648
 */
2649
#define _PIPEA_GMCH_DATA_M			0x70050
2650
#define _PIPEB_GMCH_DATA_M			0x71050
2651
 
2652
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3746 Serge 2653
#define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
2654
#define  TU_SIZE_MASK           (0x3f << 25)
2325 Serge 2655
 
3746 Serge 2656
#define  DATA_LINK_M_N_MASK	(0xffffff)
2657
#define  DATA_LINK_N_MAX	(0x800000)
2325 Serge 2658
 
2659
#define _PIPEA_GMCH_DATA_N			0x70054
2660
#define _PIPEB_GMCH_DATA_N			0x71054
2661
 
2662
/*
2663
 * Computing Link M and N values for the Display Port link
2664
 *
2665
 * Link M / N = pixel_clock / ls_clk
2666
 *
2667
 * (the DP spec calls pixel_clock the 'strm_clk')
2668
 *
2669
 * The Link value is transmitted in the Main Stream
2670
 * Attributes and VB-ID.
2671
 */
2672
 
2673
#define _PIPEA_DP_LINK_M				0x70060
2674
#define _PIPEB_DP_LINK_M				0x71060
2675
 
2676
#define _PIPEA_DP_LINK_N				0x70064
2677
#define _PIPEB_DP_LINK_N				0x71064
2678
 
2679
#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2680
#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2681
#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2682
#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2683
 
2684
/* Display & cursor control */
2685
 
2686
/* Pipe A */
3480 Serge 2687
#define _PIPEADSL		(dev_priv->info->display_mmio_offset + 0x70000)
3031 serge 2688
#define   DSL_LINEMASK_GEN2	0x00000fff
2689
#define   DSL_LINEMASK_GEN3	0x00001fff
3480 Serge 2690
#define _PIPEACONF		(dev_priv->info->display_mmio_offset + 0x70008)
2325 Serge 2691
#define   PIPECONF_ENABLE	(1<<31)
2692
#define   PIPECONF_DISABLE	0
2693
#define   PIPECONF_DOUBLE_WIDE	(1<<30)
2694
#define   I965_PIPECONF_ACTIVE	(1<<30)
3031 serge 2695
#define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2325 Serge 2696
#define   PIPECONF_SINGLE_WIDE	0
2697
#define   PIPECONF_PIPE_UNLOCKED 0
2698
#define   PIPECONF_PIPE_LOCKED	(1<<25)
2699
#define   PIPECONF_PALETTE	0
2700
#define   PIPECONF_GAMMA		(1<<24)
2701
#define   PIPECONF_FORCE_BORDER	(1<<25)
3031 serge 2702
#define   PIPECONF_INTERLACE_MASK	(7 << 21)
3243 Serge 2703
#define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
3031 serge 2704
/* Note that pre-gen3 does not support interlaced display directly. Panel
2705
 * fitting must be disabled on pre-ilk for interlaced. */
2325 Serge 2706
#define   PIPECONF_PROGRESSIVE	(0 << 21)
3031 serge 2707
#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
2708
#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
2325 Serge 2709
#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
3031 serge 2710
#define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
2711
/* Ironlake and later have a complete new set of values for interlaced. PFIT
2712
 * means panel fitter required, PF means progressive fetch, DBL means power
2713
 * saving pixel doubling. */
2714
#define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
2715
#define   PIPECONF_INTERLACED_ILK		(3 << 21)
2716
#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
2717
#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
2325 Serge 2718
#define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
3480 Serge 2719
#define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
2720
#define   PIPECONF_BPC_MASK	(0x7 << 5)
2721
#define   PIPECONF_8BPC		(0<<5)
2722
#define   PIPECONF_10BPC	(1<<5)
2723
#define   PIPECONF_6BPC		(2<<5)
2724
#define   PIPECONF_12BPC	(3<<5)
2325 Serge 2725
#define   PIPECONF_DITHER_EN	(1<<4)
2726
#define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2727
#define   PIPECONF_DITHER_TYPE_SP (0<<2)
2728
#define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
2729
#define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
2730
#define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
3480 Serge 2731
#define _PIPEASTAT		(dev_priv->info->display_mmio_offset + 0x70024)
2325 Serge 2732
#define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
3031 serge 2733
#define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
2325 Serge 2734
#define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
2735
#define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
2736
#define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
3031 serge 2737
#define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
2325 Serge 2738
#define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
2739
#define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
2740
#define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
2741
#define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
3480 Serge 2742
#define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<22)
2325 Serge 2743
#define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
2744
#define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
2745
#define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
2746
#define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
2747
#define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
2748
#define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
3031 serge 2749
#define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
2325 Serge 2750
#define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
3031 serge 2751
#define   SPRITE1_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
3480 Serge 2752
#define   SPRITE0_FLIPDONE_INT_STATUS_VLV	(1UL<<14)
2325 Serge 2753
#define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
2754
#define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
2755
#define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
3031 serge 2756
#define   PLANE_FLIPDONE_INT_STATUS_VLV		(1UL<<10)
2325 Serge 2757
#define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
2758
#define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
2759
#define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
2760
#define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
2761
#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
2762
#define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
2763
#define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
2764
#define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
2765
#define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
2766
#define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
2767
#define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
2768
 
2769
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
3243 Serge 2770
#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
2325 Serge 2771
#define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2772
#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2773
#define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2774
#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2775
 
3480 Serge 2776
#define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
3031 serge 2777
#define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
2778
#define   PIPEB_HLINE_INT_EN			(1<<28)
2779
#define   PIPEB_VBLANK_INT_EN			(1<<27)
2780
#define   SPRITED_FLIPDONE_INT_EN		(1<<26)
2781
#define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
2782
#define   PLANEB_FLIPDONE_INT_EN		(1<<24)
2783
#define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
2784
#define   PIPEA_HLINE_INT_EN			(1<<20)
2785
#define   PIPEA_VBLANK_INT_EN			(1<<19)
2786
#define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
2787
#define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
2788
#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
2789
 
3480 Serge 2790
#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
3031 serge 2791
#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
2792
#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
2793
#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
2794
#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
2795
#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
2796
#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
2797
#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
2798
#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
2799
#define   DPINVGTT_EN_MASK			0xff0000
2800
#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
2801
#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
2802
#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
2803
#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
2804
#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
2805
#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
2806
#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
2807
#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
2808
#define   DPINVGTT_STATUS_MASK			0xff
2809
 
2325 Serge 2810
#define DSPARB			0x70030
2811
#define   DSPARB_CSTART_MASK	(0x7f << 7)
2812
#define   DSPARB_CSTART_SHIFT	7
2813
#define   DSPARB_BSTART_MASK	(0x7f)
2814
#define   DSPARB_BSTART_SHIFT	0
2815
#define   DSPARB_BEND_SHIFT	9 /* on 855 */
2816
#define   DSPARB_AEND_SHIFT	0
2817
 
3480 Serge 2818
#define DSPFW1			(dev_priv->info->display_mmio_offset + 0x70034)
2325 Serge 2819
#define   DSPFW_SR_SHIFT	23
2820
#define   DSPFW_SR_MASK 	(0x1ff<<23)
2821
#define   DSPFW_CURSORB_SHIFT	16
2822
#define   DSPFW_CURSORB_MASK	(0x3f<<16)
2823
#define   DSPFW_PLANEB_SHIFT	8
2824
#define   DSPFW_PLANEB_MASK	(0x7f<<8)
2825
#define   DSPFW_PLANEA_MASK	(0x7f)
3480 Serge 2826
#define DSPFW2			(dev_priv->info->display_mmio_offset + 0x70038)
2325 Serge 2827
#define   DSPFW_CURSORA_MASK	0x00003f00
2828
#define   DSPFW_CURSORA_SHIFT	8
2829
#define   DSPFW_PLANEC_MASK	(0x7f)
3480 Serge 2830
#define DSPFW3			(dev_priv->info->display_mmio_offset + 0x7003c)
2325 Serge 2831
#define   DSPFW_HPLL_SR_EN	(1<<31)
2832
#define   DSPFW_CURSOR_SR_SHIFT	24
2833
#define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
2834
#define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
2835
#define   DSPFW_HPLL_CURSOR_SHIFT	16
2836
#define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
2837
#define   DSPFW_HPLL_SR_MASK		(0x1ff)
3746 Serge 2838
#define DSPFW4			(dev_priv->info->display_mmio_offset + 0x70070)
2839
#define DSPFW7			(dev_priv->info->display_mmio_offset + 0x7007c)
2325 Serge 2840
 
3031 serge 2841
/* drain latency register values*/
2842
#define DRAIN_LATENCY_PRECISION_32	32
2843
#define DRAIN_LATENCY_PRECISION_16	16
3480 Serge 2844
#define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)
3031 serge 2845
#define DDL_CURSORA_PRECISION_32	(1<<31)
2846
#define DDL_CURSORA_PRECISION_16	(0<<31)
2847
#define DDL_CURSORA_SHIFT		24
2848
#define DDL_PLANEA_PRECISION_32		(1<<7)
2849
#define DDL_PLANEA_PRECISION_16		(0<<7)
3480 Serge 2850
#define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
3031 serge 2851
#define DDL_CURSORB_PRECISION_32	(1<<31)
2852
#define DDL_CURSORB_PRECISION_16	(0<<31)
2853
#define DDL_CURSORB_SHIFT		24
2854
#define DDL_PLANEB_PRECISION_32		(1<<7)
2855
#define DDL_PLANEB_PRECISION_16		(0<<7)
2856
 
2325 Serge 2857
/* FIFO watermark sizes etc */
2858
#define G4X_FIFO_LINE_SIZE	64
2859
#define I915_FIFO_LINE_SIZE	64
2860
#define I830_FIFO_LINE_SIZE	32
2861
 
3031 serge 2862
#define VALLEYVIEW_FIFO_SIZE	255
2325 Serge 2863
#define G4X_FIFO_SIZE		127
2864
#define I965_FIFO_SIZE		512
2865
#define I945_FIFO_SIZE		127
2866
#define I915_FIFO_SIZE		95
2867
#define I855GM_FIFO_SIZE	127 /* In cachelines */
2868
#define I830_FIFO_SIZE		95
2869
 
3031 serge 2870
#define VALLEYVIEW_MAX_WM	0xff
2325 Serge 2871
#define G4X_MAX_WM		0x3f
2872
#define I915_MAX_WM		0x3f
2873
 
2874
#define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
2875
#define PINEVIEW_FIFO_LINE_SIZE	64
2876
#define PINEVIEW_MAX_WM		0x1ff
2877
#define PINEVIEW_DFT_WM		0x3f
2878
#define PINEVIEW_DFT_HPLLOFF_WM	0
2879
#define PINEVIEW_GUARD_WM		10
2880
#define PINEVIEW_CURSOR_FIFO		64
2881
#define PINEVIEW_CURSOR_MAX_WM	0x3f
2882
#define PINEVIEW_CURSOR_DFT_WM	0
2883
#define PINEVIEW_CURSOR_GUARD_WM	5
2884
 
3031 serge 2885
#define VALLEYVIEW_CURSOR_MAX_WM 64
2325 Serge 2886
#define I965_CURSOR_FIFO	64
2887
#define I965_CURSOR_MAX_WM	32
2888
#define I965_CURSOR_DFT_WM	8
2889
 
2890
/* define the Watermark register on Ironlake */
2891
#define WM0_PIPEA_ILK		0x45100
2892
#define  WM0_PIPE_PLANE_MASK	(0x7f<<16)
2893
#define  WM0_PIPE_PLANE_SHIFT	16
2894
#define  WM0_PIPE_SPRITE_MASK	(0x3f<<8)
2895
#define  WM0_PIPE_SPRITE_SHIFT	8
2896
#define  WM0_PIPE_CURSOR_MASK	(0x1f)
2897
 
2898
#define WM0_PIPEB_ILK		0x45104
2342 Serge 2899
#define WM0_PIPEC_IVB		0x45200
2325 Serge 2900
#define WM1_LP_ILK		0x45108
2901
#define  WM1_LP_SR_EN		(1<<31)
2902
#define  WM1_LP_LATENCY_SHIFT	24
2903
#define  WM1_LP_LATENCY_MASK	(0x7f<<24)
2904
#define  WM1_LP_FBC_MASK	(0xf<<20)
2905
#define  WM1_LP_FBC_SHIFT	20
2906
#define  WM1_LP_SR_MASK		(0x1ff<<8)
2907
#define  WM1_LP_SR_SHIFT	8
2908
#define  WM1_LP_CURSOR_MASK	(0x3f)
2909
#define WM2_LP_ILK		0x4510c
2910
#define  WM2_LP_EN		(1<<31)
2911
#define WM3_LP_ILK		0x45110
2912
#define  WM3_LP_EN		(1<<31)
2913
#define WM1S_LP_ILK		0x45120
2342 Serge 2914
#define WM2S_LP_IVB		0x45124
2915
#define WM3S_LP_IVB		0x45128
2325 Serge 2916
#define  WM1S_LP_EN		(1<<31)
2917
 
2918
/* Memory latency timer register */
2919
#define MLTR_ILK		0x11222
2920
#define  MLTR_WM1_SHIFT		0
2921
#define  MLTR_WM2_SHIFT		8
2922
/* the unit of memory self-refresh latency time is 0.5us */
2923
#define  ILK_SRLT_MASK		0x3f
2924
#define ILK_LATENCY(shift)	(I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2925
#define ILK_READ_WM1_LATENCY()	ILK_LATENCY(MLTR_WM1_SHIFT)
2926
#define ILK_READ_WM2_LATENCY()	ILK_LATENCY(MLTR_WM2_SHIFT)
2927
 
2928
/* define the fifo size on Ironlake */
2929
#define ILK_DISPLAY_FIFO	128
2930
#define ILK_DISPLAY_MAXWM	64
2931
#define ILK_DISPLAY_DFTWM	8
2932
#define ILK_CURSOR_FIFO		32
2933
#define ILK_CURSOR_MAXWM	16
2934
#define ILK_CURSOR_DFTWM	8
2935
 
2936
#define ILK_DISPLAY_SR_FIFO	512
2937
#define ILK_DISPLAY_MAX_SRWM	0x1ff
2938
#define ILK_DISPLAY_DFT_SRWM	0x3f
2939
#define ILK_CURSOR_SR_FIFO	64
2940
#define ILK_CURSOR_MAX_SRWM	0x3f
2941
#define ILK_CURSOR_DFT_SRWM	8
2942
 
2943
#define ILK_FIFO_LINE_SIZE	64
2944
 
2945
/* define the WM info on Sandybridge */
2946
#define SNB_DISPLAY_FIFO	128
2947
#define SNB_DISPLAY_MAXWM	0x7f	/* bit 16:22 */
2948
#define SNB_DISPLAY_DFTWM	8
2949
#define SNB_CURSOR_FIFO		32
2950
#define SNB_CURSOR_MAXWM	0x1f	/* bit 4:0 */
2951
#define SNB_CURSOR_DFTWM	8
2952
 
2953
#define SNB_DISPLAY_SR_FIFO	512
2954
#define SNB_DISPLAY_MAX_SRWM	0x1ff	/* bit 16:8 */
2955
#define SNB_DISPLAY_DFT_SRWM	0x3f
2956
#define SNB_CURSOR_SR_FIFO	64
2957
#define SNB_CURSOR_MAX_SRWM	0x3f	/* bit 5:0 */
2958
#define SNB_CURSOR_DFT_SRWM	8
2959
 
2960
#define SNB_FBC_MAX_SRWM	0xf	/* bit 23:20 */
2961
 
2962
#define SNB_FIFO_LINE_SIZE	64
2963
 
2964
 
2965
/* the address where we get all kinds of latency value */
2966
#define SSKPD			0x5d10
2967
#define SSKPD_WM_MASK		0x3f
2968
#define SSKPD_WM0_SHIFT		0
2969
#define SSKPD_WM1_SHIFT		8
2970
#define SSKPD_WM2_SHIFT		16
2971
#define SSKPD_WM3_SHIFT		24
2972
 
2973
#define SNB_LATENCY(shift)	(I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2974
#define SNB_READ_WM0_LATENCY()		SNB_LATENCY(SSKPD_WM0_SHIFT)
2975
#define SNB_READ_WM1_LATENCY()		SNB_LATENCY(SSKPD_WM1_SHIFT)
2976
#define SNB_READ_WM2_LATENCY()		SNB_LATENCY(SSKPD_WM2_SHIFT)
2977
#define SNB_READ_WM3_LATENCY()		SNB_LATENCY(SSKPD_WM3_SHIFT)
2978
 
2979
/*
2980
 * The two pipe frame counter registers are not synchronized, so
2981
 * reading a stable value is somewhat tricky. The following code
2982
 * should work:
2983
 *
2984
 *  do {
2985
 *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2986
 *             PIPE_FRAME_HIGH_SHIFT;
2987
 *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2988
 *             PIPE_FRAME_LOW_SHIFT);
2989
 *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2990
 *             PIPE_FRAME_HIGH_SHIFT);
2991
 *  } while (high1 != high2);
2992
 *  frame = (high1 << 8) | low1;
2993
 */
3480 Serge 2994
#define _PIPEAFRAMEHIGH          (dev_priv->info->display_mmio_offset + 0x70040)
2325 Serge 2995
#define   PIPE_FRAME_HIGH_MASK    0x0000ffff
2996
#define   PIPE_FRAME_HIGH_SHIFT   0
3480 Serge 2997
#define _PIPEAFRAMEPIXEL         (dev_priv->info->display_mmio_offset + 0x70044)
2325 Serge 2998
#define   PIPE_FRAME_LOW_MASK     0xff000000
2999
#define   PIPE_FRAME_LOW_SHIFT    24
3000
#define   PIPE_PIXEL_MASK         0x00ffffff
3001
#define   PIPE_PIXEL_SHIFT        0
3002
/* GM45+ just has to be different */
3003
#define _PIPEA_FRMCOUNT_GM45	0x70040
3004
#define _PIPEA_FLIPCOUNT_GM45	0x70044
3005
#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
3006
 
3007
/* Cursor A & B regs */
3480 Serge 3008
#define _CURACNTR		(dev_priv->info->display_mmio_offset + 0x70080)
2325 Serge 3009
/* Old style CUR*CNTR flags (desktop 8xx) */
3010
#define   CURSOR_ENABLE		0x80000000
3011
#define   CURSOR_GAMMA_ENABLE	0x40000000
3012
#define   CURSOR_STRIDE_MASK	0x30000000
3480 Serge 3013
#define   CURSOR_PIPE_CSC_ENABLE (1<<24)
2325 Serge 3014
#define   CURSOR_FORMAT_SHIFT	24
3015
#define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
3016
#define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
3017
#define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
3018
#define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
3019
#define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
3020
#define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
3021
/* New style CUR*CNTR flags */
3022
#define   CURSOR_MODE		0x27
3023
#define   CURSOR_MODE_DISABLE   0x00
3024
#define   CURSOR_MODE_64_32B_AX 0x07
3025
#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
3026
#define   MCURSOR_PIPE_SELECT	(1 << 28)
3027
#define   MCURSOR_PIPE_A	0x00
3028
#define   MCURSOR_PIPE_B	(1 << 28)
3029
#define   MCURSOR_GAMMA_ENABLE  (1 << 26)
3480 Serge 3030
#define _CURABASE		(dev_priv->info->display_mmio_offset + 0x70084)
3031
#define _CURAPOS		(dev_priv->info->display_mmio_offset + 0x70088)
2325 Serge 3032
#define   CURSOR_POS_MASK       0x007FF
3033
#define   CURSOR_POS_SIGN       0x8000
3034
#define   CURSOR_X_SHIFT        0
3035
#define   CURSOR_Y_SHIFT        16
3036
#define CURSIZE			0x700a0
3480 Serge 3037
#define _CURBCNTR		(dev_priv->info->display_mmio_offset + 0x700c0)
3038
#define _CURBBASE		(dev_priv->info->display_mmio_offset + 0x700c4)
3039
#define _CURBPOS		(dev_priv->info->display_mmio_offset + 0x700c8)
2325 Serge 3040
 
2342 Serge 3041
#define _CURBCNTR_IVB		0x71080
3042
#define _CURBBASE_IVB		0x71084
3043
#define _CURBPOS_IVB		0x71088
3044
 
2325 Serge 3045
#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3046
#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3047
#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3048
 
2342 Serge 3049
#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3050
#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3051
#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3052
 
2325 Serge 3053
/* Display A control */
3480 Serge 3054
#define _DSPACNTR                (dev_priv->info->display_mmio_offset + 0x70180)
2325 Serge 3055
#define   DISPLAY_PLANE_ENABLE			(1<<31)
3056
#define   DISPLAY_PLANE_DISABLE			0
3057
#define   DISPPLANE_GAMMA_ENABLE		(1<<30)
3058
#define   DISPPLANE_GAMMA_DISABLE		0
3059
#define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
3243 Serge 3060
#define   DISPPLANE_YUV422			(0x0<<26)
2325 Serge 3061
#define   DISPPLANE_8BPP			(0x2<<26)
3243 Serge 3062
#define   DISPPLANE_BGRA555			(0x3<<26)
3063
#define   DISPPLANE_BGRX555			(0x4<<26)
3064
#define   DISPPLANE_BGRX565			(0x5<<26)
3065
#define   DISPPLANE_BGRX888			(0x6<<26)
3066
#define   DISPPLANE_BGRA888			(0x7<<26)
3067
#define   DISPPLANE_RGBX101010			(0x8<<26)
3068
#define   DISPPLANE_RGBA101010			(0x9<<26)
3069
#define   DISPPLANE_BGRX101010			(0xa<<26)
3070
#define   DISPPLANE_RGBX161616			(0xc<<26)
3071
#define   DISPPLANE_RGBX888			(0xe<<26)
3072
#define   DISPPLANE_RGBA888			(0xf<<26)
2325 Serge 3073
#define   DISPPLANE_STEREO_ENABLE		(1<<25)
3074
#define   DISPPLANE_STEREO_DISABLE		0
3480 Serge 3075
#define   DISPPLANE_PIPE_CSC_ENABLE		(1<<24)
2325 Serge 3076
#define   DISPPLANE_SEL_PIPE_SHIFT		24
3077
#define   DISPPLANE_SEL_PIPE_MASK		(3<
3078
#define   DISPPLANE_SEL_PIPE_A			0
3079
#define   DISPPLANE_SEL_PIPE_B			(1<
3080
#define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
3081
#define   DISPPLANE_SRC_KEY_DISABLE		0
3082
#define   DISPPLANE_LINE_DOUBLE			(1<<20)
3083
#define   DISPPLANE_NO_LINE_DOUBLE		0
3084
#define   DISPPLANE_STEREO_POLARITY_FIRST	0
3085
#define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
3086
#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
3087
#define   DISPPLANE_TILED			(1<<10)
3480 Serge 3088
#define _DSPAADDR		(dev_priv->info->display_mmio_offset + 0x70184)
3089
#define _DSPASTRIDE		(dev_priv->info->display_mmio_offset + 0x70188)
3090
#define _DSPAPOS		(dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
3091
#define _DSPASIZE		(dev_priv->info->display_mmio_offset + 0x70190)
3092
#define _DSPASURF		(dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
3093
#define _DSPATILEOFF		(dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
3094
#define _DSPAOFFSET		(dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
3095
#define _DSPASURFLIVE		(dev_priv->info->display_mmio_offset + 0x701AC)
2325 Serge 3096
 
3097
#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3098
#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3099
#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3100
#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3101
#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3102
#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3103
#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3031 serge 3104
#define DSPLINOFF(plane) DSPADDR(plane)
3243 Serge 3105
#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
3106
#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
2325 Serge 3107
 
3031 serge 3108
/* Display/Sprite base address macros */
3109
#define DISP_BASEADDR_MASK	(0xfffff000)
3110
#define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
3111
#define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
3112
#define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3113
		(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3114
 
2325 Serge 3115
/* VBIOS flags */
3480 Serge 3116
#define SWF00			(dev_priv->info->display_mmio_offset + 0x71410)
3117
#define SWF01			(dev_priv->info->display_mmio_offset + 0x71414)
3118
#define SWF02			(dev_priv->info->display_mmio_offset + 0x71418)
3119
#define SWF03			(dev_priv->info->display_mmio_offset + 0x7141c)
3120
#define SWF04			(dev_priv->info->display_mmio_offset + 0x71420)
3121
#define SWF05			(dev_priv->info->display_mmio_offset + 0x71424)
3122
#define SWF06			(dev_priv->info->display_mmio_offset + 0x71428)
3123
#define SWF10			(dev_priv->info->display_mmio_offset + 0x70410)
3124
#define SWF11			(dev_priv->info->display_mmio_offset + 0x70414)
3125
#define SWF14			(dev_priv->info->display_mmio_offset + 0x71420)
3126
#define SWF30			(dev_priv->info->display_mmio_offset + 0x72414)
3127
#define SWF31			(dev_priv->info->display_mmio_offset + 0x72418)
3128
#define SWF32			(dev_priv->info->display_mmio_offset + 0x7241c)
2325 Serge 3129
 
3130
/* Pipe B */
3480 Serge 3131
#define _PIPEBDSL		(dev_priv->info->display_mmio_offset + 0x71000)
3132
#define _PIPEBCONF		(dev_priv->info->display_mmio_offset + 0x71008)
3133
#define _PIPEBSTAT		(dev_priv->info->display_mmio_offset + 0x71024)
3134
#define _PIPEBFRAMEHIGH		(dev_priv->info->display_mmio_offset + 0x71040)
3135
#define _PIPEBFRAMEPIXEL	(dev_priv->info->display_mmio_offset + 0x71044)
2325 Serge 3136
#define _PIPEB_FRMCOUNT_GM45	0x71040
3137
#define _PIPEB_FLIPCOUNT_GM45	0x71044
3138
 
3139
 
3140
/* Display B control */
3480 Serge 3141
#define _DSPBCNTR		(dev_priv->info->display_mmio_offset + 0x71180)
2325 Serge 3142
#define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
3143
#define   DISPPLANE_ALPHA_TRANS_DISABLE		0
3144
#define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
3145
#define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
3480 Serge 3146
#define _DSPBADDR		(dev_priv->info->display_mmio_offset + 0x71184)
3147
#define _DSPBSTRIDE		(dev_priv->info->display_mmio_offset + 0x71188)
3148
#define _DSPBPOS		(dev_priv->info->display_mmio_offset + 0x7118C)
3149
#define _DSPBSIZE		(dev_priv->info->display_mmio_offset + 0x71190)
3150
#define _DSPBSURF		(dev_priv->info->display_mmio_offset + 0x7119C)
3151
#define _DSPBTILEOFF		(dev_priv->info->display_mmio_offset + 0x711A4)
3152
#define _DSPBOFFSET		(dev_priv->info->display_mmio_offset + 0x711A4)
3153
#define _DSPBSURFLIVE		(dev_priv->info->display_mmio_offset + 0x711AC)
2325 Serge 3154
 
2342 Serge 3155
/* Sprite A control */
3156
#define _DVSACNTR		0x72180
3157
#define   DVS_ENABLE		(1<<31)
3158
#define   DVS_GAMMA_ENABLE	(1<<30)
3159
#define   DVS_PIXFORMAT_MASK	(3<<25)
3160
#define   DVS_FORMAT_YUV422	(0<<25)
3161
#define   DVS_FORMAT_RGBX101010	(1<<25)
3162
#define   DVS_FORMAT_RGBX888	(2<<25)
3163
#define   DVS_FORMAT_RGBX161616	(3<<25)
3480 Serge 3164
#define   DVS_PIPE_CSC_ENABLE   (1<<24)
2342 Serge 3165
#define   DVS_SOURCE_KEY	(1<<22)
3031 serge 3166
#define   DVS_RGB_ORDER_XBGR	(1<<20)
2342 Serge 3167
#define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
3168
#define   DVS_YUV_ORDER_YUYV	(0<<16)
3169
#define   DVS_YUV_ORDER_UYVY	(1<<16)
3170
#define   DVS_YUV_ORDER_YVYU	(2<<16)
3171
#define   DVS_YUV_ORDER_VYUY	(3<<16)
3172
#define   DVS_DEST_KEY		(1<<2)
3173
#define   DVS_TRICKLE_FEED_DISABLE (1<<14)
3174
#define   DVS_TILED		(1<<10)
3175
#define _DVSALINOFF		0x72184
3176
#define _DVSASTRIDE		0x72188
3177
#define _DVSAPOS		0x7218c
3178
#define _DVSASIZE		0x72190
3179
#define _DVSAKEYVAL		0x72194
3180
#define _DVSAKEYMSK		0x72198
3181
#define _DVSASURF		0x7219c
3182
#define _DVSAKEYMAXVAL		0x721a0
3183
#define _DVSATILEOFF		0x721a4
3184
#define _DVSASURFLIVE		0x721ac
3185
#define _DVSASCALE		0x72204
3186
#define   DVS_SCALE_ENABLE	(1<<31)
3187
#define   DVS_FILTER_MASK	(3<<29)
3188
#define   DVS_FILTER_MEDIUM	(0<<29)
3189
#define   DVS_FILTER_ENHANCING	(1<<29)
3190
#define   DVS_FILTER_SOFTENING	(2<<29)
3191
#define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3192
#define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3193
#define _DVSAGAMC		0x72300
3194
 
3195
#define _DVSBCNTR		0x73180
3196
#define _DVSBLINOFF		0x73184
3197
#define _DVSBSTRIDE		0x73188
3198
#define _DVSBPOS		0x7318c
3199
#define _DVSBSIZE		0x73190
3200
#define _DVSBKEYVAL		0x73194
3201
#define _DVSBKEYMSK		0x73198
3202
#define _DVSBSURF		0x7319c
3203
#define _DVSBKEYMAXVAL		0x731a0
3204
#define _DVSBTILEOFF		0x731a4
3205
#define _DVSBSURFLIVE		0x731ac
3206
#define _DVSBSCALE		0x73204
3207
#define _DVSBGAMC		0x73300
3208
 
3209
#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3210
#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3211
#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3212
#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3213
#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3214
#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3215
#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3216
#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3217
#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3218
#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3219
#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3243 Serge 3220
#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
2342 Serge 3221
 
3222
#define _SPRA_CTL		0x70280
3223
#define   SPRITE_ENABLE			(1<<31)
3224
#define   SPRITE_GAMMA_ENABLE		(1<<30)
3225
#define   SPRITE_PIXFORMAT_MASK		(7<<25)
3226
#define   SPRITE_FORMAT_YUV422		(0<<25)
3227
#define   SPRITE_FORMAT_RGBX101010	(1<<25)
3228
#define   SPRITE_FORMAT_RGBX888		(2<<25)
3229
#define   SPRITE_FORMAT_RGBX161616	(3<<25)
3230
#define   SPRITE_FORMAT_YUV444		(4<<25)
3231
#define   SPRITE_FORMAT_XR_BGR101010	(5<<25) /* Extended range */
3480 Serge 3232
#define   SPRITE_PIPE_CSC_ENABLE	(1<<24)
2342 Serge 3233
#define   SPRITE_SOURCE_KEY		(1<<22)
3234
#define   SPRITE_RGB_ORDER_RGBX		(1<<20) /* only for 888 and 161616 */
3235
#define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1<<19)
3236
#define   SPRITE_YUV_CSC_FORMAT_BT709	(1<<18) /* 0 is BT601 */
3237
#define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
3238
#define   SPRITE_YUV_ORDER_YUYV		(0<<16)
3239
#define   SPRITE_YUV_ORDER_UYVY		(1<<16)
3240
#define   SPRITE_YUV_ORDER_YVYU		(2<<16)
3241
#define   SPRITE_YUV_ORDER_VYUY		(3<<16)
3242
#define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
3243
#define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
3244
#define   SPRITE_TILED			(1<<10)
3245
#define   SPRITE_DEST_KEY		(1<<2)
3246
#define _SPRA_LINOFF		0x70284
3247
#define _SPRA_STRIDE		0x70288
3248
#define _SPRA_POS		0x7028c
3249
#define _SPRA_SIZE		0x70290
3250
#define _SPRA_KEYVAL		0x70294
3251
#define _SPRA_KEYMSK		0x70298
3252
#define _SPRA_SURF		0x7029c
3253
#define _SPRA_KEYMAX		0x702a0
3254
#define _SPRA_TILEOFF		0x702a4
3243 Serge 3255
#define _SPRA_OFFSET		0x702a4
3256
#define _SPRA_SURFLIVE		0x702ac
2342 Serge 3257
#define _SPRA_SCALE		0x70304
3258
#define   SPRITE_SCALE_ENABLE	(1<<31)
3259
#define   SPRITE_FILTER_MASK	(3<<29)
3260
#define   SPRITE_FILTER_MEDIUM	(0<<29)
3261
#define   SPRITE_FILTER_ENHANCING	(1<<29)
3262
#define   SPRITE_FILTER_SOFTENING	(2<<29)
3263
#define   SPRITE_VERTICAL_OFFSET_HALF	(1<<28) /* must be enabled below */
3264
#define   SPRITE_VERTICAL_OFFSET_ENABLE	(1<<27)
3265
#define _SPRA_GAMC		0x70400
3266
 
3267
#define _SPRB_CTL		0x71280
3268
#define _SPRB_LINOFF		0x71284
3269
#define _SPRB_STRIDE		0x71288
3270
#define _SPRB_POS		0x7128c
3271
#define _SPRB_SIZE		0x71290
3272
#define _SPRB_KEYVAL		0x71294
3273
#define _SPRB_KEYMSK		0x71298
3274
#define _SPRB_SURF		0x7129c
3275
#define _SPRB_KEYMAX		0x712a0
3276
#define _SPRB_TILEOFF		0x712a4
3243 Serge 3277
#define _SPRB_OFFSET		0x712a4
3278
#define _SPRB_SURFLIVE		0x712ac
2342 Serge 3279
#define _SPRB_SCALE		0x71304
3280
#define _SPRB_GAMC		0x71400
3281
 
3282
#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3283
#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3284
#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3285
#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3286
#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3287
#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3288
#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3289
#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3290
#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3291
#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3243 Serge 3292
#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
2342 Serge 3293
#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3294
#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3243 Serge 3295
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
2342 Serge 3296
 
3746 Serge 3297
#define _SPACNTR		0x72180
3298
#define   SP_ENABLE			(1<<31)
3299
#define   SP_GEAMMA_ENABLE		(1<<30)
3300
#define   SP_PIXFORMAT_MASK		(0xf<<26)
3301
#define   SP_FORMAT_YUV422		(0<<26)
3302
#define   SP_FORMAT_BGR565		(5<<26)
3303
#define   SP_FORMAT_BGRX8888		(6<<26)
3304
#define   SP_FORMAT_BGRA8888		(7<<26)
3305
#define   SP_FORMAT_RGBX1010102		(8<<26)
3306
#define   SP_FORMAT_RGBA1010102		(9<<26)
3307
#define   SP_FORMAT_RGBX8888		(0xe<<26)
3308
#define   SP_FORMAT_RGBA8888		(0xf<<26)
3309
#define   SP_SOURCE_KEY			(1<<22)
3310
#define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
3311
#define   SP_YUV_ORDER_YUYV		(0<<16)
3312
#define   SP_YUV_ORDER_UYVY		(1<<16)
3313
#define   SP_YUV_ORDER_YVYU		(2<<16)
3314
#define   SP_YUV_ORDER_VYUY		(3<<16)
3315
#define   SP_TILED			(1<<10)
3316
#define _SPALINOFF		0x72184
3317
#define _SPASTRIDE		0x72188
3318
#define _SPAPOS			0x7218c
3319
#define _SPASIZE		0x72190
3320
#define _SPAKEYMINVAL		0x72194
3321
#define _SPAKEYMSK		0x72198
3322
#define _SPASURF		0x7219c
3323
#define _SPAKEYMAXVAL		0x721a0
3324
#define _SPATILEOFF		0x721a4
3325
#define _SPACONSTALPHA		0x721a8
3326
#define _SPAGAMC		0x721f4
3327
 
3328
#define _SPBCNTR		0x72280
3329
#define _SPBLINOFF		0x72284
3330
#define _SPBSTRIDE		0x72288
3331
#define _SPBPOS			0x7228c
3332
#define _SPBSIZE		0x72290
3333
#define _SPBKEYMINVAL		0x72294
3334
#define _SPBKEYMSK		0x72298
3335
#define _SPBSURF		0x7229c
3336
#define _SPBKEYMAXVAL		0x722a0
3337
#define _SPBTILEOFF		0x722a4
3338
#define _SPBCONSTALPHA		0x722a8
3339
#define _SPBGAMC		0x722f4
3340
 
3341
#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3342
#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3343
#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3344
#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3345
#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3346
#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3347
#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3348
#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3349
#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3350
#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3351
#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3352
#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3353
 
2325 Serge 3354
/* VBIOS regs */
3355
#define VGACNTRL		0x71400
3356
# define VGA_DISP_DISABLE			(1 << 31)
3357
# define VGA_2X_MODE				(1 << 30)
3358
# define VGA_PIPE_B_SELECT			(1 << 29)
3359
 
3480 Serge 3360
#define VLV_VGACNTRL		(VLV_DISPLAY_BASE + 0x71400)
3361
 
2325 Serge 3362
/* Ironlake */
3363
 
3364
#define CPU_VGACNTRL	0x41000
3365
 
3366
#define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
3367
#define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
3368
#define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
3369
#define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
3370
#define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
3371
#define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
3372
#define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
3373
#define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
3374
#define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
3375
 
3376
/* refresh rate hardware control */
3377
#define RR_HW_CTL       0x45300
3378
#define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
3379
#define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
3380
 
3381
#define FDI_PLL_BIOS_0  0x46000
3382
#define  FDI_PLL_FB_CLOCK_MASK  0xff
3383
#define FDI_PLL_BIOS_1  0x46004
3384
#define FDI_PLL_BIOS_2  0x46008
3385
#define DISPLAY_PORT_PLL_BIOS_0         0x4600c
3386
#define DISPLAY_PORT_PLL_BIOS_1         0x46010
3387
#define DISPLAY_PORT_PLL_BIOS_2         0x46014
3388
 
3389
#define PCH_3DCGDIS0		0x46020
3390
# define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
3391
# define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
3392
 
3393
#define PCH_3DCGDIS1		0x46024
3394
# define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
3395
 
3396
#define FDI_PLL_FREQ_CTL        0x46030
3397
#define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
3398
#define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
3399
#define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
3400
 
3401
 
3480 Serge 3402
#define _PIPEA_DATA_M1           (dev_priv->info->display_mmio_offset + 0x60030)
2325 Serge 3403
#define  PIPE_DATA_M1_OFFSET    0
3480 Serge 3404
#define _PIPEA_DATA_N1           (dev_priv->info->display_mmio_offset + 0x60034)
2325 Serge 3405
#define  PIPE_DATA_N1_OFFSET    0
3406
 
3480 Serge 3407
#define _PIPEA_DATA_M2           (dev_priv->info->display_mmio_offset + 0x60038)
2325 Serge 3408
#define  PIPE_DATA_M2_OFFSET    0
3480 Serge 3409
#define _PIPEA_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6003c)
2325 Serge 3410
#define  PIPE_DATA_N2_OFFSET    0
3411
 
3480 Serge 3412
#define _PIPEA_LINK_M1           (dev_priv->info->display_mmio_offset + 0x60040)
2325 Serge 3413
#define  PIPE_LINK_M1_OFFSET    0
3480 Serge 3414
#define _PIPEA_LINK_N1           (dev_priv->info->display_mmio_offset + 0x60044)
2325 Serge 3415
#define  PIPE_LINK_N1_OFFSET    0
3416
 
3480 Serge 3417
#define _PIPEA_LINK_M2           (dev_priv->info->display_mmio_offset + 0x60048)
2325 Serge 3418
#define  PIPE_LINK_M2_OFFSET    0
3480 Serge 3419
#define _PIPEA_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6004c)
2325 Serge 3420
#define  PIPE_LINK_N2_OFFSET    0
3421
 
3422
/* PIPEB timing regs are same start from 0x61000 */
3423
 
3480 Serge 3424
#define _PIPEB_DATA_M1           (dev_priv->info->display_mmio_offset + 0x61030)
3425
#define _PIPEB_DATA_N1           (dev_priv->info->display_mmio_offset + 0x61034)
2325 Serge 3426
 
3480 Serge 3427
#define _PIPEB_DATA_M2           (dev_priv->info->display_mmio_offset + 0x61038)
3428
#define _PIPEB_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6103c)
2325 Serge 3429
 
3480 Serge 3430
#define _PIPEB_LINK_M1           (dev_priv->info->display_mmio_offset + 0x61040)
3431
#define _PIPEB_LINK_N1           (dev_priv->info->display_mmio_offset + 0x61044)
2325 Serge 3432
 
3480 Serge 3433
#define _PIPEB_LINK_M2           (dev_priv->info->display_mmio_offset + 0x61048)
3434
#define _PIPEB_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6104c)
2325 Serge 3435
 
3243 Serge 3436
#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3437
#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3438
#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3439
#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3440
#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3441
#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3442
#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3443
#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2325 Serge 3444
 
3445
/* CPU panel fitter */
3446
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3447
#define _PFA_CTL_1               0x68080
3448
#define _PFB_CTL_1               0x68880
3449
#define  PF_ENABLE              (1<<31)
3243 Serge 3450
#define  PF_PIPE_SEL_MASK_IVB	(3<<29)
3451
#define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)
2325 Serge 3452
#define  PF_FILTER_MASK		(3<<23)
3453
#define  PF_FILTER_PROGRAMMED	(0<<23)
3454
#define  PF_FILTER_MED_3x3	(1<<23)
3455
#define  PF_FILTER_EDGE_ENHANCE	(2<<23)
3456
#define  PF_FILTER_EDGE_SOFTEN	(3<<23)
3457
#define _PFA_WIN_SZ		0x68074
3458
#define _PFB_WIN_SZ		0x68874
3459
#define _PFA_WIN_POS		0x68070
3460
#define _PFB_WIN_POS		0x68870
3461
#define _PFA_VSCALE		0x68084
3462
#define _PFB_VSCALE		0x68884
3463
#define _PFA_HSCALE		0x68090
3464
#define _PFB_HSCALE		0x68890
3465
 
3466
#define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3467
#define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3468
#define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3469
#define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3470
#define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3471
 
3472
/* legacy palette */
3473
#define _LGC_PALETTE_A           0x4a000
3474
#define _LGC_PALETTE_B           0x4a800
3475
#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3476
 
3477
/* interrupts */
3478
#define DE_MASTER_IRQ_CONTROL   (1 << 31)
3479
#define DE_SPRITEB_FLIP_DONE    (1 << 29)
3480
#define DE_SPRITEA_FLIP_DONE    (1 << 28)
3481
#define DE_PLANEB_FLIP_DONE     (1 << 27)
3482
#define DE_PLANEA_FLIP_DONE     (1 << 26)
3483
#define DE_PCU_EVENT            (1 << 25)
3484
#define DE_GTT_FAULT            (1 << 24)
3485
#define DE_POISON               (1 << 23)
3486
#define DE_PERFORM_COUNTER      (1 << 22)
3487
#define DE_PCH_EVENT            (1 << 21)
3488
#define DE_AUX_CHANNEL_A        (1 << 20)
3489
#define DE_DP_A_HOTPLUG         (1 << 19)
3490
#define DE_GSE                  (1 << 18)
3491
#define DE_PIPEB_VBLANK         (1 << 15)
3492
#define DE_PIPEB_EVEN_FIELD     (1 << 14)
3493
#define DE_PIPEB_ODD_FIELD      (1 << 13)
3494
#define DE_PIPEB_LINE_COMPARE   (1 << 12)
3495
#define DE_PIPEB_VSYNC          (1 << 11)
3496
#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
3497
#define DE_PIPEA_VBLANK         (1 << 7)
3498
#define DE_PIPEA_EVEN_FIELD     (1 << 6)
3499
#define DE_PIPEA_ODD_FIELD      (1 << 5)
3500
#define DE_PIPEA_LINE_COMPARE   (1 << 4)
3501
#define DE_PIPEA_VSYNC          (1 << 3)
3502
#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
3503
 
3504
/* More Ivybridge lolz */
3505
#define DE_ERR_DEBUG_IVB		(1<<30)
3506
#define DE_GSE_IVB			(1<<29)
3507
#define DE_PCH_EVENT_IVB		(1<<28)
3508
#define DE_DP_A_HOTPLUG_IVB		(1<<27)
3509
#define DE_AUX_CHANNEL_A_IVB		(1<<26)
3031 serge 3510
#define DE_SPRITEC_FLIP_DONE_IVB	(1<<14)
3511
#define DE_PLANEC_FLIP_DONE_IVB		(1<<13)
3512
#define DE_PIPEC_VBLANK_IVB		(1<<10)
2325 Serge 3513
#define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
3031 serge 3514
#define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
3515
#define DE_PIPEB_VBLANK_IVB		(1<<5)
2325 Serge 3516
#define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
3517
#define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
3518
#define DE_PIPEA_VBLANK_IVB		(1<<0)
3519
 
3031 serge 3520
#define VLV_MASTER_IER			0x4400c /* Gunit master IER */
3521
#define   MASTER_INTERRUPT_ENABLE	(1<<31)
3522
 
2325 Serge 3523
#define DEISR   0x44000
3524
#define DEIMR   0x44004
3525
#define DEIIR   0x44008
3526
#define DEIER   0x4400c
3527
 
3031 serge 3528
/* GT interrupt.
3529
 * Note that for gen6+ the ring-specific interrupt bits do alias with the
3530
 * corresponding bits in the per-ring interrupt control registers. */
3531
#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT	(1 << 26)
3532
#define GT_GEN6_BLT_CS_ERROR_INTERRUPT		(1 << 25)
3533
#define GT_GEN6_BLT_USER_INTERRUPT		(1 << 22)
3534
#define GT_GEN6_BSD_CS_ERROR_INTERRUPT		(1 << 15)
3535
#define GT_GEN6_BSD_USER_INTERRUPT		(1 << 12)
3536
#define GT_BSD_USER_INTERRUPT			(1 << 5) /* ilk only */
3537
#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT	(1 << 5)
2325 Serge 3538
#define GT_PIPE_NOTIFY		(1 << 4)
3031 serge 3539
#define GT_RENDER_CS_ERROR_INTERRUPT		(1 << 3)
2325 Serge 3540
#define GT_SYNC_STATUS          (1 << 2)
3541
#define GT_USER_INTERRUPT       (1 << 0)
3542
 
3543
#define GTISR   0x44010
3544
#define GTIMR   0x44014
3545
#define GTIIR   0x44018
3546
#define GTIER   0x4401c
3547
 
3548
#define ILK_DISPLAY_CHICKEN2	0x42004
3549
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
3550
#define  ILK_ELPIN_409_SELECT	(1 << 25)
3551
#define  ILK_DPARB_GATE	(1<<22)
3552
#define  ILK_VSDPFD_FULL	(1<<21)
3553
#define ILK_DISPLAY_CHICKEN_FUSES	0x42014
3554
#define  ILK_INTERNAL_GRAPHICS_DISABLE	(1<<31)
3555
#define  ILK_INTERNAL_DISPLAY_DISABLE	(1<<30)
3556
#define  ILK_DISPLAY_DEBUG_DISABLE	(1<<29)
3557
#define  ILK_HDCP_DISABLE		(1<<25)
3558
#define  ILK_eDP_A_DISABLE		(1<<24)
3559
#define  ILK_DESKTOP			(1<<23)
3560
 
3243 Serge 3561
#define ILK_DSPCLK_GATE_D			0x42020
3562
#define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
3563
#define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
3564
#define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
3565
#define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
3566
#define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
2325 Serge 3567
 
2342 Serge 3568
#define IVB_CHICKEN3	0x4200c
3569
# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
3570
# define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
3571
 
2325 Serge 3572
#define DISP_ARB_CTL	0x45000
3573
#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
3574
#define  DISP_FBC_WM_DIS		(1<<15)
3746 Serge 3575
#define GEN7_MSG_CTL	0x45010
3576
#define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
3577
#define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
2325 Serge 3578
 
3031 serge 3579
/* GEN7 chicken */
3580
#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
3581
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
3582
 
3583
#define GEN7_L3CNTLREG1				0xB01C
3584
#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
3243 Serge 3585
#define  GEN7_L3AGDIS				(1<<19)
3031 serge 3586
 
3587
#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
3588
#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
3589
 
3243 Serge 3590
#define GEN7_L3SQCREG4				0xb034
3591
#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
3592
 
3031 serge 3593
/* WaCatErrorRejectionIssue */
3594
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
3595
#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
3596
 
3243 Serge 3597
#define HSW_FUSE_STRAP		0x42014
3598
#define  HSW_CDCLK_LIMIT	(1 << 24)
3599
 
2325 Serge 3600
/* PCH */
3601
 
3031 serge 3602
/* south display engine interrupt: IBX */
2325 Serge 3603
#define SDE_AUDIO_POWER_D	(1 << 27)
3604
#define SDE_AUDIO_POWER_C	(1 << 26)
3605
#define SDE_AUDIO_POWER_B	(1 << 25)
3606
#define SDE_AUDIO_POWER_SHIFT	(25)
3607
#define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
3608
#define SDE_GMBUS		(1 << 24)
3609
#define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
3610
#define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
3611
#define SDE_AUDIO_HDCP_MASK	(3 << 22)
3612
#define SDE_AUDIO_TRANSB	(1 << 21)
3613
#define SDE_AUDIO_TRANSA	(1 << 20)
3614
#define SDE_AUDIO_TRANS_MASK	(3 << 20)
3615
#define SDE_POISON		(1 << 19)
3616
/* 18 reserved */
3617
#define SDE_FDI_RXB		(1 << 17)
3618
#define SDE_FDI_RXA		(1 << 16)
3619
#define SDE_FDI_MASK		(3 << 16)
3620
#define SDE_AUXD		(1 << 15)
3621
#define SDE_AUXC		(1 << 14)
3622
#define SDE_AUXB		(1 << 13)
3623
#define SDE_AUX_MASK		(7 << 13)
3624
/* 12 reserved */
3625
#define SDE_CRT_HOTPLUG         (1 << 11)
3626
#define SDE_PORTD_HOTPLUG       (1 << 10)
3627
#define SDE_PORTC_HOTPLUG       (1 << 9)
3628
#define SDE_PORTB_HOTPLUG       (1 << 8)
3629
#define SDE_SDVOB_HOTPLUG       (1 << 6)
3746 Serge 3630
#define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
3631
				 SDE_SDVOB_HOTPLUG |	\
3632
				 SDE_PORTB_HOTPLUG |	\
3633
				 SDE_PORTC_HOTPLUG |	\
3634
				 SDE_PORTD_HOTPLUG)
2325 Serge 3635
#define SDE_TRANSB_CRC_DONE	(1 << 5)
3636
#define SDE_TRANSB_CRC_ERR	(1 << 4)
3637
#define SDE_TRANSB_FIFO_UNDER	(1 << 3)
3638
#define SDE_TRANSA_CRC_DONE	(1 << 2)
3639
#define SDE_TRANSA_CRC_ERR	(1 << 1)
3640
#define SDE_TRANSA_FIFO_UNDER	(1 << 0)
3641
#define SDE_TRANS_MASK		(0x3f)
3031 serge 3642
 
3643
/* south display engine interrupt: CPT/PPT */
3644
#define SDE_AUDIO_POWER_D_CPT	(1 << 31)
3645
#define SDE_AUDIO_POWER_C_CPT	(1 << 30)
3646
#define SDE_AUDIO_POWER_B_CPT	(1 << 29)
3647
#define SDE_AUDIO_POWER_SHIFT_CPT   29
3648
#define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
3649
#define SDE_AUXD_CPT		(1 << 27)
3650
#define SDE_AUXC_CPT		(1 << 26)
3651
#define SDE_AUXB_CPT		(1 << 25)
3652
#define SDE_AUX_MASK_CPT	(7 << 25)
2325 Serge 3653
#define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
3654
#define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
3655
#define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
3031 serge 3656
#define SDE_CRT_HOTPLUG_CPT	(1 << 19)
3746 Serge 3657
#define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
2325 Serge 3658
#define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
3746 Serge 3659
				 SDE_SDVOB_HOTPLUG_CPT |	\
2325 Serge 3660
				 SDE_PORTD_HOTPLUG_CPT |	\
3661
				 SDE_PORTC_HOTPLUG_CPT |	\
3662
				 SDE_PORTB_HOTPLUG_CPT)
3031 serge 3663
#define SDE_GMBUS_CPT		(1 << 17)
3664
#define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
3665
#define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
3666
#define SDE_FDI_RXC_CPT		(1 << 8)
3667
#define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
3668
#define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
3669
#define SDE_FDI_RXB_CPT		(1 << 4)
3670
#define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
3671
#define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
3672
#define SDE_FDI_RXA_CPT		(1 << 0)
3673
#define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
3674
				 SDE_AUDIO_CP_REQ_B_CPT | \
3675
				 SDE_AUDIO_CP_REQ_A_CPT)
3676
#define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
3677
				 SDE_AUDIO_CP_CHG_B_CPT | \
3678
				 SDE_AUDIO_CP_CHG_A_CPT)
3679
#define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
3680
				 SDE_FDI_RXB_CPT | \
3681
				 SDE_FDI_RXA_CPT)
2325 Serge 3682
 
3683
#define SDEISR  0xc4000
3684
#define SDEIMR  0xc4004
3685
#define SDEIIR  0xc4008
3686
#define SDEIER  0xc400c
3687
 
3688
/* digital port hotplug */
2342 Serge 3689
#define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
2325 Serge 3690
#define PORTD_HOTPLUG_ENABLE            (1 << 20)
3691
#define PORTD_PULSE_DURATION_2ms        (0)
3692
#define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
3693
#define PORTD_PULSE_DURATION_6ms        (2 << 18)
3694
#define PORTD_PULSE_DURATION_100ms      (3 << 18)
2342 Serge 3695
#define PORTD_PULSE_DURATION_MASK	(3 << 18)
3480 Serge 3696
#define PORTD_HOTPLUG_STATUS_MASK	(0x3 << 16)
3697
#define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
2325 Serge 3698
#define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
3480 Serge 3699
#define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
2325 Serge 3700
#define PORTC_HOTPLUG_ENABLE            (1 << 12)
3701
#define PORTC_PULSE_DURATION_2ms        (0)
3702
#define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
3703
#define PORTC_PULSE_DURATION_6ms        (2 << 10)
3704
#define PORTC_PULSE_DURATION_100ms      (3 << 10)
2342 Serge 3705
#define PORTC_PULSE_DURATION_MASK	(3 << 10)
3480 Serge 3706
#define PORTC_HOTPLUG_STATUS_MASK	(0x3 << 8)
3707
#define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
2325 Serge 3708
#define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
3480 Serge 3709
#define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
2325 Serge 3710
#define PORTB_HOTPLUG_ENABLE            (1 << 4)
3711
#define PORTB_PULSE_DURATION_2ms        (0)
3712
#define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
3713
#define PORTB_PULSE_DURATION_6ms        (2 << 2)
3714
#define PORTB_PULSE_DURATION_100ms      (3 << 2)
2342 Serge 3715
#define PORTB_PULSE_DURATION_MASK	(3 << 2)
3480 Serge 3716
#define PORTB_HOTPLUG_STATUS_MASK	(0x3 << 0)
3717
#define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
2325 Serge 3718
#define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
3480 Serge 3719
#define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
2325 Serge 3720
 
3721
#define PCH_GPIOA               0xc5010
3722
#define PCH_GPIOB               0xc5014
3723
#define PCH_GPIOC               0xc5018
3724
#define PCH_GPIOD               0xc501c
3725
#define PCH_GPIOE               0xc5020
3726
#define PCH_GPIOF               0xc5024
3727
 
3728
#define PCH_GMBUS0		0xc5100
3729
#define PCH_GMBUS1		0xc5104
3730
#define PCH_GMBUS2		0xc5108
3731
#define PCH_GMBUS3		0xc510c
3732
#define PCH_GMBUS4		0xc5110
3733
#define PCH_GMBUS5		0xc5120
3734
 
3735
#define _PCH_DPLL_A              0xc6014
3736
#define _PCH_DPLL_B              0xc6018
3031 serge 3737
#define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
2325 Serge 3738
 
3739
#define _PCH_FPA0                0xc6040
3740
#define  FP_CB_TUNE		(0x3<<22)
3741
#define _PCH_FPA1                0xc6044
3742
#define _PCH_FPB0                0xc6048
3743
#define _PCH_FPB1                0xc604c
3031 serge 3744
#define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
3745
#define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
2325 Serge 3746
 
3747
#define PCH_DPLL_TEST           0xc606c
3748
 
3749
#define PCH_DREF_CONTROL        0xC6200
3750
#define  DREF_CONTROL_MASK      0x7fc3
3751
#define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
3752
#define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
3753
#define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
3754
#define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
3755
#define  DREF_SSC_SOURCE_DISABLE                (0<<11)
3756
#define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
3757
#define  DREF_SSC_SOURCE_MASK			(3<<11)
3758
#define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
3759
#define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
3760
#define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
3761
#define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
3762
#define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
3763
#define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
3764
#define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
3765
#define  DREF_SSC4_DOWNSPREAD                   (0<<6)
3766
#define  DREF_SSC4_CENTERSPREAD                 (1<<6)
3767
#define  DREF_SSC1_DISABLE                      (0<<1)
3768
#define  DREF_SSC1_ENABLE                       (1<<1)
3769
#define  DREF_SSC4_DISABLE                      (0)
3770
#define  DREF_SSC4_ENABLE                       (1)
3771
 
3772
#define PCH_RAWCLK_FREQ         0xc6204
3773
#define  FDL_TP1_TIMER_SHIFT    12
3774
#define  FDL_TP1_TIMER_MASK     (3<<12)
3775
#define  FDL_TP2_TIMER_SHIFT    10
3776
#define  FDL_TP2_TIMER_MASK     (3<<10)
3777
#define  RAWCLK_FREQ_MASK       0x3ff
3778
 
3779
#define PCH_DPLL_TMR_CFG        0xc6208
3780
 
3781
#define PCH_SSC4_PARMS          0xc6210
3782
#define PCH_SSC4_AUX_PARMS      0xc6214
3783
 
3784
#define PCH_DPLL_SEL		0xc7000
3785
#define  TRANSA_DPLL_ENABLE	(1<<3)
3786
#define	 TRANSA_DPLLB_SEL	(1<<0)
3787
#define	 TRANSA_DPLLA_SEL	0
3788
#define  TRANSB_DPLL_ENABLE	(1<<7)
3789
#define	 TRANSB_DPLLB_SEL	(1<<4)
3790
#define	 TRANSB_DPLLA_SEL	(0)
3791
#define  TRANSC_DPLL_ENABLE	(1<<11)
3792
#define	 TRANSC_DPLLB_SEL	(1<<8)
3793
#define	 TRANSC_DPLLA_SEL	(0)
3794
 
3795
/* transcoder */
3796
 
3797
#define _TRANS_HTOTAL_A          0xe0000
3798
#define  TRANS_HTOTAL_SHIFT     16
3799
#define  TRANS_HACTIVE_SHIFT    0
3800
#define _TRANS_HBLANK_A          0xe0004
3801
#define  TRANS_HBLANK_END_SHIFT 16
3802
#define  TRANS_HBLANK_START_SHIFT 0
3803
#define _TRANS_HSYNC_A           0xe0008
3804
#define  TRANS_HSYNC_END_SHIFT  16
3805
#define  TRANS_HSYNC_START_SHIFT 0
3806
#define _TRANS_VTOTAL_A          0xe000c
3807
#define  TRANS_VTOTAL_SHIFT     16
3808
#define  TRANS_VACTIVE_SHIFT    0
3809
#define _TRANS_VBLANK_A          0xe0010
3810
#define  TRANS_VBLANK_END_SHIFT 16
3811
#define  TRANS_VBLANK_START_SHIFT 0
3812
#define _TRANS_VSYNC_A           0xe0014
3813
#define  TRANS_VSYNC_END_SHIFT  16
3814
#define  TRANS_VSYNC_START_SHIFT 0
3031 serge 3815
#define _TRANS_VSYNCSHIFT_A	0xe0028
2325 Serge 3816
 
3817
#define _TRANSA_DATA_M1          0xe0030
3818
#define _TRANSA_DATA_N1          0xe0034
3819
#define _TRANSA_DATA_M2          0xe0038
3820
#define _TRANSA_DATA_N2          0xe003c
3821
#define _TRANSA_DP_LINK_M1       0xe0040
3822
#define _TRANSA_DP_LINK_N1       0xe0044
3823
#define _TRANSA_DP_LINK_M2       0xe0048
3824
#define _TRANSA_DP_LINK_N2       0xe004c
3825
 
3826
/* Per-transcoder DIP controls */
3827
 
3828
#define _VIDEO_DIP_CTL_A         0xe0200
3829
#define _VIDEO_DIP_DATA_A        0xe0208
3830
#define _VIDEO_DIP_GCP_A         0xe0210
3831
 
3832
#define _VIDEO_DIP_CTL_B         0xe1200
3833
#define _VIDEO_DIP_DATA_B        0xe1208
3834
#define _VIDEO_DIP_GCP_B         0xe1210
3835
 
3836
#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3837
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3838
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3839
 
3480 Serge 3840
#define VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
3841
#define VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
3842
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
3031 serge 3843
 
3480 Serge 3844
#define VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
3845
#define VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
3846
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
3031 serge 3847
 
3848
#define VLV_TVIDEO_DIP_CTL(pipe) \
3849
	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
3850
#define VLV_TVIDEO_DIP_DATA(pipe) \
3851
	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
3852
#define VLV_TVIDEO_DIP_GCP(pipe) \
3853
	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
3854
 
3855
/* Haswell DIP controls */
3856
#define HSW_VIDEO_DIP_CTL_A		0x60200
3857
#define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
3858
#define HSW_VIDEO_DIP_VS_DATA_A		0x60260
3859
#define HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
3860
#define HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
3861
#define HSW_VIDEO_DIP_VSC_DATA_A	0x60320
3862
#define HSW_VIDEO_DIP_AVI_ECC_A		0x60240
3863
#define HSW_VIDEO_DIP_VS_ECC_A		0x60280
3864
#define HSW_VIDEO_DIP_SPD_ECC_A		0x602C0
3865
#define HSW_VIDEO_DIP_GMP_ECC_A		0x60300
3866
#define HSW_VIDEO_DIP_VSC_ECC_A		0x60344
3867
#define HSW_VIDEO_DIP_GCP_A		0x60210
3868
 
3869
#define HSW_VIDEO_DIP_CTL_B		0x61200
3870
#define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
3871
#define HSW_VIDEO_DIP_VS_DATA_B		0x61260
3872
#define HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
3873
#define HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
3874
#define HSW_VIDEO_DIP_VSC_DATA_B	0x61320
3875
#define HSW_VIDEO_DIP_BVI_ECC_B		0x61240
3876
#define HSW_VIDEO_DIP_VS_ECC_B		0x61280
3877
#define HSW_VIDEO_DIP_SPD_ECC_B		0x612C0
3878
#define HSW_VIDEO_DIP_GMP_ECC_B		0x61300
3879
#define HSW_VIDEO_DIP_VSC_ECC_B		0x61344
3880
#define HSW_VIDEO_DIP_GCP_B		0x61210
3881
 
3746 Serge 3882
#define HSW_TVIDEO_DIP_CTL(trans) \
3883
	 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
3884
#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
3885
	 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
3886
#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
3887
	 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
3888
#define HSW_TVIDEO_DIP_GCP(trans) \
3889
	_TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
3890
#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
3891
	 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
3031 serge 3892
 
2325 Serge 3893
#define _TRANS_HTOTAL_B          0xe1000
3894
#define _TRANS_HBLANK_B          0xe1004
3895
#define _TRANS_HSYNC_B           0xe1008
3896
#define _TRANS_VTOTAL_B          0xe100c
3897
#define _TRANS_VBLANK_B          0xe1010
3898
#define _TRANS_VSYNC_B           0xe1014
3031 serge 3899
#define _TRANS_VSYNCSHIFT_B	 0xe1028
2325 Serge 3900
 
3901
#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3902
#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3903
#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3904
#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3905
#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3906
#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3031 serge 3907
#define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3908
				     _TRANS_VSYNCSHIFT_B)
2325 Serge 3909
 
3910
#define _TRANSB_DATA_M1          0xe1030
3911
#define _TRANSB_DATA_N1          0xe1034
3912
#define _TRANSB_DATA_M2          0xe1038
3913
#define _TRANSB_DATA_N2          0xe103c
3914
#define _TRANSB_DP_LINK_M1       0xe1040
3915
#define _TRANSB_DP_LINK_N1       0xe1044
3916
#define _TRANSB_DP_LINK_M2       0xe1048
3917
#define _TRANSB_DP_LINK_N2       0xe104c
3918
 
3919
#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3920
#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3921
#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3922
#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3923
#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3924
#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3925
#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3926
#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3927
 
3928
#define _TRANSACONF              0xf0008
3929
#define _TRANSBCONF              0xf1008
3930
#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3931
#define  TRANS_DISABLE          (0<<31)
3932
#define  TRANS_ENABLE           (1<<31)
3933
#define  TRANS_STATE_MASK       (1<<30)
3934
#define  TRANS_STATE_DISABLE    (0<<30)
3935
#define  TRANS_STATE_ENABLE     (1<<30)
3936
#define  TRANS_FSYNC_DELAY_HB1  (0<<27)
3937
#define  TRANS_FSYNC_DELAY_HB2  (1<<27)
3938
#define  TRANS_FSYNC_DELAY_HB3  (2<<27)
3939
#define  TRANS_FSYNC_DELAY_HB4  (3<<27)
3031 serge 3940
#define  TRANS_INTERLACE_MASK   (7<<21)
2325 Serge 3941
#define  TRANS_PROGRESSIVE      (0<<21)
3031 serge 3942
#define  TRANS_INTERLACED       (3<<21)
3943
#define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
2325 Serge 3944
#define  TRANS_8BPC             (0<<5)
3945
#define  TRANS_10BPC            (1<<5)
3946
#define  TRANS_6BPC             (2<<5)
3947
#define  TRANS_12BPC            (3<<5)
3948
 
3243 Serge 3949
#define _TRANSA_CHICKEN1	 0xf0060
3950
#define _TRANSB_CHICKEN1	 0xf1060
3951
#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
3952
#define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)
2325 Serge 3953
#define _TRANSA_CHICKEN2	 0xf0064
3954
#define _TRANSB_CHICKEN2	 0xf1064
3955
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3243 Serge 3956
#define  TRANS_CHICKEN2_TIMING_OVERRIDE		(1<<31)
3746 Serge 3957
#define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1<<29)
3958
#define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3<<27)
3959
#define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1<<26)
3960
#define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1<<25)
2325 Serge 3961
 
3962
#define SOUTH_CHICKEN1		0xc2000
3963
#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
3964
#define  FDIA_PHASE_SYNC_SHIFT_EN	18
3965
#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3966
#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3243 Serge 3967
#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
2325 Serge 3968
#define SOUTH_CHICKEN2		0xc2004
3243 Serge 3969
#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
3970
#define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
2325 Serge 3971
#define  DPLS_EDP_PPS_FIX_DIS	(1<<0)
3972
 
3973
#define _FDI_RXA_CHICKEN         0xc200c
3974
#define _FDI_RXB_CHICKEN         0xc2010
3975
#define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
3976
#define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
3977
#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3978
 
3979
#define SOUTH_DSPCLK_GATE_D	0xc2020
3980
#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3243 Serge 3981
#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
2325 Serge 3982
 
3983
/* CPU: FDI_TX */
3984
#define _FDI_TXA_CTL             0x60100
3985
#define _FDI_TXB_CTL             0x61100
3986
#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3987
#define  FDI_TX_DISABLE         (0<<31)
3988
#define  FDI_TX_ENABLE          (1<<31)
3989
#define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
3990
#define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
3991
#define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
3992
#define  FDI_LINK_TRAIN_NONE            (3<<28)
3993
#define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
3994
#define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
3995
#define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
3996
#define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
3997
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3998
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3999
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
4000
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
4001
/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
4002
   SNB has different settings. */
4003
/* SNB A-stepping */
4004
#define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
4005
#define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
4006
#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
4007
#define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
4008
/* SNB B-stepping */
4009
#define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)
4010
#define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)
4011
#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
4012
#define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
4013
#define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
4014
#define  FDI_DP_PORT_WIDTH_X1           (0<<19)
4015
#define  FDI_DP_PORT_WIDTH_X2           (1<<19)
4016
#define  FDI_DP_PORT_WIDTH_X3           (2<<19)
4017
#define  FDI_DP_PORT_WIDTH_X4           (3<<19)
4018
#define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
4019
/* Ironlake: hardwired to 1 */
4020
#define  FDI_TX_PLL_ENABLE              (1<<14)
4021
 
4022
/* Ivybridge has different bits for lolz */
4023
#define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
4024
#define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
4025
#define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
4026
#define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
4027
 
4028
/* both Tx and Rx */
2342 Serge 4029
#define  FDI_COMPOSITE_SYNC		(1<<11)
2325 Serge 4030
#define  FDI_LINK_TRAIN_AUTO		(1<<10)
4031
#define  FDI_SCRAMBLING_ENABLE          (0<<7)
4032
#define  FDI_SCRAMBLING_DISABLE         (1<<7)
4033
 
4034
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
4035
#define _FDI_RXA_CTL             0xf000c
4036
#define _FDI_RXB_CTL             0xf100c
4037
#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
4038
#define  FDI_RX_ENABLE          (1<<31)
4039
/* train, dp width same as FDI_TX */
4040
#define  FDI_FS_ERRC_ENABLE		(1<<27)
4041
#define  FDI_FE_ERRC_ENABLE		(1<<26)
4042
#define  FDI_DP_PORT_WIDTH_X8           (7<<19)
3243 Serge 4043
#define  FDI_RX_POLARITY_REVERSED_LPT	(1<<16)
2325 Serge 4044
#define  FDI_8BPC                       (0<<16)
4045
#define  FDI_10BPC                      (1<<16)
4046
#define  FDI_6BPC                       (2<<16)
4047
#define  FDI_12BPC                      (3<<16)
3480 Serge 4048
#define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1<<15)
2325 Serge 4049
#define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
4050
#define  FDI_RX_PLL_ENABLE              (1<<13)
4051
#define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
4052
#define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
4053
#define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
4054
#define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
4055
#define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
4056
#define  FDI_PCDCLK	                (1<<4)
4057
/* CPT */
4058
#define  FDI_AUTO_TRAINING			(1<<10)
4059
#define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0<<8)
4060
#define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1<<8)
4061
#define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
4062
#define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
4063
#define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
3031 serge 4064
/* LPT */
4065
#define  FDI_PORT_WIDTH_2X_LPT			(1<<19)
4066
#define  FDI_PORT_WIDTH_1X_LPT			(0<<19)
2325 Serge 4067
 
4068
#define _FDI_RXA_MISC            0xf0010
4069
#define _FDI_RXB_MISC            0xf1010
3243 Serge 4070
#define  FDI_RX_PWRDN_LANE1_MASK	(3<<26)
4071
#define  FDI_RX_PWRDN_LANE1_VAL(x)	((x)<<26)
4072
#define  FDI_RX_PWRDN_LANE0_MASK	(3<<24)
4073
#define  FDI_RX_PWRDN_LANE0_VAL(x)	((x)<<24)
4074
#define  FDI_RX_TP1_TO_TP2_48		(2<<20)
4075
#define  FDI_RX_TP1_TO_TP2_64		(3<<20)
4076
#define  FDI_RX_FDI_DELAY_90		(0x90<<0)
4077
#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4078
 
2325 Serge 4079
#define _FDI_RXA_TUSIZE1         0xf0030
4080
#define _FDI_RXA_TUSIZE2         0xf0038
4081
#define _FDI_RXB_TUSIZE1         0xf1030
4082
#define _FDI_RXB_TUSIZE2         0xf1038
4083
#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4084
#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
4085
 
4086
/* FDI_RX interrupt register format */
4087
#define FDI_RX_INTER_LANE_ALIGN         (1<<10)
4088
#define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
4089
#define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
4090
#define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
4091
#define FDI_RX_FS_CODE_ERR              (1<<6)
4092
#define FDI_RX_FE_CODE_ERR              (1<<5)
4093
#define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
4094
#define FDI_RX_HDCP_LINK_FAIL           (1<<3)
4095
#define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
4096
#define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
4097
#define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
4098
 
4099
#define _FDI_RXA_IIR             0xf0014
4100
#define _FDI_RXA_IMR             0xf0018
4101
#define _FDI_RXB_IIR             0xf1014
4102
#define _FDI_RXB_IMR             0xf1018
4103
#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4104
#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
4105
 
4106
#define FDI_PLL_CTL_1           0xfe000
4107
#define FDI_PLL_CTL_2           0xfe004
4108
 
4109
#define PCH_LVDS	0xe1180
4110
#define  LVDS_DETECTED	(1 << 1)
4111
 
3031 serge 4112
/* vlv has 2 sets of panel control regs. */
3480 Serge 4113
#define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
4114
#define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
4115
#define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
4116
#define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
4117
#define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
2325 Serge 4118
 
3480 Serge 4119
#define PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
4120
#define PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
4121
#define PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
4122
#define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
4123
#define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
2325 Serge 4124
 
3746 Serge 4125
#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4126
#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4127
#define VLV_PIPE_PP_ON_DELAYS(pipe) \
4128
		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4129
#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4130
		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4131
#define VLV_PIPE_PP_DIVISOR(pipe) \
4132
		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4133
 
2325 Serge 4134
#define PCH_PP_STATUS		0xc7200
4135
#define PCH_PP_CONTROL		0xc7204
4136
#define  PANEL_UNLOCK_REGS	(0xabcd << 16)
2342 Serge 4137
#define  PANEL_UNLOCK_MASK	(0xffff << 16)
2325 Serge 4138
#define  EDP_FORCE_VDD		(1 << 3)
4139
#define  EDP_BLC_ENABLE		(1 << 2)
4140
#define  PANEL_POWER_RESET	(1 << 1)
4141
#define  PANEL_POWER_OFF	(0 << 0)
4142
#define  PANEL_POWER_ON		(1 << 0)
4143
#define PCH_PP_ON_DELAYS	0xc7208
2342 Serge 4144
#define  PANEL_PORT_SELECT_MASK	(3 << 30)
4145
#define  PANEL_PORT_SELECT_LVDS	(0 << 30)
4146
#define  PANEL_PORT_SELECT_DPA	(1 << 30)
2325 Serge 4147
#define  EDP_PANEL		(1 << 30)
2342 Serge 4148
#define  PANEL_PORT_SELECT_DPC	(2 << 30)
4149
#define  PANEL_PORT_SELECT_DPD	(3 << 30)
4150
#define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
4151
#define  PANEL_POWER_UP_DELAY_SHIFT	16
4152
#define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
4153
#define  PANEL_LIGHT_ON_DELAY_SHIFT	0
4154
 
2325 Serge 4155
#define PCH_PP_OFF_DELAYS	0xc720c
3243 Serge 4156
#define  PANEL_POWER_PORT_SELECT_MASK	(0x3 << 30)
4157
#define  PANEL_POWER_PORT_LVDS		(0 << 30)
4158
#define  PANEL_POWER_PORT_DP_A		(1 << 30)
4159
#define  PANEL_POWER_PORT_DP_C		(2 << 30)
4160
#define  PANEL_POWER_PORT_DP_D		(3 << 30)
2342 Serge 4161
#define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
4162
#define  PANEL_POWER_DOWN_DELAY_SHIFT	16
4163
#define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
4164
#define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
4165
 
2325 Serge 4166
#define PCH_PP_DIVISOR		0xc7210
2342 Serge 4167
#define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
4168
#define  PP_REFERENCE_DIVIDER_SHIFT	8
4169
#define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
4170
#define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
2325 Serge 4171
 
4172
#define PCH_DP_B		0xe4100
4173
#define PCH_DPB_AUX_CH_CTL	0xe4110
4174
#define PCH_DPB_AUX_CH_DATA1	0xe4114
4175
#define PCH_DPB_AUX_CH_DATA2	0xe4118
4176
#define PCH_DPB_AUX_CH_DATA3	0xe411c
4177
#define PCH_DPB_AUX_CH_DATA4	0xe4120
4178
#define PCH_DPB_AUX_CH_DATA5	0xe4124
4179
 
4180
#define PCH_DP_C		0xe4200
4181
#define PCH_DPC_AUX_CH_CTL	0xe4210
4182
#define PCH_DPC_AUX_CH_DATA1	0xe4214
4183
#define PCH_DPC_AUX_CH_DATA2	0xe4218
4184
#define PCH_DPC_AUX_CH_DATA3	0xe421c
4185
#define PCH_DPC_AUX_CH_DATA4	0xe4220
4186
#define PCH_DPC_AUX_CH_DATA5	0xe4224
4187
 
4188
#define PCH_DP_D		0xe4300
4189
#define PCH_DPD_AUX_CH_CTL	0xe4310
4190
#define PCH_DPD_AUX_CH_DATA1	0xe4314
4191
#define PCH_DPD_AUX_CH_DATA2	0xe4318
4192
#define PCH_DPD_AUX_CH_DATA3	0xe431c
4193
#define PCH_DPD_AUX_CH_DATA4	0xe4320
4194
#define PCH_DPD_AUX_CH_DATA5	0xe4324
4195
 
4196
/* CPT */
4197
#define  PORT_TRANS_A_SEL_CPT	0
4198
#define  PORT_TRANS_B_SEL_CPT	(1<<29)
4199
#define  PORT_TRANS_C_SEL_CPT	(2<<29)
4200
#define  PORT_TRANS_SEL_MASK	(3<<29)
4201
#define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
3031 serge 4202
#define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
4203
#define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
2325 Serge 4204
 
4205
#define TRANS_DP_CTL_A		0xe0300
4206
#define TRANS_DP_CTL_B		0xe1300
4207
#define TRANS_DP_CTL_C		0xe2300
3243 Serge 4208
#define TRANS_DP_CTL(pipe)	_PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
2325 Serge 4209
#define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
4210
#define  TRANS_DP_PORT_SEL_B	(0<<29)
4211
#define  TRANS_DP_PORT_SEL_C	(1<<29)
4212
#define  TRANS_DP_PORT_SEL_D	(2<<29)
4213
#define  TRANS_DP_PORT_SEL_NONE	(3<<29)
4214
#define  TRANS_DP_PORT_SEL_MASK	(3<<29)
4215
#define  TRANS_DP_AUDIO_ONLY	(1<<26)
4216
#define  TRANS_DP_ENH_FRAMING	(1<<18)
4217
#define  TRANS_DP_8BPC		(0<<9)
4218
#define  TRANS_DP_10BPC		(1<<9)
4219
#define  TRANS_DP_6BPC		(2<<9)
4220
#define  TRANS_DP_12BPC		(3<<9)
4221
#define  TRANS_DP_BPC_MASK	(3<<9)
4222
#define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1<<4)
4223
#define  TRANS_DP_VSYNC_ACTIVE_LOW	0
4224
#define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1<<3)
4225
#define  TRANS_DP_HSYNC_ACTIVE_LOW	0
4226
#define  TRANS_DP_SYNC_MASK	(3<<3)
4227
 
4228
/* SNB eDP training params */
4229
/* SNB A-stepping */
4230
#define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
4231
#define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
4232
#define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
4233
#define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
4234
/* SNB B-stepping */
4235
#define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)
4236
#define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)
4237
#define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)
4238
#define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)
4239
#define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)
4240
#define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)
4241
 
2342 Serge 4242
/* IVB */
4243
#define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
4244
#define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
4245
#define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
4246
#define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
4247
#define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
4248
#define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
4249
#define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x33 <<22)
4250
 
4251
/* legacy values */
4252
#define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
4253
#define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
4254
#define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
4255
#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
4256
#define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)
4257
 
4258
#define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
4259
 
2325 Serge 4260
#define  FORCEWAKE				0xA18C
3031 serge 4261
#define  FORCEWAKE_VLV				0x1300b0
4262
#define  FORCEWAKE_ACK_VLV			0x1300b4
3746 Serge 4263
#define  FORCEWAKE_MEDIA_VLV			0x1300b8
4264
#define  FORCEWAKE_ACK_MEDIA_VLV		0x1300bc
3031 serge 4265
#define  FORCEWAKE_ACK_HSW			0x130044
2325 Serge 4266
#define  FORCEWAKE_ACK				0x130090
3746 Serge 4267
#define  VLV_GTLC_WAKE_CTRL			0x130090
4268
#define  VLV_GTLC_PW_STATUS			0x130094
2342 Serge 4269
#define  FORCEWAKE_MT				0xa188 /* multi-threaded */
3243 Serge 4270
#define   FORCEWAKE_KERNEL			0x1
4271
#define   FORCEWAKE_USER			0x2
2342 Serge 4272
#define  FORCEWAKE_MT_ACK			0x130040
4273
#define  ECOBUS					0xa180
4274
#define    FORCEWAKE_MT_ENABLE			(1<<5)
2325 Serge 4275
 
3031 serge 4276
#define  GTFIFODBG				0x120000
4277
#define    GT_FIFO_CPU_ERROR_MASK		7
4278
#define    GT_FIFO_OVFERR			(1<<2)
4279
#define    GT_FIFO_IAWRERR			(1<<1)
4280
#define    GT_FIFO_IARDERR			(1<<0)
4281
 
2325 Serge 4282
#define  GT_FIFO_FREE_ENTRIES			0x120008
4283
#define    GT_FIFO_NUM_RESERVED_ENTRIES		20
4284
 
3031 serge 4285
#define GEN6_UCGCTL1				0x9400
4286
# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
4287
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
4288
 
2342 Serge 4289
#define GEN6_UCGCTL2				0x9404
3031 serge 4290
# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
4291
# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
4292
# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
2342 Serge 4293
# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
4294
# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
4295
 
3031 serge 4296
#define GEN7_UCGCTL4				0x940c
4297
#define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
4298
 
2325 Serge 4299
#define GEN6_RPNSWREQ				0xA008
4300
#define   GEN6_TURBO_DISABLE			(1<<31)
4301
#define   GEN6_FREQUENCY(x)			((x)<<25)
3746 Serge 4302
#define   HSW_FREQUENCY(x)			((x)<<24)
2325 Serge 4303
#define   GEN6_OFFSET(x)			((x)<<19)
4304
#define   GEN6_AGGRESSIVE_TURBO			(0<<15)
4305
#define GEN6_RC_VIDEO_FREQ			0xA00C
4306
#define GEN6_RC_CONTROL				0xA090
4307
#define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
4308
#define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
4309
#define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
4310
#define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)
4311
#define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)
4312
#define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
4313
#define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
4314
#define GEN6_RP_DOWN_TIMEOUT			0xA010
4315
#define GEN6_RP_INTERRUPT_LIMITS		0xA014
4316
#define GEN6_RPSTAT1				0xA01C
4317
#define   GEN6_CAGF_SHIFT			8
3480 Serge 4318
#define   HSW_CAGF_SHIFT			7
2325 Serge 4319
#define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
3480 Serge 4320
#define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
2325 Serge 4321
#define GEN6_RP_CONTROL				0xA024
4322
#define   GEN6_RP_MEDIA_TURBO			(1<<11)
2342 Serge 4323
#define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
4324
#define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
4325
#define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2<<9)
4326
#define   GEN6_RP_MEDIA_HW_MODE			(1<<9)
4327
#define   GEN6_RP_MEDIA_SW_MODE			(0<<9)
2325 Serge 4328
#define   GEN6_RP_MEDIA_IS_GFX			(1<<8)
4329
#define   GEN6_RP_ENABLE			(1<<7)
4330
#define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
4331
#define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
4332
#define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
3031 serge 4333
#define   GEN7_RP_DOWN_IDLE_AVG			(0x2<<0)
2325 Serge 4334
#define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
4335
#define GEN6_RP_UP_THRESHOLD			0xA02C
4336
#define GEN6_RP_DOWN_THRESHOLD			0xA030
4337
#define GEN6_RP_CUR_UP_EI			0xA050
4338
#define   GEN6_CURICONT_MASK			0xffffff
4339
#define GEN6_RP_CUR_UP				0xA054
4340
#define   GEN6_CURBSYTAVG_MASK			0xffffff
4341
#define GEN6_RP_PREV_UP				0xA058
4342
#define GEN6_RP_CUR_DOWN_EI			0xA05C
4343
#define   GEN6_CURIAVG_MASK			0xffffff
4344
#define GEN6_RP_CUR_DOWN			0xA060
4345
#define GEN6_RP_PREV_DOWN			0xA064
4346
#define GEN6_RP_UP_EI				0xA068
4347
#define GEN6_RP_DOWN_EI				0xA06C
4348
#define GEN6_RP_IDLE_HYSTERSIS			0xA070
4349
#define GEN6_RC_STATE				0xA094
4350
#define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
4351
#define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
4352
#define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
4353
#define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
4354
#define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
4355
#define GEN6_RC_SLEEP				0xA0B0
4356
#define GEN6_RC1e_THRESHOLD			0xA0B4
4357
#define GEN6_RC6_THRESHOLD			0xA0B8
4358
#define GEN6_RC6p_THRESHOLD			0xA0BC
4359
#define GEN6_RC6pp_THRESHOLD			0xA0C0
4360
#define GEN6_PMINTRMSK				0xA168
4361
 
4362
#define GEN6_PMISR				0x44020
4363
#define GEN6_PMIMR				0x44024 /* rps_lock */
4364
#define GEN6_PMIIR				0x44028
4365
#define GEN6_PMIER				0x4402C
4366
#define  GEN6_PM_MBOX_EVENT			(1<<25)
4367
#define  GEN6_PM_THERMAL_EVENT			(1<<24)
4368
#define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
4369
#define  GEN6_PM_RP_UP_THRESHOLD		(1<<5)
4370
#define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
4371
#define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
4372
#define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
4373
#define  GEN6_PM_DEFERRED_EVENTS		(GEN6_PM_RP_UP_THRESHOLD | \
4374
						 GEN6_PM_RP_DOWN_THRESHOLD | \
4375
						 GEN6_PM_RP_DOWN_TIMEOUT)
4376
 
3031 serge 4377
#define GEN6_GT_GFX_RC6_LOCKED			0x138104
4378
#define GEN6_GT_GFX_RC6				0x138108
4379
#define GEN6_GT_GFX_RC6p			0x13810C
4380
#define GEN6_GT_GFX_RC6pp			0x138110
4381
 
2325 Serge 4382
#define GEN6_PCODE_MAILBOX			0x138124
4383
#define   GEN6_PCODE_READY			(1<<31)
4384
#define   GEN6_READ_OC_PARAMS			0xc
4385
#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
4386
#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
3243 Serge 4387
#define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
4388
#define	  GEN6_PCODE_READ_RC6VIDS		0x5
3480 Serge 4389
#define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
4390
#define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
2325 Serge 4391
#define GEN6_PCODE_DATA				0x138128
4392
#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
3746 Serge 4393
#define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
2325 Serge 4394
 
3746 Serge 4395
#define VLV_IOSF_DOORBELL_REQ			0x182100
4396
#define   IOSF_DEVFN_SHIFT			24
4397
#define   IOSF_OPCODE_SHIFT			16
4398
#define   IOSF_PORT_SHIFT			8
4399
#define   IOSF_BYTE_ENABLES_SHIFT		4
4400
#define   IOSF_BAR_SHIFT			1
4401
#define   IOSF_SB_BUSY				(1<<0)
4402
#define   IOSF_PORT_PUNIT			0x4
4403
#define VLV_IOSF_DATA				0x182104
4404
#define VLV_IOSF_ADDR				0x182108
4405
 
4406
#define PUNIT_OPCODE_REG_READ			6
4407
#define PUNIT_OPCODE_REG_WRITE			7
4408
 
2342 Serge 4409
#define GEN6_GT_CORE_STATUS		0x138060
4410
#define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
4411
#define   GEN6_RCn_MASK			7
4412
#define   GEN6_RC0			0
4413
#define   GEN6_RC3			2
4414
#define   GEN6_RC6			3
4415
#define   GEN6_RC7			4
4416
 
3031 serge 4417
#define GEN7_MISCCPCTL			(0x9424)
4418
#define   GEN7_DOP_CLOCK_GATE_ENABLE	(1<<0)
4419
 
4420
/* IVYBRIDGE DPF */
4421
#define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
4422
#define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
4423
#define   GEN7_PARITY_ERROR_VALID	(1<<13)
4424
#define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
4425
#define   GEN7_L3CDERRST1_SUBBANK_MASK	(7<<8)
4426
#define GEN7_PARITY_ERROR_ROW(reg) \
4427
		((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4428
#define GEN7_PARITY_ERROR_BANK(reg) \
4429
		((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4430
#define GEN7_PARITY_ERROR_SUBBANK(reg) \
4431
		((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4432
#define   GEN7_L3CDERRST1_ENABLE	(1<<7)
4433
 
4434
#define GEN7_L3LOG_BASE			0xB070
4435
#define GEN7_L3LOG_SIZE			0x80
4436
 
3243 Serge 4437
#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
4438
#define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
4439
#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
4440
#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
4441
 
4442
#define GEN7_ROW_CHICKEN2		0xe4f4
4443
#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
4444
#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
4445
 
3480 Serge 4446
#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
2342 Serge 4447
#define INTEL_AUDIO_DEVCL		0x808629FB
4448
#define INTEL_AUDIO_DEVBLC		0x80862801
4449
#define INTEL_AUDIO_DEVCTG		0x80862802
4450
 
4451
#define G4X_AUD_CNTL_ST			0x620B4
4452
#define G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
4453
#define G4X_ELDV_DEVCTG			(1 << 14)
4454
#define G4X_ELD_ADDR			(0xf << 5)
4455
#define G4X_ELD_ACK			(1 << 4)
4456
#define G4X_HDMIW_HDMIEDID		0x6210C
4457
 
4458
#define IBX_HDMIW_HDMIEDID_A		0xE2050
3031 serge 4459
#define IBX_HDMIW_HDMIEDID_B		0xE2150
4460
#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4461
					IBX_HDMIW_HDMIEDID_A, \
4462
					IBX_HDMIW_HDMIEDID_B)
2342 Serge 4463
#define IBX_AUD_CNTL_ST_A		0xE20B4
3031 serge 4464
#define IBX_AUD_CNTL_ST_B		0xE21B4
4465
#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4466
					IBX_AUD_CNTL_ST_A, \
4467
					IBX_AUD_CNTL_ST_B)
2342 Serge 4468
#define IBX_ELD_BUFFER_SIZE		(0x1f << 10)
4469
#define IBX_ELD_ADDRESS			(0x1f << 5)
4470
#define IBX_ELD_ACK			(1 << 4)
4471
#define IBX_AUD_CNTL_ST2		0xE20C0
4472
#define IBX_ELD_VALIDB			(1 << 0)
4473
#define IBX_CP_READYB			(1 << 1)
4474
 
4475
#define CPT_HDMIW_HDMIEDID_A		0xE5050
3031 serge 4476
#define CPT_HDMIW_HDMIEDID_B		0xE5150
4477
#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4478
					CPT_HDMIW_HDMIEDID_A, \
4479
					CPT_HDMIW_HDMIEDID_B)
2342 Serge 4480
#define CPT_AUD_CNTL_ST_A		0xE50B4
3031 serge 4481
#define CPT_AUD_CNTL_ST_B		0xE51B4
4482
#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4483
					CPT_AUD_CNTL_ST_A, \
4484
					CPT_AUD_CNTL_ST_B)
2342 Serge 4485
#define CPT_AUD_CNTRL_ST2		0xE50C0
4486
 
4487
/* These are the 4 32-bit write offset registers for each stream
4488
 * output buffer.  It determines the offset from the
4489
 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4490
 */
4491
#define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
4492
 
3031 serge 4493
#define IBX_AUD_CONFIG_A			0xe2000
4494
#define IBX_AUD_CONFIG_B			0xe2100
4495
#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4496
					IBX_AUD_CONFIG_A, \
4497
					IBX_AUD_CONFIG_B)
4498
#define CPT_AUD_CONFIG_A			0xe5000
4499
#define CPT_AUD_CONFIG_B			0xe5100
4500
#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4501
					CPT_AUD_CONFIG_A, \
4502
					CPT_AUD_CONFIG_B)
4503
#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
4504
#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
4505
#define   AUD_CONFIG_UPPER_N_SHIFT		20
4506
#define   AUD_CONFIG_UPPER_N_VALUE		(0xff << 20)
4507
#define   AUD_CONFIG_LOWER_N_SHIFT		4
4508
#define   AUD_CONFIG_LOWER_N_VALUE		(0xfff << 4)
4509
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
4510
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI		(0xf << 16)
4511
#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
4512
 
4513
/* HSW Audio */
4514
#define   HSW_AUD_CONFIG_A		0x65000 /* Audio Configuration Transcoder A */
4515
#define   HSW_AUD_CONFIG_B		0x65100 /* Audio Configuration Transcoder B */
4516
#define   HSW_AUD_CFG(pipe) _PIPE(pipe, \
4517
					HSW_AUD_CONFIG_A, \
4518
					HSW_AUD_CONFIG_B)
4519
 
4520
#define   HSW_AUD_MISC_CTRL_A		0x65010 /* Audio Misc Control Convert 1 */
4521
#define   HSW_AUD_MISC_CTRL_B		0x65110 /* Audio Misc Control Convert 2 */
4522
#define   HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
4523
					HSW_AUD_MISC_CTRL_A, \
4524
					HSW_AUD_MISC_CTRL_B)
4525
 
4526
#define   HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4 /* Audio DIP and ELD Control State Transcoder A */
4527
#define   HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4 /* Audio DIP and ELD Control State Transcoder B */
4528
#define   HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
4529
					HSW_AUD_DIP_ELD_CTRL_ST_A, \
4530
					HSW_AUD_DIP_ELD_CTRL_ST_B)
4531
 
4532
/* Audio Digital Converter */
4533
#define   HSW_AUD_DIG_CNVT_1		0x65080 /* Audio Converter 1 */
4534
#define   HSW_AUD_DIG_CNVT_2		0x65180 /* Audio Converter 1 */
4535
#define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
4536
					HSW_AUD_DIG_CNVT_1, \
4537
					HSW_AUD_DIG_CNVT_2)
4538
#define   DIP_PORT_SEL_MASK		0x3
4539
 
4540
#define   HSW_AUD_EDID_DATA_A		0x65050
4541
#define   HSW_AUD_EDID_DATA_B		0x65150
4542
#define   HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
4543
					HSW_AUD_EDID_DATA_A, \
4544
					HSW_AUD_EDID_DATA_B)
4545
 
4546
#define   HSW_AUD_PIPE_CONV_CFG		0x6507c /* Audio pipe and converter configs */
4547
#define   HSW_AUD_PIN_ELD_CP_VLD	0x650c0 /* Audio ELD and CP Ready Status */
4548
#define   AUDIO_INACTIVE_C		(1<<11)
4549
#define   AUDIO_INACTIVE_B		(1<<7)
4550
#define   AUDIO_INACTIVE_A		(1<<3)
4551
#define   AUDIO_OUTPUT_ENABLE_A		(1<<2)
4552
#define   AUDIO_OUTPUT_ENABLE_B		(1<<6)
4553
#define   AUDIO_OUTPUT_ENABLE_C		(1<<10)
4554
#define   AUDIO_ELD_VALID_A		(1<<0)
4555
#define   AUDIO_ELD_VALID_B		(1<<4)
4556
#define   AUDIO_ELD_VALID_C		(1<<8)
4557
#define   AUDIO_CP_READY_A		(1<<1)
4558
#define   AUDIO_CP_READY_B		(1<<5)
4559
#define   AUDIO_CP_READY_C		(1<<9)
4560
 
4561
/* HSW Power Wells */
3480 Serge 4562
#define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
4563
#define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
4564
#define HSW_PWR_WELL_KVMR			0x45408 /* CTL3 */
4565
#define HSW_PWR_WELL_DEBUG			0x4540C /* CTL4 */
3031 serge 4566
#define   HSW_PWR_WELL_ENABLE				(1<<31)
4567
#define   HSW_PWR_WELL_STATE				(1<<30)
4568
#define HSW_PWR_WELL_CTL5		0x45410
4569
#define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
4570
#define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
4571
#define   HSW_PWR_WELL_FORCE_ON				(1<<19)
4572
#define HSW_PWR_WELL_CTL6		0x45414
4573
 
4574
/* Per-pipe DDI Function Control */
3243 Serge 4575
#define TRANS_DDI_FUNC_CTL_A		0x60400
4576
#define TRANS_DDI_FUNC_CTL_B		0x61400
4577
#define TRANS_DDI_FUNC_CTL_C		0x62400
4578
#define TRANS_DDI_FUNC_CTL_EDP		0x6F400
4579
#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
4580
						   TRANS_DDI_FUNC_CTL_B)
4581
#define  TRANS_DDI_FUNC_ENABLE		(1<<31)
3031 serge 4582
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
3243 Serge 4583
#define  TRANS_DDI_PORT_MASK		(7<<28)
4584
#define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
4585
#define  TRANS_DDI_PORT_NONE		(0<<28)
4586
#define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
4587
#define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
4588
#define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)
4589
#define  TRANS_DDI_MODE_SELECT_DP_SST	(2<<24)
4590
#define  TRANS_DDI_MODE_SELECT_DP_MST	(3<<24)
4591
#define  TRANS_DDI_MODE_SELECT_FDI	(4<<24)
4592
#define  TRANS_DDI_BPC_MASK		(7<<20)
4593
#define  TRANS_DDI_BPC_8		(0<<20)
4594
#define  TRANS_DDI_BPC_10		(1<<20)
4595
#define  TRANS_DDI_BPC_6		(2<<20)
4596
#define  TRANS_DDI_BPC_12		(3<<20)
4597
#define  TRANS_DDI_PVSYNC		(1<<17)
4598
#define  TRANS_DDI_PHSYNC		(1<<16)
4599
#define  TRANS_DDI_EDP_INPUT_MASK	(7<<12)
4600
#define  TRANS_DDI_EDP_INPUT_A_ON	(0<<12)
4601
#define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
4602
#define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
4603
#define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
4604
#define  TRANS_DDI_BFI_ENABLE		(1<<4)
4605
#define  TRANS_DDI_PORT_WIDTH_X1	(0<<1)
4606
#define  TRANS_DDI_PORT_WIDTH_X2	(1<<1)
4607
#define  TRANS_DDI_PORT_WIDTH_X4	(3<<1)
3031 serge 4608
 
4609
/* DisplayPort Transport Control */
4610
#define DP_TP_CTL_A			0x64040
4611
#define DP_TP_CTL_B			0x64140
4612
#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
4613
#define  DP_TP_CTL_ENABLE		(1<<31)
4614
#define  DP_TP_CTL_MODE_SST	(0<<27)
4615
#define  DP_TP_CTL_MODE_MST	(1<<27)
4616
#define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
4617
#define  DP_TP_CTL_FDI_AUTOTRAIN	(1<<15)
4618
#define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
4619
#define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
4620
#define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
3243 Serge 4621
#define  DP_TP_CTL_LINK_TRAIN_PAT3		(4<<8)
4622
#define  DP_TP_CTL_LINK_TRAIN_IDLE		(2<<8)
3031 serge 4623
#define  DP_TP_CTL_LINK_TRAIN_NORMAL	(3<<8)
3243 Serge 4624
#define  DP_TP_CTL_SCRAMBLE_DISABLE		(1<<7)
3031 serge 4625
 
4626
/* DisplayPort Transport Status */
4627
#define DP_TP_STATUS_A			0x64044
4628
#define DP_TP_STATUS_B			0x64144
4629
#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
3243 Serge 4630
#define  DP_TP_STATUS_IDLE_DONE		(1<<25)
3031 serge 4631
#define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
4632
 
4633
/* DDI Buffer Control */
4634
#define DDI_BUF_CTL_A				0x64000
4635
#define DDI_BUF_CTL_B				0x64100
4636
#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
4637
#define  DDI_BUF_CTL_ENABLE				(1<<31)
4638
#define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
4639
#define  DDI_BUF_EMP_400MV_3_5DB_HSW	(1<<24)   /* Sel1 */
4640
#define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
4641
#define  DDI_BUF_EMP_400MV_9_5DB_HSW	(3<<24)   /* Sel3 */
4642
#define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */
4643
#define  DDI_BUF_EMP_600MV_3_5DB_HSW	(5<<24)   /* Sel5 */
4644
#define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
4645
#define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
4646
#define  DDI_BUF_EMP_800MV_3_5DB_HSW	(8<<24)   /* Sel8 */
4647
#define  DDI_BUF_EMP_MASK				(0xf<<24)
3480 Serge 4648
#define  DDI_BUF_PORT_REVERSAL			(1<<16)
3031 serge 4649
#define  DDI_BUF_IS_IDLE				(1<<7)
3243 Serge 4650
#define  DDI_A_4_LANES				(1<<4)
3031 serge 4651
#define  DDI_PORT_WIDTH_X1				(0<<1)
4652
#define  DDI_PORT_WIDTH_X2				(1<<1)
4653
#define  DDI_PORT_WIDTH_X4				(3<<1)
4654
#define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
4655
 
4656
/* DDI Buffer Translations */
4657
#define DDI_BUF_TRANS_A				0x64E00
4658
#define DDI_BUF_TRANS_B				0x64E60
4659
#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
4660
 
4661
/* Sideband Interface (SBI) is programmed indirectly, via
4662
 * SBI_ADDR, which contains the register offset; and SBI_DATA,
4663
 * which contains the payload */
4664
#define SBI_ADDR				0xC6000
4665
#define SBI_DATA				0xC6004
4666
#define SBI_CTL_STAT			0xC6008
3243 Serge 4667
#define  SBI_CTL_DEST_ICLK		(0x0<<16)
4668
#define  SBI_CTL_DEST_MPHY		(0x1<<16)
4669
#define  SBI_CTL_OP_IORD		(0x2<<8)
4670
#define  SBI_CTL_OP_IOWR		(0x3<<8)
3031 serge 4671
#define  SBI_CTL_OP_CRRD		(0x6<<8)
4672
#define  SBI_CTL_OP_CRWR		(0x7<<8)
4673
#define  SBI_RESPONSE_FAIL		(0x1<<1)
4674
#define  SBI_RESPONSE_SUCCESS	(0x0<<1)
4675
#define  SBI_BUSY				(0x1<<0)
4676
#define  SBI_READY				(0x0<<0)
4677
 
4678
/* SBI offsets */
4679
#define  SBI_SSCDIVINTPHASE6		0x0600
4680
#define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	((0x7f)<<1)
4681
#define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x)<<1)
4682
#define   SBI_SSCDIVINTPHASE_INCVAL_MASK	((0x7f)<<8)
4683
#define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x)<<8)
4684
#define   SBI_SSCDIVINTPHASE_DIR(x)			((x)<<15)
4685
#define   SBI_SSCDIVINTPHASE_PROPAGATE		(1<<0)
4686
#define  SBI_SSCCTL					0x020c
4687
#define  SBI_SSCCTL6				0x060C
3243 Serge 4688
#define   SBI_SSCCTL_PATHALT			(1<<3)
3031 serge 4689
#define   SBI_SSCCTL_DISABLE		(1<<0)
4690
#define  SBI_SSCAUXDIV6				0x0610
4691
#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)
4692
#define  SBI_DBUFF0					0x2a00
3243 Serge 4693
#define   SBI_DBUFF0_ENABLE			(1<<0)
3031 serge 4694
 
4695
/* LPT PIXCLK_GATE */
4696
#define PIXCLK_GATE				0xC6020
4697
#define  PIXCLK_GATE_UNGATE		(1<<0)
4698
#define  PIXCLK_GATE_GATE		(0<<0)
4699
 
4700
/* SPLL */
4701
#define SPLL_CTL				0x46020
4702
#define  SPLL_PLL_ENABLE		(1<<31)
3243 Serge 4703
#define  SPLL_PLL_SSC			(1<<28)
4704
#define  SPLL_PLL_NON_SSC		(2<<28)
3031 serge 4705
#define  SPLL_PLL_FREQ_810MHz	(0<<26)
4706
#define  SPLL_PLL_FREQ_1350MHz	(1<<26)
4707
 
4708
/* WRPLL */
4709
#define WRPLL_CTL1				0x46040
4710
#define WRPLL_CTL2				0x46060
4711
#define  WRPLL_PLL_ENABLE				(1<<31)
4712
#define  WRPLL_PLL_SELECT_SSC			(0x01<<28)
3243 Serge 4713
#define  WRPLL_PLL_SELECT_NON_SSC	(0x02<<28)
3031 serge 4714
#define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)
4715
/* WRPLL divider programming */
4716
#define  WRPLL_DIVIDER_REFERENCE(x)		((x)<<0)
4717
#define  WRPLL_DIVIDER_POST(x)			((x)<<8)
4718
#define  WRPLL_DIVIDER_FEEDBACK(x)		((x)<<16)
4719
 
4720
/* Port clock selection */
4721
#define PORT_CLK_SEL_A			0x46100
4722
#define PORT_CLK_SEL_B			0x46104
4723
#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
4724
#define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
4725
#define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
4726
#define  PORT_CLK_SEL_LCPLL_810		(2<<29)
4727
#define  PORT_CLK_SEL_SPLL			(3<<29)
4728
#define  PORT_CLK_SEL_WRPLL1		(4<<29)
4729
#define  PORT_CLK_SEL_WRPLL2		(5<<29)
3243 Serge 4730
#define  PORT_CLK_SEL_NONE		(7<<29)
3031 serge 4731
 
3243 Serge 4732
/* Transcoder clock selection */
4733
#define TRANS_CLK_SEL_A			0x46140
4734
#define TRANS_CLK_SEL_B			0x46144
4735
#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
4736
/* For each transcoder, we need to select the corresponding port clock */
4737
#define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
4738
#define  TRANS_CLK_SEL_PORT(x)		((x+1)<<29)
3031 serge 4739
 
3243 Serge 4740
#define _TRANSA_MSA_MISC		0x60410
4741
#define _TRANSB_MSA_MISC		0x61410
4742
#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
4743
					       _TRANSB_MSA_MISC)
4744
#define  TRANS_MSA_SYNC_CLK		(1<<0)
4745
#define  TRANS_MSA_6_BPC		(0<<5)
4746
#define  TRANS_MSA_8_BPC		(1<<5)
4747
#define  TRANS_MSA_10_BPC		(2<<5)
4748
#define  TRANS_MSA_12_BPC		(3<<5)
4749
#define  TRANS_MSA_16_BPC		(4<<5)
4750
 
3031 serge 4751
/* LCPLL Control */
4752
#define LCPLL_CTL				0x130040
4753
#define  LCPLL_PLL_DISABLE		(1<<31)
4754
#define  LCPLL_PLL_LOCK			(1<<30)
3243 Serge 4755
#define  LCPLL_CLK_FREQ_MASK		(3<<26)
4756
#define  LCPLL_CLK_FREQ_450		(0<<26)
3031 serge 4757
#define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
4758
#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
3243 Serge 4759
#define  LCPLL_CD_SOURCE_FCLK		(1<<21)
3031 serge 4760
 
4761
/* Pipe WM_LINETIME - watermark line time */
4762
#define PIPE_WM_LINETIME_A		0x45270
4763
#define PIPE_WM_LINETIME_B		0x45274
4764
#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
4765
					PIPE_WM_LINETIME_B)
4766
#define   PIPE_WM_LINETIME_MASK		(0x1ff)
4767
#define   PIPE_WM_LINETIME_TIME(x)			((x))
4768
#define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
4769
#define   PIPE_WM_LINETIME_IPS_LINETIME(x)		((x)<<16)
4770
 
4771
/* SFUSE_STRAP */
4772
#define SFUSE_STRAP				0xc2014
4773
#define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
4774
#define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
4775
#define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
4776
 
4777
#define WM_DBG				0x45280
4778
#define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
4779
#define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
4780
#define  WM_DBG_DISALLOW_SPRITE		(1<<2)
4781
 
3480 Serge 4782
/* pipe CSC */
4783
#define _PIPE_A_CSC_COEFF_RY_GY	0x49010
4784
#define _PIPE_A_CSC_COEFF_BY	0x49014
4785
#define _PIPE_A_CSC_COEFF_RU_GU	0x49018
4786
#define _PIPE_A_CSC_COEFF_BU	0x4901c
4787
#define _PIPE_A_CSC_COEFF_RV_GV	0x49020
4788
#define _PIPE_A_CSC_COEFF_BV	0x49024
4789
#define _PIPE_A_CSC_MODE	0x49028
4790
#define _PIPE_A_CSC_PREOFF_HI	0x49030
4791
#define _PIPE_A_CSC_PREOFF_ME	0x49034
4792
#define _PIPE_A_CSC_PREOFF_LO	0x49038
4793
#define _PIPE_A_CSC_POSTOFF_HI	0x49040
4794
#define _PIPE_A_CSC_POSTOFF_ME	0x49044
4795
#define _PIPE_A_CSC_POSTOFF_LO	0x49048
4796
 
4797
#define _PIPE_B_CSC_COEFF_RY_GY	0x49110
4798
#define _PIPE_B_CSC_COEFF_BY	0x49114
4799
#define _PIPE_B_CSC_COEFF_RU_GU	0x49118
4800
#define _PIPE_B_CSC_COEFF_BU	0x4911c
4801
#define _PIPE_B_CSC_COEFF_RV_GV	0x49120
4802
#define _PIPE_B_CSC_COEFF_BV	0x49124
4803
#define _PIPE_B_CSC_MODE	0x49128
4804
#define _PIPE_B_CSC_PREOFF_HI	0x49130
4805
#define _PIPE_B_CSC_PREOFF_ME	0x49134
4806
#define _PIPE_B_CSC_PREOFF_LO	0x49138
4807
#define _PIPE_B_CSC_POSTOFF_HI	0x49140
4808
#define _PIPE_B_CSC_POSTOFF_ME	0x49144
4809
#define _PIPE_B_CSC_POSTOFF_LO	0x49148
4810
 
4811
#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
4812
#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
4813
#define CSC_MODE_YUV_TO_RGB (1 << 0)
4814
 
4815
#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
4816
#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
4817
#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
4818
#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
4819
#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
4820
#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
4821
#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
4822
#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
4823
#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
4824
#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
4825
#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
4826
#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
4827
#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
4828
 
2325 Serge 4829
#endif /* _I915_REG_H_ */