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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-

 */

/*

 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation the rights to use, copy, modify, merge, publish,

 * distribute, sub license, and/or sell copies of the Software, and to

 * permit persons to whom the Software is furnished to do so, subject to

 * the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial portions

 * of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include 

#include 

#include 

#include "i915_drv.h"

#include "i915_trace.h"

#include "intel_drv.h"

#define assert_spin_locked(a)

static const u32 hpd_ibx[] = {

	[HPD_CRT] = SDE_CRT_HOTPLUG,

	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,

	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,

	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,

	[HPD_PORT_D] = SDE_PORTD_HOTPLUG

};

static const u32 hpd_cpt[] = {

	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,

	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,

	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,

	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,

	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT

};

static const u32 hpd_mask_i915[] = {

	[HPD_CRT] = CRT_HOTPLUG_INT_EN,

	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,

	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,

	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,

	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,

	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN

};

static const u32 hpd_status_gen4[] = {

	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,

	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,

	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,

	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,

	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,

	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS

};

static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */

	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,

	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,

	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,

	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,

	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,

	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS

};

#define pr_err(fmt, ...) \

        printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)

#define DRM_WAKEUP( queue ) wake_up( queue )

#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )

#define MAX_NOPID ((u32)~0)

/* For display hotplug interrupt */

static void

ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)

{

	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->pc8.irqs_disabled) {

		WARN(1, "IRQs disabled\n");

		dev_priv->pc8.regsave.deimr &= ~mask;

		return;

	}

    if ((dev_priv->irq_mask & mask) != 0) {

        dev_priv->irq_mask &= ~mask;

        I915_WRITE(DEIMR, dev_priv->irq_mask);

        POSTING_READ(DEIMR);

    }

}

static void

ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)

{

	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->pc8.irqs_disabled) {

		WARN(1, "IRQs disabled\n");

		dev_priv->pc8.regsave.deimr |= mask;

		return;

	}

    if ((dev_priv->irq_mask & mask) != mask) {

        dev_priv->irq_mask |= mask;

        I915_WRITE(DEIMR, dev_priv->irq_mask);

        POSTING_READ(DEIMR);

    }

}

/**

 * ilk_update_gt_irq - update GTIMR

 * @dev_priv: driver private

 * @interrupt_mask: mask of interrupt bits to update

 * @enabled_irq_mask: mask of interrupt bits to enable

 */

static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,

			      uint32_t interrupt_mask,

			      uint32_t enabled_irq_mask)

{

	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->pc8.irqs_disabled) {

		WARN(1, "IRQs disabled\n");

		dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;

		dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &

						interrupt_mask);

		return;

	}

	dev_priv->gt_irq_mask &= ~interrupt_mask;

	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);

	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);

	POSTING_READ(GTIMR);

}

void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)

{

	ilk_update_gt_irq(dev_priv, mask, mask);

}

void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)

{

	ilk_update_gt_irq(dev_priv, mask, 0);

}

/**

  * snb_update_pm_irq - update GEN6_PMIMR

  * @dev_priv: driver private

  * @interrupt_mask: mask of interrupt bits to update

  * @enabled_irq_mask: mask of interrupt bits to enable

  */

static void snb_update_pm_irq(struct drm_i915_private *dev_priv,

			      uint32_t interrupt_mask,

			      uint32_t enabled_irq_mask)

{

	uint32_t new_val;

	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->pc8.irqs_disabled) {

		WARN(1, "IRQs disabled\n");

		dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;

		dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &

						     interrupt_mask);

		return;

	}

	new_val = dev_priv->pm_irq_mask;

	new_val &= ~interrupt_mask;

	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != dev_priv->pm_irq_mask) {

		dev_priv->pm_irq_mask = new_val;

		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);

		POSTING_READ(GEN6_PMIMR);

	}

}

void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)

{

	snb_update_pm_irq(dev_priv, mask, mask);

}

void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)

{

	snb_update_pm_irq(dev_priv, mask, 0);

}

static bool ivb_can_enable_err_int(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *crtc;

	enum pipe pipe;

	assert_spin_locked(&dev_priv->irq_lock);

	for_each_pipe(pipe) {

		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->cpu_fifo_underrun_disabled)

			return false;

	}

	return true;

}

static bool cpt_can_enable_serr_int(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	enum pipe pipe;

	struct intel_crtc *crtc;

	assert_spin_locked(&dev_priv->irq_lock);

	for_each_pipe(pipe) {

		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->pch_fifo_underrun_disabled)

			return false;

	}

	return true;

}

static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,

						 enum pipe pipe, bool enable)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :

					  DE_PIPEB_FIFO_UNDERRUN;

	if (enable)