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Rev | Author | Line No. | Line |
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6084 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | */ |
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24 | #include |
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25 | #include |
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6937 | serge | 26 | #include "i915_drv.h" |
6084 | serge | 27 | #include "intel_guc.h" |
28 | |||
29 | /** |
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6937 | serge | 30 | * DOC: GuC-based command submission |
6084 | serge | 31 | * |
32 | * i915_guc_client: |
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33 | * We use the term client to avoid confusion with contexts. A i915_guc_client is |
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34 | * equivalent to GuC object guc_context_desc. This context descriptor is |
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35 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell |
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36 | * and workqueue for it. Also the process descriptor (guc_process_desc), which |
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37 | * is mapped to client space. So the client can write Work Item then ring the |
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38 | * doorbell. |
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39 | * |
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40 | * To simplify the implementation, we allocate one gem object that contains all |
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41 | * pages for doorbell, process descriptor and workqueue. |
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42 | * |
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43 | * The Scratch registers: |
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44 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes |
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45 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then |
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46 | * triggers an interrupt on the GuC via another register write (0xC4C8). |
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47 | * Firmware writes a success/fail code back to the action register after |
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48 | * processes the request. The kernel driver polls waiting for this update and |
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49 | * then proceeds. |
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50 | * See host2guc_action() |
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51 | * |
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52 | * Doorbells: |
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53 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) |
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54 | * mapped into process space. |
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55 | * |
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56 | * Work Items: |
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57 | * There are several types of work items that the host may place into a |
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58 | * workqueue, each with its own requirements and limitations. Currently only |
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59 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which |
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60 | * represents in-order queue. The kernel driver packs ring tail pointer and an |
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61 | * ELSP context descriptor dword into Work Item. |
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62 | * See guc_add_workqueue_item() |
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63 | * |
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64 | */ |
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65 | |||
66 | /* |
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67 | * Read GuC command/status register (SOFT_SCRATCH_0) |
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68 | * Return true if it contains a response rather than a command |
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69 | */ |
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70 | static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, |
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71 | u32 *status) |
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72 | { |
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73 | u32 val = I915_READ(SOFT_SCRATCH(0)); |
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74 | *status = val; |
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75 | return GUC2HOST_IS_RESPONSE(val); |
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76 | } |
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77 | |||
78 | static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) |
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79 | { |
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80 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
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81 | u32 status; |
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82 | int i; |
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83 | int ret; |
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84 | |||
85 | if (WARN_ON(len < 1 || len > 15)) |
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86 | return -EINVAL; |
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87 | |||
88 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
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89 | |||
90 | dev_priv->guc.action_count += 1; |
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91 | dev_priv->guc.action_cmd = data[0]; |
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92 | |||
93 | for (i = 0; i < len; i++) |
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94 | I915_WRITE(SOFT_SCRATCH(i), data[i]); |
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95 | |||
96 | POSTING_READ(SOFT_SCRATCH(i - 1)); |
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97 | |||
98 | I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); |
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99 | |||
100 | /* No HOST2GUC command should take longer than 10ms */ |
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101 | ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10); |
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102 | if (status != GUC2HOST_STATUS_SUCCESS) { |
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103 | /* |
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104 | * Either the GuC explicitly returned an error (which |
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105 | * we convert to -EIO here) or no response at all was |
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106 | * received within the timeout limit (-ETIMEDOUT) |
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107 | */ |
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108 | if (ret != -ETIMEDOUT) |
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109 | ret = -EIO; |
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110 | |||
111 | DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d " |
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112 | "status=0x%08X response=0x%08X\n", |
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113 | data[0], ret, status, |
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114 | I915_READ(SOFT_SCRATCH(15))); |
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115 | |||
116 | dev_priv->guc.action_fail += 1; |
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117 | dev_priv->guc.action_err = ret; |
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118 | } |
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119 | dev_priv->guc.action_status = status; |
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120 | |||
121 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
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122 | |||
123 | return ret; |
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124 | } |
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125 | |||
126 | /* |
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127 | * Tell the GuC to allocate or deallocate a specific doorbell |
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128 | */ |
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129 | |||
130 | static int host2guc_allocate_doorbell(struct intel_guc *guc, |
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131 | struct i915_guc_client *client) |
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132 | { |
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133 | u32 data[2]; |
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134 | |||
135 | data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; |
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136 | data[1] = client->ctx_index; |
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137 | |||
138 | return host2guc_action(guc, data, 2); |
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139 | } |
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140 | |||
141 | static int host2guc_release_doorbell(struct intel_guc *guc, |
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142 | struct i915_guc_client *client) |
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143 | { |
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144 | u32 data[2]; |
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145 | |||
146 | data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; |
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147 | data[1] = client->ctx_index; |
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148 | |||
149 | return host2guc_action(guc, data, 2); |
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150 | } |
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151 | |||
152 | static int host2guc_sample_forcewake(struct intel_guc *guc, |
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153 | struct i915_guc_client *client) |
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154 | { |
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155 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
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156 | struct drm_device *dev = dev_priv->dev; |
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157 | u32 data[2]; |
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158 | |||
159 | data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; |
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160 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
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7144 | serge | 161 | if (!intel_enable_rc6(dev) || |
162 | NEEDS_WaRsDisableCoarsePowerGating(dev)) |
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6084 | serge | 163 | data[1] = 0; |
164 | else |
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165 | /* bit 0 and 1 are for Render and Media domain separately */ |
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166 | data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; |
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167 | |||
168 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
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169 | } |
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170 | |||
171 | /* |
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172 | * Initialise, update, or clear doorbell data shared with the GuC |
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173 | * |
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174 | * These functions modify shared data and so need access to the mapped |
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175 | * client object which contains the page being used for the doorbell |
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176 | */ |
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177 | |||
178 | static void guc_init_doorbell(struct intel_guc *guc, |
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179 | struct i915_guc_client *client) |
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180 | { |
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181 | struct guc_doorbell_info *doorbell; |
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182 | void *base; |
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183 | |||
184 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
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185 | doorbell = base + client->doorbell_offset; |
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186 | |||
187 | doorbell->db_status = 1; |
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188 | doorbell->cookie = 0; |
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189 | |||
190 | kunmap_atomic(base); |
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191 | } |
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192 | |||
193 | static int guc_ring_doorbell(struct i915_guc_client *gc) |
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194 | { |
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195 | struct guc_process_desc *desc; |
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196 | union guc_doorbell_qw db_cmp, db_exc, db_ret; |
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197 | union guc_doorbell_qw *db; |
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198 | void *base; |
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199 | int attempt = 2, ret = -EAGAIN; |
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200 | |||
201 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); |
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202 | desc = base + gc->proc_desc_offset; |
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203 | |||
204 | /* Update the tail so it is visible to GuC */ |
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205 | desc->tail = gc->wq_tail; |
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206 | |||
207 | /* current cookie */ |
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208 | db_cmp.db_status = GUC_DOORBELL_ENABLED; |
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209 | db_cmp.cookie = gc->cookie; |
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210 | |||
211 | /* cookie to be updated */ |
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212 | db_exc.db_status = GUC_DOORBELL_ENABLED; |
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213 | db_exc.cookie = gc->cookie + 1; |
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214 | if (db_exc.cookie == 0) |
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215 | db_exc.cookie = 1; |
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216 | |||
217 | /* pointer of current doorbell cacheline */ |
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218 | db = base + gc->doorbell_offset; |
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219 | |||
220 | while (attempt--) { |
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221 | /* lets ring the doorbell */ |
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222 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, |
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223 | db_cmp.value_qw, db_exc.value_qw); |
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224 | |||
225 | /* if the exchange was successfully executed */ |
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226 | if (db_ret.value_qw == db_cmp.value_qw) { |
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227 | /* db was successfully rung */ |
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228 | gc->cookie = db_exc.cookie; |
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229 | ret = 0; |
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230 | break; |
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231 | } |
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232 | |||
233 | /* XXX: doorbell was lost and need to acquire it again */ |
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234 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) |
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235 | break; |
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236 | |||
237 | DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n", |
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238 | db_cmp.cookie, db_ret.cookie); |
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239 | |||
240 | /* update the cookie to newly read cookie from GuC */ |
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241 | db_cmp.cookie = db_ret.cookie; |
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242 | db_exc.cookie = db_ret.cookie + 1; |
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243 | if (db_exc.cookie == 0) |
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244 | db_exc.cookie = 1; |
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245 | } |
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246 | |||
7144 | serge | 247 | /* Finally, update the cached copy of the GuC's WQ head */ |
248 | gc->wq_head = desc->head; |
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249 | |||
6084 | serge | 250 | kunmap_atomic(base); |
251 | return ret; |
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252 | } |
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253 | |||
254 | static void guc_disable_doorbell(struct intel_guc *guc, |
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255 | struct i915_guc_client *client) |
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256 | { |
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257 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
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258 | struct guc_doorbell_info *doorbell; |
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259 | void *base; |
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6937 | serge | 260 | i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id); |
6084 | serge | 261 | int value; |
262 | |||
263 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
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264 | doorbell = base + client->doorbell_offset; |
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265 | |||
266 | doorbell->db_status = 0; |
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267 | |||
268 | kunmap_atomic(base); |
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269 | |||
270 | I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID); |
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271 | |||
272 | value = I915_READ(drbreg); |
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273 | WARN_ON((value & GEN8_DRB_VALID) != 0); |
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274 | |||
275 | I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0); |
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276 | I915_WRITE(drbreg, 0); |
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277 | |||
278 | /* XXX: wait for any interrupts */ |
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279 | /* XXX: wait for workqueue to drain */ |
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280 | } |
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281 | |||
282 | /* |
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283 | * Select, assign and relase doorbell cachelines |
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284 | * |
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285 | * These functions track which doorbell cachelines are in use. |
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286 | * The data they manipulate is protected by the host2guc lock. |
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287 | */ |
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288 | |||
289 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) |
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290 | { |
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291 | const uint32_t cacheline_size = cache_line_size(); |
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292 | uint32_t offset; |
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293 | |||
294 | /* Doorbell uses a single cache line within a page */ |
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295 | offset = offset_in_page(guc->db_cacheline); |
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296 | |||
297 | /* Moving to next cache line to reduce contention */ |
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298 | guc->db_cacheline += cacheline_size; |
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299 | |||
300 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
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301 | offset, guc->db_cacheline, cacheline_size); |
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302 | |||
303 | return offset; |
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304 | } |
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305 | |||
306 | static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority) |
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307 | { |
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308 | /* |
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309 | * The bitmap is split into two halves; the first half is used for |
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310 | * normal priority contexts, the second half for high-priority ones. |
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311 | * Note that logically higher priorities are numerically less than |
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312 | * normal ones, so the test below means "is it high-priority?" |
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313 | */ |
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314 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); |
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315 | const uint16_t half = GUC_MAX_DOORBELLS / 2; |
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316 | const uint16_t start = hi_pri ? half : 0; |
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317 | const uint16_t end = start + half; |
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318 | uint16_t id; |
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319 | |||
320 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); |
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321 | if (id == end) |
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322 | id = GUC_INVALID_DOORBELL_ID; |
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323 | else |
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324 | bitmap_set(guc->doorbell_bitmap, id, 1); |
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325 | |||
326 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", |
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327 | hi_pri ? "high" : "normal", id); |
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328 | |||
329 | return id; |
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330 | } |
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331 | |||
332 | static void release_doorbell(struct intel_guc *guc, uint16_t id) |
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333 | { |
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334 | bitmap_clear(guc->doorbell_bitmap, id, 1); |
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335 | } |
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336 | |||
337 | /* |
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338 | * Initialise the process descriptor shared with the GuC firmware. |
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339 | */ |
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340 | static void guc_init_proc_desc(struct intel_guc *guc, |
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341 | struct i915_guc_client *client) |
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342 | { |
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343 | struct guc_process_desc *desc; |
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344 | void *base; |
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345 | |||
346 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
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347 | desc = base + client->proc_desc_offset; |
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348 | |||
349 | memset(desc, 0, sizeof(*desc)); |
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350 | |||
351 | /* |
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352 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address |
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353 | * space for ring3 clients (set them as in mmap_ioctl) or kernel |
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354 | * space for kernel clients (map on demand instead? May make debug |
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355 | * easier to have it mapped). |
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356 | */ |
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357 | desc->wq_base_addr = 0; |
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358 | desc->db_base_addr = 0; |
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359 | |||
360 | desc->context_id = client->ctx_index; |
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361 | desc->wq_size_bytes = client->wq_size; |
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362 | desc->wq_status = WQ_STATUS_ACTIVE; |
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363 | desc->priority = client->priority; |
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364 | |||
365 | kunmap_atomic(base); |
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366 | } |
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367 | |||
368 | /* |
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369 | * Initialise/clear the context descriptor shared with the GuC firmware. |
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370 | * |
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371 | * This descriptor tells the GuC where (in GGTT space) to find the important |
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372 | * data structures relating to this client (doorbell, process descriptor, |
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373 | * write queue, etc). |
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374 | */ |
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375 | |||
376 | static void guc_init_ctx_desc(struct intel_guc *guc, |
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377 | struct i915_guc_client *client) |
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378 | { |
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7144 | serge | 379 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
380 | struct intel_engine_cs *ring; |
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6084 | serge | 381 | struct intel_context *ctx = client->owner; |
382 | struct guc_context_desc desc; |
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383 | struct sg_table *sg; |
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384 | int i; |
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385 | |||
386 | memset(&desc, 0, sizeof(desc)); |
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387 | |||
388 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; |
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389 | desc.context_id = client->ctx_index; |
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390 | desc.priority = client->priority; |
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391 | desc.db_id = client->doorbell_id; |
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392 | |||
7144 | serge | 393 | for_each_ring(ring, dev_priv, i) { |
394 | struct guc_execlist_context *lrc = &desc.lrc[ring->guc_id]; |
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6084 | serge | 395 | struct drm_i915_gem_object *obj; |
396 | uint64_t ctx_desc; |
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397 | |||
398 | /* TODO: We have a design issue to be solved here. Only when we |
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399 | * receive the first batch, we know which engine is used by the |
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400 | * user. But here GuC expects the lrc and ring to be pinned. It |
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401 | * is not an issue for default context, which is the only one |
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402 | * for now who owns a GuC client. But for future owner of GuC |
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403 | * client, need to make sure lrc is pinned prior to enter here. |
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404 | */ |
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405 | obj = ctx->engine[i].state; |
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406 | if (!obj) |
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407 | break; /* XXX: continue? */ |
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408 | |||
409 | ctx_desc = intel_lr_context_descriptor(ctx, ring); |
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410 | lrc->context_desc = (u32)ctx_desc; |
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411 | |||
412 | /* The state page is after PPHWSP */ |
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413 | lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) + |
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414 | LRC_STATE_PN * PAGE_SIZE; |
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415 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | |
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7144 | serge | 416 | (ring->guc_id << GUC_ELC_ENGINE_OFFSET); |
6084 | serge | 417 | |
7144 | serge | 418 | obj = ctx->engine[i].ringbuf->obj; |
6084 | serge | 419 | |
420 | lrc->ring_begin = i915_gem_obj_ggtt_offset(obj); |
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421 | lrc->ring_end = lrc->ring_begin + obj->base.size - 1; |
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422 | lrc->ring_next_free_location = lrc->ring_begin; |
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423 | lrc->ring_current_tail_pointer_value = 0; |
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424 | |||
7144 | serge | 425 | desc.engines_used |= (1 << ring->guc_id); |
6084 | serge | 426 | } |
427 | |||
428 | WARN_ON(desc.engines_used == 0); |
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429 | |||
430 | /* |
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431 | * The CPU address is only needed at certain points, so kmap_atomic on |
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432 | * demand instead of storing it in the ctx descriptor. |
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433 | * XXX: May make debug easier to have it mapped |
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434 | */ |
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435 | desc.db_trigger_cpu = 0; |
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436 | desc.db_trigger_uk = client->doorbell_offset + |
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437 | i915_gem_obj_ggtt_offset(client->client_obj); |
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438 | desc.db_trigger_phy = client->doorbell_offset + |
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439 | sg_dma_address(client->client_obj->pages->sgl); |
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440 | |||
441 | desc.process_desc = client->proc_desc_offset + |
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442 | i915_gem_obj_ggtt_offset(client->client_obj); |
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443 | |||
444 | desc.wq_addr = client->wq_offset + |
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445 | i915_gem_obj_ggtt_offset(client->client_obj); |
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446 | |||
447 | desc.wq_size = client->wq_size; |
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448 | |||
449 | /* |
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450 | * XXX: Take LRCs from an existing intel_context if this is not an |
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451 | * IsKMDCreatedContext client |
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452 | */ |
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453 | desc.desc_private = (uintptr_t)client; |
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454 | |||
455 | /* Pool context is pinned already */ |
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456 | sg = guc->ctx_pool_obj->pages; |
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457 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
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458 | sizeof(desc) * client->ctx_index); |
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459 | } |
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460 | |||
461 | static void guc_fini_ctx_desc(struct intel_guc *guc, |
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462 | struct i915_guc_client *client) |
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463 | { |
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464 | struct guc_context_desc desc; |
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465 | struct sg_table *sg; |
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466 | |||
467 | memset(&desc, 0, sizeof(desc)); |
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468 | |||
469 | sg = guc->ctx_pool_obj->pages; |
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470 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
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471 | sizeof(desc) * client->ctx_index); |
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472 | } |
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473 | |||
7144 | serge | 474 | int i915_guc_wq_check_space(struct i915_guc_client *gc) |
6084 | serge | 475 | { |
476 | struct guc_process_desc *desc; |
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477 | void *base; |
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478 | u32 size = sizeof(struct guc_wq_item); |
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6937 | serge | 479 | int ret = -ETIMEDOUT, timeout_counter = 200; |
6084 | serge | 480 | |
7144 | serge | 481 | if (!gc) |
482 | return 0; |
||
483 | |||
484 | /* Quickly return if wq space is available since last time we cache the |
||
485 | * head position. */ |
||
486 | if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) |
||
487 | return 0; |
||
488 | |||
6084 | serge | 489 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); |
490 | desc = base + gc->proc_desc_offset; |
||
491 | |||
492 | while (timeout_counter-- > 0) { |
||
7144 | serge | 493 | gc->wq_head = desc->head; |
6084 | serge | 494 | |
7144 | serge | 495 | if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) { |
6937 | serge | 496 | ret = 0; |
7144 | serge | 497 | break; |
6084 | serge | 498 | } |
6937 | serge | 499 | |
500 | if (timeout_counter) |
||
501 | usleep_range(1000, 2000); |
||
6084 | serge | 502 | }; |
503 | |||
504 | kunmap_atomic(base); |
||
505 | |||
506 | return ret; |
||
507 | } |
||
508 | |||
509 | static int guc_add_workqueue_item(struct i915_guc_client *gc, |
||
510 | struct drm_i915_gem_request *rq) |
||
511 | { |
||
512 | struct guc_wq_item *wqi; |
||
513 | void *base; |
||
7144 | serge | 514 | u32 tail, wq_len, wq_off, space; |
6084 | serge | 515 | |
7144 | serge | 516 | space = CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size); |
517 | if (WARN_ON(space < sizeof(struct guc_wq_item))) |
||
518 | return -ENOSPC; /* shouldn't happen */ |
||
6084 | serge | 519 | |
7144 | serge | 520 | /* postincrement WQ tail for next time */ |
521 | wq_off = gc->wq_tail; |
||
522 | gc->wq_tail += sizeof(struct guc_wq_item); |
||
523 | gc->wq_tail &= gc->wq_size - 1; |
||
524 | |||
6084 | serge | 525 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we |
526 | * should not have the case where structure wqi is across page, neither |
||
527 | * wrapped to the beginning. This simplifies the implementation below. |
||
528 | * |
||
529 | * XXX: if not the case, we need save data to a temp wqi and copy it to |
||
530 | * workqueue buffer dw by dw. |
||
531 | */ |
||
532 | WARN_ON(sizeof(struct guc_wq_item) != 16); |
||
533 | WARN_ON(wq_off & 3); |
||
534 | |||
535 | /* wq starts from the page after doorbell / process_desc */ |
||
536 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, |
||
537 | (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT)); |
||
538 | wq_off &= PAGE_SIZE - 1; |
||
539 | wqi = (struct guc_wq_item *)((char *)base + wq_off); |
||
540 | |||
541 | /* len does not include the header */ |
||
542 | wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1; |
||
543 | wqi->header = WQ_TYPE_INORDER | |
||
544 | (wq_len << WQ_LEN_SHIFT) | |
||
7144 | serge | 545 | (rq->ring->guc_id << WQ_TARGET_SHIFT) | |
6084 | serge | 546 | WQ_NO_WCFLUSH_WAIT; |
547 | |||
548 | /* The GuC wants only the low-order word of the context descriptor */ |
||
549 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring); |
||
550 | |||
551 | /* The GuC firmware wants the tail index in QWords, not bytes */ |
||
552 | tail = rq->ringbuf->tail >> 3; |
||
553 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; |
||
554 | wqi->fence_id = 0; /*XXX: what fence to be here */ |
||
555 | |||
556 | kunmap_atomic(base); |
||
557 | |||
558 | return 0; |
||
559 | } |
||
560 | |||
561 | /** |
||
562 | * i915_guc_submit() - Submit commands through GuC |
||
563 | * @client: the guc client where commands will go through |
||
6937 | serge | 564 | * @rq: request associated with the commands |
6084 | serge | 565 | * |
566 | * Return: 0 if succeed |
||
567 | */ |
||
568 | int i915_guc_submit(struct i915_guc_client *client, |
||
569 | struct drm_i915_gem_request *rq) |
||
570 | { |
||
571 | struct intel_guc *guc = client->guc; |
||
7144 | serge | 572 | unsigned int engine_id = rq->ring->guc_id; |
6084 | serge | 573 | int q_ret, b_ret; |
574 | |||
575 | q_ret = guc_add_workqueue_item(client, rq); |
||
576 | if (q_ret == 0) |
||
577 | b_ret = guc_ring_doorbell(client); |
||
578 | |||
7144 | serge | 579 | client->submissions[engine_id] += 1; |
6084 | serge | 580 | if (q_ret) { |
581 | client->q_fail += 1; |
||
582 | client->retcode = q_ret; |
||
583 | } else if (b_ret) { |
||
584 | client->b_fail += 1; |
||
585 | client->retcode = q_ret = b_ret; |
||
586 | } else { |
||
587 | client->retcode = 0; |
||
588 | } |
||
7144 | serge | 589 | guc->submissions[engine_id] += 1; |
590 | guc->last_seqno[engine_id] = rq->seqno; |
||
6084 | serge | 591 | |
592 | return q_ret; |
||
593 | } |
||
594 | |||
595 | /* |
||
596 | * Everything below here is concerned with setup & teardown, and is |
||
597 | * therefore not part of the somewhat time-critical batch-submission |
||
598 | * path of i915_guc_submit() above. |
||
599 | */ |
||
600 | |||
601 | /** |
||
602 | * gem_allocate_guc_obj() - Allocate gem object for GuC usage |
||
603 | * @dev: drm device |
||
604 | * @size: size of object |
||
605 | * |
||
606 | * This is a wrapper to create a gem obj. In order to use it inside GuC, the |
||
607 | * object needs to be pinned lifetime. Also we must pin it to gtt space other |
||
608 | * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC. |
||
609 | * |
||
610 | * Return: A drm_i915_gem_object if successful, otherwise NULL. |
||
611 | */ |
||
612 | static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev, |
||
613 | u32 size) |
||
614 | { |
||
615 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
616 | struct drm_i915_gem_object *obj; |
||
617 | |||
618 | obj = i915_gem_alloc_object(dev, size); |
||
619 | if (!obj) |
||
620 | return NULL; |
||
621 | |||
622 | if (i915_gem_object_get_pages(obj)) { |
||
623 | drm_gem_object_unreference(&obj->base); |
||
624 | return NULL; |
||
625 | } |
||
626 | |||
627 | if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
||
628 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { |
||
629 | drm_gem_object_unreference(&obj->base); |
||
630 | return NULL; |
||
631 | } |
||
632 | |||
633 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ |
||
634 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
||
635 | |||
636 | return obj; |
||
637 | } |
||
638 | |||
639 | /** |
||
640 | * gem_release_guc_obj() - Release gem object allocated for GuC usage |
||
641 | * @obj: gem obj to be released |
||
7144 | serge | 642 | */ |
6084 | serge | 643 | static void gem_release_guc_obj(struct drm_i915_gem_object *obj) |
644 | { |
||
645 | if (!obj) |
||
646 | return; |
||
647 | |||
648 | if (i915_gem_obj_is_pinned(obj)) |
||
649 | i915_gem_object_ggtt_unpin(obj); |
||
650 | |||
651 | drm_gem_object_unreference(&obj->base); |
||
652 | } |
||
653 | |||
654 | static void guc_client_free(struct drm_device *dev, |
||
655 | struct i915_guc_client *client) |
||
656 | { |
||
657 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
658 | struct intel_guc *guc = &dev_priv->guc; |
||
659 | |||
660 | if (!client) |
||
661 | return; |
||
662 | |||
663 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) { |
||
664 | /* |
||
665 | * First disable the doorbell, then tell the GuC we've |
||
666 | * finished with it, finally deallocate it in our bitmap |
||
667 | */ |
||
668 | guc_disable_doorbell(guc, client); |
||
669 | host2guc_release_doorbell(guc, client); |
||
670 | release_doorbell(guc, client->doorbell_id); |
||
671 | } |
||
672 | |||
673 | /* |
||
674 | * XXX: wait for any outstanding submissions before freeing memory. |
||
675 | * Be sure to drop any locks |
||
676 | */ |
||
677 | |||
678 | gem_release_guc_obj(client->client_obj); |
||
679 | |||
680 | if (client->ctx_index != GUC_INVALID_CTX_ID) { |
||
681 | guc_fini_ctx_desc(guc, client); |
||
682 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); |
||
683 | } |
||
684 | |||
685 | kfree(client); |
||
686 | } |
||
687 | |||
688 | /** |
||
689 | * guc_client_alloc() - Allocate an i915_guc_client |
||
690 | * @dev: drm device |
||
691 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW |
||
692 | * The kernel client to replace ExecList submission is created with |
||
693 | * NORMAL priority. Priority of a client for scheduler can be HIGH, |
||
694 | * while a preemption context can use CRITICAL. |
||
6937 | serge | 695 | * @ctx: the context that owns the client (we use the default render |
696 | * context) |
||
6084 | serge | 697 | * |
698 | * Return: An i915_guc_client object if success. |
||
699 | */ |
||
700 | static struct i915_guc_client *guc_client_alloc(struct drm_device *dev, |
||
701 | uint32_t priority, |
||
702 | struct intel_context *ctx) |
||
703 | { |
||
704 | struct i915_guc_client *client; |
||
705 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
706 | struct intel_guc *guc = &dev_priv->guc; |
||
707 | struct drm_i915_gem_object *obj; |
||
708 | |||
709 | client = kzalloc(sizeof(*client), GFP_KERNEL); |
||
710 | if (!client) |
||
711 | return NULL; |
||
712 | |||
713 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; |
||
714 | client->priority = priority; |
||
715 | client->owner = ctx; |
||
716 | client->guc = guc; |
||
717 | |||
718 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, |
||
719 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); |
||
720 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { |
||
721 | client->ctx_index = GUC_INVALID_CTX_ID; |
||
722 | goto err; |
||
723 | } |
||
724 | |||
725 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ |
||
726 | obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE); |
||
727 | if (!obj) |
||
728 | goto err; |
||
729 | |||
730 | client->client_obj = obj; |
||
731 | client->wq_offset = GUC_DB_SIZE; |
||
732 | client->wq_size = GUC_WQ_SIZE; |
||
733 | |||
734 | client->doorbell_offset = select_doorbell_cacheline(guc); |
||
735 | |||
736 | /* |
||
737 | * Since the doorbell only requires a single cacheline, we can save |
||
738 | * space by putting the application process descriptor in the same |
||
739 | * page. Use the half of the page that doesn't include the doorbell. |
||
740 | */ |
||
741 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) |
||
742 | client->proc_desc_offset = 0; |
||
743 | else |
||
744 | client->proc_desc_offset = (GUC_DB_SIZE / 2); |
||
745 | |||
746 | client->doorbell_id = assign_doorbell(guc, client->priority); |
||
747 | if (client->doorbell_id == GUC_INVALID_DOORBELL_ID) |
||
748 | /* XXX: evict a doorbell instead */ |
||
749 | goto err; |
||
750 | |||
751 | guc_init_proc_desc(guc, client); |
||
752 | guc_init_ctx_desc(guc, client); |
||
753 | guc_init_doorbell(guc, client); |
||
754 | |||
755 | /* XXX: Any cache flushes needed? General domain mgmt calls? */ |
||
756 | |||
757 | if (host2guc_allocate_doorbell(guc, client)) |
||
758 | goto err; |
||
759 | |||
760 | DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n", |
||
761 | priority, client, client->ctx_index, client->doorbell_id); |
||
762 | |||
763 | return client; |
||
764 | |||
765 | err: |
||
766 | DRM_ERROR("FAILED to create priority %u GuC client!\n", priority); |
||
767 | |||
768 | guc_client_free(dev, client); |
||
769 | return NULL; |
||
770 | } |
||
771 | |||
772 | static void guc_create_log(struct intel_guc *guc) |
||
773 | { |
||
774 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
||
775 | struct drm_i915_gem_object *obj; |
||
776 | unsigned long offset; |
||
777 | uint32_t size, flags; |
||
778 | |||
779 | if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN) |
||
780 | return; |
||
781 | |||
782 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) |
||
783 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; |
||
784 | |||
785 | /* The first page is to save log buffer state. Allocate one |
||
786 | * extra page for others in case for overlap */ |
||
787 | size = (1 + GUC_LOG_DPC_PAGES + 1 + |
||
788 | GUC_LOG_ISR_PAGES + 1 + |
||
789 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; |
||
790 | |||
791 | obj = guc->log_obj; |
||
792 | if (!obj) { |
||
793 | obj = gem_allocate_guc_obj(dev_priv->dev, size); |
||
794 | if (!obj) { |
||
795 | /* logging will be off */ |
||
796 | i915.guc_log_level = -1; |
||
797 | return; |
||
798 | } |
||
799 | |||
800 | guc->log_obj = obj; |
||
801 | } |
||
802 | |||
803 | /* each allocated unit is a page */ |
||
804 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | |
||
805 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | |
||
806 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | |
||
807 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); |
||
808 | |||
809 | offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */ |
||
810 | guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; |
||
811 | } |
||
812 | |||
7144 | serge | 813 | static void init_guc_policies(struct guc_policies *policies) |
814 | { |
||
815 | struct guc_policy *policy; |
||
816 | u32 p, i; |
||
817 | |||
818 | policies->dpc_promote_time = 500000; |
||
819 | policies->max_num_work_items = POLICY_MAX_NUM_WI; |
||
820 | |||
821 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { |
||
822 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
||
823 | policy = &policies->policy[p][i]; |
||
824 | |||
825 | policy->execution_quantum = 1000000; |
||
826 | policy->preemption_time = 500000; |
||
827 | policy->fault_time = 250000; |
||
828 | policy->policy_flags = 0; |
||
829 | } |
||
830 | } |
||
831 | |||
832 | policies->is_valid = 1; |
||
833 | } |
||
834 | |||
835 | static void guc_create_ads(struct intel_guc *guc) |
||
836 | { |
||
837 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
||
838 | struct drm_i915_gem_object *obj; |
||
839 | struct guc_ads *ads; |
||
840 | struct guc_policies *policies; |
||
841 | struct guc_mmio_reg_state *reg_state; |
||
842 | struct intel_engine_cs *ring; |
||
843 | struct page *page; |
||
844 | u32 size, i; |
||
845 | |||
846 | /* The ads obj includes the struct itself and buffers passed to GuC */ |
||
847 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
||
848 | sizeof(struct guc_mmio_reg_state) + |
||
849 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; |
||
850 | |||
851 | obj = guc->ads_obj; |
||
852 | if (!obj) { |
||
853 | obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size)); |
||
854 | if (!obj) |
||
855 | return; |
||
856 | |||
857 | guc->ads_obj = obj; |
||
858 | } |
||
859 | |||
860 | page = i915_gem_object_get_page(obj, 0); |
||
861 | ads = kmap(page); |
||
862 | |||
863 | /* |
||
864 | * The GuC requires a "Golden Context" when it reinitialises |
||
865 | * engines after a reset. Here we use the Render ring default |
||
866 | * context, which must already exist and be pinned in the GGTT, |
||
867 | * so its address won't change after we've told the GuC where |
||
868 | * to find it. |
||
869 | */ |
||
870 | ring = &dev_priv->ring[RCS]; |
||
871 | ads->golden_context_lrca = ring->status_page.gfx_addr; |
||
872 | |||
873 | for_each_ring(ring, dev_priv, i) |
||
874 | ads->eng_state_size[ring->guc_id] = intel_lr_context_size(ring); |
||
875 | |||
876 | /* GuC scheduling policies */ |
||
877 | policies = (void *)ads + sizeof(struct guc_ads); |
||
878 | init_guc_policies(policies); |
||
879 | |||
880 | ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) + |
||
881 | sizeof(struct guc_ads); |
||
882 | |||
883 | /* MMIO reg state */ |
||
884 | reg_state = (void *)policies + sizeof(struct guc_policies); |
||
885 | |||
886 | for_each_ring(ring, dev_priv, i) { |
||
887 | reg_state->mmio_white_list[ring->guc_id].mmio_start = |
||
888 | ring->mmio_base + GUC_MMIO_WHITE_LIST_START; |
||
889 | |||
890 | /* Nothing to be saved or restored for now. */ |
||
891 | reg_state->mmio_white_list[ring->guc_id].count = 0; |
||
892 | } |
||
893 | |||
894 | ads->reg_state_addr = ads->scheduler_policies + |
||
895 | sizeof(struct guc_policies); |
||
896 | |||
897 | ads->reg_state_buffer = ads->reg_state_addr + |
||
898 | sizeof(struct guc_mmio_reg_state); |
||
899 | |||
900 | kunmap(page); |
||
901 | } |
||
902 | |||
6084 | serge | 903 | /* |
904 | * Set up the memory resources to be shared with the GuC. At this point, |
||
905 | * we require just one object that can be mapped through the GGTT. |
||
906 | */ |
||
907 | int i915_guc_submission_init(struct drm_device *dev) |
||
908 | { |
||
909 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
910 | const size_t ctxsize = sizeof(struct guc_context_desc); |
||
911 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; |
||
912 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); |
||
913 | struct intel_guc *guc = &dev_priv->guc; |
||
914 | |||
915 | if (!i915.enable_guc_submission) |
||
916 | return 0; /* not enabled */ |
||
917 | |||
918 | if (guc->ctx_pool_obj) |
||
919 | return 0; /* already allocated */ |
||
920 | |||
921 | guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize); |
||
922 | if (!guc->ctx_pool_obj) |
||
923 | return -ENOMEM; |
||
924 | |||
925 | ida_init(&guc->ctx_ids); |
||
926 | |||
927 | guc_create_log(guc); |
||
928 | |||
7144 | serge | 929 | guc_create_ads(guc); |
930 | |||
6084 | serge | 931 | return 0; |
932 | } |
||
933 | |||
934 | int i915_guc_submission_enable(struct drm_device *dev) |
||
935 | { |
||
936 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
937 | struct intel_guc *guc = &dev_priv->guc; |
||
7144 | serge | 938 | struct intel_context *ctx = dev_priv->kernel_context; |
6084 | serge | 939 | struct i915_guc_client *client; |
940 | |||
941 | /* client for execbuf submission */ |
||
942 | client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx); |
||
943 | if (!client) { |
||
944 | DRM_ERROR("Failed to create execbuf guc_client\n"); |
||
945 | return -ENOMEM; |
||
946 | } |
||
947 | |||
948 | guc->execbuf_client = client; |
||
949 | |||
950 | host2guc_sample_forcewake(guc, client); |
||
951 | |||
952 | return 0; |
||
953 | } |
||
954 | |||
955 | void i915_guc_submission_disable(struct drm_device *dev) |
||
956 | { |
||
957 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
958 | struct intel_guc *guc = &dev_priv->guc; |
||
959 | |||
960 | guc_client_free(dev, guc->execbuf_client); |
||
961 | guc->execbuf_client = NULL; |
||
962 | } |
||
963 | |||
964 | void i915_guc_submission_fini(struct drm_device *dev) |
||
965 | { |
||
966 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
967 | struct intel_guc *guc = &dev_priv->guc; |
||
968 | |||
7144 | serge | 969 | gem_release_guc_obj(dev_priv->guc.ads_obj); |
970 | guc->ads_obj = NULL; |
||
971 | |||
6084 | serge | 972 | gem_release_guc_obj(dev_priv->guc.log_obj); |
973 | guc->log_obj = NULL; |
||
974 | |||
975 | if (guc->ctx_pool_obj) |
||
976 | ida_destroy(&guc->ctx_ids); |
||
977 | gem_release_guc_obj(guc->ctx_pool_obj); |
||
978 | guc->ctx_pool_obj = NULL; |
||
979 | } |
||
980 | |||
981 | /** |
||
982 | * intel_guc_suspend() - notify GuC entering suspend state |
||
983 | * @dev: drm device |
||
984 | */ |
||
985 | int intel_guc_suspend(struct drm_device *dev) |
||
986 | { |
||
987 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
988 | struct intel_guc *guc = &dev_priv->guc; |
||
989 | struct intel_context *ctx; |
||
990 | u32 data[3]; |
||
991 | |||
992 | if (!i915.enable_guc_submission) |
||
993 | return 0; |
||
994 | |||
7144 | serge | 995 | ctx = dev_priv->kernel_context; |
6084 | serge | 996 | |
997 | data[0] = HOST2GUC_ACTION_ENTER_S_STATE; |
||
998 | /* any value greater than GUC_POWER_D0 */ |
||
999 | data[1] = GUC_POWER_D1; |
||
1000 | /* first page is shared data with GuC */ |
||
1001 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); |
||
1002 | |||
1003 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
||
1004 | } |
||
1005 | |||
1006 | |||
1007 | /** |
||
1008 | * intel_guc_resume() - notify GuC resuming from suspend state |
||
1009 | * @dev: drm device |
||
1010 | */ |
||
1011 | int intel_guc_resume(struct drm_device *dev) |
||
1012 | { |
||
1013 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1014 | struct intel_guc *guc = &dev_priv->guc; |
||
1015 | struct intel_context *ctx; |
||
1016 | u32 data[3]; |
||
1017 | |||
1018 | if (!i915.enable_guc_submission) |
||
1019 | return 0; |
||
1020 | |||
7144 | serge | 1021 | ctx = dev_priv->kernel_context; |
6084 | serge | 1022 | |
1023 | data[0] = HOST2GUC_ACTION_EXIT_S_STATE; |
||
1024 | data[1] = GUC_POWER_D0; |
||
1025 | /* first page is shared data with GuC */ |
||
1026 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); |
||
1027 | |||
1028 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
||
1029 | }>>><>><>><>><>><>>><>><>><>>><>><>><>=>>> |