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6084 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | */ |
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24 | #ifndef _I915_GUC_REG_H_ |
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25 | #define _I915_GUC_REG_H_ |
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26 | |||
27 | /* Definitions of GuC H/W registers, bits, etc */ |
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28 | |||
6937 | serge | 29 | #define GUC_STATUS _MMIO(0xc000) |
6084 | serge | 30 | #define GS_BOOTROM_SHIFT 1 |
31 | #define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT) |
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32 | #define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT) |
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33 | #define GS_UKERNEL_SHIFT 8 |
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34 | #define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT) |
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35 | #define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT) |
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36 | #define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT) |
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37 | #define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT) |
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38 | #define GS_MIA_SHIFT 16 |
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39 | #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT) |
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40 | #define GS_MIA_CORE_STATE (1 << GS_MIA_SHIFT) |
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41 | |||
6937 | serge | 42 | #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) |
6084 | serge | 43 | |
6937 | serge | 44 | #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) |
45 | #define UOS_RSA_SCRATCH_MAX_COUNT 64 |
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46 | #define DMA_ADDR_0_LOW _MMIO(0xc300) |
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47 | #define DMA_ADDR_0_HIGH _MMIO(0xc304) |
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48 | #define DMA_ADDR_1_LOW _MMIO(0xc308) |
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49 | #define DMA_ADDR_1_HIGH _MMIO(0xc30c) |
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6084 | serge | 50 | #define DMA_ADDRESS_SPACE_WOPCM (7 << 16) |
51 | #define DMA_ADDRESS_SPACE_GTT (8 << 16) |
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6937 | serge | 52 | #define DMA_COPY_SIZE _MMIO(0xc310) |
53 | #define DMA_CTRL _MMIO(0xc314) |
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6084 | serge | 54 | #define UOS_MOVE (1<<4) |
55 | #define START_DMA (1<<0) |
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6937 | serge | 56 | #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340) |
6084 | serge | 57 | #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */ |
6937 | serge | 58 | #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4) |
6084 | serge | 59 | |
6937 | serge | 60 | #define GUC_WOPCM_SIZE _MMIO(0xc050) |
6084 | serge | 61 | #define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */ |
62 | |||
63 | /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */ |
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64 | #define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE) |
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65 | |||
6937 | serge | 66 | #define GEN8_GT_PM_CONFIG _MMIO(0x138140) |
67 | #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140) |
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68 | #define GEN9_GT_PM_CONFIG _MMIO(0x13816c) |
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6084 | serge | 69 | #define GT_DOORBELL_ENABLE (1<<0) |
70 | |||
6937 | serge | 71 | #define GEN8_GTCR _MMIO(0x4274) |
6084 | serge | 72 | #define GEN8_GTCR_INVALIDATE (1<<0) |
73 | |||
6937 | serge | 74 | #define GUC_ARAT_C6DIS _MMIO(0xA178) |
6084 | serge | 75 | |
6937 | serge | 76 | #define GUC_SHIM_CONTROL _MMIO(0xc064) |
6084 | serge | 77 | #define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0) |
78 | #define GUC_ENABLE_READ_CACHE_LOGIC (1<<1) |
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79 | #define GUC_ENABLE_MIA_CACHING (1<<2) |
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80 | #define GUC_GEN10_MSGCH_ENABLE (1<<4) |
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81 | #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9) |
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82 | #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10) |
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83 | #define GUC_ENABLE_MIA_CLOCK_GATING (1<<15) |
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84 | #define GUC_GEN10_SHIM_WC_ENABLE (1<<21) |
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85 | |||
86 | #define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES | \ |
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87 | GUC_ENABLE_READ_CACHE_LOGIC | \ |
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88 | GUC_ENABLE_MIA_CACHING | \ |
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89 | GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \ |
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90 | GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \ |
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91 | GUC_ENABLE_MIA_CLOCK_GATING) |
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92 | |||
6937 | serge | 93 | #define HOST2GUC_INTERRUPT _MMIO(0xc4c8) |
6084 | serge | 94 | #define HOST2GUC_TRIGGER (1<<0) |
95 | |||
96 | #define DRBMISC1 0x1984 |
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97 | #define DOORBELL_ENABLE (1<<0) |
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98 | |||
6937 | serge | 99 | #define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8) |
6084 | serge | 100 | #define GEN8_DRB_VALID (1<<0) |
6937 | serge | 101 | #define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) |
6084 | serge | 102 | |
6937 | serge | 103 | #define DE_GUCRMR _MMIO(0x44054) |
6084 | serge | 104 | |
6937 | serge | 105 | #define GUC_BCS_RCS_IER _MMIO(0xC550) |
106 | #define GUC_VCS2_VCS1_IER _MMIO(0xC554) |
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107 | #define GUC_WD_VECS_IER _MMIO(0xC558) |
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108 | #define GUC_PM_P24C_IER _MMIO(0xC55C) |
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6084 | serge | 109 | |
110 | #endif0) |