WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_gpu_error.c

Rev	Author	Line No.	Line
4126	Serge	1	/*
		2	* Copyright (c) 2008 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	* Keith Packard
		26	* Mika Kuoppala
		27	*
		28	*/
		29
7144	serge	30	#define UTS_RELEASE " 4.6.7 "
4126	Serge	31	#include "i915_drv.h"
		32
		33	static const char *ring_str(int ring)
		34	{
		35	switch (ring) {
		36	case RCS: return "render";
		37	case VCS: return "bsd";
		38	case BCS: return "blt";
		39	case VECS: return "vebox";
5060	serge	40	case VCS2: return "bsd2";
4126	Serge	41	default: return "";
		42	}
		43	}
		44
		45	static const char *pin_flag(int pinned)
		46	{
		47	if (pinned > 0)
		48	return " P";
		49	else if (pinned < 0)
		50	return " p";
		51	else
		52	return "";
		53	}
		54
		55	static const char *tiling_flag(int tiling)
		56	{
		57	switch (tiling) {
		58	default:
		59	case I915_TILING_NONE: return "";
		60	case I915_TILING_X: return " X";
		61	case I915_TILING_Y: return " Y";
		62	}
		63	}
		64
		65	static const char *dirty_flag(int dirty)
		66	{
		67	return dirty ? " dirty" : "";
		68	}
		69
		70	static const char *purgeable_flag(int purgeable)
		71	{
		72	return purgeable ? " purgeable" : "";
		73	}
		74
		75	static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
		76	{
		77
		78	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		79	e->err = -ENOSPC;
		80	return false;
		81	}
		82
		83	if (e->bytes == e->size - 1 \|\| e->err)
		84	return false;
		85
		86	return true;
		87	}
		88
		89	static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
		90	unsigned len)
		91	{
		92	if (e->pos + len <= e->start) {
		93	e->pos += len;
		94	return false;
		95	}
		96
		97	/* First vsnprintf needs to fit in its entirety for memmove */
		98	if (len >= e->size) {
		99	e->err = -EIO;
		100	return false;
		101	}
		102
		103	return true;
		104	}
		105
		106	static void __i915_error_advance(struct drm_i915_error_state_buf *e,
		107	unsigned len)
		108	{
		109	/* If this is first printf in this window, adjust it so that
		110	* start position matches start of the buffer
		111	*/
		112
		113	if (e->pos < e->start) {
		114	const size_t off = e->start - e->pos;
		115
		116	/* Should not happen but be paranoid */
		117	if (off > len \|\| e->bytes) {
		118	e->err = -EIO;
		119	return;
		120	}
		121
		122	memmove(e->buf, e->buf + off, len - off);
		123	e->bytes = len - off;
		124	e->pos = e->start;
		125	return;
		126	}
		127
		128	e->bytes += len;
		129	e->pos += len;
		130	}
		131
		132	static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
		133	const char *f, va_list args)
		134	{
		135	unsigned len;
		136
		137	if (!__i915_error_ok(e))
		138	return;
		139
		140	/* Seek the first printf which is hits start position */
		141	if (e->pos < e->start) {
		142	va_list tmp;
		143
		144	va_copy(tmp, args);
5060	serge	145	len = vsnprintf(NULL, 0, f, tmp);
		146	va_end(tmp);
		147
		148	if (!__i915_error_seek(e, len))
4126	Serge	149	return;
		150	}
		151
		152	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
		153	if (len >= e->size - e->bytes)
		154	len = e->size - e->bytes - 1;
		155
		156	__i915_error_advance(e, len);
		157	}
		158
		159	static void i915_error_puts(struct drm_i915_error_state_buf *e,
		160	const char *str)
		161	{
		162	unsigned len;
		163
		164	if (!__i915_error_ok(e))
		165	return;
		166
		167	len = strlen(str);
		168
		169	/* Seek the first printf which is hits start position */
		170	if (e->pos < e->start) {
		171	if (!__i915_error_seek(e, len))
		172	return;
		173	}
		174
		175	if (len >= e->size - e->bytes)
		176	len = e->size - e->bytes - 1;
		177	memcpy(e->buf + e->bytes, str, len);
		178
		179	__i915_error_advance(e, len);
		180	}
		181
		182	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		183	#define err_puts(e, s) i915_error_puts(e, s)
		184
		185	static void print_error_buffers(struct drm_i915_error_state_buf *m,
		186	const char *name,
		187	struct drm_i915_error_buffer *err,
		188	int count)
		189	{
6084	serge	190	int i;
		191
5354	serge	192	err_printf(m, " %s [%d]:\n", name, count);
4126	Serge	193
		194	while (count--) {
6084	serge	195	err_printf(m, " %08x_%08x %8u %02x %02x [ ",
		196	upper_32_bits(err->gtt_offset),
		197	lower_32_bits(err->gtt_offset),
4126	Serge	198	err->size,
		199	err->read_domains,
6084	serge	200	err->write_domain);
		201	for (i = 0; i < I915_NUM_RINGS; i++)
		202	err_printf(m, "%02x ", err->rseqno[i]);
		203
		204	err_printf(m, "] %02x", err->wseqno);
4126	Serge	205	err_puts(m, pin_flag(err->pinned));
		206	err_puts(m, tiling_flag(err->tiling));
		207	err_puts(m, dirty_flag(err->dirty));
		208	err_puts(m, purgeable_flag(err->purgeable));
5060	serge	209	err_puts(m, err->userptr ? " userptr" : "");
4126	Serge	210	err_puts(m, err->ring != -1 ? " " : "");
		211	err_puts(m, ring_str(err->ring));
5354	serge	212	err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
4126	Serge	213
		214	if (err->name)
		215	err_printf(m, " (name: %d)", err->name);
		216	if (err->fence_reg != I915_FENCE_REG_NONE)
		217	err_printf(m, " (fence: %d)", err->fence_reg);
		218
		219	err_puts(m, "\n");
		220	err++;
		221	}
		222	}
		223
4560	Serge	224	static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
		225	{
		226	switch (a) {
		227	case HANGCHECK_IDLE:
		228	return "idle";
		229	case HANGCHECK_WAIT:
		230	return "wait";
		231	case HANGCHECK_ACTIVE:
		232	return "active";
5354	serge	233	case HANGCHECK_ACTIVE_LOOP:
		234	return "active (loop)";
4560	Serge	235	case HANGCHECK_KICK:
		236	return "kick";
		237	case HANGCHECK_HUNG:
		238	return "hung";
		239	}
		240
		241	return "unknown";
		242	}
		243
4126	Serge	244	static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
		245	struct drm_device *dev,
6084	serge	246	struct drm_i915_error_state *error,
		247	int ring_idx)
4126	Serge	248	{
6084	serge	249	struct drm_i915_error_ring *ring = &error->ring[ring_idx];
		250
5060	serge	251	if (!ring->valid)
4560	Serge	252	return;
		253
6084	serge	254	err_printf(m, "%s command stream:\n", ring_str(ring_idx));
		255	err_printf(m, " START: 0x%08x\n", ring->start);
		256	err_printf(m, " HEAD: 0x%08x\n", ring->head);
		257	err_printf(m, " TAIL: 0x%08x\n", ring->tail);
		258	err_printf(m, " CTL: 0x%08x\n", ring->ctl);
		259	err_printf(m, " HWS: 0x%08x\n", ring->hws);
5060	serge	260	err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
		261	err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
		262	err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
		263	err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
4560	Serge	264	if (INTEL_INFO(dev)->gen >= 4) {
5060	serge	265	err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
		266	err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
		267	err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
4560	Serge	268	}
5060	serge	269	err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
		270	err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
		271	lower_32_bits(ring->faddr));
4126	Serge	272	if (INTEL_INFO(dev)->gen >= 6) {
5060	serge	273	err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
		274	err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
4126	Serge	275	err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
5060	serge	276	ring->semaphore_mboxes[0],
		277	ring->semaphore_seqno[0]);
4126	Serge	278	err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
5060	serge	279	ring->semaphore_mboxes[1],
		280	ring->semaphore_seqno[1]);
4126	Serge	281	if (HAS_VEBOX(dev)) {
		282	err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
5060	serge	283	ring->semaphore_mboxes[2],
		284	ring->semaphore_seqno[2]);
4126	Serge	285	}
		286	}
5060	serge	287	if (USES_PPGTT(dev)) {
		288	err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
		289
		290	if (INTEL_INFO(dev)->gen >= 8) {
		291	int i;
		292	for (i = 0; i < 4; i++)
		293	err_printf(m, " PDP%d: 0x%016llx\n",
		294	i, ring->vm_info.pdp[i]);
		295	} else {
		296	err_printf(m, " PP_DIR_BASE: 0x%08x\n",
		297	ring->vm_info.pp_dir_base);
		298	}
		299	}
		300	err_printf(m, " seqno: 0x%08x\n", ring->seqno);
		301	err_printf(m, " waiting: %s\n", yesno(ring->waiting));
		302	err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
		303	err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
4560	Serge	304	err_printf(m, " hangcheck: %s [%d]\n",
5060	serge	305	hangcheck_action_to_str(ring->hangcheck_action),
		306	ring->hangcheck_score);
4126	Serge	307	}
		308
		309	void i915_error_printf(struct drm_i915_error_state_buf e, const char f, ...)
		310	{
		311	va_list args;
		312
		313	va_start(args, f);
		314	i915_error_vprintf(e, f, args);
		315	va_end(args);
		316	}
		317
5060	serge	318	static void print_error_obj(struct drm_i915_error_state_buf *m,
		319	struct drm_i915_error_object *obj)
		320	{
		321	int page, offset, elt;
		322
		323	for (page = offset = 0; page < obj->page_count; page++) {
		324	for (elt = 0; elt < PAGE_SIZE/4; elt++) {
		325	err_printf(m, "%08x : %08x\n", offset,
		326	obj->pages[page][elt]);
		327	offset += 4;
		328	}
		329	}
		330	}
		331
4126	Serge	332	int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
		333	const struct i915_error_state_file_priv *error_priv)
		334	{
		335	struct drm_device *dev = error_priv->dev;
5060	serge	336	struct drm_i915_private *dev_priv = dev->dev_private;
4126	Serge	337	struct drm_i915_error_state *error = error_priv->error;
6084	serge	338	struct drm_i915_error_object *obj;
5060	serge	339	int i, j, offset, elt;
		340	int max_hangcheck_score;
4126	Serge	341
		342	if (!error) {
		343	err_printf(m, "no error state collected\n");
		344	goto out;
		345	}
		346
5060	serge	347	err_printf(m, "%s\n", error->error_msg);
4126	Serge	348	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		349	error->time.tv_usec);
		350	err_printf(m, "Kernel: " UTS_RELEASE "\n");
5060	serge	351	max_hangcheck_score = 0;
		352	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		353	if (error->ring[i].hangcheck_score > max_hangcheck_score)
		354	max_hangcheck_score = error->ring[i].hangcheck_score;
		355	}
		356	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		357	if (error->ring[i].hangcheck_score == max_hangcheck_score &&
		358	error->ring[i].pid != -1) {
		359	err_printf(m, "Active process (on ring %s): %s [%d]\n",
		360	ring_str(i),
		361	error->ring[i].comm,
		362	error->ring[i].pid);
		363	}
		364	}
		365	err_printf(m, "Reset count: %u\n", error->reset_count);
		366	err_printf(m, "Suspend count: %u\n", error->suspend_count);
4560	Serge	367	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
7144	serge	368	err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
		369	err_printf(m, "PCI Subsystem: %04x:%04x\n",
		370	dev->pdev->subsystem_vendor,
		371	dev->pdev->subsystem_device);
6084	serge	372	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
6937	serge	373
		374	if (HAS_CSR(dev)) {
		375	struct intel_csr *csr = &dev_priv->csr;
		376
		377	err_printf(m, "DMC loaded: %s\n",
		378	yesno(csr->dmc_payload != NULL));
		379	err_printf(m, "DMC fw version: %d.%d\n",
		380	CSR_VERSION_MAJOR(csr->version),
		381	CSR_VERSION_MINOR(csr->version));
		382	}
		383
4126	Serge	384	err_printf(m, "EIR: 0x%08x\n", error->eir);
		385	err_printf(m, "IER: 0x%08x\n", error->ier);
6084	serge	386	if (INTEL_INFO(dev)->gen >= 8) {
		387	for (i = 0; i < 4; i++)
		388	err_printf(m, "GTIER gt %d: 0x%08x\n", i,
		389	error->gtier[i]);
		390	} else if (HAS_PCH_SPLIT(dev) \|\| IS_VALLEYVIEW(dev))
		391	err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
4126	Serge	392	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
		393	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
		394	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
		395	err_printf(m, "CCID: 0x%08x\n", error->ccid);
4560	Serge	396	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
4126	Serge	397
		398	for (i = 0; i < dev_priv->num_fence_regs; i++)
		399	err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
		400
		401	for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
		402	err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
		403	error->extra_instdone[i]);
		404
		405	if (INTEL_INFO(dev)->gen >= 6) {
		406	err_printf(m, "ERROR: 0x%08x\n", error->error);
6084	serge	407
		408	if (INTEL_INFO(dev)->gen >= 8)
		409	err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
		410	error->fault_data1, error->fault_data0);
		411
4126	Serge	412	err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
		413	}
		414
		415	if (INTEL_INFO(dev)->gen == 7)
		416	err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
		417
6084	serge	418	for (i = 0; i < ARRAY_SIZE(error->ring); i++)
		419	i915_ring_error_state(m, dev, error, i);
4126	Serge	420
6084	serge	421	for (i = 0; i < error->vm_count; i++) {
		422	err_printf(m, "vm[%d]\n", i);
		423
4126	Serge	424	print_error_buffers(m, "Active",
6084	serge	425	error->active_bo[i],
		426	error->active_bo_count[i]);
4126	Serge	427
		428	print_error_buffers(m, "Pinned",
6084	serge	429	error->pinned_bo[i],
		430	error->pinned_bo_count[i]);
		431	}
4126	Serge	432
		433	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
5060	serge	434	obj = error->ring[i].batchbuffer;
		435	if (obj) {
		436	err_puts(m, dev_priv->ring[i].name);
		437	if (error->ring[i].pid != -1)
		438	err_printf(m, " (submitted by %s [%d])",
		439	error->ring[i].comm,
		440	error->ring[i].pid);
6084	serge	441	err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
		442	upper_32_bits(obj->gtt_offset),
		443	lower_32_bits(obj->gtt_offset));
5060	serge	444	print_error_obj(m, obj);
6084	serge	445	}
5060	serge	446
		447	obj = error->ring[i].wa_batchbuffer;
		448	if (obj) {
		449	err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
6084	serge	450	dev_priv->ring[i].name,
		451	lower_32_bits(obj->gtt_offset));
5060	serge	452	print_error_obj(m, obj);
4126	Serge	453	}
		454
		455	if (error->ring[i].num_requests) {
		456	err_printf(m, "%s --- %d requests\n",
		457	dev_priv->ring[i].name,
		458	error->ring[i].num_requests);
		459	for (j = 0; j < error->ring[i].num_requests; j++) {
		460	err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
		461	error->ring[i].requests[j].seqno,
		462	error->ring[i].requests[j].jiffies,
		463	error->ring[i].requests[j].tail);
		464	}
		465	}
		466
		467	if ((obj = error->ring[i].ringbuffer)) {
		468	err_printf(m, "%s --- ringbuffer = 0x%08x\n",
		469	dev_priv->ring[i].name,
6084	serge	470	lower_32_bits(obj->gtt_offset));
5060	serge	471	print_error_obj(m, obj);
4126	Serge	472	}
		473
5060	serge	474	if ((obj = error->ring[i].hws_page)) {
6084	serge	475	u64 hws_offset = obj->gtt_offset;
		476	u32 *hws_page = &obj->pages[0][0];
		477
		478	if (i915.enable_execlists) {
		479	hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
		480	hws_page = &obj->pages[LRC_PPHWSP_PN][0];
		481	}
		482	err_printf(m, "%s --- HW Status = 0x%08llx\n",
		483	dev_priv->ring[i].name, hws_offset);
4126	Serge	484	offset = 0;
		485	for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
		486	err_printf(m, "[%04x] %08x %08x %08x %08x\n",
6084	serge	487	offset,
		488	hws_page[elt],
		489	hws_page[elt+1],
		490	hws_page[elt+2],
		491	hws_page[elt+3]);
4126	Serge	492	offset += 16;
		493	}
		494	}
		495
5060	serge	496	if ((obj = error->ring[i].ctx)) {
		497	err_printf(m, "%s --- HW Context = 0x%08x\n",
		498	dev_priv->ring[i].name,
6084	serge	499	lower_32_bits(obj->gtt_offset));
5060	serge	500	print_error_obj(m, obj);
		501	}
6084	serge	502	}
5060	serge	503
6084	serge	504	if ((obj = error->semaphore_obj)) {
		505	err_printf(m, "Semaphore page = 0x%08x\n",
		506	lower_32_bits(obj->gtt_offset));
		507	for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
		508	err_printf(m, "[%04x] %08x %08x %08x %08x\n",
		509	elt * 4,
		510	obj->pages[0][elt],
		511	obj->pages[0][elt+1],
		512	obj->pages[0][elt+2],
		513	obj->pages[0][elt+3]);
		514	}
		515	}
		516
7144	serge	517	// if (error->overlay)
		518	// intel_overlay_print_error_state(m, error->overlay);
4126	Serge	519
		520	if (error->display)
		521	intel_display_print_error_state(m, dev, error->display);
		522
		523	out:
		524	if (m->bytes == 0 && m->err)
		525	return m->err;
		526
		527	return 0;
		528	}
		529
		530	int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
6084	serge	531	struct drm_i915_private *i915,
4126	Serge	532	size_t count, loff_t pos)
		533	{
		534	memset(ebuf, 0, sizeof(*ebuf));
6084	serge	535	ebuf->i915 = i915;
4126	Serge	536
		537	/* We need to have enough room to store any i915_error_state printf
		538	* so that we can move it to start position.
		539	*/
		540	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
		541	ebuf->buf = kmalloc(ebuf->size,
		542	GFP_TEMPORARY \| __GFP_NORETRY \| __GFP_NOWARN);
		543
		544	if (ebuf->buf == NULL) {
		545	ebuf->size = PAGE_SIZE;
		546	ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
		547	}
		548
		549	if (ebuf->buf == NULL) {
		550	ebuf->size = 128;
		551	ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
		552	}
		553
		554	if (ebuf->buf == NULL)
		555	return -ENOMEM;
		556
		557	ebuf->start = pos;
		558
		559	return 0;
		560	}
		561
		562	static void i915_error_object_free(struct drm_i915_error_object *obj)
		563	{
		564	int page;
		565
		566	if (obj == NULL)
		567	return;
		568
		569	for (page = 0; page < obj->page_count; page++)
		570	kfree(obj->pages[page]);
		571
		572	kfree(obj);
		573	}
		574
		575	static void i915_error_state_free(struct kref *error_ref)
		576	{
		577	struct drm_i915_error_state *error = container_of(error_ref,
		578	typeof(*error), ref);
		579	int i;
		580
		581	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		582	i915_error_object_free(error->ring[i].batchbuffer);
6084	serge	583	i915_error_object_free(error->ring[i].wa_batchbuffer);
4126	Serge	584	i915_error_object_free(error->ring[i].ringbuffer);
5060	serge	585	i915_error_object_free(error->ring[i].hws_page);
4126	Serge	586	i915_error_object_free(error->ring[i].ctx);
		587	kfree(error->ring[i].requests);
		588	}
		589
6084	serge	590	i915_error_object_free(error->semaphore_obj);
		591
		592	for (i = 0; i < error->vm_count; i++)
		593	kfree(error->active_bo[i]);
		594
4126	Serge	595	kfree(error->active_bo);
6084	serge	596	kfree(error->active_bo_count);
		597	kfree(error->pinned_bo);
		598	kfree(error->pinned_bo_count);
4126	Serge	599	kfree(error->overlay);
		600	kfree(error->display);
		601	kfree(error);
		602	}
		603
		604	static struct drm_i915_error_object *
6084	serge	605	i915_error_object_create(struct drm_i915_private *dev_priv,
		606	struct drm_i915_gem_object *src,
		607	struct i915_address_space *vm)
4126	Serge	608	{
		609	struct drm_i915_error_object *dst;
6084	serge	610	struct i915_vma *vma = NULL;
		611	int num_pages;
		612	bool use_ggtt;
		613	int i = 0;
		614	u64 reloc_offset;
4126	Serge	615
		616	if (src == NULL \|\| src->pages == NULL)
		617	return NULL;
		618
6084	serge	619	num_pages = src->base.size >> PAGE_SHIFT;
		620
4126	Serge	621	dst = kmalloc(sizeof(dst) + num_pages sizeof(u32 *), GFP_ATOMIC);
		622	if (dst == NULL)
		623	return NULL;
		624
6084	serge	625	if (i915_gem_obj_bound(src, vm))
		626	dst->gtt_offset = i915_gem_obj_offset(src, vm);
		627	else
		628	dst->gtt_offset = -1;
		629
		630	reloc_offset = dst->gtt_offset;
		631	if (i915_is_ggtt(vm))
		632	vma = i915_gem_obj_to_ggtt(src);
		633	use_ggtt = (src->cache_level == I915_CACHE_NONE &&
		634	vma && (vma->bound & GLOBAL_BIND) &&
		635	reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
		636
		637	/* Cannot access stolen address directly, try to use the aperture */
		638	if (src->stolen) {
		639	use_ggtt = true;
		640
		641	if (!(vma && vma->bound & GLOBAL_BIND))
		642	goto unwind;
		643
		644	reloc_offset = i915_gem_obj_ggtt_offset(src);
		645	if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
		646	goto unwind;
		647	}
		648
		649	/* Cannot access snooped pages through the aperture */
		650	if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
		651	goto unwind;
		652
		653	dst->page_count = num_pages;
		654	while (num_pages--) {
4126	Serge	655	unsigned long flags;
		656	void *d;
		657
		658	d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
		659	if (d == NULL)
		660	goto unwind;
		661
		662	local_irq_save(flags);
6084	serge	663	if (use_ggtt) {
4126	Serge	664	void __iomem *s;
		665
		666	/* Simply ignore tiling or any overlapping fence.
		667	* It's part of the error state, and this hopefully
		668	* captures what the GPU read.
		669	*/
		670
		671	s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
		672	reloc_offset);
		673	memcpy_fromio(d, s, PAGE_SIZE);
		674	io_mapping_unmap_atomic(s);
		675	} else {
		676	struct page *page;
		677	void *s;
		678
		679	page = i915_gem_object_get_page(src, i);
		680
		681	drm_clflush_pages(&page, 1);
		682
		683	s = kmap_atomic(page);
		684	memcpy(d, s, PAGE_SIZE);
		685	kunmap_atomic(s);
		686
		687	drm_clflush_pages(&page, 1);
		688	}
		689	local_irq_restore(flags);
		690
6084	serge	691	dst->pages[i++] = d;
4126	Serge	692	reloc_offset += PAGE_SIZE;
		693	}
		694
		695	return dst;
		696
		697	unwind:
		698	while (i--)
		699	kfree(dst->pages[i]);
		700	kfree(dst);
		701	return NULL;
		702	}
5060	serge	703	#define i915_error_ggtt_object_create(dev_priv, src) \
6084	serge	704	i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
5060	serge	705
4126	Serge	706	static void capture_bo(struct drm_i915_error_buffer *err,
6084	serge	707	struct i915_vma *vma)
4126	Serge	708	{
6084	serge	709	struct drm_i915_gem_object *obj = vma->obj;
		710	int i;
		711
4126	Serge	712	err->size = obj->base.size;
		713	err->name = obj->base.name;
6084	serge	714	for (i = 0; i < I915_NUM_RINGS; i++)
		715	err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
		716	err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
		717	err->gtt_offset = vma->node.start;
4126	Serge	718	err->read_domains = obj->base.read_domains;
		719	err->write_domain = obj->base.write_domain;
		720	err->fence_reg = obj->fence_reg;
		721	err->pinned = 0;
5060	serge	722	if (i915_gem_obj_is_pinned(obj))
4126	Serge	723	err->pinned = 1;
		724	err->tiling = obj->tiling_mode;
		725	err->dirty = obj->dirty;
		726	err->purgeable = obj->madv != I915_MADV_WILLNEED;
5060	serge	727	err->userptr = obj->userptr.mm != NULL;
6084	serge	728	err->ring = obj->last_write_req ?
		729	i915_gem_request_get_ring(obj->last_write_req)->id : -1;
4126	Serge	730	err->cache_level = obj->cache_level;
		731	}
		732
		733	static u32 capture_active_bo(struct drm_i915_error_buffer *err,
		734	int count, struct list_head *head)
		735	{
		736	struct i915_vma *vma;
		737	int i = 0;
		738
7144	serge	739	list_for_each_entry(vma, head, vm_link) {
6084	serge	740	capture_bo(err++, vma);
4126	Serge	741	if (++i == count)
		742	break;
		743	}
		744
		745	return i;
		746	}
		747
		748	static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
6084	serge	749	int count, struct list_head *head,
		750	struct i915_address_space *vm)
4126	Serge	751	{
		752	struct drm_i915_gem_object *obj;
6084	serge	753	struct drm_i915_error_buffer * const first = err;
		754	struct drm_i915_error_buffer * const last = err + count;
4126	Serge	755
		756	list_for_each_entry(obj, head, global_list) {
6084	serge	757	struct i915_vma *vma;
4126	Serge	758
6084	serge	759	if (err == last)
4126	Serge	760	break;
6084	serge	761
7144	serge	762	list_for_each_entry(vma, &obj->vma_list, obj_link)
6084	serge	763	if (vma->vm == vm && vma->pin_count > 0)
		764	capture_bo(err++, vma);
4126	Serge	765	}
		766
6084	serge	767	return err - first;
4126	Serge	768	}
		769
5060	serge	770	/* Generate a semi-unique error code. The code is not meant to have meaning, The
		771	* code's only purpose is to try to prevent false duplicated bug reports by
		772	* grossly estimating a GPU error state.
		773	*
		774	* TODO Ideally, hashing the batchbuffer would be a very nice way to determine
		775	* the hang if we could strip the GTT offset information from it.
		776	*
		777	* It's only a small step better than a random number in its current form.
		778	*/
		779	static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
		780	struct drm_i915_error_state *error,
		781	int *ring_id)
		782	{
		783	uint32_t error_code = 0;
		784	int i;
		785
		786	/* IPEHR would be an ideal way to detect errors, as it's the gross
		787	* measure of "the command that hung." However, has some very common
		788	* synchronization commands which almost always appear in the case
		789	* strictly a client bug. Use instdone to differentiate those some.
		790	*/
		791	for (i = 0; i < I915_NUM_RINGS; i++) {
		792	if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
		793	if (ring_id)
		794	*ring_id = i;
		795
		796	return error->ring[i].ipehr ^ error->ring[i].instdone;
		797	}
		798	}
		799
		800	return error_code;
		801	}
		802
4126	Serge	803	static void i915_gem_record_fences(struct drm_device *dev,
		804	struct drm_i915_error_state *error)
		805	{
		806	struct drm_i915_private *dev_priv = dev->dev_private;
		807	int i;
		808
6084	serge	809	if (IS_GEN3(dev) \|\| IS_GEN2(dev)) {
4126	Serge	810	for (i = 0; i < dev_priv->num_fence_regs; i++)
6084	serge	811	error->fence[i] = I915_READ(FENCE_REG(i));
		812	} else if (IS_GEN5(dev) \|\| IS_GEN4(dev)) {
		813	for (i = 0; i < dev_priv->num_fence_regs; i++)
		814	error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
		815	} else if (INTEL_INFO(dev)->gen >= 6) {
		816	for (i = 0; i < dev_priv->num_fence_regs; i++)
		817	error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
		818	}
		819	}
4126	Serge	820
6084	serge	821
		822	static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
		823	struct drm_i915_error_state *error,
		824	struct intel_engine_cs *ring,
		825	struct drm_i915_error_ring *ering)
		826	{
		827	struct intel_engine_cs *to;
		828	int i;
		829
		830	if (!i915_semaphore_is_enabled(dev_priv->dev))
		831	return;
		832
		833	if (!error->semaphore_obj)
		834	error->semaphore_obj =
		835	i915_error_ggtt_object_create(dev_priv,
		836	dev_priv->semaphore_obj);
		837
		838	for_each_ring(to, dev_priv, i) {
		839	int idx;
		840	u16 signal_offset;
		841	u32 *tmp;
		842
		843	if (ring == to)
		844	continue;
		845
		846	signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
		847	/ 4;
		848	tmp = error->semaphore_obj->pages[0];
		849	idx = intel_ring_sync_index(ring, to);
		850
		851	ering->semaphore_mboxes[idx] = tmp[signal_offset];
		852	ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
4126	Serge	853	}
		854	}
		855
6084	serge	856	static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
		857	struct intel_engine_cs *ring,
		858	struct drm_i915_error_ring *ering)
		859	{
		860	ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
		861	ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
		862	ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
		863	ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
		864
		865	if (HAS_VEBOX(dev_priv->dev)) {
		866	ering->semaphore_mboxes[2] =
		867	I915_READ(RING_SYNC_2(ring->mmio_base));
		868	ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
		869	}
		870	}
		871
4126	Serge	872	static void i915_record_ring_state(struct drm_device *dev,
6084	serge	873	struct drm_i915_error_state *error,
5060	serge	874	struct intel_engine_cs *ring,
		875	struct drm_i915_error_ring *ering)
4126	Serge	876	{
		877	struct drm_i915_private *dev_priv = dev->dev_private;
		878
		879	if (INTEL_INFO(dev)->gen >= 6) {
6937	serge	880	ering->rc_psmi = I915_READ(RING_PSMI_CTL(ring->mmio_base));
5060	serge	881	ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
6084	serge	882	if (INTEL_INFO(dev)->gen >= 8)
		883	gen8_record_semaphore_state(dev_priv, error, ring, ering);
		884	else
		885	gen6_record_semaphore_state(dev_priv, ring, ering);
4126	Serge	886	}
		887
		888	if (INTEL_INFO(dev)->gen >= 4) {
5060	serge	889	ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
		890	ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
		891	ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
		892	ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
		893	ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
		894	ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
		895	if (INTEL_INFO(dev)->gen >= 8) {
		896	ering->faddr \|= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
		897	ering->bbaddr \|= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
		898	}
		899	ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
4126	Serge	900	} else {
5060	serge	901	ering->faddr = I915_READ(DMA_FADD_I8XX);
		902	ering->ipeir = I915_READ(IPEIR);
		903	ering->ipehr = I915_READ(IPEHR);
6084	serge	904	ering->instdone = I915_READ(GEN2_INSTDONE);
4126	Serge	905	}
		906
5060	serge	907	ering->waiting = waitqueue_active(&ring->irq_queue);
		908	ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
		909	ering->seqno = ring->get_seqno(ring, false);
		910	ering->acthd = intel_ring_get_active_head(ring);
6084	serge	911	ering->start = I915_READ_START(ring);
5060	serge	912	ering->head = I915_READ_HEAD(ring);
		913	ering->tail = I915_READ_TAIL(ring);
		914	ering->ctl = I915_READ_CTL(ring);
4126	Serge	915
5060	serge	916	if (I915_NEED_GFX_HWS(dev)) {
6937	serge	917	i915_reg_t mmio;
4560	Serge	918
5060	serge	919	if (IS_GEN7(dev)) {
		920	switch (ring->id) {
		921	default:
		922	case RCS:
		923	mmio = RENDER_HWS_PGA_GEN7;
		924	break;
		925	case BCS:
		926	mmio = BLT_HWS_PGA_GEN7;
		927	break;
		928	case VCS:
		929	mmio = BSD_HWS_PGA_GEN7;
		930	break;
		931	case VECS:
		932	mmio = VEBOX_HWS_PGA_GEN7;
		933	break;
		934	}
		935	} else if (IS_GEN6(ring->dev)) {
		936	mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
		937	} else {
		938	/* XXX: gen8 returns to sanity */
		939	mmio = RING_HWS_PGA(ring->mmio_base);
		940	}
		941
		942	ering->hws = I915_READ(mmio);
		943	}
		944
		945	ering->hangcheck_score = ring->hangcheck.score;
		946	ering->hangcheck_action = ring->hangcheck.action;
		947
		948	if (USES_PPGTT(dev)) {
		949	int i;
		950
		951	ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
		952
6084	serge	953	if (IS_GEN6(dev))
		954	ering->vm_info.pp_dir_base =
		955	I915_READ(RING_PP_DIR_BASE_READ(ring));
		956	else if (IS_GEN7(dev))
		957	ering->vm_info.pp_dir_base =
		958	I915_READ(RING_PP_DIR_BASE(ring));
		959	else if (INTEL_INFO(dev)->gen >= 8)
5060	serge	960	for (i = 0; i < 4; i++) {
		961	ering->vm_info.pdp[i] =
		962	I915_READ(GEN8_RING_PDP_UDW(ring, i));
		963	ering->vm_info.pdp[i] <<= 32;
		964	ering->vm_info.pdp[i] \|=
		965	I915_READ(GEN8_RING_PDP_LDW(ring, i));
		966	}
		967	}
4126	Serge	968	}
		969
		970
5060	serge	971	static void i915_gem_record_active_context(struct intel_engine_cs *ring,
4126	Serge	972	struct drm_i915_error_state *error,
		973	struct drm_i915_error_ring *ering)
		974	{
		975	struct drm_i915_private *dev_priv = ring->dev->dev_private;
		976	struct drm_i915_gem_object *obj;
		977
		978	/* Currently render ring is the only HW context user */
		979	if (ring->id != RCS \|\| !error->ccid)
		980	return;
		981
		982	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6084	serge	983	if (!i915_gem_obj_ggtt_bound(obj))
		984	continue;
		985
4126	Serge	986	if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
5060	serge	987	ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
4126	Serge	988	break;
		989	}
		990	}
		991	}
		992
		993	static void i915_gem_record_rings(struct drm_device *dev,
		994	struct drm_i915_error_state *error)
		995	{
		996	struct drm_i915_private *dev_priv = dev->dev_private;
		997	struct drm_i915_gem_request *request;
		998	int i, count;
		999
4560	Serge	1000	for (i = 0; i < I915_NUM_RINGS; i++) {
5060	serge	1001	struct intel_engine_cs *ring = &dev_priv->ring[i];
6084	serge	1002	struct intel_ringbuffer *rbuf;
4560	Serge	1003
5060	serge	1004	error->ring[i].pid = -1;
		1005
4560	Serge	1006	if (ring->dev == NULL)
		1007	continue;
		1008
		1009	error->ring[i].valid = true;
		1010
6084	serge	1011	i915_record_ring_state(dev, error, ring, &error->ring[i]);
4126	Serge	1012
5060	serge	1013	request = i915_gem_find_active_request(ring);
		1014	if (request) {
6084	serge	1015	struct i915_address_space *vm;
		1016
		1017	vm = request->ctx && request->ctx->ppgtt ?
		1018	&request->ctx->ppgtt->base :
		1019	&dev_priv->gtt.base;
		1020
5060	serge	1021	/* We need to copy these to an anonymous buffer
		1022	* as the simplest method to avoid being overwritten
		1023	* by userspace.
		1024	*/
6084	serge	1025	error->ring[i].batchbuffer =
5060	serge	1026	i915_error_object_create(dev_priv,
		1027	request->batch_obj,
6084	serge	1028	vm);
4126	Serge	1029
6084	serge	1030	if (HAS_BROKEN_CS_TLB(dev_priv->dev))
5060	serge	1031	error->ring[i].wa_batchbuffer =
		1032	i915_error_ggtt_object_create(dev_priv,
		1033	ring->scratch.obj);
		1034
		1035	}
		1036
6084	serge	1037	if (i915.enable_execlists) {
		1038	/* TODO: This is only a small fix to keep basic error
		1039	* capture working, but we need to add more information
		1040	* for it to be useful (e.g. dump the context being
		1041	* executed).
		1042	*/
		1043	if (request)
		1044	rbuf = request->ctx->engine[ring->id].ringbuf;
		1045	else
7144	serge	1046	rbuf = dev_priv->kernel_context->engine[ring->id].ringbuf;
6084	serge	1047	} else
		1048	rbuf = ring->buffer;
		1049
		1050	error->ring[i].cpu_ring_head = rbuf->head;
		1051	error->ring[i].cpu_ring_tail = rbuf->tail;
		1052
4126	Serge	1053	error->ring[i].ringbuffer =
6084	serge	1054	i915_error_ggtt_object_create(dev_priv, rbuf->obj);
4126	Serge	1055
6084	serge	1056	error->ring[i].hws_page =
		1057	i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
4126	Serge	1058
		1059	i915_gem_record_active_context(ring, error, &error->ring[i]);
		1060
		1061	count = 0;
		1062	list_for_each_entry(request, &ring->request_list, list)
		1063	count++;
		1064
		1065	error->ring[i].num_requests = count;
		1066	error->ring[i].requests =
4560	Serge	1067	kcalloc(count, sizeof(*error->ring[i].requests),
4126	Serge	1068	GFP_ATOMIC);
		1069	if (error->ring[i].requests == NULL) {
		1070	error->ring[i].num_requests = 0;
		1071	continue;
		1072	}
		1073
		1074	count = 0;
		1075	list_for_each_entry(request, &ring->request_list, list) {
		1076	struct drm_i915_error_request *erq;
		1077
6937	serge	1078	if (count >= error->ring[i].num_requests) {
		1079	/*
		1080	* If the ring request list was changed in
		1081	* between the point where the error request
		1082	* list was created and dimensioned and this
		1083	* point then just exit early to avoid crashes.
		1084	*
		1085	* We don't need to communicate that the
		1086	* request list changed state during error
		1087	* state capture and that the error state is
		1088	* slightly incorrect as a consequence since we
		1089	* are typically only interested in the request
		1090	* list state at the point of error state
		1091	* capture, not in any changes happening during
		1092	* the capture.
		1093	*/
		1094	break;
		1095	}
		1096
4126	Serge	1097	erq = &error->ring[i].requests[count++];
		1098	erq->seqno = request->seqno;
		1099	erq->jiffies = request->emitted_jiffies;
6084	serge	1100	erq->tail = request->postfix;
4126	Serge	1101	}
		1102	}
		1103	}
		1104
		1105	/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
		1106	* VM.
		1107	*/
		1108	static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
		1109	struct drm_i915_error_state *error,
		1110	struct i915_address_space *vm,
		1111	const int ndx)
		1112	{
		1113	struct drm_i915_error_buffer active_bo = NULL, pinned_bo = NULL;
		1114	struct drm_i915_gem_object *obj;
		1115	struct i915_vma *vma;
		1116	int i;
		1117
		1118	i = 0;
7144	serge	1119	list_for_each_entry(vma, &vm->active_list, vm_link)
4126	Serge	1120	i++;
		1121	error->active_bo_count[ndx] = i;
6084	serge	1122
		1123	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
7144	serge	1124	list_for_each_entry(vma, &obj->vma_list, obj_link)
6084	serge	1125	if (vma->vm == vm && vma->pin_count > 0)
		1126	i++;
		1127	}
4126	Serge	1128	error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
		1129
		1130	if (i) {
4560	Serge	1131	active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
4126	Serge	1132	if (active_bo)
		1133	pinned_bo = active_bo + error->active_bo_count[ndx];
		1134	}
		1135
		1136	if (active_bo)
		1137	error->active_bo_count[ndx] =
		1138	capture_active_bo(active_bo,
		1139	error->active_bo_count[ndx],
		1140	&vm->active_list);
		1141
		1142	if (pinned_bo)
		1143	error->pinned_bo_count[ndx] =
		1144	capture_pinned_bo(pinned_bo,
		1145	error->pinned_bo_count[ndx],
6084	serge	1146	&dev_priv->mm.bound_list, vm);
4126	Serge	1147	error->active_bo[ndx] = active_bo;
		1148	error->pinned_bo[ndx] = pinned_bo;
		1149	}
		1150
		1151	static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
		1152	struct drm_i915_error_state *error)
		1153	{
		1154	struct i915_address_space *vm;
		1155	int cnt = 0, i = 0;
		1156
		1157	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		1158	cnt++;
		1159
		1160	error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
		1161	error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
		1162	error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
		1163	GFP_ATOMIC);
		1164	error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
		1165	GFP_ATOMIC);
		1166
6084	serge	1167	if (error->active_bo == NULL \|\|
		1168	error->pinned_bo == NULL \|\|
		1169	error->active_bo_count == NULL \|\|
		1170	error->pinned_bo_count == NULL) {
		1171	kfree(error->active_bo);
		1172	kfree(error->active_bo_count);
		1173	kfree(error->pinned_bo);
		1174	kfree(error->pinned_bo_count);
		1175
		1176	error->active_bo = NULL;
		1177	error->active_bo_count = NULL;
		1178	error->pinned_bo = NULL;
		1179	error->pinned_bo_count = NULL;
		1180	} else {
		1181	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		1182	i915_gem_capture_vm(dev_priv, error, vm, i++);
		1183
		1184	error->vm_count = cnt;
		1185	}
4126	Serge	1186	}
		1187
5060	serge	1188	/* Capture all registers which don't fit into another category. */
		1189	static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
		1190	struct drm_i915_error_state *error)
		1191	{
		1192	struct drm_device *dev = dev_priv->dev;
6084	serge	1193	int i;
5060	serge	1194
		1195	/* General organization
		1196	* 1. Registers specific to a single generation
		1197	* 2. Registers which belong to multiple generations
		1198	* 3. Feature specific registers.
		1199	* 4. Everything else
		1200	* Please try to follow the order.
		1201	*/
		1202
		1203	/* 1: Registers specific to a single generation */
		1204	if (IS_VALLEYVIEW(dev)) {
6084	serge	1205	error->gtier[0] = I915_READ(GTIER);
		1206	error->ier = I915_READ(VLV_IER);
6937	serge	1207	error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
5060	serge	1208	}
		1209
		1210	if (IS_GEN7(dev))
		1211	error->err_int = I915_READ(GEN7_ERR_INT);
		1212
6084	serge	1213	if (INTEL_INFO(dev)->gen >= 8) {
		1214	error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		1215	error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
		1216	}
		1217
5060	serge	1218	if (IS_GEN6(dev)) {
6937	serge	1219	error->forcewake = I915_READ_FW(FORCEWAKE);
5060	serge	1220	error->gab_ctl = I915_READ(GAB_CTL);
		1221	error->gfx_mode = I915_READ(GFX_MODE);
		1222	}
		1223
		1224	/* 2: Registers which belong to multiple generations */
		1225	if (INTEL_INFO(dev)->gen >= 7)
6937	serge	1226	error->forcewake = I915_READ_FW(FORCEWAKE_MT);
5060	serge	1227
		1228	if (INTEL_INFO(dev)->gen >= 6) {
		1229	error->derrmr = I915_READ(DERRMR);
		1230	error->error = I915_READ(ERROR_GEN6);
		1231	error->done_reg = I915_READ(DONE_REG);
		1232	}
		1233
		1234	/* 3: Feature specific registers */
		1235	if (IS_GEN6(dev) \|\| IS_GEN7(dev)) {
		1236	error->gam_ecochk = I915_READ(GAM_ECOCHK);
		1237	error->gac_eco = I915_READ(GAC_ECO_BITS);
		1238	}
		1239
		1240	/* 4: Everything else */
		1241	if (HAS_HW_CONTEXTS(dev))
		1242	error->ccid = I915_READ(CCID);
		1243
6084	serge	1244	if (INTEL_INFO(dev)->gen >= 8) {
		1245	error->ier = I915_READ(GEN8_DE_MISC_IER);
		1246	for (i = 0; i < 4; i++)
		1247	error->gtier[i] = I915_READ(GEN8_GT_IER(i));
		1248	} else if (HAS_PCH_SPLIT(dev)) {
		1249	error->ier = I915_READ(DEIER);
		1250	error->gtier[0] = I915_READ(GTIER);
		1251	} else if (IS_GEN2(dev)) {
		1252	error->ier = I915_READ16(IER);
		1253	} else if (!IS_VALLEYVIEW(dev)) {
5060	serge	1254	error->ier = I915_READ(IER);
		1255	}
		1256	error->eir = I915_READ(EIR);
		1257	error->pgtbl_er = I915_READ(PGTBL_ER);
		1258
		1259	i915_get_extra_instdone(dev, error->extra_instdone);
		1260	}
		1261
		1262	static void i915_error_capture_msg(struct drm_device *dev,
		1263	struct drm_i915_error_state *error,
		1264	bool wedged,
		1265	const char *error_msg)
		1266	{
		1267	struct drm_i915_private *dev_priv = dev->dev_private;
		1268	u32 ecode;
		1269	int ring_id = -1, len;
		1270
		1271	ecode = i915_error_generate_code(dev_priv, error, &ring_id);
		1272
		1273	len = scnprintf(error->error_msg, sizeof(error->error_msg),
6084	serge	1274	"GPU HANG: ecode %d:%d:0x%08x",
		1275	INTEL_INFO(dev)->gen, ring_id, ecode);
5060	serge	1276
		1277	if (ring_id != -1 && error->ring[ring_id].pid != -1)
		1278	len += scnprintf(error->error_msg + len,
		1279	sizeof(error->error_msg) - len,
		1280	", in %s [%d]",
		1281	error->ring[ring_id].comm,
		1282	error->ring[ring_id].pid);
		1283
		1284	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		1285	", reason: %s, action: %s",
		1286	error_msg,
		1287	wedged ? "reset" : "continue");
		1288	}
		1289
		1290	static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
		1291	struct drm_i915_error_state *error)
		1292	{
6084	serge	1293	error->iommu = -1;
		1294	#ifdef CONFIG_INTEL_IOMMU
		1295	error->iommu = intel_iommu_gfx_mapped;
		1296	#endif
5060	serge	1297	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
		1298	error->suspend_count = dev_priv->suspend_count;
		1299	}
		1300
4126	Serge	1301	/**
		1302	* i915_capture_error_state - capture an error record for later analysis
		1303	* @dev: drm device
		1304	*
		1305	* Should be called when an error is detected (either a hang or an error
		1306	* interrupt) to capture error state from the time of the error. Fills
		1307	* out a structure which becomes available in debugfs for user level tools
		1308	* to pick up.
		1309	*/
5060	serge	1310	void i915_capture_error_state(struct drm_device *dev, bool wedged,
		1311	const char *error_msg)
4126	Serge	1312	{
5060	serge	1313	static bool warned;
4126	Serge	1314	struct drm_i915_private *dev_priv = dev->dev_private;
		1315	struct drm_i915_error_state *error;
		1316	unsigned long flags;
		1317
		1318	/* Account for pipe specific data like PIPESTAT /
		1319	error = kzalloc(sizeof(*error), GFP_ATOMIC);
		1320	if (!error) {
		1321	DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		1322	return;
		1323	}
		1324
		1325	kref_init(&error->ref);
		1326
5060	serge	1327	i915_capture_gen_state(dev_priv, error);
		1328	i915_capture_reg_state(dev_priv, error);
4126	Serge	1329	i915_gem_capture_buffers(dev_priv, error);
		1330	i915_gem_record_fences(dev, error);
		1331	i915_gem_record_rings(dev, error);
		1332
7144	serge	1333	// do_gettimeofday(&error->time);
4126	Serge	1334
7144	serge	1335	// error->overlay = intel_overlay_capture_error_state(dev);
4126	Serge	1336	error->display = intel_display_capture_error_state(dev);
		1337
5060	serge	1338	i915_error_capture_msg(dev, error, wedged, error_msg);
		1339	DRM_INFO("%s\n", error->error_msg);
		1340
4126	Serge	1341	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
		1342	if (dev_priv->gpu_error.first_error == NULL) {
		1343	dev_priv->gpu_error.first_error = error;
		1344	error = NULL;
		1345	}
		1346	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
		1347
5060	serge	1348	if (error) {
4126	Serge	1349	i915_error_state_free(&error->ref);
5060	serge	1350	return;
		1351	}
		1352
		1353	if (!warned) {
		1354	DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		1355	DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		1356	DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		1357	DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
		1358	DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
		1359	warned = true;
		1360	}
4126	Serge	1361	}
		1362
		1363	void i915_error_state_get(struct drm_device *dev,
		1364	struct i915_error_state_file_priv *error_priv)
		1365	{
		1366	struct drm_i915_private *dev_priv = dev->dev_private;
		1367
6084	serge	1368	spin_lock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1369	error_priv->error = dev_priv->gpu_error.first_error;
		1370	if (error_priv->error)
		1371	kref_get(&error_priv->error->ref);
6084	serge	1372	spin_unlock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1373
		1374	}
		1375
		1376	void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
		1377	{
		1378	if (error_priv->error)
		1379	kref_put(&error_priv->error->ref, i915_error_state_free);
		1380	}
		1381
		1382	void i915_destroy_error_state(struct drm_device *dev)
		1383	{
		1384	struct drm_i915_private *dev_priv = dev->dev_private;
		1385	struct drm_i915_error_state *error;
		1386
6084	serge	1387	spin_lock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1388	error = dev_priv->gpu_error.first_error;
		1389	dev_priv->gpu_error.first_error = NULL;
6084	serge	1390	spin_unlock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1391
		1392	if (error)
		1393	kref_put(&error->ref, i915_error_state_free);
		1394	}
		1395
6084	serge	1396	const char i915_cache_level_str(struct drm_i915_private i915, int type)
4126	Serge	1397	{
		1398	switch (type) {
		1399	case I915_CACHE_NONE: return " uncached";
6084	serge	1400	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
4126	Serge	1401	case I915_CACHE_L3_LLC: return " L3+LLC";
4560	Serge	1402	case I915_CACHE_WT: return " WT";
4126	Serge	1403	default: return "";
		1404	}
		1405	}
		1406
		1407	/* NB: please notice the memset */
		1408	void i915_get_extra_instdone(struct drm_device dev, uint32_t instdone)
		1409	{
		1410	struct drm_i915_private *dev_priv = dev->dev_private;
		1411	memset(instdone, 0, sizeof(instdone) I915_NUM_INSTDONE_REG);
		1412
6084	serge	1413	if (IS_GEN2(dev) \|\| IS_GEN3(dev))
		1414	instdone[0] = I915_READ(GEN2_INSTDONE);
		1415	else if (IS_GEN4(dev) \|\| IS_GEN5(dev) \|\| IS_GEN6(dev)) {
		1416	instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
		1417	instdone[1] = I915_READ(GEN4_INSTDONE1);
		1418	} else if (INTEL_INFO(dev)->gen >= 7) {
		1419	instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
4126	Serge	1420	instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		1421	instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		1422	instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
		1423	}
		1424	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gpu_error.c @ 5367 – Rev 7144