WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_gpu_error.c

Rev	Author	Line No.	Line
4126	Serge	1	/*
		2	* Copyright (c) 2008 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	* Keith Packard
		26	* Mika Kuoppala
		27	*
		28	*/
		29
		30	#include "i915_drv.h"
		31
		32	#if 0
		33
		34	static const char *ring_str(int ring)
		35	{
		36	switch (ring) {
		37	case RCS: return "render";
		38	case VCS: return "bsd";
		39	case BCS: return "blt";
		40	case VECS: return "vebox";
5060	serge	41	case VCS2: return "bsd2";
4126	Serge	42	default: return "";
		43	}
		44	}
		45
		46	static const char *pin_flag(int pinned)
		47	{
		48	if (pinned > 0)
		49	return " P";
		50	else if (pinned < 0)
		51	return " p";
		52	else
		53	return "";
		54	}
		55
		56	static const char *tiling_flag(int tiling)
		57	{
		58	switch (tiling) {
		59	default:
		60	case I915_TILING_NONE: return "";
		61	case I915_TILING_X: return " X";
		62	case I915_TILING_Y: return " Y";
		63	}
		64	}
		65
		66	static const char *dirty_flag(int dirty)
		67	{
		68	return dirty ? " dirty" : "";
		69	}
		70
		71	static const char *purgeable_flag(int purgeable)
		72	{
		73	return purgeable ? " purgeable" : "";
		74	}
		75
		76	static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
		77	{
		78
		79	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		80	e->err = -ENOSPC;
		81	return false;
		82	}
		83
		84	if (e->bytes == e->size - 1 \|\| e->err)
		85	return false;
		86
		87	return true;
		88	}
		89
		90	static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
		91	unsigned len)
		92	{
		93	if (e->pos + len <= e->start) {
		94	e->pos += len;
		95	return false;
		96	}
		97
		98	/* First vsnprintf needs to fit in its entirety for memmove */
		99	if (len >= e->size) {
		100	e->err = -EIO;
		101	return false;
		102	}
		103
		104	return true;
		105	}
		106
		107	static void __i915_error_advance(struct drm_i915_error_state_buf *e,
		108	unsigned len)
		109	{
		110	/* If this is first printf in this window, adjust it so that
		111	* start position matches start of the buffer
		112	*/
		113
		114	if (e->pos < e->start) {
		115	const size_t off = e->start - e->pos;
		116
		117	/* Should not happen but be paranoid */
		118	if (off > len \|\| e->bytes) {
		119	e->err = -EIO;
		120	return;
		121	}
		122
		123	memmove(e->buf, e->buf + off, len - off);
		124	e->bytes = len - off;
		125	e->pos = e->start;
		126	return;
		127	}
		128
		129	e->bytes += len;
		130	e->pos += len;
		131	}
		132
		133	static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
		134	const char *f, va_list args)
		135	{
		136	unsigned len;
		137
		138	if (!__i915_error_ok(e))
		139	return;
		140
		141	/* Seek the first printf which is hits start position */
		142	if (e->pos < e->start) {
		143	va_list tmp;
		144
		145	va_copy(tmp, args);
5060	serge	146	len = vsnprintf(NULL, 0, f, tmp);
		147	va_end(tmp);
		148
		149	if (!__i915_error_seek(e, len))
4126	Serge	150	return;
		151	}
		152
		153	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
		154	if (len >= e->size - e->bytes)
		155	len = e->size - e->bytes - 1;
		156
		157	__i915_error_advance(e, len);
		158	}
		159
		160	static void i915_error_puts(struct drm_i915_error_state_buf *e,
		161	const char *str)
		162	{
		163	unsigned len;
		164
		165	if (!__i915_error_ok(e))
		166	return;
		167
		168	len = strlen(str);
		169
		170	/* Seek the first printf which is hits start position */
		171	if (e->pos < e->start) {
		172	if (!__i915_error_seek(e, len))
		173	return;
		174	}
		175
		176	if (len >= e->size - e->bytes)
		177	len = e->size - e->bytes - 1;
		178	memcpy(e->buf + e->bytes, str, len);
		179
		180	__i915_error_advance(e, len);
		181	}
		182
		183	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		184	#define err_puts(e, s) i915_error_puts(e, s)
		185
		186	static void print_error_buffers(struct drm_i915_error_state_buf *m,
		187	const char *name,
		188	struct drm_i915_error_buffer *err,
		189	int count)
		190	{
6084	serge	191	int i;
		192
5354	serge	193	err_printf(m, " %s [%d]:\n", name, count);
4126	Serge	194
		195	while (count--) {
6084	serge	196	err_printf(m, " %08x_%08x %8u %02x %02x [ ",
		197	upper_32_bits(err->gtt_offset),
		198	lower_32_bits(err->gtt_offset),
4126	Serge	199	err->size,
		200	err->read_domains,
6084	serge	201	err->write_domain);
		202	for (i = 0; i < I915_NUM_RINGS; i++)
		203	err_printf(m, "%02x ", err->rseqno[i]);
		204
		205	err_printf(m, "] %02x", err->wseqno);
4126	Serge	206	err_puts(m, pin_flag(err->pinned));
		207	err_puts(m, tiling_flag(err->tiling));
		208	err_puts(m, dirty_flag(err->dirty));
		209	err_puts(m, purgeable_flag(err->purgeable));
5060	serge	210	err_puts(m, err->userptr ? " userptr" : "");
4126	Serge	211	err_puts(m, err->ring != -1 ? " " : "");
		212	err_puts(m, ring_str(err->ring));
5354	serge	213	err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
4126	Serge	214
		215	if (err->name)
		216	err_printf(m, " (name: %d)", err->name);
		217	if (err->fence_reg != I915_FENCE_REG_NONE)
		218	err_printf(m, " (fence: %d)", err->fence_reg);
		219
		220	err_puts(m, "\n");
		221	err++;
		222	}
		223	}
		224
4560	Serge	225	static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
		226	{
		227	switch (a) {
		228	case HANGCHECK_IDLE:
		229	return "idle";
		230	case HANGCHECK_WAIT:
		231	return "wait";
		232	case HANGCHECK_ACTIVE:
		233	return "active";
5354	serge	234	case HANGCHECK_ACTIVE_LOOP:
		235	return "active (loop)";
4560	Serge	236	case HANGCHECK_KICK:
		237	return "kick";
		238	case HANGCHECK_HUNG:
		239	return "hung";
		240	}
		241
		242	return "unknown";
		243	}
		244
4126	Serge	245	static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
		246	struct drm_device *dev,
6084	serge	247	struct drm_i915_error_state *error,
		248	int ring_idx)
4126	Serge	249	{
6084	serge	250	struct drm_i915_error_ring *ring = &error->ring[ring_idx];
		251
5060	serge	252	if (!ring->valid)
4560	Serge	253	return;
		254
6084	serge	255	err_printf(m, "%s command stream:\n", ring_str(ring_idx));
		256	err_printf(m, " START: 0x%08x\n", ring->start);
		257	err_printf(m, " HEAD: 0x%08x\n", ring->head);
		258	err_printf(m, " TAIL: 0x%08x\n", ring->tail);
		259	err_printf(m, " CTL: 0x%08x\n", ring->ctl);
		260	err_printf(m, " HWS: 0x%08x\n", ring->hws);
5060	serge	261	err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
		262	err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
		263	err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
		264	err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
4560	Serge	265	if (INTEL_INFO(dev)->gen >= 4) {
5060	serge	266	err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
		267	err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
		268	err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
4560	Serge	269	}
5060	serge	270	err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
		271	err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
		272	lower_32_bits(ring->faddr));
4126	Serge	273	if (INTEL_INFO(dev)->gen >= 6) {
5060	serge	274	err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
		275	err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
4126	Serge	276	err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
5060	serge	277	ring->semaphore_mboxes[0],
		278	ring->semaphore_seqno[0]);
4126	Serge	279	err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
5060	serge	280	ring->semaphore_mboxes[1],
		281	ring->semaphore_seqno[1]);
4126	Serge	282	if (HAS_VEBOX(dev)) {
		283	err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
5060	serge	284	ring->semaphore_mboxes[2],
		285	ring->semaphore_seqno[2]);
4126	Serge	286	}
		287	}
5060	serge	288	if (USES_PPGTT(dev)) {
		289	err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
		290
		291	if (INTEL_INFO(dev)->gen >= 8) {
		292	int i;
		293	for (i = 0; i < 4; i++)
		294	err_printf(m, " PDP%d: 0x%016llx\n",
		295	i, ring->vm_info.pdp[i]);
		296	} else {
		297	err_printf(m, " PP_DIR_BASE: 0x%08x\n",
		298	ring->vm_info.pp_dir_base);
		299	}
		300	}
		301	err_printf(m, " seqno: 0x%08x\n", ring->seqno);
		302	err_printf(m, " waiting: %s\n", yesno(ring->waiting));
		303	err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
		304	err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
4560	Serge	305	err_printf(m, " hangcheck: %s [%d]\n",
5060	serge	306	hangcheck_action_to_str(ring->hangcheck_action),
		307	ring->hangcheck_score);
4126	Serge	308	}
		309
		310	void i915_error_printf(struct drm_i915_error_state_buf e, const char f, ...)
		311	{
		312	va_list args;
		313
		314	va_start(args, f);
		315	i915_error_vprintf(e, f, args);
		316	va_end(args);
		317	}
		318
5060	serge	319	static void print_error_obj(struct drm_i915_error_state_buf *m,
		320	struct drm_i915_error_object *obj)
		321	{
		322	int page, offset, elt;
		323
		324	for (page = offset = 0; page < obj->page_count; page++) {
		325	for (elt = 0; elt < PAGE_SIZE/4; elt++) {
		326	err_printf(m, "%08x : %08x\n", offset,
		327	obj->pages[page][elt]);
		328	offset += 4;
		329	}
		330	}
		331	}
		332
4126	Serge	333	int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
		334	const struct i915_error_state_file_priv *error_priv)
		335	{
		336	struct drm_device *dev = error_priv->dev;
5060	serge	337	struct drm_i915_private *dev_priv = dev->dev_private;
4126	Serge	338	struct drm_i915_error_state *error = error_priv->error;
6084	serge	339	struct drm_i915_error_object *obj;
5060	serge	340	int i, j, offset, elt;
		341	int max_hangcheck_score;
4126	Serge	342
		343	if (!error) {
		344	err_printf(m, "no error state collected\n");
		345	goto out;
		346	}
		347
5060	serge	348	err_printf(m, "%s\n", error->error_msg);
4126	Serge	349	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		350	error->time.tv_usec);
		351	err_printf(m, "Kernel: " UTS_RELEASE "\n");
5060	serge	352	max_hangcheck_score = 0;
		353	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		354	if (error->ring[i].hangcheck_score > max_hangcheck_score)
		355	max_hangcheck_score = error->ring[i].hangcheck_score;
		356	}
		357	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		358	if (error->ring[i].hangcheck_score == max_hangcheck_score &&
		359	error->ring[i].pid != -1) {
		360	err_printf(m, "Active process (on ring %s): %s [%d]\n",
		361	ring_str(i),
		362	error->ring[i].comm,
		363	error->ring[i].pid);
		364	}
		365	}
		366	err_printf(m, "Reset count: %u\n", error->reset_count);
		367	err_printf(m, "Suspend count: %u\n", error->suspend_count);
4560	Serge	368	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
6084	serge	369	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
6937	serge	370
		371	if (HAS_CSR(dev)) {
		372	struct intel_csr *csr = &dev_priv->csr;
		373
		374	err_printf(m, "DMC loaded: %s\n",
		375	yesno(csr->dmc_payload != NULL));
		376	err_printf(m, "DMC fw version: %d.%d\n",
		377	CSR_VERSION_MAJOR(csr->version),
		378	CSR_VERSION_MINOR(csr->version));
		379	}
		380
4126	Serge	381	err_printf(m, "EIR: 0x%08x\n", error->eir);
		382	err_printf(m, "IER: 0x%08x\n", error->ier);
6084	serge	383	if (INTEL_INFO(dev)->gen >= 8) {
		384	for (i = 0; i < 4; i++)
		385	err_printf(m, "GTIER gt %d: 0x%08x\n", i,
		386	error->gtier[i]);
		387	} else if (HAS_PCH_SPLIT(dev) \|\| IS_VALLEYVIEW(dev))
		388	err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
4126	Serge	389	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
		390	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
		391	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
		392	err_printf(m, "CCID: 0x%08x\n", error->ccid);
4560	Serge	393	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
4126	Serge	394
		395	for (i = 0; i < dev_priv->num_fence_regs; i++)
		396	err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
		397
		398	for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
		399	err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
		400	error->extra_instdone[i]);
		401
		402	if (INTEL_INFO(dev)->gen >= 6) {
		403	err_printf(m, "ERROR: 0x%08x\n", error->error);
6084	serge	404
		405	if (INTEL_INFO(dev)->gen >= 8)
		406	err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
		407	error->fault_data1, error->fault_data0);
		408
4126	Serge	409	err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
		410	}
		411
		412	if (INTEL_INFO(dev)->gen == 7)
		413	err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
		414
6084	serge	415	for (i = 0; i < ARRAY_SIZE(error->ring); i++)
		416	i915_ring_error_state(m, dev, error, i);
4126	Serge	417
6084	serge	418	for (i = 0; i < error->vm_count; i++) {
		419	err_printf(m, "vm[%d]\n", i);
		420
4126	Serge	421	print_error_buffers(m, "Active",
6084	serge	422	error->active_bo[i],
		423	error->active_bo_count[i]);
4126	Serge	424
		425	print_error_buffers(m, "Pinned",
6084	serge	426	error->pinned_bo[i],
		427	error->pinned_bo_count[i]);
		428	}
4126	Serge	429
		430	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
5060	serge	431	obj = error->ring[i].batchbuffer;
		432	if (obj) {
		433	err_puts(m, dev_priv->ring[i].name);
		434	if (error->ring[i].pid != -1)
		435	err_printf(m, " (submitted by %s [%d])",
		436	error->ring[i].comm,
		437	error->ring[i].pid);
6084	serge	438	err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
		439	upper_32_bits(obj->gtt_offset),
		440	lower_32_bits(obj->gtt_offset));
5060	serge	441	print_error_obj(m, obj);
6084	serge	442	}
5060	serge	443
		444	obj = error->ring[i].wa_batchbuffer;
		445	if (obj) {
		446	err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
6084	serge	447	dev_priv->ring[i].name,
		448	lower_32_bits(obj->gtt_offset));
5060	serge	449	print_error_obj(m, obj);
4126	Serge	450	}
		451
		452	if (error->ring[i].num_requests) {
		453	err_printf(m, "%s --- %d requests\n",
		454	dev_priv->ring[i].name,
		455	error->ring[i].num_requests);
		456	for (j = 0; j < error->ring[i].num_requests; j++) {
		457	err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
		458	error->ring[i].requests[j].seqno,
		459	error->ring[i].requests[j].jiffies,
		460	error->ring[i].requests[j].tail);
		461	}
		462	}
		463
		464	if ((obj = error->ring[i].ringbuffer)) {
		465	err_printf(m, "%s --- ringbuffer = 0x%08x\n",
		466	dev_priv->ring[i].name,
6084	serge	467	lower_32_bits(obj->gtt_offset));
5060	serge	468	print_error_obj(m, obj);
4126	Serge	469	}
		470
5060	serge	471	if ((obj = error->ring[i].hws_page)) {
6084	serge	472	u64 hws_offset = obj->gtt_offset;
		473	u32 *hws_page = &obj->pages[0][0];
		474
		475	if (i915.enable_execlists) {
		476	hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
		477	hws_page = &obj->pages[LRC_PPHWSP_PN][0];
		478	}
		479	err_printf(m, "%s --- HW Status = 0x%08llx\n",
		480	dev_priv->ring[i].name, hws_offset);
4126	Serge	481	offset = 0;
		482	for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
		483	err_printf(m, "[%04x] %08x %08x %08x %08x\n",
6084	serge	484	offset,
		485	hws_page[elt],
		486	hws_page[elt+1],
		487	hws_page[elt+2],
		488	hws_page[elt+3]);
4126	Serge	489	offset += 16;
		490	}
		491	}
		492
5060	serge	493	if ((obj = error->ring[i].ctx)) {
		494	err_printf(m, "%s --- HW Context = 0x%08x\n",
		495	dev_priv->ring[i].name,
6084	serge	496	lower_32_bits(obj->gtt_offset));
5060	serge	497	print_error_obj(m, obj);
		498	}
6084	serge	499	}
5060	serge	500
6084	serge	501	if ((obj = error->semaphore_obj)) {
		502	err_printf(m, "Semaphore page = 0x%08x\n",
		503	lower_32_bits(obj->gtt_offset));
		504	for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
		505	err_printf(m, "[%04x] %08x %08x %08x %08x\n",
		506	elt * 4,
		507	obj->pages[0][elt],
		508	obj->pages[0][elt+1],
		509	obj->pages[0][elt+2],
		510	obj->pages[0][elt+3]);
		511	}
		512	}
		513
4126	Serge	514	if (error->overlay)
		515	intel_overlay_print_error_state(m, error->overlay);
		516
		517	if (error->display)
		518	intel_display_print_error_state(m, dev, error->display);
		519
		520	out:
		521	if (m->bytes == 0 && m->err)
		522	return m->err;
		523
		524	return 0;
		525	}
		526
		527	int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
6084	serge	528	struct drm_i915_private *i915,
4126	Serge	529	size_t count, loff_t pos)
		530	{
		531	memset(ebuf, 0, sizeof(*ebuf));
6084	serge	532	ebuf->i915 = i915;
4126	Serge	533
		534	/* We need to have enough room to store any i915_error_state printf
		535	* so that we can move it to start position.
		536	*/
		537	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
		538	ebuf->buf = kmalloc(ebuf->size,
		539	GFP_TEMPORARY \| __GFP_NORETRY \| __GFP_NOWARN);
		540
		541	if (ebuf->buf == NULL) {
		542	ebuf->size = PAGE_SIZE;
		543	ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
		544	}
		545
		546	if (ebuf->buf == NULL) {
		547	ebuf->size = 128;
		548	ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
		549	}
		550
		551	if (ebuf->buf == NULL)
		552	return -ENOMEM;
		553
		554	ebuf->start = pos;
		555
		556	return 0;
		557	}
		558
		559	static void i915_error_object_free(struct drm_i915_error_object *obj)
		560	{
		561	int page;
		562
		563	if (obj == NULL)
		564	return;
		565
		566	for (page = 0; page < obj->page_count; page++)
		567	kfree(obj->pages[page]);
		568
		569	kfree(obj);
		570	}
		571
		572	static void i915_error_state_free(struct kref *error_ref)
		573	{
		574	struct drm_i915_error_state *error = container_of(error_ref,
		575	typeof(*error), ref);
		576	int i;
		577
		578	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		579	i915_error_object_free(error->ring[i].batchbuffer);
6084	serge	580	i915_error_object_free(error->ring[i].wa_batchbuffer);
4126	Serge	581	i915_error_object_free(error->ring[i].ringbuffer);
5060	serge	582	i915_error_object_free(error->ring[i].hws_page);
4126	Serge	583	i915_error_object_free(error->ring[i].ctx);
		584	kfree(error->ring[i].requests);
		585	}
		586
6084	serge	587	i915_error_object_free(error->semaphore_obj);
		588
		589	for (i = 0; i < error->vm_count; i++)
		590	kfree(error->active_bo[i]);
		591
4126	Serge	592	kfree(error->active_bo);
6084	serge	593	kfree(error->active_bo_count);
		594	kfree(error->pinned_bo);
		595	kfree(error->pinned_bo_count);
4126	Serge	596	kfree(error->overlay);
		597	kfree(error->display);
		598	kfree(error);
		599	}
		600
		601	static struct drm_i915_error_object *
6084	serge	602	i915_error_object_create(struct drm_i915_private *dev_priv,
		603	struct drm_i915_gem_object *src,
		604	struct i915_address_space *vm)
4126	Serge	605	{
		606	struct drm_i915_error_object *dst;
6084	serge	607	struct i915_vma *vma = NULL;
		608	int num_pages;
		609	bool use_ggtt;
		610	int i = 0;
		611	u64 reloc_offset;
4126	Serge	612
		613	if (src == NULL \|\| src->pages == NULL)
		614	return NULL;
		615
6084	serge	616	num_pages = src->base.size >> PAGE_SHIFT;
		617
4126	Serge	618	dst = kmalloc(sizeof(dst) + num_pages sizeof(u32 *), GFP_ATOMIC);
		619	if (dst == NULL)
		620	return NULL;
		621
6084	serge	622	if (i915_gem_obj_bound(src, vm))
		623	dst->gtt_offset = i915_gem_obj_offset(src, vm);
		624	else
		625	dst->gtt_offset = -1;
		626
		627	reloc_offset = dst->gtt_offset;
		628	if (i915_is_ggtt(vm))
		629	vma = i915_gem_obj_to_ggtt(src);
		630	use_ggtt = (src->cache_level == I915_CACHE_NONE &&
		631	vma && (vma->bound & GLOBAL_BIND) &&
		632	reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
		633
		634	/* Cannot access stolen address directly, try to use the aperture */
		635	if (src->stolen) {
		636	use_ggtt = true;
		637
		638	if (!(vma && vma->bound & GLOBAL_BIND))
		639	goto unwind;
		640
		641	reloc_offset = i915_gem_obj_ggtt_offset(src);
		642	if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
		643	goto unwind;
		644	}
		645
		646	/* Cannot access snooped pages through the aperture */
		647	if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
		648	goto unwind;
		649
		650	dst->page_count = num_pages;
		651	while (num_pages--) {
4126	Serge	652	unsigned long flags;
		653	void *d;
		654
		655	d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
		656	if (d == NULL)
		657	goto unwind;
		658
		659	local_irq_save(flags);
6084	serge	660	if (use_ggtt) {
4126	Serge	661	void __iomem *s;
		662
		663	/* Simply ignore tiling or any overlapping fence.
		664	* It's part of the error state, and this hopefully
		665	* captures what the GPU read.
		666	*/
		667
		668	s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
		669	reloc_offset);
		670	memcpy_fromio(d, s, PAGE_SIZE);
		671	io_mapping_unmap_atomic(s);
		672	} else {
		673	struct page *page;
		674	void *s;
		675
		676	page = i915_gem_object_get_page(src, i);
		677
		678	drm_clflush_pages(&page, 1);
		679
		680	s = kmap_atomic(page);
		681	memcpy(d, s, PAGE_SIZE);
		682	kunmap_atomic(s);
		683
		684	drm_clflush_pages(&page, 1);
		685	}
		686	local_irq_restore(flags);
		687
6084	serge	688	dst->pages[i++] = d;
4126	Serge	689	reloc_offset += PAGE_SIZE;
		690	}
		691
		692	return dst;
		693
		694	unwind:
		695	while (i--)
		696	kfree(dst->pages[i]);
		697	kfree(dst);
		698	return NULL;
		699	}
5060	serge	700	#define i915_error_ggtt_object_create(dev_priv, src) \
6084	serge	701	i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
5060	serge	702
4126	Serge	703	static void capture_bo(struct drm_i915_error_buffer *err,
6084	serge	704	struct i915_vma *vma)
4126	Serge	705	{
6084	serge	706	struct drm_i915_gem_object *obj = vma->obj;
		707	int i;
		708
4126	Serge	709	err->size = obj->base.size;
		710	err->name = obj->base.name;
6084	serge	711	for (i = 0; i < I915_NUM_RINGS; i++)
		712	err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
		713	err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
		714	err->gtt_offset = vma->node.start;
4126	Serge	715	err->read_domains = obj->base.read_domains;
		716	err->write_domain = obj->base.write_domain;
		717	err->fence_reg = obj->fence_reg;
		718	err->pinned = 0;
5060	serge	719	if (i915_gem_obj_is_pinned(obj))
4126	Serge	720	err->pinned = 1;
		721	err->tiling = obj->tiling_mode;
		722	err->dirty = obj->dirty;
		723	err->purgeable = obj->madv != I915_MADV_WILLNEED;
5060	serge	724	err->userptr = obj->userptr.mm != NULL;
6084	serge	725	err->ring = obj->last_write_req ?
		726	i915_gem_request_get_ring(obj->last_write_req)->id : -1;
4126	Serge	727	err->cache_level = obj->cache_level;
		728	}
		729
		730	static u32 capture_active_bo(struct drm_i915_error_buffer *err,
		731	int count, struct list_head *head)
		732	{
		733	struct i915_vma *vma;
		734	int i = 0;
		735
		736	list_for_each_entry(vma, head, mm_list) {
6084	serge	737	capture_bo(err++, vma);
4126	Serge	738	if (++i == count)
		739	break;
		740	}
		741
		742	return i;
		743	}
		744
		745	static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
6084	serge	746	int count, struct list_head *head,
		747	struct i915_address_space *vm)
4126	Serge	748	{
		749	struct drm_i915_gem_object *obj;
6084	serge	750	struct drm_i915_error_buffer * const first = err;
		751	struct drm_i915_error_buffer * const last = err + count;
4126	Serge	752
		753	list_for_each_entry(obj, head, global_list) {
6084	serge	754	struct i915_vma *vma;
4126	Serge	755
6084	serge	756	if (err == last)
4126	Serge	757	break;
6084	serge	758
		759	list_for_each_entry(vma, &obj->vma_list, vma_link)
		760	if (vma->vm == vm && vma->pin_count > 0)
		761	capture_bo(err++, vma);
4126	Serge	762	}
		763
6084	serge	764	return err - first;
4126	Serge	765	}
		766
5060	serge	767	/* Generate a semi-unique error code. The code is not meant to have meaning, The
		768	* code's only purpose is to try to prevent false duplicated bug reports by
		769	* grossly estimating a GPU error state.
		770	*
		771	* TODO Ideally, hashing the batchbuffer would be a very nice way to determine
		772	* the hang if we could strip the GTT offset information from it.
		773	*
		774	* It's only a small step better than a random number in its current form.
		775	*/
		776	static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
		777	struct drm_i915_error_state *error,
		778	int *ring_id)
		779	{
		780	uint32_t error_code = 0;
		781	int i;
		782
		783	/* IPEHR would be an ideal way to detect errors, as it's the gross
		784	* measure of "the command that hung." However, has some very common
		785	* synchronization commands which almost always appear in the case
		786	* strictly a client bug. Use instdone to differentiate those some.
		787	*/
		788	for (i = 0; i < I915_NUM_RINGS; i++) {
		789	if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
		790	if (ring_id)
		791	*ring_id = i;
		792
		793	return error->ring[i].ipehr ^ error->ring[i].instdone;
		794	}
		795	}
		796
		797	return error_code;
		798	}
		799
4126	Serge	800	static void i915_gem_record_fences(struct drm_device *dev,
		801	struct drm_i915_error_state *error)
		802	{
		803	struct drm_i915_private *dev_priv = dev->dev_private;
		804	int i;
		805
6084	serge	806	if (IS_GEN3(dev) \|\| IS_GEN2(dev)) {
4126	Serge	807	for (i = 0; i < dev_priv->num_fence_regs; i++)
6084	serge	808	error->fence[i] = I915_READ(FENCE_REG(i));
		809	} else if (IS_GEN5(dev) \|\| IS_GEN4(dev)) {
		810	for (i = 0; i < dev_priv->num_fence_regs; i++)
		811	error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
		812	} else if (INTEL_INFO(dev)->gen >= 6) {
		813	for (i = 0; i < dev_priv->num_fence_regs; i++)
		814	error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
		815	}
		816	}
4126	Serge	817
6084	serge	818
		819	static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
		820	struct drm_i915_error_state *error,
		821	struct intel_engine_cs *ring,
		822	struct drm_i915_error_ring *ering)
		823	{
		824	struct intel_engine_cs *to;
		825	int i;
		826
		827	if (!i915_semaphore_is_enabled(dev_priv->dev))
		828	return;
		829
		830	if (!error->semaphore_obj)
		831	error->semaphore_obj =
		832	i915_error_ggtt_object_create(dev_priv,
		833	dev_priv->semaphore_obj);
		834
		835	for_each_ring(to, dev_priv, i) {
		836	int idx;
		837	u16 signal_offset;
		838	u32 *tmp;
		839
		840	if (ring == to)
		841	continue;
		842
		843	signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
		844	/ 4;
		845	tmp = error->semaphore_obj->pages[0];
		846	idx = intel_ring_sync_index(ring, to);
		847
		848	ering->semaphore_mboxes[idx] = tmp[signal_offset];
		849	ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
4126	Serge	850	}
		851	}
		852
6084	serge	853	static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
		854	struct intel_engine_cs *ring,
		855	struct drm_i915_error_ring *ering)
		856	{
		857	ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
		858	ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
		859	ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
		860	ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
		861
		862	if (HAS_VEBOX(dev_priv->dev)) {
		863	ering->semaphore_mboxes[2] =
		864	I915_READ(RING_SYNC_2(ring->mmio_base));
		865	ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
		866	}
		867	}
		868
4126	Serge	869	static void i915_record_ring_state(struct drm_device *dev,
6084	serge	870	struct drm_i915_error_state *error,
5060	serge	871	struct intel_engine_cs *ring,
		872	struct drm_i915_error_ring *ering)
4126	Serge	873	{
		874	struct drm_i915_private *dev_priv = dev->dev_private;
		875
		876	if (INTEL_INFO(dev)->gen >= 6) {
6937	serge	877	ering->rc_psmi = I915_READ(RING_PSMI_CTL(ring->mmio_base));
5060	serge	878	ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
6084	serge	879	if (INTEL_INFO(dev)->gen >= 8)
		880	gen8_record_semaphore_state(dev_priv, error, ring, ering);
		881	else
		882	gen6_record_semaphore_state(dev_priv, ring, ering);
4126	Serge	883	}
		884
		885	if (INTEL_INFO(dev)->gen >= 4) {
5060	serge	886	ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
		887	ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
		888	ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
		889	ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
		890	ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
		891	ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
		892	if (INTEL_INFO(dev)->gen >= 8) {
		893	ering->faddr \|= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
		894	ering->bbaddr \|= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
		895	}
		896	ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
4126	Serge	897	} else {
5060	serge	898	ering->faddr = I915_READ(DMA_FADD_I8XX);
		899	ering->ipeir = I915_READ(IPEIR);
		900	ering->ipehr = I915_READ(IPEHR);
6084	serge	901	ering->instdone = I915_READ(GEN2_INSTDONE);
4126	Serge	902	}
		903
5060	serge	904	ering->waiting = waitqueue_active(&ring->irq_queue);
		905	ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
		906	ering->seqno = ring->get_seqno(ring, false);
		907	ering->acthd = intel_ring_get_active_head(ring);
6084	serge	908	ering->start = I915_READ_START(ring);
5060	serge	909	ering->head = I915_READ_HEAD(ring);
		910	ering->tail = I915_READ_TAIL(ring);
		911	ering->ctl = I915_READ_CTL(ring);
4126	Serge	912
5060	serge	913	if (I915_NEED_GFX_HWS(dev)) {
6937	serge	914	i915_reg_t mmio;
4560	Serge	915
5060	serge	916	if (IS_GEN7(dev)) {
		917	switch (ring->id) {
		918	default:
		919	case RCS:
		920	mmio = RENDER_HWS_PGA_GEN7;
		921	break;
		922	case BCS:
		923	mmio = BLT_HWS_PGA_GEN7;
		924	break;
		925	case VCS:
		926	mmio = BSD_HWS_PGA_GEN7;
		927	break;
		928	case VECS:
		929	mmio = VEBOX_HWS_PGA_GEN7;
		930	break;
		931	}
		932	} else if (IS_GEN6(ring->dev)) {
		933	mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
		934	} else {
		935	/* XXX: gen8 returns to sanity */
		936	mmio = RING_HWS_PGA(ring->mmio_base);
		937	}
		938
		939	ering->hws = I915_READ(mmio);
		940	}
		941
		942	ering->hangcheck_score = ring->hangcheck.score;
		943	ering->hangcheck_action = ring->hangcheck.action;
		944
		945	if (USES_PPGTT(dev)) {
		946	int i;
		947
		948	ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
		949
6084	serge	950	if (IS_GEN6(dev))
		951	ering->vm_info.pp_dir_base =
		952	I915_READ(RING_PP_DIR_BASE_READ(ring));
		953	else if (IS_GEN7(dev))
		954	ering->vm_info.pp_dir_base =
		955	I915_READ(RING_PP_DIR_BASE(ring));
		956	else if (INTEL_INFO(dev)->gen >= 8)
5060	serge	957	for (i = 0; i < 4; i++) {
		958	ering->vm_info.pdp[i] =
		959	I915_READ(GEN8_RING_PDP_UDW(ring, i));
		960	ering->vm_info.pdp[i] <<= 32;
		961	ering->vm_info.pdp[i] \|=
		962	I915_READ(GEN8_RING_PDP_LDW(ring, i));
		963	}
		964	}
4126	Serge	965	}
		966
		967
5060	serge	968	static void i915_gem_record_active_context(struct intel_engine_cs *ring,
4126	Serge	969	struct drm_i915_error_state *error,
		970	struct drm_i915_error_ring *ering)
		971	{
		972	struct drm_i915_private *dev_priv = ring->dev->dev_private;
		973	struct drm_i915_gem_object *obj;
		974
		975	/* Currently render ring is the only HW context user */
		976	if (ring->id != RCS \|\| !error->ccid)
		977	return;
		978
		979	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6084	serge	980	if (!i915_gem_obj_ggtt_bound(obj))
		981	continue;
		982
4126	Serge	983	if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
5060	serge	984	ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
4126	Serge	985	break;
		986	}
		987	}
		988	}
		989
		990	static void i915_gem_record_rings(struct drm_device *dev,
		991	struct drm_i915_error_state *error)
		992	{
		993	struct drm_i915_private *dev_priv = dev->dev_private;
		994	struct drm_i915_gem_request *request;
		995	int i, count;
		996
4560	Serge	997	for (i = 0; i < I915_NUM_RINGS; i++) {
5060	serge	998	struct intel_engine_cs *ring = &dev_priv->ring[i];
6084	serge	999	struct intel_ringbuffer *rbuf;
4560	Serge	1000
5060	serge	1001	error->ring[i].pid = -1;
		1002
4560	Serge	1003	if (ring->dev == NULL)
		1004	continue;
		1005
		1006	error->ring[i].valid = true;
		1007
6084	serge	1008	i915_record_ring_state(dev, error, ring, &error->ring[i]);
4126	Serge	1009
5060	serge	1010	request = i915_gem_find_active_request(ring);
		1011	if (request) {
6084	serge	1012	struct i915_address_space *vm;
		1013
		1014	vm = request->ctx && request->ctx->ppgtt ?
		1015	&request->ctx->ppgtt->base :
		1016	&dev_priv->gtt.base;
		1017
5060	serge	1018	/* We need to copy these to an anonymous buffer
		1019	* as the simplest method to avoid being overwritten
		1020	* by userspace.
		1021	*/
6084	serge	1022	error->ring[i].batchbuffer =
5060	serge	1023	i915_error_object_create(dev_priv,
		1024	request->batch_obj,
6084	serge	1025	vm);
4126	Serge	1026
6084	serge	1027	if (HAS_BROKEN_CS_TLB(dev_priv->dev))
5060	serge	1028	error->ring[i].wa_batchbuffer =
		1029	i915_error_ggtt_object_create(dev_priv,
		1030	ring->scratch.obj);
		1031
6084	serge	1032	if (request->pid) {
5060	serge	1033	struct task_struct *task;
		1034
		1035	rcu_read_lock();
6084	serge	1036	task = pid_task(request->pid, PIDTYPE_PID);
5060	serge	1037	if (task) {
		1038	strcpy(error->ring[i].comm, task->comm);
		1039	error->ring[i].pid = task->pid;
		1040	}
		1041	rcu_read_unlock();
		1042	}
		1043	}
		1044
6084	serge	1045	if (i915.enable_execlists) {
		1046	/* TODO: This is only a small fix to keep basic error
		1047	* capture working, but we need to add more information
		1048	* for it to be useful (e.g. dump the context being
		1049	* executed).
		1050	*/
		1051	if (request)
		1052	rbuf = request->ctx->engine[ring->id].ringbuf;
		1053	else
		1054	rbuf = ring->default_context->engine[ring->id].ringbuf;
		1055	} else
		1056	rbuf = ring->buffer;
		1057
		1058	error->ring[i].cpu_ring_head = rbuf->head;
		1059	error->ring[i].cpu_ring_tail = rbuf->tail;
		1060
4126	Serge	1061	error->ring[i].ringbuffer =
6084	serge	1062	i915_error_ggtt_object_create(dev_priv, rbuf->obj);
4126	Serge	1063
6084	serge	1064	error->ring[i].hws_page =
		1065	i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
4126	Serge	1066
		1067	i915_gem_record_active_context(ring, error, &error->ring[i]);
		1068
		1069	count = 0;
		1070	list_for_each_entry(request, &ring->request_list, list)
		1071	count++;
		1072
		1073	error->ring[i].num_requests = count;
		1074	error->ring[i].requests =
4560	Serge	1075	kcalloc(count, sizeof(*error->ring[i].requests),
4126	Serge	1076	GFP_ATOMIC);
		1077	if (error->ring[i].requests == NULL) {
		1078	error->ring[i].num_requests = 0;
		1079	continue;
		1080	}
		1081
		1082	count = 0;
		1083	list_for_each_entry(request, &ring->request_list, list) {
		1084	struct drm_i915_error_request *erq;
		1085
6937	serge	1086	if (count >= error->ring[i].num_requests) {
		1087	/*
		1088	* If the ring request list was changed in
		1089	* between the point where the error request
		1090	* list was created and dimensioned and this
		1091	* point then just exit early to avoid crashes.
		1092	*
		1093	* We don't need to communicate that the
		1094	* request list changed state during error
		1095	* state capture and that the error state is
		1096	* slightly incorrect as a consequence since we
		1097	* are typically only interested in the request
		1098	* list state at the point of error state
		1099	* capture, not in any changes happening during
		1100	* the capture.
		1101	*/
		1102	break;
		1103	}
		1104
4126	Serge	1105	erq = &error->ring[i].requests[count++];
		1106	erq->seqno = request->seqno;
		1107	erq->jiffies = request->emitted_jiffies;
6084	serge	1108	erq->tail = request->postfix;
4126	Serge	1109	}
		1110	}
		1111	}
		1112
		1113	/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
		1114	* VM.
		1115	*/
		1116	static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
		1117	struct drm_i915_error_state *error,
		1118	struct i915_address_space *vm,
		1119	const int ndx)
		1120	{
		1121	struct drm_i915_error_buffer active_bo = NULL, pinned_bo = NULL;
		1122	struct drm_i915_gem_object *obj;
		1123	struct i915_vma *vma;
		1124	int i;
		1125
		1126	i = 0;
		1127	list_for_each_entry(vma, &vm->active_list, mm_list)
		1128	i++;
		1129	error->active_bo_count[ndx] = i;
6084	serge	1130
		1131	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
		1132	list_for_each_entry(vma, &obj->vma_list, vma_link)
		1133	if (vma->vm == vm && vma->pin_count > 0)
		1134	i++;
		1135	}
4126	Serge	1136	error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
		1137
		1138	if (i) {
4560	Serge	1139	active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
4126	Serge	1140	if (active_bo)
		1141	pinned_bo = active_bo + error->active_bo_count[ndx];
		1142	}
		1143
		1144	if (active_bo)
		1145	error->active_bo_count[ndx] =
		1146	capture_active_bo(active_bo,
		1147	error->active_bo_count[ndx],
		1148	&vm->active_list);
		1149
		1150	if (pinned_bo)
		1151	error->pinned_bo_count[ndx] =
		1152	capture_pinned_bo(pinned_bo,
		1153	error->pinned_bo_count[ndx],
6084	serge	1154	&dev_priv->mm.bound_list, vm);
4126	Serge	1155	error->active_bo[ndx] = active_bo;
		1156	error->pinned_bo[ndx] = pinned_bo;
		1157	}
		1158
		1159	static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
		1160	struct drm_i915_error_state *error)
		1161	{
		1162	struct i915_address_space *vm;
		1163	int cnt = 0, i = 0;
		1164
		1165	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		1166	cnt++;
		1167
		1168	error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
		1169	error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
		1170	error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
		1171	GFP_ATOMIC);
		1172	error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
		1173	GFP_ATOMIC);
		1174
6084	serge	1175	if (error->active_bo == NULL \|\|
		1176	error->pinned_bo == NULL \|\|
		1177	error->active_bo_count == NULL \|\|
		1178	error->pinned_bo_count == NULL) {
		1179	kfree(error->active_bo);
		1180	kfree(error->active_bo_count);
		1181	kfree(error->pinned_bo);
		1182	kfree(error->pinned_bo_count);
		1183
		1184	error->active_bo = NULL;
		1185	error->active_bo_count = NULL;
		1186	error->pinned_bo = NULL;
		1187	error->pinned_bo_count = NULL;
		1188	} else {
		1189	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		1190	i915_gem_capture_vm(dev_priv, error, vm, i++);
		1191
		1192	error->vm_count = cnt;
		1193	}
4126	Serge	1194	}
		1195
5060	serge	1196	/* Capture all registers which don't fit into another category. */
		1197	static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
		1198	struct drm_i915_error_state *error)
		1199	{
		1200	struct drm_device *dev = dev_priv->dev;
6084	serge	1201	int i;
5060	serge	1202
		1203	/* General organization
		1204	* 1. Registers specific to a single generation
		1205	* 2. Registers which belong to multiple generations
		1206	* 3. Feature specific registers.
		1207	* 4. Everything else
		1208	* Please try to follow the order.
		1209	*/
		1210
		1211	/* 1: Registers specific to a single generation */
		1212	if (IS_VALLEYVIEW(dev)) {
6084	serge	1213	error->gtier[0] = I915_READ(GTIER);
		1214	error->ier = I915_READ(VLV_IER);
6937	serge	1215	error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
5060	serge	1216	}
		1217
		1218	if (IS_GEN7(dev))
		1219	error->err_int = I915_READ(GEN7_ERR_INT);
		1220
6084	serge	1221	if (INTEL_INFO(dev)->gen >= 8) {
		1222	error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		1223	error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
		1224	}
		1225
5060	serge	1226	if (IS_GEN6(dev)) {
6937	serge	1227	error->forcewake = I915_READ_FW(FORCEWAKE);
5060	serge	1228	error->gab_ctl = I915_READ(GAB_CTL);
		1229	error->gfx_mode = I915_READ(GFX_MODE);
		1230	}
		1231
		1232	/* 2: Registers which belong to multiple generations */
		1233	if (INTEL_INFO(dev)->gen >= 7)
6937	serge	1234	error->forcewake = I915_READ_FW(FORCEWAKE_MT);
5060	serge	1235
		1236	if (INTEL_INFO(dev)->gen >= 6) {
		1237	error->derrmr = I915_READ(DERRMR);
		1238	error->error = I915_READ(ERROR_GEN6);
		1239	error->done_reg = I915_READ(DONE_REG);
		1240	}
		1241
		1242	/* 3: Feature specific registers */
		1243	if (IS_GEN6(dev) \|\| IS_GEN7(dev)) {
		1244	error->gam_ecochk = I915_READ(GAM_ECOCHK);
		1245	error->gac_eco = I915_READ(GAC_ECO_BITS);
		1246	}
		1247
		1248	/* 4: Everything else */
		1249	if (HAS_HW_CONTEXTS(dev))
		1250	error->ccid = I915_READ(CCID);
		1251
6084	serge	1252	if (INTEL_INFO(dev)->gen >= 8) {
		1253	error->ier = I915_READ(GEN8_DE_MISC_IER);
		1254	for (i = 0; i < 4; i++)
		1255	error->gtier[i] = I915_READ(GEN8_GT_IER(i));
		1256	} else if (HAS_PCH_SPLIT(dev)) {
		1257	error->ier = I915_READ(DEIER);
		1258	error->gtier[0] = I915_READ(GTIER);
		1259	} else if (IS_GEN2(dev)) {
		1260	error->ier = I915_READ16(IER);
		1261	} else if (!IS_VALLEYVIEW(dev)) {
5060	serge	1262	error->ier = I915_READ(IER);
		1263	}
		1264	error->eir = I915_READ(EIR);
		1265	error->pgtbl_er = I915_READ(PGTBL_ER);
		1266
		1267	i915_get_extra_instdone(dev, error->extra_instdone);
		1268	}
		1269
		1270	static void i915_error_capture_msg(struct drm_device *dev,
		1271	struct drm_i915_error_state *error,
		1272	bool wedged,
		1273	const char *error_msg)
		1274	{
		1275	struct drm_i915_private *dev_priv = dev->dev_private;
		1276	u32 ecode;
		1277	int ring_id = -1, len;
		1278
		1279	ecode = i915_error_generate_code(dev_priv, error, &ring_id);
		1280
		1281	len = scnprintf(error->error_msg, sizeof(error->error_msg),
6084	serge	1282	"GPU HANG: ecode %d:%d:0x%08x",
		1283	INTEL_INFO(dev)->gen, ring_id, ecode);
5060	serge	1284
		1285	if (ring_id != -1 && error->ring[ring_id].pid != -1)
		1286	len += scnprintf(error->error_msg + len,
		1287	sizeof(error->error_msg) - len,
		1288	", in %s [%d]",
		1289	error->ring[ring_id].comm,
		1290	error->ring[ring_id].pid);
		1291
		1292	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		1293	", reason: %s, action: %s",
		1294	error_msg,
		1295	wedged ? "reset" : "continue");
		1296	}
		1297
		1298	static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
		1299	struct drm_i915_error_state *error)
		1300	{
6084	serge	1301	error->iommu = -1;
		1302	#ifdef CONFIG_INTEL_IOMMU
		1303	error->iommu = intel_iommu_gfx_mapped;
		1304	#endif
5060	serge	1305	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
		1306	error->suspend_count = dev_priv->suspend_count;
		1307	}
		1308
4126	Serge	1309	/**
		1310	* i915_capture_error_state - capture an error record for later analysis
		1311	* @dev: drm device
		1312	*
		1313	* Should be called when an error is detected (either a hang or an error
		1314	* interrupt) to capture error state from the time of the error. Fills
		1315	* out a structure which becomes available in debugfs for user level tools
		1316	* to pick up.
		1317	*/
5060	serge	1318	void i915_capture_error_state(struct drm_device *dev, bool wedged,
		1319	const char *error_msg)
4126	Serge	1320	{
5060	serge	1321	static bool warned;
4126	Serge	1322	struct drm_i915_private *dev_priv = dev->dev_private;
		1323	struct drm_i915_error_state *error;
		1324	unsigned long flags;
		1325
		1326	/* Account for pipe specific data like PIPESTAT /
		1327	error = kzalloc(sizeof(*error), GFP_ATOMIC);
		1328	if (!error) {
		1329	DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		1330	return;
		1331	}
		1332
		1333	kref_init(&error->ref);
		1334
5060	serge	1335	i915_capture_gen_state(dev_priv, error);
		1336	i915_capture_reg_state(dev_priv, error);
4126	Serge	1337	i915_gem_capture_buffers(dev_priv, error);
		1338	i915_gem_record_fences(dev, error);
		1339	i915_gem_record_rings(dev, error);
		1340
		1341	do_gettimeofday(&error->time);
		1342
		1343	error->overlay = intel_overlay_capture_error_state(dev);
		1344	error->display = intel_display_capture_error_state(dev);
		1345
5060	serge	1346	i915_error_capture_msg(dev, error, wedged, error_msg);
		1347	DRM_INFO("%s\n", error->error_msg);
		1348
4126	Serge	1349	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
		1350	if (dev_priv->gpu_error.first_error == NULL) {
		1351	dev_priv->gpu_error.first_error = error;
		1352	error = NULL;
		1353	}
		1354	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
		1355
5060	serge	1356	if (error) {
4126	Serge	1357	i915_error_state_free(&error->ref);
5060	serge	1358	return;
		1359	}
		1360
		1361	if (!warned) {
		1362	DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		1363	DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		1364	DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		1365	DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
		1366	DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
		1367	warned = true;
		1368	}
4126	Serge	1369	}
		1370
		1371	void i915_error_state_get(struct drm_device *dev,
		1372	struct i915_error_state_file_priv *error_priv)
		1373	{
		1374	struct drm_i915_private *dev_priv = dev->dev_private;
		1375
6084	serge	1376	spin_lock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1377	error_priv->error = dev_priv->gpu_error.first_error;
		1378	if (error_priv->error)
		1379	kref_get(&error_priv->error->ref);
6084	serge	1380	spin_unlock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1381
		1382	}
		1383
		1384	void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
		1385	{
		1386	if (error_priv->error)
		1387	kref_put(&error_priv->error->ref, i915_error_state_free);
		1388	}
		1389
		1390	void i915_destroy_error_state(struct drm_device *dev)
		1391	{
		1392	struct drm_i915_private *dev_priv = dev->dev_private;
		1393	struct drm_i915_error_state *error;
		1394
6084	serge	1395	spin_lock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1396	error = dev_priv->gpu_error.first_error;
		1397	dev_priv->gpu_error.first_error = NULL;
6084	serge	1398	spin_unlock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1399
		1400	if (error)
		1401	kref_put(&error->ref, i915_error_state_free);
		1402	}
6084	serge	1403	#endif
4126	Serge	1404
6084	serge	1405	const char i915_cache_level_str(struct drm_i915_private i915, int type)
4126	Serge	1406	{
		1407	switch (type) {
		1408	case I915_CACHE_NONE: return " uncached";
6084	serge	1409	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
4126	Serge	1410	case I915_CACHE_L3_LLC: return " L3+LLC";
4560	Serge	1411	case I915_CACHE_WT: return " WT";
4126	Serge	1412	default: return "";
		1413	}
		1414	}
		1415
		1416	/* NB: please notice the memset */
		1417	void i915_get_extra_instdone(struct drm_device dev, uint32_t instdone)
		1418	{
		1419	struct drm_i915_private *dev_priv = dev->dev_private;
		1420	memset(instdone, 0, sizeof(instdone) I915_NUM_INSTDONE_REG);
		1421
6084	serge	1422	if (IS_GEN2(dev) \|\| IS_GEN3(dev))
		1423	instdone[0] = I915_READ(GEN2_INSTDONE);
		1424	else if (IS_GEN4(dev) \|\| IS_GEN5(dev) \|\| IS_GEN6(dev)) {
		1425	instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
		1426	instdone[1] = I915_READ(GEN4_INSTDONE1);
		1427	} else if (INTEL_INFO(dev)->gen >= 7) {
		1428	instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
4126	Serge	1429	instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		1430	instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		1431	instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
		1432	}
		1433	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gpu_error.c – Rev 6937