WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_gpu_error.c

Rev	Author	Line No.	Line
4126	Serge	1	/*
		2	* Copyright (c) 2008 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	* Keith Packard
		26	* Mika Kuoppala
		27	*
		28	*/
		29
		30	#include "i915_drv.h"
		31
		32	#if 0
		33
		34	static const char *ring_str(int ring)
		35	{
		36	switch (ring) {
		37	case RCS: return "render";
		38	case VCS: return "bsd";
		39	case BCS: return "blt";
		40	case VECS: return "vebox";
5060	serge	41	case VCS2: return "bsd2";
4126	Serge	42	default: return "";
		43	}
		44	}
		45
		46	static const char *pin_flag(int pinned)
		47	{
		48	if (pinned > 0)
		49	return " P";
		50	else if (pinned < 0)
		51	return " p";
		52	else
		53	return "";
		54	}
		55
		56	static const char *tiling_flag(int tiling)
		57	{
		58	switch (tiling) {
		59	default:
		60	case I915_TILING_NONE: return "";
		61	case I915_TILING_X: return " X";
		62	case I915_TILING_Y: return " Y";
		63	}
		64	}
		65
		66	static const char *dirty_flag(int dirty)
		67	{
		68	return dirty ? " dirty" : "";
		69	}
		70
		71	static const char *purgeable_flag(int purgeable)
		72	{
		73	return purgeable ? " purgeable" : "";
		74	}
		75
		76	static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
		77	{
		78
		79	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		80	e->err = -ENOSPC;
		81	return false;
		82	}
		83
		84	if (e->bytes == e->size - 1 \|\| e->err)
		85	return false;
		86
		87	return true;
		88	}
		89
		90	static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
		91	unsigned len)
		92	{
		93	if (e->pos + len <= e->start) {
		94	e->pos += len;
		95	return false;
		96	}
		97
		98	/* First vsnprintf needs to fit in its entirety for memmove */
		99	if (len >= e->size) {
		100	e->err = -EIO;
		101	return false;
		102	}
		103
		104	return true;
		105	}
		106
		107	static void __i915_error_advance(struct drm_i915_error_state_buf *e,
		108	unsigned len)
		109	{
		110	/* If this is first printf in this window, adjust it so that
		111	* start position matches start of the buffer
		112	*/
		113
		114	if (e->pos < e->start) {
		115	const size_t off = e->start - e->pos;
		116
		117	/* Should not happen but be paranoid */
		118	if (off > len \|\| e->bytes) {
		119	e->err = -EIO;
		120	return;
		121	}
		122
		123	memmove(e->buf, e->buf + off, len - off);
		124	e->bytes = len - off;
		125	e->pos = e->start;
		126	return;
		127	}
		128
		129	e->bytes += len;
		130	e->pos += len;
		131	}
		132
		133	static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
		134	const char *f, va_list args)
		135	{
		136	unsigned len;
		137
		138	if (!__i915_error_ok(e))
		139	return;
		140
		141	/* Seek the first printf which is hits start position */
		142	if (e->pos < e->start) {
		143	va_list tmp;
		144
		145	va_copy(tmp, args);
5060	serge	146	len = vsnprintf(NULL, 0, f, tmp);
		147	va_end(tmp);
		148
		149	if (!__i915_error_seek(e, len))
4126	Serge	150	return;
		151	}
		152
		153	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
		154	if (len >= e->size - e->bytes)
		155	len = e->size - e->bytes - 1;
		156
		157	__i915_error_advance(e, len);
		158	}
		159
		160	static void i915_error_puts(struct drm_i915_error_state_buf *e,
		161	const char *str)
		162	{
		163	unsigned len;
		164
		165	if (!__i915_error_ok(e))
		166	return;
		167
		168	len = strlen(str);
		169
		170	/* Seek the first printf which is hits start position */
		171	if (e->pos < e->start) {
		172	if (!__i915_error_seek(e, len))
		173	return;
		174	}
		175
		176	if (len >= e->size - e->bytes)
		177	len = e->size - e->bytes - 1;
		178	memcpy(e->buf + e->bytes, str, len);
		179
		180	__i915_error_advance(e, len);
		181	}
		182
		183	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		184	#define err_puts(e, s) i915_error_puts(e, s)
		185
		186	static void print_error_buffers(struct drm_i915_error_state_buf *m,
		187	const char *name,
		188	struct drm_i915_error_buffer *err,
		189	int count)
		190	{
6084	serge	191	int i;
		192
5354	serge	193	err_printf(m, " %s [%d]:\n", name, count);
4126	Serge	194
		195	while (count--) {
6084	serge	196	err_printf(m, " %08x_%08x %8u %02x %02x [ ",
		197	upper_32_bits(err->gtt_offset),
		198	lower_32_bits(err->gtt_offset),
4126	Serge	199	err->size,
		200	err->read_domains,
6084	serge	201	err->write_domain);
		202	for (i = 0; i < I915_NUM_RINGS; i++)
		203	err_printf(m, "%02x ", err->rseqno[i]);
		204
		205	err_printf(m, "] %02x", err->wseqno);
4126	Serge	206	err_puts(m, pin_flag(err->pinned));
		207	err_puts(m, tiling_flag(err->tiling));
		208	err_puts(m, dirty_flag(err->dirty));
		209	err_puts(m, purgeable_flag(err->purgeable));
5060	serge	210	err_puts(m, err->userptr ? " userptr" : "");
4126	Serge	211	err_puts(m, err->ring != -1 ? " " : "");
		212	err_puts(m, ring_str(err->ring));
5354	serge	213	err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
4126	Serge	214
		215	if (err->name)
		216	err_printf(m, " (name: %d)", err->name);
		217	if (err->fence_reg != I915_FENCE_REG_NONE)
		218	err_printf(m, " (fence: %d)", err->fence_reg);
		219
		220	err_puts(m, "\n");
		221	err++;
		222	}
		223	}
		224
4560	Serge	225	static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
		226	{
		227	switch (a) {
		228	case HANGCHECK_IDLE:
		229	return "idle";
		230	case HANGCHECK_WAIT:
		231	return "wait";
		232	case HANGCHECK_ACTIVE:
		233	return "active";
5354	serge	234	case HANGCHECK_ACTIVE_LOOP:
		235	return "active (loop)";
4560	Serge	236	case HANGCHECK_KICK:
		237	return "kick";
		238	case HANGCHECK_HUNG:
		239	return "hung";
		240	}
		241
		242	return "unknown";
		243	}
		244
4126	Serge	245	static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
		246	struct drm_device *dev,
6084	serge	247	struct drm_i915_error_state *error,
		248	int ring_idx)
4126	Serge	249	{
6084	serge	250	struct drm_i915_error_ring *ring = &error->ring[ring_idx];
		251
5060	serge	252	if (!ring->valid)
4560	Serge	253	return;
		254
6084	serge	255	err_printf(m, "%s command stream:\n", ring_str(ring_idx));
		256	err_printf(m, " START: 0x%08x\n", ring->start);
		257	err_printf(m, " HEAD: 0x%08x\n", ring->head);
		258	err_printf(m, " TAIL: 0x%08x\n", ring->tail);
		259	err_printf(m, " CTL: 0x%08x\n", ring->ctl);
		260	err_printf(m, " HWS: 0x%08x\n", ring->hws);
5060	serge	261	err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
		262	err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
		263	err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
		264	err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
4560	Serge	265	if (INTEL_INFO(dev)->gen >= 4) {
5060	serge	266	err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
		267	err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
		268	err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
4560	Serge	269	}
5060	serge	270	err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
		271	err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
		272	lower_32_bits(ring->faddr));
4126	Serge	273	if (INTEL_INFO(dev)->gen >= 6) {
5060	serge	274	err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
		275	err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
4126	Serge	276	err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
5060	serge	277	ring->semaphore_mboxes[0],
		278	ring->semaphore_seqno[0]);
4126	Serge	279	err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
5060	serge	280	ring->semaphore_mboxes[1],
		281	ring->semaphore_seqno[1]);
4126	Serge	282	if (HAS_VEBOX(dev)) {
		283	err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
5060	serge	284	ring->semaphore_mboxes[2],
		285	ring->semaphore_seqno[2]);
4126	Serge	286	}
		287	}
5060	serge	288	if (USES_PPGTT(dev)) {
		289	err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
		290
		291	if (INTEL_INFO(dev)->gen >= 8) {
		292	int i;
		293	for (i = 0; i < 4; i++)
		294	err_printf(m, " PDP%d: 0x%016llx\n",
		295	i, ring->vm_info.pdp[i]);
		296	} else {
		297	err_printf(m, " PP_DIR_BASE: 0x%08x\n",
		298	ring->vm_info.pp_dir_base);
		299	}
		300	}
		301	err_printf(m, " seqno: 0x%08x\n", ring->seqno);
		302	err_printf(m, " waiting: %s\n", yesno(ring->waiting));
		303	err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
		304	err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
4560	Serge	305	err_printf(m, " hangcheck: %s [%d]\n",
5060	serge	306	hangcheck_action_to_str(ring->hangcheck_action),
		307	ring->hangcheck_score);
4126	Serge	308	}
		309
		310	void i915_error_printf(struct drm_i915_error_state_buf e, const char f, ...)
		311	{
		312	va_list args;
		313
		314	va_start(args, f);
		315	i915_error_vprintf(e, f, args);
		316	va_end(args);
		317	}
		318
5060	serge	319	static void print_error_obj(struct drm_i915_error_state_buf *m,
		320	struct drm_i915_error_object *obj)
		321	{
		322	int page, offset, elt;
		323
		324	for (page = offset = 0; page < obj->page_count; page++) {
		325	for (elt = 0; elt < PAGE_SIZE/4; elt++) {
		326	err_printf(m, "%08x : %08x\n", offset,
		327	obj->pages[page][elt]);
		328	offset += 4;
		329	}
		330	}
		331	}
		332
4126	Serge	333	int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
		334	const struct i915_error_state_file_priv *error_priv)
		335	{
		336	struct drm_device *dev = error_priv->dev;
5060	serge	337	struct drm_i915_private *dev_priv = dev->dev_private;
4126	Serge	338	struct drm_i915_error_state *error = error_priv->error;
6084	serge	339	struct drm_i915_error_object *obj;
5060	serge	340	int i, j, offset, elt;
		341	int max_hangcheck_score;
4126	Serge	342
		343	if (!error) {
		344	err_printf(m, "no error state collected\n");
		345	goto out;
		346	}
		347
5060	serge	348	err_printf(m, "%s\n", error->error_msg);
4126	Serge	349	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		350	error->time.tv_usec);
		351	err_printf(m, "Kernel: " UTS_RELEASE "\n");
5060	serge	352	max_hangcheck_score = 0;
		353	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		354	if (error->ring[i].hangcheck_score > max_hangcheck_score)
		355	max_hangcheck_score = error->ring[i].hangcheck_score;
		356	}
		357	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		358	if (error->ring[i].hangcheck_score == max_hangcheck_score &&
		359	error->ring[i].pid != -1) {
		360	err_printf(m, "Active process (on ring %s): %s [%d]\n",
		361	ring_str(i),
		362	error->ring[i].comm,
		363	error->ring[i].pid);
		364	}
		365	}
		366	err_printf(m, "Reset count: %u\n", error->reset_count);
		367	err_printf(m, "Suspend count: %u\n", error->suspend_count);
4560	Serge	368	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
6084	serge	369	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
4126	Serge	370	err_printf(m, "EIR: 0x%08x\n", error->eir);
		371	err_printf(m, "IER: 0x%08x\n", error->ier);
6084	serge	372	if (INTEL_INFO(dev)->gen >= 8) {
		373	for (i = 0; i < 4; i++)
		374	err_printf(m, "GTIER gt %d: 0x%08x\n", i,
		375	error->gtier[i]);
		376	} else if (HAS_PCH_SPLIT(dev) \|\| IS_VALLEYVIEW(dev))
		377	err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
4126	Serge	378	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
		379	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
		380	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
		381	err_printf(m, "CCID: 0x%08x\n", error->ccid);
4560	Serge	382	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
4126	Serge	383
		384	for (i = 0; i < dev_priv->num_fence_regs; i++)
		385	err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
		386
		387	for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
		388	err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
		389	error->extra_instdone[i]);
		390
		391	if (INTEL_INFO(dev)->gen >= 6) {
		392	err_printf(m, "ERROR: 0x%08x\n", error->error);
6084	serge	393
		394	if (INTEL_INFO(dev)->gen >= 8)
		395	err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
		396	error->fault_data1, error->fault_data0);
		397
4126	Serge	398	err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
		399	}
		400
		401	if (INTEL_INFO(dev)->gen == 7)
		402	err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
		403
6084	serge	404	for (i = 0; i < ARRAY_SIZE(error->ring); i++)
		405	i915_ring_error_state(m, dev, error, i);
4126	Serge	406
6084	serge	407	for (i = 0; i < error->vm_count; i++) {
		408	err_printf(m, "vm[%d]\n", i);
		409
4126	Serge	410	print_error_buffers(m, "Active",
6084	serge	411	error->active_bo[i],
		412	error->active_bo_count[i]);
4126	Serge	413
		414	print_error_buffers(m, "Pinned",
6084	serge	415	error->pinned_bo[i],
		416	error->pinned_bo_count[i]);
		417	}
4126	Serge	418
		419	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
5060	serge	420	obj = error->ring[i].batchbuffer;
		421	if (obj) {
		422	err_puts(m, dev_priv->ring[i].name);
		423	if (error->ring[i].pid != -1)
		424	err_printf(m, " (submitted by %s [%d])",
		425	error->ring[i].comm,
		426	error->ring[i].pid);
6084	serge	427	err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
		428	upper_32_bits(obj->gtt_offset),
		429	lower_32_bits(obj->gtt_offset));
5060	serge	430	print_error_obj(m, obj);
6084	serge	431	}
5060	serge	432
		433	obj = error->ring[i].wa_batchbuffer;
		434	if (obj) {
		435	err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
6084	serge	436	dev_priv->ring[i].name,
		437	lower_32_bits(obj->gtt_offset));
5060	serge	438	print_error_obj(m, obj);
4126	Serge	439	}
		440
		441	if (error->ring[i].num_requests) {
		442	err_printf(m, "%s --- %d requests\n",
		443	dev_priv->ring[i].name,
		444	error->ring[i].num_requests);
		445	for (j = 0; j < error->ring[i].num_requests; j++) {
		446	err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
		447	error->ring[i].requests[j].seqno,
		448	error->ring[i].requests[j].jiffies,
		449	error->ring[i].requests[j].tail);
		450	}
		451	}
		452
		453	if ((obj = error->ring[i].ringbuffer)) {
		454	err_printf(m, "%s --- ringbuffer = 0x%08x\n",
		455	dev_priv->ring[i].name,
6084	serge	456	lower_32_bits(obj->gtt_offset));
5060	serge	457	print_error_obj(m, obj);
4126	Serge	458	}
		459
5060	serge	460	if ((obj = error->ring[i].hws_page)) {
6084	serge	461	u64 hws_offset = obj->gtt_offset;
		462	u32 *hws_page = &obj->pages[0][0];
		463
		464	if (i915.enable_execlists) {
		465	hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
		466	hws_page = &obj->pages[LRC_PPHWSP_PN][0];
		467	}
		468	err_printf(m, "%s --- HW Status = 0x%08llx\n",
		469	dev_priv->ring[i].name, hws_offset);
4126	Serge	470	offset = 0;
		471	for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
		472	err_printf(m, "[%04x] %08x %08x %08x %08x\n",
6084	serge	473	offset,
		474	hws_page[elt],
		475	hws_page[elt+1],
		476	hws_page[elt+2],
		477	hws_page[elt+3]);
4126	Serge	478	offset += 16;
		479	}
		480	}
		481
5060	serge	482	if ((obj = error->ring[i].ctx)) {
		483	err_printf(m, "%s --- HW Context = 0x%08x\n",
		484	dev_priv->ring[i].name,
6084	serge	485	lower_32_bits(obj->gtt_offset));
5060	serge	486	print_error_obj(m, obj);
		487	}
6084	serge	488	}
5060	serge	489
6084	serge	490	if ((obj = error->semaphore_obj)) {
		491	err_printf(m, "Semaphore page = 0x%08x\n",
		492	lower_32_bits(obj->gtt_offset));
		493	for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
		494	err_printf(m, "[%04x] %08x %08x %08x %08x\n",
		495	elt * 4,
		496	obj->pages[0][elt],
		497	obj->pages[0][elt+1],
		498	obj->pages[0][elt+2],
		499	obj->pages[0][elt+3]);
		500	}
		501	}
		502
4126	Serge	503	if (error->overlay)
		504	intel_overlay_print_error_state(m, error->overlay);
		505
		506	if (error->display)
		507	intel_display_print_error_state(m, dev, error->display);
		508
		509	out:
		510	if (m->bytes == 0 && m->err)
		511	return m->err;
		512
		513	return 0;
		514	}
		515
		516	int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
6084	serge	517	struct drm_i915_private *i915,
4126	Serge	518	size_t count, loff_t pos)
		519	{
		520	memset(ebuf, 0, sizeof(*ebuf));
6084	serge	521	ebuf->i915 = i915;
4126	Serge	522
		523	/* We need to have enough room to store any i915_error_state printf
		524	* so that we can move it to start position.
		525	*/
		526	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
		527	ebuf->buf = kmalloc(ebuf->size,
		528	GFP_TEMPORARY \| __GFP_NORETRY \| __GFP_NOWARN);
		529
		530	if (ebuf->buf == NULL) {
		531	ebuf->size = PAGE_SIZE;
		532	ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
		533	}
		534
		535	if (ebuf->buf == NULL) {
		536	ebuf->size = 128;
		537	ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
		538	}
		539
		540	if (ebuf->buf == NULL)
		541	return -ENOMEM;
		542
		543	ebuf->start = pos;
		544
		545	return 0;
		546	}
		547
		548	static void i915_error_object_free(struct drm_i915_error_object *obj)
		549	{
		550	int page;
		551
		552	if (obj == NULL)
		553	return;
		554
		555	for (page = 0; page < obj->page_count; page++)
		556	kfree(obj->pages[page]);
		557
		558	kfree(obj);
		559	}
		560
		561	static void i915_error_state_free(struct kref *error_ref)
		562	{
		563	struct drm_i915_error_state *error = container_of(error_ref,
		564	typeof(*error), ref);
		565	int i;
		566
		567	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		568	i915_error_object_free(error->ring[i].batchbuffer);
6084	serge	569	i915_error_object_free(error->ring[i].wa_batchbuffer);
4126	Serge	570	i915_error_object_free(error->ring[i].ringbuffer);
5060	serge	571	i915_error_object_free(error->ring[i].hws_page);
4126	Serge	572	i915_error_object_free(error->ring[i].ctx);
		573	kfree(error->ring[i].requests);
		574	}
		575
6084	serge	576	i915_error_object_free(error->semaphore_obj);
		577
		578	for (i = 0; i < error->vm_count; i++)
		579	kfree(error->active_bo[i]);
		580
4126	Serge	581	kfree(error->active_bo);
6084	serge	582	kfree(error->active_bo_count);
		583	kfree(error->pinned_bo);
		584	kfree(error->pinned_bo_count);
4126	Serge	585	kfree(error->overlay);
		586	kfree(error->display);
		587	kfree(error);
		588	}
		589
		590	static struct drm_i915_error_object *
6084	serge	591	i915_error_object_create(struct drm_i915_private *dev_priv,
		592	struct drm_i915_gem_object *src,
		593	struct i915_address_space *vm)
4126	Serge	594	{
		595	struct drm_i915_error_object *dst;
6084	serge	596	struct i915_vma *vma = NULL;
		597	int num_pages;
		598	bool use_ggtt;
		599	int i = 0;
		600	u64 reloc_offset;
4126	Serge	601
		602	if (src == NULL \|\| src->pages == NULL)
		603	return NULL;
		604
6084	serge	605	num_pages = src->base.size >> PAGE_SHIFT;
		606
4126	Serge	607	dst = kmalloc(sizeof(dst) + num_pages sizeof(u32 *), GFP_ATOMIC);
		608	if (dst == NULL)
		609	return NULL;
		610
6084	serge	611	if (i915_gem_obj_bound(src, vm))
		612	dst->gtt_offset = i915_gem_obj_offset(src, vm);
		613	else
		614	dst->gtt_offset = -1;
		615
		616	reloc_offset = dst->gtt_offset;
		617	if (i915_is_ggtt(vm))
		618	vma = i915_gem_obj_to_ggtt(src);
		619	use_ggtt = (src->cache_level == I915_CACHE_NONE &&
		620	vma && (vma->bound & GLOBAL_BIND) &&
		621	reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
		622
		623	/* Cannot access stolen address directly, try to use the aperture */
		624	if (src->stolen) {
		625	use_ggtt = true;
		626
		627	if (!(vma && vma->bound & GLOBAL_BIND))
		628	goto unwind;
		629
		630	reloc_offset = i915_gem_obj_ggtt_offset(src);
		631	if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
		632	goto unwind;
		633	}
		634
		635	/* Cannot access snooped pages through the aperture */
		636	if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
		637	goto unwind;
		638
		639	dst->page_count = num_pages;
		640	while (num_pages--) {
4126	Serge	641	unsigned long flags;
		642	void *d;
		643
		644	d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
		645	if (d == NULL)
		646	goto unwind;
		647
		648	local_irq_save(flags);
6084	serge	649	if (use_ggtt) {
4126	Serge	650	void __iomem *s;
		651
		652	/* Simply ignore tiling or any overlapping fence.
		653	* It's part of the error state, and this hopefully
		654	* captures what the GPU read.
		655	*/
		656
		657	s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
		658	reloc_offset);
		659	memcpy_fromio(d, s, PAGE_SIZE);
		660	io_mapping_unmap_atomic(s);
		661	} else {
		662	struct page *page;
		663	void *s;
		664
		665	page = i915_gem_object_get_page(src, i);
		666
		667	drm_clflush_pages(&page, 1);
		668
		669	s = kmap_atomic(page);
		670	memcpy(d, s, PAGE_SIZE);
		671	kunmap_atomic(s);
		672
		673	drm_clflush_pages(&page, 1);
		674	}
		675	local_irq_restore(flags);
		676
6084	serge	677	dst->pages[i++] = d;
4126	Serge	678	reloc_offset += PAGE_SIZE;
		679	}
		680
		681	return dst;
		682
		683	unwind:
		684	while (i--)
		685	kfree(dst->pages[i]);
		686	kfree(dst);
		687	return NULL;
		688	}
5060	serge	689	#define i915_error_ggtt_object_create(dev_priv, src) \
6084	serge	690	i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
5060	serge	691
4126	Serge	692	static void capture_bo(struct drm_i915_error_buffer *err,
6084	serge	693	struct i915_vma *vma)
4126	Serge	694	{
6084	serge	695	struct drm_i915_gem_object *obj = vma->obj;
		696	int i;
		697
4126	Serge	698	err->size = obj->base.size;
		699	err->name = obj->base.name;
6084	serge	700	for (i = 0; i < I915_NUM_RINGS; i++)
		701	err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
		702	err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
		703	err->gtt_offset = vma->node.start;
4126	Serge	704	err->read_domains = obj->base.read_domains;
		705	err->write_domain = obj->base.write_domain;
		706	err->fence_reg = obj->fence_reg;
		707	err->pinned = 0;
5060	serge	708	if (i915_gem_obj_is_pinned(obj))
4126	Serge	709	err->pinned = 1;
		710	err->tiling = obj->tiling_mode;
		711	err->dirty = obj->dirty;
		712	err->purgeable = obj->madv != I915_MADV_WILLNEED;
5060	serge	713	err->userptr = obj->userptr.mm != NULL;
6084	serge	714	err->ring = obj->last_write_req ?
		715	i915_gem_request_get_ring(obj->last_write_req)->id : -1;
4126	Serge	716	err->cache_level = obj->cache_level;
		717	}
		718
		719	static u32 capture_active_bo(struct drm_i915_error_buffer *err,
		720	int count, struct list_head *head)
		721	{
		722	struct i915_vma *vma;
		723	int i = 0;
		724
		725	list_for_each_entry(vma, head, mm_list) {
6084	serge	726	capture_bo(err++, vma);
4126	Serge	727	if (++i == count)
		728	break;
		729	}
		730
		731	return i;
		732	}
		733
		734	static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
6084	serge	735	int count, struct list_head *head,
		736	struct i915_address_space *vm)
4126	Serge	737	{
		738	struct drm_i915_gem_object *obj;
6084	serge	739	struct drm_i915_error_buffer * const first = err;
		740	struct drm_i915_error_buffer * const last = err + count;
4126	Serge	741
		742	list_for_each_entry(obj, head, global_list) {
6084	serge	743	struct i915_vma *vma;
4126	Serge	744
6084	serge	745	if (err == last)
4126	Serge	746	break;
6084	serge	747
		748	list_for_each_entry(vma, &obj->vma_list, vma_link)
		749	if (vma->vm == vm && vma->pin_count > 0)
		750	capture_bo(err++, vma);
4126	Serge	751	}
		752
6084	serge	753	return err - first;
4126	Serge	754	}
		755
5060	serge	756	/* Generate a semi-unique error code. The code is not meant to have meaning, The
		757	* code's only purpose is to try to prevent false duplicated bug reports by
		758	* grossly estimating a GPU error state.
		759	*
		760	* TODO Ideally, hashing the batchbuffer would be a very nice way to determine
		761	* the hang if we could strip the GTT offset information from it.
		762	*
		763	* It's only a small step better than a random number in its current form.
		764	*/
		765	static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
		766	struct drm_i915_error_state *error,
		767	int *ring_id)
		768	{
		769	uint32_t error_code = 0;
		770	int i;
		771
		772	/* IPEHR would be an ideal way to detect errors, as it's the gross
		773	* measure of "the command that hung." However, has some very common
		774	* synchronization commands which almost always appear in the case
		775	* strictly a client bug. Use instdone to differentiate those some.
		776	*/
		777	for (i = 0; i < I915_NUM_RINGS; i++) {
		778	if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
		779	if (ring_id)
		780	*ring_id = i;
		781
		782	return error->ring[i].ipehr ^ error->ring[i].instdone;
		783	}
		784	}
		785
		786	return error_code;
		787	}
		788
4126	Serge	789	static void i915_gem_record_fences(struct drm_device *dev,
		790	struct drm_i915_error_state *error)
		791	{
		792	struct drm_i915_private *dev_priv = dev->dev_private;
		793	int i;
		794
6084	serge	795	if (IS_GEN3(dev) \|\| IS_GEN2(dev)) {
4126	Serge	796	for (i = 0; i < dev_priv->num_fence_regs; i++)
6084	serge	797	error->fence[i] = I915_READ(FENCE_REG(i));
		798	} else if (IS_GEN5(dev) \|\| IS_GEN4(dev)) {
		799	for (i = 0; i < dev_priv->num_fence_regs; i++)
		800	error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
		801	} else if (INTEL_INFO(dev)->gen >= 6) {
		802	for (i = 0; i < dev_priv->num_fence_regs; i++)
		803	error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
		804	}
		805	}
4126	Serge	806
6084	serge	807
		808	static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
		809	struct drm_i915_error_state *error,
		810	struct intel_engine_cs *ring,
		811	struct drm_i915_error_ring *ering)
		812	{
		813	struct intel_engine_cs *to;
		814	int i;
		815
		816	if (!i915_semaphore_is_enabled(dev_priv->dev))
		817	return;
		818
		819	if (!error->semaphore_obj)
		820	error->semaphore_obj =
		821	i915_error_ggtt_object_create(dev_priv,
		822	dev_priv->semaphore_obj);
		823
		824	for_each_ring(to, dev_priv, i) {
		825	int idx;
		826	u16 signal_offset;
		827	u32 *tmp;
		828
		829	if (ring == to)
		830	continue;
		831
		832	signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
		833	/ 4;
		834	tmp = error->semaphore_obj->pages[0];
		835	idx = intel_ring_sync_index(ring, to);
		836
		837	ering->semaphore_mboxes[idx] = tmp[signal_offset];
		838	ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
4126	Serge	839	}
		840	}
		841
6084	serge	842	static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
		843	struct intel_engine_cs *ring,
		844	struct drm_i915_error_ring *ering)
		845	{
		846	ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
		847	ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
		848	ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
		849	ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
		850
		851	if (HAS_VEBOX(dev_priv->dev)) {
		852	ering->semaphore_mboxes[2] =
		853	I915_READ(RING_SYNC_2(ring->mmio_base));
		854	ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
		855	}
		856	}
		857
4126	Serge	858	static void i915_record_ring_state(struct drm_device *dev,
6084	serge	859	struct drm_i915_error_state *error,
5060	serge	860	struct intel_engine_cs *ring,
		861	struct drm_i915_error_ring *ering)
4126	Serge	862	{
		863	struct drm_i915_private *dev_priv = dev->dev_private;
		864
		865	if (INTEL_INFO(dev)->gen >= 6) {
5060	serge	866	ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
		867	ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
6084	serge	868	if (INTEL_INFO(dev)->gen >= 8)
		869	gen8_record_semaphore_state(dev_priv, error, ring, ering);
		870	else
		871	gen6_record_semaphore_state(dev_priv, ring, ering);
4126	Serge	872	}
		873
		874	if (INTEL_INFO(dev)->gen >= 4) {
5060	serge	875	ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
		876	ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
		877	ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
		878	ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
		879	ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
		880	ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
		881	if (INTEL_INFO(dev)->gen >= 8) {
		882	ering->faddr \|= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
		883	ering->bbaddr \|= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
		884	}
		885	ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
4126	Serge	886	} else {
5060	serge	887	ering->faddr = I915_READ(DMA_FADD_I8XX);
		888	ering->ipeir = I915_READ(IPEIR);
		889	ering->ipehr = I915_READ(IPEHR);
6084	serge	890	ering->instdone = I915_READ(GEN2_INSTDONE);
4126	Serge	891	}
		892
5060	serge	893	ering->waiting = waitqueue_active(&ring->irq_queue);
		894	ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
		895	ering->seqno = ring->get_seqno(ring, false);
		896	ering->acthd = intel_ring_get_active_head(ring);
6084	serge	897	ering->start = I915_READ_START(ring);
5060	serge	898	ering->head = I915_READ_HEAD(ring);
		899	ering->tail = I915_READ_TAIL(ring);
		900	ering->ctl = I915_READ_CTL(ring);
4126	Serge	901
5060	serge	902	if (I915_NEED_GFX_HWS(dev)) {
		903	int mmio;
4560	Serge	904
5060	serge	905	if (IS_GEN7(dev)) {
		906	switch (ring->id) {
		907	default:
		908	case RCS:
		909	mmio = RENDER_HWS_PGA_GEN7;
		910	break;
		911	case BCS:
		912	mmio = BLT_HWS_PGA_GEN7;
		913	break;
		914	case VCS:
		915	mmio = BSD_HWS_PGA_GEN7;
		916	break;
		917	case VECS:
		918	mmio = VEBOX_HWS_PGA_GEN7;
		919	break;
		920	}
		921	} else if (IS_GEN6(ring->dev)) {
		922	mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
		923	} else {
		924	/* XXX: gen8 returns to sanity */
		925	mmio = RING_HWS_PGA(ring->mmio_base);
		926	}
		927
		928	ering->hws = I915_READ(mmio);
		929	}
		930
		931	ering->hangcheck_score = ring->hangcheck.score;
		932	ering->hangcheck_action = ring->hangcheck.action;
		933
		934	if (USES_PPGTT(dev)) {
		935	int i;
		936
		937	ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
		938
6084	serge	939	if (IS_GEN6(dev))
		940	ering->vm_info.pp_dir_base =
		941	I915_READ(RING_PP_DIR_BASE_READ(ring));
		942	else if (IS_GEN7(dev))
		943	ering->vm_info.pp_dir_base =
		944	I915_READ(RING_PP_DIR_BASE(ring));
		945	else if (INTEL_INFO(dev)->gen >= 8)
5060	serge	946	for (i = 0; i < 4; i++) {
		947	ering->vm_info.pdp[i] =
		948	I915_READ(GEN8_RING_PDP_UDW(ring, i));
		949	ering->vm_info.pdp[i] <<= 32;
		950	ering->vm_info.pdp[i] \|=
		951	I915_READ(GEN8_RING_PDP_LDW(ring, i));
		952	}
		953	}
4126	Serge	954	}
		955
		956
5060	serge	957	static void i915_gem_record_active_context(struct intel_engine_cs *ring,
4126	Serge	958	struct drm_i915_error_state *error,
		959	struct drm_i915_error_ring *ering)
		960	{
		961	struct drm_i915_private *dev_priv = ring->dev->dev_private;
		962	struct drm_i915_gem_object *obj;
		963
		964	/* Currently render ring is the only HW context user */
		965	if (ring->id != RCS \|\| !error->ccid)
		966	return;
		967
		968	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6084	serge	969	if (!i915_gem_obj_ggtt_bound(obj))
		970	continue;
		971
4126	Serge	972	if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
5060	serge	973	ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
4126	Serge	974	break;
		975	}
		976	}
		977	}
		978
		979	static void i915_gem_record_rings(struct drm_device *dev,
		980	struct drm_i915_error_state *error)
		981	{
		982	struct drm_i915_private *dev_priv = dev->dev_private;
		983	struct drm_i915_gem_request *request;
		984	int i, count;
		985
4560	Serge	986	for (i = 0; i < I915_NUM_RINGS; i++) {
5060	serge	987	struct intel_engine_cs *ring = &dev_priv->ring[i];
6084	serge	988	struct intel_ringbuffer *rbuf;
4560	Serge	989
5060	serge	990	error->ring[i].pid = -1;
		991
4560	Serge	992	if (ring->dev == NULL)
		993	continue;
		994
		995	error->ring[i].valid = true;
		996
6084	serge	997	i915_record_ring_state(dev, error, ring, &error->ring[i]);
4126	Serge	998
5060	serge	999	request = i915_gem_find_active_request(ring);
		1000	if (request) {
6084	serge	1001	struct i915_address_space *vm;
		1002
		1003	vm = request->ctx && request->ctx->ppgtt ?
		1004	&request->ctx->ppgtt->base :
		1005	&dev_priv->gtt.base;
		1006
5060	serge	1007	/* We need to copy these to an anonymous buffer
		1008	* as the simplest method to avoid being overwritten
		1009	* by userspace.
		1010	*/
6084	serge	1011	error->ring[i].batchbuffer =
5060	serge	1012	i915_error_object_create(dev_priv,
		1013	request->batch_obj,
6084	serge	1014	vm);
4126	Serge	1015
6084	serge	1016	if (HAS_BROKEN_CS_TLB(dev_priv->dev))
5060	serge	1017	error->ring[i].wa_batchbuffer =
		1018	i915_error_ggtt_object_create(dev_priv,
		1019	ring->scratch.obj);
		1020
6084	serge	1021	if (request->pid) {
5060	serge	1022	struct task_struct *task;
		1023
		1024	rcu_read_lock();
6084	serge	1025	task = pid_task(request->pid, PIDTYPE_PID);
5060	serge	1026	if (task) {
		1027	strcpy(error->ring[i].comm, task->comm);
		1028	error->ring[i].pid = task->pid;
		1029	}
		1030	rcu_read_unlock();
		1031	}
		1032	}
		1033
6084	serge	1034	if (i915.enable_execlists) {
		1035	/* TODO: This is only a small fix to keep basic error
		1036	* capture working, but we need to add more information
		1037	* for it to be useful (e.g. dump the context being
		1038	* executed).
		1039	*/
		1040	if (request)
		1041	rbuf = request->ctx->engine[ring->id].ringbuf;
		1042	else
		1043	rbuf = ring->default_context->engine[ring->id].ringbuf;
		1044	} else
		1045	rbuf = ring->buffer;
		1046
		1047	error->ring[i].cpu_ring_head = rbuf->head;
		1048	error->ring[i].cpu_ring_tail = rbuf->tail;
		1049
4126	Serge	1050	error->ring[i].ringbuffer =
6084	serge	1051	i915_error_ggtt_object_create(dev_priv, rbuf->obj);
4126	Serge	1052
6084	serge	1053	error->ring[i].hws_page =
		1054	i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
4126	Serge	1055
		1056	i915_gem_record_active_context(ring, error, &error->ring[i]);
		1057
		1058	count = 0;
		1059	list_for_each_entry(request, &ring->request_list, list)
		1060	count++;
		1061
		1062	error->ring[i].num_requests = count;
		1063	error->ring[i].requests =
4560	Serge	1064	kcalloc(count, sizeof(*error->ring[i].requests),
4126	Serge	1065	GFP_ATOMIC);
		1066	if (error->ring[i].requests == NULL) {
		1067	error->ring[i].num_requests = 0;
		1068	continue;
		1069	}
		1070
		1071	count = 0;
		1072	list_for_each_entry(request, &ring->request_list, list) {
		1073	struct drm_i915_error_request *erq;
		1074
		1075	erq = &error->ring[i].requests[count++];
		1076	erq->seqno = request->seqno;
		1077	erq->jiffies = request->emitted_jiffies;
6084	serge	1078	erq->tail = request->postfix;
4126	Serge	1079	}
		1080	}
		1081	}
		1082
		1083	/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
		1084	* VM.
		1085	*/
		1086	static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
		1087	struct drm_i915_error_state *error,
		1088	struct i915_address_space *vm,
		1089	const int ndx)
		1090	{
		1091	struct drm_i915_error_buffer active_bo = NULL, pinned_bo = NULL;
		1092	struct drm_i915_gem_object *obj;
		1093	struct i915_vma *vma;
		1094	int i;
		1095
		1096	i = 0;
		1097	list_for_each_entry(vma, &vm->active_list, mm_list)
		1098	i++;
		1099	error->active_bo_count[ndx] = i;
6084	serge	1100
		1101	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
		1102	list_for_each_entry(vma, &obj->vma_list, vma_link)
		1103	if (vma->vm == vm && vma->pin_count > 0)
		1104	i++;
		1105	}
4126	Serge	1106	error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
		1107
		1108	if (i) {
4560	Serge	1109	active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
4126	Serge	1110	if (active_bo)
		1111	pinned_bo = active_bo + error->active_bo_count[ndx];
		1112	}
		1113
		1114	if (active_bo)
		1115	error->active_bo_count[ndx] =
		1116	capture_active_bo(active_bo,
		1117	error->active_bo_count[ndx],
		1118	&vm->active_list);
		1119
		1120	if (pinned_bo)
		1121	error->pinned_bo_count[ndx] =
		1122	capture_pinned_bo(pinned_bo,
		1123	error->pinned_bo_count[ndx],
6084	serge	1124	&dev_priv->mm.bound_list, vm);
4126	Serge	1125	error->active_bo[ndx] = active_bo;
		1126	error->pinned_bo[ndx] = pinned_bo;
		1127	}
		1128
		1129	static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
		1130	struct drm_i915_error_state *error)
		1131	{
		1132	struct i915_address_space *vm;
		1133	int cnt = 0, i = 0;
		1134
		1135	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		1136	cnt++;
		1137
		1138	error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
		1139	error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
		1140	error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
		1141	GFP_ATOMIC);
		1142	error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
		1143	GFP_ATOMIC);
		1144
6084	serge	1145	if (error->active_bo == NULL \|\|
		1146	error->pinned_bo == NULL \|\|
		1147	error->active_bo_count == NULL \|\|
		1148	error->pinned_bo_count == NULL) {
		1149	kfree(error->active_bo);
		1150	kfree(error->active_bo_count);
		1151	kfree(error->pinned_bo);
		1152	kfree(error->pinned_bo_count);
		1153
		1154	error->active_bo = NULL;
		1155	error->active_bo_count = NULL;
		1156	error->pinned_bo = NULL;
		1157	error->pinned_bo_count = NULL;
		1158	} else {
		1159	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		1160	i915_gem_capture_vm(dev_priv, error, vm, i++);
		1161
		1162	error->vm_count = cnt;
		1163	}
4126	Serge	1164	}
		1165
5060	serge	1166	/* Capture all registers which don't fit into another category. */
		1167	static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
		1168	struct drm_i915_error_state *error)
		1169	{
		1170	struct drm_device *dev = dev_priv->dev;
6084	serge	1171	int i;
5060	serge	1172
		1173	/* General organization
		1174	* 1. Registers specific to a single generation
		1175	* 2. Registers which belong to multiple generations
		1176	* 3. Feature specific registers.
		1177	* 4. Everything else
		1178	* Please try to follow the order.
		1179	*/
		1180
		1181	/* 1: Registers specific to a single generation */
		1182	if (IS_VALLEYVIEW(dev)) {
6084	serge	1183	error->gtier[0] = I915_READ(GTIER);
		1184	error->ier = I915_READ(VLV_IER);
5060	serge	1185	error->forcewake = I915_READ(FORCEWAKE_VLV);
		1186	}
		1187
		1188	if (IS_GEN7(dev))
		1189	error->err_int = I915_READ(GEN7_ERR_INT);
		1190
6084	serge	1191	if (INTEL_INFO(dev)->gen >= 8) {
		1192	error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		1193	error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
		1194	}
		1195
5060	serge	1196	if (IS_GEN6(dev)) {
		1197	error->forcewake = I915_READ(FORCEWAKE);
		1198	error->gab_ctl = I915_READ(GAB_CTL);
		1199	error->gfx_mode = I915_READ(GFX_MODE);
		1200	}
		1201
		1202	/* 2: Registers which belong to multiple generations */
		1203	if (INTEL_INFO(dev)->gen >= 7)
		1204	error->forcewake = I915_READ(FORCEWAKE_MT);
		1205
		1206	if (INTEL_INFO(dev)->gen >= 6) {
		1207	error->derrmr = I915_READ(DERRMR);
		1208	error->error = I915_READ(ERROR_GEN6);
		1209	error->done_reg = I915_READ(DONE_REG);
		1210	}
		1211
		1212	/* 3: Feature specific registers */
		1213	if (IS_GEN6(dev) \|\| IS_GEN7(dev)) {
		1214	error->gam_ecochk = I915_READ(GAM_ECOCHK);
		1215	error->gac_eco = I915_READ(GAC_ECO_BITS);
		1216	}
		1217
		1218	/* 4: Everything else */
		1219	if (HAS_HW_CONTEXTS(dev))
		1220	error->ccid = I915_READ(CCID);
		1221
6084	serge	1222	if (INTEL_INFO(dev)->gen >= 8) {
		1223	error->ier = I915_READ(GEN8_DE_MISC_IER);
		1224	for (i = 0; i < 4; i++)
		1225	error->gtier[i] = I915_READ(GEN8_GT_IER(i));
		1226	} else if (HAS_PCH_SPLIT(dev)) {
		1227	error->ier = I915_READ(DEIER);
		1228	error->gtier[0] = I915_READ(GTIER);
		1229	} else if (IS_GEN2(dev)) {
		1230	error->ier = I915_READ16(IER);
		1231	} else if (!IS_VALLEYVIEW(dev)) {
5060	serge	1232	error->ier = I915_READ(IER);
		1233	}
		1234	error->eir = I915_READ(EIR);
		1235	error->pgtbl_er = I915_READ(PGTBL_ER);
		1236
		1237	i915_get_extra_instdone(dev, error->extra_instdone);
		1238	}
		1239
		1240	static void i915_error_capture_msg(struct drm_device *dev,
		1241	struct drm_i915_error_state *error,
		1242	bool wedged,
		1243	const char *error_msg)
		1244	{
		1245	struct drm_i915_private *dev_priv = dev->dev_private;
		1246	u32 ecode;
		1247	int ring_id = -1, len;
		1248
		1249	ecode = i915_error_generate_code(dev_priv, error, &ring_id);
		1250
		1251	len = scnprintf(error->error_msg, sizeof(error->error_msg),
6084	serge	1252	"GPU HANG: ecode %d:%d:0x%08x",
		1253	INTEL_INFO(dev)->gen, ring_id, ecode);
5060	serge	1254
		1255	if (ring_id != -1 && error->ring[ring_id].pid != -1)
		1256	len += scnprintf(error->error_msg + len,
		1257	sizeof(error->error_msg) - len,
		1258	", in %s [%d]",
		1259	error->ring[ring_id].comm,
		1260	error->ring[ring_id].pid);
		1261
		1262	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		1263	", reason: %s, action: %s",
		1264	error_msg,
		1265	wedged ? "reset" : "continue");
		1266	}
		1267
		1268	static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
		1269	struct drm_i915_error_state *error)
		1270	{
6084	serge	1271	error->iommu = -1;
		1272	#ifdef CONFIG_INTEL_IOMMU
		1273	error->iommu = intel_iommu_gfx_mapped;
		1274	#endif
5060	serge	1275	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
		1276	error->suspend_count = dev_priv->suspend_count;
		1277	}
		1278
4126	Serge	1279	/**
		1280	* i915_capture_error_state - capture an error record for later analysis
		1281	* @dev: drm device
		1282	*
		1283	* Should be called when an error is detected (either a hang or an error
		1284	* interrupt) to capture error state from the time of the error. Fills
		1285	* out a structure which becomes available in debugfs for user level tools
		1286	* to pick up.
		1287	*/
5060	serge	1288	void i915_capture_error_state(struct drm_device *dev, bool wedged,
		1289	const char *error_msg)
4126	Serge	1290	{
5060	serge	1291	static bool warned;
4126	Serge	1292	struct drm_i915_private *dev_priv = dev->dev_private;
		1293	struct drm_i915_error_state *error;
		1294	unsigned long flags;
		1295
		1296	/* Account for pipe specific data like PIPESTAT /
		1297	error = kzalloc(sizeof(*error), GFP_ATOMIC);
		1298	if (!error) {
		1299	DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		1300	return;
		1301	}
		1302
		1303	kref_init(&error->ref);
		1304
5060	serge	1305	i915_capture_gen_state(dev_priv, error);
		1306	i915_capture_reg_state(dev_priv, error);
4126	Serge	1307	i915_gem_capture_buffers(dev_priv, error);
		1308	i915_gem_record_fences(dev, error);
		1309	i915_gem_record_rings(dev, error);
		1310
		1311	do_gettimeofday(&error->time);
		1312
		1313	error->overlay = intel_overlay_capture_error_state(dev);
		1314	error->display = intel_display_capture_error_state(dev);
		1315
5060	serge	1316	i915_error_capture_msg(dev, error, wedged, error_msg);
		1317	DRM_INFO("%s\n", error->error_msg);
		1318
4126	Serge	1319	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
		1320	if (dev_priv->gpu_error.first_error == NULL) {
		1321	dev_priv->gpu_error.first_error = error;
		1322	error = NULL;
		1323	}
		1324	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
		1325
5060	serge	1326	if (error) {
4126	Serge	1327	i915_error_state_free(&error->ref);
5060	serge	1328	return;
		1329	}
		1330
		1331	if (!warned) {
		1332	DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		1333	DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		1334	DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		1335	DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
		1336	DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
		1337	warned = true;
		1338	}
4126	Serge	1339	}
		1340
		1341	void i915_error_state_get(struct drm_device *dev,
		1342	struct i915_error_state_file_priv *error_priv)
		1343	{
		1344	struct drm_i915_private *dev_priv = dev->dev_private;
		1345
6084	serge	1346	spin_lock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1347	error_priv->error = dev_priv->gpu_error.first_error;
		1348	if (error_priv->error)
		1349	kref_get(&error_priv->error->ref);
6084	serge	1350	spin_unlock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1351
		1352	}
		1353
		1354	void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
		1355	{
		1356	if (error_priv->error)
		1357	kref_put(&error_priv->error->ref, i915_error_state_free);
		1358	}
		1359
		1360	void i915_destroy_error_state(struct drm_device *dev)
		1361	{
		1362	struct drm_i915_private *dev_priv = dev->dev_private;
		1363	struct drm_i915_error_state *error;
		1364
6084	serge	1365	spin_lock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1366	error = dev_priv->gpu_error.first_error;
		1367	dev_priv->gpu_error.first_error = NULL;
6084	serge	1368	spin_unlock_irq(&dev_priv->gpu_error.lock);
4126	Serge	1369
		1370	if (error)
		1371	kref_put(&error->ref, i915_error_state_free);
		1372	}
6084	serge	1373	#endif
4126	Serge	1374
6084	serge	1375	const char i915_cache_level_str(struct drm_i915_private i915, int type)
4126	Serge	1376	{
		1377	switch (type) {
		1378	case I915_CACHE_NONE: return " uncached";
6084	serge	1379	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
4126	Serge	1380	case I915_CACHE_L3_LLC: return " L3+LLC";
4560	Serge	1381	case I915_CACHE_WT: return " WT";
4126	Serge	1382	default: return "";
		1383	}
		1384	}
		1385
		1386	/* NB: please notice the memset */
		1387	void i915_get_extra_instdone(struct drm_device dev, uint32_t instdone)
		1388	{
		1389	struct drm_i915_private *dev_priv = dev->dev_private;
		1390	memset(instdone, 0, sizeof(instdone) I915_NUM_INSTDONE_REG);
		1391
6084	serge	1392	if (IS_GEN2(dev) \|\| IS_GEN3(dev))
		1393	instdone[0] = I915_READ(GEN2_INSTDONE);
		1394	else if (IS_GEN4(dev) \|\| IS_GEN5(dev) \|\| IS_GEN6(dev)) {
		1395	instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
		1396	instdone[1] = I915_READ(GEN4_INSTDONE1);
		1397	} else if (INTEL_INFO(dev)->gen >= 7) {
		1398	instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
4126	Serge	1399	instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		1400	instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		1401	instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
		1402	}
		1403	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gpu_error.c – Rev 6084