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2326 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
3031 | serge | 28 | #include |
29 | #include |
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30 | #include |
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31 | #include |
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2326 | Serge | 32 | #include "i915_drv.h" |
33 | |||
6084 | serge | 34 | /** |
35 | * DOC: buffer object tiling |
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2326 | Serge | 36 | * |
6084 | serge | 37 | * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to |
38 | * declare fence register requirements. |
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2326 | Serge | 39 | * |
6084 | serge | 40 | * In principle GEM doesn't care at all about the internal data layout of an |
41 | * object, and hence it also doesn't care about tiling or swizzling. There's two |
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42 | * exceptions: |
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2326 | Serge | 43 | * |
6084 | serge | 44 | * - For X and Y tiling the hardware provides detilers for CPU access, so called |
45 | * fences. Since there's only a limited amount of them the kernel must manage |
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46 | * these, and therefore userspace must tell the kernel the object tiling if it |
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47 | * wants to use fences for detiling. |
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48 | * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which |
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49 | * depends upon the physical page frame number. When swapping such objects the |
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50 | * page frame number might change and the kernel must be able to fix this up |
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51 | * and hence now the tiling. Note that on a subset of platforms with |
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52 | * asymmetric memory channel population the swizzling pattern changes in an |
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53 | * unknown way, and for those the kernel simply forbids swapping completely. |
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2326 | Serge | 54 | * |
6084 | serge | 55 | * Since neither of this applies for new tiling layouts on modern platforms like |
56 | * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. |
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57 | * Anything else can be handled in userspace entirely without the kernel's |
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58 | * invovlement. |
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2326 | Serge | 59 | */ |
60 | |||
61 | /* Check pitch constriants for all chips & tiling formats */ |
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62 | static bool |
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63 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
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64 | { |
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65 | int tile_width; |
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66 | |||
67 | /* Linear is always fine */ |
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68 | if (tiling_mode == I915_TILING_NONE) |
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69 | return true; |
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70 | |||
71 | if (IS_GEN2(dev) || |
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72 | (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
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73 | tile_width = 128; |
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74 | else |
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75 | tile_width = 512; |
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76 | |||
77 | /* check maximum stride & object size */ |
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3746 | Serge | 78 | /* i965+ stores the end address of the gtt mapping in the fence |
6084 | serge | 79 | * reg, so dont bother to check the size */ |
3746 | Serge | 80 | if (INTEL_INFO(dev)->gen >= 7) { |
81 | if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) |
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82 | return false; |
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83 | } else if (INTEL_INFO(dev)->gen >= 4) { |
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2326 | Serge | 84 | if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) |
85 | return false; |
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86 | } else { |
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87 | if (stride > 8192) |
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88 | return false; |
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89 | |||
90 | if (IS_GEN3(dev)) { |
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91 | if (size > I830_FENCE_MAX_SIZE_VAL << 20) |
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92 | return false; |
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93 | } else { |
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94 | if (size > I830_FENCE_MAX_SIZE_VAL << 19) |
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95 | return false; |
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96 | } |
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97 | } |
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98 | |||
3746 | Serge | 99 | if (stride < tile_width) |
100 | return false; |
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101 | |||
2326 | Serge | 102 | /* 965+ just needs multiples of tile width */ |
103 | if (INTEL_INFO(dev)->gen >= 4) { |
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104 | if (stride & (tile_width - 1)) |
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105 | return false; |
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106 | return true; |
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107 | } |
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108 | |||
109 | /* Pre-965 needs power of two tile widths */ |
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110 | if (stride & (stride - 1)) |
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111 | return false; |
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112 | |||
113 | return true; |
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114 | } |
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115 | |||
116 | /* Is the current GTT allocation valid for the change in tiling? */ |
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117 | static bool |
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118 | i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) |
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119 | { |
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120 | u32 size; |
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121 | |||
122 | if (tiling_mode == I915_TILING_NONE) |
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123 | return true; |
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124 | |||
125 | if (INTEL_INFO(obj->base.dev)->gen >= 4) |
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126 | return true; |
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127 | |||
128 | if (INTEL_INFO(obj->base.dev)->gen == 3) { |
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4104 | Serge | 129 | if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) |
2326 | Serge | 130 | return false; |
131 | } else { |
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4104 | Serge | 132 | if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) |
2326 | Serge | 133 | return false; |
134 | } |
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135 | |||
3480 | Serge | 136 | size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); |
4104 | Serge | 137 | if (i915_gem_obj_ggtt_size(obj) != size) |
2326 | Serge | 138 | return false; |
139 | |||
4104 | Serge | 140 | if (i915_gem_obj_ggtt_offset(obj) & (size - 1)) |
2326 | Serge | 141 | return false; |
142 | |||
143 | return true; |
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144 | } |
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145 | |||
146 | /** |
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6084 | serge | 147 | * i915_gem_set_tiling - IOCTL handler to set tiling mode |
148 | * @dev: DRM device |
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149 | * @data: data pointer for the ioctl |
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150 | * @file: DRM file for the ioctl call |
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151 | * |
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2326 | Serge | 152 | * Sets the tiling mode of an object, returning the required swizzling of |
153 | * bit 6 of addresses in the object. |
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6084 | serge | 154 | * |
155 | * Called by the user via ioctl. |
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156 | * |
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157 | * Returns: |
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158 | * Zero on success, negative errno on failure. |
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2326 | Serge | 159 | */ |
160 | int |
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161 | i915_gem_set_tiling(struct drm_device *dev, void *data, |
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162 | struct drm_file *file) |
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163 | { |
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164 | struct drm_i915_gem_set_tiling *args = data; |
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5060 | serge | 165 | struct drm_i915_private *dev_priv = dev->dev_private; |
2326 | Serge | 166 | struct drm_i915_gem_object *obj; |
167 | int ret = 0; |
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168 | |||
169 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
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170 | if (&obj->base == NULL) |
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171 | return -ENOENT; |
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172 | |||
173 | if (!i915_tiling_ok(dev, |
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174 | args->stride, obj->base.size, args->tiling_mode)) { |
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175 | drm_gem_object_unreference_unlocked(&obj->base); |
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176 | return -EINVAL; |
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177 | } |
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178 | |||
6084 | serge | 179 | mutex_lock(&dev->struct_mutex); |
180 | if (obj->pin_display || obj->framebuffer_references) { |
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181 | ret = -EBUSY; |
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182 | goto err; |
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2326 | Serge | 183 | } |
184 | |||
185 | if (args->tiling_mode == I915_TILING_NONE) { |
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186 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
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187 | args->stride = 0; |
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188 | } else { |
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189 | if (args->tiling_mode == I915_TILING_X) |
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190 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
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191 | else |
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192 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
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193 | |||
194 | /* Hide bit 17 swizzling from the user. This prevents old Mesa |
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195 | * from aborting the application on sw fallbacks to bit 17, |
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196 | * and we use the pread/pwrite bit17 paths to swizzle for it. |
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197 | * If there was a user that was relying on the swizzle |
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198 | * information for drm_intel_bo_map()ed reads/writes this would |
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199 | * break it, but we don't have any of those. |
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200 | */ |
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201 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
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202 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
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203 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
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204 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
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205 | |||
206 | /* If we can't handle the swizzling, make it untiled. */ |
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207 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { |
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208 | args->tiling_mode = I915_TILING_NONE; |
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209 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
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210 | args->stride = 0; |
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211 | } |
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212 | } |
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213 | |||
214 | if (args->tiling_mode != obj->tiling_mode || |
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215 | args->stride != obj->stride) { |
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216 | /* We need to rebind the object if its current allocation |
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217 | * no longer meets the alignment restrictions for its new |
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218 | * tiling mode. Otherwise we can just leave it alone, but |
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3031 | serge | 219 | * need to ensure that any fence register is updated before |
220 | * the next fenced (either through the GTT or by the BLT unit |
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221 | * on older GPUs) access. |
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222 | * |
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223 | * After updating the tiling parameters, we then flag whether |
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224 | * we need to update an associated fence register. Note this |
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225 | * has to also include the unfenced register the GPU uses |
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226 | * whilst executing a fenced command for an untiled object. |
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2326 | Serge | 227 | */ |
5354 | serge | 228 | if (obj->map_and_fenceable && |
229 | !i915_gem_object_fence_ok(obj, args->tiling_mode)) |
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230 | ret = i915_gem_object_ggtt_unbind(obj); |
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2326 | Serge | 231 | |
5354 | serge | 232 | if (ret == 0) { |
233 | if (obj->pages && |
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234 | obj->madv == I915_MADV_WILLNEED && |
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235 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
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236 | if (args->tiling_mode == I915_TILING_NONE) |
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237 | i915_gem_object_unpin_pages(obj); |
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238 | if (obj->tiling_mode == I915_TILING_NONE) |
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239 | i915_gem_object_pin_pages(obj); |
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6084 | serge | 240 | } |
2326 | Serge | 241 | |
3031 | serge | 242 | obj->fence_dirty = |
6084 | serge | 243 | obj->last_fenced_req || |
3031 | serge | 244 | obj->fence_reg != I915_FENCE_REG_NONE; |
245 | |||
2326 | Serge | 246 | obj->tiling_mode = args->tiling_mode; |
247 | obj->stride = args->stride; |
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3031 | serge | 248 | |
249 | /* Force the fence to be reacquired for GTT access */ |
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250 | i915_gem_release_mmap(obj); |
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2326 | Serge | 251 | } |
252 | } |
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253 | /* we have to maintain this existing ABI... */ |
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254 | args->stride = obj->stride; |
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255 | args->tiling_mode = obj->tiling_mode; |
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3480 | Serge | 256 | |
257 | /* Try to preallocate memory required to save swizzling on put-pages */ |
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258 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
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259 | if (obj->bit_17 == NULL) { |
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4560 | Serge | 260 | obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT), |
3480 | Serge | 261 | sizeof(long), GFP_KERNEL); |
262 | } |
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263 | } else { |
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264 | kfree(obj->bit_17); |
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265 | obj->bit_17 = NULL; |
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266 | } |
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267 | |||
6084 | serge | 268 | err: |
2326 | Serge | 269 | drm_gem_object_unreference(&obj->base); |
270 | mutex_unlock(&dev->struct_mutex); |
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271 | |||
272 | return ret; |
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273 | } |
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274 | |||
275 | /** |
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6084 | serge | 276 | * i915_gem_get_tiling - IOCTL handler to get tiling mode |
277 | * @dev: DRM device |
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278 | * @data: data pointer for the ioctl |
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279 | * @file: DRM file for the ioctl call |
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280 | * |
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2326 | Serge | 281 | * Returns the current tiling mode and required bit 6 swizzling for the object. |
6084 | serge | 282 | * |
283 | * Called by the user via ioctl. |
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284 | * |
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285 | * Returns: |
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286 | * Zero on success, negative errno on failure. |
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2326 | Serge | 287 | */ |
288 | int |
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289 | i915_gem_get_tiling(struct drm_device *dev, void *data, |
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290 | struct drm_file *file) |
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291 | { |
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292 | struct drm_i915_gem_get_tiling *args = data; |
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5060 | serge | 293 | struct drm_i915_private *dev_priv = dev->dev_private; |
2326 | Serge | 294 | struct drm_i915_gem_object *obj; |
295 | |||
296 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
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297 | if (&obj->base == NULL) |
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298 | return -ENOENT; |
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299 | |||
300 | mutex_lock(&dev->struct_mutex); |
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301 | |||
302 | args->tiling_mode = obj->tiling_mode; |
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303 | switch (obj->tiling_mode) { |
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304 | case I915_TILING_X: |
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305 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
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306 | break; |
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307 | case I915_TILING_Y: |
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308 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
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309 | break; |
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310 | case I915_TILING_NONE: |
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311 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
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312 | break; |
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313 | default: |
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314 | DRM_ERROR("unknown tiling mode\n"); |
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315 | } |
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316 | |||
317 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
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6084 | serge | 318 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
319 | args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN; |
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320 | else |
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321 | args->phys_swizzle_mode = args->swizzle_mode; |
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2326 | Serge | 322 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
323 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
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324 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
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325 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
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326 | |||
327 | drm_gem_object_unreference(&obj->base); |
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328 | mutex_unlock(&dev->struct_mutex); |
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329 | |||
330 | return 0; |
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331 | }>><>><> |