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Rev | Author | Line No. | Line |
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2332 | Serge | 1 | /* |
2 | * Copyright © 2010 Daniel Vetter |
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5060 | serge | 3 | * Copyright © 2011-2014 Intel Corporation |
2332 | Serge | 4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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22 | * IN THE SOFTWARE. |
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23 | * |
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24 | */ |
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25 | |||
5354 | serge | 26 | #include |
3031 | serge | 27 | #include |
28 | #include |
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2332 | Serge | 29 | #include "i915_drv.h" |
2351 | Serge | 30 | #include "i915_trace.h" |
2332 | Serge | 31 | #include "intel_drv.h" |
32 | |||
5354 | serge | 33 | #include |
34 | |||
5060 | serge | 35 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
36 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); |
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3243 | Serge | 37 | |
5354 | serge | 38 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
5060 | serge | 39 | { |
5354 | serge | 40 | bool has_aliasing_ppgtt; |
41 | bool has_full_ppgtt; |
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3243 | Serge | 42 | |
5354 | serge | 43 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; |
44 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; |
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45 | if (IS_GEN8(dev)) |
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46 | has_full_ppgtt = false; /* XXX why? */ |
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3243 | Serge | 47 | |
5354 | serge | 48 | /* |
49 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for |
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50 | * execlists, the sole mechanism available to submit work. |
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51 | */ |
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52 | if (INTEL_INFO(dev)->gen < 9 && |
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53 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) |
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5060 | serge | 54 | return 0; |
4104 | Serge | 55 | |
5060 | serge | 56 | if (enable_ppgtt == 1) |
57 | return 1; |
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4560 | Serge | 58 | |
5354 | serge | 59 | if (enable_ppgtt == 2 && has_full_ppgtt) |
5060 | serge | 60 | return 2; |
4560 | Serge | 61 | |
5060 | serge | 62 | #ifdef CONFIG_INTEL_IOMMU |
63 | /* Disable ppgtt on SNB if VT-d is on. */ |
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64 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { |
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65 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
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66 | return 0; |
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67 | } |
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68 | #endif |
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69 | |||
70 | /* Early VLV doesn't have this */ |
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71 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
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72 | dev->pdev->revision < 0xb) { |
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73 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
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74 | return 0; |
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75 | } |
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76 | |||
5354 | serge | 77 | return has_aliasing_ppgtt ? 1 : 0; |
5060 | serge | 78 | } |
79 | |||
80 | |||
81 | static void ppgtt_bind_vma(struct i915_vma *vma, |
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82 | enum i915_cache_level cache_level, |
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83 | u32 flags); |
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84 | static void ppgtt_unbind_vma(struct i915_vma *vma); |
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85 | |||
4560 | Serge | 86 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
87 | enum i915_cache_level level, |
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88 | bool valid) |
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89 | { |
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5060 | serge | 90 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
4560 | Serge | 91 | pte |= addr; |
5060 | serge | 92 | |
93 | switch (level) { |
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94 | case I915_CACHE_NONE: |
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95 | pte |= PPAT_UNCACHED_INDEX; |
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96 | break; |
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97 | case I915_CACHE_WT: |
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98 | pte |= PPAT_DISPLAY_ELLC_INDEX; |
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99 | break; |
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100 | default: |
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4560 | Serge | 101 | pte |= PPAT_CACHED_INDEX; |
5060 | serge | 102 | break; |
103 | } |
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104 | |||
4560 | Serge | 105 | return pte; |
106 | } |
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107 | |||
108 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
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109 | dma_addr_t addr, |
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110 | enum i915_cache_level level) |
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111 | { |
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112 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
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113 | pde |= addr; |
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114 | if (level != I915_CACHE_NONE) |
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115 | pde |= PPAT_CACHED_PDE_INDEX; |
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116 | else |
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117 | pde |= PPAT_UNCACHED_INDEX; |
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118 | return pde; |
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119 | } |
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120 | |||
4104 | Serge | 121 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
4280 | Serge | 122 | enum i915_cache_level level, |
5060 | serge | 123 | bool valid, u32 unused) |
4104 | Serge | 124 | { |
4280 | Serge | 125 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4104 | Serge | 126 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
127 | |||
128 | switch (level) { |
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129 | case I915_CACHE_L3_LLC: |
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130 | case I915_CACHE_LLC: |
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131 | pte |= GEN6_PTE_CACHE_LLC; |
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132 | break; |
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133 | case I915_CACHE_NONE: |
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134 | pte |= GEN6_PTE_UNCACHED; |
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135 | break; |
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136 | default: |
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137 | WARN_ON(1); |
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138 | } |
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139 | |||
140 | return pte; |
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141 | } |
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142 | |||
143 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, |
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4280 | Serge | 144 | enum i915_cache_level level, |
5060 | serge | 145 | bool valid, u32 unused) |
3243 | Serge | 146 | { |
4280 | Serge | 147 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
3243 | Serge | 148 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
149 | |||
150 | switch (level) { |
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4104 | Serge | 151 | case I915_CACHE_L3_LLC: |
152 | pte |= GEN7_PTE_CACHE_L3_LLC; |
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3243 | Serge | 153 | break; |
154 | case I915_CACHE_LLC: |
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155 | pte |= GEN6_PTE_CACHE_LLC; |
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156 | break; |
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157 | case I915_CACHE_NONE: |
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158 | pte |= GEN6_PTE_UNCACHED; |
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159 | break; |
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160 | default: |
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4104 | Serge | 161 | WARN_ON(1); |
3243 | Serge | 162 | } |
163 | |||
164 | return pte; |
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165 | } |
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166 | |||
4104 | Serge | 167 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
4280 | Serge | 168 | enum i915_cache_level level, |
5060 | serge | 169 | bool valid, u32 flags) |
3746 | Serge | 170 | { |
4280 | Serge | 171 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4104 | Serge | 172 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
173 | |||
5060 | serge | 174 | if (!(flags & PTE_READ_ONLY)) |
4104 | Serge | 175 | pte |= BYT_PTE_WRITEABLE; |
176 | |||
177 | if (level != I915_CACHE_NONE) |
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178 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; |
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179 | |||
180 | return pte; |
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181 | } |
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182 | |||
183 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
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4280 | Serge | 184 | enum i915_cache_level level, |
5060 | serge | 185 | bool valid, u32 unused) |
4104 | Serge | 186 | { |
4280 | Serge | 187 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4104 | Serge | 188 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
189 | |||
190 | if (level != I915_CACHE_NONE) |
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191 | pte |= HSW_WB_LLC_AGE3; |
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192 | |||
193 | return pte; |
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194 | } |
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195 | |||
196 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
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4280 | Serge | 197 | enum i915_cache_level level, |
5060 | serge | 198 | bool valid, u32 unused) |
4104 | Serge | 199 | { |
4280 | Serge | 200 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4104 | Serge | 201 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
202 | |||
203 | switch (level) { |
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204 | case I915_CACHE_NONE: |
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205 | break; |
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206 | case I915_CACHE_WT: |
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4560 | Serge | 207 | pte |= HSW_WT_ELLC_LLC_AGE3; |
4104 | Serge | 208 | break; |
209 | default: |
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4560 | Serge | 210 | pte |= HSW_WB_ELLC_LLC_AGE3; |
4104 | Serge | 211 | break; |
212 | } |
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213 | |||
214 | return pte; |
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215 | } |
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216 | |||
4560 | Serge | 217 | /* Broadwell Page Directory Pointer Descriptors */ |
5060 | serge | 218 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
5354 | serge | 219 | uint64_t val) |
4560 | Serge | 220 | { |
221 | int ret; |
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222 | |||
223 | BUG_ON(entry >= 4); |
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224 | |||
225 | ret = intel_ring_begin(ring, 6); |
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226 | if (ret) |
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227 | return ret; |
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228 | |||
229 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
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230 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); |
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231 | intel_ring_emit(ring, (u32)(val >> 32)); |
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232 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
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233 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); |
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234 | intel_ring_emit(ring, (u32)(val)); |
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235 | intel_ring_advance(ring); |
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236 | |||
237 | return 0; |
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238 | } |
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239 | |||
5060 | serge | 240 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
5354 | serge | 241 | struct intel_engine_cs *ring) |
4560 | Serge | 242 | { |
5060 | serge | 243 | int i, ret; |
4560 | Serge | 244 | |
245 | /* bit of a hack to find the actual last used pd */ |
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246 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; |
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247 | |||
248 | for (i = used_pd - 1; i >= 0; i--) { |
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249 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; |
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5354 | serge | 250 | ret = gen8_write_pdp(ring, i, addr); |
4560 | Serge | 251 | if (ret) |
5060 | serge | 252 | return ret; |
4560 | Serge | 253 | } |
5060 | serge | 254 | |
4560 | Serge | 255 | return 0; |
256 | } |
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257 | |||
258 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
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5060 | serge | 259 | uint64_t start, |
260 | uint64_t length, |
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4560 | Serge | 261 | bool use_scratch) |
262 | { |
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263 | struct i915_hw_ppgtt *ppgtt = |
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264 | container_of(vm, struct i915_hw_ppgtt, base); |
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265 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; |
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5060 | serge | 266 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
267 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; |
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268 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; |
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269 | unsigned num_entries = length >> PAGE_SHIFT; |
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4560 | Serge | 270 | unsigned last_pte, i; |
271 | |||
272 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, |
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273 | I915_CACHE_LLC, use_scratch); |
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274 | |||
275 | while (num_entries) { |
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5060 | serge | 276 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
4560 | Serge | 277 | |
5060 | serge | 278 | last_pte = pte + num_entries; |
4560 | Serge | 279 | if (last_pte > GEN8_PTES_PER_PAGE) |
280 | last_pte = GEN8_PTES_PER_PAGE; |
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281 | |||
5354 | serge | 282 | pt_vaddr = kmap_atomic(page_table); |
4560 | Serge | 283 | |
5060 | serge | 284 | for (i = pte; i < last_pte; i++) { |
4560 | Serge | 285 | pt_vaddr[i] = scratch_pte; |
5060 | serge | 286 | num_entries--; |
287 | } |
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4560 | Serge | 288 | |
5060 | serge | 289 | if (!HAS_LLC(ppgtt->base.dev)) |
290 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); |
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5354 | serge | 291 | kunmap_atomic(pt_vaddr); |
5060 | serge | 292 | |
293 | pte = 0; |
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294 | if (++pde == GEN8_PDES_PER_PAGE) { |
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295 | pdpe++; |
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296 | pde = 0; |
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297 | } |
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4560 | Serge | 298 | } |
299 | } |
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300 | |||
301 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
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302 | struct sg_table *pages, |
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5060 | serge | 303 | uint64_t start, |
304 | enum i915_cache_level cache_level, u32 unused) |
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4560 | Serge | 305 | { |
306 | struct i915_hw_ppgtt *ppgtt = |
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307 | container_of(vm, struct i915_hw_ppgtt, base); |
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308 | gen8_gtt_pte_t *pt_vaddr; |
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5060 | serge | 309 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
310 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; |
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311 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; |
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4560 | Serge | 312 | struct sg_page_iter sg_iter; |
313 | |||
5354 | serge | 314 | pt_vaddr = NULL; |
4560 | Serge | 315 | |
316 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
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5060 | serge | 317 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
318 | break; |
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4560 | Serge | 319 | |
5354 | serge | 320 | if (pt_vaddr == NULL) |
321 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
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322 | |||
5060 | serge | 323 | pt_vaddr[pte] = |
4560 | Serge | 324 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
325 | cache_level, true); |
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5060 | serge | 326 | if (++pte == GEN8_PTES_PER_PAGE) { |
327 | if (!HAS_LLC(ppgtt->base.dev)) |
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328 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); |
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5354 | serge | 329 | kunmap_atomic(pt_vaddr); |
330 | pt_vaddr = NULL; |
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5060 | serge | 331 | if (++pde == GEN8_PDES_PER_PAGE) { |
332 | pdpe++; |
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333 | pde = 0; |
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334 | } |
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335 | pte = 0; |
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4560 | Serge | 336 | } |
337 | } |
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5354 | serge | 338 | if (pt_vaddr) { |
339 | if (!HAS_LLC(ppgtt->base.dev)) |
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340 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); |
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341 | kunmap_atomic(pt_vaddr); |
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342 | } |
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4560 | Serge | 343 | } |
344 | |||
5060 | serge | 345 | static void gen8_free_page_tables(struct page **pt_pages) |
4560 | Serge | 346 | { |
5060 | serge | 347 | int i; |
348 | |||
349 | if (pt_pages == NULL) |
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350 | return; |
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351 | |||
352 | // for (i = 0; i < GEN8_PDES_PER_PAGE; i++) |
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353 | // if (pt_pages[i]) |
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354 | // __free_pages(pt_pages[i], 0); |
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355 | } |
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356 | |||
357 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) |
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358 | { |
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359 | int i; |
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360 | |||
361 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
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362 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); |
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363 | kfree(ppgtt->gen8_pt_pages[i]); |
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364 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
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365 | } |
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366 | |||
367 | // __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
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368 | } |
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369 | |||
370 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
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371 | { |
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372 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
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4560 | Serge | 373 | int i, j; |
374 | |||
5060 | serge | 375 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
376 | /* TODO: In the future we'll support sparse mappings, so this |
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377 | * will have to change. */ |
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378 | if (!ppgtt->pd_dma_addr[i]) |
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379 | continue; |
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4560 | Serge | 380 | |
5060 | serge | 381 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
382 | PCI_DMA_BIDIRECTIONAL); |
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4560 | Serge | 383 | |
384 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
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385 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; |
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386 | if (addr) |
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5060 | serge | 387 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
4560 | Serge | 388 | PCI_DMA_BIDIRECTIONAL); |
5060 | serge | 389 | } |
390 | } |
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391 | } |
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4560 | Serge | 392 | |
5060 | serge | 393 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
394 | { |
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395 | struct i915_hw_ppgtt *ppgtt = |
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396 | container_of(vm, struct i915_hw_ppgtt, base); |
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397 | |||
398 | gen8_ppgtt_unmap_pages(ppgtt); |
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399 | gen8_ppgtt_free(ppgtt); |
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400 | } |
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401 | |||
402 | static struct page **__gen8_alloc_page_tables(void) |
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403 | { |
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404 | struct page **pt_pages; |
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405 | int i; |
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406 | |||
407 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); |
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408 | if (!pt_pages) |
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409 | return ERR_PTR(-ENOMEM); |
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410 | |||
411 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { |
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412 | pt_pages[i] = alloc_page(GFP_KERNEL); |
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413 | if (!pt_pages[i]) |
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414 | goto bail; |
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4560 | Serge | 415 | } |
5060 | serge | 416 | |
417 | return pt_pages; |
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418 | |||
419 | bail: |
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420 | gen8_free_page_tables(pt_pages); |
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421 | kfree(pt_pages); |
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422 | return ERR_PTR(-ENOMEM); |
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423 | } |
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424 | |||
425 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
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426 | const int max_pdp) |
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427 | { |
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428 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
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429 | int i, ret; |
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430 | |||
431 | for (i = 0; i < max_pdp; i++) { |
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432 | pt_pages[i] = __gen8_alloc_page_tables(); |
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433 | if (IS_ERR(pt_pages[i])) { |
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434 | ret = PTR_ERR(pt_pages[i]); |
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435 | goto unwind_out; |
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4560 | Serge | 436 | } |
437 | } |
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438 | |||
5060 | serge | 439 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, |
440 | * "atomic" - for cleanup purposes. |
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441 | */ |
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442 | for (i = 0; i < max_pdp; i++) |
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443 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; |
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444 | |||
445 | return 0; |
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446 | |||
447 | unwind_out: |
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448 | while (i--) { |
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449 | gen8_free_page_tables(pt_pages[i]); |
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450 | kfree(pt_pages[i]); |
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451 | } |
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452 | |||
453 | return ret; |
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4560 | Serge | 454 | } |
455 | |||
5060 | serge | 456 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) |
457 | { |
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458 | int i; |
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459 | |||
460 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
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461 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, |
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462 | sizeof(dma_addr_t), |
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463 | GFP_KERNEL); |
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464 | if (!ppgtt->gen8_pt_dma_addr[i]) |
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465 | return -ENOMEM; |
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466 | } |
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467 | |||
468 | return 0; |
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469 | } |
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470 | |||
471 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, |
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472 | const int max_pdp) |
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473 | { |
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474 | // ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); |
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475 | if (!ppgtt->pd_pages) |
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476 | return -ENOMEM; |
||
477 | |||
478 | // ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); |
||
479 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); |
||
480 | |||
481 | return 0; |
||
482 | } |
||
483 | |||
484 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, |
||
485 | const int max_pdp) |
||
486 | { |
||
487 | int ret; |
||
488 | |||
489 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); |
||
490 | if (ret) |
||
491 | return ret; |
||
492 | |||
493 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); |
||
494 | if (ret) { |
||
495 | // __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); |
||
496 | return ret; |
||
497 | } |
||
498 | |||
499 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; |
||
500 | |||
501 | ret = gen8_ppgtt_allocate_dma(ppgtt); |
||
502 | if (ret) |
||
503 | gen8_ppgtt_free(ppgtt); |
||
504 | |||
505 | return ret; |
||
506 | } |
||
507 | |||
508 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, |
||
509 | const int pd) |
||
510 | { |
||
511 | dma_addr_t pd_addr; |
||
512 | int ret; |
||
513 | |||
514 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, |
||
515 | &ppgtt->pd_pages[pd], 0, |
||
516 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
||
517 | |||
518 | // ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); |
||
519 | // if (ret) |
||
520 | // return ret; |
||
521 | |||
522 | ppgtt->pd_dma_addr[pd] = pd_addr; |
||
523 | |||
524 | return 0; |
||
525 | } |
||
526 | |||
527 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, |
||
528 | const int pd, |
||
529 | const int pt) |
||
530 | { |
||
531 | dma_addr_t pt_addr; |
||
532 | struct page *p; |
||
533 | int ret; |
||
534 | |||
535 | p = ppgtt->gen8_pt_pages[pd][pt]; |
||
536 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
||
537 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
||
538 | // ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); |
||
539 | // if (ret) |
||
540 | // return ret; |
||
541 | |||
542 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; |
||
543 | |||
544 | return 0; |
||
545 | } |
||
546 | |||
4560 | Serge | 547 | /** |
5060 | serge | 548 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
549 | * with a net effect resembling a 2-level page table in normal x86 terms. Each |
||
550 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address |
||
551 | * space. |
||
4560 | Serge | 552 | * |
5060 | serge | 553 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
554 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. |
||
4560 | Serge | 555 | * TODO: Do something with the size parameter |
5060 | serge | 556 | */ |
4560 | Serge | 557 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
558 | { |
||
559 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
||
5060 | serge | 560 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
561 | int i, j, ret; |
||
4560 | Serge | 562 | |
563 | if (size % (1<<30)) |
||
564 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); |
||
565 | |||
5060 | serge | 566 | /* 1. Do all our allocations for page directories and page tables. */ |
567 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); |
||
568 | if (ret) |
||
569 | return ret; |
||
4560 | Serge | 570 | |
571 | /* |
||
5060 | serge | 572 | * 2. Create DMA mappings for the page directories and page tables. |
4560 | Serge | 573 | */ |
574 | for (i = 0; i < max_pdp; i++) { |
||
5060 | serge | 575 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
576 | if (ret) |
||
577 | goto bail; |
||
4560 | Serge | 578 | |
579 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
||
5060 | serge | 580 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
581 | if (ret) |
||
582 | goto bail; |
||
4560 | Serge | 583 | } |
584 | } |
||
585 | |||
5060 | serge | 586 | /* |
587 | * 3. Map all the page directory entires to point to the page tables |
||
588 | * we've allocated. |
||
589 | * |
||
590 | * For now, the PPGTT helper functions all require that the PDEs are |
||
4560 | Serge | 591 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
5060 | serge | 592 | * will never need to touch the PDEs again. |
593 | */ |
||
4560 | Serge | 594 | for (i = 0; i < max_pdp; i++) { |
5354 | serge | 595 | gen8_ppgtt_pde_t *pd_vaddr; |
596 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); |
||
4560 | Serge | 597 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
598 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; |
||
599 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, |
||
600 | I915_CACHE_LLC); |
||
601 | } |
||
5060 | serge | 602 | if (!HAS_LLC(ppgtt->base.dev)) |
603 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); |
||
5354 | serge | 604 | kunmap_atomic(pd_vaddr); |
4560 | Serge | 605 | } |
606 | |||
5060 | serge | 607 | ppgtt->switch_mm = gen8_mm_switch; |
608 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
||
609 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
||
610 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
||
611 | ppgtt->base.start = 0; |
||
612 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
||
4560 | Serge | 613 | |
5060 | serge | 614 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
615 | |||
4560 | Serge | 616 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
617 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); |
||
618 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", |
||
5060 | serge | 619 | ppgtt->num_pd_entries, |
620 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); |
||
4560 | Serge | 621 | return 0; |
622 | |||
5060 | serge | 623 | bail: |
624 | gen8_ppgtt_unmap_pages(ppgtt); |
||
625 | gen8_ppgtt_free(ppgtt); |
||
4560 | Serge | 626 | return ret; |
627 | } |
||
628 | |||
4104 | Serge | 629 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
630 | { |
||
631 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
||
3746 | Serge | 632 | gen6_gtt_pte_t __iomem *pd_addr; |
633 | uint32_t pd_entry; |
||
634 | int i; |
||
635 | |||
4104 | Serge | 636 | WARN_ON(ppgtt->pd_offset & 0x3f); |
3746 | Serge | 637 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
638 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); |
||
639 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
||
640 | dma_addr_t pt_addr; |
||
641 | |||
642 | pt_addr = ppgtt->pt_dma_addr[i]; |
||
643 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
||
644 | pd_entry |= GEN6_PDE_VALID; |
||
645 | |||
646 | writel(pd_entry, pd_addr + i); |
||
647 | } |
||
648 | readl(pd_addr); |
||
4104 | Serge | 649 | } |
3746 | Serge | 650 | |
5060 | serge | 651 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
4104 | Serge | 652 | { |
653 | BUG_ON(ppgtt->pd_offset & 0x3f); |
||
654 | |||
5060 | serge | 655 | return (ppgtt->pd_offset / 64) << 16; |
656 | } |
||
4104 | Serge | 657 | |
5060 | serge | 658 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
5354 | serge | 659 | struct intel_engine_cs *ring) |
5060 | serge | 660 | { |
661 | int ret; |
||
3746 | Serge | 662 | |
5060 | serge | 663 | /* NB: TLBs must be flushed and invalidated before a switch */ |
664 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
||
665 | if (ret) |
||
666 | return ret; |
||
3746 | Serge | 667 | |
5060 | serge | 668 | ret = intel_ring_begin(ring, 6); |
669 | if (ret) |
||
670 | return ret; |
||
3746 | Serge | 671 | |
5060 | serge | 672 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
673 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); |
||
674 | intel_ring_emit(ring, PP_DIR_DCLV_2G); |
||
675 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); |
||
676 | intel_ring_emit(ring, get_pd_offset(ppgtt)); |
||
677 | intel_ring_emit(ring, MI_NOOP); |
||
678 | intel_ring_advance(ring); |
||
679 | |||
680 | return 0; |
||
681 | } |
||
682 | |||
683 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
||
5354 | serge | 684 | struct intel_engine_cs *ring) |
5060 | serge | 685 | { |
686 | int ret; |
||
687 | |||
688 | /* NB: TLBs must be flushed and invalidated before a switch */ |
||
689 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
||
690 | if (ret) |
||
691 | return ret; |
||
692 | |||
693 | ret = intel_ring_begin(ring, 6); |
||
694 | if (ret) |
||
695 | return ret; |
||
696 | |||
697 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
||
698 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); |
||
699 | intel_ring_emit(ring, PP_DIR_DCLV_2G); |
||
700 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); |
||
701 | intel_ring_emit(ring, get_pd_offset(ppgtt)); |
||
702 | intel_ring_emit(ring, MI_NOOP); |
||
703 | intel_ring_advance(ring); |
||
704 | |||
705 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
||
706 | if (ring->id != RCS) { |
||
707 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
||
708 | if (ret) |
||
709 | return ret; |
||
710 | } |
||
711 | |||
712 | return 0; |
||
713 | } |
||
714 | |||
715 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
||
5354 | serge | 716 | struct intel_engine_cs *ring) |
5060 | serge | 717 | { |
718 | struct drm_device *dev = ppgtt->base.dev; |
||
719 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
720 | |||
721 | |||
722 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
||
723 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
||
724 | |||
725 | POSTING_READ(RING_PP_DIR_DCLV(ring)); |
||
726 | |||
727 | return 0; |
||
728 | } |
||
729 | |||
5354 | serge | 730 | static void gen8_ppgtt_enable(struct drm_device *dev) |
5060 | serge | 731 | { |
732 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
733 | struct intel_engine_cs *ring; |
||
5354 | serge | 734 | int j; |
5060 | serge | 735 | |
736 | for_each_ring(ring, dev_priv, j) { |
||
737 | I915_WRITE(RING_MODE_GEN7(ring), |
||
738 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
||
739 | } |
||
740 | } |
||
741 | |||
5354 | serge | 742 | static void gen7_ppgtt_enable(struct drm_device *dev) |
5060 | serge | 743 | { |
744 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
745 | struct intel_engine_cs *ring; |
||
3746 | Serge | 746 | uint32_t ecochk, ecobits; |
5060 | serge | 747 | int i; |
3746 | Serge | 748 | |
749 | ecobits = I915_READ(GAC_ECO_BITS); |
||
750 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); |
||
751 | |||
752 | ecochk = I915_READ(GAM_ECOCHK); |
||
753 | if (IS_HASWELL(dev)) { |
||
754 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
||
755 | } else { |
||
756 | ecochk |= ECOCHK_PPGTT_LLC_IVB; |
||
757 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; |
||
758 | } |
||
759 | I915_WRITE(GAM_ECOCHK, ecochk); |
||
760 | |||
761 | for_each_ring(ring, dev_priv, i) { |
||
5060 | serge | 762 | /* GFX_MODE is per-ring on gen7+ */ |
3746 | Serge | 763 | I915_WRITE(RING_MODE_GEN7(ring), |
764 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
||
765 | } |
||
766 | } |
||
767 | |||
5354 | serge | 768 | static void gen6_ppgtt_enable(struct drm_device *dev) |
5060 | serge | 769 | { |
770 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
771 | uint32_t ecochk, gab_ctl, ecobits; |
||
772 | |||
773 | ecobits = I915_READ(GAC_ECO_BITS); |
||
774 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
||
775 | ECOBITS_PPGTT_CACHE64B); |
||
776 | |||
777 | gab_ctl = I915_READ(GAB_CTL); |
||
778 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); |
||
779 | |||
780 | ecochk = I915_READ(GAM_ECOCHK); |
||
781 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); |
||
782 | |||
783 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
||
784 | } |
||
785 | |||
3031 | serge | 786 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
4104 | Serge | 787 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
5060 | serge | 788 | uint64_t start, |
789 | uint64_t length, |
||
4280 | Serge | 790 | bool use_scratch) |
3031 | serge | 791 | { |
4104 | Serge | 792 | struct i915_hw_ppgtt *ppgtt = |
793 | container_of(vm, struct i915_hw_ppgtt, base); |
||
3746 | Serge | 794 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
5060 | serge | 795 | unsigned first_entry = start >> PAGE_SHIFT; |
796 | unsigned num_entries = length >> PAGE_SHIFT; |
||
3746 | Serge | 797 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
3031 | serge | 798 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
799 | unsigned last_pte, i; |
||
800 | |||
5060 | serge | 801 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
3031 | serge | 802 | |
3480 | Serge | 803 | while (num_entries) { |
3031 | serge | 804 | last_pte = first_pte + num_entries; |
805 | if (last_pte > I915_PPGTT_PT_ENTRIES) |
||
806 | last_pte = I915_PPGTT_PT_ENTRIES; |
||
807 | |||
5354 | serge | 808 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
3031 | serge | 809 | |
810 | for (i = first_pte; i < last_pte; i++) |
||
811 | pt_vaddr[i] = scratch_pte; |
||
812 | |||
5354 | serge | 813 | kunmap_atomic(pt_vaddr); |
814 | |||
3031 | serge | 815 | num_entries -= last_pte - first_pte; |
816 | first_pte = 0; |
||
3746 | Serge | 817 | act_pt++; |
5354 | serge | 818 | } |
3480 | Serge | 819 | } |
820 | |||
4104 | Serge | 821 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
3480 | Serge | 822 | struct sg_table *pages, |
5060 | serge | 823 | uint64_t start, |
824 | enum i915_cache_level cache_level, u32 flags) |
||
3480 | Serge | 825 | { |
4104 | Serge | 826 | struct i915_hw_ppgtt *ppgtt = |
827 | container_of(vm, struct i915_hw_ppgtt, base); |
||
3746 | Serge | 828 | gen6_gtt_pte_t *pt_vaddr; |
5060 | serge | 829 | unsigned first_entry = start >> PAGE_SHIFT; |
3746 | Serge | 830 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
831 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
||
832 | struct sg_page_iter sg_iter; |
||
3480 | Serge | 833 | |
5354 | serge | 834 | pt_vaddr = NULL; |
3746 | Serge | 835 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
5354 | serge | 836 | if (pt_vaddr == NULL) |
837 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
||
3480 | Serge | 838 | |
4560 | Serge | 839 | pt_vaddr[act_pte] = |
840 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), |
||
5060 | serge | 841 | cache_level, true, flags); |
842 | |||
3746 | Serge | 843 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
5354 | serge | 844 | kunmap_atomic(pt_vaddr); |
845 | pt_vaddr = NULL; |
||
3746 | Serge | 846 | act_pt++; |
847 | act_pte = 0; |
||
4104 | Serge | 848 | } |
3480 | Serge | 849 | } |
5354 | serge | 850 | if (pt_vaddr) |
851 | kunmap_atomic(pt_vaddr); |
||
3031 | serge | 852 | } |
853 | |||
5060 | serge | 854 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
3031 | serge | 855 | { |
3480 | Serge | 856 | int i; |
857 | |||
858 | if (ppgtt->pt_dma_addr) { |
||
859 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
||
4104 | Serge | 860 | pci_unmap_page(ppgtt->base.dev->pdev, |
3480 | Serge | 861 | ppgtt->pt_dma_addr[i], |
862 | 4096, PCI_DMA_BIDIRECTIONAL); |
||
863 | } |
||
5060 | serge | 864 | } |
3480 | Serge | 865 | |
5060 | serge | 866 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) |
867 | { |
||
868 | int i; |
||
869 | |||
3480 | Serge | 870 | kfree(ppgtt->pt_dma_addr); |
871 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
||
872 | __free_page(ppgtt->pt_pages[i]); |
||
873 | kfree(ppgtt->pt_pages); |
||
874 | } |
||
875 | |||
5060 | serge | 876 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
3480 | Serge | 877 | { |
5060 | serge | 878 | struct i915_hw_ppgtt *ppgtt = |
879 | container_of(vm, struct i915_hw_ppgtt, base); |
||
880 | |||
881 | drm_mm_remove_node(&ppgtt->node); |
||
882 | |||
883 | gen6_ppgtt_unmap_pages(ppgtt); |
||
884 | gen6_ppgtt_free(ppgtt); |
||
885 | } |
||
886 | |||
887 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
||
888 | { |
||
4104 | Serge | 889 | struct drm_device *dev = ppgtt->base.dev; |
3031 | serge | 890 | struct drm_i915_private *dev_priv = dev->dev_private; |
5060 | serge | 891 | bool retried = false; |
892 | int ret; |
||
3031 | serge | 893 | |
5060 | serge | 894 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
895 | * allocator works in address space sizes, so it's multiplied by page |
||
896 | * size. We allocate at the top of the GTT to avoid fragmentation. |
||
897 | */ |
||
898 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); |
||
899 | alloc: |
||
900 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
||
901 | &ppgtt->node, GEN6_PD_SIZE, |
||
902 | GEN6_PD_ALIGN, 0, |
||
903 | 0, dev_priv->gtt.base.total, |
||
904 | DRM_MM_TOPDOWN); |
||
905 | if (ret == -ENOSPC && !retried) { |
||
906 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, |
||
907 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
||
908 | I915_CACHE_NONE, |
||
909 | 0, dev_priv->gtt.base.total, |
||
910 | 0); |
||
911 | if (ret) |
||
912 | return ret; |
||
3031 | serge | 913 | |
5060 | serge | 914 | retried = true; |
915 | goto alloc; |
||
916 | } |
||
917 | |||
918 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
||
919 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
||
920 | |||
4104 | Serge | 921 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
5060 | serge | 922 | return ret; |
923 | } |
||
924 | |||
925 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) |
||
926 | { |
||
927 | int i; |
||
928 | |||
4560 | Serge | 929 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
3031 | serge | 930 | GFP_KERNEL); |
5060 | serge | 931 | |
3031 | serge | 932 | if (!ppgtt->pt_pages) |
3480 | Serge | 933 | return -ENOMEM; |
3031 | serge | 934 | |
935 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
||
3243 | Serge | 936 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); |
5060 | serge | 937 | if (!ppgtt->pt_pages[i]) { |
938 | gen6_ppgtt_free(ppgtt); |
||
939 | return -ENOMEM; |
||
940 | } |
||
3031 | serge | 941 | } |
942 | |||
5060 | serge | 943 | return 0; |
944 | } |
||
3031 | serge | 945 | |
5060 | serge | 946 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
947 | { |
||
948 | int ret; |
||
3031 | serge | 949 | |
5060 | serge | 950 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); |
951 | if (ret) |
||
952 | return ret; |
||
3031 | serge | 953 | |
5060 | serge | 954 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); |
955 | if (ret) { |
||
956 | drm_mm_remove_node(&ppgtt->node); |
||
957 | return ret; |
||
958 | } |
||
3031 | serge | 959 | |
5060 | serge | 960 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
961 | GFP_KERNEL); |
||
962 | if (!ppgtt->pt_dma_addr) { |
||
963 | drm_mm_remove_node(&ppgtt->node); |
||
964 | gen6_ppgtt_free(ppgtt); |
||
965 | return -ENOMEM; |
||
966 | } |
||
3031 | serge | 967 | |
968 | return 0; |
||
5060 | serge | 969 | } |
3031 | serge | 970 | |
5060 | serge | 971 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) |
972 | { |
||
973 | struct drm_device *dev = ppgtt->base.dev; |
||
974 | int i; |
||
975 | |||
3031 | serge | 976 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
5060 | serge | 977 | dma_addr_t pt_addr; |
978 | |||
979 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
||
980 | PCI_DMA_BIDIRECTIONAL); |
||
981 | |||
982 | // if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
||
983 | // gen6_ppgtt_unmap_pages(ppgtt); |
||
984 | // return -EIO; |
||
985 | // } |
||
986 | |||
987 | ppgtt->pt_dma_addr[i] = pt_addr; |
||
3031 | serge | 988 | } |
989 | |||
5060 | serge | 990 | return 0; |
3031 | serge | 991 | } |
992 | |||
5060 | serge | 993 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
3031 | serge | 994 | { |
5060 | serge | 995 | struct drm_device *dev = ppgtt->base.dev; |
3031 | serge | 996 | struct drm_i915_private *dev_priv = dev->dev_private; |
3480 | Serge | 997 | int ret; |
3031 | serge | 998 | |
5060 | serge | 999 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
1000 | if (IS_GEN6(dev)) { |
||
1001 | ppgtt->switch_mm = gen6_mm_switch; |
||
1002 | } else if (IS_HASWELL(dev)) { |
||
1003 | ppgtt->switch_mm = hsw_mm_switch; |
||
1004 | } else if (IS_GEN7(dev)) { |
||
1005 | ppgtt->switch_mm = gen7_mm_switch; |
||
1006 | } else |
||
1007 | BUG(); |
||
3031 | serge | 1008 | |
5060 | serge | 1009 | ret = gen6_ppgtt_alloc(ppgtt); |
1010 | if (ret) |
||
1011 | return ret; |
||
1012 | |||
1013 | ret = gen6_ppgtt_setup_page_tables(ppgtt); |
||
1014 | if (ret) { |
||
1015 | gen6_ppgtt_free(ppgtt); |
||
1016 | return ret; |
||
1017 | } |
||
1018 | |||
1019 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
||
1020 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; |
||
1021 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
||
1022 | ppgtt->base.start = 0; |
||
1023 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
||
1024 | // ppgtt->debug_dump = gen6_dump_ppgtt; |
||
1025 | |||
1026 | ppgtt->pd_offset = |
||
1027 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); |
||
1028 | |||
1029 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
||
1030 | |||
1031 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
||
1032 | ppgtt->node.size >> 20, |
||
1033 | ppgtt->node.start / PAGE_SIZE); |
||
1034 | |||
5354 | serge | 1035 | gen6_write_pdes(ppgtt); |
1036 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
||
1037 | ppgtt->pd_offset << 10); |
||
1038 | |||
5060 | serge | 1039 | return 0; |
1040 | } |
||
1041 | |||
5354 | serge | 1042 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
5060 | serge | 1043 | { |
1044 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1045 | |||
4104 | Serge | 1046 | ppgtt->base.dev = dev; |
5060 | serge | 1047 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3031 | serge | 1048 | |
3746 | Serge | 1049 | if (INTEL_INFO(dev)->gen < 8) |
5354 | serge | 1050 | return gen6_ppgtt_init(ppgtt); |
1051 | else if (IS_GEN8(dev) || IS_GEN9(dev)) |
||
1052 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
||
3746 | Serge | 1053 | else |
1054 | BUG(); |
||
5354 | serge | 1055 | } |
1056 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
||
1057 | { |
||
1058 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1059 | int ret = 0; |
||
3746 | Serge | 1060 | |
5354 | serge | 1061 | ret = __hw_ppgtt_init(dev, ppgtt); |
1062 | if (ret == 0) { |
||
5060 | serge | 1063 | kref_init(&ppgtt->ref); |
4104 | Serge | 1064 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1065 | ppgtt->base.total); |
||
5060 | serge | 1066 | i915_init_vm(dev_priv, &ppgtt->base); |
5354 | serge | 1067 | } |
1068 | |||
1069 | return ret; |
||
1070 | } |
||
1071 | |||
1072 | int i915_ppgtt_init_hw(struct drm_device *dev) |
||
1073 | { |
||
1074 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1075 | struct intel_engine_cs *ring; |
||
1076 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
||
1077 | int i, ret = 0; |
||
1078 | |||
1079 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
||
1080 | * and the PDPs are contained within the context itself. We don't |
||
1081 | * need to do anything here. */ |
||
1082 | if (i915.enable_execlists) |
||
1083 | return 0; |
||
1084 | |||
1085 | if (!USES_PPGTT(dev)) |
||
1086 | return 0; |
||
1087 | |||
1088 | if (IS_GEN6(dev)) |
||
1089 | gen6_ppgtt_enable(dev); |
||
1090 | else if (IS_GEN7(dev)) |
||
1091 | gen7_ppgtt_enable(dev); |
||
1092 | else if (INTEL_INFO(dev)->gen >= 8) |
||
1093 | gen8_ppgtt_enable(dev); |
||
1094 | else |
||
1095 | WARN_ON(1); |
||
1096 | |||
1097 | if (ppgtt) { |
||
1098 | for_each_ring(ring, dev_priv, i) { |
||
1099 | ret = ppgtt->switch_mm(ppgtt, ring); |
||
1100 | if (ret != 0) |
||
1101 | return ret; |
||
5060 | serge | 1102 | } |
4104 | Serge | 1103 | } |
3480 | Serge | 1104 | |
1105 | return ret; |
||
3031 | serge | 1106 | } |
5354 | serge | 1107 | struct i915_hw_ppgtt * |
1108 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) |
||
1109 | { |
||
1110 | struct i915_hw_ppgtt *ppgtt; |
||
1111 | int ret; |
||
3031 | serge | 1112 | |
5354 | serge | 1113 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
1114 | if (!ppgtt) |
||
1115 | return ERR_PTR(-ENOMEM); |
||
1116 | |||
1117 | ret = i915_ppgtt_init(dev, ppgtt); |
||
1118 | if (ret) { |
||
1119 | kfree(ppgtt); |
||
1120 | return ERR_PTR(ret); |
||
1121 | } |
||
1122 | |||
1123 | ppgtt->file_priv = fpriv; |
||
1124 | |||
1125 | trace_i915_ppgtt_create(&ppgtt->base); |
||
1126 | |||
1127 | return ppgtt; |
||
1128 | } |
||
1129 | |||
1130 | void i915_ppgtt_release(struct kref *kref) |
||
1131 | { |
||
1132 | struct i915_hw_ppgtt *ppgtt = |
||
1133 | container_of(kref, struct i915_hw_ppgtt, ref); |
||
1134 | |||
1135 | trace_i915_ppgtt_release(&ppgtt->base); |
||
1136 | |||
1137 | /* vmas should already be unbound */ |
||
1138 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
||
1139 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); |
||
1140 | |||
1141 | list_del(&ppgtt->base.global_link); |
||
1142 | drm_mm_takedown(&ppgtt->base.mm); |
||
1143 | |||
1144 | ppgtt->base.cleanup(&ppgtt->base); |
||
1145 | kfree(ppgtt); |
||
1146 | } |
||
1147 | |||
5060 | serge | 1148 | static void |
1149 | ppgtt_bind_vma(struct i915_vma *vma, |
||
1150 | enum i915_cache_level cache_level, |
||
1151 | u32 flags) |
||
3031 | serge | 1152 | { |
5060 | serge | 1153 | /* Currently applicable only to VLV */ |
1154 | if (vma->obj->gt_ro) |
||
1155 | flags |= PTE_READ_ONLY; |
||
3031 | serge | 1156 | |
5060 | serge | 1157 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
1158 | cache_level, flags); |
||
3031 | serge | 1159 | } |
1160 | |||
5060 | serge | 1161 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
3031 | serge | 1162 | { |
5060 | serge | 1163 | vma->vm->clear_range(vma->vm, |
1164 | vma->node.start, |
||
1165 | vma->obj->base.size, |
||
4280 | Serge | 1166 | true); |
3031 | serge | 1167 | } |
1168 | |||
3480 | Serge | 1169 | extern int intel_iommu_gfx_mapped; |
1170 | /* Certain Gen5 chipsets require require idling the GPU before |
||
1171 | * unmapping anything from the GTT when VT-d is enabled. |
||
1172 | */ |
||
1173 | static inline bool needs_idle_maps(struct drm_device *dev) |
||
1174 | { |
||
1175 | #ifdef CONFIG_INTEL_IOMMU |
||
1176 | /* Query intel_iommu to see if we need the workaround. Presumably that |
||
1177 | * was loaded first. |
||
1178 | */ |
||
1179 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) |
||
1180 | return true; |
||
1181 | #endif |
||
1182 | return false; |
||
1183 | } |
||
1184 | |||
2344 | Serge | 1185 | static bool do_idling(struct drm_i915_private *dev_priv) |
1186 | { |
||
1187 | bool ret = dev_priv->mm.interruptible; |
||
1188 | |||
3480 | Serge | 1189 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
2344 | Serge | 1190 | dev_priv->mm.interruptible = false; |
1191 | if (i915_gpu_idle(dev_priv->dev)) { |
||
1192 | DRM_ERROR("Couldn't idle GPU\n"); |
||
1193 | /* Wait a bit, in hopes it avoids the hang */ |
||
1194 | udelay(10); |
||
1195 | } |
||
1196 | } |
||
1197 | |||
1198 | return ret; |
||
1199 | } |
||
1200 | |||
1201 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) |
||
1202 | { |
||
3480 | Serge | 1203 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2344 | Serge | 1204 | dev_priv->mm.interruptible = interruptible; |
1205 | } |
||
1206 | |||
4280 | Serge | 1207 | void i915_check_and_clear_faults(struct drm_device *dev) |
1208 | { |
||
1209 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5060 | serge | 1210 | struct intel_engine_cs *ring; |
4280 | Serge | 1211 | int i; |
1212 | |||
1213 | if (INTEL_INFO(dev)->gen < 6) |
||
1214 | return; |
||
1215 | |||
1216 | for_each_ring(ring, dev_priv, i) { |
||
1217 | u32 fault_reg; |
||
1218 | fault_reg = I915_READ(RING_FAULT_REG(ring)); |
||
1219 | if (fault_reg & RING_FAULT_VALID) { |
||
1220 | DRM_DEBUG_DRIVER("Unexpected fault\n" |
||
5354 | serge | 1221 | "\tAddr: 0x%08lx\n" |
4280 | Serge | 1222 | "\tAddress space: %s\n" |
1223 | "\tSource ID: %d\n" |
||
1224 | "\tType: %d\n", |
||
1225 | fault_reg & PAGE_MASK, |
||
1226 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", |
||
1227 | RING_FAULT_SRCID(fault_reg), |
||
1228 | RING_FAULT_FAULT_TYPE(fault_reg)); |
||
1229 | I915_WRITE(RING_FAULT_REG(ring), |
||
1230 | fault_reg & ~RING_FAULT_VALID); |
||
1231 | } |
||
1232 | } |
||
1233 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); |
||
1234 | } |
||
1235 | |||
5354 | serge | 1236 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1237 | { |
||
1238 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { |
||
1239 | intel_gtt_chipset_flush(); |
||
1240 | } else { |
||
1241 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
||
1242 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
||
1243 | } |
||
1244 | } |
||
1245 | |||
4280 | Serge | 1246 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1247 | { |
||
1248 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1249 | |||
1250 | /* Don't bother messing with faults pre GEN6 as we have little |
||
1251 | * documentation supporting that it's a good idea. |
||
1252 | */ |
||
1253 | if (INTEL_INFO(dev)->gen < 6) |
||
1254 | return; |
||
1255 | |||
1256 | i915_check_and_clear_faults(dev); |
||
1257 | |||
1258 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
||
5060 | serge | 1259 | dev_priv->gtt.base.start, |
1260 | dev_priv->gtt.base.total, |
||
1261 | true); |
||
5354 | serge | 1262 | |
1263 | i915_ggtt_flush(dev_priv); |
||
4280 | Serge | 1264 | } |
1265 | |||
2332 | Serge | 1266 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1267 | { |
||
1268 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1269 | struct drm_i915_gem_object *obj; |
||
5060 | serge | 1270 | struct i915_address_space *vm; |
2332 | Serge | 1271 | |
4280 | Serge | 1272 | i915_check_and_clear_faults(dev); |
1273 | |||
2332 | Serge | 1274 | /* First fill our portion of the GTT with scratch pages */ |
4104 | Serge | 1275 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
5060 | serge | 1276 | dev_priv->gtt.base.start, |
1277 | dev_priv->gtt.base.total, |
||
4280 | Serge | 1278 | true); |
2332 | Serge | 1279 | |
4104 | Serge | 1280 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
5060 | serge | 1281 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1282 | &dev_priv->gtt.base); |
||
1283 | if (!vma) |
||
1284 | continue; |
||
1285 | |||
4104 | Serge | 1286 | i915_gem_clflush_object(obj, obj->pin_display); |
5060 | serge | 1287 | /* The bind_vma code tries to be smart about tracking mappings. |
1288 | * Unfortunately above, we've just wiped out the mappings |
||
1289 | * without telling our object about it. So we need to fake it. |
||
1290 | */ |
||
5354 | serge | 1291 | vma->bound &= ~GLOBAL_BIND; |
5060 | serge | 1292 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
2332 | Serge | 1293 | } |
1294 | |||
5060 | serge | 1295 | |
1296 | if (INTEL_INFO(dev)->gen >= 8) { |
||
1297 | if (IS_CHERRYVIEW(dev)) |
||
1298 | chv_setup_private_ppat(dev_priv); |
||
1299 | else |
||
1300 | bdw_setup_private_ppat(dev_priv); |
||
1301 | |||
1302 | return; |
||
1303 | } |
||
1304 | |||
1305 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
||
1306 | /* TODO: Perhaps it shouldn't be gen6 specific */ |
||
1307 | if (i915_is_ggtt(vm)) { |
||
1308 | if (dev_priv->mm.aliasing_ppgtt) |
||
1309 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); |
||
1310 | continue; |
||
1311 | } |
||
1312 | |||
1313 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); |
||
1314 | } |
||
1315 | |||
5354 | serge | 1316 | i915_ggtt_flush(dev_priv); |
2332 | Serge | 1317 | } |
1318 | |||
3031 | serge | 1319 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
2332 | Serge | 1320 | { |
3243 | Serge | 1321 | if (obj->has_dma_mapping) |
1322 | return 0; |
||
1323 | |||
3480 | Serge | 1324 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
1325 | obj->pages->sgl, obj->pages->nents, |
||
1326 | PCI_DMA_BIDIRECTIONAL)) |
||
1327 | return -ENOSPC; |
||
3243 | Serge | 1328 | |
2332 | Serge | 1329 | return 0; |
1330 | } |
||
1331 | |||
4560 | Serge | 1332 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1333 | { |
||
1334 | #ifdef writeq |
||
1335 | writeq(pte, addr); |
||
1336 | #else |
||
1337 | iowrite32((u32)pte, addr); |
||
1338 | iowrite32(pte >> 32, addr + 4); |
||
1339 | #endif |
||
1340 | } |
||
1341 | |||
1342 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
||
1343 | struct sg_table *st, |
||
5060 | serge | 1344 | uint64_t start, |
1345 | enum i915_cache_level level, u32 unused) |
||
4560 | Serge | 1346 | { |
1347 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
||
5060 | serge | 1348 | unsigned first_entry = start >> PAGE_SHIFT; |
4560 | Serge | 1349 | gen8_gtt_pte_t __iomem *gtt_entries = |
1350 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
||
1351 | int i = 0; |
||
1352 | struct sg_page_iter sg_iter; |
||
5060 | serge | 1353 | dma_addr_t addr = 0; /* shut up gcc */ |
4560 | Serge | 1354 | |
1355 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
||
1356 | addr = sg_dma_address(sg_iter.sg) + |
||
1357 | (sg_iter.sg_pgoffset << PAGE_SHIFT); |
||
1358 | gen8_set_pte(>t_entries[i], |
||
1359 | gen8_pte_encode(addr, level, true)); |
||
1360 | i++; |
||
1361 | } |
||
1362 | |||
1363 | /* |
||
1364 | * XXX: This serves as a posting read to make sure that the PTE has |
||
1365 | * actually been updated. There is some concern that even though |
||
1366 | * registers and PTEs are within the same BAR that they are potentially |
||
1367 | * of NUMA access patterns. Therefore, even with the way we assume |
||
1368 | * hardware should work, we must keep this posting read for paranoia. |
||
1369 | */ |
||
1370 | if (i != 0) |
||
1371 | WARN_ON(readq(>t_entries[i-1]) |
||
1372 | != gen8_pte_encode(addr, level, true)); |
||
1373 | |||
1374 | /* This next bit makes the above posting read even more important. We |
||
1375 | * want to flush the TLBs only after we're certain all the PTE updates |
||
1376 | * have finished. |
||
1377 | */ |
||
1378 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
||
1379 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
||
1380 | } |
||
1381 | |||
3243 | Serge | 1382 | /* |
1383 | * Binds an object into the global gtt with the specified cache level. The object |
||
1384 | * will be accessible to the GPU via commands whose operands reference offsets |
||
1385 | * within the global GTT as well as accessible by the GPU through the GMADR |
||
1386 | * mapped BAR (dev_priv->mm.gtt->gtt). |
||
1387 | */ |
||
4104 | Serge | 1388 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
3480 | Serge | 1389 | struct sg_table *st, |
5060 | serge | 1390 | uint64_t start, |
1391 | enum i915_cache_level level, u32 flags) |
||
3243 | Serge | 1392 | { |
4104 | Serge | 1393 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
5060 | serge | 1394 | unsigned first_entry = start >> PAGE_SHIFT; |
3746 | Serge | 1395 | gen6_gtt_pte_t __iomem *gtt_entries = |
1396 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
||
1397 | int i = 0; |
||
1398 | struct sg_page_iter sg_iter; |
||
5060 | serge | 1399 | dma_addr_t addr = 0; |
3243 | Serge | 1400 | |
3746 | Serge | 1401 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
1402 | addr = sg_page_iter_dma_address(&sg_iter); |
||
5060 | serge | 1403 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
3243 | Serge | 1404 | i++; |
1405 | } |
||
1406 | |||
1407 | /* XXX: This serves as a posting read to make sure that the PTE has |
||
1408 | * actually been updated. There is some concern that even though |
||
1409 | * registers and PTEs are within the same BAR that they are potentially |
||
1410 | * of NUMA access patterns. Therefore, even with the way we assume |
||
1411 | * hardware should work, we must keep this posting read for paranoia. |
||
1412 | */ |
||
5060 | serge | 1413 | if (i != 0) { |
1414 | unsigned long gtt = readl(>t_entries[i-1]); |
||
1415 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); |
||
1416 | } |
||
3243 | Serge | 1417 | |
1418 | /* This next bit makes the above posting read even more important. We |
||
1419 | * want to flush the TLBs only after we're certain all the PTE updates |
||
1420 | * have finished. |
||
1421 | */ |
||
1422 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
||
1423 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
||
1424 | } |
||
1425 | |||
4560 | Serge | 1426 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
5060 | serge | 1427 | uint64_t start, |
1428 | uint64_t length, |
||
4560 | Serge | 1429 | bool use_scratch) |
1430 | { |
||
1431 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
||
5060 | serge | 1432 | unsigned first_entry = start >> PAGE_SHIFT; |
1433 | unsigned num_entries = length >> PAGE_SHIFT; |
||
4560 | Serge | 1434 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1435 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
||
1436 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
||
1437 | int i; |
||
1438 | |||
1439 | if (WARN(num_entries > max_entries, |
||
1440 | "First entry = %d; Num entries = %d (max=%d)\n", |
||
1441 | first_entry, num_entries, max_entries)) |
||
1442 | num_entries = max_entries; |
||
1443 | |||
1444 | scratch_pte = gen8_pte_encode(vm->scratch.addr, |
||
1445 | I915_CACHE_LLC, |
||
1446 | use_scratch); |
||
1447 | for (i = 0; i < num_entries; i++) |
||
1448 | gen8_set_pte(>t_base[i], scratch_pte); |
||
1449 | readl(gtt_base); |
||
1450 | } |
||
1451 | |||
4104 | Serge | 1452 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
5060 | serge | 1453 | uint64_t start, |
1454 | uint64_t length, |
||
4280 | Serge | 1455 | bool use_scratch) |
3480 | Serge | 1456 | { |
4104 | Serge | 1457 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
5060 | serge | 1458 | unsigned first_entry = start >> PAGE_SHIFT; |
1459 | unsigned num_entries = length >> PAGE_SHIFT; |
||
3746 | Serge | 1460 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1461 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
||
3480 | Serge | 1462 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1463 | int i; |
||
1464 | |||
4126 | Serge | 1465 | if (WARN(num_entries > max_entries, |
1466 | "First entry = %d; Num entries = %d (max=%d)\n", |
||
1467 | first_entry, num_entries, max_entries)) |
||
4104 | Serge | 1468 | num_entries = max_entries; |
3480 | Serge | 1469 | |
5060 | serge | 1470 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
4280 | Serge | 1471 | |
3480 | Serge | 1472 | for (i = 0; i < num_entries; i++) |
1473 | iowrite32(scratch_pte, >t_base[i]); |
||
1474 | readl(gtt_base); |
||
1475 | } |
||
1476 | |||
5060 | serge | 1477 | |
1478 | static void i915_ggtt_bind_vma(struct i915_vma *vma, |
||
1479 | enum i915_cache_level cache_level, |
||
1480 | u32 unused) |
||
3480 | Serge | 1481 | { |
5060 | serge | 1482 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
3480 | Serge | 1483 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1484 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; |
||
1485 | |||
5060 | serge | 1486 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1487 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); |
||
5354 | serge | 1488 | vma->bound = GLOBAL_BIND; |
3480 | Serge | 1489 | } |
1490 | |||
4104 | Serge | 1491 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
5060 | serge | 1492 | uint64_t start, |
1493 | uint64_t length, |
||
4280 | Serge | 1494 | bool unused) |
3480 | Serge | 1495 | { |
5060 | serge | 1496 | unsigned first_entry = start >> PAGE_SHIFT; |
1497 | unsigned num_entries = length >> PAGE_SHIFT; |
||
3480 | Serge | 1498 | intel_gtt_clear_range(first_entry, num_entries); |
1499 | } |
||
1500 | |||
5060 | serge | 1501 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1502 | { |
||
1503 | const unsigned int first = vma->node.start >> PAGE_SHIFT; |
||
1504 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; |
||
3480 | Serge | 1505 | |
5060 | serge | 1506 | BUG_ON(!i915_is_ggtt(vma->vm)); |
5354 | serge | 1507 | vma->bound = 0; |
5060 | serge | 1508 | intel_gtt_clear_range(first, size); |
1509 | } |
||
1510 | |||
1511 | static void ggtt_bind_vma(struct i915_vma *vma, |
||
1512 | enum i915_cache_level cache_level, |
||
1513 | u32 flags) |
||
2332 | Serge | 1514 | { |
5060 | serge | 1515 | struct drm_device *dev = vma->vm->dev; |
3480 | Serge | 1516 | struct drm_i915_private *dev_priv = dev->dev_private; |
5060 | serge | 1517 | struct drm_i915_gem_object *obj = vma->obj; |
3480 | Serge | 1518 | |
5060 | serge | 1519 | /* Currently applicable only to VLV */ |
1520 | if (obj->gt_ro) |
||
1521 | flags |= PTE_READ_ONLY; |
||
2332 | Serge | 1522 | |
5060 | serge | 1523 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1524 | * or we have a global mapping already but the cacheability flags have |
||
1525 | * changed, set the global PTEs. |
||
1526 | * |
||
1527 | * If there is an aliasing PPGTT it is anecdotally faster, so use that |
||
1528 | * instead if none of the above hold true. |
||
1529 | * |
||
1530 | * NB: A global mapping should only be needed for special regions like |
||
1531 | * "gtt mappable", SNB errata, or if specified via special execbuf |
||
1532 | * flags. At all other times, the GPU will use the aliasing PPGTT. |
||
1533 | */ |
||
1534 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
||
5354 | serge | 1535 | if (!(vma->bound & GLOBAL_BIND) || |
5060 | serge | 1536 | (cache_level != obj->cache_level)) { |
1537 | vma->vm->insert_entries(vma->vm, obj->pages, |
||
1538 | vma->node.start, |
||
1539 | cache_level, flags); |
||
5354 | serge | 1540 | vma->bound |= GLOBAL_BIND; |
5060 | serge | 1541 | } |
1542 | } |
||
1543 | |||
1544 | if (dev_priv->mm.aliasing_ppgtt && |
||
5354 | serge | 1545 | (!(vma->bound & LOCAL_BIND) || |
5060 | serge | 1546 | (cache_level != obj->cache_level))) { |
1547 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
||
1548 | appgtt->base.insert_entries(&appgtt->base, |
||
1549 | vma->obj->pages, |
||
1550 | vma->node.start, |
||
1551 | cache_level, flags); |
||
5354 | serge | 1552 | vma->bound |= LOCAL_BIND; |
5060 | serge | 1553 | } |
2332 | Serge | 1554 | } |
1555 | |||
5060 | serge | 1556 | static void ggtt_unbind_vma(struct i915_vma *vma) |
2332 | Serge | 1557 | { |
5060 | serge | 1558 | struct drm_device *dev = vma->vm->dev; |
3480 | Serge | 1559 | struct drm_i915_private *dev_priv = dev->dev_private; |
5060 | serge | 1560 | struct drm_i915_gem_object *obj = vma->obj; |
3480 | Serge | 1561 | |
5354 | serge | 1562 | if (vma->bound & GLOBAL_BIND) { |
5060 | serge | 1563 | vma->vm->clear_range(vma->vm, |
1564 | vma->node.start, |
||
1565 | obj->base.size, |
||
4280 | Serge | 1566 | true); |
5354 | serge | 1567 | vma->bound &= ~GLOBAL_BIND; |
5060 | serge | 1568 | } |
3031 | serge | 1569 | |
5354 | serge | 1570 | if (vma->bound & LOCAL_BIND) { |
5060 | serge | 1571 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1572 | appgtt->base.clear_range(&appgtt->base, |
||
1573 | vma->node.start, |
||
1574 | obj->base.size, |
||
1575 | true); |
||
5354 | serge | 1576 | vma->bound &= ~LOCAL_BIND; |
5060 | serge | 1577 | } |
3031 | serge | 1578 | } |
1579 | |||
1580 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) |
||
1581 | { |
||
2344 | Serge | 1582 | struct drm_device *dev = obj->base.dev; |
1583 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1584 | bool interruptible; |
||
1585 | |||
1586 | interruptible = do_idling(dev_priv); |
||
1587 | |||
3480 | Serge | 1588 | if (!obj->has_dma_mapping) |
1589 | dma_unmap_sg(&dev->pdev->dev, |
||
1590 | obj->pages->sgl, obj->pages->nents, |
||
1591 | PCI_DMA_BIDIRECTIONAL); |
||
2332 | Serge | 1592 | |
3031 | serge | 1593 | undo_idling(dev_priv, interruptible); |
1594 | } |
||
1595 | |||
1596 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
||
1597 | unsigned long color, |
||
1598 | unsigned long *start, |
||
1599 | unsigned long *end) |
||
1600 | { |
||
1601 | if (node->color != color) |
||
1602 | *start += 4096; |
||
1603 | |||
1604 | if (!list_empty(&node->node_list)) { |
||
1605 | node = list_entry(node->node_list.next, |
||
1606 | struct drm_mm_node, |
||
1607 | node_list); |
||
1608 | if (node->allocated && node->color != color) |
||
1609 | *end -= 4096; |
||
2332 | Serge | 1610 | } |
3031 | serge | 1611 | } |
4560 | Serge | 1612 | |
5354 | serge | 1613 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
3031 | serge | 1614 | unsigned long start, |
1615 | unsigned long mappable_end, |
||
1616 | unsigned long end) |
||
1617 | { |
||
3480 | Serge | 1618 | /* Let GEM Manage all of the aperture. |
1619 | * |
||
1620 | * However, leave one page at the end still bound to the scratch page. |
||
1621 | * There are a number of places where the hardware apparently prefetches |
||
1622 | * past the end of the object, and we've seen multiple hangs with the |
||
1623 | * GPU head pointer stuck in a batchbuffer bound at the last page of the |
||
1624 | * aperture. One page should be enough to keep any prefetching inside |
||
1625 | * of the aperture. |
||
1626 | */ |
||
4104 | Serge | 1627 | struct drm_i915_private *dev_priv = dev->dev_private; |
1628 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; |
||
3480 | Serge | 1629 | struct drm_mm_node *entry; |
1630 | struct drm_i915_gem_object *obj; |
||
1631 | unsigned long hole_start, hole_end; |
||
5354 | serge | 1632 | int ret; |
3031 | serge | 1633 | |
3480 | Serge | 1634 | BUG_ON(mappable_end > end); |
1635 | |||
1636 | /* Subtract the guard page ... */ |
||
4104 | Serge | 1637 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
3031 | serge | 1638 | if (!HAS_LLC(dev)) |
4104 | Serge | 1639 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
3031 | serge | 1640 | |
3480 | Serge | 1641 | /* Mark any preallocated objects as occupied */ |
4104 | Serge | 1642 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1643 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
||
5354 | serge | 1644 | |
4104 | Serge | 1645 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
1646 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
||
3031 | serge | 1647 | |
4104 | Serge | 1648 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); |
1649 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
||
5354 | serge | 1650 | if (ret) { |
1651 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); |
||
1652 | return ret; |
||
1653 | } |
||
1654 | vma->bound |= GLOBAL_BIND; |
||
3480 | Serge | 1655 | } |
1656 | |||
4104 | Serge | 1657 | dev_priv->gtt.base.start = start; |
1658 | dev_priv->gtt.base.total = end - start; |
||
3480 | Serge | 1659 | |
1660 | /* Clear any non-preallocated blocks */ |
||
4104 | Serge | 1661 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
3480 | Serge | 1662 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1663 | hole_start, hole_end); |
||
5060 | serge | 1664 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1665 | hole_end - hole_start, true); |
||
3480 | Serge | 1666 | } |
1667 | |||
1668 | /* And finally clear the reserved guard page */ |
||
5060 | serge | 1669 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
5354 | serge | 1670 | |
1671 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
||
1672 | struct i915_hw_ppgtt *ppgtt; |
||
1673 | |||
1674 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
||
1675 | if (!ppgtt) |
||
1676 | return -ENOMEM; |
||
1677 | |||
1678 | ret = __hw_ppgtt_init(dev, ppgtt); |
||
1679 | if (ret != 0) |
||
1680 | return ret; |
||
1681 | |||
1682 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
||
1683 | } |
||
1684 | |||
1685 | return 0; |
||
2332 | Serge | 1686 | } |
3243 | Serge | 1687 | |
3480 | Serge | 1688 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1689 | { |
||
1690 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1691 | unsigned long gtt_size, mappable_size; |
||
1692 | |||
4104 | Serge | 1693 | gtt_size = dev_priv->gtt.base.total; |
3480 | Serge | 1694 | mappable_size = dev_priv->gtt.mappable_end; |
1695 | |||
4280 | Serge | 1696 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
3480 | Serge | 1697 | } |
1698 | |||
5354 | serge | 1699 | void i915_global_gtt_cleanup(struct drm_device *dev) |
1700 | { |
||
1701 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1702 | struct i915_address_space *vm = &dev_priv->gtt.base; |
||
1703 | |||
1704 | if (dev_priv->mm.aliasing_ppgtt) { |
||
1705 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
||
1706 | |||
1707 | ppgtt->base.cleanup(&ppgtt->base); |
||
1708 | } |
||
1709 | |||
1710 | if (drm_mm_initialized(&vm->mm)) { |
||
1711 | drm_mm_takedown(&vm->mm); |
||
1712 | list_del(&vm->global_link); |
||
1713 | } |
||
1714 | |||
1715 | vm->cleanup(vm); |
||
1716 | } |
||
1717 | |||
3243 | Serge | 1718 | static int setup_scratch_page(struct drm_device *dev) |
1719 | { |
||
1720 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1721 | struct page *page; |
||
1722 | dma_addr_t dma_addr; |
||
1723 | |||
1724 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
||
1725 | if (page == NULL) |
||
1726 | return -ENOMEM; |
||
3480 | Serge | 1727 | set_pages_uc(page, 1); |
3243 | Serge | 1728 | |
1729 | #ifdef CONFIG_INTEL_IOMMU |
||
1730 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, |
||
1731 | PCI_DMA_BIDIRECTIONAL); |
||
1732 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) |
||
1733 | return -EINVAL; |
||
1734 | #else |
||
1735 | dma_addr = page_to_phys(page); |
||
1736 | #endif |
||
4104 | Serge | 1737 | dev_priv->gtt.base.scratch.page = page; |
1738 | dev_priv->gtt.base.scratch.addr = dma_addr; |
||
3243 | Serge | 1739 | |
1740 | return 0; |
||
1741 | } |
||
1742 | |||
3480 | Serge | 1743 | static void teardown_scratch_page(struct drm_device *dev) |
1744 | { |
||
1745 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4104 | Serge | 1746 | struct page *page = dev_priv->gtt.base.scratch.page; |
1747 | |||
1748 | set_pages_wb(page, 1); |
||
1749 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, |
||
3480 | Serge | 1750 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
4104 | Serge | 1751 | __free_page(page); |
3480 | Serge | 1752 | } |
3243 | Serge | 1753 | |
1754 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
||
1755 | { |
||
1756 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; |
||
1757 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; |
||
1758 | return snb_gmch_ctl << 20; |
||
1759 | } |
||
1760 | |||
4560 | Serge | 1761 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1762 | { |
||
1763 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; |
||
1764 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; |
||
1765 | if (bdw_gmch_ctl) |
||
1766 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; |
||
1767 | |||
5060 | serge | 1768 | #ifdef CONFIG_X86_32 |
1769 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ |
||
1770 | if (bdw_gmch_ctl > 4) |
||
1771 | bdw_gmch_ctl = 4; |
||
1772 | #endif |
||
1773 | |||
4560 | Serge | 1774 | return bdw_gmch_ctl << 20; |
1775 | } |
||
1776 | |||
5060 | serge | 1777 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
1778 | { |
||
1779 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; |
||
1780 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; |
||
1781 | |||
1782 | if (gmch_ctrl) |
||
1783 | return 1 << (20 + gmch_ctrl); |
||
1784 | |||
1785 | return 0; |
||
1786 | } |
||
1787 | |||
3480 | Serge | 1788 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
3243 | Serge | 1789 | { |
1790 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; |
||
1791 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; |
||
1792 | return snb_gmch_ctl << 25; /* 32 MB units */ |
||
1793 | } |
||
1794 | |||
4560 | Serge | 1795 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1796 | { |
||
1797 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; |
||
1798 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; |
||
1799 | return bdw_gmch_ctl << 25; /* 32 MB units */ |
||
1800 | } |
||
1801 | |||
5060 | serge | 1802 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
1803 | { |
||
1804 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; |
||
1805 | gmch_ctrl &= SNB_GMCH_GMS_MASK; |
||
1806 | |||
1807 | /* |
||
1808 | * 0x0 to 0x10: 32MB increments starting at 0MB |
||
1809 | * 0x11 to 0x16: 4MB increments starting at 8MB |
||
1810 | * 0x17 to 0x1d: 4MB increments start at 36MB |
||
1811 | */ |
||
1812 | if (gmch_ctrl < 0x11) |
||
1813 | return gmch_ctrl << 25; |
||
1814 | else if (gmch_ctrl < 0x17) |
||
1815 | return (gmch_ctrl - 0x11 + 2) << 22; |
||
1816 | else |
||
1817 | return (gmch_ctrl - 0x17 + 9) << 22; |
||
1818 | } |
||
1819 | |||
5354 | serge | 1820 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
1821 | { |
||
1822 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; |
||
1823 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; |
||
1824 | |||
1825 | if (gen9_gmch_ctl < 0xf0) |
||
1826 | return gen9_gmch_ctl << 25; /* 32 MB units */ |
||
1827 | else |
||
1828 | /* 4MB increments starting at 0xf0 for 4MB */ |
||
1829 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; |
||
1830 | } |
||
1831 | |||
4560 | Serge | 1832 | static int ggtt_probe_common(struct drm_device *dev, |
1833 | size_t gtt_size) |
||
1834 | { |
||
1835 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1836 | phys_addr_t gtt_phys_addr; |
||
1837 | int ret; |
||
1838 | |||
1839 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
||
1840 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
||
1841 | (pci_resource_len(dev->pdev, 0) / 2); |
||
1842 | |||
1843 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
||
1844 | if (!dev_priv->gtt.gsm) { |
||
1845 | DRM_ERROR("Failed to map the gtt page table\n"); |
||
1846 | return -ENOMEM; |
||
1847 | } |
||
1848 | |||
1849 | ret = setup_scratch_page(dev); |
||
1850 | if (ret) { |
||
1851 | DRM_ERROR("Scratch setup failed\n"); |
||
1852 | /* iounmap will also get called at remove, but meh */ |
||
1853 | iounmap(dev_priv->gtt.gsm); |
||
1854 | } |
||
1855 | |||
1856 | return ret; |
||
1857 | } |
||
1858 | |||
1859 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
||
1860 | * bits. When using advanced contexts each context stores its own PAT, but |
||
1861 | * writing this data shouldn't be harmful even in those cases. */ |
||
5060 | serge | 1862 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
4560 | Serge | 1863 | { |
1864 | uint64_t pat; |
||
1865 | |||
1866 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ |
||
1867 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ |
||
1868 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ |
||
1869 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ |
||
1870 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | |
||
1871 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | |
||
1872 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | |
||
1873 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); |
||
1874 | |||
5354 | serge | 1875 | if (!USES_PPGTT(dev_priv->dev)) |
1876 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
||
1877 | * so RTL will always use the value corresponding to |
||
1878 | * pat_sel = 000". |
||
1879 | * So let's disable cache for GGTT to avoid screen corruptions. |
||
1880 | * MOCS still can be used though. |
||
1881 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work |
||
1882 | * before this patch, i.e. the same uncached + snooping access |
||
1883 | * like on gen6/7 seems to be in effect. |
||
1884 | * - So this just fixes blitter/render access. Again it looks |
||
1885 | * like it's not just uncached access, but uncached + snooping. |
||
1886 | * So we can still hold onto all our assumptions wrt cpu |
||
1887 | * clflushing on LLC machines. |
||
1888 | */ |
||
1889 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); |
||
1890 | |||
4560 | Serge | 1891 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
1892 | * write would work. */ |
||
1893 | I915_WRITE(GEN8_PRIVATE_PAT, pat); |
||
1894 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); |
||
1895 | } |
||
1896 | |||
5060 | serge | 1897 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
1898 | { |
||
1899 | uint64_t pat; |
||
1900 | |||
1901 | /* |
||
1902 | * Map WB on BDW to snooped on CHV. |
||
1903 | * |
||
1904 | * Only the snoop bit has meaning for CHV, the rest is |
||
1905 | * ignored. |
||
1906 | * |
||
5354 | serge | 1907 | * The hardware will never snoop for certain types of accesses: |
1908 | * - CPU GTT (GMADR->GGTT->no snoop->memory) |
||
1909 | * - PPGTT page tables |
||
1910 | * - some other special cycles |
||
1911 | * |
||
1912 | * As with BDW, we also need to consider the following for GT accesses: |
||
1913 | * "For GGTT, there is NO pat_sel[2:0] from the entry, |
||
1914 | * so RTL will always use the value corresponding to |
||
1915 | * pat_sel = 000". |
||
1916 | * Which means we must set the snoop bit in PAT entry 0 |
||
1917 | * in order to keep the global status page working. |
||
5060 | serge | 1918 | */ |
1919 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | |
||
1920 | GEN8_PPAT(1, 0) | |
||
1921 | GEN8_PPAT(2, 0) | |
||
1922 | GEN8_PPAT(3, 0) | |
||
1923 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | |
||
1924 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | |
||
1925 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | |
||
1926 | GEN8_PPAT(7, CHV_PPAT_SNOOP); |
||
1927 | |||
1928 | I915_WRITE(GEN8_PRIVATE_PAT, pat); |
||
1929 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); |
||
1930 | } |
||
1931 | |||
4560 | Serge | 1932 | static int gen8_gmch_probe(struct drm_device *dev, |
1933 | size_t *gtt_total, |
||
1934 | size_t *stolen, |
||
1935 | phys_addr_t *mappable_base, |
||
1936 | unsigned long *mappable_end) |
||
1937 | { |
||
1938 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1939 | unsigned int gtt_size; |
||
1940 | u16 snb_gmch_ctl; |
||
1941 | int ret; |
||
1942 | |||
1943 | /* TODO: We're not aware of mappable constraints on gen8 yet */ |
||
1944 | *mappable_base = pci_resource_start(dev->pdev, 2); |
||
1945 | *mappable_end = pci_resource_len(dev->pdev, 2); |
||
1946 | |||
1947 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) |
||
1948 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); |
||
1949 | |||
1950 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
||
1951 | |||
5354 | serge | 1952 | if (INTEL_INFO(dev)->gen >= 9) { |
1953 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); |
||
1954 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); |
||
1955 | } else if (IS_CHERRYVIEW(dev)) { |
||
5060 | serge | 1956 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
1957 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); |
||
1958 | } else { |
||
4560 | Serge | 1959 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); |
5060 | serge | 1960 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); |
1961 | } |
||
4560 | Serge | 1962 | |
1963 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
||
1964 | |||
5060 | serge | 1965 | if (IS_CHERRYVIEW(dev)) |
1966 | chv_setup_private_ppat(dev_priv); |
||
1967 | else |
||
1968 | bdw_setup_private_ppat(dev_priv); |
||
4560 | Serge | 1969 | |
1970 | ret = ggtt_probe_common(dev, gtt_size); |
||
1971 | |||
1972 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
||
1973 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; |
||
1974 | |||
1975 | return ret; |
||
1976 | } |
||
1977 | |||
3480 | Serge | 1978 | static int gen6_gmch_probe(struct drm_device *dev, |
1979 | size_t *gtt_total, |
||
1980 | size_t *stolen, |
||
1981 | phys_addr_t *mappable_base, |
||
1982 | unsigned long *mappable_end) |
||
3243 | Serge | 1983 | { |
1984 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3480 | Serge | 1985 | unsigned int gtt_size; |
3243 | Serge | 1986 | u16 snb_gmch_ctl; |
1987 | int ret; |
||
1988 | |||
3480 | Serge | 1989 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1990 | *mappable_end = pci_resource_len(dev->pdev, 2); |
||
1991 | |||
1992 | /* 64/512MB is the current min/max we actually know of, but this is just |
||
1993 | * a coarse sanity check. |
||
3243 | Serge | 1994 | */ |
3480 | Serge | 1995 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
1996 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
||
1997 | dev_priv->gtt.mappable_end); |
||
1998 | return -ENXIO; |
||
3243 | Serge | 1999 | } |
2000 | |||
3480 | Serge | 2001 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2002 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); |
||
2003 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
||
3243 | Serge | 2004 | |
4104 | Serge | 2005 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
4560 | Serge | 2006 | |
2007 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
||
3746 | Serge | 2008 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
3243 | Serge | 2009 | |
4560 | Serge | 2010 | ret = ggtt_probe_common(dev, gtt_size); |
3243 | Serge | 2011 | |
4104 | Serge | 2012 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2013 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; |
||
3480 | Serge | 2014 | |
2015 | return ret; |
||
2016 | } |
||
2017 | |||
4104 | Serge | 2018 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3480 | Serge | 2019 | { |
4104 | Serge | 2020 | |
2021 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); |
||
5060 | serge | 2022 | |
4104 | Serge | 2023 | iounmap(gtt->gsm); |
2024 | teardown_scratch_page(vm->dev); |
||
3480 | Serge | 2025 | } |
2026 | |||
2027 | static int i915_gmch_probe(struct drm_device *dev, |
||
2028 | size_t *gtt_total, |
||
2029 | size_t *stolen, |
||
2030 | phys_addr_t *mappable_base, |
||
2031 | unsigned long *mappable_end) |
||
2032 | { |
||
2033 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2034 | int ret; |
||
2035 | |||
2036 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
||
2037 | if (!ret) { |
||
2038 | DRM_ERROR("failed to set up gmch\n"); |
||
2039 | return -EIO; |
||
3243 | Serge | 2040 | } |
2041 | |||
3480 | Serge | 2042 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
3243 | Serge | 2043 | |
3480 | Serge | 2044 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); |
4104 | Serge | 2045 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
3480 | Serge | 2046 | |
4560 | Serge | 2047 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2048 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
||
2049 | |||
3243 | Serge | 2050 | return 0; |
3480 | Serge | 2051 | } |
3243 | Serge | 2052 | |
4104 | Serge | 2053 | static void i915_gmch_remove(struct i915_address_space *vm) |
3480 | Serge | 2054 | { |
4560 | Serge | 2055 | // intel_gmch_remove(); |
3480 | Serge | 2056 | } |
2057 | |||
2058 | int i915_gem_gtt_init(struct drm_device *dev) |
||
2059 | { |
||
2060 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2061 | struct i915_gtt *gtt = &dev_priv->gtt; |
||
2062 | int ret; |
||
2063 | |||
2064 | if (INTEL_INFO(dev)->gen <= 5) { |
||
4104 | Serge | 2065 | gtt->gtt_probe = i915_gmch_probe; |
2066 | gtt->base.cleanup = i915_gmch_remove; |
||
4560 | Serge | 2067 | } else if (INTEL_INFO(dev)->gen < 8) { |
4104 | Serge | 2068 | gtt->gtt_probe = gen6_gmch_probe; |
2069 | gtt->base.cleanup = gen6_gmch_remove; |
||
2070 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
||
2071 | gtt->base.pte_encode = iris_pte_encode; |
||
2072 | else if (IS_HASWELL(dev)) |
||
2073 | gtt->base.pte_encode = hsw_pte_encode; |
||
2074 | else if (IS_VALLEYVIEW(dev)) |
||
2075 | gtt->base.pte_encode = byt_pte_encode; |
||
2076 | else if (INTEL_INFO(dev)->gen >= 7) |
||
2077 | gtt->base.pte_encode = ivb_pte_encode; |
||
2078 | else |
||
2079 | gtt->base.pte_encode = snb_pte_encode; |
||
4560 | Serge | 2080 | } else { |
2081 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; |
||
2082 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; |
||
3480 | Serge | 2083 | } |
2084 | |||
4104 | Serge | 2085 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
2086 | >t->mappable_base, >t->mappable_end); |
||
3480 | Serge | 2087 | if (ret) |
4104 | Serge | 2088 | return ret; |
3480 | Serge | 2089 | |
4104 | Serge | 2090 | gtt->base.dev = dev; |
2091 | |||
3480 | Serge | 2092 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
2093 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
||
4104 | Serge | 2094 | gtt->base.total >> 20); |
2095 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
||
2096 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
||
5060 | serge | 2097 | #ifdef CONFIG_INTEL_IOMMU |
2098 | if (intel_iommu_gfx_mapped) |
||
2099 | DRM_INFO("VT-d active for gfx access\n"); |
||
2100 | #endif |
||
2101 | /* |
||
2102 | * i915.enable_ppgtt is read-only, so do an early pass to validate the |
||
2103 | * user's requested state against the hardware/driver capabilities. We |
||
2104 | * do this now so that we can print out any log messages once rather |
||
2105 | * than every time we check intel_enable_ppgtt(). |
||
2106 | */ |
||
2107 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); |
||
2108 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); |
||
3480 | Serge | 2109 | |
2110 | return 0; |
||
3243 | Serge | 2111 | } |
2112 | |||
5060 | serge | 2113 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, |
2114 | struct i915_address_space *vm) |
||
2115 | { |
||
2116 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
||
2117 | if (vma == NULL) |
||
2118 | return ERR_PTR(-ENOMEM); |
||
2119 | |||
2120 | INIT_LIST_HEAD(&vma->vma_link); |
||
2121 | INIT_LIST_HEAD(&vma->mm_list); |
||
2122 | INIT_LIST_HEAD(&vma->exec_list); |
||
2123 | vma->vm = vm; |
||
2124 | vma->obj = obj; |
||
2125 | |||
2126 | switch (INTEL_INFO(vm->dev)->gen) { |
||
5354 | serge | 2127 | case 9: |
5060 | serge | 2128 | case 8: |
2129 | case 7: |
||
2130 | case 6: |
||
2131 | if (i915_is_ggtt(vm)) { |
||
2132 | vma->unbind_vma = ggtt_unbind_vma; |
||
2133 | vma->bind_vma = ggtt_bind_vma; |
||
2134 | } else { |
||
2135 | vma->unbind_vma = ppgtt_unbind_vma; |
||
2136 | vma->bind_vma = ppgtt_bind_vma; |
||
2137 | } |
||
2138 | break; |
||
2139 | case 5: |
||
2140 | case 4: |
||
2141 | case 3: |
||
2142 | case 2: |
||
2143 | BUG_ON(!i915_is_ggtt(vm)); |
||
2144 | vma->unbind_vma = i915_ggtt_unbind_vma; |
||
2145 | vma->bind_vma = i915_ggtt_bind_vma; |
||
2146 | break; |
||
2147 | default: |
||
2148 | BUG(); |
||
2149 | } |
||
2150 | |||
2151 | /* Keep GGTT vmas first to make debug easier */ |
||
2152 | if (i915_is_ggtt(vm)) |
||
2153 | list_add(&vma->vma_link, &obj->vma_list); |
||
5354 | serge | 2154 | else { |
5060 | serge | 2155 | list_add_tail(&vma->vma_link, &obj->vma_list); |
5354 | serge | 2156 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
2157 | } |
||
5060 | serge | 2158 | |
2159 | return vma; |
||
2160 | } |
||
2161 | |||
2162 | struct i915_vma * |
||
2163 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
||
2164 | struct i915_address_space *vm) |
||
2165 | { |
||
2166 | struct i915_vma *vma; |
||
2167 | |||
2168 | vma = i915_gem_obj_to_vma(obj, vm); |
||
2169 | if (!vma) |
||
2170 | vma = __i915_gem_vma_create(obj, vm); |
||
2171 | |||
2172 | return vma; |
||
2173 | } |
||
2174 | |||
3243 | Serge | 2175 | struct scatterlist *sg_next(struct scatterlist *sg) |
2176 | { |
||
2177 | if (sg_is_last(sg)) |
||
2178 | return NULL; |
||
2179 | |||
2180 | sg++; |
||
2181 | if (unlikely(sg_is_chain(sg))) |
||
2182 | sg = sg_chain_ptr(sg); |
||
2183 | |||
2184 | return sg; |
||
2185 | } |
||
2186 | |||
2187 | |||
2188 | void __sg_free_table(struct sg_table *table, unsigned int max_ents, |
||
5060 | serge | 2189 | bool skip_first_chunk, sg_free_fn *free_fn) |
3243 | Serge | 2190 | { |
2191 | struct scatterlist *sgl, *next; |
||
2192 | |||
2193 | if (unlikely(!table->sgl)) |
||
5060 | serge | 2194 | return; |
3243 | Serge | 2195 | |
2196 | sgl = table->sgl; |
||
2197 | while (table->orig_nents) { |
||
2198 | unsigned int alloc_size = table->orig_nents; |
||
2199 | unsigned int sg_size; |
||
2200 | |||
2201 | /* |
||
2202 | * If we have more than max_ents segments left, |
||
2203 | * then assign 'next' to the sg table after the current one. |
||
2204 | * sg_size is then one less than alloc size, since the last |
||
2205 | * element is the chain pointer. |
||
2206 | */ |
||
2207 | if (alloc_size > max_ents) { |
||
5060 | serge | 2208 | next = sg_chain_ptr(&sgl[max_ents - 1]); |
2209 | alloc_size = max_ents; |
||
2210 | sg_size = alloc_size - 1; |
||
3243 | Serge | 2211 | } else { |
5060 | serge | 2212 | sg_size = alloc_size; |
2213 | next = NULL; |
||
3243 | Serge | 2214 | } |
2215 | |||
2216 | table->orig_nents -= sg_size; |
||
5060 | serge | 2217 | if (!skip_first_chunk) { |
2218 | kfree(sgl); |
||
2219 | skip_first_chunk = false; |
||
2220 | } |
||
3243 | Serge | 2221 | sgl = next; |
2222 | } |
||
2223 | |||
2224 | table->sgl = NULL; |
||
2225 | } |
||
2226 | void sg_free_table(struct sg_table *table) |
||
2227 | { |
||
5060 | serge | 2228 | __sg_free_table(table, SG_MAX_SINGLE_ALLOC, false, NULL); |
3243 | Serge | 2229 | } |
2230 | |||
2231 | int sg_alloc_table(struct sg_table *table, unsigned int nents, gfp_t gfp_mask) |
||
2232 | { |
||
2233 | struct scatterlist *sg, *prv; |
||
2234 | unsigned int left; |
||
2235 | unsigned int max_ents = SG_MAX_SINGLE_ALLOC; |
||
2236 | |||
2237 | #ifndef ARCH_HAS_SG_CHAIN |
||
2238 | BUG_ON(nents > max_ents); |
||
2239 | #endif |
||
2240 | |||
2241 | memset(table, 0, sizeof(*table)); |
||
2242 | |||
2243 | left = nents; |
||
2244 | prv = NULL; |
||
2245 | do { |
||
2246 | unsigned int sg_size, alloc_size = left; |
||
2247 | |||
2248 | if (alloc_size > max_ents) { |
||
2249 | alloc_size = max_ents; |
||
2250 | sg_size = alloc_size - 1; |
||
2251 | } else |
||
2252 | sg_size = alloc_size; |
||
2253 | |||
2254 | left -= sg_size; |
||
2255 | |||
2256 | sg = kmalloc(alloc_size * sizeof(struct scatterlist), gfp_mask); |
||
2257 | if (unlikely(!sg)) { |
||
2258 | /* |
||
2259 | * Adjust entry count to reflect that the last |
||
2260 | * entry of the previous table won't be used for |
||
2261 | * linkage. Without this, sg_kfree() may get |
||
2262 | * confused. |
||
2263 | */ |
||
2264 | if (prv) |
||
2265 | table->nents = ++table->orig_nents; |
||
2266 | |||
2267 | goto err; |
||
2268 | } |
||
2269 | |||
2270 | sg_init_table(sg, alloc_size); |
||
2271 | table->nents = table->orig_nents += sg_size; |
||
2272 | |||
2273 | /* |
||
2274 | * If this is the first mapping, assign the sg table header. |
||
2275 | * If this is not the first mapping, chain previous part. |
||
2276 | */ |
||
2277 | if (prv) |
||
2278 | sg_chain(prv, max_ents, sg); |
||
2279 | else |
||
2280 | table->sgl = sg; |
||
2281 | |||
2282 | /* |
||
2283 | * If no more entries after this one, mark the end |
||
2284 | */ |
||
2285 | if (!left) |
||
2286 | sg_mark_end(&sg[sg_size - 1]); |
||
2287 | |||
2288 | prv = sg; |
||
2289 | } while (left); |
||
2290 | |||
2291 | return 0; |
||
2292 | |||
2293 | err: |
||
5060 | serge | 2294 | __sg_free_table(table, SG_MAX_SINGLE_ALLOC, false, NULL); |
3243 | Serge | 2295 | |
2296 | return -ENOMEM; |
||
2297 | } |
||
2298 | |||
2299 | |||
2300 | void sg_init_table(struct scatterlist *sgl, unsigned int nents) |
||
2301 | { |
||
2302 | memset(sgl, 0, sizeof(*sgl) * nents); |
||
2303 | #ifdef CONFIG_DEBUG_SG |
||
2304 | { |
||
2305 | unsigned int i; |
||
2306 | for (i = 0; i < nents; i++) |
||
2307 | sgl[i].sg_magic = SG_MAGIC; |
||
2308 | } |
||
2309 | #endif |
||
2310 | sg_mark_end(&sgl[nents - 1]); |
||
2311 | } |
||
2312 | |||
3746 | Serge | 2313 | |
2314 | void __sg_page_iter_start(struct sg_page_iter *piter, |
||
2315 | struct scatterlist *sglist, unsigned int nents, |
||
2316 | unsigned long pgoffset) |
||
2317 | { |
||
2318 | piter->__pg_advance = 0; |
||
2319 | piter->__nents = nents; |
||
2320 | |||
2321 | piter->sg = sglist; |
||
2322 | piter->sg_pgoffset = pgoffset; |
||
2323 | } |
||
2324 | |||
2325 | static int sg_page_count(struct scatterlist *sg) |
||
2326 | { |
||
2327 | return PAGE_ALIGN(sg->offset + sg->length) >> PAGE_SHIFT; |
||
2328 | } |
||
2329 | |||
2330 | bool __sg_page_iter_next(struct sg_page_iter *piter) |
||
2331 | { |
||
2332 | if (!piter->__nents || !piter->sg) |
||
2333 | return false; |
||
2334 | |||
2335 | piter->sg_pgoffset += piter->__pg_advance; |
||
2336 | piter->__pg_advance = 1; |
||
2337 | |||
2338 | while (piter->sg_pgoffset >= sg_page_count(piter->sg)) { |
||
2339 | piter->sg_pgoffset -= sg_page_count(piter->sg); |
||
2340 | piter->sg = sg_next(piter->sg); |
||
2341 | if (!--piter->__nents || !piter->sg) |
||
2342 | return false; |
||
2343 | } |
||
2344 | |||
2345 | return true; |
||
2346 | } |
||
2347 | EXPORT_SYMBOL(__sg_page_iter_next);>>=>><>20))))><20))))>20)><20)>>><>><>><>>><>><>>><>>><>><>><>><>><>><>><>>>><>>>>>><>>>>>>>><>>30)); |
||
2348 | |||
2349 |