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2332 | Serge | 1 | /* |
2 | * Copyright © 2010 Daniel Vetter |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | */ |
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24 | |||
25 | #include "drmP.h" |
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26 | #include "drm.h" |
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27 | #include "i915_drm.h" |
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28 | #include "i915_drv.h" |
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29 | //#include "i915_trace.h" |
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30 | #include "intel_drv.h" |
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31 | |||
32 | #define AGP_USER_TYPES (1 << 16) |
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33 | #define AGP_USER_MEMORY (AGP_USER_TYPES) |
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34 | #define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1) |
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35 | |||
36 | /* XXX kill agp_type! */ |
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37 | static unsigned int cache_level_to_agp_type(struct drm_device *dev, |
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38 | enum i915_cache_level cache_level) |
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39 | { |
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40 | switch (cache_level) { |
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41 | case I915_CACHE_LLC_MLC: |
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42 | if (INTEL_INFO(dev)->gen >= 6) |
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43 | return AGP_USER_CACHED_MEMORY_LLC_MLC; |
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44 | /* Older chipsets do not have this extra level of CPU |
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45 | * cacheing, so fallthrough and request the PTE simply |
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46 | * as cached. |
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47 | */ |
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48 | case I915_CACHE_LLC: |
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49 | return AGP_USER_CACHED_MEMORY; |
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50 | default: |
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51 | case I915_CACHE_NONE: |
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52 | return AGP_USER_MEMORY; |
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53 | } |
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54 | } |
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55 | |||
56 | #if 0 |
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57 | |||
58 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
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59 | { |
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60 | struct drm_i915_private *dev_priv = dev->dev_private; |
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61 | struct drm_i915_gem_object *obj; |
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62 | |||
63 | /* First fill our portion of the GTT with scratch pages */ |
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64 | intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE, |
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65 | (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE); |
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66 | |||
67 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { |
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68 | i915_gem_clflush_object(obj); |
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69 | i915_gem_gtt_rebind_object(obj, obj->cache_level); |
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70 | } |
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71 | |||
72 | intel_gtt_chipset_flush(); |
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73 | } |
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74 | #endif |
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75 | |||
76 | int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj) |
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77 | { |
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78 | struct drm_device *dev = obj->base.dev; |
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79 | struct drm_i915_private *dev_priv = dev->dev_private; |
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80 | unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level); |
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81 | int ret; |
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82 | |||
83 | ENTER(); |
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84 | // if (dev_priv->mm.gtt->needs_dmar) { |
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85 | // ret = intel_gtt_map_memory(obj->pages, |
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86 | // obj->base.size >> PAGE_SHIFT, |
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87 | // &obj->sg_list, |
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88 | // &obj->num_sg); |
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89 | // if (ret != 0) |
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90 | // return ret; |
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91 | |||
92 | // intel_gtt_insert_sg_entries(obj->sg_list, |
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93 | // obj->num_sg, |
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94 | // obj->gtt_space->start >> PAGE_SHIFT, |
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95 | // agp_type); |
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96 | // } else |
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97 | intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT, |
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98 | obj->base.size >> PAGE_SHIFT, |
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99 | obj->pages, |
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100 | agp_type); |
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101 | LEAVE(); |
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102 | return 0; |
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103 | } |
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104 | |||
105 | #if 0 |
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106 | void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, |
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107 | enum i915_cache_level cache_level) |
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108 | { |
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109 | struct drm_device *dev = obj->base.dev; |
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110 | struct drm_i915_private *dev_priv = dev->dev_private; |
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111 | unsigned int agp_type = cache_level_to_agp_type(dev, cache_level); |
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112 | |||
113 | if (dev_priv->mm.gtt->needs_dmar) { |
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114 | BUG_ON(!obj->sg_list); |
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115 | |||
116 | intel_gtt_insert_sg_entries(obj->sg_list, |
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117 | obj->num_sg, |
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118 | obj->gtt_space->start >> PAGE_SHIFT, |
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119 | agp_type); |
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120 | } else |
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121 | intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT, |
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122 | obj->base.size >> PAGE_SHIFT, |
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123 | obj->pages, |
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124 | agp_type); |
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125 | } |
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126 | |||
127 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
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128 | { |
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129 | intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT, |
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130 | obj->base.size >> PAGE_SHIFT); |
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131 | |||
132 | if (obj->sg_list) { |
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133 | intel_gtt_unmap_memory(obj->sg_list, obj->num_sg); |
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134 | obj->sg_list = NULL; |
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135 | } |
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136 | } |
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137 | |||
138 | #endif><> |