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Rev | Author | Line No. | Line |
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3263 | Serge | 1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * Chris Wilson |
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26 | * |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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31 | #include "i915_drv.h" |
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32 | #include "i915_trace.h" |
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33 | #include "intel_drv.h" |
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34 | //#include |
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35 | |||
36 | #define I915_EXEC_SECURE (1<<9) |
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37 | #define I915_EXEC_IS_PINNED (1<<10) |
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4104 | Serge | 38 | #define I915_EXEC_VEBOX (4<<0) |
3263 | Serge | 39 | |
40 | #define wmb() asm volatile ("sfence") |
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41 | |||
42 | struct drm_i915_gem_object *get_fb_obj(); |
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43 | |||
44 | |||
45 | static unsigned long |
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46 | copy_to_user(void __user *to, const void *from, unsigned long n) |
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47 | { |
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48 | memcpy(to, from, n); |
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49 | return 0; |
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50 | } |
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51 | |||
52 | static unsigned long |
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53 | copy_from_user(void *to, const void __user *from, unsigned long n) |
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54 | { |
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55 | memcpy(to, from, n); |
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56 | return 0; |
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57 | } |
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58 | |||
59 | struct eb_objects { |
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3480 | Serge | 60 | struct list_head objects; |
3263 | Serge | 61 | int and; |
3480 | Serge | 62 | union { |
63 | struct drm_i915_gem_object *lut[0]; |
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3263 | Serge | 64 | struct hlist_head buckets[0]; |
3480 | Serge | 65 | }; |
3263 | Serge | 66 | }; |
67 | |||
68 | static struct eb_objects * |
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3480 | Serge | 69 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
3263 | Serge | 70 | { |
3480 | Serge | 71 | struct eb_objects *eb = NULL; |
72 | |||
73 | if (args->flags & I915_EXEC_HANDLE_LUT) { |
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74 | int size = args->buffer_count; |
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75 | size *= sizeof(struct drm_i915_gem_object *); |
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76 | size += sizeof(struct eb_objects); |
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77 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
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78 | } |
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79 | |||
80 | if (eb == NULL) { |
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81 | int size = args->buffer_count; |
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3263 | Serge | 82 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; |
3480 | Serge | 83 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
84 | while (count > 2*size) |
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3263 | Serge | 85 | count >>= 1; |
86 | eb = kzalloc(count*sizeof(struct hlist_head) + |
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87 | sizeof(struct eb_objects), |
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3480 | Serge | 88 | GFP_TEMPORARY); |
3263 | Serge | 89 | if (eb == NULL) |
90 | return eb; |
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91 | |||
92 | eb->and = count - 1; |
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3480 | Serge | 93 | } else |
94 | eb->and = -args->buffer_count; |
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95 | |||
96 | INIT_LIST_HEAD(&eb->objects); |
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3263 | Serge | 97 | return eb; |
98 | } |
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99 | |||
100 | static void |
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101 | eb_reset(struct eb_objects *eb) |
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102 | { |
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3480 | Serge | 103 | if (eb->and >= 0) |
3263 | Serge | 104 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); |
105 | } |
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106 | |||
3480 | Serge | 107 | static int |
108 | eb_lookup_objects(struct eb_objects *eb, |
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109 | struct drm_i915_gem_exec_object2 *exec, |
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110 | const struct drm_i915_gem_execbuffer2 *args, |
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111 | struct drm_file *file) |
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3263 | Serge | 112 | { |
3480 | Serge | 113 | int i; |
114 | |||
115 | spin_lock(&file->table_lock); |
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116 | for (i = 0; i < args->buffer_count; i++) { |
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117 | struct drm_i915_gem_object *obj; |
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118 | |||
119 | if(exec[i].handle == -2) |
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120 | obj = get_fb_obj(); |
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121 | else |
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122 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
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123 | if (obj == NULL) { |
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124 | spin_unlock(&file->table_lock); |
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125 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
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126 | exec[i].handle, i); |
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127 | return -ENOENT; |
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128 | } |
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129 | |||
130 | if (!list_empty(&obj->exec_list)) { |
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131 | spin_unlock(&file->table_lock); |
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132 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
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133 | obj, exec[i].handle, i); |
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134 | return -EINVAL; |
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135 | } |
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136 | |||
137 | drm_gem_object_reference(&obj->base); |
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138 | list_add_tail(&obj->exec_list, &eb->objects); |
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139 | |||
140 | obj->exec_entry = &exec[i]; |
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4246 | Serge | 141 | |
142 | if(exec[i].handle == -2) |
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143 | continue; |
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144 | |||
3480 | Serge | 145 | if (eb->and < 0) { |
146 | eb->lut[i] = obj; |
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147 | } else { |
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148 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; |
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149 | obj->exec_handle = handle; |
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3263 | Serge | 150 | hlist_add_head(&obj->exec_node, |
3480 | Serge | 151 | &eb->buckets[handle & eb->and]); |
152 | } |
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153 | } |
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154 | spin_unlock(&file->table_lock); |
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155 | |||
156 | return 0; |
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3263 | Serge | 157 | } |
158 | |||
159 | static struct drm_i915_gem_object * |
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160 | eb_get_object(struct eb_objects *eb, unsigned long handle) |
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161 | { |
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4246 | Serge | 162 | |
163 | if(handle == -2) |
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164 | return get_fb_obj(); |
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165 | |||
3480 | Serge | 166 | if (eb->and < 0) { |
167 | if (handle >= -eb->and) |
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168 | return NULL; |
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169 | return eb->lut[handle]; |
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170 | } else { |
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3263 | Serge | 171 | struct hlist_head *head; |
172 | struct hlist_node *node; |
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173 | |||
174 | head = &eb->buckets[handle & eb->and]; |
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175 | hlist_for_each(node, head) { |
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3480 | Serge | 176 | struct drm_i915_gem_object *obj; |
177 | |||
3263 | Serge | 178 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); |
179 | if (obj->exec_handle == handle) |
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180 | return obj; |
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181 | } |
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182 | return NULL; |
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3480 | Serge | 183 | } |
3263 | Serge | 184 | } |
185 | |||
186 | static void |
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187 | eb_destroy(struct eb_objects *eb) |
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188 | { |
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3480 | Serge | 189 | while (!list_empty(&eb->objects)) { |
190 | struct drm_i915_gem_object *obj; |
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191 | |||
192 | obj = list_first_entry(&eb->objects, |
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193 | struct drm_i915_gem_object, |
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194 | exec_list); |
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195 | list_del_init(&obj->exec_list); |
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196 | drm_gem_object_unreference(&obj->base); |
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197 | } |
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3263 | Serge | 198 | kfree(eb); |
199 | } |
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200 | |||
201 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
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202 | { |
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203 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || |
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204 | !obj->map_and_fenceable || |
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205 | obj->cache_level != I915_CACHE_NONE); |
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206 | } |
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207 | |||
208 | static int |
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209 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
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210 | struct eb_objects *eb, |
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4104 | Serge | 211 | struct drm_i915_gem_relocation_entry *reloc, |
212 | struct i915_address_space *vm) |
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3263 | Serge | 213 | { |
214 | struct drm_device *dev = obj->base.dev; |
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215 | struct drm_gem_object *target_obj; |
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216 | struct drm_i915_gem_object *target_i915_obj; |
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217 | uint32_t target_offset; |
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218 | int ret = -EINVAL; |
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219 | |||
220 | /* we've already hold a reference to all valid objects */ |
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221 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; |
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222 | if (unlikely(target_obj == NULL)) |
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223 | return -ENOENT; |
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224 | |||
225 | target_i915_obj = to_intel_bo(target_obj); |
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4104 | Serge | 226 | target_offset = i915_gem_obj_ggtt_offset(target_i915_obj); |
3263 | Serge | 227 | |
228 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
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229 | * pipe_control writes because the gpu doesn't properly redirect them |
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230 | * through the ppgtt for non_secure batchbuffers. */ |
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231 | if (unlikely(IS_GEN6(dev) && |
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232 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && |
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233 | !target_i915_obj->has_global_gtt_mapping)) { |
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234 | i915_gem_gtt_bind_object(target_i915_obj, |
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235 | target_i915_obj->cache_level); |
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236 | } |
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237 | |||
238 | /* Validate that the target is in a valid r/w GPU domain */ |
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239 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
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240 | DRM_DEBUG("reloc with multiple write domains: " |
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241 | "obj %p target %d offset %d " |
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242 | "read %08x write %08x", |
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243 | obj, reloc->target_handle, |
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244 | (int) reloc->offset, |
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245 | reloc->read_domains, |
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246 | reloc->write_domain); |
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247 | return ret; |
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248 | } |
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249 | if (unlikely((reloc->write_domain | reloc->read_domains) |
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250 | & ~I915_GEM_GPU_DOMAINS)) { |
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251 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
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252 | "obj %p target %d offset %d " |
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253 | "read %08x write %08x", |
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254 | obj, reloc->target_handle, |
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255 | (int) reloc->offset, |
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256 | reloc->read_domains, |
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257 | reloc->write_domain); |
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258 | return ret; |
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259 | } |
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260 | |||
261 | target_obj->pending_read_domains |= reloc->read_domains; |
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262 | target_obj->pending_write_domain |= reloc->write_domain; |
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263 | |||
264 | /* If the relocation already has the right value in it, no |
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265 | * more work needs to be done. |
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266 | */ |
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267 | if (target_offset == reloc->presumed_offset) |
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268 | return 0; |
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269 | |||
270 | /* Check that the relocation address is valid... */ |
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271 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
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272 | DRM_DEBUG("Relocation beyond object bounds: " |
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273 | "obj %p target %d offset %d size %d.\n", |
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274 | obj, reloc->target_handle, |
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275 | (int) reloc->offset, |
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276 | (int) obj->base.size); |
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277 | return ret; |
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278 | } |
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279 | if (unlikely(reloc->offset & 3)) { |
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280 | DRM_DEBUG("Relocation not 4-byte aligned: " |
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281 | "obj %p target %d offset %d.\n", |
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282 | obj, reloc->target_handle, |
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283 | (int) reloc->offset); |
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284 | return ret; |
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285 | } |
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286 | |||
287 | /* We can't wait for rendering with pagefaults disabled */ |
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288 | |||
289 | reloc->delta += target_offset; |
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290 | if (use_cpu_reloc(obj)) { |
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291 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
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292 | char *vaddr; |
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293 | |||
294 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
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295 | if (ret) |
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296 | return ret; |
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297 | |||
298 | vaddr = (char *)MapIoMem((addr_t)i915_gem_object_get_page(obj, |
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299 | reloc->offset >> PAGE_SHIFT), 4096, 3); |
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300 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
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301 | FreeKernelSpace(vaddr); |
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302 | } else { |
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303 | struct drm_i915_private *dev_priv = dev->dev_private; |
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304 | uint32_t __iomem *reloc_entry; |
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305 | void __iomem *reloc_page; |
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306 | |||
307 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
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308 | if (ret) |
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309 | return ret; |
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310 | |||
311 | ret = i915_gem_object_put_fence(obj); |
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312 | if (ret) |
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313 | return ret; |
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314 | |||
315 | /* Map the page containing the relocation we're going to perform. */ |
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4104 | Serge | 316 | reloc->offset += i915_gem_obj_ggtt_offset(obj); |
3263 | Serge | 317 | reloc_page = (void*)MapIoMem(reloc->offset & PAGE_MASK, 4096, 3); |
318 | reloc_entry = (uint32_t __iomem *) |
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319 | (reloc_page + (reloc->offset & ~PAGE_MASK)); |
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320 | iowrite32(reloc->delta, reloc_entry); |
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321 | FreeKernelSpace(reloc_page); |
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322 | } |
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323 | |||
324 | /* and update the user's relocation entry */ |
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325 | reloc->presumed_offset = target_offset; |
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326 | |||
327 | return 0; |
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328 | } |
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329 | |||
330 | static int |
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331 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, |
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4104 | Serge | 332 | struct eb_objects *eb, |
333 | struct i915_address_space *vm) |
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3263 | Serge | 334 | { |
335 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
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3266 | Serge | 336 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(64)]; |
3263 | Serge | 337 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
338 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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339 | int remain, ret; |
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340 | |||
341 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
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342 | |||
343 | remain = entry->relocation_count; |
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344 | while (remain) { |
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345 | struct drm_i915_gem_relocation_entry *r = stack_reloc; |
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346 | int count = remain; |
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347 | if (count > ARRAY_SIZE(stack_reloc)) |
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348 | count = ARRAY_SIZE(stack_reloc); |
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349 | remain -= count; |
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350 | |||
351 | memcpy(r, user_relocs, count*sizeof(r[0])); |
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352 | |||
353 | do { |
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354 | u64 offset = r->presumed_offset; |
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355 | |||
4104 | Serge | 356 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r, |
357 | vm); |
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3263 | Serge | 358 | if (ret) |
359 | return ret; |
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360 | |||
361 | memcpy(&user_relocs->presumed_offset, |
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362 | &r->presumed_offset, |
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363 | sizeof(r->presumed_offset)); |
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364 | |||
365 | user_relocs++; |
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366 | r++; |
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367 | } while (--count); |
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368 | } |
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369 | |||
370 | return 0; |
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371 | #undef N_RELOC |
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372 | } |
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373 | |||
374 | static int |
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375 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, |
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376 | struct eb_objects *eb, |
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4104 | Serge | 377 | struct drm_i915_gem_relocation_entry *relocs, |
378 | struct i915_address_space *vm) |
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3263 | Serge | 379 | { |
380 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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381 | int i, ret; |
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382 | |||
383 | for (i = 0; i < entry->relocation_count; i++) { |
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4104 | Serge | 384 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i], |
385 | vm); |
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3263 | Serge | 386 | if (ret) |
387 | return ret; |
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388 | } |
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389 | |||
390 | return 0; |
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391 | } |
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392 | |||
393 | static int |
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4104 | Serge | 394 | i915_gem_execbuffer_relocate(struct eb_objects *eb, |
395 | struct i915_address_space *vm) |
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3263 | Serge | 396 | { |
397 | struct drm_i915_gem_object *obj; |
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398 | int ret = 0; |
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399 | |||
400 | /* This is the fast path and we cannot handle a pagefault whilst |
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401 | * holding the struct mutex lest the user pass in the relocations |
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402 | * contained within a mmaped bo. For in such a case we, the page |
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403 | * fault handler would call i915_gem_fault() and we would try to |
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404 | * acquire the struct mutex again. Obviously this is bad and so |
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405 | * lockdep complains vehemently. |
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406 | */ |
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4104 | Serge | 407 | // pagefault_disable(); |
3480 | Serge | 408 | list_for_each_entry(obj, &eb->objects, exec_list) { |
4104 | Serge | 409 | ret = i915_gem_execbuffer_relocate_object(obj, eb, vm); |
3263 | Serge | 410 | if (ret) |
411 | break; |
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412 | } |
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413 | // pagefault_enable(); |
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414 | |||
415 | return ret; |
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416 | } |
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417 | |||
418 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
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419 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) |
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420 | |||
421 | static int |
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422 | need_reloc_mappable(struct drm_i915_gem_object *obj) |
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423 | { |
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424 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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425 | return entry->relocation_count && !use_cpu_reloc(obj); |
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426 | } |
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427 | |||
428 | static int |
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429 | i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, |
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3480 | Serge | 430 | struct intel_ring_buffer *ring, |
4104 | Serge | 431 | struct i915_address_space *vm, |
3480 | Serge | 432 | bool *need_reloc) |
3263 | Serge | 433 | { |
434 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
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435 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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436 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
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437 | bool need_fence, need_mappable; |
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438 | int ret; |
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439 | |||
440 | need_fence = |
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441 | has_fenced_gpu_access && |
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442 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
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443 | obj->tiling_mode != I915_TILING_NONE; |
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444 | need_mappable = need_fence || need_reloc_mappable(obj); |
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445 | |||
4104 | Serge | 446 | ret = i915_gem_object_pin(obj, vm, entry->alignment, need_mappable, |
447 | false); |
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3263 | Serge | 448 | if (ret) |
449 | return ret; |
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450 | |||
451 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
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452 | |||
453 | if (has_fenced_gpu_access) { |
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454 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
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455 | ret = i915_gem_object_get_fence(obj); |
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456 | if (ret) |
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457 | return ret; |
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458 | |||
459 | if (i915_gem_object_pin_fence(obj)) |
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460 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
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461 | |||
462 | obj->pending_fenced_gpu_access = true; |
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463 | } |
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464 | } |
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465 | |||
466 | /* Ensure ppgtt mapping exists if needed */ |
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467 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { |
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468 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
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469 | obj, obj->cache_level); |
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470 | |||
471 | obj->has_aliasing_ppgtt_mapping = 1; |
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472 | } |
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473 | |||
4104 | Serge | 474 | if (entry->offset != i915_gem_obj_offset(obj, vm)) { |
475 | entry->offset = i915_gem_obj_offset(obj, vm); |
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3480 | Serge | 476 | *need_reloc = true; |
477 | } |
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3266 | Serge | 478 | |
3480 | Serge | 479 | if (entry->flags & EXEC_OBJECT_WRITE) { |
480 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; |
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481 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; |
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482 | } |
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483 | |||
484 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT && |
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485 | !obj->has_global_gtt_mapping) |
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486 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
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487 | |||
3263 | Serge | 488 | return 0; |
489 | } |
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490 | |||
491 | static void |
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492 | i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) |
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493 | { |
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494 | struct drm_i915_gem_exec_object2 *entry; |
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495 | |||
4104 | Serge | 496 | if (!i915_gem_obj_bound_any(obj)) |
3263 | Serge | 497 | return; |
498 | |||
499 | entry = obj->exec_entry; |
||
500 | |||
501 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) |
||
502 | i915_gem_object_unpin_fence(obj); |
||
503 | |||
504 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) |
||
505 | i915_gem_object_unpin(obj); |
||
506 | |||
507 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
||
508 | } |
||
509 | |||
510 | static int |
||
511 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
||
3480 | Serge | 512 | struct list_head *objects, |
4104 | Serge | 513 | struct i915_address_space *vm, |
3480 | Serge | 514 | bool *need_relocs) |
3263 | Serge | 515 | { |
516 | struct drm_i915_gem_object *obj; |
||
517 | struct list_head ordered_objects; |
||
518 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
||
519 | int retry; |
||
520 | |||
521 | INIT_LIST_HEAD(&ordered_objects); |
||
522 | while (!list_empty(objects)) { |
||
523 | struct drm_i915_gem_exec_object2 *entry; |
||
524 | bool need_fence, need_mappable; |
||
525 | |||
526 | obj = list_first_entry(objects, |
||
527 | struct drm_i915_gem_object, |
||
528 | exec_list); |
||
529 | entry = obj->exec_entry; |
||
530 | |||
531 | need_fence = |
||
532 | has_fenced_gpu_access && |
||
533 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
||
534 | obj->tiling_mode != I915_TILING_NONE; |
||
535 | need_mappable = need_fence || need_reloc_mappable(obj); |
||
536 | |||
537 | if (need_mappable) |
||
538 | list_move(&obj->exec_list, &ordered_objects); |
||
539 | else |
||
540 | list_move_tail(&obj->exec_list, &ordered_objects); |
||
541 | |||
3480 | Serge | 542 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
3263 | Serge | 543 | obj->base.pending_write_domain = 0; |
544 | obj->pending_fenced_gpu_access = false; |
||
545 | } |
||
546 | list_splice(&ordered_objects, objects); |
||
547 | |||
548 | /* Attempt to pin all of the buffers into the GTT. |
||
549 | * This is done in 3 phases: |
||
550 | * |
||
551 | * 1a. Unbind all objects that do not match the GTT constraints for |
||
552 | * the execbuffer (fenceable, mappable, alignment etc). |
||
553 | * 1b. Increment pin count for already bound objects. |
||
554 | * 2. Bind new objects. |
||
555 | * 3. Decrement pin count. |
||
556 | * |
||
557 | * This avoid unnecessary unbinding of later objects in order to make |
||
558 | * room for the earlier objects *unless* we need to defragment. |
||
559 | */ |
||
560 | retry = 0; |
||
561 | do { |
||
562 | int ret = 0; |
||
563 | |||
564 | /* Unbind any ill-fitting objects or pin. */ |
||
565 | list_for_each_entry(obj, objects, exec_list) { |
||
566 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
||
567 | bool need_fence, need_mappable; |
||
4104 | Serge | 568 | u32 obj_offset; |
3263 | Serge | 569 | |
4104 | Serge | 570 | if (!i915_gem_obj_bound(obj, vm)) |
3263 | Serge | 571 | continue; |
572 | |||
4104 | Serge | 573 | obj_offset = i915_gem_obj_offset(obj, vm); |
3263 | Serge | 574 | need_fence = |
575 | has_fenced_gpu_access && |
||
576 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
||
577 | obj->tiling_mode != I915_TILING_NONE; |
||
578 | need_mappable = need_fence || need_reloc_mappable(obj); |
||
579 | |||
4246 | Serge | 580 | WARN_ON((need_mappable || need_fence) && |
581 | !i915_is_ggtt(vm)); |
||
4104 | Serge | 582 | |
583 | if ((entry->alignment && |
||
584 | obj_offset & (entry->alignment - 1)) || |
||
3263 | Serge | 585 | (need_mappable && !obj->map_and_fenceable)) |
4104 | Serge | 586 | ret = i915_vma_unbind(i915_gem_obj_to_vma(obj, vm)); |
3263 | Serge | 587 | else |
4104 | Serge | 588 | ret = i915_gem_execbuffer_reserve_object(obj, ring, vm, need_relocs); |
3263 | Serge | 589 | if (ret) |
590 | goto err; |
||
591 | } |
||
592 | |||
593 | /* Bind fresh objects */ |
||
594 | list_for_each_entry(obj, objects, exec_list) { |
||
4104 | Serge | 595 | if (i915_gem_obj_bound(obj, vm)) |
3263 | Serge | 596 | continue; |
597 | |||
4104 | Serge | 598 | ret = i915_gem_execbuffer_reserve_object(obj, ring, vm, need_relocs); |
3263 | Serge | 599 | if (ret) |
600 | goto err; |
||
601 | } |
||
602 | |||
603 | err: /* Decrement pin count for bound objects */ |
||
604 | list_for_each_entry(obj, objects, exec_list) |
||
605 | i915_gem_execbuffer_unreserve_object(obj); |
||
606 | |||
607 | if (ret != -ENOSPC || retry++) |
||
608 | return ret; |
||
609 | |||
610 | // ret = i915_gem_evict_everything(ring->dev); |
||
611 | if (ret) |
||
612 | return ret; |
||
613 | } while (1); |
||
614 | } |
||
615 | |||
616 | static int |
||
617 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, |
||
3480 | Serge | 618 | struct drm_i915_gem_execbuffer2 *args, |
3263 | Serge | 619 | struct drm_file *file, |
620 | struct intel_ring_buffer *ring, |
||
621 | struct eb_objects *eb, |
||
4104 | Serge | 622 | struct drm_i915_gem_exec_object2 *exec, |
623 | struct i915_address_space *vm) |
||
3263 | Serge | 624 | { |
625 | struct drm_i915_gem_relocation_entry *reloc; |
||
626 | struct drm_i915_gem_object *obj; |
||
3480 | Serge | 627 | bool need_relocs; |
3263 | Serge | 628 | int *reloc_offset; |
629 | int i, total, ret; |
||
3480 | Serge | 630 | int count = args->buffer_count; |
3263 | Serge | 631 | |
632 | /* We may process another execbuffer during the unlock... */ |
||
3480 | Serge | 633 | while (!list_empty(&eb->objects)) { |
634 | obj = list_first_entry(&eb->objects, |
||
3263 | Serge | 635 | struct drm_i915_gem_object, |
636 | exec_list); |
||
637 | list_del_init(&obj->exec_list); |
||
638 | drm_gem_object_unreference(&obj->base); |
||
639 | } |
||
640 | |||
641 | mutex_unlock(&dev->struct_mutex); |
||
642 | |||
643 | total = 0; |
||
644 | for (i = 0; i < count; i++) |
||
645 | total += exec[i].relocation_count; |
||
646 | |||
647 | reloc_offset = malloc(count * sizeof(*reloc_offset)); |
||
648 | reloc = malloc(total * sizeof(*reloc)); |
||
649 | if (reloc == NULL || reloc_offset == NULL) { |
||
3266 | Serge | 650 | kfree(reloc); |
651 | kfree(reloc_offset); |
||
3263 | Serge | 652 | mutex_lock(&dev->struct_mutex); |
653 | return -ENOMEM; |
||
654 | } |
||
655 | |||
656 | total = 0; |
||
657 | for (i = 0; i < count; i++) { |
||
658 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
||
659 | u64 invalid_offset = (u64)-1; |
||
660 | int j; |
||
661 | |||
662 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
||
663 | |||
664 | if (copy_from_user(reloc+total, user_relocs, |
||
665 | exec[i].relocation_count * sizeof(*reloc))) { |
||
666 | ret = -EFAULT; |
||
667 | mutex_lock(&dev->struct_mutex); |
||
668 | goto err; |
||
669 | } |
||
670 | |||
671 | /* As we do not update the known relocation offsets after |
||
672 | * relocating (due to the complexities in lock handling), |
||
673 | * we need to mark them as invalid now so that we force the |
||
674 | * relocation processing next time. Just in case the target |
||
675 | * object is evicted and then rebound into its old |
||
676 | * presumed_offset before the next execbuffer - if that |
||
677 | * happened we would make the mistake of assuming that the |
||
678 | * relocations were valid. |
||
679 | */ |
||
680 | for (j = 0; j < exec[i].relocation_count; j++) { |
||
681 | if (copy_to_user(&user_relocs[j].presumed_offset, |
||
682 | &invalid_offset, |
||
683 | sizeof(invalid_offset))) { |
||
684 | ret = -EFAULT; |
||
685 | mutex_lock(&dev->struct_mutex); |
||
686 | goto err; |
||
687 | } |
||
688 | } |
||
689 | |||
690 | reloc_offset[i] = total; |
||
691 | total += exec[i].relocation_count; |
||
692 | } |
||
693 | |||
694 | ret = i915_mutex_lock_interruptible(dev); |
||
695 | if (ret) { |
||
696 | mutex_lock(&dev->struct_mutex); |
||
697 | goto err; |
||
698 | } |
||
699 | |||
700 | /* reacquire the objects */ |
||
701 | eb_reset(eb); |
||
3480 | Serge | 702 | ret = eb_lookup_objects(eb, exec, args, file); |
703 | if (ret) |
||
3263 | Serge | 704 | goto err; |
705 | |||
3480 | Serge | 706 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
4104 | Serge | 707 | ret = i915_gem_execbuffer_reserve(ring, &eb->objects, vm, &need_relocs); |
3263 | Serge | 708 | if (ret) |
709 | goto err; |
||
710 | |||
3480 | Serge | 711 | list_for_each_entry(obj, &eb->objects, exec_list) { |
3263 | Serge | 712 | int offset = obj->exec_entry - exec; |
713 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
||
4104 | Serge | 714 | reloc + reloc_offset[offset], |
715 | vm); |
||
3263 | Serge | 716 | if (ret) |
717 | goto err; |
||
718 | } |
||
719 | |||
720 | /* Leave the user relocations as are, this is the painfully slow path, |
||
721 | * and we want to avoid the complication of dropping the lock whilst |
||
722 | * having buffers reserved in the aperture and so causing spurious |
||
723 | * ENOSPC for random operations. |
||
724 | */ |
||
725 | |||
726 | err: |
||
3266 | Serge | 727 | kfree(reloc); |
728 | kfree(reloc_offset); |
||
3263 | Serge | 729 | return ret; |
730 | } |
||
731 | |||
732 | static int |
||
733 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
||
734 | struct list_head *objects) |
||
735 | { |
||
736 | struct drm_i915_gem_object *obj; |
||
737 | uint32_t flush_domains = 0; |
||
4104 | Serge | 738 | bool flush_chipset = false; |
3263 | Serge | 739 | int ret; |
740 | |||
741 | list_for_each_entry(obj, objects, exec_list) { |
||
742 | ret = i915_gem_object_sync(obj, ring); |
||
743 | if (ret) |
||
744 | return ret; |
||
745 | |||
746 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) |
||
4104 | Serge | 747 | flush_chipset |= i915_gem_clflush_object(obj, false); |
3263 | Serge | 748 | |
749 | flush_domains |= obj->base.write_domain; |
||
750 | } |
||
751 | |||
4104 | Serge | 752 | if (flush_chipset) |
3263 | Serge | 753 | i915_gem_chipset_flush(ring->dev); |
754 | |||
755 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
||
756 | wmb(); |
||
757 | |||
758 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
||
759 | * any residual writes from the previous batch. |
||
760 | */ |
||
761 | return intel_ring_invalidate_all_caches(ring); |
||
762 | } |
||
763 | |||
764 | static bool |
||
765 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) |
||
766 | { |
||
3480 | Serge | 767 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
768 | return false; |
||
769 | |||
3263 | Serge | 770 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
771 | } |
||
772 | |||
773 | static int |
||
774 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
||
775 | int count) |
||
776 | { |
||
777 | int i; |
||
3480 | Serge | 778 | int relocs_total = 0; |
779 | int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry); |
||
3263 | Serge | 780 | |
781 | for (i = 0; i < count; i++) { |
||
3746 | Serge | 782 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
3263 | Serge | 783 | int length; /* limited by fault_in_pages_readable() */ |
784 | |||
3480 | Serge | 785 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
3263 | Serge | 786 | return -EINVAL; |
787 | |||
3480 | Serge | 788 | /* First check for malicious input causing overflow in |
789 | * the worst case where we need to allocate the entire |
||
790 | * relocation tree as a single array. |
||
791 | */ |
||
792 | if (exec[i].relocation_count > relocs_max - relocs_total) |
||
793 | return -EINVAL; |
||
794 | relocs_total += exec[i].relocation_count; |
||
795 | |||
3263 | Serge | 796 | length = exec[i].relocation_count * |
797 | sizeof(struct drm_i915_gem_relocation_entry); |
||
3746 | Serge | 798 | /* |
799 | * We must check that the entire relocation array is safe |
||
800 | * to read, but since we may need to update the presumed |
||
801 | * offsets during execution, check for full write access. |
||
802 | */ |
||
3263 | Serge | 803 | // if (!access_ok(VERIFY_WRITE, ptr, length)) |
804 | // return -EFAULT; |
||
805 | |||
806 | // if (fault_in_multipages_readable(ptr, length)) |
||
807 | // return -EFAULT; |
||
808 | } |
||
809 | |||
810 | return 0; |
||
811 | } |
||
812 | |||
813 | static void |
||
814 | i915_gem_execbuffer_move_to_active(struct list_head *objects, |
||
4104 | Serge | 815 | struct i915_address_space *vm, |
3263 | Serge | 816 | struct intel_ring_buffer *ring) |
817 | { |
||
818 | struct drm_i915_gem_object *obj; |
||
819 | |||
820 | list_for_each_entry(obj, objects, exec_list) { |
||
821 | u32 old_read = obj->base.read_domains; |
||
822 | u32 old_write = obj->base.write_domain; |
||
823 | |||
3480 | Serge | 824 | obj->base.write_domain = obj->base.pending_write_domain; |
825 | if (obj->base.write_domain == 0) |
||
826 | obj->base.pending_read_domains |= obj->base.read_domains; |
||
3263 | Serge | 827 | obj->base.read_domains = obj->base.pending_read_domains; |
828 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
||
829 | |||
4104 | Serge | 830 | /* FIXME: This lookup gets fixed later <-- danvet */ |
831 | list_move_tail(&i915_gem_obj_to_vma(obj, vm)->mm_list, &vm->active_list); |
||
3263 | Serge | 832 | i915_gem_object_move_to_active(obj, ring); |
833 | if (obj->base.write_domain) { |
||
834 | obj->dirty = 1; |
||
835 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
||
836 | if (obj->pin_count) /* check for potential scanout */ |
||
4104 | Serge | 837 | intel_mark_fb_busy(obj, ring); |
3263 | Serge | 838 | } |
839 | |||
840 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
||
841 | } |
||
842 | } |
||
843 | |||
844 | static void |
||
845 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
||
846 | struct drm_file *file, |
||
4104 | Serge | 847 | struct intel_ring_buffer *ring, |
848 | struct drm_i915_gem_object *obj) |
||
3263 | Serge | 849 | { |
850 | /* Unconditionally force add_request to emit a full flush. */ |
||
851 | ring->gpu_caches_dirty = true; |
||
852 | |||
853 | /* Add a breadcrumb for the completion of the batch buffer */ |
||
4104 | Serge | 854 | (void)__i915_add_request(ring, file, obj, NULL); |
3263 | Serge | 855 | } |
856 | |||
857 | static int |
||
858 | i915_reset_gen7_sol_offsets(struct drm_device *dev, |
||
859 | struct intel_ring_buffer *ring) |
||
860 | { |
||
861 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
862 | int ret, i; |
||
863 | |||
864 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) |
||
865 | return 0; |
||
866 | |||
867 | ret = intel_ring_begin(ring, 4 * 3); |
||
868 | if (ret) |
||
869 | return ret; |
||
870 | |||
871 | for (i = 0; i < 4; i++) { |
||
872 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
||
873 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); |
||
874 | intel_ring_emit(ring, 0); |
||
875 | } |
||
876 | |||
877 | intel_ring_advance(ring); |
||
878 | |||
879 | return 0; |
||
880 | } |
||
881 | |||
882 | static int |
||
883 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
||
884 | struct drm_file *file, |
||
885 | struct drm_i915_gem_execbuffer2 *args, |
||
4104 | Serge | 886 | struct drm_i915_gem_exec_object2 *exec, |
887 | struct i915_address_space *vm) |
||
3263 | Serge | 888 | { |
889 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
890 | struct eb_objects *eb; |
||
891 | struct drm_i915_gem_object *batch_obj; |
||
892 | struct drm_clip_rect *cliprects = NULL; |
||
893 | struct intel_ring_buffer *ring; |
||
894 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
||
895 | u32 exec_start, exec_len; |
||
3480 | Serge | 896 | u32 mask, flags; |
3263 | Serge | 897 | int ret, mode, i; |
3480 | Serge | 898 | bool need_relocs; |
3263 | Serge | 899 | |
3480 | Serge | 900 | if (!i915_gem_check_execbuffer(args)) |
3263 | Serge | 901 | return -EINVAL; |
902 | |||
903 | ret = validate_exec_list(exec, args->buffer_count); |
||
904 | if (ret) |
||
905 | return ret; |
||
906 | |||
907 | flags = 0; |
||
908 | if (args->flags & I915_EXEC_SECURE) { |
||
909 | |||
910 | flags |= I915_DISPATCH_SECURE; |
||
911 | } |
||
912 | if (args->flags & I915_EXEC_IS_PINNED) |
||
913 | flags |= I915_DISPATCH_PINNED; |
||
914 | |||
915 | switch (args->flags & I915_EXEC_RING_MASK) { |
||
916 | case I915_EXEC_DEFAULT: |
||
917 | case I915_EXEC_RENDER: |
||
918 | ring = &dev_priv->ring[RCS]; |
||
919 | break; |
||
920 | case I915_EXEC_BSD: |
||
921 | ring = &dev_priv->ring[VCS]; |
||
4104 | Serge | 922 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
3263 | Serge | 923 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
924 | ring->name); |
||
925 | return -EPERM; |
||
926 | } |
||
927 | break; |
||
928 | case I915_EXEC_BLT: |
||
929 | ring = &dev_priv->ring[BCS]; |
||
4104 | Serge | 930 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
3263 | Serge | 931 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
932 | ring->name); |
||
933 | return -EPERM; |
||
934 | } |
||
935 | break; |
||
4104 | Serge | 936 | case I915_EXEC_VEBOX: |
937 | ring = &dev_priv->ring[VECS]; |
||
938 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
||
939 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
||
940 | ring->name); |
||
941 | return -EPERM; |
||
942 | } |
||
943 | break; |
||
944 | |||
3263 | Serge | 945 | default: |
946 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
||
947 | (int)(args->flags & I915_EXEC_RING_MASK)); |
||
948 | return -EINVAL; |
||
949 | } |
||
950 | if (!intel_ring_initialized(ring)) { |
||
951 | DRM_DEBUG("execbuf with invalid ring: %d\n", |
||
952 | (int)(args->flags & I915_EXEC_RING_MASK)); |
||
953 | return -EINVAL; |
||
954 | } |
||
955 | |||
956 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
||
957 | mask = I915_EXEC_CONSTANTS_MASK; |
||
958 | switch (mode) { |
||
959 | case I915_EXEC_CONSTANTS_REL_GENERAL: |
||
960 | case I915_EXEC_CONSTANTS_ABSOLUTE: |
||
961 | case I915_EXEC_CONSTANTS_REL_SURFACE: |
||
962 | if (ring == &dev_priv->ring[RCS] && |
||
963 | mode != dev_priv->relative_constants_mode) { |
||
964 | if (INTEL_INFO(dev)->gen < 4) |
||
965 | return -EINVAL; |
||
966 | |||
967 | if (INTEL_INFO(dev)->gen > 5 && |
||
968 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) |
||
969 | return -EINVAL; |
||
970 | |||
971 | /* The HW changed the meaning on this bit on gen6 */ |
||
972 | if (INTEL_INFO(dev)->gen >= 6) |
||
973 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
||
974 | } |
||
975 | break; |
||
976 | default: |
||
977 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
||
978 | return -EINVAL; |
||
979 | } |
||
980 | |||
981 | if (args->buffer_count < 1) { |
||
982 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
||
983 | return -EINVAL; |
||
984 | } |
||
985 | |||
986 | if (args->num_cliprects != 0) { |
||
987 | if (ring != &dev_priv->ring[RCS]) { |
||
988 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
||
989 | return -EINVAL; |
||
990 | } |
||
991 | |||
992 | if (INTEL_INFO(dev)->gen >= 5) { |
||
993 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); |
||
994 | return -EINVAL; |
||
995 | } |
||
996 | |||
997 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
||
998 | DRM_DEBUG("execbuf with %u cliprects\n", |
||
999 | args->num_cliprects); |
||
1000 | return -EINVAL; |
||
1001 | } |
||
1002 | |||
1003 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
||
1004 | GFP_KERNEL); |
||
1005 | if (cliprects == NULL) { |
||
1006 | ret = -ENOMEM; |
||
1007 | goto pre_mutex_err; |
||
1008 | } |
||
1009 | |||
1010 | if (copy_from_user(cliprects, |
||
3746 | Serge | 1011 | to_user_ptr(args->cliprects_ptr), |
3263 | Serge | 1012 | sizeof(*cliprects)*args->num_cliprects)) { |
1013 | ret = -EFAULT; |
||
1014 | goto pre_mutex_err; |
||
1015 | } |
||
1016 | } |
||
1017 | |||
1018 | ret = i915_mutex_lock_interruptible(dev); |
||
1019 | if (ret) |
||
1020 | goto pre_mutex_err; |
||
1021 | |||
4104 | Serge | 1022 | if (dev_priv->ums.mm_suspended) { |
3263 | Serge | 1023 | mutex_unlock(&dev->struct_mutex); |
1024 | ret = -EBUSY; |
||
1025 | goto pre_mutex_err; |
||
1026 | } |
||
1027 | |||
3480 | Serge | 1028 | eb = eb_create(args); |
3263 | Serge | 1029 | if (eb == NULL) { |
1030 | mutex_unlock(&dev->struct_mutex); |
||
1031 | ret = -ENOMEM; |
||
1032 | goto pre_mutex_err; |
||
1033 | } |
||
1034 | |||
1035 | /* Look up object handles */ |
||
3480 | Serge | 1036 | ret = eb_lookup_objects(eb, exec, args, file); |
1037 | if (ret) |
||
3263 | Serge | 1038 | goto err; |
1039 | |||
1040 | /* take note of the batch buffer before we might reorder the lists */ |
||
3480 | Serge | 1041 | batch_obj = list_entry(eb->objects.prev, |
3263 | Serge | 1042 | struct drm_i915_gem_object, |
1043 | exec_list); |
||
1044 | |||
1045 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
||
3480 | Serge | 1046 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
4104 | Serge | 1047 | ret = i915_gem_execbuffer_reserve(ring, &eb->objects, vm, &need_relocs); |
3263 | Serge | 1048 | if (ret) |
1049 | goto err; |
||
1050 | |||
1051 | /* The objects are in their final locations, apply the relocations. */ |
||
3480 | Serge | 1052 | if (need_relocs) |
4104 | Serge | 1053 | ret = i915_gem_execbuffer_relocate(eb, vm); |
3263 | Serge | 1054 | if (ret) { |
1055 | if (ret == -EFAULT) { |
||
3480 | Serge | 1056 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
4104 | Serge | 1057 | eb, exec, vm); |
3263 | Serge | 1058 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1059 | } |
||
1060 | if (ret) |
||
1061 | goto err; |
||
1062 | } |
||
1063 | |||
1064 | /* Set the pending read domains for the batch buffer to COMMAND */ |
||
1065 | if (batch_obj->base.pending_write_domain) { |
||
1066 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
||
1067 | ret = -EINVAL; |
||
1068 | goto err; |
||
1069 | } |
||
1070 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
||
1071 | |||
1072 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
||
1073 | * batch" bit. Hence we need to pin secure batches into the global gtt. |
||
1074 | * hsw should have this fixed, but let's be paranoid and do it |
||
1075 | * unconditionally for now. */ |
||
1076 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) |
||
1077 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); |
||
1078 | |||
3480 | Serge | 1079 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects); |
3263 | Serge | 1080 | if (ret) |
1081 | goto err; |
||
1082 | |||
1083 | ret = i915_switch_context(ring, file, ctx_id); |
||
1084 | if (ret) |
||
1085 | goto err; |
||
1086 | |||
1087 | if (ring == &dev_priv->ring[RCS] && |
||
1088 | mode != dev_priv->relative_constants_mode) { |
||
1089 | ret = intel_ring_begin(ring, 4); |
||
1090 | if (ret) |
||
1091 | goto err; |
||
1092 | |||
1093 | intel_ring_emit(ring, MI_NOOP); |
||
1094 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
||
1095 | intel_ring_emit(ring, INSTPM); |
||
1096 | intel_ring_emit(ring, mask << 16 | mode); |
||
1097 | intel_ring_advance(ring); |
||
1098 | |||
1099 | dev_priv->relative_constants_mode = mode; |
||
1100 | } |
||
1101 | |||
1102 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
||
1103 | ret = i915_reset_gen7_sol_offsets(dev, ring); |
||
1104 | if (ret) |
||
1105 | goto err; |
||
1106 | } |
||
1107 | |||
4104 | Serge | 1108 | exec_start = i915_gem_obj_offset(batch_obj, vm) + |
1109 | args->batch_start_offset; |
||
3263 | Serge | 1110 | exec_len = args->batch_len; |
1111 | if (cliprects) { |
||
4246 | Serge | 1112 | for (i = 0; i < args->num_cliprects; i++) { |
1113 | ret = i915_emit_box(dev, &cliprects[i], |
||
1114 | args->DR1, args->DR4); |
||
1115 | if (ret) |
||
1116 | goto err; |
||
3263 | Serge | 1117 | |
4246 | Serge | 1118 | ret = ring->dispatch_execbuffer(ring, |
1119 | exec_start, exec_len, |
||
1120 | flags); |
||
1121 | if (ret) |
||
1122 | goto err; |
||
1123 | } |
||
3263 | Serge | 1124 | } else { |
1125 | ret = ring->dispatch_execbuffer(ring, |
||
1126 | exec_start, exec_len, |
||
1127 | flags); |
||
1128 | if (ret) |
||
1129 | goto err; |
||
1130 | } |
||
1131 | |||
3266 | Serge | 1132 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
3263 | Serge | 1133 | |
4104 | Serge | 1134 | i915_gem_execbuffer_move_to_active(&eb->objects, vm, ring); |
1135 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
||
3266 | Serge | 1136 | |
3263 | Serge | 1137 | err: |
1138 | eb_destroy(eb); |
||
1139 | |||
1140 | mutex_unlock(&dev->struct_mutex); |
||
1141 | |||
1142 | pre_mutex_err: |
||
4104 | Serge | 1143 | kfree(cliprects); |
3263 | Serge | 1144 | return ret; |
1145 | } |
||
1146 | |||
4246 | Serge | 1147 | #if 0 |
1148 | /* |
||
1149 | * Legacy execbuffer just creates an exec2 list from the original exec object |
||
1150 | * list array and passes it to the real function. |
||
1151 | */ |
||
1152 | int |
||
1153 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
||
1154 | struct drm_file *file) |
||
1155 | { |
||
1156 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1157 | struct drm_i915_gem_execbuffer *args = data; |
||
1158 | struct drm_i915_gem_execbuffer2 exec2; |
||
1159 | struct drm_i915_gem_exec_object *exec_list = NULL; |
||
1160 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
||
1161 | int ret, i; |
||
3480 | Serge | 1162 | |
4246 | Serge | 1163 | if (args->buffer_count < 1) { |
1164 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
||
1165 | return -EINVAL; |
||
1166 | } |
||
3480 | Serge | 1167 | |
4246 | Serge | 1168 | /* Copy in the exec list from userland */ |
1169 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
||
1170 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
||
1171 | if (exec_list == NULL || exec2_list == NULL) { |
||
1172 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
||
1173 | args->buffer_count); |
||
1174 | drm_free_large(exec_list); |
||
1175 | drm_free_large(exec2_list); |
||
1176 | return -ENOMEM; |
||
1177 | } |
||
1178 | ret = copy_from_user(exec_list, |
||
1179 | to_user_ptr(args->buffers_ptr), |
||
1180 | sizeof(*exec_list) * args->buffer_count); |
||
1181 | if (ret != 0) { |
||
1182 | DRM_DEBUG("copy %d exec entries failed %d\n", |
||
1183 | args->buffer_count, ret); |
||
1184 | drm_free_large(exec_list); |
||
1185 | drm_free_large(exec2_list); |
||
1186 | return -EFAULT; |
||
1187 | } |
||
1188 | |||
1189 | for (i = 0; i < args->buffer_count; i++) { |
||
1190 | exec2_list[i].handle = exec_list[i].handle; |
||
1191 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
||
1192 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
||
1193 | exec2_list[i].alignment = exec_list[i].alignment; |
||
1194 | exec2_list[i].offset = exec_list[i].offset; |
||
1195 | if (INTEL_INFO(dev)->gen < 4) |
||
1196 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
||
1197 | else |
||
1198 | exec2_list[i].flags = 0; |
||
1199 | } |
||
1200 | |||
1201 | exec2.buffers_ptr = args->buffers_ptr; |
||
1202 | exec2.buffer_count = args->buffer_count; |
||
1203 | exec2.batch_start_offset = args->batch_start_offset; |
||
1204 | exec2.batch_len = args->batch_len; |
||
1205 | exec2.DR1 = args->DR1; |
||
1206 | exec2.DR4 = args->DR4; |
||
1207 | exec2.num_cliprects = args->num_cliprects; |
||
1208 | exec2.cliprects_ptr = args->cliprects_ptr; |
||
1209 | exec2.flags = I915_EXEC_RENDER; |
||
1210 | i915_execbuffer2_set_context_id(exec2, 0); |
||
1211 | |||
1212 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list, |
||
1213 | &dev_priv->gtt.base); |
||
1214 | if (!ret) { |
||
1215 | /* Copy the new buffer offsets back to the user's exec list. */ |
||
1216 | for (i = 0; i < args->buffer_count; i++) |
||
1217 | exec_list[i].offset = exec2_list[i].offset; |
||
1218 | /* ... and back out to userspace */ |
||
1219 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
||
1220 | exec_list, |
||
1221 | sizeof(*exec_list) * args->buffer_count); |
||
1222 | if (ret) { |
||
1223 | ret = -EFAULT; |
||
1224 | DRM_DEBUG("failed to copy %d exec entries " |
||
1225 | "back to user (%d)\n", |
||
1226 | args->buffer_count, ret); |
||
1227 | } |
||
1228 | } |
||
1229 | |||
1230 | drm_free_large(exec_list); |
||
1231 | drm_free_large(exec2_list); |
||
1232 | return ret; |
||
1233 | } |
||
1234 | #endif |
||
1235 | |||
3263 | Serge | 1236 | int |
1237 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
||
1238 | struct drm_file *file) |
||
1239 | { |
||
4104 | Serge | 1240 | struct drm_i915_private *dev_priv = dev->dev_private; |
3263 | Serge | 1241 | struct drm_i915_gem_execbuffer2 *args = data; |
1242 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
||
1243 | int ret; |
||
1244 | |||
1245 | if (args->buffer_count < 1 || |
||
1246 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { |
||
1247 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
||
1248 | return -EINVAL; |
||
1249 | } |
||
1250 | |||
3480 | Serge | 1251 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1252 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
||
3263 | Serge | 1253 | if (exec2_list == NULL) { |
1254 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
||
1255 | args->buffer_count); |
||
1256 | return -ENOMEM; |
||
1257 | } |
||
1258 | ret = copy_from_user(exec2_list, |
||
1259 | (struct drm_i915_relocation_entry __user *) |
||
1260 | (uintptr_t) args->buffers_ptr, |
||
1261 | sizeof(*exec2_list) * args->buffer_count); |
||
1262 | if (ret != 0) { |
||
1263 | DRM_DEBUG("copy %d exec entries failed %d\n", |
||
1264 | args->buffer_count, ret); |
||
3266 | Serge | 1265 | kfree(exec2_list); |
1266 | FAIL(); |
||
3263 | Serge | 1267 | return -EFAULT; |
1268 | } |
||
1269 | |||
4104 | Serge | 1270 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list, |
1271 | &dev_priv->gtt.base); |
||
3263 | Serge | 1272 | if (!ret) { |
1273 | /* Copy the new buffer offsets back to the user's exec list. */ |
||
1274 | ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr, |
||
1275 | exec2_list, |
||
1276 | sizeof(*exec2_list) * args->buffer_count); |
||
1277 | if (ret) { |
||
1278 | ret = -EFAULT; |
||
1279 | DRM_DEBUG("failed to copy %d exec entries " |
||
1280 | "back to user (%d)\n", |
||
1281 | args->buffer_count, ret); |
||
1282 | } |
||
1283 | } |
||
1284 | |||
3266 | Serge | 1285 | kfree(exec2_list); |
3263 | Serge | 1286 | return ret; |
1287 | }>>>>>>><>>>>-->>>>>>>30) |