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3263 | Serge | 1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * Chris Wilson |
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26 | * |
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27 | */ |
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28 | |||
29 | #define iowrite32(v, addr) writel((v), (addr)) |
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30 | |||
31 | #include |
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32 | #include |
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33 | #include "i915_drv.h" |
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34 | #include "i915_trace.h" |
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35 | #include "intel_drv.h" |
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36 | //#include |
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37 | |||
38 | #define I915_EXEC_SECURE (1<<9) |
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39 | #define I915_EXEC_IS_PINNED (1<<10) |
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40 | |||
41 | #define wmb() asm volatile ("sfence") |
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42 | |||
43 | struct drm_i915_gem_object *get_fb_obj(); |
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44 | |||
45 | static inline __attribute__((const)) |
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46 | bool is_power_of_2(unsigned long n) |
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47 | { |
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48 | return (n != 0 && ((n & (n - 1)) == 0)); |
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49 | } |
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50 | |||
51 | static unsigned long |
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52 | copy_to_user(void __user *to, const void *from, unsigned long n) |
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53 | { |
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54 | memcpy(to, from, n); |
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55 | return 0; |
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56 | } |
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57 | |||
58 | static unsigned long |
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59 | copy_from_user(void *to, const void __user *from, unsigned long n) |
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60 | { |
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61 | memcpy(to, from, n); |
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62 | return 0; |
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63 | } |
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64 | |||
65 | struct eb_objects { |
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66 | int and; |
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67 | struct hlist_head buckets[0]; |
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68 | }; |
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69 | |||
70 | static struct eb_objects * |
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71 | eb_create(int size) |
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72 | { |
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73 | struct eb_objects *eb; |
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74 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; |
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75 | BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head))); |
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76 | while (count > size) |
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77 | count >>= 1; |
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78 | eb = kzalloc(count*sizeof(struct hlist_head) + |
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79 | sizeof(struct eb_objects), |
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80 | GFP_KERNEL); |
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81 | if (eb == NULL) |
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82 | return eb; |
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83 | |||
84 | eb->and = count - 1; |
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85 | return eb; |
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86 | } |
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87 | |||
88 | static void |
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89 | eb_reset(struct eb_objects *eb) |
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90 | { |
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91 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); |
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92 | } |
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93 | |||
94 | static void |
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95 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) |
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96 | { |
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97 | hlist_add_head(&obj->exec_node, |
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98 | &eb->buckets[obj->exec_handle & eb->and]); |
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99 | } |
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100 | |||
101 | static struct drm_i915_gem_object * |
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102 | eb_get_object(struct eb_objects *eb, unsigned long handle) |
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103 | { |
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104 | struct hlist_head *head; |
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105 | struct hlist_node *node; |
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106 | struct drm_i915_gem_object *obj; |
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107 | |||
108 | head = &eb->buckets[handle & eb->and]; |
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109 | hlist_for_each(node, head) { |
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110 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); |
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111 | if (obj->exec_handle == handle) |
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112 | return obj; |
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113 | } |
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114 | |||
115 | return NULL; |
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116 | } |
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117 | |||
118 | static void |
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119 | eb_destroy(struct eb_objects *eb) |
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120 | { |
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121 | kfree(eb); |
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122 | } |
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123 | |||
124 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
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125 | { |
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126 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || |
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127 | !obj->map_and_fenceable || |
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128 | obj->cache_level != I915_CACHE_NONE); |
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129 | } |
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130 | |||
131 | static int |
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132 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
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133 | struct eb_objects *eb, |
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134 | struct drm_i915_gem_relocation_entry *reloc) |
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135 | { |
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136 | struct drm_device *dev = obj->base.dev; |
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137 | struct drm_gem_object *target_obj; |
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138 | struct drm_i915_gem_object *target_i915_obj; |
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139 | uint32_t target_offset; |
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140 | int ret = -EINVAL; |
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141 | |||
142 | /* we've already hold a reference to all valid objects */ |
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143 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; |
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144 | if (unlikely(target_obj == NULL)) |
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145 | return -ENOENT; |
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146 | |||
147 | target_i915_obj = to_intel_bo(target_obj); |
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148 | target_offset = target_i915_obj->gtt_offset; |
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149 | |||
150 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
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151 | * pipe_control writes because the gpu doesn't properly redirect them |
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152 | * through the ppgtt for non_secure batchbuffers. */ |
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153 | if (unlikely(IS_GEN6(dev) && |
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154 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && |
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155 | !target_i915_obj->has_global_gtt_mapping)) { |
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156 | i915_gem_gtt_bind_object(target_i915_obj, |
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157 | target_i915_obj->cache_level); |
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158 | } |
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159 | |||
160 | /* Validate that the target is in a valid r/w GPU domain */ |
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161 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
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162 | DRM_DEBUG("reloc with multiple write domains: " |
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163 | "obj %p target %d offset %d " |
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164 | "read %08x write %08x", |
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165 | obj, reloc->target_handle, |
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166 | (int) reloc->offset, |
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167 | reloc->read_domains, |
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168 | reloc->write_domain); |
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169 | return ret; |
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170 | } |
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171 | if (unlikely((reloc->write_domain | reloc->read_domains) |
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172 | & ~I915_GEM_GPU_DOMAINS)) { |
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173 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
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174 | "obj %p target %d offset %d " |
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175 | "read %08x write %08x", |
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176 | obj, reloc->target_handle, |
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177 | (int) reloc->offset, |
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178 | reloc->read_domains, |
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179 | reloc->write_domain); |
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180 | return ret; |
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181 | } |
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182 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
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183 | reloc->write_domain != target_obj->pending_write_domain)) { |
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184 | DRM_DEBUG("Write domain conflict: " |
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185 | "obj %p target %d offset %d " |
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186 | "new %08x old %08x\n", |
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187 | obj, reloc->target_handle, |
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188 | (int) reloc->offset, |
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189 | reloc->write_domain, |
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190 | target_obj->pending_write_domain); |
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191 | return ret; |
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192 | } |
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193 | |||
194 | target_obj->pending_read_domains |= reloc->read_domains; |
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195 | target_obj->pending_write_domain |= reloc->write_domain; |
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196 | |||
197 | /* If the relocation already has the right value in it, no |
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198 | * more work needs to be done. |
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199 | */ |
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200 | if (target_offset == reloc->presumed_offset) |
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201 | return 0; |
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202 | |||
203 | /* Check that the relocation address is valid... */ |
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204 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
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205 | DRM_DEBUG("Relocation beyond object bounds: " |
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206 | "obj %p target %d offset %d size %d.\n", |
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207 | obj, reloc->target_handle, |
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208 | (int) reloc->offset, |
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209 | (int) obj->base.size); |
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210 | return ret; |
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211 | } |
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212 | if (unlikely(reloc->offset & 3)) { |
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213 | DRM_DEBUG("Relocation not 4-byte aligned: " |
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214 | "obj %p target %d offset %d.\n", |
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215 | obj, reloc->target_handle, |
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216 | (int) reloc->offset); |
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217 | return ret; |
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218 | } |
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219 | |||
220 | /* We can't wait for rendering with pagefaults disabled */ |
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221 | // if (obj->active && in_atomic()) |
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222 | // return -EFAULT; |
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223 | |||
224 | reloc->delta += target_offset; |
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225 | if (use_cpu_reloc(obj)) { |
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226 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
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227 | char *vaddr; |
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228 | |||
229 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
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230 | if (ret) |
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231 | return ret; |
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232 | |||
233 | vaddr = (char *)MapIoMem((addr_t)i915_gem_object_get_page(obj, |
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234 | reloc->offset >> PAGE_SHIFT), 4096, 3); |
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235 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
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236 | FreeKernelSpace(vaddr); |
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237 | } else { |
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238 | struct drm_i915_private *dev_priv = dev->dev_private; |
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239 | uint32_t __iomem *reloc_entry; |
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240 | void __iomem *reloc_page; |
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241 | |||
242 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
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243 | if (ret) |
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244 | return ret; |
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245 | |||
246 | ret = i915_gem_object_put_fence(obj); |
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247 | if (ret) |
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248 | return ret; |
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249 | |||
250 | /* Map the page containing the relocation we're going to perform. */ |
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251 | reloc->offset += obj->gtt_offset; |
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252 | reloc_page = (void*)MapIoMem(reloc->offset & PAGE_MASK, 4096, 3); |
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253 | reloc_entry = (uint32_t __iomem *) |
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254 | (reloc_page + (reloc->offset & ~PAGE_MASK)); |
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255 | iowrite32(reloc->delta, reloc_entry); |
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256 | FreeKernelSpace(reloc_page); |
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257 | } |
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258 | |||
259 | /* and update the user's relocation entry */ |
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260 | reloc->presumed_offset = target_offset; |
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261 | |||
262 | return 0; |
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263 | } |
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264 | |||
265 | static int |
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266 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, |
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267 | struct eb_objects *eb) |
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268 | { |
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269 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
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270 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; |
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271 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
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272 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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273 | int remain, ret; |
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274 | |||
275 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
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276 | |||
277 | remain = entry->relocation_count; |
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278 | while (remain) { |
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279 | struct drm_i915_gem_relocation_entry *r = stack_reloc; |
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280 | int count = remain; |
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281 | if (count > ARRAY_SIZE(stack_reloc)) |
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282 | count = ARRAY_SIZE(stack_reloc); |
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283 | remain -= count; |
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284 | |||
285 | memcpy(r, user_relocs, count*sizeof(r[0])); |
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286 | |||
287 | do { |
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288 | u64 offset = r->presumed_offset; |
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289 | |||
290 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
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291 | if (ret) |
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292 | return ret; |
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293 | |||
294 | memcpy(&user_relocs->presumed_offset, |
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295 | &r->presumed_offset, |
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296 | sizeof(r->presumed_offset)); |
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297 | |||
298 | user_relocs++; |
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299 | r++; |
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300 | } while (--count); |
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301 | } |
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302 | |||
303 | return 0; |
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304 | #undef N_RELOC |
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305 | } |
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306 | |||
307 | static int |
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308 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, |
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309 | struct eb_objects *eb, |
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310 | struct drm_i915_gem_relocation_entry *relocs) |
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311 | { |
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312 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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313 | int i, ret; |
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314 | |||
315 | for (i = 0; i < entry->relocation_count; i++) { |
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316 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
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317 | if (ret) |
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318 | return ret; |
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319 | } |
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320 | |||
321 | return 0; |
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322 | } |
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323 | |||
324 | static int |
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325 | i915_gem_execbuffer_relocate(struct drm_device *dev, |
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326 | struct eb_objects *eb, |
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327 | struct list_head *objects) |
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328 | { |
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329 | struct drm_i915_gem_object *obj; |
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330 | int ret = 0; |
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331 | |||
332 | /* This is the fast path and we cannot handle a pagefault whilst |
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333 | * holding the struct mutex lest the user pass in the relocations |
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334 | * contained within a mmaped bo. For in such a case we, the page |
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335 | * fault handler would call i915_gem_fault() and we would try to |
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336 | * acquire the struct mutex again. Obviously this is bad and so |
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337 | * lockdep complains vehemently. |
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338 | */ |
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339 | // pagefault_disable(); |
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340 | list_for_each_entry(obj, objects, exec_list) { |
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341 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
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342 | if (ret) |
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343 | break; |
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344 | } |
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345 | // pagefault_enable(); |
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346 | |||
347 | return ret; |
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348 | } |
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349 | |||
350 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
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351 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) |
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352 | |||
353 | static int |
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354 | need_reloc_mappable(struct drm_i915_gem_object *obj) |
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355 | { |
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356 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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357 | return entry->relocation_count && !use_cpu_reloc(obj); |
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358 | } |
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359 | |||
360 | static int |
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361 | i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, |
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362 | struct intel_ring_buffer *ring) |
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363 | { |
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364 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
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365 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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366 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
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367 | bool need_fence, need_mappable; |
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368 | int ret; |
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369 | |||
370 | need_fence = |
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371 | has_fenced_gpu_access && |
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372 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
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373 | obj->tiling_mode != I915_TILING_NONE; |
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374 | need_mappable = need_fence || need_reloc_mappable(obj); |
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375 | |||
376 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false); |
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377 | if (ret) |
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378 | return ret; |
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379 | |||
380 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
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381 | |||
382 | if (has_fenced_gpu_access) { |
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383 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
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384 | ret = i915_gem_object_get_fence(obj); |
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385 | if (ret) |
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386 | return ret; |
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387 | |||
388 | if (i915_gem_object_pin_fence(obj)) |
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389 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
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390 | |||
391 | obj->pending_fenced_gpu_access = true; |
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392 | } |
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393 | } |
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394 | |||
395 | /* Ensure ppgtt mapping exists if needed */ |
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396 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { |
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397 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
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398 | obj, obj->cache_level); |
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399 | |||
400 | obj->has_aliasing_ppgtt_mapping = 1; |
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401 | } |
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402 | |||
403 | entry->offset = obj->gtt_offset; |
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404 | return 0; |
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405 | } |
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406 | |||
407 | static void |
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408 | i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) |
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409 | { |
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410 | struct drm_i915_gem_exec_object2 *entry; |
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411 | |||
412 | if (!obj->gtt_space) |
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413 | return; |
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414 | |||
415 | entry = obj->exec_entry; |
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416 | |||
417 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) |
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418 | i915_gem_object_unpin_fence(obj); |
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419 | |||
420 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) |
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421 | i915_gem_object_unpin(obj); |
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422 | |||
423 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
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424 | } |
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425 | |||
426 | static int |
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427 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
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428 | struct drm_file *file, |
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429 | struct list_head *objects) |
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430 | { |
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431 | struct drm_i915_gem_object *obj; |
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432 | struct list_head ordered_objects; |
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433 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
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434 | int retry; |
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435 | |||
436 | INIT_LIST_HEAD(&ordered_objects); |
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437 | while (!list_empty(objects)) { |
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438 | struct drm_i915_gem_exec_object2 *entry; |
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439 | bool need_fence, need_mappable; |
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440 | |||
441 | obj = list_first_entry(objects, |
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442 | struct drm_i915_gem_object, |
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443 | exec_list); |
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444 | entry = obj->exec_entry; |
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445 | |||
446 | need_fence = |
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447 | has_fenced_gpu_access && |
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448 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
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449 | obj->tiling_mode != I915_TILING_NONE; |
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450 | need_mappable = need_fence || need_reloc_mappable(obj); |
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451 | |||
452 | if (need_mappable) |
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453 | list_move(&obj->exec_list, &ordered_objects); |
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454 | else |
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455 | list_move_tail(&obj->exec_list, &ordered_objects); |
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456 | |||
457 | obj->base.pending_read_domains = 0; |
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458 | obj->base.pending_write_domain = 0; |
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459 | obj->pending_fenced_gpu_access = false; |
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460 | } |
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461 | list_splice(&ordered_objects, objects); |
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462 | |||
463 | /* Attempt to pin all of the buffers into the GTT. |
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464 | * This is done in 3 phases: |
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465 | * |
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466 | * 1a. Unbind all objects that do not match the GTT constraints for |
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467 | * the execbuffer (fenceable, mappable, alignment etc). |
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468 | * 1b. Increment pin count for already bound objects. |
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469 | * 2. Bind new objects. |
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470 | * 3. Decrement pin count. |
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471 | * |
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472 | * This avoid unnecessary unbinding of later objects in order to make |
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473 | * room for the earlier objects *unless* we need to defragment. |
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474 | */ |
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475 | retry = 0; |
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476 | do { |
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477 | int ret = 0; |
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478 | |||
479 | /* Unbind any ill-fitting objects or pin. */ |
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480 | list_for_each_entry(obj, objects, exec_list) { |
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481 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
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482 | bool need_fence, need_mappable; |
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483 | |||
484 | if (!obj->gtt_space) |
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485 | continue; |
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486 | |||
487 | need_fence = |
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488 | has_fenced_gpu_access && |
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489 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
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490 | obj->tiling_mode != I915_TILING_NONE; |
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491 | need_mappable = need_fence || need_reloc_mappable(obj); |
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492 | |||
493 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || |
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494 | (need_mappable && !obj->map_and_fenceable)) |
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495 | ret = i915_gem_object_unbind(obj); |
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496 | else |
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497 | ret = i915_gem_execbuffer_reserve_object(obj, ring); |
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498 | if (ret) |
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499 | goto err; |
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500 | } |
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501 | |||
502 | /* Bind fresh objects */ |
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503 | list_for_each_entry(obj, objects, exec_list) { |
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504 | if (obj->gtt_space) |
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505 | continue; |
||
506 | |||
507 | ret = i915_gem_execbuffer_reserve_object(obj, ring); |
||
508 | if (ret) |
||
509 | goto err; |
||
510 | } |
||
511 | |||
512 | err: /* Decrement pin count for bound objects */ |
||
513 | list_for_each_entry(obj, objects, exec_list) |
||
514 | i915_gem_execbuffer_unreserve_object(obj); |
||
515 | |||
516 | if (ret != -ENOSPC || retry++) |
||
517 | return ret; |
||
518 | |||
519 | // ret = i915_gem_evict_everything(ring->dev); |
||
520 | if (ret) |
||
521 | return ret; |
||
522 | } while (1); |
||
523 | } |
||
524 | |||
525 | static int |
||
526 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, |
||
527 | struct drm_file *file, |
||
528 | struct intel_ring_buffer *ring, |
||
529 | struct list_head *objects, |
||
530 | struct eb_objects *eb, |
||
531 | struct drm_i915_gem_exec_object2 *exec, |
||
532 | int count) |
||
533 | { |
||
534 | struct drm_i915_gem_relocation_entry *reloc; |
||
535 | struct drm_i915_gem_object *obj; |
||
536 | int *reloc_offset; |
||
537 | int i, total, ret; |
||
538 | |||
539 | /* We may process another execbuffer during the unlock... */ |
||
540 | while (!list_empty(objects)) { |
||
541 | obj = list_first_entry(objects, |
||
542 | struct drm_i915_gem_object, |
||
543 | exec_list); |
||
544 | list_del_init(&obj->exec_list); |
||
545 | drm_gem_object_unreference(&obj->base); |
||
546 | } |
||
547 | |||
548 | mutex_unlock(&dev->struct_mutex); |
||
549 | |||
550 | total = 0; |
||
551 | for (i = 0; i < count; i++) |
||
552 | total += exec[i].relocation_count; |
||
553 | |||
554 | reloc_offset = malloc(count * sizeof(*reloc_offset)); |
||
555 | reloc = malloc(total * sizeof(*reloc)); |
||
556 | if (reloc == NULL || reloc_offset == NULL) { |
||
557 | free(reloc); |
||
558 | free(reloc_offset); |
||
559 | mutex_lock(&dev->struct_mutex); |
||
560 | return -ENOMEM; |
||
561 | } |
||
562 | |||
563 | total = 0; |
||
564 | for (i = 0; i < count; i++) { |
||
565 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
||
566 | u64 invalid_offset = (u64)-1; |
||
567 | int j; |
||
568 | |||
569 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
||
570 | |||
571 | if (copy_from_user(reloc+total, user_relocs, |
||
572 | exec[i].relocation_count * sizeof(*reloc))) { |
||
573 | ret = -EFAULT; |
||
574 | mutex_lock(&dev->struct_mutex); |
||
575 | goto err; |
||
576 | } |
||
577 | |||
578 | /* As we do not update the known relocation offsets after |
||
579 | * relocating (due to the complexities in lock handling), |
||
580 | * we need to mark them as invalid now so that we force the |
||
581 | * relocation processing next time. Just in case the target |
||
582 | * object is evicted and then rebound into its old |
||
583 | * presumed_offset before the next execbuffer - if that |
||
584 | * happened we would make the mistake of assuming that the |
||
585 | * relocations were valid. |
||
586 | */ |
||
587 | for (j = 0; j < exec[i].relocation_count; j++) { |
||
588 | if (copy_to_user(&user_relocs[j].presumed_offset, |
||
589 | &invalid_offset, |
||
590 | sizeof(invalid_offset))) { |
||
591 | ret = -EFAULT; |
||
592 | mutex_lock(&dev->struct_mutex); |
||
593 | goto err; |
||
594 | } |
||
595 | } |
||
596 | |||
597 | reloc_offset[i] = total; |
||
598 | total += exec[i].relocation_count; |
||
599 | } |
||
600 | |||
601 | ret = i915_mutex_lock_interruptible(dev); |
||
602 | if (ret) { |
||
603 | mutex_lock(&dev->struct_mutex); |
||
604 | goto err; |
||
605 | } |
||
606 | |||
607 | /* reacquire the objects */ |
||
608 | eb_reset(eb); |
||
609 | for (i = 0; i < count; i++) { |
||
610 | |||
611 | if(exec[i].handle == -2) |
||
612 | obj = get_fb_obj(); |
||
613 | else |
||
614 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
||
615 | exec[i].handle)); |
||
616 | if (&obj->base == NULL) { |
||
617 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
||
618 | exec[i].handle, i); |
||
619 | ret = -ENOENT; |
||
620 | goto err; |
||
621 | } |
||
622 | |||
623 | list_add_tail(&obj->exec_list, objects); |
||
624 | obj->exec_handle = exec[i].handle; |
||
625 | obj->exec_entry = &exec[i]; |
||
626 | eb_add_object(eb, obj); |
||
627 | } |
||
628 | |||
629 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
||
630 | if (ret) |
||
631 | goto err; |
||
632 | |||
633 | list_for_each_entry(obj, objects, exec_list) { |
||
634 | int offset = obj->exec_entry - exec; |
||
635 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
||
636 | reloc + reloc_offset[offset]); |
||
637 | if (ret) |
||
638 | goto err; |
||
639 | } |
||
640 | |||
641 | /* Leave the user relocations as are, this is the painfully slow path, |
||
642 | * and we want to avoid the complication of dropping the lock whilst |
||
643 | * having buffers reserved in the aperture and so causing spurious |
||
644 | * ENOSPC for random operations. |
||
645 | */ |
||
646 | |||
647 | err: |
||
648 | free(reloc); |
||
649 | free(reloc_offset); |
||
650 | return ret; |
||
651 | } |
||
652 | |||
653 | static int |
||
654 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) |
||
655 | { |
||
656 | u32 plane, flip_mask; |
||
657 | int ret; |
||
658 | |||
659 | /* Check for any pending flips. As we only maintain a flip queue depth |
||
660 | * of 1, we can simply insert a WAIT for the next display flip prior |
||
661 | * to executing the batch and avoid stalling the CPU. |
||
662 | */ |
||
663 | |||
664 | for (plane = 0; flips >> plane; plane++) { |
||
665 | if (((flips >> plane) & 1) == 0) |
||
666 | continue; |
||
667 | |||
668 | if (plane) |
||
669 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
||
670 | else |
||
671 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
||
672 | |||
673 | ret = intel_ring_begin(ring, 2); |
||
674 | if (ret) |
||
675 | return ret; |
||
676 | |||
677 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
||
678 | intel_ring_emit(ring, MI_NOOP); |
||
679 | intel_ring_advance(ring); |
||
680 | } |
||
681 | |||
682 | return 0; |
||
683 | } |
||
684 | |||
685 | static int |
||
686 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
||
687 | struct list_head *objects) |
||
688 | { |
||
689 | struct drm_i915_gem_object *obj; |
||
690 | uint32_t flush_domains = 0; |
||
691 | uint32_t flips = 0; |
||
692 | int ret; |
||
693 | |||
694 | list_for_each_entry(obj, objects, exec_list) { |
||
695 | ret = i915_gem_object_sync(obj, ring); |
||
696 | if (ret) |
||
697 | return ret; |
||
698 | |||
699 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) |
||
700 | i915_gem_clflush_object(obj); |
||
701 | |||
702 | if (obj->base.pending_write_domain) |
||
703 | flips |= atomic_read(&obj->pending_flip); |
||
704 | |||
705 | flush_domains |= obj->base.write_domain; |
||
706 | } |
||
707 | |||
708 | if (flips) { |
||
709 | ret = i915_gem_execbuffer_wait_for_flips(ring, flips); |
||
710 | if (ret) |
||
711 | return ret; |
||
712 | } |
||
713 | |||
714 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
||
715 | i915_gem_chipset_flush(ring->dev); |
||
716 | |||
717 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
||
718 | wmb(); |
||
719 | |||
720 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
||
721 | * any residual writes from the previous batch. |
||
722 | */ |
||
723 | return intel_ring_invalidate_all_caches(ring); |
||
724 | } |
||
725 | |||
726 | static bool |
||
727 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) |
||
728 | { |
||
729 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
||
730 | } |
||
731 | |||
732 | static int |
||
733 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
||
734 | int count) |
||
735 | { |
||
736 | int i; |
||
737 | |||
738 | for (i = 0; i < count; i++) { |
||
739 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
||
740 | int length; /* limited by fault_in_pages_readable() */ |
||
741 | |||
742 | /* First check for malicious input causing overflow */ |
||
743 | if (exec[i].relocation_count > |
||
744 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) |
||
745 | return -EINVAL; |
||
746 | |||
747 | length = exec[i].relocation_count * |
||
748 | sizeof(struct drm_i915_gem_relocation_entry); |
||
749 | // if (!access_ok(VERIFY_READ, ptr, length)) |
||
750 | // return -EFAULT; |
||
751 | |||
752 | /* we may also need to update the presumed offsets */ |
||
753 | // if (!access_ok(VERIFY_WRITE, ptr, length)) |
||
754 | // return -EFAULT; |
||
755 | |||
756 | // if (fault_in_multipages_readable(ptr, length)) |
||
757 | // return -EFAULT; |
||
758 | } |
||
759 | |||
760 | return 0; |
||
761 | } |
||
762 | |||
763 | static void |
||
764 | i915_gem_execbuffer_move_to_active(struct list_head *objects, |
||
765 | struct intel_ring_buffer *ring) |
||
766 | { |
||
767 | struct drm_i915_gem_object *obj; |
||
768 | |||
769 | list_for_each_entry(obj, objects, exec_list) { |
||
770 | u32 old_read = obj->base.read_domains; |
||
771 | u32 old_write = obj->base.write_domain; |
||
772 | |||
773 | obj->base.read_domains = obj->base.pending_read_domains; |
||
774 | obj->base.write_domain = obj->base.pending_write_domain; |
||
775 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
||
776 | |||
777 | i915_gem_object_move_to_active(obj, ring); |
||
778 | if (obj->base.write_domain) { |
||
779 | obj->dirty = 1; |
||
780 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
||
781 | if (obj->pin_count) /* check for potential scanout */ |
||
782 | intel_mark_fb_busy(obj); |
||
783 | } |
||
784 | |||
785 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
||
786 | } |
||
787 | } |
||
788 | |||
789 | static void |
||
790 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
||
791 | struct drm_file *file, |
||
792 | struct intel_ring_buffer *ring) |
||
793 | { |
||
794 | /* Unconditionally force add_request to emit a full flush. */ |
||
795 | ring->gpu_caches_dirty = true; |
||
796 | |||
797 | /* Add a breadcrumb for the completion of the batch buffer */ |
||
798 | (void)i915_add_request(ring, file, NULL); |
||
799 | } |
||
800 | |||
801 | static int |
||
802 | i915_reset_gen7_sol_offsets(struct drm_device *dev, |
||
803 | struct intel_ring_buffer *ring) |
||
804 | { |
||
805 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
806 | int ret, i; |
||
807 | |||
808 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) |
||
809 | return 0; |
||
810 | |||
811 | ret = intel_ring_begin(ring, 4 * 3); |
||
812 | if (ret) |
||
813 | return ret; |
||
814 | |||
815 | for (i = 0; i < 4; i++) { |
||
816 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
||
817 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); |
||
818 | intel_ring_emit(ring, 0); |
||
819 | } |
||
820 | |||
821 | intel_ring_advance(ring); |
||
822 | |||
823 | return 0; |
||
824 | } |
||
825 | |||
826 | static int |
||
827 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
||
828 | struct drm_file *file, |
||
829 | struct drm_i915_gem_execbuffer2 *args, |
||
830 | struct drm_i915_gem_exec_object2 *exec) |
||
831 | { |
||
832 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
833 | struct list_head objects; |
||
834 | struct eb_objects *eb; |
||
835 | struct drm_i915_gem_object *batch_obj; |
||
836 | struct drm_clip_rect *cliprects = NULL; |
||
837 | struct intel_ring_buffer *ring; |
||
838 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
||
839 | u32 exec_start, exec_len; |
||
840 | u32 mask; |
||
841 | u32 flags; |
||
842 | int ret, mode, i; |
||
843 | |||
844 | if (!i915_gem_check_execbuffer(args)) { |
||
845 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
||
846 | return -EINVAL; |
||
847 | } |
||
848 | |||
849 | ret = validate_exec_list(exec, args->buffer_count); |
||
850 | if (ret) |
||
851 | return ret; |
||
852 | |||
853 | flags = 0; |
||
854 | if (args->flags & I915_EXEC_SECURE) { |
||
855 | // if (!file->is_master || !capable(CAP_SYS_ADMIN)) |
||
856 | // return -EPERM; |
||
857 | |||
858 | flags |= I915_DISPATCH_SECURE; |
||
859 | } |
||
860 | if (args->flags & I915_EXEC_IS_PINNED) |
||
861 | flags |= I915_DISPATCH_PINNED; |
||
862 | |||
863 | switch (args->flags & I915_EXEC_RING_MASK) { |
||
864 | case I915_EXEC_DEFAULT: |
||
865 | case I915_EXEC_RENDER: |
||
866 | ring = &dev_priv->ring[RCS]; |
||
867 | break; |
||
868 | case I915_EXEC_BSD: |
||
869 | ring = &dev_priv->ring[VCS]; |
||
870 | if (ctx_id != 0) { |
||
871 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
||
872 | ring->name); |
||
873 | return -EPERM; |
||
874 | } |
||
875 | break; |
||
876 | case I915_EXEC_BLT: |
||
877 | ring = &dev_priv->ring[BCS]; |
||
878 | if (ctx_id != 0) { |
||
879 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
||
880 | ring->name); |
||
881 | return -EPERM; |
||
882 | } |
||
883 | break; |
||
884 | default: |
||
885 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
||
886 | (int)(args->flags & I915_EXEC_RING_MASK)); |
||
887 | return -EINVAL; |
||
888 | } |
||
889 | if (!intel_ring_initialized(ring)) { |
||
890 | DRM_DEBUG("execbuf with invalid ring: %d\n", |
||
891 | (int)(args->flags & I915_EXEC_RING_MASK)); |
||
892 | return -EINVAL; |
||
893 | } |
||
894 | |||
895 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
||
896 | mask = I915_EXEC_CONSTANTS_MASK; |
||
897 | switch (mode) { |
||
898 | case I915_EXEC_CONSTANTS_REL_GENERAL: |
||
899 | case I915_EXEC_CONSTANTS_ABSOLUTE: |
||
900 | case I915_EXEC_CONSTANTS_REL_SURFACE: |
||
901 | if (ring == &dev_priv->ring[RCS] && |
||
902 | mode != dev_priv->relative_constants_mode) { |
||
903 | if (INTEL_INFO(dev)->gen < 4) |
||
904 | return -EINVAL; |
||
905 | |||
906 | if (INTEL_INFO(dev)->gen > 5 && |
||
907 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) |
||
908 | return -EINVAL; |
||
909 | |||
910 | /* The HW changed the meaning on this bit on gen6 */ |
||
911 | if (INTEL_INFO(dev)->gen >= 6) |
||
912 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
||
913 | } |
||
914 | break; |
||
915 | default: |
||
916 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
||
917 | return -EINVAL; |
||
918 | } |
||
919 | |||
920 | if (args->buffer_count < 1) { |
||
921 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
||
922 | return -EINVAL; |
||
923 | } |
||
924 | |||
925 | if (args->num_cliprects != 0) { |
||
926 | if (ring != &dev_priv->ring[RCS]) { |
||
927 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
||
928 | return -EINVAL; |
||
929 | } |
||
930 | |||
931 | if (INTEL_INFO(dev)->gen >= 5) { |
||
932 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); |
||
933 | return -EINVAL; |
||
934 | } |
||
935 | |||
936 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
||
937 | DRM_DEBUG("execbuf with %u cliprects\n", |
||
938 | args->num_cliprects); |
||
939 | return -EINVAL; |
||
940 | } |
||
941 | |||
942 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
||
943 | GFP_KERNEL); |
||
944 | if (cliprects == NULL) { |
||
945 | ret = -ENOMEM; |
||
946 | goto pre_mutex_err; |
||
947 | } |
||
948 | |||
949 | if (copy_from_user(cliprects, |
||
950 | (struct drm_clip_rect __user *)(uintptr_t) |
||
951 | args->cliprects_ptr, |
||
952 | sizeof(*cliprects)*args->num_cliprects)) { |
||
953 | ret = -EFAULT; |
||
954 | goto pre_mutex_err; |
||
955 | } |
||
956 | } |
||
957 | |||
958 | ret = i915_mutex_lock_interruptible(dev); |
||
959 | if (ret) |
||
960 | goto pre_mutex_err; |
||
961 | |||
962 | if (dev_priv->mm.suspended) { |
||
963 | mutex_unlock(&dev->struct_mutex); |
||
964 | ret = -EBUSY; |
||
965 | goto pre_mutex_err; |
||
966 | } |
||
967 | |||
968 | eb = eb_create(args->buffer_count); |
||
969 | if (eb == NULL) { |
||
970 | mutex_unlock(&dev->struct_mutex); |
||
971 | ret = -ENOMEM; |
||
972 | goto pre_mutex_err; |
||
973 | } |
||
974 | |||
975 | /* Look up object handles */ |
||
976 | INIT_LIST_HEAD(&objects); |
||
977 | for (i = 0; i < args->buffer_count; i++) { |
||
978 | struct drm_i915_gem_object *obj; |
||
979 | |||
980 | if(exec[i].handle == -2) |
||
981 | obj = get_fb_obj(); |
||
982 | else |
||
983 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
||
984 | exec[i].handle)); |
||
985 | if (&obj->base == NULL) { |
||
986 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
||
987 | exec[i].handle, i); |
||
988 | /* prevent error path from reading uninitialized data */ |
||
989 | ret = -ENOENT; |
||
990 | goto err; |
||
991 | } |
||
992 | |||
993 | if (!list_empty(&obj->exec_list)) { |
||
994 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
||
995 | obj, exec[i].handle, i); |
||
996 | ret = -EINVAL; |
||
997 | goto err; |
||
998 | } |
||
999 | |||
1000 | list_add_tail(&obj->exec_list, &objects); |
||
1001 | obj->exec_handle = exec[i].handle; |
||
1002 | obj->exec_entry = &exec[i]; |
||
1003 | eb_add_object(eb, obj); |
||
1004 | } |
||
1005 | |||
1006 | /* take note of the batch buffer before we might reorder the lists */ |
||
1007 | batch_obj = list_entry(objects.prev, |
||
1008 | struct drm_i915_gem_object, |
||
1009 | exec_list); |
||
1010 | |||
1011 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
||
1012 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
||
1013 | if (ret) |
||
1014 | goto err; |
||
1015 | |||
1016 | /* The objects are in their final locations, apply the relocations. */ |
||
1017 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
||
1018 | if (ret) { |
||
1019 | if (ret == -EFAULT) { |
||
1020 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
||
1021 | &objects, eb, |
||
1022 | exec, |
||
1023 | args->buffer_count); |
||
1024 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
||
1025 | } |
||
1026 | if (ret) |
||
1027 | goto err; |
||
1028 | } |
||
1029 | |||
1030 | /* Set the pending read domains for the batch buffer to COMMAND */ |
||
1031 | if (batch_obj->base.pending_write_domain) { |
||
1032 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
||
1033 | ret = -EINVAL; |
||
1034 | goto err; |
||
1035 | } |
||
1036 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
||
1037 | |||
1038 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
||
1039 | * batch" bit. Hence we need to pin secure batches into the global gtt. |
||
1040 | * hsw should have this fixed, but let's be paranoid and do it |
||
1041 | * unconditionally for now. */ |
||
1042 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) |
||
1043 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); |
||
1044 | |||
1045 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
||
1046 | if (ret) |
||
1047 | goto err; |
||
1048 | |||
1049 | ret = i915_switch_context(ring, file, ctx_id); |
||
1050 | if (ret) |
||
1051 | goto err; |
||
1052 | |||
1053 | if (ring == &dev_priv->ring[RCS] && |
||
1054 | mode != dev_priv->relative_constants_mode) { |
||
1055 | ret = intel_ring_begin(ring, 4); |
||
1056 | if (ret) |
||
1057 | goto err; |
||
1058 | |||
1059 | intel_ring_emit(ring, MI_NOOP); |
||
1060 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
||
1061 | intel_ring_emit(ring, INSTPM); |
||
1062 | intel_ring_emit(ring, mask << 16 | mode); |
||
1063 | intel_ring_advance(ring); |
||
1064 | |||
1065 | dev_priv->relative_constants_mode = mode; |
||
1066 | } |
||
1067 | |||
1068 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
||
1069 | ret = i915_reset_gen7_sol_offsets(dev, ring); |
||
1070 | if (ret) |
||
1071 | goto err; |
||
1072 | } |
||
1073 | |||
1074 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
||
1075 | exec_len = args->batch_len; |
||
1076 | if (cliprects) { |
||
1077 | // for (i = 0; i < args->num_cliprects; i++) { |
||
1078 | // ret = i915_emit_box(dev, &cliprects[i], |
||
1079 | // args->DR1, args->DR4); |
||
1080 | // if (ret) |
||
1081 | // goto err; |
||
1082 | |||
1083 | // ret = ring->dispatch_execbuffer(ring, |
||
1084 | // exec_start, exec_len, |
||
1085 | // flags); |
||
1086 | // if (ret) |
||
1087 | // goto err; |
||
1088 | // } |
||
1089 | } else { |
||
1090 | ret = ring->dispatch_execbuffer(ring, |
||
1091 | exec_start, exec_len, |
||
1092 | flags); |
||
1093 | if (ret) |
||
1094 | goto err; |
||
1095 | } |
||
1096 | |||
1097 | // i915_gem_execbuffer_move_to_active(&objects, ring); |
||
1098 | // i915_gem_execbuffer_retire_commands(dev, file, ring); |
||
1099 | ring->gpu_caches_dirty = true; |
||
1100 | intel_ring_flush_all_caches(ring); |
||
1101 | |||
1102 | err: |
||
1103 | eb_destroy(eb); |
||
1104 | while (!list_empty(&objects)) { |
||
1105 | struct drm_i915_gem_object *obj; |
||
1106 | |||
1107 | obj = list_first_entry(&objects, |
||
1108 | struct drm_i915_gem_object, |
||
1109 | exec_list); |
||
1110 | list_del_init(&obj->exec_list); |
||
1111 | drm_gem_object_unreference(&obj->base); |
||
1112 | } |
||
1113 | |||
1114 | mutex_unlock(&dev->struct_mutex); |
||
1115 | |||
1116 | pre_mutex_err: |
||
1117 | kfree(cliprects); |
||
1118 | return ret; |
||
1119 | } |
||
1120 | |||
1121 | |||
1122 | int |
||
1123 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
||
1124 | struct drm_file *file) |
||
1125 | { |
||
1126 | struct drm_i915_gem_execbuffer2 *args = data; |
||
1127 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
||
1128 | int ret; |
||
1129 | |||
1130 | if (args->buffer_count < 1 || |
||
1131 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { |
||
1132 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
||
1133 | return -EINVAL; |
||
1134 | } |
||
1135 | |||
1136 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, 0); |
||
1137 | if (exec2_list == NULL) |
||
1138 | exec2_list = malloc(sizeof(*exec2_list) * args->buffer_count); |
||
1139 | if (exec2_list == NULL) { |
||
1140 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
||
1141 | args->buffer_count); |
||
1142 | return -ENOMEM; |
||
1143 | } |
||
1144 | ret = copy_from_user(exec2_list, |
||
1145 | (struct drm_i915_relocation_entry __user *) |
||
1146 | (uintptr_t) args->buffers_ptr, |
||
1147 | sizeof(*exec2_list) * args->buffer_count); |
||
1148 | if (ret != 0) { |
||
1149 | DRM_DEBUG("copy %d exec entries failed %d\n", |
||
1150 | args->buffer_count, ret); |
||
1151 | free(exec2_list); |
||
1152 | return -EFAULT; |
||
1153 | } |
||
1154 | |||
1155 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
||
1156 | if (!ret) { |
||
1157 | /* Copy the new buffer offsets back to the user's exec list. */ |
||
1158 | ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr, |
||
1159 | exec2_list, |
||
1160 | sizeof(*exec2_list) * args->buffer_count); |
||
1161 | if (ret) { |
||
1162 | ret = -EFAULT; |
||
1163 | DRM_DEBUG("failed to copy %d exec entries " |
||
1164 | "back to user (%d)\n", |
||
1165 | args->buffer_count, ret); |
||
1166 | } |
||
1167 | } |
||
1168 | |||
1169 | free(exec2_list); |
||
1170 | return ret; |
||
1171 | }>>><>>>>>>>>>>>>30) |