WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_gem_context.c

Rev	Author	Line No.	Line
3031	serge	1	/*
		2	* Copyright © 2011-2012 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Ben Widawsky
		25	*
		26	*/
		27
		28	/*
		29	* This file implements HW context support. On gen5+ a HW context consists of an
		30	* opaque GPU object which is referenced at times of context saves and restores.
		31	* With RC6 enabled, the context is also referenced as the GPU enters and exists
		32	* from RC6 (GPU has it's own internal power context, except on gen5). Though
		33	* something like a context does exist for the media ring, the code only
		34	* supports contexts for the render ring.
		35	*
		36	* In software, there is a distinction between contexts created by the user,
		37	* and the default HW context. The default HW context is used by GPU clients
		38	* that do not request setup of their own hardware context. The default
		39	* context's state is never restored to help prevent programming errors. This
		40	* would happen if a client ran and piggy-backed off another clients GPU state.
		41	* The default context only exists to give the GPU some offset to load as the
		42	* current to invoke a save of the context we actually care about. In fact, the
		43	* code could likely be constructed, albeit in a more complicated fashion, to
		44	* never use the default context, though that limits the driver's ability to
		45	* swap out, and/or destroy other contexts.
		46	*
		47	* All other contexts are created as a request by the GPU client. These contexts
		48	* store GPU state, and thus allow GPU clients to not re-emit state (and
		49	* potentially query certain state) at any time. The kernel driver makes
		50	* certain that the appropriate commands are inserted.
		51	*
		52	* The context life cycle is semi-complicated in that context BOs may live
		53	* longer than the context itself because of the way the hardware, and object
		54	* tracking works. Below is a very crude representation of the state machine
		55	* describing the context life.
		56	* refcount pincount active
		57	* S0: initial state 0 0 0
		58	* S1: context created 1 0 0
		59	* S2: context is currently running 2 1 X
		60	* S3: GPU referenced, but not current 2 0 1
		61	* S4: context is current, but destroyed 1 1 0
		62	* S5: like S3, but destroyed 1 0 1
		63	*
		64	* The most common (but not all) transitions:
		65	* S0->S1: client creates a context
		66	* S1->S2: client submits execbuf with context
		67	* S2->S3: other clients submits execbuf with context
		68	* S3->S1: context object was retired
		69	* S3->S2: clients submits another execbuf
		70	* S2->S4: context destroy called with current context
		71	* S3->S5->S0: destroy path
		72	* S4->S5->S0: destroy path on current context
		73	*
		74	* There are two confusing terms used above:
		75	* The "current context" means the context which is currently running on the
4560	Serge	76	* GPU. The GPU has loaded its state already and has stored away the gtt
3031	serge	77	* offset of the BO. The GPU is not actively referencing the data at this
		78	* offset, but it will on the next context switch. The only way to avoid this
		79	* is to do a GPU reset.
		80	*
		81	* An "active context' is one which was previously the "current context" and is
		82	* on the active list waiting for the next context switch to occur. Until this
		83	* happens, the object must remain at the same gtt offset. It is therefore
		84	* possible to destroy a context, but it is still active.
		85	*
		86	*/
		87
		88	#include
		89	#include
		90	#include "i915_drv.h"
5354	serge	91	#include "i915_trace.h"
3031	serge	92
		93	/* This is a HW constraint. The value below is the largest known requirement
		94	* I've seen in a spec to date, and that was a workaround for a non-shipping
		95	* part. It should be safe to decrease this, but it's more future proof as is.
		96	*/
5060	serge	97	#define GEN6_CONTEXT_ALIGN (64<<10)
		98	#define GEN7_CONTEXT_ALIGN 4096
3031	serge	99
5060	serge	100	static size_t get_context_alignment(struct drm_device *dev)
		101	{
		102	if (IS_GEN6(dev))
		103	return GEN6_CONTEXT_ALIGN;
		104
		105	return GEN7_CONTEXT_ALIGN;
		106	}
		107
3031	serge	108	static int get_context_size(struct drm_device *dev)
		109	{
		110	struct drm_i915_private *dev_priv = dev->dev_private;
		111	int ret;
		112	u32 reg;
		113
		114	switch (INTEL_INFO(dev)->gen) {
		115	case 6:
		116	reg = I915_READ(CXT_SIZE);
		117	ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
		118	break;
		119	case 7:
		120	reg = I915_READ(GEN7_CXT_SIZE);
		121	if (IS_HASWELL(dev))
4104	Serge	122	ret = HSW_CXT_TOTAL_SIZE;
3031	serge	123	else
		124	ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
		125	break;
4560	Serge	126	case 8:
		127	ret = GEN8_CXT_TOTAL_SIZE;
		128	break;
3031	serge	129	default:
		130	BUG();
		131	}
		132
		133	return ret;
		134	}
		135
6084	serge	136	static void i915_gem_context_clean(struct intel_context *ctx)
		137	{
		138	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
		139	struct i915_vma vma, next;
		140
		141	if (!ppgtt)
		142	return;
		143
		144	list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
		145	mm_list) {
		146	if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
		147	break;
		148	}
		149	}
		150
4104	Serge	151	void i915_gem_context_free(struct kref *ctx_ref)
3031	serge	152	{
6084	serge	153	struct intel_context ctx = container_of(ctx_ref, typeof(ctx), ref);
3031	serge	154
5354	serge	155	trace_i915_context_free(ctx);
5060	serge	156
5354	serge	157	if (i915.enable_execlists)
		158	intel_lr_context_free(ctx);
		159
6084	serge	160	/*
		161	* This context is going away and we need to remove all VMAs still
		162	* around. This is to handle imported shared objects for which
		163	* destructor did not run when their handles were closed.
		164	*/
		165	i915_gem_context_clean(ctx);
		166
5354	serge	167	i915_ppgtt_put(ctx->ppgtt);
		168
5060	serge	169	if (ctx->legacy_hw_ctx.rcs_state)
		170	drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
4560	Serge	171	list_del(&ctx->link);
3031	serge	172	kfree(ctx);
		173	}
		174
5354	serge	175	struct drm_i915_gem_object *
5060	serge	176	i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
		177	{
		178	struct drm_i915_gem_object *obj;
		179	int ret;
		180
		181	obj = i915_gem_alloc_object(dev, size);
		182	if (obj == NULL)
		183	return ERR_PTR(-ENOMEM);
		184
		185	/*
		186	* Try to make the context utilize L3 as well as LLC.
		187	*
		188	* On VLV we don't have L3 controls in the PTEs so we
		189	* shouldn't touch the cache level, especially as that
		190	* would make the object snooped which might have a
		191	* negative performance impact.
		192	*/
		193	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
		194	ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
		195	/* Failure shouldn't ever happen this early */
		196	if (WARN_ON(ret)) {
		197	drm_gem_object_unreference(&obj->base);
		198	return ERR_PTR(ret);
		199	}
		200	}
		201
		202	return obj;
		203	}
		204
		205	static struct intel_context *
		206	__create_hw_context(struct drm_device *dev,
6084	serge	207	struct drm_i915_file_private *file_priv)
3031	serge	208	{
		209	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	210	struct intel_context *ctx;
3480	Serge	211	int ret;
3031	serge	212
3243	Serge	213	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
3031	serge	214	if (ctx == NULL)
		215	return ERR_PTR(-ENOMEM);
		216
4104	Serge	217	kref_init(&ctx->ref);
5060	serge	218	list_add_tail(&ctx->link, &dev_priv->context_list);
6084	serge	219	ctx->i915 = dev_priv;
3031	serge	220
5060	serge	221	if (dev_priv->hw_context_size) {
		222	struct drm_i915_gem_object *obj =
		223	i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
		224	if (IS_ERR(obj)) {
		225	ret = PTR_ERR(obj);
3746	Serge	226	goto err_out;
6084	serge	227	}
5060	serge	228	ctx->legacy_hw_ctx.rcs_state = obj;
		229	}
3746	Serge	230
3031	serge	231	/* Default context will never have a file_priv */
5060	serge	232	if (file_priv != NULL) {
		233	ret = idr_alloc(&file_priv->context_idr, ctx,
		234	DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
6084	serge	235	if (ret < 0)
		236	goto err_out;
5060	serge	237	} else
		238	ret = DEFAULT_CONTEXT_HANDLE;
4104	Serge	239
		240	ctx->file_priv = file_priv;
5060	serge	241	ctx->user_handle = ret;
4560	Serge	242	/* NB: Mark all slices as needing a remap so that when the context first
		243	* loads it will restore whatever remap state already exists. If there
		244	* is no remap info, it will be a NOP. */
		245	ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
3031	serge	246
6084	serge	247	ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
		248
3031	serge	249	return ctx;
		250
		251	err_out:
4104	Serge	252	i915_gem_context_unreference(ctx);
3031	serge	253	return ERR_PTR(ret);
		254	}
		255
		256	/**
		257	* The default context needs to exist per ring that uses contexts. It stores the
		258	* context state of the GPU for applications that don't utilize HW contexts, as
		259	* well as an idle case.
		260	*/
5060	serge	261	static struct intel_context *
		262	i915_gem_create_context(struct drm_device *dev,
5354	serge	263	struct drm_i915_file_private *file_priv)
3031	serge	264	{
5060	serge	265	const bool is_global_default_ctx = file_priv == NULL;
		266	struct intel_context *ctx;
		267	int ret = 0;
3031	serge	268
5060	serge	269	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
3031	serge	270
5060	serge	271	ctx = __create_hw_context(dev, file_priv);
3031	serge	272	if (IS_ERR(ctx))
5060	serge	273	return ctx;
3031	serge	274
5060	serge	275	if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) {
		276	/* We may need to do things with the shrinker which
		277	* require us to immediately switch back to the default
		278	* context. This can cause a problem as pinning the
		279	* default context also requires GTT space which may not
		280	* be available. To avoid this we always pin the default
		281	* context.
6084	serge	282	*/
5060	serge	283	ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
		284	get_context_alignment(dev), 0);
6084	serge	285	if (ret) {
		286	DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
		287	goto err_destroy;
		288	}
4104	Serge	289	}
3031	serge	290
5354	serge	291	if (USES_FULL_PPGTT(dev)) {
		292	struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
5060	serge	293
		294	if (IS_ERR_OR_NULL(ppgtt)) {
		295	DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
		296	PTR_ERR(ppgtt));
		297	ret = PTR_ERR(ppgtt);
		298	goto err_unpin;
5354	serge	299	}
5060	serge	300
5354	serge	301	ctx->ppgtt = ppgtt;
4104	Serge	302	}
3031	serge	303
5354	serge	304	trace_i915_context_create(ctx);
4560	Serge	305
5060	serge	306	return ctx;
3031	serge	307
		308	err_unpin:
5060	serge	309	if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state)
		310	i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
3031	serge	311	err_destroy:
6084	serge	312	idr_remove(&file_priv->context_idr, ctx->user_handle);
4104	Serge	313	i915_gem_context_unreference(ctx);
5060	serge	314	return ERR_PTR(ret);
3031	serge	315	}
		316
5060	serge	317	void i915_gem_context_reset(struct drm_device *dev)
		318	{
		319	struct drm_i915_private *dev_priv = dev->dev_private;
		320	int i;
		321
6084	serge	322	if (i915.enable_execlists) {
		323	struct intel_context *ctx;
		324
		325	list_for_each_entry(ctx, &dev_priv->context_list, link) {
		326	intel_lr_context_reset(dev, ctx);
		327	}
		328
5354	serge	329	return;
6084	serge	330	}
5354	serge	331
5060	serge	332	for (i = 0; i < I915_NUM_RINGS; i++) {
		333	struct intel_engine_cs *ring = &dev_priv->ring[i];
		334	struct intel_context *lctx = ring->last_context;
		335
5354	serge	336	if (lctx) {
6084	serge	337	if (lctx->legacy_hw_ctx.rcs_state && i == RCS)
		338	i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state);
5060	serge	339
6084	serge	340	i915_gem_context_unreference(lctx);
5354	serge	341	ring->last_context = NULL;
		342	}
6320	serge	343
		344	/* Force the GPU state to be reinitialised on enabling */
		345	if (ring->default_context)
		346	ring->default_context->legacy_hw_ctx.initialized = false;
5060	serge	347	}
		348	}
		349
4560	Serge	350	int i915_gem_context_init(struct drm_device *dev)
3031	serge	351	{
		352	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	353	struct intel_context *ctx;
		354	int i;
3031	serge	355
5060	serge	356	/* Init should only be called once per module load. Eventually the
		357	* restriction on the context_disabled check can be loosened. */
		358	if (WARN_ON(dev_priv->ring[RCS].default_context))
4560	Serge	359	return 0;
3031	serge	360
6084	serge	361	if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
		362	if (!i915.enable_execlists) {
		363	DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
		364	return -EINVAL;
		365	}
		366	}
		367
5354	serge	368	if (i915.enable_execlists) {
		369	/* NB: intentionally left blank. We will allocate our own
		370	* backing objects as we need them, thank you very much */
		371	dev_priv->hw_context_size = 0;
		372	} else if (HAS_HW_CONTEXTS(dev)) {
6084	serge	373	dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
		374	if (dev_priv->hw_context_size > (1<<20)) {
5060	serge	375	DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
		376	dev_priv->hw_context_size);
		377	dev_priv->hw_context_size = 0;
		378	}
3031	serge	379	}
		380
5354	serge	381	ctx = i915_gem_create_context(dev, NULL);
5060	serge	382	if (IS_ERR(ctx)) {
		383	DRM_ERROR("Failed to create default global context (error %ld)\n",
		384	PTR_ERR(ctx));
		385	return PTR_ERR(ctx);
3031	serge	386	}
		387
5354	serge	388	for (i = 0; i < I915_NUM_RINGS; i++) {
		389	struct intel_engine_cs *ring = &dev_priv->ring[i];
		390
6084	serge	391	/* NB: RCS will hold a ref for all rings */
5354	serge	392	ring->default_context = ctx;
		393	}
5060	serge	394
5354	serge	395	DRM_DEBUG_DRIVER("%s context support initialized\n",
		396	i915.enable_execlists ? "LR" :
		397	dev_priv->hw_context_size ? "HW" : "fake");
4560	Serge	398	return 0;
3031	serge	399	}
		400
		401	void i915_gem_context_fini(struct drm_device *dev)
		402	{
		403	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	404	struct intel_context *dctx = dev_priv->ring[RCS].default_context;
		405	int i;
3031	serge	406
5060	serge	407	if (dctx->legacy_hw_ctx.rcs_state) {
6084	serge	408	/* The only known way to stop the gpu from accessing the hw context is
		409	* to reset it. Do this as the very last operation to avoid confusing
		410	* other code, leading to spurious errors. */
		411	intel_gpu_reset(dev);
3031	serge	412
6084	serge	413	/* When default context is created and switched to, base object refcount
		414	* will be 2 (+1 from object creation and +1 from do_switch()).
		415	* i915_gem_context_fini() will be called after gpu_idle() has switched
		416	* to default context. So we need to unreference the base object once
		417	* to offset the do_switch part, so that i915_gem_context_unreference()
		418	* can then free the base object correctly. */
		419	WARN_ON(!dev_priv->ring[RCS].last_context);
		420	if (dev_priv->ring[RCS].last_context == dctx) {
		421	/* Fake switch to NULL context */
5060	serge	422	WARN_ON(dctx->legacy_hw_ctx.rcs_state->active);
		423	i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
6084	serge	424	i915_gem_context_unreference(dctx);
5060	serge	425	dev_priv->ring[RCS].last_context = NULL;
6084	serge	426	}
4560	Serge	427
5060	serge	428	i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
		429	}
		430
		431	for (i = 0; i < I915_NUM_RINGS; i++) {
		432	struct intel_engine_cs *ring = &dev_priv->ring[i];
		433
		434	if (ring->last_context)
		435	i915_gem_context_unreference(ring->last_context);
		436
		437	ring->default_context = NULL;
		438	ring->last_context = NULL;
		439	}
		440
4560	Serge	441	i915_gem_context_unreference(dctx);
3031	serge	442	}
		443
6084	serge	444	int i915_gem_context_enable(struct drm_i915_gem_request *req)
5060	serge	445	{
6084	serge	446	struct intel_engine_cs *ring = req->ring;
		447	int ret;
5060	serge	448
6084	serge	449	if (i915.enable_execlists) {
		450	if (ring->init_context == NULL)
		451	return 0;
5060	serge	452
6084	serge	453	ret = ring->init_context(req);
		454	} else
		455	ret = i915_switch_context(req);
5060	serge	456
6084	serge	457	if (ret) {
		458	DRM_ERROR("ring init context: %d\n", ret);
		459	return ret;
5060	serge	460	}
		461
		462	return 0;
		463	}
		464
3031	serge	465	static int context_idr_cleanup(int id, void p, void data)
		466	{
5060	serge	467	struct intel_context *ctx = p;
3031	serge	468
4280	Serge	469	i915_gem_context_unreference(ctx);
		470	return 0;
		471	}
3031	serge	472
5060	serge	473	int i915_gem_context_open(struct drm_device dev, struct drm_file file)
4280	Serge	474	{
		475	struct drm_i915_file_private *file_priv = file->driver_priv;
5060	serge	476	struct intel_context *ctx;
4104	Serge	477
5060	serge	478	idr_init(&file_priv->context_idr);
4280	Serge	479
5060	serge	480	mutex_lock(&dev->struct_mutex);
5354	serge	481	ctx = i915_gem_create_context(dev, file_priv);
5060	serge	482	mutex_unlock(&dev->struct_mutex);
4560	Serge	483
5060	serge	484	if (IS_ERR(ctx)) {
		485	idr_destroy(&file_priv->context_idr);
		486	return PTR_ERR(ctx);
		487	}
4280	Serge	488
5060	serge	489	return 0;
3031	serge	490	}
		491
		492	void i915_gem_context_close(struct drm_device dev, struct drm_file file)
		493	{
		494	struct drm_i915_file_private *file_priv = file->driver_priv;
		495
4246	Serge	496	idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
3031	serge	497	idr_destroy(&file_priv->context_idr);
		498	}
		499
5060	serge	500	struct intel_context *
3031	serge	501	i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
		502	{
5060	serge	503	struct intel_context *ctx;
		504
		505	ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id);
		506	if (!ctx)
		507	return ERR_PTR(-ENOENT);
		508
		509	return ctx;
3031	serge	510	}
		511
		512	static inline int
6084	serge	513	mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
3031	serge	514	{
6084	serge	515	struct intel_engine_cs *ring = req->ring;
5354	serge	516	u32 flags = hw_flags \| MI_MM_SPACE_GTT;
		517	const int num_rings =
		518	/* Use an extended w/a on ivb+ if signalling from other rings */
		519	i915_semaphore_is_enabled(ring->dev) ?
		520	hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
		521	0;
		522	int len, i, ret;
3031	serge	523
		524	/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
		525	* invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
		526	* explicitly, so we rely on the value at ring init, stored in
		527	* itlb_before_ctx_switch.
		528	*/
5060	serge	529	if (IS_GEN6(ring->dev)) {
6084	serge	530	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
3031	serge	531	if (ret)
		532	return ret;
		533	}
		534
5354	serge	535	/* These flags are for resource streamer on HSW+ */
6084	serge	536	if (IS_HASWELL(ring->dev) \|\| INTEL_INFO(ring->dev)->gen >= 8)
		537	flags \|= (HSW_MI_RS_SAVE_STATE_EN \| HSW_MI_RS_RESTORE_STATE_EN);
		538	else if (INTEL_INFO(ring->dev)->gen < 8)
5354	serge	539	flags \|= (MI_SAVE_EXT_STATE_EN \| MI_RESTORE_EXT_STATE_EN);
		540
		541
		542	len = 4;
		543	if (INTEL_INFO(ring->dev)->gen >= 7)
		544	len += 2 + (num_rings ? 4*num_rings + 2 : 0);
		545
6084	serge	546	ret = intel_ring_begin(req, len);
3031	serge	547	if (ret)
		548	return ret;
		549
5060	serge	550	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
5354	serge	551	if (INTEL_INFO(ring->dev)->gen >= 7) {
3031	serge	552	intel_ring_emit(ring, MI_ARB_ON_OFF \| MI_ARB_DISABLE);
5354	serge	553	if (num_rings) {
		554	struct intel_engine_cs *signaller;
3031	serge	555
5354	serge	556	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
		557	for_each_ring(signaller, to_i915(ring->dev), i) {
		558	if (signaller == ring)
		559	continue;
		560
		561	intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
		562	intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
		563	}
		564	}
		565	}
		566
3031	serge	567	intel_ring_emit(ring, MI_NOOP);
		568	intel_ring_emit(ring, MI_SET_CONTEXT);
6084	serge	569	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) \|
5354	serge	570	flags);
5060	serge	571	/*
		572	* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
		573	* WaMiSetContext_Hang:snb,ivb,vlv
		574	*/
3031	serge	575	intel_ring_emit(ring, MI_NOOP);
		576
5354	serge	577	if (INTEL_INFO(ring->dev)->gen >= 7) {
		578	if (num_rings) {
		579	struct intel_engine_cs *signaller;
		580
		581	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
		582	for_each_ring(signaller, to_i915(ring->dev), i) {
		583	if (signaller == ring)
		584	continue;
		585
		586	intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
		587	intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
		588	}
		589	}
3031	serge	590	intel_ring_emit(ring, MI_ARB_ON_OFF \| MI_ARB_ENABLE);
5354	serge	591	}
3031	serge	592
		593	intel_ring_advance(ring);
		594
		595	return ret;
		596	}
		597
6084	serge	598	static inline bool should_skip_switch(struct intel_engine_cs *ring,
		599	struct intel_context *from,
		600	struct intel_context *to)
3031	serge	601	{
6084	serge	602	if (to->remap_slice)
		603	return false;
		604
		605	if (to->ppgtt && from == to &&
		606	!(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings))
		607	return true;
		608
		609	return false;
		610	}
		611
		612	static bool
		613	needs_pd_load_pre(struct intel_engine_cs ring, struct intel_context to)
		614	{
5060	serge	615	struct drm_i915_private *dev_priv = ring->dev->dev_private;
6084	serge	616
		617	if (!to->ppgtt)
		618	return false;
		619
		620	if (INTEL_INFO(ring->dev)->gen < 8)
		621	return true;
		622
		623	if (ring != &dev_priv->ring[RCS])
		624	return true;
		625
		626	return false;
		627	}
		628
		629	static bool
		630	needs_pd_load_post(struct intel_engine_cs ring, struct intel_context to,
		631	u32 hw_flags)
		632	{
		633	struct drm_i915_private *dev_priv = ring->dev->dev_private;
		634
		635	if (!to->ppgtt)
		636	return false;
		637
		638	if (!IS_GEN8(ring->dev))
		639	return false;
		640
		641	if (ring != &dev_priv->ring[RCS])
		642	return false;
		643
		644	if (hw_flags & MI_RESTORE_INHIBIT)
		645	return true;
		646
		647	return false;
		648	}
		649
		650	static int do_switch(struct drm_i915_gem_request *req)
		651	{
		652	struct intel_context *to = req->ctx;
		653	struct intel_engine_cs *ring = req->ring;
		654	struct drm_i915_private *dev_priv = ring->dev->dev_private;
5060	serge	655	struct intel_context *from = ring->last_context;
3031	serge	656	u32 hw_flags = 0;
5060	serge	657	bool uninitialized = false;
4560	Serge	658	int ret, i;
3031	serge	659
5060	serge	660	if (from != NULL && ring == &dev_priv->ring[RCS]) {
		661	BUG_ON(from->legacy_hw_ctx.rcs_state == NULL);
		662	BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state));
		663	}
3031	serge	664
6084	serge	665	if (should_skip_switch(ring, from, to))
3031	serge	666	return 0;
		667
5060	serge	668	/* Trying to pin first makes error handling easier. */
		669	if (ring == &dev_priv->ring[RCS]) {
		670	ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
		671	get_context_alignment(ring->dev), 0);
6084	serge	672	if (ret)
		673	return ret;
5060	serge	674	}
3031	serge	675
4539	Serge	676	/*
		677	* Pin can switch back to the default context if we end up calling into
		678	* evict_everything - as a last ditch gtt defrag effort that also
		679	* switches to the default context. Hence we need to reload from here.
		680	*/
		681	from = ring->last_context;
		682
6084	serge	683	if (needs_pd_load_pre(ring, to)) {
		684	/* Older GENs and non render rings still want the load first,
		685	* "PP_DCLV followed by PP_DIR_BASE register through Load
		686	* Register Immediate commands in Ring Buffer before submitting
		687	* a context."*/
5354	serge	688	trace_switch_mm(ring, to);
6084	serge	689	ret = to->ppgtt->switch_mm(to->ppgtt, req);
5060	serge	690	if (ret)
		691	goto unpin_out;
6084	serge	692
		693	/* Doing a PD load always reloads the page dirs */
		694	to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
5060	serge	695	}
		696
		697	if (ring != &dev_priv->ring[RCS]) {
		698	if (from)
		699	i915_gem_context_unreference(from);
		700	goto done;
		701	}
		702
4539	Serge	703	/*
		704	* Clear this page out of any CPU caches for coherent swap-in/out. Note
3031	serge	705	* that thanks to write = false in this call and us not setting any gpu
		706	* write domains when putting a context object onto the active list
		707	* (when switching away from it), this won't block.
4539	Serge	708	*
		709	* XXX: We need a real interface to do this instead of trickery.
		710	*/
5060	serge	711	ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false);
		712	if (ret)
		713	goto unpin_out;
		714
6320	serge	715	if (!to->legacy_hw_ctx.initialized \|\| i915_gem_context_is_default(to)) {
3031	serge	716	hw_flags \|= MI_RESTORE_INHIBIT;
6084	serge	717	/* NB: If we inhibit the restore, the context is not allowed to
		718	* die because future work may end up depending on valid address
		719	* space. This means we must enforce that a page table load
		720	* occur when this occurs. */
		721	} else if (to->ppgtt &&
		722	(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) {
		723	hw_flags \|= MI_FORCE_RESTORE;
		724	to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
		725	}
3031	serge	726
6084	serge	727	/* We should never emit switch_mm more than once */
		728	WARN_ON(needs_pd_load_pre(ring, to) &&
		729	needs_pd_load_post(ring, to, hw_flags));
		730
		731	ret = mi_set_context(req, hw_flags);
5060	serge	732	if (ret)
		733	goto unpin_out;
3031	serge	734
6084	serge	735	/* GEN8 does not require an explicit reload if the PDPs have been
		736	* setup, and we do not wish to move them.
		737	*/
		738	if (needs_pd_load_post(ring, to, hw_flags)) {
		739	trace_switch_mm(ring, to);
		740	ret = to->ppgtt->switch_mm(to->ppgtt, req);
		741	/* The hardware context switch is emitted, but we haven't
		742	* actually changed the state - so it's probably safe to bail
		743	* here. Still, let the user know something dangerous has
		744	* happened.
		745	*/
		746	if (ret) {
		747	DRM_ERROR("Failed to change address space on context switch\n");
		748	goto unpin_out;
		749	}
		750	}
		751
4560	Serge	752	for (i = 0; i < MAX_L3_SLICES; i++) {
		753	if (!(to->remap_slice & (1<
		754	continue;
		755
6084	serge	756	ret = i915_gem_l3_remap(req, i);
4560	Serge	757	/* If it failed, try again next round */
		758	if (ret)
		759	DRM_DEBUG_DRIVER("L3 remapping failed\n");
		760	else
		761	to->remap_slice &= ~(1<
		762	}
		763
3031	serge	764	/* The backing object for the context is done after switching to the
		765	* next context. Therefore we cannot retire the previous context until
		766	* the next context has already started running. In fact, the below code
		767	* is a bit suboptimal because the retiring can occur simply after the
		768	* MI_SET_CONTEXT instead of when the next seqno has completed.
		769	*/
4104	Serge	770	if (from != NULL) {
5060	serge	771	from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
6084	serge	772	i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req);
3031	serge	773	/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
		774	* whole damn pipeline, we don't need to explicitly mark the
		775	* object dirty. The only exception is that the context must be
		776	* correct in case the object gets swapped out. Ideally we'd be
		777	* able to defer doing this until we know the object would be
		778	* swapped, but there is no way to do that yet.
		779	*/
5060	serge	780	from->legacy_hw_ctx.rcs_state->dirty = 1;
3031	serge	781
4560	Serge	782	/* obj is kept alive until the next request by its active ref */
5060	serge	783	i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state);
4104	Serge	784	i915_gem_context_unreference(from);
3031	serge	785	}
		786
6084	serge	787	uninitialized = !to->legacy_hw_ctx.initialized;
5060	serge	788	to->legacy_hw_ctx.initialized = true;
		789
		790	done:
4104	Serge	791	i915_gem_context_reference(to);
		792	ring->last_context = to;
3031	serge	793
5060	serge	794	if (uninitialized) {
5354	serge	795	if (ring->init_context) {
6084	serge	796	ret = ring->init_context(req);
5354	serge	797	if (ret)
		798	DRM_ERROR("ring init context: %d\n", ret);
		799	}
5060	serge	800	}
		801
3031	serge	802	return 0;
5060	serge	803
		804	unpin_out:
		805	if (ring->id == RCS)
		806	i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
		807	return ret;
3031	serge	808	}
		809
		810	/**
		811	* i915_switch_context() - perform a GPU context switch.
6084	serge	812	* @req: request for which we'll execute the context switch
3031	serge	813	*
		814	* The context life cycle is simple. The context refcount is incremented and
		815	* decremented by 1 and create and destroy. If the context is in use by the GPU,
5354	serge	816	* it will have a refcount > 1. This allows us to destroy the context abstract
3031	serge	817	* object while letting the normal object tracking destroy the backing BO.
5354	serge	818	*
		819	* This function should not be used in execlists mode. Instead the context is
		820	* switched by writing to the ELSP and requests keep a reference to their
		821	* context.
3031	serge	822	*/
6084	serge	823	int i915_switch_context(struct drm_i915_gem_request *req)
3031	serge	824	{
6084	serge	825	struct intel_engine_cs *ring = req->ring;
3031	serge	826	struct drm_i915_private *dev_priv = ring->dev->dev_private;
		827
5354	serge	828	WARN_ON(i915.enable_execlists);
4104	Serge	829	WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
		830
6084	serge	831	if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
		832	if (req->ctx != ring->last_context) {
		833	i915_gem_context_reference(req->ctx);
5060	serge	834	if (ring->last_context)
		835	i915_gem_context_unreference(ring->last_context);
6084	serge	836	ring->last_context = req->ctx;
5060	serge	837	}
3031	serge	838	return 0;
		839	}
		840
6084	serge	841	return do_switch(req);
3031	serge	842	}
		843
5354	serge	844	static bool contexts_enabled(struct drm_device *dev)
5060	serge	845	{
5354	serge	846	return i915.enable_execlists \|\| to_i915(dev)->hw_context_size;
5060	serge	847	}
		848
3031	serge	849	int i915_gem_context_create_ioctl(struct drm_device dev, void data,
		850	struct drm_file *file)
		851	{
		852	struct drm_i915_gem_context_create *args = data;
		853	struct drm_i915_file_private *file_priv = file->driver_priv;
5060	serge	854	struct intel_context *ctx;
3031	serge	855	int ret;
		856
5354	serge	857	if (!contexts_enabled(dev))
3031	serge	858	return -ENODEV;
		859
		860	ret = i915_mutex_lock_interruptible(dev);
		861	if (ret)
		862	return ret;
		863
5354	serge	864	ctx = i915_gem_create_context(dev, file_priv);
3031	serge	865	mutex_unlock(&dev->struct_mutex);
		866	if (IS_ERR(ctx))
		867	return PTR_ERR(ctx);
		868
5060	serge	869	args->ctx_id = ctx->user_handle;
3031	serge	870	DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
		871
		872	return 0;
		873	}
		874
		875	int i915_gem_context_destroy_ioctl(struct drm_device dev, void data,
		876	struct drm_file *file)
		877	{
		878	struct drm_i915_gem_context_destroy *args = data;
		879	struct drm_i915_file_private *file_priv = file->driver_priv;
5060	serge	880	struct intel_context *ctx;
3031	serge	881	int ret;
		882
5060	serge	883	if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
		884	return -ENOENT;
3031	serge	885
		886	ret = i915_mutex_lock_interruptible(dev);
		887	if (ret)
		888	return ret;
		889
		890	ctx = i915_gem_context_get(file_priv, args->ctx_id);
5060	serge	891	if (IS_ERR(ctx)) {
3031	serge	892	mutex_unlock(&dev->struct_mutex);
5060	serge	893	return PTR_ERR(ctx);
3031	serge	894	}
		895
5060	serge	896	idr_remove(&ctx->file_priv->context_idr, ctx->user_handle);
4246	Serge	897	i915_gem_context_unreference(ctx);
3031	serge	898	mutex_unlock(&dev->struct_mutex);
		899
		900	DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
		901	return 0;
		902	}
6084	serge	903
		904	int i915_gem_context_getparam_ioctl(struct drm_device dev, void data,
		905	struct drm_file *file)
		906	{
		907	struct drm_i915_file_private *file_priv = file->driver_priv;
		908	struct drm_i915_gem_context_param *args = data;
		909	struct intel_context *ctx;
		910	int ret;
		911
		912	ret = i915_mutex_lock_interruptible(dev);
		913	if (ret)
		914	return ret;
		915
		916	ctx = i915_gem_context_get(file_priv, args->ctx_id);
		917	if (IS_ERR(ctx)) {
		918	mutex_unlock(&dev->struct_mutex);
		919	return PTR_ERR(ctx);
		920	}
		921
		922	args->size = 0;
		923	switch (args->param) {
		924	case I915_CONTEXT_PARAM_BAN_PERIOD:
		925	args->value = ctx->hang_stats.ban_period_seconds;
		926	break;
		927	case I915_CONTEXT_PARAM_NO_ZEROMAP:
		928	args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
		929	break;
		930	default:
		931	ret = -EINVAL;
		932	break;
		933	}
		934	mutex_unlock(&dev->struct_mutex);
		935
		936	return ret;
		937	}
		938
		939	int i915_gem_context_setparam_ioctl(struct drm_device dev, void data,
		940	struct drm_file *file)
		941	{
		942	struct drm_i915_file_private *file_priv = file->driver_priv;
		943	struct drm_i915_gem_context_param *args = data;
		944	struct intel_context *ctx;
		945	int ret;
		946
		947	ret = i915_mutex_lock_interruptible(dev);
		948	if (ret)
		949	return ret;
		950
		951	ctx = i915_gem_context_get(file_priv, args->ctx_id);
		952	if (IS_ERR(ctx)) {
		953	mutex_unlock(&dev->struct_mutex);
		954	return PTR_ERR(ctx);
		955	}
		956
		957	switch (args->param) {
		958	case I915_CONTEXT_PARAM_BAN_PERIOD:
		959	if (args->size)
		960	ret = -EINVAL;
		961	else if (args->value < ctx->hang_stats.ban_period_seconds)
		962	ret = -EPERM;
		963	else
		964	ctx->hang_stats.ban_period_seconds = args->value;
		965	break;
		966	case I915_CONTEXT_PARAM_NO_ZEROMAP:
		967	if (args->size) {
		968	ret = -EINVAL;
		969	} else {
		970	ctx->flags &= ~CONTEXT_NO_ZEROMAP;
		971	ctx->flags \|= args->value ? CONTEXT_NO_ZEROMAP : 0;
		972	}
		973	break;
		974	default:
		975	ret = -EINVAL;
		976	break;
		977	}
		978	mutex_unlock(&dev->struct_mutex);
		979
		980	return ret;
		981	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem_context.c – Rev 6320