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3031 | serge | 1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Ben Widawsky |
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25 | * |
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26 | */ |
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27 | |||
28 | /* |
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29 | * This file implements HW context support. On gen5+ a HW context consists of an |
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30 | * opaque GPU object which is referenced at times of context saves and restores. |
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31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists |
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32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though |
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33 | * something like a context does exist for the media ring, the code only |
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34 | * supports contexts for the render ring. |
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35 | * |
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36 | * In software, there is a distinction between contexts created by the user, |
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37 | * and the default HW context. The default HW context is used by GPU clients |
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38 | * that do not request setup of their own hardware context. The default |
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39 | * context's state is never restored to help prevent programming errors. This |
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40 | * would happen if a client ran and piggy-backed off another clients GPU state. |
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41 | * The default context only exists to give the GPU some offset to load as the |
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42 | * current to invoke a save of the context we actually care about. In fact, the |
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43 | * code could likely be constructed, albeit in a more complicated fashion, to |
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44 | * never use the default context, though that limits the driver's ability to |
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45 | * swap out, and/or destroy other contexts. |
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46 | * |
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47 | * All other contexts are created as a request by the GPU client. These contexts |
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48 | * store GPU state, and thus allow GPU clients to not re-emit state (and |
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49 | * potentially query certain state) at any time. The kernel driver makes |
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50 | * certain that the appropriate commands are inserted. |
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51 | * |
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52 | * The context life cycle is semi-complicated in that context BOs may live |
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53 | * longer than the context itself because of the way the hardware, and object |
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54 | * tracking works. Below is a very crude representation of the state machine |
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55 | * describing the context life. |
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56 | * refcount pincount active |
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57 | * S0: initial state 0 0 0 |
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58 | * S1: context created 1 0 0 |
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59 | * S2: context is currently running 2 1 X |
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60 | * S3: GPU referenced, but not current 2 0 1 |
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61 | * S4: context is current, but destroyed 1 1 0 |
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62 | * S5: like S3, but destroyed 1 0 1 |
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63 | * |
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64 | * The most common (but not all) transitions: |
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65 | * S0->S1: client creates a context |
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66 | * S1->S2: client submits execbuf with context |
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67 | * S2->S3: other clients submits execbuf with context |
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68 | * S3->S1: context object was retired |
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69 | * S3->S2: clients submits another execbuf |
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70 | * S2->S4: context destroy called with current context |
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71 | * S3->S5->S0: destroy path |
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72 | * S4->S5->S0: destroy path on current context |
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73 | * |
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74 | * There are two confusing terms used above: |
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75 | * The "current context" means the context which is currently running on the |
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4560 | Serge | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
3031 | serge | 77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this |
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79 | * is to do a GPU reset. |
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80 | * |
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81 | * An "active context' is one which was previously the "current context" and is |
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82 | * on the active list waiting for the next context switch to occur. Until this |
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83 | * happens, the object must remain at the same gtt offset. It is therefore |
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84 | * possible to destroy a context, but it is still active. |
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85 | * |
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86 | */ |
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87 | |||
88 | #include |
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89 | #include |
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90 | #include "i915_drv.h" |
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5354 | serge | 91 | #include "i915_trace.h" |
3031 | serge | 92 | |
93 | /* This is a HW constraint. The value below is the largest known requirement |
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94 | * I've seen in a spec to date, and that was a workaround for a non-shipping |
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95 | * part. It should be safe to decrease this, but it's more future proof as is. |
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96 | */ |
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5060 | serge | 97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
98 | #define GEN7_CONTEXT_ALIGN 4096 |
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3031 | serge | 99 | |
5060 | serge | 100 | static size_t get_context_alignment(struct drm_device *dev) |
101 | { |
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102 | if (IS_GEN6(dev)) |
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103 | return GEN6_CONTEXT_ALIGN; |
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104 | |||
105 | return GEN7_CONTEXT_ALIGN; |
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106 | } |
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107 | |||
3031 | serge | 108 | static int get_context_size(struct drm_device *dev) |
109 | { |
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110 | struct drm_i915_private *dev_priv = dev->dev_private; |
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111 | int ret; |
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112 | u32 reg; |
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113 | |||
114 | switch (INTEL_INFO(dev)->gen) { |
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115 | case 6: |
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116 | reg = I915_READ(CXT_SIZE); |
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117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; |
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118 | break; |
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119 | case 7: |
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120 | reg = I915_READ(GEN7_CXT_SIZE); |
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121 | if (IS_HASWELL(dev)) |
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4104 | Serge | 122 | ret = HSW_CXT_TOTAL_SIZE; |
3031 | serge | 123 | else |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; |
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125 | break; |
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4560 | Serge | 126 | case 8: |
127 | ret = GEN8_CXT_TOTAL_SIZE; |
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128 | break; |
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3031 | serge | 129 | default: |
130 | BUG(); |
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131 | } |
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132 | |||
133 | return ret; |
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134 | } |
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135 | |||
6084 | serge | 136 | static void i915_gem_context_clean(struct intel_context *ctx) |
137 | { |
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138 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
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139 | struct i915_vma *vma, *next; |
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140 | |||
141 | if (!ppgtt) |
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142 | return; |
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143 | |||
144 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
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145 | mm_list) { |
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146 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
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147 | break; |
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148 | } |
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149 | } |
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150 | |||
4104 | Serge | 151 | void i915_gem_context_free(struct kref *ctx_ref) |
3031 | serge | 152 | { |
6084 | serge | 153 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
3031 | serge | 154 | |
5354 | serge | 155 | trace_i915_context_free(ctx); |
5060 | serge | 156 | |
5354 | serge | 157 | if (i915.enable_execlists) |
158 | intel_lr_context_free(ctx); |
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159 | |||
6084 | serge | 160 | /* |
161 | * This context is going away and we need to remove all VMAs still |
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162 | * around. This is to handle imported shared objects for which |
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163 | * destructor did not run when their handles were closed. |
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164 | */ |
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165 | i915_gem_context_clean(ctx); |
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166 | |||
5354 | serge | 167 | i915_ppgtt_put(ctx->ppgtt); |
168 | |||
5060 | serge | 169 | if (ctx->legacy_hw_ctx.rcs_state) |
170 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); |
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4560 | Serge | 171 | list_del(&ctx->link); |
3031 | serge | 172 | kfree(ctx); |
173 | } |
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174 | |||
5354 | serge | 175 | struct drm_i915_gem_object * |
5060 | serge | 176 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
177 | { |
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178 | struct drm_i915_gem_object *obj; |
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179 | int ret; |
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180 | |||
181 | obj = i915_gem_alloc_object(dev, size); |
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182 | if (obj == NULL) |
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183 | return ERR_PTR(-ENOMEM); |
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184 | |||
185 | /* |
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186 | * Try to make the context utilize L3 as well as LLC. |
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187 | * |
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188 | * On VLV we don't have L3 controls in the PTEs so we |
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189 | * shouldn't touch the cache level, especially as that |
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190 | * would make the object snooped which might have a |
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191 | * negative performance impact. |
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192 | */ |
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193 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { |
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194 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
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195 | /* Failure shouldn't ever happen this early */ |
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196 | if (WARN_ON(ret)) { |
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197 | drm_gem_object_unreference(&obj->base); |
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198 | return ERR_PTR(ret); |
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199 | } |
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200 | } |
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201 | |||
202 | return obj; |
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203 | } |
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204 | |||
205 | static struct intel_context * |
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206 | __create_hw_context(struct drm_device *dev, |
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6084 | serge | 207 | struct drm_i915_file_private *file_priv) |
3031 | serge | 208 | { |
209 | struct drm_i915_private *dev_priv = dev->dev_private; |
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5060 | serge | 210 | struct intel_context *ctx; |
3480 | Serge | 211 | int ret; |
3031 | serge | 212 | |
3243 | Serge | 213 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
3031 | serge | 214 | if (ctx == NULL) |
215 | return ERR_PTR(-ENOMEM); |
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216 | |||
4104 | Serge | 217 | kref_init(&ctx->ref); |
5060 | serge | 218 | list_add_tail(&ctx->link, &dev_priv->context_list); |
6084 | serge | 219 | ctx->i915 = dev_priv; |
3031 | serge | 220 | |
5060 | serge | 221 | if (dev_priv->hw_context_size) { |
222 | struct drm_i915_gem_object *obj = |
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223 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); |
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224 | if (IS_ERR(obj)) { |
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225 | ret = PTR_ERR(obj); |
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3746 | Serge | 226 | goto err_out; |
6084 | serge | 227 | } |
5060 | serge | 228 | ctx->legacy_hw_ctx.rcs_state = obj; |
229 | } |
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3746 | Serge | 230 | |
3031 | serge | 231 | /* Default context will never have a file_priv */ |
5060 | serge | 232 | if (file_priv != NULL) { |
233 | ret = idr_alloc(&file_priv->context_idr, ctx, |
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234 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
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6084 | serge | 235 | if (ret < 0) |
236 | goto err_out; |
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5060 | serge | 237 | } else |
238 | ret = DEFAULT_CONTEXT_HANDLE; |
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4104 | Serge | 239 | |
240 | ctx->file_priv = file_priv; |
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5060 | serge | 241 | ctx->user_handle = ret; |
4560 | Serge | 242 | /* NB: Mark all slices as needing a remap so that when the context first |
243 | * loads it will restore whatever remap state already exists. If there |
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244 | * is no remap info, it will be a NOP. */ |
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245 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; |
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3031 | serge | 246 | |
6084 | serge | 247 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
248 | |||
3031 | serge | 249 | return ctx; |
250 | |||
251 | err_out: |
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4104 | Serge | 252 | i915_gem_context_unreference(ctx); |
3031 | serge | 253 | return ERR_PTR(ret); |
254 | } |
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255 | |||
256 | /** |
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257 | * The default context needs to exist per ring that uses contexts. It stores the |
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258 | * context state of the GPU for applications that don't utilize HW contexts, as |
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259 | * well as an idle case. |
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260 | */ |
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5060 | serge | 261 | static struct intel_context * |
262 | i915_gem_create_context(struct drm_device *dev, |
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5354 | serge | 263 | struct drm_i915_file_private *file_priv) |
3031 | serge | 264 | { |
5060 | serge | 265 | const bool is_global_default_ctx = file_priv == NULL; |
266 | struct intel_context *ctx; |
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267 | int ret = 0; |
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3031 | serge | 268 | |
5060 | serge | 269 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
3031 | serge | 270 | |
5060 | serge | 271 | ctx = __create_hw_context(dev, file_priv); |
3031 | serge | 272 | if (IS_ERR(ctx)) |
5060 | serge | 273 | return ctx; |
3031 | serge | 274 | |
5060 | serge | 275 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
276 | /* We may need to do things with the shrinker which |
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277 | * require us to immediately switch back to the default |
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278 | * context. This can cause a problem as pinning the |
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279 | * default context also requires GTT space which may not |
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280 | * be available. To avoid this we always pin the default |
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281 | * context. |
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6084 | serge | 282 | */ |
5060 | serge | 283 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
284 | get_context_alignment(dev), 0); |
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6084 | serge | 285 | if (ret) { |
286 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); |
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287 | goto err_destroy; |
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288 | } |
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4104 | Serge | 289 | } |
3031 | serge | 290 | |
5354 | serge | 291 | if (USES_FULL_PPGTT(dev)) { |
292 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
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5060 | serge | 293 | |
294 | if (IS_ERR_OR_NULL(ppgtt)) { |
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295 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
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296 | PTR_ERR(ppgtt)); |
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297 | ret = PTR_ERR(ppgtt); |
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298 | goto err_unpin; |
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5354 | serge | 299 | } |
5060 | serge | 300 | |
5354 | serge | 301 | ctx->ppgtt = ppgtt; |
4104 | Serge | 302 | } |
3031 | serge | 303 | |
5354 | serge | 304 | trace_i915_context_create(ctx); |
4560 | Serge | 305 | |
5060 | serge | 306 | return ctx; |
3031 | serge | 307 | |
308 | err_unpin: |
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5060 | serge | 309 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
310 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); |
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3031 | serge | 311 | err_destroy: |
6084 | serge | 312 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
4104 | Serge | 313 | i915_gem_context_unreference(ctx); |
5060 | serge | 314 | return ERR_PTR(ret); |
3031 | serge | 315 | } |
316 | |||
5060 | serge | 317 | void i915_gem_context_reset(struct drm_device *dev) |
318 | { |
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319 | struct drm_i915_private *dev_priv = dev->dev_private; |
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320 | int i; |
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321 | |||
6084 | serge | 322 | if (i915.enable_execlists) { |
323 | struct intel_context *ctx; |
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324 | |||
325 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
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326 | intel_lr_context_reset(dev, ctx); |
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327 | } |
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328 | |||
5354 | serge | 329 | return; |
6084 | serge | 330 | } |
5354 | serge | 331 | |
5060 | serge | 332 | for (i = 0; i < I915_NUM_RINGS; i++) { |
333 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
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334 | struct intel_context *lctx = ring->last_context; |
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335 | |||
5354 | serge | 336 | if (lctx) { |
6084 | serge | 337 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) |
338 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); |
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5060 | serge | 339 | |
6084 | serge | 340 | i915_gem_context_unreference(lctx); |
5354 | serge | 341 | ring->last_context = NULL; |
342 | } |
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5060 | serge | 343 | } |
344 | } |
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345 | |||
4560 | Serge | 346 | int i915_gem_context_init(struct drm_device *dev) |
3031 | serge | 347 | { |
348 | struct drm_i915_private *dev_priv = dev->dev_private; |
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5060 | serge | 349 | struct intel_context *ctx; |
350 | int i; |
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3031 | serge | 351 | |
5060 | serge | 352 | /* Init should only be called once per module load. Eventually the |
353 | * restriction on the context_disabled check can be loosened. */ |
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354 | if (WARN_ON(dev_priv->ring[RCS].default_context)) |
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4560 | Serge | 355 | return 0; |
3031 | serge | 356 | |
6084 | serge | 357 | if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) { |
358 | if (!i915.enable_execlists) { |
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359 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); |
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360 | return -EINVAL; |
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361 | } |
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362 | } |
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363 | |||
5354 | serge | 364 | if (i915.enable_execlists) { |
365 | /* NB: intentionally left blank. We will allocate our own |
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366 | * backing objects as we need them, thank you very much */ |
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367 | dev_priv->hw_context_size = 0; |
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368 | } else if (HAS_HW_CONTEXTS(dev)) { |
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6084 | serge | 369 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
370 | if (dev_priv->hw_context_size > (1<<20)) { |
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5060 | serge | 371 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", |
372 | dev_priv->hw_context_size); |
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373 | dev_priv->hw_context_size = 0; |
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374 | } |
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3031 | serge | 375 | } |
376 | |||
5354 | serge | 377 | ctx = i915_gem_create_context(dev, NULL); |
5060 | serge | 378 | if (IS_ERR(ctx)) { |
379 | DRM_ERROR("Failed to create default global context (error %ld)\n", |
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380 | PTR_ERR(ctx)); |
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381 | return PTR_ERR(ctx); |
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3031 | serge | 382 | } |
383 | |||
5354 | serge | 384 | for (i = 0; i < I915_NUM_RINGS; i++) { |
385 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
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386 | |||
6084 | serge | 387 | /* NB: RCS will hold a ref for all rings */ |
5354 | serge | 388 | ring->default_context = ctx; |
389 | } |
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5060 | serge | 390 | |
5354 | serge | 391 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
392 | i915.enable_execlists ? "LR" : |
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393 | dev_priv->hw_context_size ? "HW" : "fake"); |
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4560 | Serge | 394 | return 0; |
3031 | serge | 395 | } |
396 | |||
397 | void i915_gem_context_fini(struct drm_device *dev) |
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398 | { |
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399 | struct drm_i915_private *dev_priv = dev->dev_private; |
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5060 | serge | 400 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
401 | int i; |
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3031 | serge | 402 | |
5060 | serge | 403 | if (dctx->legacy_hw_ctx.rcs_state) { |
6084 | serge | 404 | /* The only known way to stop the gpu from accessing the hw context is |
405 | * to reset it. Do this as the very last operation to avoid confusing |
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406 | * other code, leading to spurious errors. */ |
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407 | intel_gpu_reset(dev); |
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3031 | serge | 408 | |
6084 | serge | 409 | /* When default context is created and switched to, base object refcount |
410 | * will be 2 (+1 from object creation and +1 from do_switch()). |
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411 | * i915_gem_context_fini() will be called after gpu_idle() has switched |
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412 | * to default context. So we need to unreference the base object once |
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413 | * to offset the do_switch part, so that i915_gem_context_unreference() |
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414 | * can then free the base object correctly. */ |
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415 | WARN_ON(!dev_priv->ring[RCS].last_context); |
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416 | if (dev_priv->ring[RCS].last_context == dctx) { |
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417 | /* Fake switch to NULL context */ |
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5060 | serge | 418 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
419 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
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6084 | serge | 420 | i915_gem_context_unreference(dctx); |
5060 | serge | 421 | dev_priv->ring[RCS].last_context = NULL; |
6084 | serge | 422 | } |
4560 | Serge | 423 | |
5060 | serge | 424 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
425 | } |
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426 | |||
427 | for (i = 0; i < I915_NUM_RINGS; i++) { |
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428 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
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429 | |||
430 | if (ring->last_context) |
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431 | i915_gem_context_unreference(ring->last_context); |
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432 | |||
433 | ring->default_context = NULL; |
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434 | ring->last_context = NULL; |
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435 | } |
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436 | |||
4560 | Serge | 437 | i915_gem_context_unreference(dctx); |
3031 | serge | 438 | } |
439 | |||
6084 | serge | 440 | int i915_gem_context_enable(struct drm_i915_gem_request *req) |
5060 | serge | 441 | { |
6084 | serge | 442 | struct intel_engine_cs *ring = req->ring; |
443 | int ret; |
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5060 | serge | 444 | |
6084 | serge | 445 | if (i915.enable_execlists) { |
446 | if (ring->init_context == NULL) |
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447 | return 0; |
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5060 | serge | 448 | |
6084 | serge | 449 | ret = ring->init_context(req); |
450 | } else |
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451 | ret = i915_switch_context(req); |
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5060 | serge | 452 | |
6084 | serge | 453 | if (ret) { |
454 | DRM_ERROR("ring init context: %d\n", ret); |
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455 | return ret; |
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5060 | serge | 456 | } |
457 | |||
458 | return 0; |
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459 | } |
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460 | |||
3031 | serge | 461 | static int context_idr_cleanup(int id, void *p, void *data) |
462 | { |
||
5060 | serge | 463 | struct intel_context *ctx = p; |
3031 | serge | 464 | |
4280 | Serge | 465 | i915_gem_context_unreference(ctx); |
466 | return 0; |
||
467 | } |
||
3031 | serge | 468 | |
5060 | serge | 469 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
4280 | Serge | 470 | { |
471 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
5060 | serge | 472 | struct intel_context *ctx; |
4104 | Serge | 473 | |
5060 | serge | 474 | idr_init(&file_priv->context_idr); |
4280 | Serge | 475 | |
5060 | serge | 476 | mutex_lock(&dev->struct_mutex); |
5354 | serge | 477 | ctx = i915_gem_create_context(dev, file_priv); |
5060 | serge | 478 | mutex_unlock(&dev->struct_mutex); |
4560 | Serge | 479 | |
5060 | serge | 480 | if (IS_ERR(ctx)) { |
481 | idr_destroy(&file_priv->context_idr); |
||
482 | return PTR_ERR(ctx); |
||
483 | } |
||
4280 | Serge | 484 | |
5060 | serge | 485 | return 0; |
3031 | serge | 486 | } |
487 | |||
488 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
||
489 | { |
||
490 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
491 | |||
4246 | Serge | 492 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
3031 | serge | 493 | idr_destroy(&file_priv->context_idr); |
494 | } |
||
495 | |||
5060 | serge | 496 | struct intel_context * |
3031 | serge | 497 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
498 | { |
||
5060 | serge | 499 | struct intel_context *ctx; |
500 | |||
501 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
||
502 | if (!ctx) |
||
503 | return ERR_PTR(-ENOENT); |
||
504 | |||
505 | return ctx; |
||
3031 | serge | 506 | } |
507 | |||
508 | static inline int |
||
6084 | serge | 509 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
3031 | serge | 510 | { |
6084 | serge | 511 | struct intel_engine_cs *ring = req->ring; |
5354 | serge | 512 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
513 | const int num_rings = |
||
514 | /* Use an extended w/a on ivb+ if signalling from other rings */ |
||
515 | i915_semaphore_is_enabled(ring->dev) ? |
||
516 | hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : |
||
517 | 0; |
||
518 | int len, i, ret; |
||
3031 | serge | 519 | |
520 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
||
521 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value |
||
522 | * explicitly, so we rely on the value at ring init, stored in |
||
523 | * itlb_before_ctx_switch. |
||
524 | */ |
||
5060 | serge | 525 | if (IS_GEN6(ring->dev)) { |
6084 | serge | 526 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); |
3031 | serge | 527 | if (ret) |
528 | return ret; |
||
529 | } |
||
530 | |||
5354 | serge | 531 | /* These flags are for resource streamer on HSW+ */ |
6084 | serge | 532 | if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) |
533 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
||
534 | else if (INTEL_INFO(ring->dev)->gen < 8) |
||
5354 | serge | 535 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
536 | |||
537 | |||
538 | len = 4; |
||
539 | if (INTEL_INFO(ring->dev)->gen >= 7) |
||
540 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); |
||
541 | |||
6084 | serge | 542 | ret = intel_ring_begin(req, len); |
3031 | serge | 543 | if (ret) |
544 | return ret; |
||
545 | |||
5060 | serge | 546 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
5354 | serge | 547 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
3031 | serge | 548 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
5354 | serge | 549 | if (num_rings) { |
550 | struct intel_engine_cs *signaller; |
||
3031 | serge | 551 | |
5354 | serge | 552 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
553 | for_each_ring(signaller, to_i915(ring->dev), i) { |
||
554 | if (signaller == ring) |
||
555 | continue; |
||
556 | |||
557 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
||
558 | intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
||
559 | } |
||
560 | } |
||
561 | } |
||
562 | |||
3031 | serge | 563 | intel_ring_emit(ring, MI_NOOP); |
564 | intel_ring_emit(ring, MI_SET_CONTEXT); |
||
6084 | serge | 565 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | |
5354 | serge | 566 | flags); |
5060 | serge | 567 | /* |
568 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP |
||
569 | * WaMiSetContext_Hang:snb,ivb,vlv |
||
570 | */ |
||
3031 | serge | 571 | intel_ring_emit(ring, MI_NOOP); |
572 | |||
5354 | serge | 573 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
574 | if (num_rings) { |
||
575 | struct intel_engine_cs *signaller; |
||
576 | |||
577 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
||
578 | for_each_ring(signaller, to_i915(ring->dev), i) { |
||
579 | if (signaller == ring) |
||
580 | continue; |
||
581 | |||
582 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
||
583 | intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
||
584 | } |
||
585 | } |
||
3031 | serge | 586 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
5354 | serge | 587 | } |
3031 | serge | 588 | |
589 | intel_ring_advance(ring); |
||
590 | |||
591 | return ret; |
||
592 | } |
||
593 | |||
6084 | serge | 594 | static inline bool should_skip_switch(struct intel_engine_cs *ring, |
595 | struct intel_context *from, |
||
596 | struct intel_context *to) |
||
3031 | serge | 597 | { |
6084 | serge | 598 | if (to->remap_slice) |
599 | return false; |
||
600 | |||
601 | if (to->ppgtt && from == to && |
||
602 | !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) |
||
603 | return true; |
||
604 | |||
605 | return false; |
||
606 | } |
||
607 | |||
608 | static bool |
||
609 | needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to) |
||
610 | { |
||
5060 | serge | 611 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
6084 | serge | 612 | |
613 | if (!to->ppgtt) |
||
614 | return false; |
||
615 | |||
616 | if (INTEL_INFO(ring->dev)->gen < 8) |
||
617 | return true; |
||
618 | |||
619 | if (ring != &dev_priv->ring[RCS]) |
||
620 | return true; |
||
621 | |||
622 | return false; |
||
623 | } |
||
624 | |||
625 | static bool |
||
626 | needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, |
||
627 | u32 hw_flags) |
||
628 | { |
||
629 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
||
630 | |||
631 | if (!to->ppgtt) |
||
632 | return false; |
||
633 | |||
634 | if (!IS_GEN8(ring->dev)) |
||
635 | return false; |
||
636 | |||
637 | if (ring != &dev_priv->ring[RCS]) |
||
638 | return false; |
||
639 | |||
640 | if (hw_flags & MI_RESTORE_INHIBIT) |
||
641 | return true; |
||
642 | |||
643 | return false; |
||
644 | } |
||
645 | |||
646 | static int do_switch(struct drm_i915_gem_request *req) |
||
647 | { |
||
648 | struct intel_context *to = req->ctx; |
||
649 | struct intel_engine_cs *ring = req->ring; |
||
650 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
||
5060 | serge | 651 | struct intel_context *from = ring->last_context; |
3031 | serge | 652 | u32 hw_flags = 0; |
5060 | serge | 653 | bool uninitialized = false; |
4560 | Serge | 654 | int ret, i; |
3031 | serge | 655 | |
5060 | serge | 656 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
657 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
||
658 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); |
||
659 | } |
||
3031 | serge | 660 | |
6084 | serge | 661 | if (should_skip_switch(ring, from, to)) |
3031 | serge | 662 | return 0; |
663 | |||
5060 | serge | 664 | /* Trying to pin first makes error handling easier. */ |
665 | if (ring == &dev_priv->ring[RCS]) { |
||
666 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
||
667 | get_context_alignment(ring->dev), 0); |
||
6084 | serge | 668 | if (ret) |
669 | return ret; |
||
5060 | serge | 670 | } |
3031 | serge | 671 | |
4539 | Serge | 672 | /* |
673 | * Pin can switch back to the default context if we end up calling into |
||
674 | * evict_everything - as a last ditch gtt defrag effort that also |
||
675 | * switches to the default context. Hence we need to reload from here. |
||
676 | */ |
||
677 | from = ring->last_context; |
||
678 | |||
6084 | serge | 679 | if (needs_pd_load_pre(ring, to)) { |
680 | /* Older GENs and non render rings still want the load first, |
||
681 | * "PP_DCLV followed by PP_DIR_BASE register through Load |
||
682 | * Register Immediate commands in Ring Buffer before submitting |
||
683 | * a context."*/ |
||
5354 | serge | 684 | trace_switch_mm(ring, to); |
6084 | serge | 685 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
5060 | serge | 686 | if (ret) |
687 | goto unpin_out; |
||
6084 | serge | 688 | |
689 | /* Doing a PD load always reloads the page dirs */ |
||
690 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
||
5060 | serge | 691 | } |
692 | |||
693 | if (ring != &dev_priv->ring[RCS]) { |
||
694 | if (from) |
||
695 | i915_gem_context_unreference(from); |
||
696 | goto done; |
||
697 | } |
||
698 | |||
4539 | Serge | 699 | /* |
700 | * Clear this page out of any CPU caches for coherent swap-in/out. Note |
||
3031 | serge | 701 | * that thanks to write = false in this call and us not setting any gpu |
702 | * write domains when putting a context object onto the active list |
||
703 | * (when switching away from it), this won't block. |
||
4539 | Serge | 704 | * |
705 | * XXX: We need a real interface to do this instead of trickery. |
||
706 | */ |
||
5060 | serge | 707 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
708 | if (ret) |
||
709 | goto unpin_out; |
||
710 | |||
6084 | serge | 711 | if (!to->legacy_hw_ctx.initialized) { |
3031 | serge | 712 | hw_flags |= MI_RESTORE_INHIBIT; |
6084 | serge | 713 | /* NB: If we inhibit the restore, the context is not allowed to |
714 | * die because future work may end up depending on valid address |
||
715 | * space. This means we must enforce that a page table load |
||
716 | * occur when this occurs. */ |
||
717 | } else if (to->ppgtt && |
||
718 | (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { |
||
719 | hw_flags |= MI_FORCE_RESTORE; |
||
720 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
||
721 | } |
||
3031 | serge | 722 | |
6084 | serge | 723 | /* We should never emit switch_mm more than once */ |
724 | WARN_ON(needs_pd_load_pre(ring, to) && |
||
725 | needs_pd_load_post(ring, to, hw_flags)); |
||
726 | |||
727 | ret = mi_set_context(req, hw_flags); |
||
5060 | serge | 728 | if (ret) |
729 | goto unpin_out; |
||
3031 | serge | 730 | |
6084 | serge | 731 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
732 | * setup, and we do not wish to move them. |
||
733 | */ |
||
734 | if (needs_pd_load_post(ring, to, hw_flags)) { |
||
735 | trace_switch_mm(ring, to); |
||
736 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
||
737 | /* The hardware context switch is emitted, but we haven't |
||
738 | * actually changed the state - so it's probably safe to bail |
||
739 | * here. Still, let the user know something dangerous has |
||
740 | * happened. |
||
741 | */ |
||
742 | if (ret) { |
||
743 | DRM_ERROR("Failed to change address space on context switch\n"); |
||
744 | goto unpin_out; |
||
745 | } |
||
746 | } |
||
747 | |||
4560 | Serge | 748 | for (i = 0; i < MAX_L3_SLICES; i++) { |
749 | if (!(to->remap_slice & (1< |
||
750 | continue; |
||
751 | |||
6084 | serge | 752 | ret = i915_gem_l3_remap(req, i); |
4560 | Serge | 753 | /* If it failed, try again next round */ |
754 | if (ret) |
||
755 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); |
||
756 | else |
||
757 | to->remap_slice &= ~(1< |
||
758 | } |
||
759 | |||
3031 | serge | 760 | /* The backing object for the context is done after switching to the |
761 | * *next* context. Therefore we cannot retire the previous context until |
||
762 | * the next context has already started running. In fact, the below code |
||
763 | * is a bit suboptimal because the retiring can occur simply after the |
||
764 | * MI_SET_CONTEXT instead of when the next seqno has completed. |
||
765 | */ |
||
4104 | Serge | 766 | if (from != NULL) { |
5060 | serge | 767 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
6084 | serge | 768 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
3031 | serge | 769 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
770 | * whole damn pipeline, we don't need to explicitly mark the |
||
771 | * object dirty. The only exception is that the context must be |
||
772 | * correct in case the object gets swapped out. Ideally we'd be |
||
773 | * able to defer doing this until we know the object would be |
||
774 | * swapped, but there is no way to do that yet. |
||
775 | */ |
||
5060 | serge | 776 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
3031 | serge | 777 | |
4560 | Serge | 778 | /* obj is kept alive until the next request by its active ref */ |
5060 | serge | 779 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
4104 | Serge | 780 | i915_gem_context_unreference(from); |
3031 | serge | 781 | } |
782 | |||
6084 | serge | 783 | uninitialized = !to->legacy_hw_ctx.initialized; |
5060 | serge | 784 | to->legacy_hw_ctx.initialized = true; |
785 | |||
786 | done: |
||
4104 | Serge | 787 | i915_gem_context_reference(to); |
788 | ring->last_context = to; |
||
3031 | serge | 789 | |
5060 | serge | 790 | if (uninitialized) { |
5354 | serge | 791 | if (ring->init_context) { |
6084 | serge | 792 | ret = ring->init_context(req); |
5354 | serge | 793 | if (ret) |
794 | DRM_ERROR("ring init context: %d\n", ret); |
||
795 | } |
||
5060 | serge | 796 | } |
797 | |||
3031 | serge | 798 | return 0; |
5060 | serge | 799 | |
800 | unpin_out: |
||
801 | if (ring->id == RCS) |
||
802 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
||
803 | return ret; |
||
3031 | serge | 804 | } |
805 | |||
806 | /** |
||
807 | * i915_switch_context() - perform a GPU context switch. |
||
6084 | serge | 808 | * @req: request for which we'll execute the context switch |
3031 | serge | 809 | * |
810 | * The context life cycle is simple. The context refcount is incremented and |
||
811 | * decremented by 1 and create and destroy. If the context is in use by the GPU, |
||
5354 | serge | 812 | * it will have a refcount > 1. This allows us to destroy the context abstract |
3031 | serge | 813 | * object while letting the normal object tracking destroy the backing BO. |
5354 | serge | 814 | * |
815 | * This function should not be used in execlists mode. Instead the context is |
||
816 | * switched by writing to the ELSP and requests keep a reference to their |
||
817 | * context. |
||
3031 | serge | 818 | */ |
6084 | serge | 819 | int i915_switch_context(struct drm_i915_gem_request *req) |
3031 | serge | 820 | { |
6084 | serge | 821 | struct intel_engine_cs *ring = req->ring; |
3031 | serge | 822 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
823 | |||
5354 | serge | 824 | WARN_ON(i915.enable_execlists); |
4104 | Serge | 825 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
826 | |||
6084 | serge | 827 | if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
828 | if (req->ctx != ring->last_context) { |
||
829 | i915_gem_context_reference(req->ctx); |
||
5060 | serge | 830 | if (ring->last_context) |
831 | i915_gem_context_unreference(ring->last_context); |
||
6084 | serge | 832 | ring->last_context = req->ctx; |
5060 | serge | 833 | } |
3031 | serge | 834 | return 0; |
835 | } |
||
836 | |||
6084 | serge | 837 | return do_switch(req); |
3031 | serge | 838 | } |
839 | |||
5354 | serge | 840 | static bool contexts_enabled(struct drm_device *dev) |
5060 | serge | 841 | { |
5354 | serge | 842 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
5060 | serge | 843 | } |
844 | |||
3031 | serge | 845 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
846 | struct drm_file *file) |
||
847 | { |
||
848 | struct drm_i915_gem_context_create *args = data; |
||
849 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
5060 | serge | 850 | struct intel_context *ctx; |
3031 | serge | 851 | int ret; |
852 | |||
5354 | serge | 853 | if (!contexts_enabled(dev)) |
3031 | serge | 854 | return -ENODEV; |
855 | |||
856 | ret = i915_mutex_lock_interruptible(dev); |
||
857 | if (ret) |
||
858 | return ret; |
||
859 | |||
5354 | serge | 860 | ctx = i915_gem_create_context(dev, file_priv); |
3031 | serge | 861 | mutex_unlock(&dev->struct_mutex); |
862 | if (IS_ERR(ctx)) |
||
863 | return PTR_ERR(ctx); |
||
864 | |||
5060 | serge | 865 | args->ctx_id = ctx->user_handle; |
3031 | serge | 866 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
867 | |||
868 | return 0; |
||
869 | } |
||
870 | |||
871 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
||
872 | struct drm_file *file) |
||
873 | { |
||
874 | struct drm_i915_gem_context_destroy *args = data; |
||
875 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
5060 | serge | 876 | struct intel_context *ctx; |
3031 | serge | 877 | int ret; |
878 | |||
5060 | serge | 879 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
880 | return -ENOENT; |
||
3031 | serge | 881 | |
882 | ret = i915_mutex_lock_interruptible(dev); |
||
883 | if (ret) |
||
884 | return ret; |
||
885 | |||
886 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
||
5060 | serge | 887 | if (IS_ERR(ctx)) { |
3031 | serge | 888 | mutex_unlock(&dev->struct_mutex); |
5060 | serge | 889 | return PTR_ERR(ctx); |
3031 | serge | 890 | } |
891 | |||
5060 | serge | 892 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
4246 | Serge | 893 | i915_gem_context_unreference(ctx); |
3031 | serge | 894 | mutex_unlock(&dev->struct_mutex); |
895 | |||
896 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); |
||
897 | return 0; |
||
898 | } |
||
6084 | serge | 899 | |
900 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
||
901 | struct drm_file *file) |
||
902 | { |
||
903 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
904 | struct drm_i915_gem_context_param *args = data; |
||
905 | struct intel_context *ctx; |
||
906 | int ret; |
||
907 | |||
908 | ret = i915_mutex_lock_interruptible(dev); |
||
909 | if (ret) |
||
910 | return ret; |
||
911 | |||
912 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
||
913 | if (IS_ERR(ctx)) { |
||
914 | mutex_unlock(&dev->struct_mutex); |
||
915 | return PTR_ERR(ctx); |
||
916 | } |
||
917 | |||
918 | args->size = 0; |
||
919 | switch (args->param) { |
||
920 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
||
921 | args->value = ctx->hang_stats.ban_period_seconds; |
||
922 | break; |
||
923 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
||
924 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; |
||
925 | break; |
||
926 | default: |
||
927 | ret = -EINVAL; |
||
928 | break; |
||
929 | } |
||
930 | mutex_unlock(&dev->struct_mutex); |
||
931 | |||
932 | return ret; |
||
933 | } |
||
934 | |||
935 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
||
936 | struct drm_file *file) |
||
937 | { |
||
938 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
939 | struct drm_i915_gem_context_param *args = data; |
||
940 | struct intel_context *ctx; |
||
941 | int ret; |
||
942 | |||
943 | ret = i915_mutex_lock_interruptible(dev); |
||
944 | if (ret) |
||
945 | return ret; |
||
946 | |||
947 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
||
948 | if (IS_ERR(ctx)) { |
||
949 | mutex_unlock(&dev->struct_mutex); |
||
950 | return PTR_ERR(ctx); |
||
951 | } |
||
952 | |||
953 | switch (args->param) { |
||
954 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
||
955 | if (args->size) |
||
956 | ret = -EINVAL; |
||
957 | else if (args->value < ctx->hang_stats.ban_period_seconds) |
||
958 | ret = -EPERM; |
||
959 | else |
||
960 | ctx->hang_stats.ban_period_seconds = args->value; |
||
961 | break; |
||
962 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
||
963 | if (args->size) { |
||
964 | ret = -EINVAL; |
||
965 | } else { |
||
966 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; |
||
967 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; |
||
968 | } |
||
969 | break; |
||
970 | default: |
||
971 | ret = -EINVAL; |
||
972 | break; |
||
973 | } |
||
974 | mutex_unlock(&dev->struct_mutex); |
||
975 | |||
976 | return ret; |
||
977 | }> |