WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_drv.h

Rev	Author	Line No.	Line
2325	Serge	1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --
		2	*/
		3	/*
		4	*
		5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
		6	* All Rights Reserved.
		7	*
		8	* Permission is hereby granted, free of charge, to any person obtaining a
		9	* copy of this software and associated documentation files (the
		10	* "Software"), to deal in the Software without restriction, including
		11	* without limitation the rights to use, copy, modify, merge, publish,
		12	* distribute, sub license, and/or sell copies of the Software, and to
		13	* permit persons to whom the Software is furnished to do so, subject to
		14	* the following conditions:
		15	*
		16	* The above copyright notice and this permission notice (including the
		17	* next paragraph) shall be included in all copies or substantial portions
		18	* of the Software.
		19	*
		20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
		21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
		23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
		24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
		25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
		26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		27	*
		28	*/
		29
		30	#ifndef _I915_DRV_H_
		31	#define _I915_DRV_H_
		32
3480	Serge	33	#include
6084	serge	34	#include
3480	Serge	35
6937	serge	36	#include
7144	serge	37	#include "i915_params.h"
2325	Serge	38	#include "i915_reg.h"
2327	Serge	39	#include "intel_bios.h"
2326	Serge	40	#include "intel_ringbuffer.h"
5354	serge	41	#include "intel_lrc.h"
5060	serge	42	#include "i915_gem_gtt.h"
5354	serge	43	#include "i915_gem_render_state.h"
7144	serge	44	#include
2330	Serge	45	#include
3031	serge	46	#include
2332	Serge	47	#include
5354	serge	48	#include /* for struct drm_dma_handle */
		49	#include
6937	serge	50	#include
5060	serge	51	#include
7144	serge	52	#include
6084	serge	53	#include
		54	#include "intel_guc.h"
2325	Serge	55
		56	/* General customization:
		57	*/
		58
		59	#define DRIVER_NAME "i915"
		60	#define DRIVER_DESC "Intel Graphics"
7144	serge	61	#define DRIVER_DATE "20160229"
2325	Serge	62
5354	serge	63	#undef WARN_ON
6084	serge	64	/* Many gcc seem to no see through this and fall over :( */
		65	#if 0
		66	#define WARN_ON(x) ({ \
		67	bool __i915_warn_cond = (x); \
		68	if (__builtin_constant_p(__i915_warn_cond)) \
		69	BUILD_BUG_ON(__i915_warn_cond); \
		70	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
		71	#else
7144	serge	72	#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
6084	serge	73	#endif
5354	serge	74
6084	serge	75	#undef WARN_ON_ONCE
7144	serge	76	#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
6084	serge	77
		78	#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
		79	(long) (x), __func__);
		80
		81	/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
		82	* WARN_ON()) for hw state sanity checks to check for unexpected conditions
		83	* which may not necessarily be a user visible problem. This will either
		84	* WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
		85	* enable distros and users to tailor their preferred amount of i915 abrt
		86	* spam.
		87	*/
		88	#define I915_STATE_WARN(condition, format...) ({ \
		89	int __ret_warn_on = !!(condition); \
7144	serge	90	if (unlikely(__ret_warn_on)) \
		91	if (!WARN(i915.verbose_state_checks, format)) \
6084	serge	92	DRM_ERROR(format); \
		93	unlikely(__ret_warn_on); \
		94	})
		95
7144	serge	96	#define I915_STATE_WARN_ON(x) \
		97	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
6084	serge	98
		99	static inline const char *yesno(bool v)
		100	{
		101	return v ? "yes" : "no";
		102	}
		103
7144	serge	104	static inline const char *onoff(bool v)
		105	{
		106	return v ? "on" : "off";
		107	}
		108
2325	Serge	109	enum pipe {
4560	Serge	110	INVALID_PIPE = -1,
2325	Serge	111	PIPE_A = 0,
		112	PIPE_B,
		113	PIPE_C,
5060	serge	114	_PIPE_EDP,
		115	I915_MAX_PIPES = _PIPE_EDP
2325	Serge	116	};
		117	#define pipe_name(p) ((p) + 'A')
		118
3243	Serge	119	enum transcoder {
		120	TRANSCODER_A = 0,
		121	TRANSCODER_B,
		122	TRANSCODER_C,
5060	serge	123	TRANSCODER_EDP,
		124	I915_MAX_TRANSCODERS
3243	Serge	125	};
		126	#define transcoder_name(t) ((t) + 'A')
		127
5354	serge	128	/*
6084	serge	129	* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
		130	* number of planes per CRTC. Not all platforms really have this many planes,
		131	* which means some arrays of size I915_MAX_PLANES may have unused entries
		132	* between the topmost sprite plane and the cursor plane.
5354	serge	133	*/
2325	Serge	134	enum plane {
		135	PLANE_A = 0,
		136	PLANE_B,
		137	PLANE_C,
6084	serge	138	PLANE_CURSOR,
		139	I915_MAX_PLANES,
2325	Serge	140	};
		141	#define plane_name(p) ((p) + 'A')
		142
5060	serge	143	#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
4104	Serge	144
3031	serge	145	enum port {
		146	PORT_A = 0,
		147	PORT_B,
		148	PORT_C,
		149	PORT_D,
		150	PORT_E,
		151	I915_MAX_PORTS
		152	};
		153	#define port_name(p) ((p) + 'A')
		154
5060	serge	155	#define I915_NUM_PHYS_VLV 2
4560	Serge	156
		157	enum dpio_channel {
		158	DPIO_CH0,
		159	DPIO_CH1
		160	};
		161
		162	enum dpio_phy {
		163	DPIO_PHY0,
		164	DPIO_PHY1
		165	};
		166
4104	Serge	167	enum intel_display_power_domain {
		168	POWER_DOMAIN_PIPE_A,
		169	POWER_DOMAIN_PIPE_B,
		170	POWER_DOMAIN_PIPE_C,
		171	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
		172	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
		173	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
		174	POWER_DOMAIN_TRANSCODER_A,
		175	POWER_DOMAIN_TRANSCODER_B,
		176	POWER_DOMAIN_TRANSCODER_C,
4560	Serge	177	POWER_DOMAIN_TRANSCODER_EDP,
6937	serge	178	POWER_DOMAIN_PORT_DDI_A_LANES,
		179	POWER_DOMAIN_PORT_DDI_B_LANES,
		180	POWER_DOMAIN_PORT_DDI_C_LANES,
		181	POWER_DOMAIN_PORT_DDI_D_LANES,
		182	POWER_DOMAIN_PORT_DDI_E_LANES,
5060	serge	183	POWER_DOMAIN_PORT_DSI,
		184	POWER_DOMAIN_PORT_CRT,
		185	POWER_DOMAIN_PORT_OTHER,
4560	Serge	186	POWER_DOMAIN_VGA,
		187	POWER_DOMAIN_AUDIO,
5060	serge	188	POWER_DOMAIN_PLLS,
6084	serge	189	POWER_DOMAIN_AUX_A,
		190	POWER_DOMAIN_AUX_B,
		191	POWER_DOMAIN_AUX_C,
		192	POWER_DOMAIN_AUX_D,
		193	POWER_DOMAIN_GMBUS,
6937	serge	194	POWER_DOMAIN_MODESET,
4560	Serge	195	POWER_DOMAIN_INIT,
		196
		197	POWER_DOMAIN_NUM,
4104	Serge	198	};
		199
		200	#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
		201	#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		202	((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
4560	Serge	203	#define POWER_DOMAIN_TRANSCODER(tran) \
		204	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
		205	(tran) + POWER_DOMAIN_TRANSCODER_A)
4104	Serge	206
3746	Serge	207	enum hpd_pin {
		208	HPD_NONE = 0,
		209	HPD_TV = HPD_NONE, /* TV is known to be unreliable */
		210	HPD_CRT,
		211	HPD_SDVO_B,
		212	HPD_SDVO_C,
6084	serge	213	HPD_PORT_A,
3746	Serge	214	HPD_PORT_B,
		215	HPD_PORT_C,
		216	HPD_PORT_D,
6084	serge	217	HPD_PORT_E,
3746	Serge	218	HPD_NUM_PINS
		219	};
		220
6084	serge	221	#define for_each_hpd_pin(__pin) \
		222	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
		223
		224	struct i915_hotplug {
		225	struct work_struct hotplug_work;
		226
		227	struct {
		228	unsigned long last_jiffies;
		229	int count;
		230	enum {
		231	HPD_ENABLED = 0,
		232	HPD_DISABLED = 1,
		233	HPD_MARK_DISABLED = 2
		234	} state;
		235	} stats[HPD_NUM_PINS];
		236	u32 event_bits;
		237	struct delayed_work reenable_work;
		238
		239	struct intel_digital_port *irq_port[I915_MAX_PORTS];
		240	u32 long_port_mask;
		241	u32 short_port_mask;
		242	struct work_struct dig_port_work;
		243
		244	/*
		245	* if we get a HPD irq from DP and a HPD irq from non-DP
		246	* the non-DP HPD could block the workqueue on a mode config
		247	* mutex getting, that userspace may have taken. However
		248	* userspace is waiting on the DP workqueue to run which is
		249	* blocked behind the non-DP one.
		250	*/
		251	struct workqueue_struct *dp_wq;
		252	};
		253
3480	Serge	254	#define I915_GEM_GPU_DOMAINS \
		255	(I915_GEM_DOMAIN_RENDER \| \
		256	I915_GEM_DOMAIN_SAMPLER \| \
		257	I915_GEM_DOMAIN_COMMAND \| \
		258	I915_GEM_DOMAIN_INSTRUCTION \| \
		259	I915_GEM_DOMAIN_VERTEX)
2325	Serge	260
5354	serge	261	#define for_each_pipe(__dev_priv, __p) \
		262	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
7144	serge	263	#define for_each_pipe_masked(__dev_priv, __p, __mask) \
		264	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		265	for_each_if ((__mask) & (1 << (__p)))
6084	serge	266	#define for_each_plane(__dev_priv, __pipe, __p) \
		267	for ((__p) = 0; \
		268	(__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
		269	(__p)++)
		270	#define for_each_sprite(__dev_priv, __p, __s) \
		271	for ((__s) = 0; \
		272	(__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
		273	(__s)++)
2325	Serge	274
5060	serge	275	#define for_each_crtc(dev, crtc) \
		276	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
		277
6084	serge	278	#define for_each_intel_plane(dev, intel_plane) \
		279	list_for_each_entry(intel_plane, \
		280	&dev->mode_config.plane_list, \
		281	base.head)
		282
		283	#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
		284	list_for_each_entry(intel_plane, \
		285	&(dev)->mode_config.plane_list, \
		286	base.head) \
6937	serge	287	for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
6084	serge	288
5060	serge	289	#define for_each_intel_crtc(dev, intel_crtc) \
		290	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
		291
5354	serge	292	#define for_each_intel_encoder(dev, intel_encoder) \
		293	list_for_each_entry(intel_encoder, \
		294	&(dev)->mode_config.encoder_list, \
		295	base.head)
		296
6084	serge	297	#define for_each_intel_connector(dev, intel_connector) \
		298	list_for_each_entry(intel_connector, \
		299	&dev->mode_config.connector_list, \
		300	base.head)
		301
3031	serge	302	#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
		303	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
6937	serge	304	for_each_if ((intel_encoder)->base.crtc == (__crtc))
3031	serge	305
5060	serge	306	#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
		307	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
6937	serge	308	for_each_if ((intel_connector)->base.encoder == (__encoder))
5060	serge	309
		310	#define for_each_power_domain(domain, mask) \
		311	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6937	serge	312	for_each_if ((1 << (domain)) & (mask))
5060	serge	313
4104	Serge	314	struct drm_i915_private;
5128	serge	315	struct i915_mm_struct;
5060	serge	316	struct i915_mmu_object;
4104	Serge	317
6084	serge	318	struct drm_i915_file_private {
		319	struct drm_i915_private *dev_priv;
		320	struct drm_file *file;
		321
		322	struct {
		323	spinlock_t lock;
		324	struct list_head request_list;
		325	/* 20ms is a fairly arbitrary limit (greater than the average frame time)
		326	* chosen to prevent the CPU getting more than a frame ahead of the GPU
		327	* (when using lax throttling for the frontbuffer). We also use it to
		328	* offer free GPU waitboosts for severely congested workloads.
		329	*/
		330	#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
		331	} mm;
		332	struct idr context_idr;
		333
		334	struct intel_rps_client {
		335	struct list_head link;
		336	unsigned boosts;
		337	} rps;
		338
7144	serge	339	unsigned int bsd_ring;
6084	serge	340	};
		341
4104	Serge	342	enum intel_dpll_id {
		343	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
		344	/* real shared dpll ids must be >= 0 */
5060	serge	345	DPLL_ID_PCH_PLL_A = 0,
		346	DPLL_ID_PCH_PLL_B = 1,
5354	serge	347	/* hsw/bdw */
5060	serge	348	DPLL_ID_WRPLL1 = 0,
		349	DPLL_ID_WRPLL2 = 1,
6084	serge	350	DPLL_ID_SPLL = 2,
		351
5354	serge	352	/* skl */
		353	DPLL_ID_SKL_DPLL1 = 0,
		354	DPLL_ID_SKL_DPLL2 = 1,
		355	DPLL_ID_SKL_DPLL3 = 2,
4104	Serge	356	};
5354	serge	357	#define I915_NUM_PLLS 3
4104	Serge	358
		359	struct intel_dpll_hw_state {
5354	serge	360	/* i9xx, pch plls */
4104	Serge	361	uint32_t dpll;
		362	uint32_t dpll_md;
		363	uint32_t fp0;
		364	uint32_t fp1;
5354	serge	365
		366	/* hsw, bdw */
5060	serge	367	uint32_t wrpll;
6084	serge	368	uint32_t spll;
5354	serge	369
		370	/* skl */
		371	/*
		372	* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
6084	serge	373	* lower part of ctrl1 and they get shifted into position when writing
5354	serge	374	* the register. This allows us to easily compare the state to share
		375	* the DPLL.
		376	*/
		377	uint32_t ctrl1;
		378	/* HDMI only, 0 when used for DP */
		379	uint32_t cfgcr1, cfgcr2;
6084	serge	380
		381	/* bxt */
		382	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
		383	pcsdw12;
4104	Serge	384	};
		385
5354	serge	386	struct intel_shared_dpll_config {
		387	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
		388	struct intel_dpll_hw_state hw_state;
		389	};
		390
4104	Serge	391	struct intel_shared_dpll {
5354	serge	392	struct intel_shared_dpll_config config;
		393
3031	serge	394	int active; /* count of number of active CRTCs (i.e. DPMS on) */
		395	bool on; /* is the PLL actually active? Disabled during modeset */
4104	Serge	396	const char *name;
		397	/* should match the index in the dev_priv->shared_dplls array */
		398	enum intel_dpll_id id;
5060	serge	399	/* The mode_set hook is optional and should be used together with the
		400	* intel_prepare_shared_dpll function. */
4104	Serge	401	void (mode_set)(struct drm_i915_private dev_priv,
		402	struct intel_shared_dpll *pll);
		403	void (enable)(struct drm_i915_private dev_priv,
		404	struct intel_shared_dpll *pll);
		405	void (disable)(struct drm_i915_private dev_priv,
		406	struct intel_shared_dpll *pll);
		407	bool (get_hw_state)(struct drm_i915_private dev_priv,
		408	struct intel_shared_dpll *pll,
		409	struct intel_dpll_hw_state *hw_state);
3031	serge	410	};
		411
5354	serge	412	#define SKL_DPLL0 0
		413	#define SKL_DPLL1 1
		414	#define SKL_DPLL2 2
		415	#define SKL_DPLL3 3
		416
3480	Serge	417	/* Used by dp and fdi links */
		418	struct intel_link_m_n {
		419	uint32_t tu;
		420	uint32_t gmch_m;
		421	uint32_t gmch_n;
		422	uint32_t link_m;
		423	uint32_t link_n;
		424	};
		425
		426	void intel_link_compute_m_n(int bpp, int nlanes,
		427	int pixel_clock, int link_clock,
		428	struct intel_link_m_n *m_n);
		429
2325	Serge	430	/* Interface history:
		431	*
		432	* 1.1: Original.
		433	* 1.2: Add Power Management
		434	* 1.3: Add vblank support
		435	* 1.4: Fix cmdbuffer path, add heap destroy
		436	* 1.5: Add vblank pipe configuration
		437	* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
		438	* - Support vertical blank on secondary display pipe
		439	*/
		440	#define DRIVER_MAJOR 1
		441	#define DRIVER_MINOR 6
		442	#define DRIVER_PATCHLEVEL 0
		443
		444	#define WATCH_LISTS 0
		445
		446	struct opregion_header;
		447	struct opregion_acpi;
		448	struct opregion_swsci;
		449	struct opregion_asle;
		450
		451	struct intel_opregion {
6084	serge	452	struct opregion_header *header;
		453	struct opregion_acpi *acpi;
		454	struct opregion_swsci *swsci;
4560	Serge	455	u32 swsci_gbda_sub_functions;
		456	u32 swsci_sbcb_sub_functions;
6084	serge	457	struct opregion_asle *asle;
6937	serge	458	void *rvda;
		459	const void *vbt;
		460	u32 vbt_size;
6084	serge	461	u32 *lid_state;
4560	Serge	462	struct work_struct asle_work;
2325	Serge	463	};
		464	#define OPREGION_SIZE (8*1024)
		465
		466	struct intel_overlay;
		467	struct intel_overlay_error_state;
		468
		469	#define I915_FENCE_REG_NONE -1
3746	Serge	470	#define I915_MAX_NUM_FENCES 32
		471	/* 32 fences + sign bit for FENCE_REG_NONE */
		472	#define I915_MAX_NUM_FENCE_BITS 6
2325	Serge	473
		474	struct drm_i915_fence_reg {
		475	struct list_head lru_list;
		476	struct drm_i915_gem_object *obj;
3031	serge	477	int pin_count;
2325	Serge	478	};
		479
		480	struct sdvo_device_mapping {
		481	u8 initialized;
		482	u8 dvo_port;
		483	u8 slave_addr;
		484	u8 dvo_wiring;
		485	u8 i2c_pin;
		486	u8 ddc_pin;
		487	};
		488
		489	struct intel_display_error_state;
		490
		491	struct drm_i915_error_state {
3243	Serge	492	struct kref ref;
5060	serge	493	struct timeval time;
		494
		495	char error_msg[128];
6084	serge	496	int iommu;
5060	serge	497	u32 reset_count;
		498	u32 suspend_count;
		499
		500	/* Generic register state */
2325	Serge	501	u32 eir;
		502	u32 pgtbl_er;
3031	serge	503	u32 ier;
5060	serge	504	u32 gtier[4];
3031	serge	505	u32 ccid;
3243	Serge	506	u32 derrmr;
		507	u32 forcewake;
2325	Serge	508	u32 error; /* gen6+ */
3031	serge	509	u32 err_int; /* gen7 */
6084	serge	510	u32 fault_data0; /* gen8, gen9 */
		511	u32 fault_data1; /* gen8, gen9 */
5060	serge	512	u32 done_reg;
		513	u32 gac_eco;
		514	u32 gam_ecochk;
		515	u32 gab_ctl;
		516	u32 gfx_mode;
3031	serge	517	u32 extra_instdone[I915_NUM_INSTDONE_REG];
2342	Serge	518	u64 fence[I915_MAX_NUM_FENCES];
5060	serge	519	struct intel_overlay_error_state *overlay;
		520	struct intel_display_error_state *display;
6084	serge	521	struct drm_i915_error_object *semaphore_obj;
5060	serge	522
3031	serge	523	struct drm_i915_error_ring {
4560	Serge	524	bool valid;
5060	serge	525	/* Software tracked state */
		526	bool waiting;
		527	int hangcheck_score;
		528	enum intel_ring_hangcheck_action hangcheck_action;
		529	int num_requests;
		530
		531	/* our own tracking of ring head and tail */
		532	u32 cpu_ring_head;
		533	u32 cpu_ring_tail;
		534
		535	u32 semaphore_seqno[I915_NUM_RINGS - 1];
		536
		537	/* Register state */
6084	serge	538	u32 start;
5060	serge	539	u32 tail;
		540	u32 head;
		541	u32 ctl;
		542	u32 hws;
		543	u32 ipeir;
		544	u32 ipehr;
		545	u32 instdone;
		546	u32 bbstate;
		547	u32 instpm;
		548	u32 instps;
		549	u32 seqno;
		550	u64 bbaddr;
		551	u64 acthd;
		552	u32 fault_reg;
		553	u64 faddr;
		554	u32 rc_psmi; /* sleep state */
		555	u32 semaphore_mboxes[I915_NUM_RINGS - 1];
		556
6084	serge	557	struct drm_i915_error_object {
		558	int page_count;
		559	u64 gtt_offset;
		560	u32 *pages[0];
5060	serge	561	} ringbuffer, batchbuffer, wa_batchbuffer, ctx, *hws_page;
		562
3031	serge	563	struct drm_i915_error_request {
		564	long jiffies;
		565	u32 seqno;
		566	u32 tail;
		567	} *requests;
5060	serge	568
		569	struct {
		570	u32 gfx_mode;
		571	union {
		572	u64 pdp[4];
		573	u32 pp_dir_base;
		574	};
		575	} vm_info;
		576
		577	pid_t pid;
		578	char comm[TASK_COMM_LEN];
3031	serge	579	} ring[I915_NUM_RINGS];
5354	serge	580
2325	Serge	581	struct drm_i915_error_buffer {
		582	u32 size;
		583	u32 name;
6084	serge	584	u32 rseqno[I915_NUM_RINGS], wseqno;
		585	u64 gtt_offset;
2325	Serge	586	u32 read_domains;
		587	u32 write_domain;
2342	Serge	588	s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
2325	Serge	589	s32 pinned:2;
		590	u32 tiling:2;
		591	u32 dirty:1;
		592	u32 purgeable:1;
5060	serge	593	u32 userptr:1;
3031	serge	594	s32 ring:4;
4560	Serge	595	u32 cache_level:3;
4104	Serge	596	} active_bo, pinned_bo;
5060	serge	597
4104	Serge	598	u32 active_bo_count, pinned_bo_count;
5354	serge	599	u32 vm_count;
2325	Serge	600	};
		601
4560	Serge	602	struct intel_connector;
5354	serge	603	struct intel_encoder;
6084	serge	604	struct intel_crtc_state;
		605	struct intel_initial_plane_config;
3746	Serge	606	struct intel_crtc;
4104	Serge	607	struct intel_limit;
		608	struct dpll;
3746	Serge	609
2325	Serge	610	struct drm_i915_display_funcs {
		611	int (get_display_clock_speed)(struct drm_device dev);
		612	int (get_fifo_size)(struct drm_device dev, int plane);
4104	Serge	613	/**
		614	* find_dpll() - Find the best values for the PLL
		615	* @limit: limits for the PLL
		616	* @crtc: current CRTC
		617	* @target: target frequency in kHz
		618	* @refclk: reference clock frequency in kHz
		619	* @match_clock: if provided, @best_clock P divider must
		620	* match the P divider from @match_clock
		621	* used for LVDS downclocking
		622	* @best_clock: best PLL values found
		623	*
		624	* Returns true on success, false on failure.
		625	*/
		626	bool (find_dpll)(const struct intel_limit limit,
6084	serge	627	struct intel_crtc_state *crtc_state,
4104	Serge	628	int target, int refclk,
		629	struct dpll *match_clock,
		630	struct dpll *best_clock);
6937	serge	631	int (compute_pipe_wm)(struct intel_crtc crtc,
		632	struct drm_atomic_state *state);
7144	serge	633	void (program_watermarks)(struct intel_crtc_state cstate);
4560	Serge	634	void (update_wm)(struct drm_crtc crtc);
6084	serge	635	int (modeset_calc_cdclk)(struct drm_atomic_state state);
		636	void (modeset_commit_cdclk)(struct drm_atomic_state state);
3746	Serge	637	/* Returns the active state of the crtc, and if the crtc is active,
		638	* fills out the pipe-config with the hw state. */
		639	bool (get_pipe_config)(struct intel_crtc ,
6084	serge	640	struct intel_crtc_state *);
		641	void (get_initial_plane_config)(struct intel_crtc ,
		642	struct intel_initial_plane_config *);
		643	int (crtc_compute_clock)(struct intel_crtc crtc,
		644	struct intel_crtc_state *crtc_state);
3031	serge	645	void (crtc_enable)(struct drm_crtc crtc);
		646	void (crtc_disable)(struct drm_crtc crtc);
5354	serge	647	void (audio_codec_enable)(struct drm_connector connector,
		648	struct intel_encoder *encoder,
6084	serge	649	const struct drm_display_mode *adjusted_mode);
5354	serge	650	void (audio_codec_disable)(struct intel_encoder encoder);
2325	Serge	651	void (fdi_link_train)(struct drm_crtc crtc);
		652	void (init_clock_gating)(struct drm_device dev);
		653	int (queue_flip)(struct drm_device dev, struct drm_crtc *crtc,
		654	struct drm_framebuffer *fb,
4104	Serge	655	struct drm_i915_gem_object *obj,
6084	serge	656	struct drm_i915_gem_request *req,
4104	Serge	657	uint32_t flags);
3480	Serge	658	void (hpd_irq_setup)(struct drm_device dev);
2325	Serge	659	/* clock updates for mode set */
		660	/* cursor updates */
		661	/* render clock increase/decrease */
		662	/* display clock increase/decrease */
		663	/* pll clock increase/decrease */
6084	serge	664	};
4560	Serge	665
6084	serge	666	enum forcewake_domain_id {
		667	FW_DOMAIN_ID_RENDER = 0,
		668	FW_DOMAIN_ID_BLITTER,
		669	FW_DOMAIN_ID_MEDIA,
		670
		671	FW_DOMAIN_ID_COUNT
2325	Serge	672	};
		673
6084	serge	674	enum forcewake_domains {
		675	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
		676	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
		677	FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
		678	FORCEWAKE_ALL = (FORCEWAKE_RENDER \|
		679	FORCEWAKE_BLITTER \|
		680	FORCEWAKE_MEDIA)
		681	};
		682
4104	Serge	683	struct intel_uncore_funcs {
4560	Serge	684	void (force_wake_get)(struct drm_i915_private dev_priv,
6084	serge	685	enum forcewake_domains domains);
4560	Serge	686	void (force_wake_put)(struct drm_i915_private dev_priv,
6084	serge	687	enum forcewake_domains domains);
4560	Serge	688
6937	serge	689	uint8_t (mmio_readb)(struct drm_i915_private dev_priv, i915_reg_t r, bool trace);
		690	uint16_t (mmio_readw)(struct drm_i915_private dev_priv, i915_reg_t r, bool trace);
		691	uint32_t (mmio_readl)(struct drm_i915_private dev_priv, i915_reg_t r, bool trace);
		692	uint64_t (mmio_readq)(struct drm_i915_private dev_priv, i915_reg_t r, bool trace);
4560	Serge	693
6937	serge	694	void (mmio_writeb)(struct drm_i915_private dev_priv, i915_reg_t r,
4560	Serge	695	uint8_t val, bool trace);
6937	serge	696	void (mmio_writew)(struct drm_i915_private dev_priv, i915_reg_t r,
4560	Serge	697	uint16_t val, bool trace);
6937	serge	698	void (mmio_writel)(struct drm_i915_private dev_priv, i915_reg_t r,
4560	Serge	699	uint32_t val, bool trace);
6937	serge	700	void (mmio_writeq)(struct drm_i915_private dev_priv, i915_reg_t r,
4560	Serge	701	uint64_t val, bool trace);
3031	serge	702	};
		703
4104	Serge	704	struct intel_uncore {
		705	spinlock_t lock; /** lock is also taken in irq contexts. */
3031	serge	706
4104	Serge	707	struct intel_uncore_funcs funcs;
		708
		709	unsigned fifo_count;
6084	serge	710	enum forcewake_domains fw_domains;
4560	Serge	711
6084	serge	712	struct intel_uncore_forcewake_domain {
		713	struct drm_i915_private *i915;
		714	enum forcewake_domain_id id;
		715	unsigned wake_count;
		716	struct timer_list timer;
6937	serge	717	i915_reg_t reg_set;
6084	serge	718	u32 val_set;
		719	u32 val_clear;
6937	serge	720	i915_reg_t reg_ack;
		721	i915_reg_t reg_post;
6084	serge	722	u32 val_reset;
		723	} fw_domain[FW_DOMAIN_ID_COUNT];
7144	serge	724
		725	int unclaimed_mmio_check;
6084	serge	726	};
4560	Serge	727
6084	serge	728	/* Iterate over initialised fw domains */
		729	#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
		730	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
		731	(i__) < FW_DOMAIN_ID_COUNT; \
		732	(i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
6937	serge	733	for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
6084	serge	734
		735	#define for_each_fw_domain(domain__, dev_priv__, i__) \
		736	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
		737
6937	serge	738	#define CSR_VERSION(major, minor) ((major) << 16 \| (minor))
		739	#define CSR_VERSION_MAJOR(version) ((version) >> 16)
		740	#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
4104	Serge	741
6084	serge	742	struct intel_csr {
6937	serge	743	struct work_struct work;
6084	serge	744	const char *fw_path;
		745	uint32_t *dmc_payload;
		746	uint32_t dmc_fw_size;
6937	serge	747	uint32_t version;
6084	serge	748	uint32_t mmio_count;
6937	serge	749	i915_reg_t mmioaddr[8];
6084	serge	750	uint32_t mmiodata[8];
6937	serge	751	uint32_t dc_state;
6084	serge	752	};
		753
4104	Serge	754	#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
		755	func(is_mobile) sep \
		756	func(is_i85x) sep \
		757	func(is_i915g) sep \
		758	func(is_i945gm) sep \
		759	func(is_g33) sep \
		760	func(need_gfx_hws) sep \
		761	func(is_g4x) sep \
		762	func(is_pineview) sep \
		763	func(is_broadwater) sep \
		764	func(is_crestline) sep \
		765	func(is_ivybridge) sep \
		766	func(is_valleyview) sep \
6937	serge	767	func(is_cherryview) sep \
4104	Serge	768	func(is_haswell) sep \
5354	serge	769	func(is_skylake) sep \
6937	serge	770	func(is_broxton) sep \
		771	func(is_kabylake) sep \
4560	Serge	772	func(is_preliminary) sep \
4104	Serge	773	func(has_fbc) sep \
		774	func(has_pipe_cxsr) sep \
		775	func(has_hotplug) sep \
		776	func(cursor_needs_physical) sep \
		777	func(has_overlay) sep \
		778	func(overlay_needs_physical) sep \
		779	func(supports_tv) sep \
		780	func(has_llc) sep \
		781	func(has_ddi) sep \
		782	func(has_fpga_dbg)
		783
		784	#define DEFINE_FLAG(name) u8 name:1
		785	#define SEP_SEMICOLON ;
		786
2325	Serge	787	struct intel_device_info {
3480	Serge	788	u32 display_mmio_offset;
5354	serge	789	u16 device_id;
3746	Serge	790	u8 num_pipes:3;
5060	serge	791	u8 num_sprites[I915_MAX_PIPES];
2325	Serge	792	u8 gen;
4560	Serge	793	u8 ring_mask; /* Rings supported by the HW */
4104	Serge	794	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
5060	serge	795	/* Register offsets for the various display pipes and transcoders */
		796	int pipe_offsets[I915_MAX_TRANSCODERS];
		797	int trans_offsets[I915_MAX_TRANSCODERS];
		798	int palette_offsets[I915_MAX_PIPES];
		799	int cursor_offsets[I915_MAX_PIPES];
6084	serge	800
		801	/* Slice/subslice/EU info */
		802	u8 slice_total;
		803	u8 subslice_total;
		804	u8 subslice_per_slice;
		805	u8 eu_total;
		806	u8 eu_per_subslice;
		807	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
		808	u8 subslice_7eu[3];
		809	u8 has_slice_pg:1;
		810	u8 has_subslice_pg:1;
		811	u8 has_eu_pg:1;
2325	Serge	812	};
		813
4104	Serge	814	#undef DEFINE_FLAG
		815	#undef SEP_SEMICOLON
		816
3480	Serge	817	enum i915_cache_level {
		818	I915_CACHE_NONE = 0,
4104	Serge	819	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
		820	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
		821	caches, eg sampler/render caches, and the
		822	large Last-Level-Cache. LLC is coherent with
		823	the CPU, but L3 is only visible to the GPU. */
		824	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
3480	Serge	825	};
		826
4104	Serge	827	struct i915_ctx_hang_stats {
		828	/* This context had batch pending when hang was declared */
		829	unsigned batch_pending;
		830
		831	/* This context had batch active when hang was declared */
		832	unsigned batch_active;
4560	Serge	833
		834	/* Time when this context was last blamed for a GPU reset */
		835	unsigned long guilty_ts;
		836
6084	serge	837	/* If the contexts causes a second GPU hang within this time,
		838	* it is permanently banned from submitting any more work.
		839	*/
		840	unsigned long ban_period_seconds;
		841
4560	Serge	842	/* This context is banned to submit more work */
		843	bool banned;
4104	Serge	844	};
		845
3031	serge	846	/* This must match up with the value previously used for execbuf2.rsvd1. */
5060	serge	847	#define DEFAULT_CONTEXT_HANDLE 0
6084	serge	848
		849	#define CONTEXT_NO_ZEROMAP (1<<0)
5060	serge	850	/**
		851	* struct intel_context - as the name implies, represents a context.
		852	* @ref: reference count.
		853	* @user_handle: userspace tracking identity for this context.
		854	* @remap_slice: l3 row remapping information.
6084	serge	855	* @flags: context specific flags:
		856	* CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
5060	serge	857	* @file_priv: filp associated with this context (NULL for global default
		858	* context).
		859	* @hang_stats: information about the role of this context in possible GPU
		860	* hangs.
6084	serge	861	* @ppgtt: virtual memory space used by this context.
5060	serge	862	* @legacy_hw_ctx: render context backing object and whether it is correctly
		863	* initialized (legacy ring submission mechanism only).
		864	* @link: link in the global list of contexts.
		865	*
		866	* Contexts are memory images used by the hardware to store copies of their
		867	* internal state.
		868	*/
		869	struct intel_context {
4104	Serge	870	struct kref ref;
5060	serge	871	int user_handle;
4560	Serge	872	uint8_t remap_slice;
6084	serge	873	struct drm_i915_private *i915;
		874	int flags;
3031	serge	875	struct drm_i915_file_private *file_priv;
4104	Serge	876	struct i915_ctx_hang_stats hang_stats;
5354	serge	877	struct i915_hw_ppgtt *ppgtt;
4560	Serge	878
5354	serge	879	/* Legacy ring buffer submission */
5060	serge	880	struct {
		881	struct drm_i915_gem_object *rcs_state;
		882	bool initialized;
		883	} legacy_hw_ctx;
		884
5354	serge	885	/* Execlists */
		886	struct {
		887	struct drm_i915_gem_object *state;
		888	struct intel_ringbuffer *ringbuf;
6084	serge	889	int pin_count;
7144	serge	890	struct i915_vma *lrc_vma;
		891	u64 lrc_desc;
		892	uint32_t *lrc_reg_state;
5354	serge	893	} engine[I915_NUM_RINGS];
		894
4560	Serge	895	struct list_head link;
3031	serge	896	};
		897
6084	serge	898	enum fb_op_origin {
		899	ORIGIN_GTT,
		900	ORIGIN_CPU,
		901	ORIGIN_CS,
		902	ORIGIN_FLIP,
		903	ORIGIN_DIRTYFB,
		904	};
		905
7144	serge	906	struct intel_fbc {
6084	serge	907	/* This is always the inner lock when overlapping with struct_mutex and
		908	* it's the outer lock when overlapping with stolen_lock. */
		909	struct mutex lock;
5060	serge	910	unsigned threshold;
6084	serge	911	unsigned int possible_framebuffer_bits;
		912	unsigned int busy_bits;
7144	serge	913	unsigned int visible_pipes_mask;
6084	serge	914	struct intel_crtc *crtc;
4104	Serge	915
5060	serge	916	struct drm_mm_node compressed_fb;
4104	Serge	917	struct drm_mm_node *compressed_llb;
		918
5354	serge	919	bool false_color;
		920
		921	bool enabled;
6937	serge	922	bool active;
5354	serge	923
7144	serge	924	struct intel_fbc_state_cache {
		925	struct {
		926	unsigned int mode_flags;
		927	uint32_t hsw_bdw_pixel_rate;
		928	} crtc;
		929
		930	struct {
		931	unsigned int rotation;
		932	int src_w;
		933	int src_h;
		934	bool visible;
		935	} plane;
		936
		937	struct {
		938	u64 ilk_ggtt_offset;
		939	uint32_t pixel_format;
		940	unsigned int stride;
		941	int fence_reg;
		942	unsigned int tiling_mode;
		943	} fb;
		944	} state_cache;
		945
		946	struct intel_fbc_reg_params {
		947	struct {
		948	enum pipe pipe;
		949	enum plane plane;
		950	unsigned int fence_y_offset;
		951	} crtc;
		952
		953	struct {
		954	u64 ggtt_offset;
		955	uint32_t pixel_format;
		956	unsigned int stride;
		957	int fence_reg;
		958	} fb;
		959
		960	int cfb_size;
		961	} params;
		962
4104	Serge	963	struct intel_fbc_work {
6937	serge	964	bool scheduled;
7144	serge	965	u32 scheduled_vblank;
6937	serge	966	struct work_struct work;
		967	} work;
4104	Serge	968
6937	serge	969	const char *no_fbc_reason;
2325	Serge	970	};
		971
6084	serge	972	/**
		973	* HIGH_RR is the highest eDP panel refresh rate read from EDID
		974	* LOW_RR is the lowest eDP panel refresh rate found from EDID
		975	* parsing for same resolution.
		976	*/
		977	enum drrs_refresh_rate_type {
		978	DRRS_HIGH_RR,
		979	DRRS_LOW_RR,
		980	DRRS_MAX_RR, /* RR count */
		981	};
		982
		983	enum drrs_support_type {
		984	DRRS_NOT_SUPPORTED = 0,
		985	STATIC_DRRS_SUPPORT = 1,
		986	SEAMLESS_DRRS_SUPPORT = 2
		987	};
		988
		989	struct intel_dp;
5060	serge	990	struct i915_drrs {
6084	serge	991	struct mutex mutex;
		992	struct delayed_work work;
		993	struct intel_dp *dp;
		994	unsigned busy_frontbuffer_bits;
		995	enum drrs_refresh_rate_type refresh_rate_type;
		996	enum drrs_support_type type;
5060	serge	997	};
		998
4560	Serge	999	struct i915_psr {
5060	serge	1000	struct mutex lock;
4560	Serge	1001	bool sink_support;
		1002	bool source_ok;
5060	serge	1003	struct intel_dp *enabled;
		1004	bool active;
		1005	struct delayed_work work;
		1006	unsigned busy_frontbuffer_bits;
6084	serge	1007	bool psr2_support;
		1008	bool aux_frame_sync;
7144	serge	1009	bool link_standby;
4104	Serge	1010	};
		1011
2325	Serge	1012	enum intel_pch {
3031	serge	1013	PCH_NONE = 0, /* No PCH present */
2325	Serge	1014	PCH_IBX, /* Ibexpeak PCH */
		1015	PCH_CPT, /* Cougarpoint PCH */
3031	serge	1016	PCH_LPT, /* Lynxpoint PCH */
5354	serge	1017	PCH_SPT, /* Sunrisepoint PCH */
3746	Serge	1018	PCH_NOP,
2325	Serge	1019	};
		1020
3243	Serge	1021	enum intel_sbi_destination {
		1022	SBI_ICLK,
		1023	SBI_MPHY,
		1024	};
		1025
2325	Serge	1026	#define QUIRK_PIPEA_FORCE (1<<0)
		1027	#define QUIRK_LVDS_SSC_DISABLE (1<<1)
3031	serge	1028	#define QUIRK_INVERT_BRIGHTNESS (1<<2)
5060	serge	1029	#define QUIRK_BACKLIGHT_PRESENT (1<<3)
5354	serge	1030	#define QUIRK_PIPEB_FORCE (1<<4)
		1031	#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
2325	Serge	1032
		1033	struct intel_fbdev;
		1034	struct intel_fbc_work;
		1035
3031	serge	1036	struct intel_gmbus {
		1037	struct i2c_adapter adapter;
3243	Serge	1038	u32 force_bit;
3031	serge	1039	u32 reg0;
6937	serge	1040	i915_reg_t gpio_reg;
3031	serge	1041	struct i2c_algo_bit_data bit_algo;
		1042	struct drm_i915_private *dev_priv;
		1043	};
		1044
3243	Serge	1045	struct i915_suspend_saved_registers {
2325	Serge	1046	u32 saveDSPARB;
		1047	u32 saveLVDS;
		1048	u32 savePP_ON_DELAYS;
		1049	u32 savePP_OFF_DELAYS;
		1050	u32 savePP_ON;
		1051	u32 savePP_OFF;
		1052	u32 savePP_CONTROL;
		1053	u32 savePP_DIVISOR;
		1054	u32 saveFBC_CONTROL;
		1055	u32 saveCACHE_MODE_0;
		1056	u32 saveMI_ARB_STATE;
		1057	u32 saveSWF0[16];
		1058	u32 saveSWF1[16];
6084	serge	1059	u32 saveSWF3[3];
2342	Serge	1060	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
2325	Serge	1061	u32 savePCH_PORT_HOTPLUG;
5354	serge	1062	u16 saveGCDGMBUS;
3243	Serge	1063	};
2325	Serge	1064
5060	serge	1065	struct vlv_s0ix_state {
		1066	/* GAM */
		1067	u32 wr_watermark;
		1068	u32 gfx_prio_ctrl;
		1069	u32 arb_mode;
		1070	u32 gfx_pend_tlb0;
		1071	u32 gfx_pend_tlb1;
		1072	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
		1073	u32 media_max_req_count;
		1074	u32 gfx_max_req_count;
		1075	u32 render_hwsp;
		1076	u32 ecochk;
		1077	u32 bsd_hwsp;
		1078	u32 blt_hwsp;
		1079	u32 tlb_rd_addr;
		1080
		1081	/* MBC */
		1082	u32 g3dctl;
		1083	u32 gsckgctl;
		1084	u32 mbctl;
		1085
		1086	/* GCP */
		1087	u32 ucgctl1;
		1088	u32 ucgctl3;
		1089	u32 rcgctl1;
		1090	u32 rcgctl2;
		1091	u32 rstctl;
		1092	u32 misccpctl;
		1093
		1094	/* GPM */
		1095	u32 gfxpause;
		1096	u32 rpdeuhwtc;
		1097	u32 rpdeuc;
		1098	u32 ecobus;
		1099	u32 pwrdwnupctl;
		1100	u32 rp_down_timeout;
		1101	u32 rp_deucsw;
		1102	u32 rcubmabdtmr;
		1103	u32 rcedata;
		1104	u32 spare2gh;
		1105
		1106	/* Display 1 CZ domain */
		1107	u32 gt_imr;
		1108	u32 gt_ier;
		1109	u32 pm_imr;
		1110	u32 pm_ier;
		1111	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
		1112
		1113	/* GT SA CZ domain */
		1114	u32 tilectl;
		1115	u32 gt_fifoctl;
		1116	u32 gtlc_wake_ctrl;
		1117	u32 gtlc_survive;
		1118	u32 pmwgicz;
		1119
		1120	/* Display 2 CZ domain */
		1121	u32 gu_ctl0;
		1122	u32 gu_ctl1;
6084	serge	1123	u32 pcbr;
5060	serge	1124	u32 clock_gate_dis2;
		1125	};
		1126
		1127	struct intel_rps_ei {
		1128	u32 cz_clock;
		1129	u32 render_c0;
		1130	u32 media_c0;
		1131	};
		1132
3243	Serge	1133	struct intel_gen6_power_mgmt {
5354	serge	1134	/*
		1135	* work, interrupts_enabled and pm_iir are protected by
		1136	* dev_priv->irq_lock
		1137	*/
3243	Serge	1138	struct work_struct work;
5354	serge	1139	bool interrupts_enabled;
3243	Serge	1140	u32 pm_iir;
		1141
5060	serge	1142	/* Frequencies are stored in potentially platform dependent multiples.
		1143	* In other words, *_freq needs to be multiplied by X to be interesting.
		1144	* Soft limits are those which are used for the dynamic reclocking done
		1145	* by the driver (raise frequencies under heavy loads, and lower for
		1146	* lighter loads). Hard limits are those imposed by the hardware.
		1147	*
		1148	* A distinction is made for overclocking, which is never enabled by
		1149	* default, and is considered to be above the hard limit if it's
		1150	* possible at all.
		1151	*/
		1152	u8 cur_freq; /* Current frequency (cached, may not == HW) */
		1153	u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
		1154	u8 max_freq_softlimit; /* Max frequency permitted by the driver */
		1155	u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
		1156	u8 min_freq; /* AKA RPn. Minimum frequency */
6084	serge	1157	u8 idle_freq; /* Frequency to request when we are idle */
5060	serge	1158	u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
		1159	u8 rp1_freq; /* "less than" RP0 power/freqency */
		1160	u8 rp0_freq; /* Non-overclocked max frequency. */
3243	Serge	1161
6084	serge	1162	u8 up_threshold; /* Current %busy required to uplock */
		1163	u8 down_threshold; /* Current %busy required to downclock */
5060	serge	1164
4560	Serge	1165	int last_adj;
		1166	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
		1167
6084	serge	1168	spinlock_t client_lock;
		1169	struct list_head clients;
		1170	bool client_boost;
		1171
4560	Serge	1172	bool enabled;
3243	Serge	1173	struct delayed_work delayed_resume_work;
6084	serge	1174	unsigned boosts;
3243	Serge	1175
6084	serge	1176	struct intel_rps_client semaphores, mmioflips;
		1177
5060	serge	1178	/* manual wa residency calculations */
6937	serge	1179	struct intel_rps_ei up_ei, down_ei;
5060	serge	1180
3243	Serge	1181	/*
		1182	* Protects RPS/RC6 register access and PCU communication.
6084	serge	1183	* Must be taken after struct_mutex if nested. Note that
		1184	* this lock may be held for long periods of time when
		1185	* talking to hw - so only take it when talking to hw!
3243	Serge	1186	*/
		1187	struct mutex hw_lock;
		1188	};
		1189
3480	Serge	1190	/* defined intel_pm.c */
		1191	extern spinlock_t mchdev_lock;
		1192
3243	Serge	1193	struct intel_ilk_power_mgmt {
		1194	u8 cur_delay;
		1195	u8 min_delay;
		1196	u8 max_delay;
		1197	u8 fmax;
		1198	u8 fstart;
		1199
		1200	u64 last_count1;
		1201	unsigned long last_time1;
		1202	unsigned long chipset_power;
		1203	u64 last_count2;
5060	serge	1204	u64 last_time2;
3243	Serge	1205	unsigned long gfx_power;
		1206	u8 corr;
		1207
		1208	int c_m;
		1209	int r_t;
		1210	};
		1211
5060	serge	1212	struct drm_i915_private;
		1213	struct i915_power_well;
		1214
		1215	struct i915_power_well_ops {
		1216	/*
		1217	* Synchronize the well's hw state to match the current sw state, for
		1218	* example enable/disable it based on the current refcount. Called
		1219	* during driver init and resume time, possibly after first calling
		1220	* the enable/disable handlers.
		1221	*/
		1222	void (sync_hw)(struct drm_i915_private dev_priv,
		1223	struct i915_power_well *power_well);
		1224	/*
		1225	* Enable the well and resources that depend on it (for example
		1226	* interrupts located on the well). Called after the 0->1 refcount
		1227	* transition.
		1228	*/
		1229	void (enable)(struct drm_i915_private dev_priv,
		1230	struct i915_power_well *power_well);
		1231	/*
		1232	* Disable the well and resources that depend on it. Called after
		1233	* the 1->0 refcount transition.
		1234	*/
		1235	void (disable)(struct drm_i915_private dev_priv,
		1236	struct i915_power_well *power_well);
		1237	/* Returns the hw enabled state. */
		1238	bool (is_enabled)(struct drm_i915_private dev_priv,
		1239	struct i915_power_well *power_well);
		1240	};
		1241
4104	Serge	1242	/* Power well structure for haswell */
		1243	struct i915_power_well {
4560	Serge	1244	const char *name;
		1245	bool always_on;
4104	Serge	1246	/* power well enable/disable usage count */
		1247	int count;
5060	serge	1248	/* cached hw enabled state */
		1249	bool hw_enabled;
4560	Serge	1250	unsigned long domains;
5060	serge	1251	unsigned long data;
		1252	const struct i915_power_well_ops *ops;
4104	Serge	1253	};
		1254
4560	Serge	1255	struct i915_power_domains {
		1256	/*
		1257	* Power wells needed for initialization at driver init and suspend
		1258	* time are on. They are kept on until after the first modeset.
		1259	*/
		1260	bool init_power_on;
5060	serge	1261	bool initializing;
4560	Serge	1262	int power_well_count;
		1263
		1264	struct mutex lock;
		1265	int domain_use_count[POWER_DOMAIN_NUM];
		1266	struct i915_power_well *power_wells;
		1267	};
		1268
		1269	#define MAX_L3_SLICES 2
3243	Serge	1270	struct intel_l3_parity {
4560	Serge	1271	u32 *remap_info[MAX_L3_SLICES];
3243	Serge	1272	struct work_struct error_work;
4560	Serge	1273	int which_slice;
3243	Serge	1274	};
		1275
3480	Serge	1276	struct i915_gem_mm {
		1277	/** Memory allocator for GTT stolen memory */
		1278	struct drm_mm stolen;
6084	serge	1279	/** Protects the usage of the GTT stolen memory allocator. This is
		1280	* always the inner lock when overlapping with struct_mutex. */
		1281	struct mutex stolen_lock;
		1282
3480	Serge	1283	/** List of all objects in gtt_space. Used to restore gtt
		1284	* mappings on resume */
		1285	struct list_head bound_list;
		1286	/**
		1287	* List of objects which are not bound to the GTT (thus
		1288	* are idle and not used by the GPU) but still have
		1289	* (presumably uncached) pages still attached.
		1290	*/
		1291	struct list_head unbound_list;
		1292
		1293	/** Usable portion of the GTT for GEM */
		1294	unsigned long stolen_base; /* limited to low memory (32-bit) */
		1295
		1296	/** PPGTT used for aliasing the PPGTT with the GTT */
		1297	struct i915_hw_ppgtt *aliasing_ppgtt;
		1298
6937	serge	1299	struct notifier_block oom_notifier;
3480	Serge	1300	/** LRU list of objects with fence regs on them. */
		1301	struct list_head fence_list;
		1302
		1303	/**
		1304	* We leave the user IRQ off as much as possible,
		1305	* but this means that requests will finish and never
		1306	* be retired once the system goes idle. Set a timer to
		1307	* fire periodically while the ring is running. When it
		1308	* fires, go retire requests.
		1309	*/
		1310	struct delayed_work retire_work;
		1311
		1312	/**
4560	Serge	1313	* When we detect an idle GPU, we want to turn on
		1314	* powersaving features. So once we see that there
		1315	* are no more requests outstanding and no more
		1316	* arrive within a small period of time, we fire
		1317	* off the idle_work.
		1318	*/
		1319	struct delayed_work idle_work;
		1320
		1321	/**
3480	Serge	1322	* Are we in a non-interruptible section of code like
		1323	* modesetting?
		1324	*/
		1325	bool interruptible;
		1326
5060	serge	1327	/**
		1328	* Is the GPU currently considered idle, or busy executing userspace
		1329	* requests? Whilst idle, we attempt to power down the hardware and
		1330	* display clocks. In order to reduce the effect on performance, there
		1331	* is a slight delay before we do so.
		1332	*/
		1333	bool busy;
		1334
		1335	/* the indicator for dispatch video commands on two BSD rings */
7144	serge	1336	unsigned int bsd_ring_dispatch_index;
5060	serge	1337
3480	Serge	1338	/** Bit 6 swizzling required for X tiling */
		1339	uint32_t bit_6_swizzle_x;
		1340	/** Bit 6 swizzling required for Y tiling */
		1341	uint32_t bit_6_swizzle_y;
		1342
		1343	/* accounting, useful for userland debugging */
4104	Serge	1344	spinlock_t object_stat_lock;
3480	Serge	1345	size_t object_memory;
		1346	u32 object_count;
		1347	};
		1348
4104	Serge	1349	struct drm_i915_error_state_buf {
5354	serge	1350	struct drm_i915_private *i915;
4104	Serge	1351	unsigned bytes;
		1352	unsigned size;
		1353	int err;
		1354	u8 *buf;
		1355	loff_t start;
		1356	loff_t pos;
		1357	};
		1358
		1359	struct i915_error_state_file_priv {
		1360	struct drm_device *dev;
		1361	struct drm_i915_error_state *error;
		1362	};
		1363
3480	Serge	1364	struct i915_gpu_error {
		1365	/* For hangcheck timer */
		1366	#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
		1367	#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
4560	Serge	1368	/* Hang gpu twice in this window and your context gets banned */
		1369	#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
		1370
6084	serge	1371	struct workqueue_struct *hangcheck_wq;
		1372	struct delayed_work hangcheck_work;
3480	Serge	1373
		1374	/* For reset and error_state handling. */
		1375	spinlock_t lock;
		1376	/* Protected by the above dev->gpu_error.lock. */
		1377	struct drm_i915_error_state *first_error;
		1378
4560	Serge	1379	unsigned long missed_irq_rings;
		1380
3480	Serge	1381	/**
4560	Serge	1382	* State variable controlling the reset flow and count
3480	Serge	1383	*
4560	Serge	1384	* This is a counter which gets incremented when reset is triggered,
		1385	* and again when reset has been handled. So odd values (lowest bit set)
		1386	* means that reset is in progress and even values that
		1387	* (reset_counter >> 1):th reset was successfully completed.
3480	Serge	1388	*
4560	Serge	1389	* If reset is not completed succesfully, the I915_WEDGE bit is
		1390	* set meaning that hardware is terminally sour and there is no
		1391	* recovery. All waiters on the reset_queue will be woken when
		1392	* that happens.
		1393	*
		1394	* This counter is used by the wait_seqno code to notice that reset
		1395	* event happened and it needs to restart the entire ioctl (since most
		1396	* likely the seqno it waited for won't ever signal anytime soon).
		1397	*
3480	Serge	1398	* This is important for lock-free wait paths, where no contended lock
		1399	* naturally enforces the correct ordering between the bail-out of the
		1400	* waiter and the gpu reset work code.
		1401	*/
		1402	atomic_t reset_counter;
		1403
		1404	#define I915_RESET_IN_PROGRESS_FLAG 1
4560	Serge	1405	#define I915_WEDGED (1 << 31)
3480	Serge	1406
		1407	/**
		1408	* Waitqueue to signal when the reset has completed. Used by clients
		1409	* that wait for dev_priv->mm.wedged to settle.
		1410	*/
		1411	wait_queue_head_t reset_queue;
		1412
5060	serge	1413	/* Userspace knobs for gpu hang simulation;
		1414	* combines both a ring mask, and extra flags
		1415	*/
		1416	u32 stop_rings;
		1417	#define I915_STOP_RING_ALLOW_BAN (1 << 31)
		1418	#define I915_STOP_RING_ALLOW_WARN (1 << 30)
4560	Serge	1419
		1420	/* For missed irq/seqno simulation. */
		1421	unsigned int test_irq_rings;
5354	serge	1422
		1423	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
		1424	bool reload_in_reset;
3480	Serge	1425	};
		1426
		1427	enum modeset_restore {
		1428	MODESET_ON_LID_OPEN,
		1429	MODESET_DONE,
		1430	MODESET_SUSPENDED,
		1431	};
		1432
6084	serge	1433	#define DP_AUX_A 0x40
		1434	#define DP_AUX_B 0x10
		1435	#define DP_AUX_C 0x20
		1436	#define DP_AUX_D 0x30
		1437
		1438	#define DDC_PIN_B 0x05
		1439	#define DDC_PIN_C 0x04
		1440	#define DDC_PIN_D 0x06
		1441
4560	Serge	1442	struct ddi_vbt_port_info {
5354	serge	1443	/*
		1444	* This is an index in the HDMI/DVI DDI buffer translation table.
		1445	* The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
		1446	* populate this field.
		1447	*/
		1448	#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
4560	Serge	1449	uint8_t hdmi_level_shift;
		1450
		1451	uint8_t supports_dvi:1;
		1452	uint8_t supports_hdmi:1;
		1453	uint8_t supports_dp:1;
6084	serge	1454
		1455	uint8_t alternate_aux_channel;
		1456	uint8_t alternate_ddc_pin;
		1457
		1458	uint8_t dp_boost_level;
		1459	uint8_t hdmi_boost_level;
4560	Serge	1460	};
		1461
6084	serge	1462	enum psr_lines_to_wait {
		1463	PSR_0_LINES_TO_WAIT = 0,
		1464	PSR_1_LINE_TO_WAIT,
		1465	PSR_4_LINES_TO_WAIT,
		1466	PSR_8_LINES_TO_WAIT
5060	serge	1467	};
		1468
4104	Serge	1469	struct intel_vbt_data {
		1470	struct drm_display_mode lfp_lvds_vbt_mode; / if any */
		1471	struct drm_display_mode sdvo_lvds_vbt_mode; / if any */
		1472
		1473	/* Feature bits */
		1474	unsigned int int_tv_support:1;
		1475	unsigned int lvds_dither:1;
		1476	unsigned int lvds_vbt:1;
		1477	unsigned int int_crt_support:1;
		1478	unsigned int lvds_use_ssc:1;
		1479	unsigned int display_clock_mode:1;
		1480	unsigned int fdi_rx_polarity_inverted:1;
5060	serge	1481	unsigned int has_mipi:1;
4104	Serge	1482	int lvds_ssc_freq;
		1483	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
		1484
5060	serge	1485	enum drrs_support_type drrs_type;
		1486
4104	Serge	1487	/* eDP */
		1488	int edp_rate;
		1489	int edp_lanes;
		1490	int edp_preemphasis;
		1491	int edp_vswing;
		1492	bool edp_initialized;
		1493	bool edp_support;
		1494	int edp_bpp;
		1495	struct edp_power_seq edp_pps;
		1496
4560	Serge	1497	struct {
6084	serge	1498	bool full_link;
		1499	bool require_aux_wakeup;
		1500	int idle_frames;
		1501	enum psr_lines_to_wait lines_to_wait;
		1502	int tp1_wakeup_time;
		1503	int tp2_tp3_wakeup_time;
		1504	} psr;
		1505
		1506	struct {
4560	Serge	1507	u16 pwm_freq_hz;
5060	serge	1508	bool present;
4560	Serge	1509	bool active_low_pwm;
5060	serge	1510	u8 min_brightness; /* min_brightness/255 of max */
4560	Serge	1511	} backlight;
		1512
		1513	/* MIPI DSI */
		1514	struct {
5060	serge	1515	u16 port;
4560	Serge	1516	u16 panel_id;
5060	serge	1517	struct mipi_config *config;
		1518	struct mipi_pps_data *pps;
		1519	u8 seq_version;
		1520	u32 size;
		1521	u8 *data;
7144	serge	1522	const u8 *sequence[MIPI_SEQ_MAX];
4560	Serge	1523	} dsi;
		1524
4104	Serge	1525	int crt_ddc_pin;
		1526
		1527	int child_dev_num;
4560	Serge	1528	union child_device_config *child_dev;
		1529
		1530	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
4104	Serge	1531	};
		1532
		1533	enum intel_ddb_partitioning {
		1534	INTEL_DDB_PART_1_2,
		1535	INTEL_DDB_PART_5_6, /* IVB+ */
		1536	};
		1537
		1538	struct intel_wm_level {
		1539	bool enable;
		1540	uint32_t pri_val;
		1541	uint32_t spr_val;
		1542	uint32_t cur_val;
		1543	uint32_t fbc_val;
		1544	};
		1545
4560	Serge	1546	struct ilk_wm_values {
		1547	uint32_t wm_pipe[3];
		1548	uint32_t wm_lp[3];
		1549	uint32_t wm_lp_spr[3];
		1550	uint32_t wm_linetime[3];
		1551	bool enable_fbc_wm;
		1552	enum intel_ddb_partitioning partitioning;
		1553	};
		1554
6084	serge	1555	struct vlv_pipe_wm {
		1556	uint16_t primary;
		1557	uint16_t sprite[2];
		1558	uint8_t cursor;
		1559	};
		1560
		1561	struct vlv_sr_wm {
		1562	uint16_t plane;
		1563	uint8_t cursor;
		1564	};
		1565
		1566	struct vlv_wm_values {
		1567	struct vlv_pipe_wm pipe[3];
		1568	struct vlv_sr_wm sr;
		1569	struct {
		1570	uint8_t cursor;
		1571	uint8_t sprite[2];
		1572	uint8_t primary;
		1573	} ddl[3];
		1574	uint8_t level;
		1575	bool cxsr;
		1576	};
		1577
5354	serge	1578	struct skl_ddb_entry {
		1579	uint16_t start, end; /* in number of blocks, 'end' is exclusive */
		1580	};
		1581
		1582	static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
		1583	{
		1584	return entry->end - entry->start;
		1585	}
		1586
		1587	static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
		1588	const struct skl_ddb_entry *e2)
		1589	{
		1590	if (e1->start == e2->start && e1->end == e2->end)
		1591	return true;
		1592
		1593	return false;
		1594	}
		1595
		1596	struct skl_ddb_allocation {
		1597	struct skl_ddb_entry pipe[I915_MAX_PIPES];
6084	serge	1598	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
		1599	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
5354	serge	1600	};
		1601
		1602	struct skl_wm_values {
		1603	bool dirty[I915_MAX_PIPES];
		1604	struct skl_ddb_allocation ddb;
		1605	uint32_t wm_linetime[I915_MAX_PIPES];
		1606	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
		1607	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
		1608	};
		1609
		1610	struct skl_wm_level {
		1611	bool plane_en[I915_MAX_PLANES];
		1612	uint16_t plane_res_b[I915_MAX_PLANES];
		1613	uint8_t plane_res_l[I915_MAX_PLANES];
		1614	};
		1615
4104	Serge	1616	/*
5060	serge	1617	* This struct helps tracking the state needed for runtime PM, which puts the
		1618	* device in PCI D3 state. Notice that when this happens, nothing on the
		1619	* graphics device works, even register access, so we don't get interrupts nor
		1620	* anything else.
4104	Serge	1621	*
5060	serge	1622	* Every piece of our code that needs to actually touch the hardware needs to
		1623	* either call intel_runtime_pm_get or call intel_display_power_get with the
		1624	* appropriate power domain.
4104	Serge	1625	*
5060	serge	1626	* Our driver uses the autosuspend delay feature, which means we'll only really
		1627	* suspend if we stay with zero refcount for a certain amount of time. The
5354	serge	1628	* default value is currently very conservative (see intel_runtime_pm_enable), but
5060	serge	1629	* it can be changed with the standard runtime PM files from sysfs.
4104	Serge	1630	*
		1631	* The irqs_disabled variable becomes true exactly after we disable the IRQs and
		1632	* goes back to false exactly before we reenable the IRQs. We use this variable
		1633	* to check if someone is trying to enable/disable IRQs while they're supposed
		1634	* to be disabled. This shouldn't happen and we'll print some error messages in
5060	serge	1635	* case it happens.
4104	Serge	1636	*
5060	serge	1637	* For more, read the Documentation/power/runtime_pm.txt.
4104	Serge	1638	*/
4560	Serge	1639	struct i915_runtime_pm {
6937	serge	1640	atomic_t wakeref_count;
		1641	atomic_t atomic_seq;
4560	Serge	1642	bool suspended;
5354	serge	1643	bool irqs_enabled;
4560	Serge	1644	};
		1645
		1646	enum intel_pipe_crc_source {
		1647	INTEL_PIPE_CRC_SOURCE_NONE,
		1648	INTEL_PIPE_CRC_SOURCE_PLANE1,
		1649	INTEL_PIPE_CRC_SOURCE_PLANE2,
		1650	INTEL_PIPE_CRC_SOURCE_PF,
		1651	INTEL_PIPE_CRC_SOURCE_PIPE,
		1652	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
		1653	INTEL_PIPE_CRC_SOURCE_TV,
		1654	INTEL_PIPE_CRC_SOURCE_DP_B,
		1655	INTEL_PIPE_CRC_SOURCE_DP_C,
		1656	INTEL_PIPE_CRC_SOURCE_DP_D,
		1657	INTEL_PIPE_CRC_SOURCE_AUTO,
		1658	INTEL_PIPE_CRC_SOURCE_MAX,
		1659	};
		1660
		1661	struct intel_pipe_crc_entry {
		1662	uint32_t frame;
		1663	uint32_t crc[5];
		1664	};
		1665
		1666	#define INTEL_PIPE_CRC_ENTRIES_NR 128
		1667	struct intel_pipe_crc {
		1668	spinlock_t lock;
		1669	bool opened; /* exclusive access to the result file */
		1670	struct intel_pipe_crc_entry *entries;
		1671	enum intel_pipe_crc_source source;
		1672	int head, tail;
		1673	wait_queue_head_t wq;
		1674	};
		1675
5060	serge	1676	struct i915_frontbuffer_tracking {
		1677	struct mutex lock;
		1678
		1679	/*
		1680	* Tracking bits for delayed frontbuffer flushing du to gpu activity or
		1681	* scheduled flips.
		1682	*/
		1683	unsigned busy_bits;
		1684	unsigned flip_bits;
		1685	};
		1686
5354	serge	1687	struct i915_wa_reg {
6937	serge	1688	i915_reg_t addr;
5354	serge	1689	u32 value;
		1690	/* bitmask representing WA bits */
		1691	u32 mask;
		1692	};
		1693
7144	serge	1694	/*
		1695	* RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
		1696	* allowing it for RCS as we don't foresee any requirement of having
		1697	* a whitelist for other engines. When it is really required for
		1698	* other engines then the limit need to be increased.
		1699	*/
		1700	#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
5354	serge	1701
		1702	struct i915_workarounds {
		1703	struct i915_wa_reg reg[I915_MAX_WA_REGS];
		1704	u32 count;
7144	serge	1705	u32 hw_whitelist_count[I915_NUM_RINGS];
5354	serge	1706	};
		1707
6084	serge	1708	struct i915_virtual_gpu {
		1709	bool active;
		1710	};
		1711
		1712	struct i915_execbuffer_params {
		1713	struct drm_device *dev;
		1714	struct drm_file *file;
		1715	uint32_t dispatch_flags;
		1716	uint32_t args_batch_start_offset;
		1717	uint64_t batch_obj_vm_offset;
		1718	struct intel_engine_cs *ring;
		1719	struct drm_i915_gem_object *batch_obj;
		1720	struct intel_context *ctx;
		1721	struct drm_i915_gem_request *request;
		1722	};
		1723
6937	serge	1724	/* used in computing the new watermarks state */
		1725	struct intel_wm_config {
		1726	unsigned int num_pipes_active;
		1727	bool sprites_enabled;
		1728	bool sprites_scaled;
		1729	};
		1730
5060	serge	1731	struct drm_i915_private {
3243	Serge	1732	struct drm_device *dev;
6084	serge	1733	struct kmem_cache *objects;
		1734	struct kmem_cache *vmas;
		1735	struct kmem_cache *requests;
3243	Serge	1736
5060	serge	1737	const struct intel_device_info info;
3243	Serge	1738
		1739	int relative_constants_mode;
		1740
		1741	void __iomem *regs;
		1742
4104	Serge	1743	struct intel_uncore uncore;
3243	Serge	1744
6084	serge	1745	struct i915_virtual_gpu vgpu;
3243	Serge	1746
6084	serge	1747	struct intel_guc guc;
3480	Serge	1748
6084	serge	1749	struct intel_csr csr;
		1750
		1751	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
		1752
3243	Serge	1753	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
		1754	* controller on different i2c buses. */
		1755	struct mutex gmbus_mutex;
		1756
		1757	/**
		1758	* Base address of the gmbus and gpio block.
		1759	*/
		1760	uint32_t gpio_mmio_base;
		1761
5060	serge	1762	/* MMIO base address for MIPI regs */
		1763	uint32_t mipi_mmio_base;
		1764
6937	serge	1765	uint32_t psr_mmio_base;
		1766
3480	Serge	1767	wait_queue_head_t gmbus_wait_queue;
		1768
3243	Serge	1769	struct pci_dev *bridge_dev;
5060	serge	1770	struct intel_engine_cs ring[I915_NUM_RINGS];
		1771	struct drm_i915_gem_object *semaphore_obj;
3480	Serge	1772	uint32_t last_seqno, next_seqno;
3243	Serge	1773
5354	serge	1774	struct drm_dma_handle *status_page_dmah;
3243	Serge	1775	struct resource mch_res;
		1776
		1777	/* protects the irq masks */
		1778	spinlock_t irq_lock;
		1779
5060	serge	1780	/* protects the mmio flip data */
		1781	spinlock_t mmio_flip_lock;
		1782
		1783	bool display_irqs_enabled;
		1784
3480	Serge	1785
6084	serge	1786	/* Sideband mailbox protection */
		1787	struct mutex sb_lock;
3243	Serge	1788
		1789	/** Cached value of IMR to avoid reads in updating the bitfield */
4560	Serge	1790	union {
6084	serge	1791	u32 irq_mask;
4560	Serge	1792	u32 de_irq_mask[I915_MAX_PIPES];
		1793	};
3243	Serge	1794	u32 gt_irq_mask;
4104	Serge	1795	u32 pm_irq_mask;
5060	serge	1796	u32 pm_rps_events;
		1797	u32 pipestat_irq_mask[I915_MAX_PIPES];
3243	Serge	1798
6084	serge	1799	struct i915_hotplug hotplug;
7144	serge	1800	struct intel_fbc fbc;
5060	serge	1801	struct i915_drrs drrs;
3243	Serge	1802	struct intel_opregion opregion;
4104	Serge	1803	struct intel_vbt_data vbt;
3243	Serge	1804
5354	serge	1805	bool preserve_bios_swizzle;
		1806
3243	Serge	1807	/* overlay */
		1808	struct intel_overlay *overlay;
		1809
4560	Serge	1810	/* backlight registers and fields in struct intel_panel */
5354	serge	1811	struct mutex backlight_lock;
3746	Serge	1812
3243	Serge	1813	/* LVDS info */
		1814	bool no_aux_handshake;
		1815
5354	serge	1816	/* protects panel power sequencer state */
		1817	struct mutex pps_mutex;
		1818
3243	Serge	1819	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
		1820	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
		1821
		1822	unsigned int fsb_freq, mem_freq, is_ddr3;
6084	serge	1823	unsigned int skl_boot_cdclk;
7144	serge	1824	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
6084	serge	1825	unsigned int max_dotclk_freq;
5354	serge	1826	unsigned int hpll_freq;
6084	serge	1827	unsigned int czclk_freq;
3243	Serge	1828
4104	Serge	1829	/**
		1830	* wq - Driver workqueue for GEM.
		1831	*
		1832	* NOTE: Work items scheduled here are not allowed to grab any modeset
		1833	* locks, for otherwise the flushing done in the pageflip code will
		1834	* result in deadlocks.
		1835	*/
3243	Serge	1836	struct workqueue_struct *wq;
		1837
		1838	/* Display functions */
		1839	struct drm_i915_display_funcs display;
		1840
		1841	/* PCH chipset type */
		1842	enum intel_pch pch_type;
		1843	unsigned short pch_id;
		1844
		1845	unsigned long quirks;
		1846
3480	Serge	1847	enum modeset_restore modeset_restore;
		1848	struct mutex modeset_restore_lock;
7144	serge	1849	struct drm_atomic_state *modeset_restore_state;
3243	Serge	1850
4104	Serge	1851	struct list_head vm_list; /* Global list of all address spaces */
5060	serge	1852	struct i915_gtt gtt; /* VM representing the global address space */
2325	Serge	1853
3480	Serge	1854	struct i915_gem_mm mm;
5128	serge	1855	DECLARE_HASHTABLE(mm_structs, 7);
		1856	struct mutex mm_lock;
2325	Serge	1857
3031	serge	1858	/* Kernel Modesetting */
		1859
6084	serge	1860	struct sdvo_device_mapping sdvo_mappings[2];
2325	Serge	1861
5060	serge	1862	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
		1863	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2352	Serge	1864	wait_queue_head_t pending_flip_queue;
2325	Serge	1865
4560	Serge	1866	#ifdef CONFIG_DEBUG_FS
		1867	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
		1868	#endif
		1869
7144	serge	1870	/* dpll and cdclk state is protected by connection_mutex */
4104	Serge	1871	int num_shared_dpll;
		1872	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
7144	serge	1873
		1874	unsigned int active_crtcs;
		1875	unsigned int min_pixclk[I915_MAX_PIPES];
		1876
4560	Serge	1877	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
3031	serge	1878
5354	serge	1879	struct i915_workarounds workarounds;
		1880
2325	Serge	1881	/* Reclocking support */
		1882	bool render_reclock_avail;
5060	serge	1883
		1884	struct i915_frontbuffer_tracking fb_tracking;
		1885
2325	Serge	1886	u16 orig_clock;
		1887
		1888	bool mchbar_need_disable;
		1889
3243	Serge	1890	struct intel_l3_parity l3_parity;
		1891
4104	Serge	1892	/* Cannot be determined by PCIID. You must always read a register. */
		1893	size_t ellc_size;
		1894
3031	serge	1895	/* gen6+ rps state */
3243	Serge	1896	struct intel_gen6_power_mgmt rps;
2325	Serge	1897
3031	serge	1898	/* ilk-only ips/rps state. Everything in here is protected by the global
		1899	* mchdev_lock in intel_pm.c */
3243	Serge	1900	struct intel_ilk_power_mgmt ips;
2325	Serge	1901
4560	Serge	1902	struct i915_power_domains power_domains;
2325	Serge	1903
4560	Serge	1904	struct i915_psr psr;
2325	Serge	1905
3480	Serge	1906	struct i915_gpu_error gpu_error;
2325	Serge	1907
4104	Serge	1908	struct drm_i915_gem_object *vlv_pctx;
		1909
6084	serge	1910	#ifdef CONFIG_DRM_FBDEV_EMULATION
2325	Serge	1911	/* list of fbdev register on this device */
6084	serge	1912	struct intel_fbdev *fbdev;
5354	serge	1913	struct work_struct fbdev_suspend_work;
4560	Serge	1914	#endif
2325	Serge	1915
3031	serge	1916	struct drm_property *broadcast_rgb_property;
		1917	struct drm_property *force_audio_property;
		1918
6084	serge	1919	/* hda/i915 audio component */
		1920	struct i915_audio_component *audio_component;
		1921	bool audio_component_registered;
		1922	/**
		1923	* av_mutex - mutex for audio/video sync
		1924	*
		1925	*/
		1926	struct mutex av_mutex;
		1927
3031	serge	1928	uint32_t hw_context_size;
4560	Serge	1929	struct list_head context_list;
3243	Serge	1930
3480	Serge	1931	u32 fdi_rx_config;
3243	Serge	1932
6084	serge	1933	u32 chv_phy_control;
		1934
5060	serge	1935	u32 suspend_count;
6937	serge	1936	bool suspended_to_idle;
3243	Serge	1937	struct i915_suspend_saved_registers regfile;
5060	serge	1938	struct vlv_s0ix_state vlv_s0ix_state;
3243	Serge	1939
4104	Serge	1940	struct {
		1941	/*
		1942	* Raw watermark latency values:
		1943	* in 0.1us units for WM0,
		1944	* in 0.5us units for WM1+.
		1945	*/
		1946	/* primary */
		1947	uint16_t pri_latency[5];
		1948	/* sprite */
		1949	uint16_t spr_latency[5];
		1950	/* cursor */
		1951	uint16_t cur_latency[5];
5354	serge	1952	/*
		1953	* Raw watermark memory latency values
		1954	* for SKL for all 8 levels
		1955	* in 1us units.
		1956	*/
		1957	uint16_t skl_latency[8];
4560	Serge	1958
6937	serge	1959	/* Committed wm config */
		1960	struct intel_wm_config config;
		1961
5354	serge	1962	/*
		1963	* The skl_wm_values structure is a bit too big for stack
		1964	* allocation, so we keep the staging struct where we store
		1965	* intermediate results here instead.
		1966	*/
		1967	struct skl_wm_values skl_results;
		1968
4560	Serge	1969	/* current hardware state */
5354	serge	1970	union {
6084	serge	1971	struct ilk_wm_values hw;
5354	serge	1972	struct skl_wm_values skl_hw;
6084	serge	1973	struct vlv_wm_values vlv;
5354	serge	1974	};
6084	serge	1975
		1976	uint8_t max_level;
4104	Serge	1977	} wm;
		1978
4560	Serge	1979	struct i915_runtime_pm pm;
		1980
5354	serge	1981	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
		1982	struct {
6084	serge	1983	int (execbuf_submit)(struct i915_execbuffer_params params,
		1984	struct drm_i915_gem_execbuffer2 *args,
		1985	struct list_head *vmas);
5354	serge	1986	int (init_rings)(struct drm_device dev);
		1987	void (cleanup_ring)(struct intel_engine_cs ring);
		1988	void (stop_ring)(struct intel_engine_cs ring);
		1989	} gt;
		1990
7144	serge	1991	struct intel_context *kernel_context;
		1992
6084	serge	1993	bool edp_low_vswing;
		1994
		1995	/* perform PHY state sanity checks? */
		1996	bool chv_phy_assert[2];
		1997
6937	serge	1998	struct intel_encoder *dig_port_map[I915_MAX_PORTS];
		1999
5060	serge	2000	/*
		2001	* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
		2002	* will be rejected. Instead look for a better place.
		2003	*/
		2004	};
		2005
4104	Serge	2006	static inline struct drm_i915_private to_i915(const struct drm_device dev)
		2007	{
		2008	return dev->dev_private;
		2009	}
		2010
6084	serge	2011	static inline struct drm_i915_private dev_to_i915(struct device dev)
		2012	{
		2013	return to_i915(dev_get_drvdata(dev));
		2014	}
		2015
		2016	static inline struct drm_i915_private guc_to_i915(struct intel_guc guc)
		2017	{
		2018	return container_of(guc, struct drm_i915_private, guc);
		2019	}
		2020
3031	serge	2021	/* Iterate over initialised rings */
		2022	#define for_each_ring(ring__, dev_priv__, i__) \
		2023	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
6937	serge	2024	for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
3031	serge	2025
		2026	enum hdmi_force_audio {
		2027	HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
		2028	HDMI_AUDIO_OFF, /* force turn off HDMI audio */
		2029	HDMI_AUDIO_AUTO, /* trust EDID */
		2030	HDMI_AUDIO_ON, /* force turn on HDMI audio */
		2031	};
		2032
4104	Serge	2033	#define I915_GTT_OFFSET_NONE ((u32)-1)
2325	Serge	2034
3031	serge	2035	struct drm_i915_gem_object_ops {
6937	serge	2036	unsigned int flags;
		2037	#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
		2038
3031	serge	2039	/* Interface between the GEM object and its backing storage.
		2040	* get_pages() is called once prior to the use of the associated set
		2041	* of pages before to binding them into the GTT, and put_pages() is
		2042	* called after we no longer need them. As we expect there to be
		2043	* associated cost with migrating pages between the backing storage
		2044	* and making them available for the GPU (e.g. clflush), we may hold
		2045	* onto the pages after they are no longer referenced by the GPU
		2046	* in case they may be used again shortly (for example migrating the
		2047	* pages to a different memory domain within the GTT). put_pages()
		2048	* will therefore most likely be called when the object itself is
		2049	* being released or under memory pressure (where we attempt to
		2050	* reap pages for the shrinker).
		2051	*/
		2052	int (get_pages)(struct drm_i915_gem_object );
		2053	void (put_pages)(struct drm_i915_gem_object );
6937	serge	2054
5060	serge	2055	int (dmabuf_export)(struct drm_i915_gem_object );
		2056	void (release)(struct drm_i915_gem_object );
3031	serge	2057	};
		2058
5060	serge	2059	/*
		2060	* Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
6084	serge	2061	* considered to be the frontbuffer for the given plane interface-wise. This
5060	serge	2062	* doesn't mean that the hw necessarily already scans it out, but that any
		2063	* rendering (by the cpu or gpu) will land in the frontbuffer eventually.
		2064	*
		2065	* We have one bit per pipe and per scanout plane type.
		2066	*/
6084	serge	2067	#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
		2068	#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
5060	serge	2069	#define INTEL_FRONTBUFFER_BITS \
		2070	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
		2071	#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
		2072	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
		2073	#define INTEL_FRONTBUFFER_CURSOR(pipe) \
6084	serge	2074	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
		2075	#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
		2076	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
5060	serge	2077	#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
6084	serge	2078	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
5060	serge	2079	#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
6084	serge	2080	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
5060	serge	2081
2327	Serge	2082	struct drm_i915_gem_object {
6084	serge	2083	struct drm_gem_object base;
2325	Serge	2084
3031	serge	2085	const struct drm_i915_gem_object_ops *ops;
		2086
4104	Serge	2087	/** List of VMAs backed by this object */
		2088	struct list_head vma_list;
		2089
3480	Serge	2090	/** Stolen memory for this object, instead of being backed by shmem. */
		2091	struct drm_mm_node *stolen;
4104	Serge	2092	struct list_head global_list;
2327	Serge	2093
6084	serge	2094	struct list_head ring_list[I915_NUM_RINGS];
4104	Serge	2095	/** Used in execbuf to temporarily hold a ref */
		2096	struct list_head obj_exec_link;
2327	Serge	2097
6084	serge	2098	struct list_head batch_pool_link;
		2099
		2100	/**
3031	serge	2101	* This is set if the object is on the active lists (has pending
		2102	* rendering and so a non-zero seqno), and is not set if it i s on
		2103	* inactive (ready to be unbound) list.
6084	serge	2104	*/
		2105	unsigned int active:I915_NUM_RINGS;
2327	Serge	2106
6084	serge	2107	/**
		2108	* This is set if the object has been written to since last bound
		2109	* to the GTT
		2110	*/
2342	Serge	2111	unsigned int dirty:1;
2327	Serge	2112
6084	serge	2113	/**
		2114	* Fence register bits (if any) for this object. Will be set
		2115	* as needed when mapped into the GTT.
		2116	* Protected by dev->struct_mutex.
		2117	*/
2342	Serge	2118	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2327	Serge	2119
6084	serge	2120	/**
		2121	* Advice: are the backing pages purgeable?
		2122	*/
2342	Serge	2123	unsigned int madv:2;
2327	Serge	2124
6084	serge	2125	/**
		2126	* Current tiling mode for the object.
		2127	*/
2342	Serge	2128	unsigned int tiling_mode:2;
3031	serge	2129	/**
		2130	* Whether the tiling parameters for the currently associated fence
		2131	* register have changed. Note that for the purposes of tracking
		2132	* tiling changes we also treat the unfenced register, the register
		2133	* slot that the object occupies whilst it executes a fenced
		2134	* command (such as BLT on gen2/3), as a "fence".
		2135	*/
		2136	unsigned int fence_dirty:1;
2327	Serge	2137
6084	serge	2138	/**
		2139	* Is the object at the current location in the gtt mappable and
		2140	* fenceable? Used to avoid costly recalculations.
		2141	*/
2342	Serge	2142	unsigned int map_and_fenceable:1;
2327	Serge	2143
6084	serge	2144	/**
		2145	* Whether the current gtt mapping needs to be mappable (and isn't just
		2146	* mappable by accident). Track pin and fault separate for a more
		2147	* accurate mappable working set.
		2148	*/
2342	Serge	2149	unsigned int fault_mappable:1;
2327	Serge	2150
6084	serge	2151	/*
5060	serge	2152	* Is the object to be mapped as read-only to the GPU
		2153	* Only honoured if hardware has relevant pte bit
		2154	*/
		2155	unsigned long gt_ro:1;
4104	Serge	2156	unsigned int cache_level:3;
6084	serge	2157	unsigned int cache_dirty:1;
2327	Serge	2158
5060	serge	2159	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
		2160
6084	serge	2161	unsigned int pin_display;
		2162
3243	Serge	2163	struct sg_table *pages;
3031	serge	2164	int pages_pin_count;
6084	serge	2165	struct get_page {
		2166	struct scatterlist *sg;
		2167	int last;
		2168	} get_page;
2327	Serge	2169
3031	serge	2170	/* prime dma-buf support */
		2171	void *dma_buf_vmapping;
		2172	int vmapping_count;
		2173
6084	serge	2174	/** Breadcrumb of last rendering to the buffer.
		2175	* There can only be one writer, but we allow for multiple readers.
		2176	* If there is a writer that necessarily implies that all other
		2177	* read requests are complete - but we may only be lazily clearing
		2178	* the read requests. A read request is naturally the most recent
		2179	* request on a ring, so we may have two different write and read
		2180	* requests on one ring where the write request is older than the
		2181	* read request. This allows for the CPU to read from an active
		2182	* buffer by only waiting for the write to complete.
		2183	* */
		2184	struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
		2185	struct drm_i915_gem_request *last_write_req;
		2186	/** Breadcrumb of last fenced GPU access to the buffer. */
		2187	struct drm_i915_gem_request *last_fenced_req;
3031	serge	2188
6084	serge	2189	/** Current tiling stride for the object, if it's tiled. */
		2190	uint32_t stride;
2327	Serge	2191
4560	Serge	2192	/** References from framebuffers, locks out tiling changes. */
		2193	unsigned long framebuffer_references;
		2194
6084	serge	2195	/** Record of address bit 17 of each page at last unbind. */
		2196	unsigned long *bit_17;
2327	Serge	2197
6937	serge	2198	union {
		2199	/** for phy allocated objects */
		2200	struct drm_dma_handle *phys_handle;
		2201
5060	serge	2202	struct i915_gem_userptr {
		2203	uintptr_t ptr;
		2204	unsigned read_only :1;
		2205	unsigned workers :4;
		2206	#define I915_GEM_USERPTR_MAX_WORKERS 15
		2207
5128	serge	2208	struct i915_mm_struct *mm;
		2209	struct i915_mmu_object *mmu_object;
5060	serge	2210	struct work_struct *work;
		2211	} userptr;
6937	serge	2212	};
2327	Serge	2213	};
2325	Serge	2214	#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
		2215
5060	serge	2216	void i915_gem_track_fb(struct drm_i915_gem_object *old,
		2217	struct drm_i915_gem_object *new,
		2218	unsigned frontbuffer_bits);
		2219
2325	Serge	2220	/**
		2221	* Request queue structure.
		2222	*
		2223	* The request queue allows us to note sequence numbers that have been emitted
		2224	* and may be associated with active buffers to be retired.
		2225	*
6084	serge	2226	* By keeping this list, we can avoid having to do questionable sequence
		2227	* number comparisons on buffer last_read\|write_seqno. It also allows an
		2228	* emission time to be associated with the request for tracking how far ahead
		2229	* of the GPU the submission is.
		2230	*
		2231	* The requests are reference counted, so upon creation they should have an
		2232	* initial reference taken using kref_init
2325	Serge	2233	*/
		2234	struct drm_i915_gem_request {
6084	serge	2235	struct kref ref;
		2236
2325	Serge	2237	/** On Which ring this request was generated */
6084	serge	2238	struct drm_i915_private *i915;
5060	serge	2239	struct intel_engine_cs *ring;
2325	Serge	2240
6084	serge	2241	/** GEM sequence number associated with the previous request,
		2242	* when the HWS breadcrumb is equal to this the GPU is processing
		2243	* this request.
		2244	*/
		2245	u32 previous_seqno;
2325	Serge	2246
6084	serge	2247	/** GEM sequence number associated with this request,
		2248	* when the HWS breadcrumb is equal or greater than this the GPU
		2249	* has finished processing this request.
		2250	*/
		2251	u32 seqno;
		2252
4104	Serge	2253	/** Position in the ringbuffer of the start of the request */
		2254	u32 head;
		2255
6084	serge	2256	/**
		2257	* Position in the ringbuffer of the start of the postfix.
		2258	* This is required to calculate the maximum available ringbuffer
		2259	* space without overwriting the postfix.
		2260	*/
		2261	u32 postfix;
		2262
		2263	/** Position in the ringbuffer of the end of the whole request */
3031	serge	2264	u32 tail;
		2265
6084	serge	2266	/**
		2267	* Context and ring buffer related to this request
		2268	* Contexts are refcounted, so when this request is associated with a
		2269	* context, we must increment the context's refcount, to guarantee that
		2270	* it persists while any request is linked to it. Requests themselves
		2271	* are also refcounted, so the request will only be freed when the last
		2272	* reference to it is dismissed, and the code in
		2273	* i915_gem_request_free() will then decrement the refcount on the
		2274	* context.
		2275	*/
5060	serge	2276	struct intel_context *ctx;
6084	serge	2277	struct intel_ringbuffer *ringbuf;
4104	Serge	2278
6084	serge	2279	/** Batch buffer related to this request if any (used for
		2280	error state dump only) */
4104	Serge	2281	struct drm_i915_gem_object *batch_obj;
		2282
2325	Serge	2283	/** Time at which this request was emitted, in jiffies. */
		2284	unsigned long emitted_jiffies;
		2285
		2286	/** global list entry for this request */
		2287	struct list_head list;
		2288
		2289	struct drm_i915_file_private *file_priv;
		2290	/** file_priv list entry for this request */
		2291	struct list_head client_list;
		2292
6084	serge	2293	/** process identifier submitting this request */
		2294	struct pid *pid;
4560	Serge	2295
6084	serge	2296	/**
		2297	* The ELSP only accepts two elements at a time, so we queue
		2298	* context/tail pairs on a given queue (ring->execlist_queue) until the
		2299	* hardware is available. The queue serves a double purpose: we also use
		2300	* it to keep track of the up to 2 contexts currently in the hardware
		2301	* (usually one in execution and the other queued up by the GPU): We
		2302	* only remove elements from the head of the queue when the hardware
		2303	* informs us that an element has been completed.
		2304	*
		2305	* All accesses to the queue are mediated by a spinlock
		2306	* (ring->execlist_lock).
		2307	*/
4104	Serge	2308
6084	serge	2309	/** Execlist link in the submission queue.*/
		2310	struct list_head execlist_link;
		2311
		2312	/** Execlists no. of times this request has been sent to the ELSP */
		2313	int elsp_submitted;
		2314
2325	Serge	2315	};
		2316
7144	serge	2317	struct drm_i915_gem_request * __must_check
		2318	i915_gem_request_alloc(struct intel_engine_cs *engine,
		2319	struct intel_context *ctx);
6084	serge	2320	void i915_gem_request_cancel(struct drm_i915_gem_request *req);
		2321	void i915_gem_request_free(struct kref *req_ref);
		2322	int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
		2323	struct drm_file *file);
		2324
		2325	static inline uint32_t
		2326	i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
		2327	{
		2328	return req ? req->seqno : 0;
		2329	}
		2330
		2331	static inline struct intel_engine_cs *
		2332	i915_gem_request_get_ring(struct drm_i915_gem_request *req)
		2333	{
		2334	return req ? req->ring : NULL;
		2335	}
		2336
		2337	static inline struct drm_i915_gem_request *
		2338	i915_gem_request_reference(struct drm_i915_gem_request *req)
		2339	{
		2340	if (req)
		2341	kref_get(&req->ref);
		2342	return req;
		2343	}
		2344
		2345	static inline void
		2346	i915_gem_request_unreference(struct drm_i915_gem_request *req)
		2347	{
		2348	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
		2349	kref_put(&req->ref, i915_gem_request_free);
		2350	}
		2351
		2352	static inline void
		2353	i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
		2354	{
		2355	struct drm_device *dev;
		2356
		2357	if (!req)
		2358	return;
		2359
		2360	dev = req->ring->dev;
		2361	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
		2362	mutex_unlock(&dev->struct_mutex);
		2363	}
		2364
		2365	static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
		2366	struct drm_i915_gem_request *src)
		2367	{
		2368	if (src)
		2369	i915_gem_request_reference(src);
		2370
		2371	if (*pdst)
		2372	i915_gem_request_unreference(*pdst);
		2373
		2374	*pdst = src;
		2375	}
		2376
5060	serge	2377	/*
6084	serge	2378	* XXX: i915_gem_request_completed should be here but currently needs the
		2379	* definition of i915_seqno_passed() which is below. It will be moved in
		2380	* a later patch when the call to i915_seqno_passed() is obsoleted...
		2381	*/
		2382
		2383	/*
5060	serge	2384	* A command that requires special handling by the command parser.
		2385	*/
		2386	struct drm_i915_cmd_descriptor {
		2387	/*
		2388	* Flags describing how the command parser processes the command.
		2389	*
		2390	* CMD_DESC_FIXED: The command has a fixed length if this is set,
		2391	* a length mask if not set
		2392	* CMD_DESC_SKIP: The command is allowed but does not follow the
		2393	* standard length encoding for the opcode range in
		2394	* which it falls
		2395	* CMD_DESC_REJECT: The command is never allowed
		2396	* CMD_DESC_REGISTER: The command should be checked against the
		2397	* register whitelist for the appropriate ring
		2398	* CMD_DESC_MASTER: The command is allowed if the submitting process
		2399	* is the DRM master
		2400	*/
		2401	u32 flags;
		2402	#define CMD_DESC_FIXED (1<<0)
		2403	#define CMD_DESC_SKIP (1<<1)
		2404	#define CMD_DESC_REJECT (1<<2)
		2405	#define CMD_DESC_REGISTER (1<<3)
		2406	#define CMD_DESC_BITMASK (1<<4)
		2407	#define CMD_DESC_MASTER (1<<5)
2325	Serge	2408
5060	serge	2409	/*
		2410	* The command's unique identification bits and the bitmask to get them.
		2411	* This isn't strictly the opcode field as defined in the spec and may
		2412	* also include type, subtype, and/or subop fields.
		2413	*/
		2414	struct {
		2415	u32 value;
		2416	u32 mask;
		2417	} cmd;
		2418
		2419	/*
		2420	* The command's length. The command is either fixed length (i.e. does
		2421	* not include a length field) or has a length field mask. The flag
		2422	* CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
		2423	* a length mask. All command entries in a command table must include
		2424	* length information.
		2425	*/
		2426	union {
		2427	u32 fixed;
		2428	u32 mask;
		2429	} length;
		2430
		2431	/*
		2432	* Describes where to find a register address in the command to check
		2433	* against the ring's register whitelist. Only valid if flags has the
		2434	* CMD_DESC_REGISTER bit set.
6084	serge	2435	*
		2436	* A non-zero step value implies that the command may access multiple
		2437	* registers in sequence (e.g. LRI), in that case step gives the
		2438	* distance in dwords between individual offset fields.
5060	serge	2439	*/
		2440	struct {
		2441	u32 offset;
		2442	u32 mask;
6084	serge	2443	u32 step;
5060	serge	2444	} reg;
		2445
		2446	#define MAX_CMD_DESC_BITMASKS 3
		2447	/*
		2448	* Describes command checks where a particular dword is masked and
		2449	* compared against an expected value. If the command does not match
		2450	* the expected value, the parser rejects it. Only valid if flags has
		2451	* the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
		2452	* are valid.
		2453	*
		2454	* If the check specifies a non-zero condition_mask then the parser
		2455	* only performs the check when the bits specified by condition_mask
		2456	* are non-zero.
		2457	*/
		2458	struct {
		2459	u32 offset;
		2460	u32 mask;
		2461	u32 expected;
		2462	u32 condition_offset;
		2463	u32 condition_mask;
		2464	} bits[MAX_CMD_DESC_BITMASKS];
		2465	};
		2466
		2467	/*
		2468	* A table of commands requiring special handling by the command parser.
		2469	*
		2470	* Each ring has an array of tables. Each table consists of an array of command
		2471	* descriptors, which must be sorted with command opcodes in ascending order.
		2472	*/
		2473	struct drm_i915_cmd_table {
		2474	const struct drm_i915_cmd_descriptor *table;
		2475	int count;
		2476	};
		2477
5354	serge	2478	/* Note that the (struct drm_i915_private ) cast is just to shut up gcc. /
		2479	#define __I915__(p) ({ \
		2480	struct drm_i915_private *__p; \
		2481	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		2482	__p = (struct drm_i915_private *)p; \
		2483	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		2484	__p = to_i915((struct drm_device *)p); \
		2485	else \
		2486	BUILD_BUG(); \
		2487	__p; \
		2488	})
		2489	#define INTEL_INFO(p) (&__I915__(p)->info)
		2490	#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
6084	serge	2491	#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
5060	serge	2492
6937	serge	2493	#define REVID_FOREVER 0xff
		2494	/*
		2495	* Return true if revision is in range [since,until] inclusive.
		2496	*
		2497	* Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
		2498	*/
		2499	#define IS_REVID(p, since, until) \
		2500	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
		2501
5354	serge	2502	#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
		2503	#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2325	Serge	2504	#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
5354	serge	2505	#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2325	Serge	2506	#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
5354	serge	2507	#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
		2508	#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2325	Serge	2509	#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
		2510	#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
		2511	#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
5354	serge	2512	#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2325	Serge	2513	#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
5354	serge	2514	#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
		2515	#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2325	Serge	2516	#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
		2517	#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
5354	serge	2518	#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2325	Serge	2519	#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
5354	serge	2520	#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 \|\| \
		2521	INTEL_DEVID(dev) == 0x0152 \|\| \
		2522	INTEL_DEVID(dev) == 0x015a)
3031	serge	2523	#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
6937	serge	2524	#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
3031	serge	2525	#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
6937	serge	2526	#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
5354	serge	2527	#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
6937	serge	2528	#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
		2529	#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2325	Serge	2530	#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
4104	Serge	2531	#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
5354	serge	2532	(INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
4560	Serge	2533	#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
6084	serge	2534	((INTEL_DEVID(dev) & 0xf) == 0x6 \|\| \
		2535	(INTEL_DEVID(dev) & 0xf) == 0xb \|\| \
5354	serge	2536	(INTEL_DEVID(dev) & 0xf) == 0xe))
6084	serge	2537	/* ULX machines are also considered ULT. */
		2538	#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
		2539	(INTEL_DEVID(dev) & 0xf) == 0xe)
5354	serge	2540	#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
		2541	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
4560	Serge	2542	#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
5354	serge	2543	(INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
4560	Serge	2544	#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
5354	serge	2545	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
5060	serge	2546	/* ULX machines are also considered ULT. */
5354	serge	2547	#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E \|\| \
		2548	INTEL_DEVID(dev) == 0x0A1E)
6084	serge	2549	#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 \|\| \
		2550	INTEL_DEVID(dev) == 0x1913 \|\| \
		2551	INTEL_DEVID(dev) == 0x1916 \|\| \
		2552	INTEL_DEVID(dev) == 0x1921 \|\| \
		2553	INTEL_DEVID(dev) == 0x1926)
		2554	#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E \|\| \
		2555	INTEL_DEVID(dev) == 0x1915 \|\| \
		2556	INTEL_DEVID(dev) == 0x191E)
6937	serge	2557	#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 \|\| \
		2558	INTEL_DEVID(dev) == 0x5913 \|\| \
		2559	INTEL_DEVID(dev) == 0x5916 \|\| \
		2560	INTEL_DEVID(dev) == 0x5921 \|\| \
		2561	INTEL_DEVID(dev) == 0x5926)
		2562	#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E \|\| \
		2563	INTEL_DEVID(dev) == 0x5915 \|\| \
		2564	INTEL_DEVID(dev) == 0x591E)
6084	serge	2565	#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
		2566	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
		2567	#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
		2568	(INTEL_DEVID(dev) & 0x00F0) == 0x0030)
		2569
4560	Serge	2570	#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2325	Serge	2571
6937	serge	2572	#define SKL_REVID_A0 0x0
		2573	#define SKL_REVID_B0 0x1
		2574	#define SKL_REVID_C0 0x2
		2575	#define SKL_REVID_D0 0x3
		2576	#define SKL_REVID_E0 0x4
		2577	#define SKL_REVID_F0 0x5
6084	serge	2578
6937	serge	2579	#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
6084	serge	2580
6937	serge	2581	#define BXT_REVID_A0 0x0
		2582	#define BXT_REVID_A1 0x1
		2583	#define BXT_REVID_B0 0x3
		2584	#define BXT_REVID_C0 0x9
		2585
		2586	#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
		2587
2325	Serge	2588	/*
		2589	* The genX designation typically refers to the render engine, so render
		2590	* capability related checks should use IS_GEN, while display and other checks
		2591	* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
		2592	* chips, etc.).
		2593	*/
		2594	#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
		2595	#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
		2596	#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
		2597	#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
		2598	#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
		2599	#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
4560	Serge	2600	#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
5354	serge	2601	#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2325	Serge	2602
4560	Serge	2603	#define RENDER_RING (1<
		2604	#define BSD_RING (1<
		2605	#define BLT_RING (1<
		2606	#define VEBOX_RING (1<
5060	serge	2607	#define BSD2_RING (1<
6084	serge	2608	#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
5060	serge	2609	#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
6084	serge	2610	#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
		2611	#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
		2612	#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
5060	serge	2613	#define HAS_WT(dev) ((IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) && \
5354	serge	2614	__I915__(dev)->ellc_size)
2325	Serge	2615	#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
		2616
3031	serge	2617	#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
5354	serge	2618	#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
		2619	#define USES_PPGTT(dev) (i915.enable_ppgtt)
6084	serge	2620	#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
		2621	#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
3031	serge	2622
2325	Serge	2623	#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
		2624	#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
		2625
3243	Serge	2626	/* Early gen2 have a totally busted CS tlb and require pinned batches. */
		2627	#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) \|\| IS_845G(dev))
7144	serge	2628
		2629	/* WaRsDisableCoarsePowerGating:skl,bxt */
		2630	#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) \|\| \
		2631	IS_SKL_GT3(dev) \|\| \
		2632	IS_SKL_GT4(dev))
		2633
5060	serge	2634	/*
		2635	* dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
		2636	* even when in MSI mode. This results in spurious interrupt warnings if the
		2637	* legacy irq no. is shared with another device. The kernel then disables that
		2638	* interrupt source and so prevents the other device from working properly.
		2639	*/
		2640	#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
		2641	#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
3243	Serge	2642
2325	Serge	2643	/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
		2644	* rows, which changed the alignment requirements and fence programming.
		2645	*/
		2646	#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) \|\| \
		2647	IS_I915GM(dev)))
		2648	#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
		2649	#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
		2650
		2651	#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
		2652	#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
4560	Serge	2653	#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2325	Serge	2654
5354	serge	2655	#define HAS_IPS(dev) (IS_HSW_ULT(dev) \|\| IS_BROADWELL(dev))
2325	Serge	2656
6084	serge	2657	#define HAS_DP_MST(dev) (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| \
		2658	INTEL_INFO(dev)->gen >= 9)
		2659
4104	Serge	2660	#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
		2661	#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
6084	serge	2662	#define HAS_PSR(dev) (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| \
		2663	IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev) \|\| \
6937	serge	2664	IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
5060	serge	2665	#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) \|\| IS_HASWELL(dev) \|\| \
6084	serge	2666	IS_BROADWELL(dev) \|\| IS_VALLEYVIEW(dev) \|\| \
6937	serge	2667	IS_CHERRYVIEW(dev) \|\| IS_SKYLAKE(dev) \|\| \
		2668	IS_KABYLAKE(dev))
5354	serge	2669	#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
		2670	#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 \|\| IS_IVYBRIDGE(dev))
3480	Serge	2671
6084	serge	2672	#define HAS_CSR(dev) (IS_GEN9(dev))
		2673
6937	serge	2674	#define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
		2675	#define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
6084	serge	2676
		2677	#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) \|\| \
		2678	INTEL_INFO(dev)->gen >= 8)
		2679
		2680	#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
6937	serge	2681	!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
		2682	!IS_BROXTON(dev))
6084	serge	2683
3243	Serge	2684	#define INTEL_PCH_DEVICE_ID_MASK 0xff00
		2685	#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
		2686	#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
		2687	#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
		2688	#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
		2689	#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
5354	serge	2690	#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
		2691	#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
6084	serge	2692	#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
6320	serge	2693	#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3243	Serge	2694
5354	serge	2695	#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
		2696	#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
3031	serge	2697	#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
6084	serge	2698	#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6937	serge	2699	#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2325	Serge	2700	#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
		2701	#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
3746	Serge	2702	#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
3031	serge	2703	#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2325	Serge	2704
6937	serge	2705	#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 \|\| \
		2706	IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev))
5060	serge	2707
4560	Serge	2708	/* DPF == dynamic parity feature */
		2709	#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		2710	#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2325	Serge	2711
3031	serge	2712	#define GT_FREQUENCY_MULTIPLIER 50
6084	serge	2713	#define GEN9_FREQ_SCALER 3
3031	serge	2714
		2715	#include "i915_trace.h"
		2716
6084	serge	2717	extern const struct drm_ioctl_desc i915_ioctls[];
		2718	extern int i915_max_ioctl;
3031	serge	2719
6660	serge	2720	extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
6084	serge	2721	extern int i915_resume_switcheroo(struct drm_device *dev);
2325	Serge	2722
7144	serge	2723	/* i915_dma.c */
2325	Serge	2724	extern int i915_driver_load(struct drm_device *, unsigned long flags);
		2725	extern int i915_driver_unload(struct drm_device *);
5060	serge	2726	extern int i915_driver_open(struct drm_device dev, struct drm_file file);
2325	Serge	2727	extern void i915_driver_lastclose(struct drm_device * dev);
		2728	extern void i915_driver_preclose(struct drm_device *dev,
5060	serge	2729	struct drm_file *file);
2325	Serge	2730	extern void i915_driver_postclose(struct drm_device *dev,
5060	serge	2731	struct drm_file *file);
3031	serge	2732	#ifdef CONFIG_COMPAT
2325	Serge	2733	extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
		2734	unsigned long arg);
3031	serge	2735	#endif
		2736	extern int intel_gpu_reset(struct drm_device *dev);
6084	serge	2737	extern bool intel_has_gpu_reset(struct drm_device *dev);
3031	serge	2738	extern int i915_reset(struct drm_device *dev);
2325	Serge	2739	extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
		2740	extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
		2741	extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
		2742	extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
5060	serge	2743	int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
6084	serge	2744
		2745	/* intel_hotplug.c */
		2746	void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
		2747	void intel_hpd_init(struct drm_i915_private *dev_priv);
		2748	void intel_hpd_init_work(struct drm_i915_private *dev_priv);
5060	serge	2749	void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
6084	serge	2750	bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2325	Serge	2751
		2752	/* i915_irq.c */
4104	Serge	2753	void i915_queue_hangcheck(struct drm_device *dev);
5060	serge	2754	__printf(3, 4)
		2755	void i915_handle_error(struct drm_device *dev, bool wedged,
		2756	const char *fmt, ...);
2325	Serge	2757
5354	serge	2758	extern void intel_irq_init(struct drm_i915_private *dev_priv);
		2759	int intel_irq_install(struct drm_i915_private *dev_priv);
		2760	void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2325	Serge	2761
4104	Serge	2762	extern void intel_uncore_sanitize(struct drm_device *dev);
5060	serge	2763	extern void intel_uncore_early_sanitize(struct drm_device *dev,
		2764	bool restore_forcewake);
4104	Serge	2765	extern void intel_uncore_init(struct drm_device *dev);
7144	serge	2766	extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
		2767	extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
4560	Serge	2768	extern void intel_uncore_fini(struct drm_device *dev);
5060	serge	2769	extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
6084	serge	2770	const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
		2771	void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
		2772	enum forcewake_domains domains);
		2773	void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
		2774	enum forcewake_domains domains);
		2775	/* Like above but the caller must manage the uncore.lock itself.
		2776	* Must be used with I915_READ_FW and friends.
		2777	*/
		2778	void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
		2779	enum forcewake_domains domains);
		2780	void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
		2781	enum forcewake_domains domains);
		2782	void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
		2783	static inline bool intel_vgpu_active(struct drm_device *dev)
		2784	{
		2785	return to_i915(dev)->vgpu.active;
		2786	}
2325	Serge	2787
		2788	void
5060	serge	2789	i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		2790	u32 status_mask);
2325	Serge	2791
		2792	void
5060	serge	2793	i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		2794	u32 status_mask);
2325	Serge	2795
5060	serge	2796	void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
		2797	void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
6084	serge	2798	void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
		2799	uint32_t mask,
		2800	uint32_t bits);
6937	serge	2801	void ilk_update_display_irq(struct drm_i915_private *dev_priv,
		2802	uint32_t interrupt_mask,
		2803	uint32_t enabled_irq_mask);
		2804	static inline void
		2805	ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
		2806	{
		2807	ilk_update_display_irq(dev_priv, bits, bits);
		2808	}
		2809	static inline void
		2810	ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
		2811	{
		2812	ilk_update_display_irq(dev_priv, bits, 0);
		2813	}
		2814	void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
		2815	enum pipe pipe,
		2816	uint32_t interrupt_mask,
		2817	uint32_t enabled_irq_mask);
		2818	static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
		2819	enum pipe pipe, uint32_t bits)
		2820	{
		2821	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
		2822	}
		2823	static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
		2824	enum pipe pipe, uint32_t bits)
		2825	{
		2826	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
		2827	}
5354	serge	2828	void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
		2829	uint32_t interrupt_mask,
		2830	uint32_t enabled_irq_mask);
6937	serge	2831	static inline void
		2832	ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
		2833	{
		2834	ibx_display_interrupt_update(dev_priv, bits, bits);
		2835	}
		2836	static inline void
		2837	ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
		2838	{
		2839	ibx_display_interrupt_update(dev_priv, bits, 0);
		2840	}
5060	serge	2841
6937	serge	2842
2325	Serge	2843	/* i915_gem.c */
		2844	int i915_gem_create_ioctl(struct drm_device dev, void data,
		2845	struct drm_file *file_priv);
		2846	int i915_gem_pread_ioctl(struct drm_device dev, void data,
		2847	struct drm_file *file_priv);
		2848	int i915_gem_pwrite_ioctl(struct drm_device dev, void data,
		2849	struct drm_file *file_priv);
		2850	int i915_gem_mmap_ioctl(struct drm_device dev, void data,
		2851	struct drm_file *file_priv);
		2852	int i915_gem_mmap_gtt_ioctl(struct drm_device dev, void data,
		2853	struct drm_file *file_priv);
		2854	int i915_gem_set_domain_ioctl(struct drm_device dev, void data,
		2855	struct drm_file *file_priv);
		2856	int i915_gem_sw_finish_ioctl(struct drm_device dev, void data,
		2857	struct drm_file *file_priv);
5354	serge	2858	void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
6084	serge	2859	struct drm_i915_gem_request *req);
		2860	void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
		2861	int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
5354	serge	2862	struct drm_i915_gem_execbuffer2 *args,
6084	serge	2863	struct list_head *vmas);
2325	Serge	2864	int i915_gem_execbuffer(struct drm_device dev, void data,
		2865	struct drm_file *file_priv);
		2866	int i915_gem_execbuffer2(struct drm_device dev, void data,
		2867	struct drm_file *file_priv);
		2868	int i915_gem_busy_ioctl(struct drm_device dev, void data,
		2869	struct drm_file *file_priv);
3031	serge	2870	int i915_gem_get_caching_ioctl(struct drm_device dev, void data,
		2871	struct drm_file *file);
		2872	int i915_gem_set_caching_ioctl(struct drm_device dev, void data,
		2873	struct drm_file *file);
2325	Serge	2874	int i915_gem_throttle_ioctl(struct drm_device dev, void data,
		2875	struct drm_file *file_priv);
		2876	int i915_gem_madvise_ioctl(struct drm_device dev, void data,
		2877	struct drm_file *file_priv);
		2878	int i915_gem_set_tiling(struct drm_device dev, void data,
		2879	struct drm_file *file_priv);
		2880	int i915_gem_get_tiling(struct drm_device dev, void data,
		2881	struct drm_file *file_priv);
5060	serge	2882	int i915_gem_init_userptr(struct drm_device *dev);
		2883	int i915_gem_userptr_ioctl(struct drm_device dev, void data,
		2884	struct drm_file *file);
2325	Serge	2885	int i915_gem_get_aperture_ioctl(struct drm_device dev, void data,
		2886	struct drm_file *file_priv);
3031	serge	2887	int i915_gem_wait_ioctl(struct drm_device dev, void data,
		2888	struct drm_file *file_priv);
7144	serge	2889	void i915_gem_load_init(struct drm_device *dev);
		2890	void i915_gem_load_cleanup(struct drm_device *dev);
3480	Serge	2891	void i915_gem_object_alloc(struct drm_device dev);
		2892	void i915_gem_object_free(struct drm_i915_gem_object *obj);
3031	serge	2893	void i915_gem_object_init(struct drm_i915_gem_object *obj,
		2894	const struct drm_i915_gem_object_ops *ops);
2325	Serge	2895	struct drm_i915_gem_object i915_gem_alloc_object(struct drm_device dev,
		2896	size_t size);
6084	serge	2897	struct drm_i915_gem_object *i915_gem_object_create_from_data(
		2898	struct drm_device dev, const void data, size_t size);
2325	Serge	2899	void i915_gem_free_object(struct drm_gem_object *obj);
4104	Serge	2900	void i915_gem_vma_destroy(struct i915_vma *vma);
3480	Serge	2901
6084	serge	2902	/* Flags used by pin/bind&friends. */
		2903	#define PIN_MAPPABLE (1<<0)
		2904	#define PIN_NONBLOCK (1<<1)
		2905	#define PIN_GLOBAL (1<<2)
		2906	#define PIN_OFFSET_BIAS (1<<3)
		2907	#define PIN_USER (1<<4)
		2908	#define PIN_UPDATE (1<<5)
		2909	#define PIN_ZONE_4G (1<<6)
		2910	#define PIN_HIGH (1<<7)
6937	serge	2911	#define PIN_OFFSET_FIXED (1<<8)
5060	serge	2912	#define PIN_OFFSET_MASK (~4095)
6084	serge	2913	int __must_check
		2914	i915_gem_object_pin(struct drm_i915_gem_object *obj,
		2915	struct i915_address_space *vm,
		2916	uint32_t alignment,
		2917	uint64_t flags);
		2918	int __must_check
		2919	i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
		2920	const struct i915_ggtt_view *view,
		2921	uint32_t alignment,
		2922	uint64_t flags);
		2923
		2924	int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		2925	u32 flags);
		2926	void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
4104	Serge	2927	int __must_check i915_vma_unbind(struct i915_vma *vma);
6084	serge	2928	/*
		2929	* BEWARE: Do not use the function below unless you can _absolutely_
		2930	* _guarantee_ VMA in question is _not in use_ anywhere.
		2931	*/
		2932	int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3480	Serge	2933	int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
4560	Serge	2934	void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2325	Serge	2935	void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
		2936
5060	serge	2937	int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
		2938	int *needs_clflush);
		2939
3031	serge	2940	int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
6084	serge	2941
		2942	static inline int __sg_page_count(struct scatterlist *sg)
3031	serge	2943	{
6084	serge	2944	return sg->length >> PAGE_SHIFT;
		2945	}
3031	serge	2946
6937	serge	2947	struct page *
		2948	i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
		2949
6084	serge	2950	static inline struct page *
		2951	i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
		2952	{
		2953	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		2954	return NULL;
3746	Serge	2955
6084	serge	2956	if (n < obj->get_page.last) {
		2957	obj->get_page.sg = obj->pages->sgl;
		2958	obj->get_page.last = 0;
		2959	}
		2960
		2961	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		2962	obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		2963	if (unlikely(sg_is_chain(obj->get_page.sg)))
		2964	obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
		2965	}
		2966
		2967	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3243	Serge	2968	}
6084	serge	2969
3031	serge	2970	static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
		2971	{
3243	Serge	2972	BUG_ON(obj->pages == NULL);
3031	serge	2973	obj->pages_pin_count++;
		2974	}
		2975	static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
		2976	{
		2977	BUG_ON(obj->pages_pin_count == 0);
		2978	obj->pages_pin_count--;
		2979	}
		2980
2325	Serge	2981	int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3031	serge	2982	int i915_gem_object_sync(struct drm_i915_gem_object *obj,
6084	serge	2983	struct intel_engine_cs *to,
		2984	struct drm_i915_gem_request **to_req);
4560	Serge	2985	void i915_vma_move_to_active(struct i915_vma *vma,
6084	serge	2986	struct drm_i915_gem_request *req);
2325	Serge	2987	int i915_gem_dumb_create(struct drm_file *file_priv,
		2988	struct drm_device *dev,
		2989	struct drm_mode_create_dumb *args);
		2990	int i915_gem_mmap_gtt(struct drm_file file_priv, struct drm_device dev,
		2991	uint32_t handle, uint64_t *offset);
		2992	/**
		2993	* Returns true if seq1 is later than seq2.
		2994	*/
2340	Serge	2995	static inline bool
		2996	i915_seqno_passed(uint32_t seq1, uint32_t seq2)
		2997	{
		2998	return (int32_t)(seq1 - seq2) >= 0;
		2999	}
2325	Serge	3000
6084	serge	3001	static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
		3002	bool lazy_coherency)
		3003	{
		3004	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
		3005	return i915_seqno_passed(seqno, req->previous_seqno);
		3006	}
		3007
		3008	static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
		3009	bool lazy_coherency)
		3010	{
		3011	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
		3012	return i915_seqno_passed(seqno, req->seqno);
		3013	}
		3014
3480	Serge	3015	int __must_check i915_gem_get_seqno(struct drm_device dev, u32 seqno);
		3016	int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3031	serge	3017
5060	serge	3018	struct drm_i915_gem_request *
		3019	i915_gem_find_active_request(struct intel_engine_cs *ring);
2332	Serge	3020
4560	Serge	3021	bool i915_gem_retire_requests(struct drm_device *dev);
5060	serge	3022	void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3480	Serge	3023	int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3031	serge	3024	bool interruptible);
5060	serge	3025
3480	Serge	3026	static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
		3027	{
		3028	return unlikely(atomic_read(&error->reset_counter)
4560	Serge	3029	& (I915_RESET_IN_PROGRESS_FLAG \| I915_WEDGED));
3480	Serge	3030	}
3031	serge	3031
3480	Serge	3032	static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
		3033	{
4560	Serge	3034	return atomic_read(&error->reset_counter) & I915_WEDGED;
3480	Serge	3035	}
		3036
4560	Serge	3037	static inline u32 i915_reset_count(struct i915_gpu_error *error)
		3038	{
		3039	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
		3040	}
		3041
5060	serge	3042	static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
		3043	{
		3044	return dev_priv->gpu_error.stop_rings == 0 \|\|
		3045	dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
		3046	}
		3047
		3048	static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
		3049	{
		3050	return dev_priv->gpu_error.stop_rings == 0 \|\|
		3051	dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
		3052	}
		3053
2325	Serge	3054	void i915_gem_reset(struct drm_device *dev);
4104	Serge	3055	bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3031	serge	3056	int __must_check i915_gem_init(struct drm_device *dev);
5354	serge	3057	int i915_gem_init_rings(struct drm_device *dev);
3031	serge	3058	int __must_check i915_gem_init_hw(struct drm_device *dev);
6084	serge	3059	int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3031	serge	3060	void i915_gem_init_swizzling(struct drm_device *dev);
2325	Serge	3061	void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
		3062	int __must_check i915_gpu_idle(struct drm_device *dev);
4560	Serge	3063	int __must_check i915_gem_suspend(struct drm_device *dev);
6084	serge	3064	void __i915_add_request(struct drm_i915_gem_request *req,
		3065	struct drm_i915_gem_object *batch_obj,
		3066	bool flush_caches);
		3067	#define i915_add_request(req) \
		3068	__i915_add_request(req, NULL, true)
		3069	#define i915_add_request_no_flush(req) \
		3070	__i915_add_request(req, NULL, false)
		3071	int __i915_wait_request(struct drm_i915_gem_request *req,
5354	serge	3072	unsigned reset_counter,
		3073	bool interruptible,
		3074	s64 *timeout,
6084	serge	3075	struct intel_rps_client *rps);
		3076	int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2325	Serge	3077	int i915_gem_fault(struct vm_area_struct vma, struct vm_fault vmf);
		3078	int __must_check
6084	serge	3079	i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
		3080	bool readonly);
		3081	int __must_check
2325	Serge	3082	i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
		3083	bool write);
		3084	int __must_check
3031	serge	3085	i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
		3086	int __must_check
2325	Serge	3087	i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
		3088	u32 alignment,
6084	serge	3089	const struct i915_ggtt_view *view);
		3090	void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
		3091	const struct i915_ggtt_view *view);
5060	serge	3092	int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2325	Serge	3093	int align);
4560	Serge	3094	int i915_gem_open(struct drm_device dev, struct drm_file file);
2325	Serge	3095	void i915_gem_release(struct drm_device dev, struct drm_file file);
		3096
		3097	uint32_t
3480	Serge	3098	i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
		3099	uint32_t
		3100	i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
		3101	int tiling_mode, bool fenced);
2325	Serge	3102
		3103	int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
		3104	enum i915_cache_level cache_level);
		3105
4104	Serge	3106	struct drm_gem_object i915_gem_prime_import(struct drm_device dev,
		3107	struct dma_buf *dma_buf);
3031	serge	3108
		3109	struct dma_buf i915_gem_prime_export(struct drm_device dev,
		3110	struct drm_gem_object *gem_obj, int flags);
		3111
6084	serge	3112	u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
		3113	const struct i915_ggtt_view *view);
		3114	u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
		3115	struct i915_address_space *vm);
		3116	static inline u64
		3117	i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
		3118	{
		3119	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
		3120	}
3746	Serge	3121
4104	Serge	3122	bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
6084	serge	3123	bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
		3124	const struct i915_ggtt_view *view);
4104	Serge	3125	bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
		3126	struct i915_address_space *vm);
6084	serge	3127
4104	Serge	3128	unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
		3129	struct i915_address_space *vm);
		3130	struct i915_vma *
6084	serge	3131	i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		3132	struct i915_address_space *vm);
		3133	struct i915_vma *
		3134	i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
		3135	const struct i915_ggtt_view *view);
		3136
		3137	struct i915_vma *
4104	Serge	3138	i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
		3139	struct i915_address_space *vm);
6084	serge	3140	struct i915_vma *
		3141	i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
		3142	const struct i915_ggtt_view *view);
4560	Serge	3143
6084	serge	3144	static inline struct i915_vma *
		3145	i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
		3146	{
		3147	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
5060	serge	3148	}
6084	serge	3149	bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
4560	Serge	3150
4104	Serge	3151	/* Some GGTT VM helpers */
5354	serge	3152	#define i915_obj_to_ggtt(obj) \
4104	Serge	3153	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
		3154
5354	serge	3155	static inline struct i915_hw_ppgtt *
		3156	i915_vm_to_ppgtt(struct i915_address_space *vm)
		3157	{
		3158	WARN_ON(i915_is_ggtt(vm));
		3159	return container_of(vm, struct i915_hw_ppgtt, base);
		3160	}
		3161
		3162
4104	Serge	3163	static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
		3164	{
6084	serge	3165	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
4104	Serge	3166	}
		3167
		3168	static inline unsigned long
		3169	i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
		3170	{
5354	serge	3171	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
4104	Serge	3172	}
		3173
		3174	static inline int __must_check
		3175	i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		3176	uint32_t alignment,
5060	serge	3177	unsigned flags)
4104	Serge	3178	{
5354	serge	3179	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
		3180	alignment, flags \| PIN_GLOBAL);
4104	Serge	3181	}
		3182
5060	serge	3183	static inline int
		3184	i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
		3185	{
		3186	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
		3187	}
		3188
6084	serge	3189	void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
		3190	const struct i915_ggtt_view *view);
		3191	static inline void
		3192	i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
		3193	{
		3194	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
		3195	}
5060	serge	3196
6084	serge	3197	/* i915_gem_fence.c */
		3198	int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
		3199	int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
		3200
		3201	bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
		3202	void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
		3203
		3204	void i915_gem_restore_fences(struct drm_device *dev);
		3205
		3206	void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
		3207	void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
		3208	void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
		3209
3031	serge	3210	/* i915_gem_context.c */
4560	Serge	3211	int __must_check i915_gem_context_init(struct drm_device *dev);
3031	serge	3212	void i915_gem_context_fini(struct drm_device *dev);
5060	serge	3213	void i915_gem_context_reset(struct drm_device *dev);
		3214	int i915_gem_context_open(struct drm_device dev, struct drm_file file);
6084	serge	3215	int i915_gem_context_enable(struct drm_i915_gem_request *req);
3031	serge	3216	void i915_gem_context_close(struct drm_device dev, struct drm_file file);
6084	serge	3217	int i915_switch_context(struct drm_i915_gem_request *req);
5060	serge	3218	struct intel_context *
		3219	i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
4104	Serge	3220	void i915_gem_context_free(struct kref *ctx_ref);
5354	serge	3221	struct drm_i915_gem_object *
		3222	i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
5060	serge	3223	static inline void i915_gem_context_reference(struct intel_context *ctx)
4104	Serge	3224	{
		3225	kref_get(&ctx->ref);
		3226	}
		3227
5060	serge	3228	static inline void i915_gem_context_unreference(struct intel_context *ctx)
4104	Serge	3229	{
		3230	kref_put(&ctx->ref, i915_gem_context_free);
		3231	}
		3232
5060	serge	3233	static inline bool i915_gem_context_is_default(const struct intel_context *c)
		3234	{
		3235	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
		3236	}
		3237
3031	serge	3238	int i915_gem_context_create_ioctl(struct drm_device dev, void data,
		3239	struct drm_file *file);
		3240	int i915_gem_context_destroy_ioctl(struct drm_device dev, void data,
		3241	struct drm_file *file);
6084	serge	3242	int i915_gem_context_getparam_ioctl(struct drm_device dev, void data,
		3243	struct drm_file *file_priv);
		3244	int i915_gem_context_setparam_ioctl(struct drm_device dev, void data,
		3245	struct drm_file *file_priv);
3031	serge	3246
2325	Serge	3247	/* i915_gem_evict.c */
4104	Serge	3248	int __must_check i915_gem_evict_something(struct drm_device *dev,
		3249	struct i915_address_space *vm,
		3250	int min_size,
3031	serge	3251	unsigned alignment,
		3252	unsigned cache_level,
5060	serge	3253	unsigned long start,
		3254	unsigned long end,
		3255	unsigned flags);
6937	serge	3256	int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
4560	Serge	3257	int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2325	Serge	3258
5060	serge	3259	/* belongs in i915_gem_gtt.h */
		3260	static inline void i915_gem_chipset_flush(struct drm_device *dev)
		3261	{
		3262	if (INTEL_INFO(dev)->gen < 6)
		3263	intel_gtt_chipset_flush();
		3264	}
		3265
3031	serge	3266	/* i915_gem_stolen.c */
6084	serge	3267	int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
		3268	struct drm_mm_node *node, u64 size,
		3269	unsigned alignment);
		3270	int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
		3271	struct drm_mm_node *node, u64 size,
		3272	unsigned alignment, u64 start,
		3273	u64 end);
		3274	void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
		3275	struct drm_mm_node *node);
3031	serge	3276	int i915_gem_init_stolen(struct drm_device *dev);
		3277	void i915_gem_cleanup_stolen(struct drm_device *dev);
3480	Serge	3278	struct drm_i915_gem_object *
		3279	i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3746	Serge	3280	struct drm_i915_gem_object *
		3281	i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
		3282	u32 stolen_offset,
		3283	u32 gtt_offset,
		3284	u32 size);
3031	serge	3285
6084	serge	3286	/* i915_gem_shrinker.c */
		3287	unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
		3288	unsigned long target,
		3289	unsigned flags);
		3290	#define I915_SHRINK_PURGEABLE 0x1
		3291	#define I915_SHRINK_UNBOUND 0x2
		3292	#define I915_SHRINK_BOUND 0x4
		3293	#define I915_SHRINK_ACTIVE 0x8
		3294	unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
		3295	void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
7144	serge	3296	void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
6084	serge	3297
		3298
2325	Serge	3299	/* i915_gem_tiling.c */
4104	Serge	3300	static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3480	Serge	3301	{
5060	serge	3302	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3480	Serge	3303
		3304	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		3305	obj->tiling_mode != I915_TILING_NONE;
		3306	}
		3307
2325	Serge	3308	/* i915_gem_debug.c */
		3309	#if WATCH_LISTS
		3310	int i915_verify_lists(struct drm_device *dev);
		3311	#else
		3312	#define i915_verify_lists(dev) 0
		3313	#endif
		3314
		3315	/* i915_debugfs.c */
		3316	int i915_debugfs_init(struct drm_minor *minor);
		3317	void i915_debugfs_cleanup(struct drm_minor *minor);
4560	Serge	3318	#ifdef CONFIG_DEBUG_FS
6084	serge	3319	int i915_debugfs_connector_add(struct drm_connector *connector);
4560	Serge	3320	void intel_display_crc_init(struct drm_device *dev);
		3321	#else
6084	serge	3322	static inline int i915_debugfs_connector_add(struct drm_connector *connector)
		3323	{ return 0; }
4560	Serge	3324	static inline void intel_display_crc_init(struct drm_device *dev) {}
		3325	#endif
2325	Serge	3326
4104	Serge	3327	/* i915_gpu_error.c */
		3328	__printf(2, 3)
		3329	void i915_error_printf(struct drm_i915_error_state_buf e, const char f, ...);
		3330	int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
		3331	const struct i915_error_state_file_priv *error);
		3332	int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
5354	serge	3333	struct drm_i915_private *i915,
4104	Serge	3334	size_t count, loff_t pos);
		3335	static inline void i915_error_state_buf_release(
		3336	struct drm_i915_error_state_buf *eb)
		3337	{
		3338	kfree(eb->buf);
		3339	}
5060	serge	3340	void i915_capture_error_state(struct drm_device *dev, bool wedge,
		3341	const char *error_msg);
4104	Serge	3342	void i915_error_state_get(struct drm_device *dev,
		3343	struct i915_error_state_file_priv *error_priv);
		3344	void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
		3345	void i915_destroy_error_state(struct drm_device *dev);
		3346
		3347	void i915_get_extra_instdone(struct drm_device dev, uint32_t instdone);
5354	serge	3348	const char i915_cache_level_str(struct drm_i915_private i915, int type);
4104	Serge	3349
5060	serge	3350	/* i915_cmd_parser.c */
		3351	int i915_cmd_parser_get_version(void);
		3352	int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
		3353	void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
		3354	bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
		3355	int i915_parse_cmds(struct intel_engine_cs *ring,
		3356	struct drm_i915_gem_object *batch_obj,
6084	serge	3357	struct drm_i915_gem_object *shadow_batch_obj,
5060	serge	3358	u32 batch_start_offset,
6084	serge	3359	u32 batch_len,
5060	serge	3360	bool is_master);
		3361
2325	Serge	3362	/* i915_suspend.c */
		3363	extern int i915_save_state(struct drm_device *dev);
		3364	extern int i915_restore_state(struct drm_device *dev);
		3365
3031	serge	3366	/* i915_sysfs.c */
		3367	void i915_setup_sysfs(struct drm_device *dev_priv);
		3368	void i915_teardown_sysfs(struct drm_device *dev_priv);
		3369
2325	Serge	3370	/* intel_i2c.c */
		3371	extern int intel_setup_gmbus(struct drm_device *dev);
		3372	extern void intel_teardown_gmbus(struct drm_device *dev);
6084	serge	3373	extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
		3374	unsigned int pin);
3031	serge	3375
6084	serge	3376	extern struct i2c_adapter *
		3377	intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
2325	Serge	3378	extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
		3379	extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
4104	Serge	3380	static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2342	Serge	3381	{
		3382	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
		3383	}
2325	Serge	3384	extern void intel_i2c_reset(struct drm_device *dev);
		3385
6935	serge	3386	/* intel_bios.c */
6937	serge	3387	int intel_bios_init(struct drm_i915_private *dev_priv);
		3388	bool intel_bios_is_valid_vbt(const void *buf, size_t size);
6935	serge	3389
2325	Serge	3390	/* intel_opregion.c */
4560	Serge	3391	#ifdef CONFIG_ACPI
2325	Serge	3392	extern int intel_opregion_setup(struct drm_device *dev);
		3393	extern void intel_opregion_init(struct drm_device *dev);
		3394	extern void intel_opregion_fini(struct drm_device *dev);
		3395	extern void intel_opregion_asle_intr(struct drm_device *dev);
4560	Serge	3396	extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
		3397	bool enable);
		3398	extern int intel_opregion_notify_adapter(struct drm_device *dev,
		3399	pci_power_t state);
2325	Serge	3400	#else
4560	Serge	3401	static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2325	Serge	3402	static inline void intel_opregion_init(struct drm_device *dev) { return; }
		3403	static inline void intel_opregion_fini(struct drm_device *dev) { return; }
		3404	static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
4560	Serge	3405	static inline int
		3406	intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
		3407	{
		3408	return 0;
		3409	}
		3410	static inline int
		3411	intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
		3412	{
		3413	return 0;
		3414	}
2325	Serge	3415	#endif
		3416
		3417	/* intel_acpi.c */
		3418	#ifdef CONFIG_ACPI
		3419	extern void intel_register_dsm_handler(void);
		3420	extern void intel_unregister_dsm_handler(void);
		3421	#else
		3422	static inline void intel_register_dsm_handler(void) { return; }
		3423	static inline void intel_unregister_dsm_handler(void) { return; }
		3424	#endif /* CONFIG_ACPI */
		3425
		3426	/* modesetting */
3031	serge	3427	extern void intel_modeset_init_hw(struct drm_device *dev);
2325	Serge	3428	extern void intel_modeset_init(struct drm_device *dev);
		3429	extern void intel_modeset_gem_init(struct drm_device *dev);
		3430	extern void intel_modeset_cleanup(struct drm_device *dev);
5060	serge	3431	extern void intel_connector_unregister(struct intel_connector *);
2325	Serge	3432	extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
6084	serge	3433	extern void intel_display_resume(struct drm_device *dev);
3480	Serge	3434	extern void i915_redisable_vga(struct drm_device *dev);
5060	serge	3435	extern void i915_redisable_vga_power_on(struct drm_device *dev);
2325	Serge	3436	extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3243	Serge	3437	extern void intel_init_pch_refclk(struct drm_device *dev);
6084	serge	3438	extern void intel_set_rps(struct drm_device *dev, u8 val);
5060	serge	3439	extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
		3440	bool enable);
2342	Serge	3441	extern void intel_detect_pch(struct drm_device *dev);
3031	serge	3442	extern int intel_enable_rc6(const struct drm_device *dev);
2325	Serge	3443
3031	serge	3444	extern bool i915_semaphore_is_enabled(struct drm_device *dev);
		3445	int i915_reg_read_ioctl(struct drm_device dev, void data,
		3446	struct drm_file *file);
4560	Serge	3447	int i915_get_reset_stats_ioctl(struct drm_device dev, void data,
		3448	struct drm_file *file);
2342	Serge	3449
2325	Serge	3450	/* overlay */
		3451	extern struct intel_overlay_error_state intel_overlay_capture_error_state(struct drm_device dev);
4104	Serge	3452	extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
		3453	struct intel_overlay_error_state *error);
2325	Serge	3454
		3455	extern struct intel_display_error_state intel_display_capture_error_state(struct drm_device dev);
4104	Serge	3456	extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2325	Serge	3457	struct drm_device *dev,
		3458	struct intel_display_error_state *error);
		3459
5354	serge	3460	int sandybridge_pcode_read(struct drm_i915_private dev_priv, u32 mbox, u32 val);
		3461	int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3243	Serge	3462
4104	Serge	3463	/* intel_sideband.c */
6084	serge	3464	u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
		3465	void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
4104	Serge	3466	u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
7144	serge	3467	u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
		3468	void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
4560	Serge	3469	u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
		3470	void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3471	u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
		3472	void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3473	u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
		3474	void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3475	u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
		3476	void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
4104	Serge	3477	u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		3478	enum intel_sbi_destination destination);
		3479	void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		3480	enum intel_sbi_destination destination);
4560	Serge	3481	u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
		3482	void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2325	Serge	3483
6084	serge	3484	int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
		3485	int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
4104	Serge	3486
4560	Serge	3487	#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
		3488	#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2325	Serge	3489
4560	Serge	3490	#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
		3491	#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
		3492	#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
		3493	#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
		3494
		3495	#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
		3496	#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
		3497	#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
		3498	#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
		3499
5060	serge	3500	/* Be very careful with read/write 64-bit values. On 32-bit machines, they
		3501	* will be implemented using 2 32-bit writes in an arbitrary order with
		3502	* an arbitrary delay between them. This can cause the hardware to
		3503	* act upon the intermediate value, possibly leading to corruption and
		3504	* machine death. You have been warned.
		3505	*/
4560	Serge	3506	#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
		3507	#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
		3508
5060	serge	3509	#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
6084	serge	3510	u32 upper, lower, old_upper, loop = 0; \
		3511	upper = I915_READ(upper_reg); \
		3512	do { \
		3513	old_upper = upper; \
		3514	lower = I915_READ(lower_reg); \
		3515	upper = I915_READ(upper_reg); \
		3516	} while (upper != old_upper && loop++ < 2); \
		3517	(u64)upper << 32 \| lower; })
5060	serge	3518
2325	Serge	3519	#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
		3520	#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
		3521
6937	serge	3522	#define __raw_read(x, s) \
		3523	static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
		3524	i915_reg_t reg) \
		3525	{ \
		3526	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
		3527	}
		3528
		3529	#define __raw_write(x, s) \
		3530	static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
		3531	i915_reg_t reg, uint##x##_t val) \
		3532	{ \
		3533	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
		3534	}
		3535	__raw_read(8, b)
		3536	__raw_read(16, w)
		3537	__raw_read(32, l)
		3538	__raw_read(64, q)
		3539
		3540	__raw_write(8, b)
		3541	__raw_write(16, w)
		3542	__raw_write(32, l)
		3543	__raw_write(64, q)
		3544
		3545	#undef __raw_read
		3546	#undef __raw_write
		3547
6084	serge	3548	/* These are untraced mmio-accessors that are only valid to be used inside
		3549	* criticial sections inside IRQ handlers where forcewake is explicitly
		3550	* controlled.
		3551	* Think twice, and think again, before using these.
		3552	* Note: Should only be used between intel_uncore_forcewake_irqlock() and
		3553	* intel_uncore_forcewake_irqunlock().
		3554	*/
6937	serge	3555	#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
		3556	#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
6084	serge	3557	#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
		3558
3480	Serge	3559	/* "Broadcast RGB" property */
		3560	#define INTEL_BROADCAST_RGB_AUTO 0
		3561	#define INTEL_BROADCAST_RGB_FULL 1
		3562	#define INTEL_BROADCAST_RGB_LIMITED 2
		3563
6937	serge	3564	static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3480	Serge	3565	{
6937	serge	3566	if (IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev))
5060	serge	3567	return VLV_VGACNTRL;
		3568	else if (INTEL_INFO(dev)->gen >= 5)
3480	Serge	3569	return CPU_VGACNTRL;
		3570	else
		3571	return VGACNTRL;
		3572	}
		3573
3746	Serge	3574	static inline void __user *to_user_ptr(u64 address)
		3575	{
		3576	return (void __user *)(uintptr_t)address;
		3577	}
		3578
		3579	static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
		3580	{
		3581	unsigned long j = msecs_to_jiffies(m);
		3582
		3583	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
		3584	}
		3585
5354	serge	3586	static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
		3587	{
		3588	return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
		3589	}
		3590
3746	Serge	3591	static inline unsigned long
		3592	timespec_to_jiffies_timeout(const struct timespec *value)
		3593	{
		3594	unsigned long j = timespec_to_jiffies(value);
		3595
		3596	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
		3597	}
		3598
5060	serge	3599	/*
		3600	* If you need to wait X milliseconds between events A and B, but event B
		3601	* doesn't happen exactly after event A, you record the timestamp (jiffies) of
		3602	* when event A happened, then just before event B you call this function and
		3603	* pass the timestamp as the first argument, and X as the second argument.
		3604	*/
		3605	static inline void
		3606	wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4280	Serge	3607	{
5060	serge	3608	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
		3609
		3610	/*
		3611	* Don't re-read the value of "jiffies" every time since it may change
		3612	* behind our back and break the math.
		3613	*/
		3614	tmp_jiffies = jiffies;
		3615	target_jiffies = timestamp_jiffies +
		3616	msecs_to_jiffies_timeout(to_wait_ms);
		3617
		3618	if (time_after(target_jiffies, tmp_jiffies)) {
		3619	remaining_jiffies = target_jiffies - tmp_jiffies;
6103	serge	3620	delay(remaining_jiffies);
5060	serge	3621	}
4280	Serge	3622	}
3746	Serge	3623
6084	serge	3624	static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
		3625	struct drm_i915_gem_request *req)
2338	Serge	3626	{
6084	serge	3627	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
		3628	i915_gem_request_assign(&ring->trace_irq_req, req);
5354	serge	3629	}
		3630
2325	Serge	3631	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.h – Rev 7144