WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_drv.h

Rev	Author	Line No.	Line
2325	Serge	1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --
		2	*/
		3	/*
		4	*
		5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
		6	* All Rights Reserved.
		7	*
		8	* Permission is hereby granted, free of charge, to any person obtaining a
		9	* copy of this software and associated documentation files (the
		10	* "Software"), to deal in the Software without restriction, including
		11	* without limitation the rights to use, copy, modify, merge, publish,
		12	* distribute, sub license, and/or sell copies of the Software, and to
		13	* permit persons to whom the Software is furnished to do so, subject to
		14	* the following conditions:
		15	*
		16	* The above copyright notice and this permission notice (including the
		17	* next paragraph) shall be included in all copies or substantial portions
		18	* of the Software.
		19	*
		20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
		21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
		23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
		24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
		25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
		26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		27	*
		28	*/
		29
		30	#ifndef _I915_DRV_H_
		31	#define _I915_DRV_H_
		32
3480	Serge	33	#include
6084	serge	34	#include
3480	Serge	35
2325	Serge	36	#include "i915_reg.h"
2327	Serge	37	#include "intel_bios.h"
2326	Serge	38	#include "intel_ringbuffer.h"
5354	serge	39	#include "intel_lrc.h"
5060	serge	40	#include "i915_gem_gtt.h"
5354	serge	41	#include "i915_gem_render_state.h"
6084	serge	42	#include
2330	Serge	43	#include
3031	serge	44	#include
2332	Serge	45	#include
5354	serge	46	#include /* for struct drm_dma_handle */
		47	#include
2325	Serge	48	//#include
5060	serge	49	#include
6084	serge	50	#include
		51	#include "intel_guc.h"
2325	Serge	52
		53	#include
		54
6084	serge	55	#define ioread32(addr) readl(addr)
		56	static inline u8 inb(u16 port)
		57	{
		58	u8 v;
		59	asm volatile("inb %1,%0" : "=a" (v) : "dN" (port));
		60	return v;
		61	}
		62
		63	static inline void outb(u8 v, u16 port)
		64	{
		65	asm volatile("outb %0,%1" : : "a" (v), "dN" (port));
		66	}
		67
		68
2325	Serge	69	/* General customization:
		70	*/
		71
		72	#define DRIVER_NAME "i915"
		73	#define DRIVER_DESC "Intel Graphics"
6084	serge	74	#define DRIVER_DATE "20151010"
2325	Serge	75
5354	serge	76	#undef WARN_ON
6084	serge	77	/* Many gcc seem to no see through this and fall over :( */
		78	#if 0
		79	#define WARN_ON(x) ({ \
		80	bool __i915_warn_cond = (x); \
		81	if (__builtin_constant_p(__i915_warn_cond)) \
		82	BUILD_BUG_ON(__i915_warn_cond); \
		83	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
		84	#else
		85	#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
		86	#endif
5354	serge	87
6084	serge	88	#undef WARN_ON_ONCE
		89	#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
		90
		91	#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
		92	(long) (x), __func__);
		93
		94	/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
		95	* WARN_ON()) for hw state sanity checks to check for unexpected conditions
		96	* which may not necessarily be a user visible problem. This will either
		97	* WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
		98	* enable distros and users to tailor their preferred amount of i915 abrt
		99	* spam.
		100	*/
		101	#define I915_STATE_WARN(condition, format...) ({ \
		102	int __ret_warn_on = !!(condition); \
		103	if (unlikely(__ret_warn_on)) { \
		104	if (i915.verbose_state_checks) \
		105	WARN(1, format); \
		106	else \
		107	DRM_ERROR(format); \
		108	} \
		109	unlikely(__ret_warn_on); \
		110	})
		111
		112	#define I915_STATE_WARN_ON(condition) ({ \
		113	int __ret_warn_on = !!(condition); \
		114	if (unlikely(__ret_warn_on)) { \
		115	if (i915.verbose_state_checks) \
		116	WARN(1, "WARN_ON(" #condition ")\n"); \
		117	else \
		118	DRM_ERROR("WARN_ON(" #condition ")\n"); \
		119	} \
		120	unlikely(__ret_warn_on); \
		121	})
		122
		123	static inline const char *yesno(bool v)
		124	{
		125	return v ? "yes" : "no";
		126	}
		127
2325	Serge	128	enum pipe {
4560	Serge	129	INVALID_PIPE = -1,
2325	Serge	130	PIPE_A = 0,
		131	PIPE_B,
		132	PIPE_C,
5060	serge	133	_PIPE_EDP,
		134	I915_MAX_PIPES = _PIPE_EDP
2325	Serge	135	};
		136	#define pipe_name(p) ((p) + 'A')
		137
3243	Serge	138	enum transcoder {
		139	TRANSCODER_A = 0,
		140	TRANSCODER_B,
		141	TRANSCODER_C,
5060	serge	142	TRANSCODER_EDP,
		143	I915_MAX_TRANSCODERS
3243	Serge	144	};
		145	#define transcoder_name(t) ((t) + 'A')
		146
5354	serge	147	/*
6084	serge	148	* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
		149	* number of planes per CRTC. Not all platforms really have this many planes,
		150	* which means some arrays of size I915_MAX_PLANES may have unused entries
		151	* between the topmost sprite plane and the cursor plane.
5354	serge	152	*/
2325	Serge	153	enum plane {
		154	PLANE_A = 0,
		155	PLANE_B,
		156	PLANE_C,
6084	serge	157	PLANE_CURSOR,
		158	I915_MAX_PLANES,
2325	Serge	159	};
		160	#define plane_name(p) ((p) + 'A')
		161
5060	serge	162	#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
4104	Serge	163
3031	serge	164	enum port {
		165	PORT_A = 0,
		166	PORT_B,
		167	PORT_C,
		168	PORT_D,
		169	PORT_E,
		170	I915_MAX_PORTS
		171	};
		172	#define port_name(p) ((p) + 'A')
		173
5060	serge	174	#define I915_NUM_PHYS_VLV 2
4560	Serge	175
		176	enum dpio_channel {
		177	DPIO_CH0,
		178	DPIO_CH1
		179	};
		180
		181	enum dpio_phy {
		182	DPIO_PHY0,
		183	DPIO_PHY1
		184	};
		185
4104	Serge	186	enum intel_display_power_domain {
		187	POWER_DOMAIN_PIPE_A,
		188	POWER_DOMAIN_PIPE_B,
		189	POWER_DOMAIN_PIPE_C,
		190	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
		191	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
		192	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
		193	POWER_DOMAIN_TRANSCODER_A,
		194	POWER_DOMAIN_TRANSCODER_B,
		195	POWER_DOMAIN_TRANSCODER_C,
4560	Serge	196	POWER_DOMAIN_TRANSCODER_EDP,
5060	serge	197	POWER_DOMAIN_PORT_DDI_A_2_LANES,
		198	POWER_DOMAIN_PORT_DDI_A_4_LANES,
		199	POWER_DOMAIN_PORT_DDI_B_2_LANES,
		200	POWER_DOMAIN_PORT_DDI_B_4_LANES,
		201	POWER_DOMAIN_PORT_DDI_C_2_LANES,
		202	POWER_DOMAIN_PORT_DDI_C_4_LANES,
		203	POWER_DOMAIN_PORT_DDI_D_2_LANES,
		204	POWER_DOMAIN_PORT_DDI_D_4_LANES,
6084	serge	205	POWER_DOMAIN_PORT_DDI_E_2_LANES,
5060	serge	206	POWER_DOMAIN_PORT_DSI,
		207	POWER_DOMAIN_PORT_CRT,
		208	POWER_DOMAIN_PORT_OTHER,
4560	Serge	209	POWER_DOMAIN_VGA,
		210	POWER_DOMAIN_AUDIO,
5060	serge	211	POWER_DOMAIN_PLLS,
6084	serge	212	POWER_DOMAIN_AUX_A,
		213	POWER_DOMAIN_AUX_B,
		214	POWER_DOMAIN_AUX_C,
		215	POWER_DOMAIN_AUX_D,
		216	POWER_DOMAIN_GMBUS,
4560	Serge	217	POWER_DOMAIN_INIT,
		218
		219	POWER_DOMAIN_NUM,
4104	Serge	220	};
		221
		222	#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
		223	#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		224	((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
4560	Serge	225	#define POWER_DOMAIN_TRANSCODER(tran) \
		226	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
		227	(tran) + POWER_DOMAIN_TRANSCODER_A)
4104	Serge	228
3746	Serge	229	enum hpd_pin {
		230	HPD_NONE = 0,
		231	HPD_TV = HPD_NONE, /* TV is known to be unreliable */
		232	HPD_CRT,
		233	HPD_SDVO_B,
		234	HPD_SDVO_C,
6084	serge	235	HPD_PORT_A,
3746	Serge	236	HPD_PORT_B,
		237	HPD_PORT_C,
		238	HPD_PORT_D,
6084	serge	239	HPD_PORT_E,
3746	Serge	240	HPD_NUM_PINS
		241	};
		242
6084	serge	243	#define for_each_hpd_pin(__pin) \
		244	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
		245
		246	struct i915_hotplug {
		247	struct work_struct hotplug_work;
		248
		249	struct {
		250	unsigned long last_jiffies;
		251	int count;
		252	enum {
		253	HPD_ENABLED = 0,
		254	HPD_DISABLED = 1,
		255	HPD_MARK_DISABLED = 2
		256	} state;
		257	} stats[HPD_NUM_PINS];
		258	u32 event_bits;
		259	struct delayed_work reenable_work;
		260
		261	struct intel_digital_port *irq_port[I915_MAX_PORTS];
		262	u32 long_port_mask;
		263	u32 short_port_mask;
		264	struct work_struct dig_port_work;
		265
		266	/*
		267	* if we get a HPD irq from DP and a HPD irq from non-DP
		268	* the non-DP HPD could block the workqueue on a mode config
		269	* mutex getting, that userspace may have taken. However
		270	* userspace is waiting on the DP workqueue to run which is
		271	* blocked behind the non-DP one.
		272	*/
		273	struct workqueue_struct *dp_wq;
		274	};
		275
3480	Serge	276	#define I915_GEM_GPU_DOMAINS \
		277	(I915_GEM_DOMAIN_RENDER \| \
		278	I915_GEM_DOMAIN_SAMPLER \| \
		279	I915_GEM_DOMAIN_COMMAND \| \
		280	I915_GEM_DOMAIN_INSTRUCTION \| \
		281	I915_GEM_DOMAIN_VERTEX)
2325	Serge	282
5354	serge	283	#define for_each_pipe(__dev_priv, __p) \
		284	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
6084	serge	285	#define for_each_plane(__dev_priv, __pipe, __p) \
		286	for ((__p) = 0; \
		287	(__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
		288	(__p)++)
		289	#define for_each_sprite(__dev_priv, __p, __s) \
		290	for ((__s) = 0; \
		291	(__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
		292	(__s)++)
2325	Serge	293
5060	serge	294	#define for_each_crtc(dev, crtc) \
		295	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
		296
6084	serge	297	#define for_each_intel_plane(dev, intel_plane) \
		298	list_for_each_entry(intel_plane, \
		299	&dev->mode_config.plane_list, \
		300	base.head)
		301
		302	#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
		303	list_for_each_entry(intel_plane, \
		304	&(dev)->mode_config.plane_list, \
		305	base.head) \
		306	if ((intel_plane)->pipe == (intel_crtc)->pipe)
		307
5060	serge	308	#define for_each_intel_crtc(dev, intel_crtc) \
		309	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
		310
5354	serge	311	#define for_each_intel_encoder(dev, intel_encoder) \
		312	list_for_each_entry(intel_encoder, \
		313	&(dev)->mode_config.encoder_list, \
		314	base.head)
		315
6084	serge	316	#define for_each_intel_connector(dev, intel_connector) \
		317	list_for_each_entry(intel_connector, \
		318	&dev->mode_config.connector_list, \
		319	base.head)
		320
3031	serge	321	#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
		322	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
		323	if ((intel_encoder)->base.crtc == (__crtc))
		324
5060	serge	325	#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
		326	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
		327	if ((intel_connector)->base.encoder == (__encoder))
		328
		329	#define for_each_power_domain(domain, mask) \
		330	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
		331	if ((1 << (domain)) & (mask))
		332
4104	Serge	333	struct drm_i915_private;
5128	serge	334	struct i915_mm_struct;
5060	serge	335	struct i915_mmu_object;
4104	Serge	336
6084	serge	337	struct drm_i915_file_private {
		338	struct drm_i915_private *dev_priv;
		339	struct drm_file *file;
		340
		341	struct {
		342	spinlock_t lock;
		343	struct list_head request_list;
		344	/* 20ms is a fairly arbitrary limit (greater than the average frame time)
		345	* chosen to prevent the CPU getting more than a frame ahead of the GPU
		346	* (when using lax throttling for the frontbuffer). We also use it to
		347	* offer free GPU waitboosts for severely congested workloads.
		348	*/
		349	#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
		350	} mm;
		351	struct idr context_idr;
		352
		353	struct intel_rps_client {
		354	struct list_head link;
		355	unsigned boosts;
		356	} rps;
		357
		358	struct intel_engine_cs *bsd_ring;
		359	};
		360
4104	Serge	361	enum intel_dpll_id {
		362	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
		363	/* real shared dpll ids must be >= 0 */
5060	serge	364	DPLL_ID_PCH_PLL_A = 0,
		365	DPLL_ID_PCH_PLL_B = 1,
5354	serge	366	/* hsw/bdw */
5060	serge	367	DPLL_ID_WRPLL1 = 0,
		368	DPLL_ID_WRPLL2 = 1,
6084	serge	369	DPLL_ID_SPLL = 2,
		370
5354	serge	371	/* skl */
		372	DPLL_ID_SKL_DPLL1 = 0,
		373	DPLL_ID_SKL_DPLL2 = 1,
		374	DPLL_ID_SKL_DPLL3 = 2,
4104	Serge	375	};
5354	serge	376	#define I915_NUM_PLLS 3
4104	Serge	377
		378	struct intel_dpll_hw_state {
5354	serge	379	/* i9xx, pch plls */
4104	Serge	380	uint32_t dpll;
		381	uint32_t dpll_md;
		382	uint32_t fp0;
		383	uint32_t fp1;
5354	serge	384
		385	/* hsw, bdw */
5060	serge	386	uint32_t wrpll;
6084	serge	387	uint32_t spll;
5354	serge	388
		389	/* skl */
		390	/*
		391	* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
6084	serge	392	* lower part of ctrl1 and they get shifted into position when writing
5354	serge	393	* the register. This allows us to easily compare the state to share
		394	* the DPLL.
		395	*/
		396	uint32_t ctrl1;
		397	/* HDMI only, 0 when used for DP */
		398	uint32_t cfgcr1, cfgcr2;
6084	serge	399
		400	/* bxt */
		401	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
		402	pcsdw12;
4104	Serge	403	};
		404
5354	serge	405	struct intel_shared_dpll_config {
		406	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
		407	struct intel_dpll_hw_state hw_state;
		408	};
		409
4104	Serge	410	struct intel_shared_dpll {
5354	serge	411	struct intel_shared_dpll_config config;
		412
3031	serge	413	int active; /* count of number of active CRTCs (i.e. DPMS on) */
		414	bool on; /* is the PLL actually active? Disabled during modeset */
4104	Serge	415	const char *name;
		416	/* should match the index in the dev_priv->shared_dplls array */
		417	enum intel_dpll_id id;
5060	serge	418	/* The mode_set hook is optional and should be used together with the
		419	* intel_prepare_shared_dpll function. */
4104	Serge	420	void (mode_set)(struct drm_i915_private dev_priv,
		421	struct intel_shared_dpll *pll);
		422	void (enable)(struct drm_i915_private dev_priv,
		423	struct intel_shared_dpll *pll);
		424	void (disable)(struct drm_i915_private dev_priv,
		425	struct intel_shared_dpll *pll);
		426	bool (get_hw_state)(struct drm_i915_private dev_priv,
		427	struct intel_shared_dpll *pll,
		428	struct intel_dpll_hw_state *hw_state);
3031	serge	429	};
		430
5354	serge	431	#define SKL_DPLL0 0
		432	#define SKL_DPLL1 1
		433	#define SKL_DPLL2 2
		434	#define SKL_DPLL3 3
		435
3480	Serge	436	/* Used by dp and fdi links */
		437	struct intel_link_m_n {
		438	uint32_t tu;
		439	uint32_t gmch_m;
		440	uint32_t gmch_n;
		441	uint32_t link_m;
		442	uint32_t link_n;
		443	};
		444
		445	void intel_link_compute_m_n(int bpp, int nlanes,
		446	int pixel_clock, int link_clock,
		447	struct intel_link_m_n *m_n);
		448
2325	Serge	449	/* Interface history:
		450	*
		451	* 1.1: Original.
		452	* 1.2: Add Power Management
		453	* 1.3: Add vblank support
		454	* 1.4: Fix cmdbuffer path, add heap destroy
		455	* 1.5: Add vblank pipe configuration
		456	* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
		457	* - Support vertical blank on secondary display pipe
		458	*/
		459	#define DRIVER_MAJOR 1
		460	#define DRIVER_MINOR 6
		461	#define DRIVER_PATCHLEVEL 0
		462
		463	#define WATCH_LISTS 0
		464
		465	struct opregion_header;
		466	struct opregion_acpi;
		467	struct opregion_swsci;
		468	struct opregion_asle;
		469
		470	struct intel_opregion {
6084	serge	471	struct opregion_header *header;
		472	struct opregion_acpi *acpi;
		473	struct opregion_swsci *swsci;
4560	Serge	474	u32 swsci_gbda_sub_functions;
		475	u32 swsci_sbcb_sub_functions;
6084	serge	476	struct opregion_asle *asle;
		477	void *vbt;
		478	u32 *lid_state;
4560	Serge	479	struct work_struct asle_work;
2325	Serge	480	};
		481	#define OPREGION_SIZE (8*1024)
		482
		483	struct intel_overlay;
		484	struct intel_overlay_error_state;
		485
		486	#define I915_FENCE_REG_NONE -1
3746	Serge	487	#define I915_MAX_NUM_FENCES 32
		488	/* 32 fences + sign bit for FENCE_REG_NONE */
		489	#define I915_MAX_NUM_FENCE_BITS 6
2325	Serge	490
		491	struct drm_i915_fence_reg {
		492	struct list_head lru_list;
		493	struct drm_i915_gem_object *obj;
3031	serge	494	int pin_count;
2325	Serge	495	};
		496
		497	struct sdvo_device_mapping {
		498	u8 initialized;
		499	u8 dvo_port;
		500	u8 slave_addr;
		501	u8 dvo_wiring;
		502	u8 i2c_pin;
		503	u8 ddc_pin;
		504	};
		505
		506	struct intel_display_error_state;
		507
		508	struct drm_i915_error_state {
3243	Serge	509	struct kref ref;
5060	serge	510	struct timeval time;
		511
		512	char error_msg[128];
6084	serge	513	int iommu;
5060	serge	514	u32 reset_count;
		515	u32 suspend_count;
		516
		517	/* Generic register state */
2325	Serge	518	u32 eir;
		519	u32 pgtbl_er;
3031	serge	520	u32 ier;
5060	serge	521	u32 gtier[4];
3031	serge	522	u32 ccid;
3243	Serge	523	u32 derrmr;
		524	u32 forcewake;
2325	Serge	525	u32 error; /* gen6+ */
3031	serge	526	u32 err_int; /* gen7 */
6084	serge	527	u32 fault_data0; /* gen8, gen9 */
		528	u32 fault_data1; /* gen8, gen9 */
5060	serge	529	u32 done_reg;
		530	u32 gac_eco;
		531	u32 gam_ecochk;
		532	u32 gab_ctl;
		533	u32 gfx_mode;
3031	serge	534	u32 extra_instdone[I915_NUM_INSTDONE_REG];
2342	Serge	535	u64 fence[I915_MAX_NUM_FENCES];
5060	serge	536	struct intel_overlay_error_state *overlay;
		537	struct intel_display_error_state *display;
6084	serge	538	struct drm_i915_error_object *semaphore_obj;
5060	serge	539
3031	serge	540	struct drm_i915_error_ring {
4560	Serge	541	bool valid;
5060	serge	542	/* Software tracked state */
		543	bool waiting;
		544	int hangcheck_score;
		545	enum intel_ring_hangcheck_action hangcheck_action;
		546	int num_requests;
		547
		548	/* our own tracking of ring head and tail */
		549	u32 cpu_ring_head;
		550	u32 cpu_ring_tail;
		551
		552	u32 semaphore_seqno[I915_NUM_RINGS - 1];
		553
		554	/* Register state */
6084	serge	555	u32 start;
5060	serge	556	u32 tail;
		557	u32 head;
		558	u32 ctl;
		559	u32 hws;
		560	u32 ipeir;
		561	u32 ipehr;
		562	u32 instdone;
		563	u32 bbstate;
		564	u32 instpm;
		565	u32 instps;
		566	u32 seqno;
		567	u64 bbaddr;
		568	u64 acthd;
		569	u32 fault_reg;
		570	u64 faddr;
		571	u32 rc_psmi; /* sleep state */
		572	u32 semaphore_mboxes[I915_NUM_RINGS - 1];
		573
6084	serge	574	struct drm_i915_error_object {
		575	int page_count;
		576	u64 gtt_offset;
		577	u32 *pages[0];
5060	serge	578	} ringbuffer, batchbuffer, wa_batchbuffer, ctx, *hws_page;
		579
3031	serge	580	struct drm_i915_error_request {
		581	long jiffies;
		582	u32 seqno;
		583	u32 tail;
		584	} *requests;
5060	serge	585
		586	struct {
		587	u32 gfx_mode;
		588	union {
		589	u64 pdp[4];
		590	u32 pp_dir_base;
		591	};
		592	} vm_info;
		593
		594	pid_t pid;
		595	char comm[TASK_COMM_LEN];
3031	serge	596	} ring[I915_NUM_RINGS];
5354	serge	597
2325	Serge	598	struct drm_i915_error_buffer {
		599	u32 size;
		600	u32 name;
6084	serge	601	u32 rseqno[I915_NUM_RINGS], wseqno;
		602	u64 gtt_offset;
2325	Serge	603	u32 read_domains;
		604	u32 write_domain;
2342	Serge	605	s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
2325	Serge	606	s32 pinned:2;
		607	u32 tiling:2;
		608	u32 dirty:1;
		609	u32 purgeable:1;
5060	serge	610	u32 userptr:1;
3031	serge	611	s32 ring:4;
4560	Serge	612	u32 cache_level:3;
4104	Serge	613	} active_bo, pinned_bo;
5060	serge	614
4104	Serge	615	u32 active_bo_count, pinned_bo_count;
5354	serge	616	u32 vm_count;
2325	Serge	617	};
		618
4560	Serge	619	struct intel_connector;
5354	serge	620	struct intel_encoder;
6084	serge	621	struct intel_crtc_state;
		622	struct intel_initial_plane_config;
3746	Serge	623	struct intel_crtc;
4104	Serge	624	struct intel_limit;
		625	struct dpll;
3746	Serge	626
2325	Serge	627	struct drm_i915_display_funcs {
		628	int (get_display_clock_speed)(struct drm_device dev);
		629	int (get_fifo_size)(struct drm_device dev, int plane);
4104	Serge	630	/**
		631	* find_dpll() - Find the best values for the PLL
		632	* @limit: limits for the PLL
		633	* @crtc: current CRTC
		634	* @target: target frequency in kHz
		635	* @refclk: reference clock frequency in kHz
		636	* @match_clock: if provided, @best_clock P divider must
		637	* match the P divider from @match_clock
		638	* used for LVDS downclocking
		639	* @best_clock: best PLL values found
		640	*
		641	* Returns true on success, false on failure.
		642	*/
		643	bool (find_dpll)(const struct intel_limit limit,
6084	serge	644	struct intel_crtc_state *crtc_state,
4104	Serge	645	int target, int refclk,
		646	struct dpll *match_clock,
		647	struct dpll *best_clock);
4560	Serge	648	void (update_wm)(struct drm_crtc crtc);
4104	Serge	649	void (update_sprite_wm)(struct drm_plane plane,
		650	struct drm_crtc *crtc,
5060	serge	651	uint32_t sprite_width, uint32_t sprite_height,
		652	int pixel_size, bool enable, bool scaled);
6084	serge	653	int (modeset_calc_cdclk)(struct drm_atomic_state state);
		654	void (modeset_commit_cdclk)(struct drm_atomic_state state);
3746	Serge	655	/* Returns the active state of the crtc, and if the crtc is active,
		656	* fills out the pipe-config with the hw state. */
		657	bool (get_pipe_config)(struct intel_crtc ,
6084	serge	658	struct intel_crtc_state *);
		659	void (get_initial_plane_config)(struct intel_crtc ,
		660	struct intel_initial_plane_config *);
		661	int (crtc_compute_clock)(struct intel_crtc crtc,
		662	struct intel_crtc_state *crtc_state);
3031	serge	663	void (crtc_enable)(struct drm_crtc crtc);
		664	void (crtc_disable)(struct drm_crtc crtc);
5354	serge	665	void (audio_codec_enable)(struct drm_connector connector,
		666	struct intel_encoder *encoder,
6084	serge	667	const struct drm_display_mode *adjusted_mode);
5354	serge	668	void (audio_codec_disable)(struct intel_encoder encoder);
2325	Serge	669	void (fdi_link_train)(struct drm_crtc crtc);
		670	void (init_clock_gating)(struct drm_device dev);
		671	int (queue_flip)(struct drm_device dev, struct drm_crtc *crtc,
		672	struct drm_framebuffer *fb,
4104	Serge	673	struct drm_i915_gem_object *obj,
6084	serge	674	struct drm_i915_gem_request *req,
4104	Serge	675	uint32_t flags);
5060	serge	676	void (update_primary_plane)(struct drm_crtc crtc,
6084	serge	677	struct drm_framebuffer *fb,
		678	int x, int y);
3480	Serge	679	void (hpd_irq_setup)(struct drm_device dev);
2325	Serge	680	/* clock updates for mode set */
		681	/* cursor updates */
		682	/* render clock increase/decrease */
		683	/* display clock increase/decrease */
		684	/* pll clock increase/decrease */
6084	serge	685	};
4560	Serge	686
6084	serge	687	enum forcewake_domain_id {
		688	FW_DOMAIN_ID_RENDER = 0,
		689	FW_DOMAIN_ID_BLITTER,
		690	FW_DOMAIN_ID_MEDIA,
		691
		692	FW_DOMAIN_ID_COUNT
2325	Serge	693	};
		694
6084	serge	695	enum forcewake_domains {
		696	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
		697	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
		698	FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
		699	FORCEWAKE_ALL = (FORCEWAKE_RENDER \|
		700	FORCEWAKE_BLITTER \|
		701	FORCEWAKE_MEDIA)
		702	};
		703
4104	Serge	704	struct intel_uncore_funcs {
4560	Serge	705	void (force_wake_get)(struct drm_i915_private dev_priv,
6084	serge	706	enum forcewake_domains domains);
4560	Serge	707	void (force_wake_put)(struct drm_i915_private dev_priv,
6084	serge	708	enum forcewake_domains domains);
4560	Serge	709
		710	uint8_t (mmio_readb)(struct drm_i915_private dev_priv, off_t offset, bool trace);
		711	uint16_t (mmio_readw)(struct drm_i915_private dev_priv, off_t offset, bool trace);
		712	uint32_t (mmio_readl)(struct drm_i915_private dev_priv, off_t offset, bool trace);
		713	uint64_t (mmio_readq)(struct drm_i915_private dev_priv, off_t offset, bool trace);
		714
		715	void (mmio_writeb)(struct drm_i915_private dev_priv, off_t offset,
		716	uint8_t val, bool trace);
		717	void (mmio_writew)(struct drm_i915_private dev_priv, off_t offset,
		718	uint16_t val, bool trace);
		719	void (mmio_writel)(struct drm_i915_private dev_priv, off_t offset,
		720	uint32_t val, bool trace);
		721	void (mmio_writeq)(struct drm_i915_private dev_priv, off_t offset,
		722	uint64_t val, bool trace);
3031	serge	723	};
		724
4104	Serge	725	struct intel_uncore {
		726	spinlock_t lock; /** lock is also taken in irq contexts. */
3031	serge	727
4104	Serge	728	struct intel_uncore_funcs funcs;
		729
		730	unsigned fifo_count;
6084	serge	731	enum forcewake_domains fw_domains;
4560	Serge	732
6084	serge	733	struct intel_uncore_forcewake_domain {
		734	struct drm_i915_private *i915;
		735	enum forcewake_domain_id id;
		736	unsigned wake_count;
		737	struct timer_list timer;
		738	u32 reg_set;
		739	u32 val_set;
		740	u32 val_clear;
		741	u32 reg_ack;
		742	u32 reg_post;
		743	u32 val_reset;
		744	} fw_domain[FW_DOMAIN_ID_COUNT];
		745	};
4560	Serge	746
6084	serge	747	/* Iterate over initialised fw domains */
		748	#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
		749	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
		750	(i__) < FW_DOMAIN_ID_COUNT; \
		751	(i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
		752	if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
		753
		754	#define for_each_fw_domain(domain__, dev_priv__, i__) \
		755	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
		756
		757	enum csr_state {
		758	FW_UNINITIALIZED = 0,
		759	FW_LOADED,
		760	FW_FAILED
4104	Serge	761	};
		762
6084	serge	763	struct intel_csr {
		764	const char *fw_path;
		765	uint32_t *dmc_payload;
		766	uint32_t dmc_fw_size;
		767	uint32_t mmio_count;
		768	uint32_t mmioaddr[8];
		769	uint32_t mmiodata[8];
		770	enum csr_state state;
		771	};
		772
4104	Serge	773	#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
		774	func(is_mobile) sep \
		775	func(is_i85x) sep \
		776	func(is_i915g) sep \
		777	func(is_i945gm) sep \
		778	func(is_g33) sep \
		779	func(need_gfx_hws) sep \
		780	func(is_g4x) sep \
		781	func(is_pineview) sep \
		782	func(is_broadwater) sep \
		783	func(is_crestline) sep \
		784	func(is_ivybridge) sep \
		785	func(is_valleyview) sep \
		786	func(is_haswell) sep \
5354	serge	787	func(is_skylake) sep \
4560	Serge	788	func(is_preliminary) sep \
4104	Serge	789	func(has_fbc) sep \
		790	func(has_pipe_cxsr) sep \
		791	func(has_hotplug) sep \
		792	func(cursor_needs_physical) sep \
		793	func(has_overlay) sep \
		794	func(overlay_needs_physical) sep \
		795	func(supports_tv) sep \
		796	func(has_llc) sep \
		797	func(has_ddi) sep \
		798	func(has_fpga_dbg)
		799
		800	#define DEFINE_FLAG(name) u8 name:1
		801	#define SEP_SEMICOLON ;
		802
2325	Serge	803	struct intel_device_info {
3480	Serge	804	u32 display_mmio_offset;
5354	serge	805	u16 device_id;
3746	Serge	806	u8 num_pipes:3;
5060	serge	807	u8 num_sprites[I915_MAX_PIPES];
2325	Serge	808	u8 gen;
4560	Serge	809	u8 ring_mask; /* Rings supported by the HW */
4104	Serge	810	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
5060	serge	811	/* Register offsets for the various display pipes and transcoders */
		812	int pipe_offsets[I915_MAX_TRANSCODERS];
		813	int trans_offsets[I915_MAX_TRANSCODERS];
		814	int palette_offsets[I915_MAX_PIPES];
		815	int cursor_offsets[I915_MAX_PIPES];
6084	serge	816
		817	/* Slice/subslice/EU info */
		818	u8 slice_total;
		819	u8 subslice_total;
		820	u8 subslice_per_slice;
		821	u8 eu_total;
		822	u8 eu_per_subslice;
		823	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
		824	u8 subslice_7eu[3];
		825	u8 has_slice_pg:1;
		826	u8 has_subslice_pg:1;
		827	u8 has_eu_pg:1;
2325	Serge	828	};
		829
4104	Serge	830	#undef DEFINE_FLAG
		831	#undef SEP_SEMICOLON
		832
3480	Serge	833	enum i915_cache_level {
		834	I915_CACHE_NONE = 0,
4104	Serge	835	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
		836	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
		837	caches, eg sampler/render caches, and the
		838	large Last-Level-Cache. LLC is coherent with
		839	the CPU, but L3 is only visible to the GPU. */
		840	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
3480	Serge	841	};
		842
4104	Serge	843	struct i915_ctx_hang_stats {
		844	/* This context had batch pending when hang was declared */
		845	unsigned batch_pending;
		846
		847	/* This context had batch active when hang was declared */
		848	unsigned batch_active;
4560	Serge	849
		850	/* Time when this context was last blamed for a GPU reset */
		851	unsigned long guilty_ts;
		852
6084	serge	853	/* If the contexts causes a second GPU hang within this time,
		854	* it is permanently banned from submitting any more work.
		855	*/
		856	unsigned long ban_period_seconds;
		857
4560	Serge	858	/* This context is banned to submit more work */
		859	bool banned;
4104	Serge	860	};
		861
3031	serge	862	/* This must match up with the value previously used for execbuf2.rsvd1. */
5060	serge	863	#define DEFAULT_CONTEXT_HANDLE 0
6084	serge	864
		865	#define CONTEXT_NO_ZEROMAP (1<<0)
5060	serge	866	/**
		867	* struct intel_context - as the name implies, represents a context.
		868	* @ref: reference count.
		869	* @user_handle: userspace tracking identity for this context.
		870	* @remap_slice: l3 row remapping information.
6084	serge	871	* @flags: context specific flags:
		872	* CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
5060	serge	873	* @file_priv: filp associated with this context (NULL for global default
		874	* context).
		875	* @hang_stats: information about the role of this context in possible GPU
		876	* hangs.
6084	serge	877	* @ppgtt: virtual memory space used by this context.
5060	serge	878	* @legacy_hw_ctx: render context backing object and whether it is correctly
		879	* initialized (legacy ring submission mechanism only).
		880	* @link: link in the global list of contexts.
		881	*
		882	* Contexts are memory images used by the hardware to store copies of their
		883	* internal state.
		884	*/
		885	struct intel_context {
4104	Serge	886	struct kref ref;
5060	serge	887	int user_handle;
4560	Serge	888	uint8_t remap_slice;
6084	serge	889	struct drm_i915_private *i915;
		890	int flags;
3031	serge	891	struct drm_i915_file_private *file_priv;
4104	Serge	892	struct i915_ctx_hang_stats hang_stats;
5354	serge	893	struct i915_hw_ppgtt *ppgtt;
4560	Serge	894
5354	serge	895	/* Legacy ring buffer submission */
5060	serge	896	struct {
		897	struct drm_i915_gem_object *rcs_state;
		898	bool initialized;
		899	} legacy_hw_ctx;
		900
5354	serge	901	/* Execlists */
		902	struct {
		903	struct drm_i915_gem_object *state;
		904	struct intel_ringbuffer *ringbuf;
6084	serge	905	int pin_count;
5354	serge	906	} engine[I915_NUM_RINGS];
		907
4560	Serge	908	struct list_head link;
3031	serge	909	};
		910
6084	serge	911	enum fb_op_origin {
		912	ORIGIN_GTT,
		913	ORIGIN_CPU,
		914	ORIGIN_CS,
		915	ORIGIN_FLIP,
		916	ORIGIN_DIRTYFB,
		917	};
		918
4104	Serge	919	struct i915_fbc {
6084	serge	920	/* This is always the inner lock when overlapping with struct_mutex and
		921	* it's the outer lock when overlapping with stolen_lock. */
		922	struct mutex lock;
		923	unsigned long uncompressed_size;
5060	serge	924	unsigned threshold;
4104	Serge	925	unsigned int fb_id;
6084	serge	926	unsigned int possible_framebuffer_bits;
		927	unsigned int busy_bits;
		928	struct intel_crtc *crtc;
4104	Serge	929	int y;
		930
5060	serge	931	struct drm_mm_node compressed_fb;
4104	Serge	932	struct drm_mm_node *compressed_llb;
		933
5354	serge	934	bool false_color;
		935
		936	/* Tracks whether the HW is actually enabled, not whether the feature is
		937	* possible. */
		938	bool enabled;
		939
4104	Serge	940	struct intel_fbc_work {
		941	struct delayed_work work;
6084	serge	942	struct intel_crtc *crtc;
4104	Serge	943	struct drm_framebuffer *fb;
		944	} *fbc_work;
		945
4539	Serge	946	enum no_fbc_reason {
4104	Serge	947	FBC_OK, /* FBC is enabled */
		948	FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
6084	serge	949	FBC_NO_OUTPUT, /* no outputs enabled to compress */
4104	Serge	950	FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
6084	serge	951	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
		952	FBC_MODE_TOO_LARGE, /* mode too large for compression */
		953	FBC_BAD_PLANE, /* fbc not supported on plane */
		954	FBC_NOT_TILED, /* buffer not tiled */
		955	FBC_MULTIPLE_PIPES, /* more than one pipe active */
		956	FBC_MODULE_PARAM,
4104	Serge	957	FBC_CHIP_DEFAULT, /* disabled by default on this chip */
6084	serge	958	FBC_ROTATION, /* rotation is not supported */
		959	FBC_IN_DBG_MASTER, /* kernel debugger is active */
		960	FBC_BAD_STRIDE, /* stride is not supported */
		961	FBC_PIXEL_RATE, /* pixel rate is too big */
		962	FBC_PIXEL_FORMAT /* pixel format is invalid */
4104	Serge	963	} no_fbc_reason;
6084	serge	964
		965	bool (fbc_enabled)(struct drm_i915_private dev_priv);
		966	void (enable_fbc)(struct intel_crtc crtc);
		967	void (disable_fbc)(struct drm_i915_private dev_priv);
2325	Serge	968	};
		969
6084	serge	970	/**
		971	* HIGH_RR is the highest eDP panel refresh rate read from EDID
		972	* LOW_RR is the lowest eDP panel refresh rate found from EDID
		973	* parsing for same resolution.
		974	*/
		975	enum drrs_refresh_rate_type {
		976	DRRS_HIGH_RR,
		977	DRRS_LOW_RR,
		978	DRRS_MAX_RR, /* RR count */
		979	};
		980
		981	enum drrs_support_type {
		982	DRRS_NOT_SUPPORTED = 0,
		983	STATIC_DRRS_SUPPORT = 1,
		984	SEAMLESS_DRRS_SUPPORT = 2
		985	};
		986
		987	struct intel_dp;
5060	serge	988	struct i915_drrs {
6084	serge	989	struct mutex mutex;
		990	struct delayed_work work;
		991	struct intel_dp *dp;
		992	unsigned busy_frontbuffer_bits;
		993	enum drrs_refresh_rate_type refresh_rate_type;
		994	enum drrs_support_type type;
5060	serge	995	};
		996
4560	Serge	997	struct i915_psr {
5060	serge	998	struct mutex lock;
4560	Serge	999	bool sink_support;
		1000	bool source_ok;
5060	serge	1001	struct intel_dp *enabled;
		1002	bool active;
		1003	struct delayed_work work;
		1004	unsigned busy_frontbuffer_bits;
6084	serge	1005	bool psr2_support;
		1006	bool aux_frame_sync;
4104	Serge	1007	};
		1008
2325	Serge	1009	enum intel_pch {
3031	serge	1010	PCH_NONE = 0, /* No PCH present */
2325	Serge	1011	PCH_IBX, /* Ibexpeak PCH */
		1012	PCH_CPT, /* Cougarpoint PCH */
3031	serge	1013	PCH_LPT, /* Lynxpoint PCH */
5354	serge	1014	PCH_SPT, /* Sunrisepoint PCH */
3746	Serge	1015	PCH_NOP,
2325	Serge	1016	};
		1017
3243	Serge	1018	enum intel_sbi_destination {
		1019	SBI_ICLK,
		1020	SBI_MPHY,
		1021	};
		1022
2325	Serge	1023	#define QUIRK_PIPEA_FORCE (1<<0)
		1024	#define QUIRK_LVDS_SSC_DISABLE (1<<1)
3031	serge	1025	#define QUIRK_INVERT_BRIGHTNESS (1<<2)
5060	serge	1026	#define QUIRK_BACKLIGHT_PRESENT (1<<3)
5354	serge	1027	#define QUIRK_PIPEB_FORCE (1<<4)
		1028	#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
2325	Serge	1029
		1030	struct intel_fbdev;
		1031	struct intel_fbc_work;
		1032
3031	serge	1033	struct intel_gmbus {
		1034	struct i2c_adapter adapter;
3243	Serge	1035	u32 force_bit;
3031	serge	1036	u32 reg0;
		1037	u32 gpio_reg;
		1038	struct i2c_algo_bit_data bit_algo;
		1039	struct drm_i915_private *dev_priv;
		1040	};
		1041
3243	Serge	1042	struct i915_suspend_saved_registers {
2325	Serge	1043	u32 saveDSPARB;
		1044	u32 saveLVDS;
		1045	u32 savePP_ON_DELAYS;
		1046	u32 savePP_OFF_DELAYS;
		1047	u32 savePP_ON;
		1048	u32 savePP_OFF;
		1049	u32 savePP_CONTROL;
		1050	u32 savePP_DIVISOR;
		1051	u32 saveFBC_CONTROL;
		1052	u32 saveCACHE_MODE_0;
		1053	u32 saveMI_ARB_STATE;
		1054	u32 saveSWF0[16];
		1055	u32 saveSWF1[16];
6084	serge	1056	u32 saveSWF3[3];
2342	Serge	1057	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
2325	Serge	1058	u32 savePCH_PORT_HOTPLUG;
5354	serge	1059	u16 saveGCDGMBUS;
3243	Serge	1060	};
2325	Serge	1061
5060	serge	1062	struct vlv_s0ix_state {
		1063	/* GAM */
		1064	u32 wr_watermark;
		1065	u32 gfx_prio_ctrl;
		1066	u32 arb_mode;
		1067	u32 gfx_pend_tlb0;
		1068	u32 gfx_pend_tlb1;
		1069	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
		1070	u32 media_max_req_count;
		1071	u32 gfx_max_req_count;
		1072	u32 render_hwsp;
		1073	u32 ecochk;
		1074	u32 bsd_hwsp;
		1075	u32 blt_hwsp;
		1076	u32 tlb_rd_addr;
		1077
		1078	/* MBC */
		1079	u32 g3dctl;
		1080	u32 gsckgctl;
		1081	u32 mbctl;
		1082
		1083	/* GCP */
		1084	u32 ucgctl1;
		1085	u32 ucgctl3;
		1086	u32 rcgctl1;
		1087	u32 rcgctl2;
		1088	u32 rstctl;
		1089	u32 misccpctl;
		1090
		1091	/* GPM */
		1092	u32 gfxpause;
		1093	u32 rpdeuhwtc;
		1094	u32 rpdeuc;
		1095	u32 ecobus;
		1096	u32 pwrdwnupctl;
		1097	u32 rp_down_timeout;
		1098	u32 rp_deucsw;
		1099	u32 rcubmabdtmr;
		1100	u32 rcedata;
		1101	u32 spare2gh;
		1102
		1103	/* Display 1 CZ domain */
		1104	u32 gt_imr;
		1105	u32 gt_ier;
		1106	u32 pm_imr;
		1107	u32 pm_ier;
		1108	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
		1109
		1110	/* GT SA CZ domain */
		1111	u32 tilectl;
		1112	u32 gt_fifoctl;
		1113	u32 gtlc_wake_ctrl;
		1114	u32 gtlc_survive;
		1115	u32 pmwgicz;
		1116
		1117	/* Display 2 CZ domain */
		1118	u32 gu_ctl0;
		1119	u32 gu_ctl1;
6084	serge	1120	u32 pcbr;
5060	serge	1121	u32 clock_gate_dis2;
		1122	};
		1123
		1124	struct intel_rps_ei {
		1125	u32 cz_clock;
		1126	u32 render_c0;
		1127	u32 media_c0;
		1128	};
		1129
3243	Serge	1130	struct intel_gen6_power_mgmt {
5354	serge	1131	/*
		1132	* work, interrupts_enabled and pm_iir are protected by
		1133	* dev_priv->irq_lock
		1134	*/
3243	Serge	1135	struct work_struct work;
5354	serge	1136	bool interrupts_enabled;
3243	Serge	1137	u32 pm_iir;
		1138
5060	serge	1139	/* Frequencies are stored in potentially platform dependent multiples.
		1140	* In other words, *_freq needs to be multiplied by X to be interesting.
		1141	* Soft limits are those which are used for the dynamic reclocking done
		1142	* by the driver (raise frequencies under heavy loads, and lower for
		1143	* lighter loads). Hard limits are those imposed by the hardware.
		1144	*
		1145	* A distinction is made for overclocking, which is never enabled by
		1146	* default, and is considered to be above the hard limit if it's
		1147	* possible at all.
		1148	*/
		1149	u8 cur_freq; /* Current frequency (cached, may not == HW) */
		1150	u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
		1151	u8 max_freq_softlimit; /* Max frequency permitted by the driver */
		1152	u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
		1153	u8 min_freq; /* AKA RPn. Minimum frequency */
6084	serge	1154	u8 idle_freq; /* Frequency to request when we are idle */
5060	serge	1155	u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
		1156	u8 rp1_freq; /* "less than" RP0 power/freqency */
		1157	u8 rp0_freq; /* Non-overclocked max frequency. */
3243	Serge	1158
6084	serge	1159	u8 up_threshold; /* Current %busy required to uplock */
		1160	u8 down_threshold; /* Current %busy required to downclock */
5060	serge	1161
4560	Serge	1162	int last_adj;
		1163	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
		1164
6084	serge	1165	spinlock_t client_lock;
		1166	struct list_head clients;
		1167	bool client_boost;
		1168
4560	Serge	1169	bool enabled;
3243	Serge	1170	struct delayed_work delayed_resume_work;
6084	serge	1171	unsigned boosts;
3243	Serge	1172
6084	serge	1173	struct intel_rps_client semaphores, mmioflips;
		1174
5060	serge	1175	/* manual wa residency calculations */
6935	serge	1176	struct intel_rps_ei ei;
5060	serge	1177
3243	Serge	1178	/*
		1179	* Protects RPS/RC6 register access and PCU communication.
6084	serge	1180	* Must be taken after struct_mutex if nested. Note that
		1181	* this lock may be held for long periods of time when
		1182	* talking to hw - so only take it when talking to hw!
3243	Serge	1183	*/
		1184	struct mutex hw_lock;
		1185	};
		1186
3480	Serge	1187	/* defined intel_pm.c */
		1188	extern spinlock_t mchdev_lock;
		1189
3243	Serge	1190	struct intel_ilk_power_mgmt {
		1191	u8 cur_delay;
		1192	u8 min_delay;
		1193	u8 max_delay;
		1194	u8 fmax;
		1195	u8 fstart;
		1196
		1197	u64 last_count1;
		1198	unsigned long last_time1;
		1199	unsigned long chipset_power;
		1200	u64 last_count2;
5060	serge	1201	u64 last_time2;
3243	Serge	1202	unsigned long gfx_power;
		1203	u8 corr;
		1204
		1205	int c_m;
		1206	int r_t;
		1207	};
		1208
5060	serge	1209	struct drm_i915_private;
		1210	struct i915_power_well;
		1211
		1212	struct i915_power_well_ops {
		1213	/*
		1214	* Synchronize the well's hw state to match the current sw state, for
		1215	* example enable/disable it based on the current refcount. Called
		1216	* during driver init and resume time, possibly after first calling
		1217	* the enable/disable handlers.
		1218	*/
		1219	void (sync_hw)(struct drm_i915_private dev_priv,
		1220	struct i915_power_well *power_well);
		1221	/*
		1222	* Enable the well and resources that depend on it (for example
		1223	* interrupts located on the well). Called after the 0->1 refcount
		1224	* transition.
		1225	*/
		1226	void (enable)(struct drm_i915_private dev_priv,
		1227	struct i915_power_well *power_well);
		1228	/*
		1229	* Disable the well and resources that depend on it. Called after
		1230	* the 1->0 refcount transition.
		1231	*/
		1232	void (disable)(struct drm_i915_private dev_priv,
		1233	struct i915_power_well *power_well);
		1234	/* Returns the hw enabled state. */
		1235	bool (is_enabled)(struct drm_i915_private dev_priv,
		1236	struct i915_power_well *power_well);
		1237	};
		1238
4104	Serge	1239	/* Power well structure for haswell */
		1240	struct i915_power_well {
4560	Serge	1241	const char *name;
		1242	bool always_on;
4104	Serge	1243	/* power well enable/disable usage count */
		1244	int count;
5060	serge	1245	/* cached hw enabled state */
		1246	bool hw_enabled;
4560	Serge	1247	unsigned long domains;
5060	serge	1248	unsigned long data;
		1249	const struct i915_power_well_ops *ops;
4104	Serge	1250	};
		1251
4560	Serge	1252	struct i915_power_domains {
		1253	/*
		1254	* Power wells needed for initialization at driver init and suspend
		1255	* time are on. They are kept on until after the first modeset.
		1256	*/
		1257	bool init_power_on;
5060	serge	1258	bool initializing;
4560	Serge	1259	int power_well_count;
		1260
		1261	struct mutex lock;
		1262	int domain_use_count[POWER_DOMAIN_NUM];
		1263	struct i915_power_well *power_wells;
		1264	};
		1265
		1266	#define MAX_L3_SLICES 2
3243	Serge	1267	struct intel_l3_parity {
4560	Serge	1268	u32 *remap_info[MAX_L3_SLICES];
3243	Serge	1269	struct work_struct error_work;
4560	Serge	1270	int which_slice;
3243	Serge	1271	};
		1272
3480	Serge	1273	struct i915_gem_mm {
		1274	/** Memory allocator for GTT stolen memory */
		1275	struct drm_mm stolen;
6084	serge	1276	/** Protects the usage of the GTT stolen memory allocator. This is
		1277	* always the inner lock when overlapping with struct_mutex. */
		1278	struct mutex stolen_lock;
		1279
3480	Serge	1280	/** List of all objects in gtt_space. Used to restore gtt
		1281	* mappings on resume */
		1282	struct list_head bound_list;
		1283	/**
		1284	* List of objects which are not bound to the GTT (thus
		1285	* are idle and not used by the GPU) but still have
		1286	* (presumably uncached) pages still attached.
		1287	*/
		1288	struct list_head unbound_list;
		1289
		1290	/** Usable portion of the GTT for GEM */
		1291	unsigned long stolen_base; /* limited to low memory (32-bit) */
		1292
		1293	/** PPGTT used for aliasing the PPGTT with the GTT */
		1294	struct i915_hw_ppgtt *aliasing_ppgtt;
		1295
		1296	/** LRU list of objects with fence regs on them. */
		1297	struct list_head fence_list;
		1298
		1299	/**
		1300	* We leave the user IRQ off as much as possible,
		1301	* but this means that requests will finish and never
		1302	* be retired once the system goes idle. Set a timer to
		1303	* fire periodically while the ring is running. When it
		1304	* fires, go retire requests.
		1305	*/
		1306	struct delayed_work retire_work;
		1307
		1308	/**
4560	Serge	1309	* When we detect an idle GPU, we want to turn on
		1310	* powersaving features. So once we see that there
		1311	* are no more requests outstanding and no more
		1312	* arrive within a small period of time, we fire
		1313	* off the idle_work.
		1314	*/
		1315	struct delayed_work idle_work;
		1316
		1317	/**
3480	Serge	1318	* Are we in a non-interruptible section of code like
		1319	* modesetting?
		1320	*/
		1321	bool interruptible;
		1322
5060	serge	1323	/**
		1324	* Is the GPU currently considered idle, or busy executing userspace
		1325	* requests? Whilst idle, we attempt to power down the hardware and
		1326	* display clocks. In order to reduce the effect on performance, there
		1327	* is a slight delay before we do so.
		1328	*/
		1329	bool busy;
		1330
		1331	/* the indicator for dispatch video commands on two BSD rings */
		1332	int bsd_ring_dispatch_index;
		1333
3480	Serge	1334	/** Bit 6 swizzling required for X tiling */
		1335	uint32_t bit_6_swizzle_x;
		1336	/** Bit 6 swizzling required for Y tiling */
		1337	uint32_t bit_6_swizzle_y;
		1338
		1339	/* accounting, useful for userland debugging */
4104	Serge	1340	spinlock_t object_stat_lock;
3480	Serge	1341	size_t object_memory;
		1342	u32 object_count;
		1343	};
		1344
4104	Serge	1345	struct drm_i915_error_state_buf {
5354	serge	1346	struct drm_i915_private *i915;
4104	Serge	1347	unsigned bytes;
		1348	unsigned size;
		1349	int err;
		1350	u8 *buf;
		1351	loff_t start;
		1352	loff_t pos;
		1353	};
		1354
		1355	struct i915_error_state_file_priv {
		1356	struct drm_device *dev;
		1357	struct drm_i915_error_state *error;
		1358	};
		1359
3480	Serge	1360	struct i915_gpu_error {
		1361	/* For hangcheck timer */
		1362	#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
		1363	#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
4560	Serge	1364	/* Hang gpu twice in this window and your context gets banned */
		1365	#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
		1366
6084	serge	1367	struct workqueue_struct *hangcheck_wq;
		1368	struct delayed_work hangcheck_work;
3480	Serge	1369
		1370	/* For reset and error_state handling. */
		1371	spinlock_t lock;
		1372	/* Protected by the above dev->gpu_error.lock. */
		1373	struct drm_i915_error_state *first_error;
		1374
4560	Serge	1375	unsigned long missed_irq_rings;
		1376
3480	Serge	1377	/**
4560	Serge	1378	* State variable controlling the reset flow and count
3480	Serge	1379	*
4560	Serge	1380	* This is a counter which gets incremented when reset is triggered,
		1381	* and again when reset has been handled. So odd values (lowest bit set)
		1382	* means that reset is in progress and even values that
		1383	* (reset_counter >> 1):th reset was successfully completed.
3480	Serge	1384	*
4560	Serge	1385	* If reset is not completed succesfully, the I915_WEDGE bit is
		1386	* set meaning that hardware is terminally sour and there is no
		1387	* recovery. All waiters on the reset_queue will be woken when
		1388	* that happens.
		1389	*
		1390	* This counter is used by the wait_seqno code to notice that reset
		1391	* event happened and it needs to restart the entire ioctl (since most
		1392	* likely the seqno it waited for won't ever signal anytime soon).
		1393	*
3480	Serge	1394	* This is important for lock-free wait paths, where no contended lock
		1395	* naturally enforces the correct ordering between the bail-out of the
		1396	* waiter and the gpu reset work code.
		1397	*/
		1398	atomic_t reset_counter;
		1399
		1400	#define I915_RESET_IN_PROGRESS_FLAG 1
4560	Serge	1401	#define I915_WEDGED (1 << 31)
3480	Serge	1402
		1403	/**
		1404	* Waitqueue to signal when the reset has completed. Used by clients
		1405	* that wait for dev_priv->mm.wedged to settle.
		1406	*/
		1407	wait_queue_head_t reset_queue;
		1408
5060	serge	1409	/* Userspace knobs for gpu hang simulation;
		1410	* combines both a ring mask, and extra flags
		1411	*/
		1412	u32 stop_rings;
		1413	#define I915_STOP_RING_ALLOW_BAN (1 << 31)
		1414	#define I915_STOP_RING_ALLOW_WARN (1 << 30)
4560	Serge	1415
		1416	/* For missed irq/seqno simulation. */
		1417	unsigned int test_irq_rings;
5354	serge	1418
		1419	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
		1420	bool reload_in_reset;
3480	Serge	1421	};
		1422
		1423	enum modeset_restore {
		1424	MODESET_ON_LID_OPEN,
		1425	MODESET_DONE,
		1426	MODESET_SUSPENDED,
		1427	};
		1428
6084	serge	1429	#define DP_AUX_A 0x40
		1430	#define DP_AUX_B 0x10
		1431	#define DP_AUX_C 0x20
		1432	#define DP_AUX_D 0x30
		1433
		1434	#define DDC_PIN_B 0x05
		1435	#define DDC_PIN_C 0x04
		1436	#define DDC_PIN_D 0x06
		1437
4560	Serge	1438	struct ddi_vbt_port_info {
5354	serge	1439	/*
		1440	* This is an index in the HDMI/DVI DDI buffer translation table.
		1441	* The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
		1442	* populate this field.
		1443	*/
		1444	#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
4560	Serge	1445	uint8_t hdmi_level_shift;
		1446
		1447	uint8_t supports_dvi:1;
		1448	uint8_t supports_hdmi:1;
		1449	uint8_t supports_dp:1;
6084	serge	1450
		1451	uint8_t alternate_aux_channel;
		1452	uint8_t alternate_ddc_pin;
		1453
		1454	uint8_t dp_boost_level;
		1455	uint8_t hdmi_boost_level;
4560	Serge	1456	};
		1457
6084	serge	1458	enum psr_lines_to_wait {
		1459	PSR_0_LINES_TO_WAIT = 0,
		1460	PSR_1_LINE_TO_WAIT,
		1461	PSR_4_LINES_TO_WAIT,
		1462	PSR_8_LINES_TO_WAIT
5060	serge	1463	};
		1464
4104	Serge	1465	struct intel_vbt_data {
		1466	struct drm_display_mode lfp_lvds_vbt_mode; / if any */
		1467	struct drm_display_mode sdvo_lvds_vbt_mode; / if any */
		1468
		1469	/* Feature bits */
		1470	unsigned int int_tv_support:1;
		1471	unsigned int lvds_dither:1;
		1472	unsigned int lvds_vbt:1;
		1473	unsigned int int_crt_support:1;
		1474	unsigned int lvds_use_ssc:1;
		1475	unsigned int display_clock_mode:1;
		1476	unsigned int fdi_rx_polarity_inverted:1;
5060	serge	1477	unsigned int has_mipi:1;
4104	Serge	1478	int lvds_ssc_freq;
		1479	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
		1480
5060	serge	1481	enum drrs_support_type drrs_type;
		1482
4104	Serge	1483	/* eDP */
		1484	int edp_rate;
		1485	int edp_lanes;
		1486	int edp_preemphasis;
		1487	int edp_vswing;
		1488	bool edp_initialized;
		1489	bool edp_support;
		1490	int edp_bpp;
		1491	struct edp_power_seq edp_pps;
		1492
4560	Serge	1493	struct {
6084	serge	1494	bool full_link;
		1495	bool require_aux_wakeup;
		1496	int idle_frames;
		1497	enum psr_lines_to_wait lines_to_wait;
		1498	int tp1_wakeup_time;
		1499	int tp2_tp3_wakeup_time;
		1500	} psr;
		1501
		1502	struct {
4560	Serge	1503	u16 pwm_freq_hz;
5060	serge	1504	bool present;
4560	Serge	1505	bool active_low_pwm;
5060	serge	1506	u8 min_brightness; /* min_brightness/255 of max */
4560	Serge	1507	} backlight;
		1508
		1509	/* MIPI DSI */
		1510	struct {
5060	serge	1511	u16 port;
4560	Serge	1512	u16 panel_id;
5060	serge	1513	struct mipi_config *config;
		1514	struct mipi_pps_data *pps;
		1515	u8 seq_version;
		1516	u32 size;
		1517	u8 *data;
		1518	u8 *sequence[MIPI_SEQ_MAX];
4560	Serge	1519	} dsi;
		1520
4104	Serge	1521	int crt_ddc_pin;
		1522
		1523	int child_dev_num;
4560	Serge	1524	union child_device_config *child_dev;
		1525
		1526	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
4104	Serge	1527	};
		1528
		1529	enum intel_ddb_partitioning {
		1530	INTEL_DDB_PART_1_2,
		1531	INTEL_DDB_PART_5_6, /* IVB+ */
		1532	};
		1533
		1534	struct intel_wm_level {
		1535	bool enable;
		1536	uint32_t pri_val;
		1537	uint32_t spr_val;
		1538	uint32_t cur_val;
		1539	uint32_t fbc_val;
		1540	};
		1541
4560	Serge	1542	struct ilk_wm_values {
		1543	uint32_t wm_pipe[3];
		1544	uint32_t wm_lp[3];
		1545	uint32_t wm_lp_spr[3];
		1546	uint32_t wm_linetime[3];
		1547	bool enable_fbc_wm;
		1548	enum intel_ddb_partitioning partitioning;
		1549	};
		1550
6084	serge	1551	struct vlv_pipe_wm {
		1552	uint16_t primary;
		1553	uint16_t sprite[2];
		1554	uint8_t cursor;
		1555	};
		1556
		1557	struct vlv_sr_wm {
		1558	uint16_t plane;
		1559	uint8_t cursor;
		1560	};
		1561
		1562	struct vlv_wm_values {
		1563	struct vlv_pipe_wm pipe[3];
		1564	struct vlv_sr_wm sr;
		1565	struct {
		1566	uint8_t cursor;
		1567	uint8_t sprite[2];
		1568	uint8_t primary;
		1569	} ddl[3];
		1570	uint8_t level;
		1571	bool cxsr;
		1572	};
		1573
5354	serge	1574	struct skl_ddb_entry {
		1575	uint16_t start, end; /* in number of blocks, 'end' is exclusive */
		1576	};
		1577
		1578	static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
		1579	{
		1580	return entry->end - entry->start;
		1581	}
		1582
		1583	static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
		1584	const struct skl_ddb_entry *e2)
		1585	{
		1586	if (e1->start == e2->start && e1->end == e2->end)
		1587	return true;
		1588
		1589	return false;
		1590	}
		1591
		1592	struct skl_ddb_allocation {
		1593	struct skl_ddb_entry pipe[I915_MAX_PIPES];
6084	serge	1594	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
		1595	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
5354	serge	1596	};
		1597
		1598	struct skl_wm_values {
		1599	bool dirty[I915_MAX_PIPES];
		1600	struct skl_ddb_allocation ddb;
		1601	uint32_t wm_linetime[I915_MAX_PIPES];
		1602	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
		1603	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
		1604	};
		1605
		1606	struct skl_wm_level {
		1607	bool plane_en[I915_MAX_PLANES];
		1608	uint16_t plane_res_b[I915_MAX_PLANES];
		1609	uint8_t plane_res_l[I915_MAX_PLANES];
		1610	};
		1611
4104	Serge	1612	/*
5060	serge	1613	* This struct helps tracking the state needed for runtime PM, which puts the
		1614	* device in PCI D3 state. Notice that when this happens, nothing on the
		1615	* graphics device works, even register access, so we don't get interrupts nor
		1616	* anything else.
4104	Serge	1617	*
5060	serge	1618	* Every piece of our code that needs to actually touch the hardware needs to
		1619	* either call intel_runtime_pm_get or call intel_display_power_get with the
		1620	* appropriate power domain.
4104	Serge	1621	*
5060	serge	1622	* Our driver uses the autosuspend delay feature, which means we'll only really
		1623	* suspend if we stay with zero refcount for a certain amount of time. The
5354	serge	1624	* default value is currently very conservative (see intel_runtime_pm_enable), but
5060	serge	1625	* it can be changed with the standard runtime PM files from sysfs.
4104	Serge	1626	*
		1627	* The irqs_disabled variable becomes true exactly after we disable the IRQs and
		1628	* goes back to false exactly before we reenable the IRQs. We use this variable
		1629	* to check if someone is trying to enable/disable IRQs while they're supposed
		1630	* to be disabled. This shouldn't happen and we'll print some error messages in
5060	serge	1631	* case it happens.
4104	Serge	1632	*
5060	serge	1633	* For more, read the Documentation/power/runtime_pm.txt.
4104	Serge	1634	*/
4560	Serge	1635	struct i915_runtime_pm {
		1636	bool suspended;
5354	serge	1637	bool irqs_enabled;
4560	Serge	1638	};
		1639
		1640	enum intel_pipe_crc_source {
		1641	INTEL_PIPE_CRC_SOURCE_NONE,
		1642	INTEL_PIPE_CRC_SOURCE_PLANE1,
		1643	INTEL_PIPE_CRC_SOURCE_PLANE2,
		1644	INTEL_PIPE_CRC_SOURCE_PF,
		1645	INTEL_PIPE_CRC_SOURCE_PIPE,
		1646	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
		1647	INTEL_PIPE_CRC_SOURCE_TV,
		1648	INTEL_PIPE_CRC_SOURCE_DP_B,
		1649	INTEL_PIPE_CRC_SOURCE_DP_C,
		1650	INTEL_PIPE_CRC_SOURCE_DP_D,
		1651	INTEL_PIPE_CRC_SOURCE_AUTO,
		1652	INTEL_PIPE_CRC_SOURCE_MAX,
		1653	};
		1654
		1655	struct intel_pipe_crc_entry {
		1656	uint32_t frame;
		1657	uint32_t crc[5];
		1658	};
		1659
		1660	#define INTEL_PIPE_CRC_ENTRIES_NR 128
		1661	struct intel_pipe_crc {
		1662	spinlock_t lock;
		1663	bool opened; /* exclusive access to the result file */
		1664	struct intel_pipe_crc_entry *entries;
		1665	enum intel_pipe_crc_source source;
		1666	int head, tail;
		1667	wait_queue_head_t wq;
		1668	};
		1669
5060	serge	1670	struct i915_frontbuffer_tracking {
		1671	struct mutex lock;
		1672
		1673	/*
		1674	* Tracking bits for delayed frontbuffer flushing du to gpu activity or
		1675	* scheduled flips.
		1676	*/
		1677	unsigned busy_bits;
		1678	unsigned flip_bits;
		1679	};
		1680
5354	serge	1681	struct i915_wa_reg {
		1682	u32 addr;
		1683	u32 value;
		1684	/* bitmask representing WA bits */
		1685	u32 mask;
		1686	};
		1687
		1688	#define I915_MAX_WA_REGS 16
		1689
		1690	struct i915_workarounds {
		1691	struct i915_wa_reg reg[I915_MAX_WA_REGS];
		1692	u32 count;
		1693	};
		1694
6084	serge	1695	struct i915_virtual_gpu {
		1696	bool active;
		1697	};
		1698
		1699	struct i915_execbuffer_params {
		1700	struct drm_device *dev;
		1701	struct drm_file *file;
		1702	uint32_t dispatch_flags;
		1703	uint32_t args_batch_start_offset;
		1704	uint64_t batch_obj_vm_offset;
		1705	struct intel_engine_cs *ring;
		1706	struct drm_i915_gem_object *batch_obj;
		1707	struct intel_context *ctx;
		1708	struct drm_i915_gem_request *request;
		1709	};
		1710
5060	serge	1711	struct drm_i915_private {
3243	Serge	1712	struct drm_device *dev;
6084	serge	1713	struct kmem_cache *objects;
		1714	struct kmem_cache *vmas;
		1715	struct kmem_cache *requests;
3243	Serge	1716
5060	serge	1717	const struct intel_device_info info;
3243	Serge	1718
		1719	int relative_constants_mode;
		1720
		1721	void __iomem *regs;
		1722
4104	Serge	1723	struct intel_uncore uncore;
3243	Serge	1724
6084	serge	1725	struct i915_virtual_gpu vgpu;
3243	Serge	1726
6084	serge	1727	struct intel_guc guc;
3480	Serge	1728
6084	serge	1729	struct intel_csr csr;
		1730
		1731	/* Display CSR-related protection */
		1732	struct mutex csr_lock;
		1733
		1734	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
		1735
3243	Serge	1736	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
		1737	* controller on different i2c buses. */
		1738	struct mutex gmbus_mutex;
		1739
		1740	/**
		1741	* Base address of the gmbus and gpio block.
		1742	*/
		1743	uint32_t gpio_mmio_base;
		1744
5060	serge	1745	/* MMIO base address for MIPI regs */
		1746	uint32_t mipi_mmio_base;
		1747
3480	Serge	1748	wait_queue_head_t gmbus_wait_queue;
		1749
3243	Serge	1750	struct pci_dev *bridge_dev;
5060	serge	1751	struct intel_engine_cs ring[I915_NUM_RINGS];
		1752	struct drm_i915_gem_object *semaphore_obj;
3480	Serge	1753	uint32_t last_seqno, next_seqno;
3243	Serge	1754
5354	serge	1755	struct drm_dma_handle *status_page_dmah;
3243	Serge	1756	struct resource mch_res;
		1757
		1758	/* protects the irq masks */
		1759	spinlock_t irq_lock;
		1760
5060	serge	1761	/* protects the mmio flip data */
		1762	spinlock_t mmio_flip_lock;
		1763
		1764	bool display_irqs_enabled;
		1765
3480	Serge	1766
6084	serge	1767	/* Sideband mailbox protection */
		1768	struct mutex sb_lock;
3243	Serge	1769
		1770	/** Cached value of IMR to avoid reads in updating the bitfield */
4560	Serge	1771	union {
6084	serge	1772	u32 irq_mask;
4560	Serge	1773	u32 de_irq_mask[I915_MAX_PIPES];
		1774	};
3243	Serge	1775	u32 gt_irq_mask;
4104	Serge	1776	u32 pm_irq_mask;
5060	serge	1777	u32 pm_rps_events;
		1778	u32 pipestat_irq_mask[I915_MAX_PIPES];
3243	Serge	1779
6084	serge	1780	struct i915_hotplug hotplug;
4104	Serge	1781	struct i915_fbc fbc;
5060	serge	1782	struct i915_drrs drrs;
3243	Serge	1783	struct intel_opregion opregion;
4104	Serge	1784	struct intel_vbt_data vbt;
3243	Serge	1785
5354	serge	1786	bool preserve_bios_swizzle;
		1787
3243	Serge	1788	/* overlay */
		1789	struct intel_overlay *overlay;
		1790
4560	Serge	1791	/* backlight registers and fields in struct intel_panel */
5354	serge	1792	struct mutex backlight_lock;
3746	Serge	1793
3243	Serge	1794	/* LVDS info */
		1795	bool no_aux_handshake;
		1796
5354	serge	1797	/* protects panel power sequencer state */
		1798	struct mutex pps_mutex;
		1799
3243	Serge	1800	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
		1801	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
		1802
		1803	unsigned int fsb_freq, mem_freq, is_ddr3;
6084	serge	1804	unsigned int skl_boot_cdclk;
		1805	unsigned int cdclk_freq, max_cdclk_freq;
		1806	unsigned int max_dotclk_freq;
5354	serge	1807	unsigned int hpll_freq;
6084	serge	1808	unsigned int czclk_freq;
3243	Serge	1809
4104	Serge	1810	/**
		1811	* wq - Driver workqueue for GEM.
		1812	*
		1813	* NOTE: Work items scheduled here are not allowed to grab any modeset
		1814	* locks, for otherwise the flushing done in the pageflip code will
		1815	* result in deadlocks.
		1816	*/
3243	Serge	1817	struct workqueue_struct *wq;
		1818
		1819	/* Display functions */
		1820	struct drm_i915_display_funcs display;
		1821
		1822	/* PCH chipset type */
		1823	enum intel_pch pch_type;
		1824	unsigned short pch_id;
		1825
		1826	unsigned long quirks;
		1827
3480	Serge	1828	enum modeset_restore modeset_restore;
		1829	struct mutex modeset_restore_lock;
3243	Serge	1830
4104	Serge	1831	struct list_head vm_list; /* Global list of all address spaces */
5060	serge	1832	struct i915_gtt gtt; /* VM representing the global address space */
2325	Serge	1833
3480	Serge	1834	struct i915_gem_mm mm;
5128	serge	1835	DECLARE_HASHTABLE(mm_structs, 7);
		1836	struct mutex mm_lock;
2325	Serge	1837
3031	serge	1838	/* Kernel Modesetting */
		1839
6084	serge	1840	struct sdvo_device_mapping sdvo_mappings[2];
2325	Serge	1841
5060	serge	1842	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
		1843	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2352	Serge	1844	wait_queue_head_t pending_flip_queue;
2325	Serge	1845
4560	Serge	1846	#ifdef CONFIG_DEBUG_FS
		1847	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
		1848	#endif
		1849
4104	Serge	1850	int num_shared_dpll;
		1851	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
4560	Serge	1852	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
3031	serge	1853
5354	serge	1854	struct i915_workarounds workarounds;
		1855
2325	Serge	1856	/* Reclocking support */
		1857	bool render_reclock_avail;
5060	serge	1858
		1859	struct i915_frontbuffer_tracking fb_tracking;
		1860
2325	Serge	1861	u16 orig_clock;
		1862
		1863	bool mchbar_need_disable;
		1864
3243	Serge	1865	struct intel_l3_parity l3_parity;
		1866
4104	Serge	1867	/* Cannot be determined by PCIID. You must always read a register. */
		1868	size_t ellc_size;
		1869
3031	serge	1870	/* gen6+ rps state */
3243	Serge	1871	struct intel_gen6_power_mgmt rps;
2325	Serge	1872
3031	serge	1873	/* ilk-only ips/rps state. Everything in here is protected by the global
		1874	* mchdev_lock in intel_pm.c */
3243	Serge	1875	struct intel_ilk_power_mgmt ips;
2325	Serge	1876
4560	Serge	1877	struct i915_power_domains power_domains;
2325	Serge	1878
4560	Serge	1879	struct i915_psr psr;
2325	Serge	1880
3480	Serge	1881	struct i915_gpu_error gpu_error;
2325	Serge	1882
4104	Serge	1883	struct drm_i915_gem_object *vlv_pctx;
		1884
6084	serge	1885	#ifdef CONFIG_DRM_FBDEV_EMULATION
2325	Serge	1886	/* list of fbdev register on this device */
6084	serge	1887	struct intel_fbdev *fbdev;
5354	serge	1888	struct work_struct fbdev_suspend_work;
4560	Serge	1889	#endif
2325	Serge	1890
3031	serge	1891	struct drm_property *broadcast_rgb_property;
		1892	struct drm_property *force_audio_property;
		1893
6084	serge	1894	/* hda/i915 audio component */
		1895	struct i915_audio_component *audio_component;
		1896	bool audio_component_registered;
		1897	/**
		1898	* av_mutex - mutex for audio/video sync
		1899	*
		1900	*/
		1901	struct mutex av_mutex;
		1902
3031	serge	1903	uint32_t hw_context_size;
4560	Serge	1904	struct list_head context_list;
3243	Serge	1905
3480	Serge	1906	u32 fdi_rx_config;
3243	Serge	1907
6084	serge	1908	u32 chv_phy_control;
		1909
5060	serge	1910	u32 suspend_count;
3243	Serge	1911	struct i915_suspend_saved_registers regfile;
5060	serge	1912	struct vlv_s0ix_state vlv_s0ix_state;
3243	Serge	1913
4104	Serge	1914	struct {
		1915	/*
		1916	* Raw watermark latency values:
		1917	* in 0.1us units for WM0,
		1918	* in 0.5us units for WM1+.
		1919	*/
		1920	/* primary */
		1921	uint16_t pri_latency[5];
		1922	/* sprite */
		1923	uint16_t spr_latency[5];
		1924	/* cursor */
		1925	uint16_t cur_latency[5];
5354	serge	1926	/*
		1927	* Raw watermark memory latency values
		1928	* for SKL for all 8 levels
		1929	* in 1us units.
		1930	*/
		1931	uint16_t skl_latency[8];
4560	Serge	1932
5354	serge	1933	/*
		1934	* The skl_wm_values structure is a bit too big for stack
		1935	* allocation, so we keep the staging struct where we store
		1936	* intermediate results here instead.
		1937	*/
		1938	struct skl_wm_values skl_results;
		1939
4560	Serge	1940	/* current hardware state */
5354	serge	1941	union {
6084	serge	1942	struct ilk_wm_values hw;
5354	serge	1943	struct skl_wm_values skl_hw;
6084	serge	1944	struct vlv_wm_values vlv;
5354	serge	1945	};
6084	serge	1946
		1947	uint8_t max_level;
4104	Serge	1948	} wm;
		1949
4560	Serge	1950	struct i915_runtime_pm pm;
		1951
5354	serge	1952	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
		1953	struct {
6084	serge	1954	int (execbuf_submit)(struct i915_execbuffer_params params,
		1955	struct drm_i915_gem_execbuffer2 *args,
		1956	struct list_head *vmas);
5354	serge	1957	int (init_rings)(struct drm_device dev);
		1958	void (cleanup_ring)(struct intel_engine_cs ring);
		1959	void (stop_ring)(struct intel_engine_cs ring);
		1960	} gt;
		1961
6084	serge	1962	bool edp_low_vswing;
		1963
		1964	/* perform PHY state sanity checks? */
		1965	bool chv_phy_assert[2];
		1966
5060	serge	1967	/*
		1968	* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
		1969	* will be rejected. Instead look for a better place.
		1970	*/
		1971	};
		1972
4104	Serge	1973	static inline struct drm_i915_private to_i915(const struct drm_device dev)
		1974	{
		1975	return dev->dev_private;
		1976	}
		1977
6084	serge	1978	static inline struct drm_i915_private dev_to_i915(struct device dev)
		1979	{
		1980	return to_i915(dev_get_drvdata(dev));
		1981	}
		1982
		1983	static inline struct drm_i915_private guc_to_i915(struct intel_guc guc)
		1984	{
		1985	return container_of(guc, struct drm_i915_private, guc);
		1986	}
		1987
3031	serge	1988	/* Iterate over initialised rings */
		1989	#define for_each_ring(ring__, dev_priv__, i__) \
		1990	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
		1991	if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
		1992
		1993	enum hdmi_force_audio {
		1994	HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
		1995	HDMI_AUDIO_OFF, /* force turn off HDMI audio */
		1996	HDMI_AUDIO_AUTO, /* trust EDID */
		1997	HDMI_AUDIO_ON, /* force turn on HDMI audio */
		1998	};
		1999
4104	Serge	2000	#define I915_GTT_OFFSET_NONE ((u32)-1)
2325	Serge	2001
3031	serge	2002	struct drm_i915_gem_object_ops {
		2003	/* Interface between the GEM object and its backing storage.
		2004	* get_pages() is called once prior to the use of the associated set
		2005	* of pages before to binding them into the GTT, and put_pages() is
		2006	* called after we no longer need them. As we expect there to be
		2007	* associated cost with migrating pages between the backing storage
		2008	* and making them available for the GPU (e.g. clflush), we may hold
		2009	* onto the pages after they are no longer referenced by the GPU
		2010	* in case they may be used again shortly (for example migrating the
		2011	* pages to a different memory domain within the GTT). put_pages()
		2012	* will therefore most likely be called when the object itself is
		2013	* being released or under memory pressure (where we attempt to
		2014	* reap pages for the shrinker).
		2015	*/
		2016	int (get_pages)(struct drm_i915_gem_object );
		2017	void (put_pages)(struct drm_i915_gem_object );
5060	serge	2018	int (dmabuf_export)(struct drm_i915_gem_object );
		2019	void (release)(struct drm_i915_gem_object );
3031	serge	2020	};
		2021
5060	serge	2022	/*
		2023	* Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
6084	serge	2024	* considered to be the frontbuffer for the given plane interface-wise. This
5060	serge	2025	* doesn't mean that the hw necessarily already scans it out, but that any
		2026	* rendering (by the cpu or gpu) will land in the frontbuffer eventually.
		2027	*
		2028	* We have one bit per pipe and per scanout plane type.
		2029	*/
6084	serge	2030	#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
		2031	#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
5060	serge	2032	#define INTEL_FRONTBUFFER_BITS \
		2033	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
		2034	#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
		2035	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
		2036	#define INTEL_FRONTBUFFER_CURSOR(pipe) \
6084	serge	2037	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
		2038	#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
		2039	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
5060	serge	2040	#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
6084	serge	2041	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
5060	serge	2042	#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
6084	serge	2043	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
5060	serge	2044
2327	Serge	2045	struct drm_i915_gem_object {
6084	serge	2046	struct drm_gem_object base;
2325	Serge	2047
3031	serge	2048	const struct drm_i915_gem_object_ops *ops;
		2049
4104	Serge	2050	/** List of VMAs backed by this object */
		2051	struct list_head vma_list;
		2052
3480	Serge	2053	/** Stolen memory for this object, instead of being backed by shmem. */
		2054	struct drm_mm_node *stolen;
4104	Serge	2055	struct list_head global_list;
2327	Serge	2056
6084	serge	2057	struct list_head ring_list[I915_NUM_RINGS];
4104	Serge	2058	/** Used in execbuf to temporarily hold a ref */
		2059	struct list_head obj_exec_link;
2327	Serge	2060
6084	serge	2061	struct list_head batch_pool_link;
		2062
		2063	/**
3031	serge	2064	* This is set if the object is on the active lists (has pending
		2065	* rendering and so a non-zero seqno), and is not set if it i s on
		2066	* inactive (ready to be unbound) list.
6084	serge	2067	*/
		2068	unsigned int active:I915_NUM_RINGS;
2327	Serge	2069
6084	serge	2070	/**
		2071	* This is set if the object has been written to since last bound
		2072	* to the GTT
		2073	*/
2342	Serge	2074	unsigned int dirty:1;
2327	Serge	2075
6084	serge	2076	/**
		2077	* Fence register bits (if any) for this object. Will be set
		2078	* as needed when mapped into the GTT.
		2079	* Protected by dev->struct_mutex.
		2080	*/
2342	Serge	2081	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2327	Serge	2082
6084	serge	2083	/**
		2084	* Advice: are the backing pages purgeable?
		2085	*/
2342	Serge	2086	unsigned int madv:2;
2327	Serge	2087
6084	serge	2088	/**
		2089	* Current tiling mode for the object.
		2090	*/
2342	Serge	2091	unsigned int tiling_mode:2;
3031	serge	2092	/**
		2093	* Whether the tiling parameters for the currently associated fence
		2094	* register have changed. Note that for the purposes of tracking
		2095	* tiling changes we also treat the unfenced register, the register
		2096	* slot that the object occupies whilst it executes a fenced
		2097	* command (such as BLT on gen2/3), as a "fence".
		2098	*/
		2099	unsigned int fence_dirty:1;
2327	Serge	2100
6084	serge	2101	/**
		2102	* Is the object at the current location in the gtt mappable and
		2103	* fenceable? Used to avoid costly recalculations.
		2104	*/
2342	Serge	2105	unsigned int map_and_fenceable:1;
2327	Serge	2106
6084	serge	2107	/**
		2108	* Whether the current gtt mapping needs to be mappable (and isn't just
		2109	* mappable by accident). Track pin and fault separate for a more
		2110	* accurate mappable working set.
		2111	*/
2342	Serge	2112	unsigned int fault_mappable:1;
2327	Serge	2113
6084	serge	2114	/*
5060	serge	2115	* Is the object to be mapped as read-only to the GPU
		2116	* Only honoured if hardware has relevant pte bit
		2117	*/
		2118	unsigned long gt_ro:1;
4104	Serge	2119	unsigned int cache_level:3;
6084	serge	2120	unsigned int cache_dirty:1;
2327	Serge	2121
5060	serge	2122	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
		2123
6084	serge	2124	unsigned int pin_display;
		2125
3243	Serge	2126	struct sg_table *pages;
3031	serge	2127	int pages_pin_count;
6084	serge	2128	struct get_page {
		2129	struct scatterlist *sg;
		2130	int last;
		2131	} get_page;
2327	Serge	2132
3031	serge	2133	/* prime dma-buf support */
		2134	void *dma_buf_vmapping;
		2135	int vmapping_count;
		2136
6084	serge	2137	/** Breadcrumb of last rendering to the buffer.
		2138	* There can only be one writer, but we allow for multiple readers.
		2139	* If there is a writer that necessarily implies that all other
		2140	* read requests are complete - but we may only be lazily clearing
		2141	* the read requests. A read request is naturally the most recent
		2142	* request on a ring, so we may have two different write and read
		2143	* requests on one ring where the write request is older than the
		2144	* read request. This allows for the CPU to read from an active
		2145	* buffer by only waiting for the write to complete.
		2146	* */
		2147	struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
		2148	struct drm_i915_gem_request *last_write_req;
		2149	/** Breadcrumb of last fenced GPU access to the buffer. */
		2150	struct drm_i915_gem_request *last_fenced_req;
3031	serge	2151
6084	serge	2152	/** Current tiling stride for the object, if it's tiled. */
		2153	uint32_t stride;
2327	Serge	2154
4560	Serge	2155	/** References from framebuffers, locks out tiling changes. */
		2156	unsigned long framebuffer_references;
		2157
6084	serge	2158	/** Record of address bit 17 of each page at last unbind. */
		2159	unsigned long *bit_17;
2327	Serge	2160
5060	serge	2161	struct i915_gem_userptr {
		2162	uintptr_t ptr;
		2163	unsigned read_only :1;
		2164	unsigned workers :4;
		2165	#define I915_GEM_USERPTR_MAX_WORKERS 15
		2166
5128	serge	2167	struct i915_mm_struct *mm;
		2168	struct i915_mmu_object *mmu_object;
5060	serge	2169	struct work_struct *work;
		2170	} userptr;
6935	serge	2171
		2172	/** for phys allocated objects */
		2173	struct drm_dma_handle *phys_handle;
2327	Serge	2174	};
2325	Serge	2175	#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
		2176
5060	serge	2177	void i915_gem_track_fb(struct drm_i915_gem_object *old,
		2178	struct drm_i915_gem_object *new,
		2179	unsigned frontbuffer_bits);
		2180
2325	Serge	2181	/**
		2182	* Request queue structure.
		2183	*
		2184	* The request queue allows us to note sequence numbers that have been emitted
		2185	* and may be associated with active buffers to be retired.
		2186	*
6084	serge	2187	* By keeping this list, we can avoid having to do questionable sequence
		2188	* number comparisons on buffer last_read\|write_seqno. It also allows an
		2189	* emission time to be associated with the request for tracking how far ahead
		2190	* of the GPU the submission is.
		2191	*
		2192	* The requests are reference counted, so upon creation they should have an
		2193	* initial reference taken using kref_init
2325	Serge	2194	*/
		2195	struct drm_i915_gem_request {
6084	serge	2196	struct kref ref;
		2197
2325	Serge	2198	/** On Which ring this request was generated */
6084	serge	2199	struct drm_i915_private *i915;
5060	serge	2200	struct intel_engine_cs *ring;
2325	Serge	2201
6084	serge	2202	/** GEM sequence number associated with the previous request,
		2203	* when the HWS breadcrumb is equal to this the GPU is processing
		2204	* this request.
		2205	*/
		2206	u32 previous_seqno;
2325	Serge	2207
6084	serge	2208	/** GEM sequence number associated with this request,
		2209	* when the HWS breadcrumb is equal or greater than this the GPU
		2210	* has finished processing this request.
		2211	*/
		2212	u32 seqno;
		2213
4104	Serge	2214	/** Position in the ringbuffer of the start of the request */
		2215	u32 head;
		2216
6084	serge	2217	/**
		2218	* Position in the ringbuffer of the start of the postfix.
		2219	* This is required to calculate the maximum available ringbuffer
		2220	* space without overwriting the postfix.
		2221	*/
		2222	u32 postfix;
		2223
		2224	/** Position in the ringbuffer of the end of the whole request */
3031	serge	2225	u32 tail;
		2226
6084	serge	2227	/**
		2228	* Context and ring buffer related to this request
		2229	* Contexts are refcounted, so when this request is associated with a
		2230	* context, we must increment the context's refcount, to guarantee that
		2231	* it persists while any request is linked to it. Requests themselves
		2232	* are also refcounted, so the request will only be freed when the last
		2233	* reference to it is dismissed, and the code in
		2234	* i915_gem_request_free() will then decrement the refcount on the
		2235	* context.
		2236	*/
5060	serge	2237	struct intel_context *ctx;
6084	serge	2238	struct intel_ringbuffer *ringbuf;
4104	Serge	2239
6084	serge	2240	/** Batch buffer related to this request if any (used for
		2241	error state dump only) */
4104	Serge	2242	struct drm_i915_gem_object *batch_obj;
		2243
2325	Serge	2244	/** Time at which this request was emitted, in jiffies. */
		2245	unsigned long emitted_jiffies;
		2246
		2247	/** global list entry for this request */
		2248	struct list_head list;
		2249
		2250	struct drm_i915_file_private *file_priv;
		2251	/** file_priv list entry for this request */
		2252	struct list_head client_list;
		2253
6084	serge	2254	/** process identifier submitting this request */
		2255	struct pid *pid;
4560	Serge	2256
6084	serge	2257	/**
		2258	* The ELSP only accepts two elements at a time, so we queue
		2259	* context/tail pairs on a given queue (ring->execlist_queue) until the
		2260	* hardware is available. The queue serves a double purpose: we also use
		2261	* it to keep track of the up to 2 contexts currently in the hardware
		2262	* (usually one in execution and the other queued up by the GPU): We
		2263	* only remove elements from the head of the queue when the hardware
		2264	* informs us that an element has been completed.
		2265	*
		2266	* All accesses to the queue are mediated by a spinlock
		2267	* (ring->execlist_lock).
		2268	*/
4104	Serge	2269
6084	serge	2270	/** Execlist link in the submission queue.*/
		2271	struct list_head execlist_link;
		2272
		2273	/** Execlists no. of times this request has been sent to the ELSP */
		2274	int elsp_submitted;
		2275
2325	Serge	2276	};
		2277
6084	serge	2278	int i915_gem_request_alloc(struct intel_engine_cs *ring,
		2279	struct intel_context *ctx,
		2280	struct drm_i915_gem_request **req_out);
		2281	void i915_gem_request_cancel(struct drm_i915_gem_request *req);
		2282	void i915_gem_request_free(struct kref *req_ref);
		2283	int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
		2284	struct drm_file *file);
		2285
		2286	static inline uint32_t
		2287	i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
		2288	{
		2289	return req ? req->seqno : 0;
		2290	}
		2291
		2292	static inline struct intel_engine_cs *
		2293	i915_gem_request_get_ring(struct drm_i915_gem_request *req)
		2294	{
		2295	return req ? req->ring : NULL;
		2296	}
		2297
		2298	static inline struct drm_i915_gem_request *
		2299	i915_gem_request_reference(struct drm_i915_gem_request *req)
		2300	{
		2301	if (req)
		2302	kref_get(&req->ref);
		2303	return req;
		2304	}
		2305
		2306	static inline void
		2307	i915_gem_request_unreference(struct drm_i915_gem_request *req)
		2308	{
		2309	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
		2310	kref_put(&req->ref, i915_gem_request_free);
		2311	}
		2312
		2313	static inline void
		2314	i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
		2315	{
		2316	struct drm_device *dev;
		2317
		2318	if (!req)
		2319	return;
		2320
		2321	dev = req->ring->dev;
		2322	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
		2323	mutex_unlock(&dev->struct_mutex);
		2324	}
		2325
		2326	static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
		2327	struct drm_i915_gem_request *src)
		2328	{
		2329	if (src)
		2330	i915_gem_request_reference(src);
		2331
		2332	if (*pdst)
		2333	i915_gem_request_unreference(*pdst);
		2334
		2335	*pdst = src;
		2336	}
		2337
5060	serge	2338	/*
6084	serge	2339	* XXX: i915_gem_request_completed should be here but currently needs the
		2340	* definition of i915_seqno_passed() which is below. It will be moved in
		2341	* a later patch when the call to i915_seqno_passed() is obsoleted...
		2342	*/
		2343
		2344	/*
5060	serge	2345	* A command that requires special handling by the command parser.
		2346	*/
		2347	struct drm_i915_cmd_descriptor {
		2348	/*
		2349	* Flags describing how the command parser processes the command.
		2350	*
		2351	* CMD_DESC_FIXED: The command has a fixed length if this is set,
		2352	* a length mask if not set
		2353	* CMD_DESC_SKIP: The command is allowed but does not follow the
		2354	* standard length encoding for the opcode range in
		2355	* which it falls
		2356	* CMD_DESC_REJECT: The command is never allowed
		2357	* CMD_DESC_REGISTER: The command should be checked against the
		2358	* register whitelist for the appropriate ring
		2359	* CMD_DESC_MASTER: The command is allowed if the submitting process
		2360	* is the DRM master
		2361	*/
		2362	u32 flags;
		2363	#define CMD_DESC_FIXED (1<<0)
		2364	#define CMD_DESC_SKIP (1<<1)
		2365	#define CMD_DESC_REJECT (1<<2)
		2366	#define CMD_DESC_REGISTER (1<<3)
		2367	#define CMD_DESC_BITMASK (1<<4)
		2368	#define CMD_DESC_MASTER (1<<5)
2325	Serge	2369
5060	serge	2370	/*
		2371	* The command's unique identification bits and the bitmask to get them.
		2372	* This isn't strictly the opcode field as defined in the spec and may
		2373	* also include type, subtype, and/or subop fields.
		2374	*/
		2375	struct {
		2376	u32 value;
		2377	u32 mask;
		2378	} cmd;
		2379
		2380	/*
		2381	* The command's length. The command is either fixed length (i.e. does
		2382	* not include a length field) or has a length field mask. The flag
		2383	* CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
		2384	* a length mask. All command entries in a command table must include
		2385	* length information.
		2386	*/
		2387	union {
		2388	u32 fixed;
		2389	u32 mask;
		2390	} length;
		2391
		2392	/*
		2393	* Describes where to find a register address in the command to check
		2394	* against the ring's register whitelist. Only valid if flags has the
		2395	* CMD_DESC_REGISTER bit set.
6084	serge	2396	*
		2397	* A non-zero step value implies that the command may access multiple
		2398	* registers in sequence (e.g. LRI), in that case step gives the
		2399	* distance in dwords between individual offset fields.
5060	serge	2400	*/
		2401	struct {
		2402	u32 offset;
		2403	u32 mask;
6084	serge	2404	u32 step;
5060	serge	2405	} reg;
		2406
		2407	#define MAX_CMD_DESC_BITMASKS 3
		2408	/*
		2409	* Describes command checks where a particular dword is masked and
		2410	* compared against an expected value. If the command does not match
		2411	* the expected value, the parser rejects it. Only valid if flags has
		2412	* the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
		2413	* are valid.
		2414	*
		2415	* If the check specifies a non-zero condition_mask then the parser
		2416	* only performs the check when the bits specified by condition_mask
		2417	* are non-zero.
		2418	*/
		2419	struct {
		2420	u32 offset;
		2421	u32 mask;
		2422	u32 expected;
		2423	u32 condition_offset;
		2424	u32 condition_mask;
		2425	} bits[MAX_CMD_DESC_BITMASKS];
		2426	};
		2427
		2428	/*
		2429	* A table of commands requiring special handling by the command parser.
		2430	*
		2431	* Each ring has an array of tables. Each table consists of an array of command
		2432	* descriptors, which must be sorted with command opcodes in ascending order.
		2433	*/
		2434	struct drm_i915_cmd_table {
		2435	const struct drm_i915_cmd_descriptor *table;
		2436	int count;
		2437	};
		2438
5354	serge	2439	/* Note that the (struct drm_i915_private ) cast is just to shut up gcc. /
		2440	#define __I915__(p) ({ \
		2441	struct drm_i915_private *__p; \
		2442	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		2443	__p = (struct drm_i915_private *)p; \
		2444	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		2445	__p = to_i915((struct drm_device *)p); \
		2446	else \
		2447	BUILD_BUG(); \
		2448	__p; \
		2449	})
		2450	#define INTEL_INFO(p) (&__I915__(p)->info)
		2451	#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
6084	serge	2452	#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
5060	serge	2453
5354	serge	2454	#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
		2455	#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2325	Serge	2456	#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
5354	serge	2457	#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2325	Serge	2458	#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
5354	serge	2459	#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
		2460	#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2325	Serge	2461	#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
		2462	#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
		2463	#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
5354	serge	2464	#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2325	Serge	2465	#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
5354	serge	2466	#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
		2467	#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2325	Serge	2468	#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
		2469	#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
5354	serge	2470	#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2325	Serge	2471	#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
5354	serge	2472	#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 \|\| \
		2473	INTEL_DEVID(dev) == 0x0152 \|\| \
		2474	INTEL_DEVID(dev) == 0x015a)
3031	serge	2475	#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
5060	serge	2476	#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
3031	serge	2477	#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
5060	serge	2478	#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
5354	serge	2479	#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
6084	serge	2480	#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2325	Serge	2481	#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
4104	Serge	2482	#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
5354	serge	2483	(INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
4560	Serge	2484	#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
6084	serge	2485	((INTEL_DEVID(dev) & 0xf) == 0x6 \|\| \
		2486	(INTEL_DEVID(dev) & 0xf) == 0xb \|\| \
5354	serge	2487	(INTEL_DEVID(dev) & 0xf) == 0xe))
6084	serge	2488	/* ULX machines are also considered ULT. */
		2489	#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
		2490	(INTEL_DEVID(dev) & 0xf) == 0xe)
5354	serge	2491	#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
		2492	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
4560	Serge	2493	#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
5354	serge	2494	(INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
4560	Serge	2495	#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
5354	serge	2496	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
5060	serge	2497	/* ULX machines are also considered ULT. */
5354	serge	2498	#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E \|\| \
		2499	INTEL_DEVID(dev) == 0x0A1E)
6084	serge	2500	#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 \|\| \
		2501	INTEL_DEVID(dev) == 0x1913 \|\| \
		2502	INTEL_DEVID(dev) == 0x1916 \|\| \
		2503	INTEL_DEVID(dev) == 0x1921 \|\| \
		2504	INTEL_DEVID(dev) == 0x1926)
		2505	#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E \|\| \
		2506	INTEL_DEVID(dev) == 0x1915 \|\| \
		2507	INTEL_DEVID(dev) == 0x191E)
		2508	#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
		2509	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
		2510	#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
		2511	(INTEL_DEVID(dev) & 0x00F0) == 0x0030)
		2512
4560	Serge	2513	#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2325	Serge	2514
6084	serge	2515	#define SKL_REVID_A0 (0x0)
		2516	#define SKL_REVID_B0 (0x1)
		2517	#define SKL_REVID_C0 (0x2)
		2518	#define SKL_REVID_D0 (0x3)
		2519	#define SKL_REVID_E0 (0x4)
		2520	#define SKL_REVID_F0 (0x5)
		2521
		2522	#define BXT_REVID_A0 (0x0)
		2523	#define BXT_REVID_B0 (0x3)
		2524	#define BXT_REVID_C0 (0x9)
		2525
2325	Serge	2526	/*
		2527	* The genX designation typically refers to the render engine, so render
		2528	* capability related checks should use IS_GEN, while display and other checks
		2529	* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
		2530	* chips, etc.).
		2531	*/
		2532	#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
		2533	#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
		2534	#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
		2535	#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
		2536	#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
		2537	#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
4560	Serge	2538	#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
5354	serge	2539	#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2325	Serge	2540
4560	Serge	2541	#define RENDER_RING (1<
		2542	#define BSD_RING (1<
		2543	#define BLT_RING (1<
		2544	#define VEBOX_RING (1<
5060	serge	2545	#define BSD2_RING (1<
6084	serge	2546	#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
5060	serge	2547	#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
6084	serge	2548	#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
		2549	#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
		2550	#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
5060	serge	2551	#define HAS_WT(dev) ((IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) && \
5354	serge	2552	__I915__(dev)->ellc_size)
2325	Serge	2553	#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
		2554
3031	serge	2555	#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
5354	serge	2556	#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
		2557	#define USES_PPGTT(dev) (i915.enable_ppgtt)
6084	serge	2558	#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
		2559	#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
3031	serge	2560
2325	Serge	2561	#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
		2562	#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
		2563
3243	Serge	2564	/* Early gen2 have a totally busted CS tlb and require pinned batches. */
		2565	#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) \|\| IS_845G(dev))
5060	serge	2566	/*
		2567	* dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
		2568	* even when in MSI mode. This results in spurious interrupt warnings if the
		2569	* legacy irq no. is shared with another device. The kernel then disables that
		2570	* interrupt source and so prevents the other device from working properly.
		2571	*/
		2572	#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
		2573	#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
3243	Serge	2574
2325	Serge	2575	/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
		2576	* rows, which changed the alignment requirements and fence programming.
		2577	*/
		2578	#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) \|\| \
		2579	IS_I915GM(dev)))
		2580	#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
		2581	#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
		2582
		2583	#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
		2584	#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
4560	Serge	2585	#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2325	Serge	2586
5354	serge	2587	#define HAS_IPS(dev) (IS_HSW_ULT(dev) \|\| IS_BROADWELL(dev))
2325	Serge	2588
6084	serge	2589	#define HAS_DP_MST(dev) (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| \
		2590	INTEL_INFO(dev)->gen >= 9)
		2591
4104	Serge	2592	#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
		2593	#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
6084	serge	2594	#define HAS_PSR(dev) (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| \
		2595	IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev) \|\| \
		2596	IS_SKYLAKE(dev))
5060	serge	2597	#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) \|\| IS_HASWELL(dev) \|\| \
6084	serge	2598	IS_BROADWELL(dev) \|\| IS_VALLEYVIEW(dev) \|\| \
		2599	IS_SKYLAKE(dev))
5354	serge	2600	#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
		2601	#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 \|\| IS_IVYBRIDGE(dev))
3480	Serge	2602
6084	serge	2603	#define HAS_CSR(dev) (IS_GEN9(dev))
		2604
		2605	#define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
		2606	#define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
		2607
		2608	#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) \|\| \
		2609	INTEL_INFO(dev)->gen >= 8)
		2610
		2611	#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
		2612	!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
		2613
3243	Serge	2614	#define INTEL_PCH_DEVICE_ID_MASK 0xff00
		2615	#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
		2616	#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
		2617	#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
		2618	#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
		2619	#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
5354	serge	2620	#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
		2621	#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
6084	serge	2622	#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
6320	serge	2623	#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3243	Serge	2624
5354	serge	2625	#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
		2626	#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
3031	serge	2627	#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
6084	serge	2628	#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2325	Serge	2629	#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
		2630	#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
3746	Serge	2631	#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
3031	serge	2632	#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2325	Serge	2633
5060	serge	2634	#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 \|\| IS_VALLEYVIEW(dev))
		2635
4560	Serge	2636	/* DPF == dynamic parity feature */
		2637	#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		2638	#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2325	Serge	2639
3031	serge	2640	#define GT_FREQUENCY_MULTIPLIER 50
6084	serge	2641	#define GEN9_FREQ_SCALER 3
3031	serge	2642
		2643	#include "i915_trace.h"
		2644
6084	serge	2645	extern const struct drm_ioctl_desc i915_ioctls[];
		2646	extern int i915_max_ioctl;
3031	serge	2647
6660	serge	2648	extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
6084	serge	2649	extern int i915_resume_switcheroo(struct drm_device *dev);
2325	Serge	2650
5060	serge	2651	/* i915_params.c */
		2652	struct i915_params {
		2653	int modeset;
		2654	int panel_ignore_lid;
		2655	int semaphores;
		2656	int lvds_channel_mode;
		2657	int panel_use_ssc;
		2658	int vbt_sdvo_panel_type;
		2659	int enable_rc6;
		2660	int enable_fbc;
		2661	int enable_ppgtt;
5354	serge	2662	int enable_execlists;
5060	serge	2663	int enable_psr;
		2664	unsigned int preliminary_hw_support;
		2665	int disable_power_well;
		2666	int enable_ips;
		2667	int invert_brightness;
		2668	int enable_cmd_parser;
		2669	/* leave bools at the end to not create holes */
		2670	bool enable_hangcheck;
		2671	bool fastboot;
		2672	bool prefault_disable;
6084	serge	2673	bool load_detect_test;
5060	serge	2674	bool reset;
		2675	bool disable_display;
		2676	bool disable_vtd_wa;
6084	serge	2677	bool enable_guc_submission;
		2678	int guc_log_level;
5060	serge	2679	int use_mmio_flip;
6084	serge	2680	int mmio_debug;
		2681	bool verbose_state_checks;
		2682	bool nuclear_pageflip;
		2683	int edp_vswing;
6103	serge	2684	/* Kolibri related */
		2685	char *log_file;
		2686	char *cmdline_mode;
5060	serge	2687	};
		2688	extern struct i915_params i915 __read_mostly;
		2689
2325	Serge	2690	/* i915_dma.c */
		2691	extern int i915_driver_load(struct drm_device *, unsigned long flags);
		2692	extern int i915_driver_unload(struct drm_device *);
5060	serge	2693	extern int i915_driver_open(struct drm_device dev, struct drm_file file);
2325	Serge	2694	extern void i915_driver_lastclose(struct drm_device * dev);
		2695	extern void i915_driver_preclose(struct drm_device *dev,
5060	serge	2696	struct drm_file *file);
2325	Serge	2697	extern void i915_driver_postclose(struct drm_device *dev,
5060	serge	2698	struct drm_file *file);
3031	serge	2699	#ifdef CONFIG_COMPAT
2325	Serge	2700	extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
		2701	unsigned long arg);
3031	serge	2702	#endif
		2703	extern int intel_gpu_reset(struct drm_device *dev);
6084	serge	2704	extern bool intel_has_gpu_reset(struct drm_device *dev);
3031	serge	2705	extern int i915_reset(struct drm_device *dev);
2325	Serge	2706	extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
		2707	extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
		2708	extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
		2709	extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
5060	serge	2710	int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
6084	serge	2711	void i915_firmware_load_error_print(const char *fw_path, int err);
		2712
		2713	/* intel_hotplug.c */
		2714	void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
		2715	void intel_hpd_init(struct drm_i915_private *dev_priv);
		2716	void intel_hpd_init_work(struct drm_i915_private *dev_priv);
5060	serge	2717	void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
6084	serge	2718	bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2325	Serge	2719
		2720	/* i915_irq.c */
4104	Serge	2721	void i915_queue_hangcheck(struct drm_device *dev);
5060	serge	2722	__printf(3, 4)
		2723	void i915_handle_error(struct drm_device *dev, bool wedged,
		2724	const char *fmt, ...);
2325	Serge	2725
5354	serge	2726	extern void intel_irq_init(struct drm_i915_private *dev_priv);
		2727	int intel_irq_install(struct drm_i915_private *dev_priv);
		2728	void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2325	Serge	2729
4104	Serge	2730	extern void intel_uncore_sanitize(struct drm_device *dev);
5060	serge	2731	extern void intel_uncore_early_sanitize(struct drm_device *dev,
		2732	bool restore_forcewake);
4104	Serge	2733	extern void intel_uncore_init(struct drm_device *dev);
		2734	extern void intel_uncore_check_errors(struct drm_device *dev);
4560	Serge	2735	extern void intel_uncore_fini(struct drm_device *dev);
5060	serge	2736	extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
6084	serge	2737	const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
		2738	void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
		2739	enum forcewake_domains domains);
		2740	void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
		2741	enum forcewake_domains domains);
		2742	/* Like above but the caller must manage the uncore.lock itself.
		2743	* Must be used with I915_READ_FW and friends.
		2744	*/
		2745	void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
		2746	enum forcewake_domains domains);
		2747	void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
		2748	enum forcewake_domains domains);
		2749	void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
		2750	static inline bool intel_vgpu_active(struct drm_device *dev)
		2751	{
		2752	return to_i915(dev)->vgpu.active;
		2753	}
2325	Serge	2754
		2755	void
5060	serge	2756	i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		2757	u32 status_mask);
2325	Serge	2758
		2759	void
5060	serge	2760	i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		2761	u32 status_mask);
2325	Serge	2762
5060	serge	2763	void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
		2764	void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
6084	serge	2765	void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
		2766	uint32_t mask,
		2767	uint32_t bits);
5354	serge	2768	void
		2769	ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
		2770	void
		2771	ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
		2772	void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
		2773	uint32_t interrupt_mask,
		2774	uint32_t enabled_irq_mask);
		2775	#define ibx_enable_display_interrupt(dev_priv, bits) \
		2776	ibx_display_interrupt_update((dev_priv), (bits), (bits))
		2777	#define ibx_disable_display_interrupt(dev_priv, bits) \
		2778	ibx_display_interrupt_update((dev_priv), (bits), 0)
5060	serge	2779
2325	Serge	2780	/* i915_gem.c */
		2781	int i915_gem_create_ioctl(struct drm_device dev, void data,
		2782	struct drm_file *file_priv);
		2783	int i915_gem_pread_ioctl(struct drm_device dev, void data,
		2784	struct drm_file *file_priv);
		2785	int i915_gem_pwrite_ioctl(struct drm_device dev, void data,
		2786	struct drm_file *file_priv);
		2787	int i915_gem_mmap_ioctl(struct drm_device dev, void data,
		2788	struct drm_file *file_priv);
		2789	int i915_gem_mmap_gtt_ioctl(struct drm_device dev, void data,
		2790	struct drm_file *file_priv);
		2791	int i915_gem_set_domain_ioctl(struct drm_device dev, void data,
		2792	struct drm_file *file_priv);
		2793	int i915_gem_sw_finish_ioctl(struct drm_device dev, void data,
		2794	struct drm_file *file_priv);
5354	serge	2795	void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
6084	serge	2796	struct drm_i915_gem_request *req);
		2797	void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
		2798	int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
5354	serge	2799	struct drm_i915_gem_execbuffer2 *args,
6084	serge	2800	struct list_head *vmas);
2325	Serge	2801	int i915_gem_execbuffer(struct drm_device dev, void data,
		2802	struct drm_file *file_priv);
		2803	int i915_gem_execbuffer2(struct drm_device dev, void data,
		2804	struct drm_file *file_priv);
		2805	int i915_gem_busy_ioctl(struct drm_device dev, void data,
		2806	struct drm_file *file_priv);
3031	serge	2807	int i915_gem_get_caching_ioctl(struct drm_device dev, void data,
		2808	struct drm_file *file);
		2809	int i915_gem_set_caching_ioctl(struct drm_device dev, void data,
		2810	struct drm_file *file);
2325	Serge	2811	int i915_gem_throttle_ioctl(struct drm_device dev, void data,
		2812	struct drm_file *file_priv);
		2813	int i915_gem_madvise_ioctl(struct drm_device dev, void data,
		2814	struct drm_file *file_priv);
		2815	int i915_gem_set_tiling(struct drm_device dev, void data,
		2816	struct drm_file *file_priv);
		2817	int i915_gem_get_tiling(struct drm_device dev, void data,
		2818	struct drm_file *file_priv);
5060	serge	2819	int i915_gem_init_userptr(struct drm_device *dev);
		2820	int i915_gem_userptr_ioctl(struct drm_device dev, void data,
		2821	struct drm_file *file);
2325	Serge	2822	int i915_gem_get_aperture_ioctl(struct drm_device dev, void data,
		2823	struct drm_file *file_priv);
3031	serge	2824	int i915_gem_wait_ioctl(struct drm_device dev, void data,
		2825	struct drm_file *file_priv);
2325	Serge	2826	void i915_gem_load(struct drm_device *dev);
3480	Serge	2827	void i915_gem_object_alloc(struct drm_device dev);
		2828	void i915_gem_object_free(struct drm_i915_gem_object *obj);
3031	serge	2829	void i915_gem_object_init(struct drm_i915_gem_object *obj,
		2830	const struct drm_i915_gem_object_ops *ops);
2325	Serge	2831	struct drm_i915_gem_object i915_gem_alloc_object(struct drm_device dev,
		2832	size_t size);
6084	serge	2833	struct drm_i915_gem_object *i915_gem_object_create_from_data(
		2834	struct drm_device dev, const void data, size_t size);
2325	Serge	2835	void i915_gem_free_object(struct drm_gem_object *obj);
4104	Serge	2836	void i915_gem_vma_destroy(struct i915_vma *vma);
3480	Serge	2837
6084	serge	2838	/* Flags used by pin/bind&friends. */
		2839	#define PIN_MAPPABLE (1<<0)
		2840	#define PIN_NONBLOCK (1<<1)
		2841	#define PIN_GLOBAL (1<<2)
		2842	#define PIN_OFFSET_BIAS (1<<3)
		2843	#define PIN_USER (1<<4)
		2844	#define PIN_UPDATE (1<<5)
		2845	#define PIN_ZONE_4G (1<<6)
		2846	#define PIN_HIGH (1<<7)
5060	serge	2847	#define PIN_OFFSET_MASK (~4095)
6084	serge	2848	int __must_check
		2849	i915_gem_object_pin(struct drm_i915_gem_object *obj,
		2850	struct i915_address_space *vm,
		2851	uint32_t alignment,
		2852	uint64_t flags);
		2853	int __must_check
		2854	i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
		2855	const struct i915_ggtt_view *view,
		2856	uint32_t alignment,
		2857	uint64_t flags);
		2858
		2859	int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		2860	u32 flags);
		2861	void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
4104	Serge	2862	int __must_check i915_vma_unbind(struct i915_vma *vma);
6084	serge	2863	/*
		2864	* BEWARE: Do not use the function below unless you can _absolutely_
		2865	* _guarantee_ VMA in question is _not in use_ anywhere.
		2866	*/
		2867	int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3480	Serge	2868	int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
4560	Serge	2869	void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2325	Serge	2870	void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
		2871
5060	serge	2872	int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
		2873	int *needs_clflush);
		2874
3031	serge	2875	int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
6084	serge	2876
		2877	static inline int __sg_page_count(struct scatterlist *sg)
3031	serge	2878	{
6084	serge	2879	return sg->length >> PAGE_SHIFT;
		2880	}
3031	serge	2881
6084	serge	2882	static inline struct page *
		2883	i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
		2884	{
		2885	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		2886	return NULL;
3746	Serge	2887
6084	serge	2888	if (n < obj->get_page.last) {
		2889	obj->get_page.sg = obj->pages->sgl;
		2890	obj->get_page.last = 0;
		2891	}
		2892
		2893	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		2894	obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		2895	if (unlikely(sg_is_chain(obj->get_page.sg)))
		2896	obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
		2897	}
		2898
		2899	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3243	Serge	2900	}
6084	serge	2901
3031	serge	2902	static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
		2903	{
3243	Serge	2904	BUG_ON(obj->pages == NULL);
3031	serge	2905	obj->pages_pin_count++;
		2906	}
		2907	static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
		2908	{
		2909	BUG_ON(obj->pages_pin_count == 0);
		2910	obj->pages_pin_count--;
		2911	}
		2912
2325	Serge	2913	int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3031	serge	2914	int i915_gem_object_sync(struct drm_i915_gem_object *obj,
6084	serge	2915	struct intel_engine_cs *to,
		2916	struct drm_i915_gem_request **to_req);
4560	Serge	2917	void i915_vma_move_to_active(struct i915_vma *vma,
6084	serge	2918	struct drm_i915_gem_request *req);
2325	Serge	2919	int i915_gem_dumb_create(struct drm_file *file_priv,
		2920	struct drm_device *dev,
		2921	struct drm_mode_create_dumb *args);
		2922	int i915_gem_mmap_gtt(struct drm_file file_priv, struct drm_device dev,
		2923	uint32_t handle, uint64_t *offset);
		2924	/**
		2925	* Returns true if seq1 is later than seq2.
		2926	*/
2340	Serge	2927	static inline bool
		2928	i915_seqno_passed(uint32_t seq1, uint32_t seq2)
		2929	{
		2930	return (int32_t)(seq1 - seq2) >= 0;
		2931	}
2325	Serge	2932
6084	serge	2933	static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
		2934	bool lazy_coherency)
		2935	{
		2936	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
		2937	return i915_seqno_passed(seqno, req->previous_seqno);
		2938	}
		2939
		2940	static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
		2941	bool lazy_coherency)
		2942	{
		2943	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
		2944	return i915_seqno_passed(seqno, req->seqno);
		2945	}
		2946
3480	Serge	2947	int __must_check i915_gem_get_seqno(struct drm_device dev, u32 seqno);
		2948	int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3031	serge	2949
5060	serge	2950	struct drm_i915_gem_request *
		2951	i915_gem_find_active_request(struct intel_engine_cs *ring);
2332	Serge	2952
4560	Serge	2953	bool i915_gem_retire_requests(struct drm_device *dev);
5060	serge	2954	void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3480	Serge	2955	int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3031	serge	2956	bool interruptible);
5060	serge	2957
3480	Serge	2958	static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
		2959	{
		2960	return unlikely(atomic_read(&error->reset_counter)
4560	Serge	2961	& (I915_RESET_IN_PROGRESS_FLAG \| I915_WEDGED));
3480	Serge	2962	}
3031	serge	2963
3480	Serge	2964	static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
		2965	{
4560	Serge	2966	return atomic_read(&error->reset_counter) & I915_WEDGED;
3480	Serge	2967	}
		2968
4560	Serge	2969	static inline u32 i915_reset_count(struct i915_gpu_error *error)
		2970	{
		2971	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
		2972	}
		2973
5060	serge	2974	static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
		2975	{
		2976	return dev_priv->gpu_error.stop_rings == 0 \|\|
		2977	dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
		2978	}
		2979
		2980	static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
		2981	{
		2982	return dev_priv->gpu_error.stop_rings == 0 \|\|
		2983	dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
		2984	}
		2985
2325	Serge	2986	void i915_gem_reset(struct drm_device *dev);
4104	Serge	2987	bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3031	serge	2988	int __must_check i915_gem_init(struct drm_device *dev);
5354	serge	2989	int i915_gem_init_rings(struct drm_device *dev);
3031	serge	2990	int __must_check i915_gem_init_hw(struct drm_device *dev);
6084	serge	2991	int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3031	serge	2992	void i915_gem_init_swizzling(struct drm_device *dev);
2325	Serge	2993	void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
		2994	int __must_check i915_gpu_idle(struct drm_device *dev);
4560	Serge	2995	int __must_check i915_gem_suspend(struct drm_device *dev);
6084	serge	2996	void __i915_add_request(struct drm_i915_gem_request *req,
		2997	struct drm_i915_gem_object *batch_obj,
		2998	bool flush_caches);
		2999	#define i915_add_request(req) \
		3000	__i915_add_request(req, NULL, true)
		3001	#define i915_add_request_no_flush(req) \
		3002	__i915_add_request(req, NULL, false)
		3003	int __i915_wait_request(struct drm_i915_gem_request *req,
5354	serge	3004	unsigned reset_counter,
		3005	bool interruptible,
		3006	s64 *timeout,
6084	serge	3007	struct intel_rps_client *rps);
		3008	int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2325	Serge	3009	int i915_gem_fault(struct vm_area_struct vma, struct vm_fault vmf);
		3010	int __must_check
6084	serge	3011	i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
		3012	bool readonly);
		3013	int __must_check
2325	Serge	3014	i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
		3015	bool write);
		3016	int __must_check
3031	serge	3017	i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
		3018	int __must_check
2325	Serge	3019	i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
		3020	u32 alignment,
6084	serge	3021	struct intel_engine_cs *pipelined,
		3022	struct drm_i915_gem_request **pipelined_request,
		3023	const struct i915_ggtt_view *view);
		3024	void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
		3025	const struct i915_ggtt_view *view);
5060	serge	3026	int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2325	Serge	3027	int align);
4560	Serge	3028	int i915_gem_open(struct drm_device dev, struct drm_file file);
2325	Serge	3029	void i915_gem_release(struct drm_device dev, struct drm_file file);
		3030
		3031	uint32_t
3480	Serge	3032	i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
		3033	uint32_t
		3034	i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
		3035	int tiling_mode, bool fenced);
2325	Serge	3036
		3037	int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
		3038	enum i915_cache_level cache_level);
		3039
4104	Serge	3040	struct drm_gem_object i915_gem_prime_import(struct drm_device dev,
		3041	struct dma_buf *dma_buf);
3031	serge	3042
		3043	struct dma_buf i915_gem_prime_export(struct drm_device dev,
		3044	struct drm_gem_object *gem_obj, int flags);
		3045
6084	serge	3046	u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
		3047	const struct i915_ggtt_view *view);
		3048	u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
		3049	struct i915_address_space *vm);
		3050	static inline u64
		3051	i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
		3052	{
		3053	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
		3054	}
3746	Serge	3055
4104	Serge	3056	bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
6084	serge	3057	bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
		3058	const struct i915_ggtt_view *view);
4104	Serge	3059	bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
		3060	struct i915_address_space *vm);
6084	serge	3061
4104	Serge	3062	unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
		3063	struct i915_address_space *vm);
		3064	struct i915_vma *
6084	serge	3065	i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		3066	struct i915_address_space *vm);
		3067	struct i915_vma *
		3068	i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
		3069	const struct i915_ggtt_view *view);
		3070
		3071	struct i915_vma *
4104	Serge	3072	i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
		3073	struct i915_address_space *vm);
6084	serge	3074	struct i915_vma *
		3075	i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
		3076	const struct i915_ggtt_view *view);
4560	Serge	3077
6084	serge	3078	static inline struct i915_vma *
		3079	i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
		3080	{
		3081	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
5060	serge	3082	}
6084	serge	3083	bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
4560	Serge	3084
4104	Serge	3085	/* Some GGTT VM helpers */
5354	serge	3086	#define i915_obj_to_ggtt(obj) \
4104	Serge	3087	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
		3088	static inline bool i915_is_ggtt(struct i915_address_space *vm)
		3089	{
		3090	struct i915_address_space *ggtt =
		3091	&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
		3092	return vm == ggtt;
		3093	}
		3094
5354	serge	3095	static inline struct i915_hw_ppgtt *
		3096	i915_vm_to_ppgtt(struct i915_address_space *vm)
		3097	{
		3098	WARN_ON(i915_is_ggtt(vm));
		3099
		3100	return container_of(vm, struct i915_hw_ppgtt, base);
		3101	}
		3102
		3103
4104	Serge	3104	static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
		3105	{
6084	serge	3106	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
4104	Serge	3107	}
		3108
		3109	static inline unsigned long
		3110	i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
		3111	{
5354	serge	3112	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
4104	Serge	3113	}
		3114
		3115	static inline int __must_check
		3116	i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		3117	uint32_t alignment,
5060	serge	3118	unsigned flags)
4104	Serge	3119	{
5354	serge	3120	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
		3121	alignment, flags \| PIN_GLOBAL);
4104	Serge	3122	}
		3123
5060	serge	3124	static inline int
		3125	i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
		3126	{
		3127	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
		3128	}
		3129
6084	serge	3130	void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
		3131	const struct i915_ggtt_view *view);
		3132	static inline void
		3133	i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
		3134	{
		3135	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
		3136	}
5060	serge	3137
6084	serge	3138	/* i915_gem_fence.c */
		3139	int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
		3140	int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
		3141
		3142	bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
		3143	void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
		3144
		3145	void i915_gem_restore_fences(struct drm_device *dev);
		3146
		3147	void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
		3148	void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
		3149	void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
		3150
3031	serge	3151	/* i915_gem_context.c */
4560	Serge	3152	int __must_check i915_gem_context_init(struct drm_device *dev);
3031	serge	3153	void i915_gem_context_fini(struct drm_device *dev);
5060	serge	3154	void i915_gem_context_reset(struct drm_device *dev);
		3155	int i915_gem_context_open(struct drm_device dev, struct drm_file file);
6084	serge	3156	int i915_gem_context_enable(struct drm_i915_gem_request *req);
3031	serge	3157	void i915_gem_context_close(struct drm_device dev, struct drm_file file);
6084	serge	3158	int i915_switch_context(struct drm_i915_gem_request *req);
5060	serge	3159	struct intel_context *
		3160	i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
4104	Serge	3161	void i915_gem_context_free(struct kref *ctx_ref);
5354	serge	3162	struct drm_i915_gem_object *
		3163	i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
5060	serge	3164	static inline void i915_gem_context_reference(struct intel_context *ctx)
4104	Serge	3165	{
		3166	kref_get(&ctx->ref);
		3167	}
		3168
5060	serge	3169	static inline void i915_gem_context_unreference(struct intel_context *ctx)
4104	Serge	3170	{
		3171	kref_put(&ctx->ref, i915_gem_context_free);
		3172	}
		3173
5060	serge	3174	static inline bool i915_gem_context_is_default(const struct intel_context *c)
		3175	{
		3176	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
		3177	}
		3178
3031	serge	3179	int i915_gem_context_create_ioctl(struct drm_device dev, void data,
		3180	struct drm_file *file);
		3181	int i915_gem_context_destroy_ioctl(struct drm_device dev, void data,
		3182	struct drm_file *file);
6084	serge	3183	int i915_gem_context_getparam_ioctl(struct drm_device dev, void data,
		3184	struct drm_file *file_priv);
		3185	int i915_gem_context_setparam_ioctl(struct drm_device dev, void data,
		3186	struct drm_file *file_priv);
3031	serge	3187
2325	Serge	3188	/* i915_gem_evict.c */
4104	Serge	3189	int __must_check i915_gem_evict_something(struct drm_device *dev,
		3190	struct i915_address_space *vm,
		3191	int min_size,
3031	serge	3192	unsigned alignment,
		3193	unsigned cache_level,
5060	serge	3194	unsigned long start,
		3195	unsigned long end,
		3196	unsigned flags);
4560	Serge	3197	int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2325	Serge	3198
5060	serge	3199	/* belongs in i915_gem_gtt.h */
		3200	static inline void i915_gem_chipset_flush(struct drm_device *dev)
		3201	{
		3202	if (INTEL_INFO(dev)->gen < 6)
		3203	intel_gtt_chipset_flush();
		3204	}
		3205
3031	serge	3206	/* i915_gem_stolen.c */
6084	serge	3207	int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
		3208	struct drm_mm_node *node, u64 size,
		3209	unsigned alignment);
		3210	int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
		3211	struct drm_mm_node *node, u64 size,
		3212	unsigned alignment, u64 start,
		3213	u64 end);
		3214	void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
		3215	struct drm_mm_node *node);
3031	serge	3216	int i915_gem_init_stolen(struct drm_device *dev);
		3217	void i915_gem_cleanup_stolen(struct drm_device *dev);
3480	Serge	3218	struct drm_i915_gem_object *
		3219	i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3746	Serge	3220	struct drm_i915_gem_object *
		3221	i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
		3222	u32 stolen_offset,
		3223	u32 gtt_offset,
		3224	u32 size);
3031	serge	3225
6084	serge	3226	/* i915_gem_shrinker.c */
		3227	unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
		3228	unsigned long target,
		3229	unsigned flags);
		3230	#define I915_SHRINK_PURGEABLE 0x1
		3231	#define I915_SHRINK_UNBOUND 0x2
		3232	#define I915_SHRINK_BOUND 0x4
		3233	#define I915_SHRINK_ACTIVE 0x8
		3234	unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
		3235	void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
		3236
		3237
2325	Serge	3238	/* i915_gem_tiling.c */
4104	Serge	3239	static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3480	Serge	3240	{
5060	serge	3241	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3480	Serge	3242
		3243	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		3244	obj->tiling_mode != I915_TILING_NONE;
		3245	}
		3246
2325	Serge	3247	/* i915_gem_debug.c */
		3248	#if WATCH_LISTS
		3249	int i915_verify_lists(struct drm_device *dev);
		3250	#else
		3251	#define i915_verify_lists(dev) 0
		3252	#endif
		3253
		3254	/* i915_debugfs.c */
		3255	int i915_debugfs_init(struct drm_minor *minor);
		3256	void i915_debugfs_cleanup(struct drm_minor *minor);
4560	Serge	3257	#ifdef CONFIG_DEBUG_FS
6084	serge	3258	int i915_debugfs_connector_add(struct drm_connector *connector);
4560	Serge	3259	void intel_display_crc_init(struct drm_device *dev);
		3260	#else
6084	serge	3261	static inline int i915_debugfs_connector_add(struct drm_connector *connector)
		3262	{ return 0; }
4560	Serge	3263	static inline void intel_display_crc_init(struct drm_device *dev) {}
		3264	#endif
2325	Serge	3265
4104	Serge	3266	/* i915_gpu_error.c */
		3267	__printf(2, 3)
		3268	void i915_error_printf(struct drm_i915_error_state_buf e, const char f, ...);
		3269	int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
		3270	const struct i915_error_state_file_priv *error);
		3271	int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
5354	serge	3272	struct drm_i915_private *i915,
4104	Serge	3273	size_t count, loff_t pos);
		3274	static inline void i915_error_state_buf_release(
		3275	struct drm_i915_error_state_buf *eb)
		3276	{
		3277	kfree(eb->buf);
		3278	}
5060	serge	3279	void i915_capture_error_state(struct drm_device *dev, bool wedge,
		3280	const char *error_msg);
4104	Serge	3281	void i915_error_state_get(struct drm_device *dev,
		3282	struct i915_error_state_file_priv *error_priv);
		3283	void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
		3284	void i915_destroy_error_state(struct drm_device *dev);
		3285
		3286	void i915_get_extra_instdone(struct drm_device dev, uint32_t instdone);
5354	serge	3287	const char i915_cache_level_str(struct drm_i915_private i915, int type);
4104	Serge	3288
5060	serge	3289	/* i915_cmd_parser.c */
		3290	int i915_cmd_parser_get_version(void);
		3291	int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
		3292	void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
		3293	bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
		3294	int i915_parse_cmds(struct intel_engine_cs *ring,
		3295	struct drm_i915_gem_object *batch_obj,
6084	serge	3296	struct drm_i915_gem_object *shadow_batch_obj,
5060	serge	3297	u32 batch_start_offset,
6084	serge	3298	u32 batch_len,
5060	serge	3299	bool is_master);
		3300
2325	Serge	3301	/* i915_suspend.c */
		3302	extern int i915_save_state(struct drm_device *dev);
		3303	extern int i915_restore_state(struct drm_device *dev);
		3304
3031	serge	3305	/* i915_sysfs.c */
		3306	void i915_setup_sysfs(struct drm_device *dev_priv);
		3307	void i915_teardown_sysfs(struct drm_device *dev_priv);
		3308
2325	Serge	3309	/* intel_i2c.c */
		3310	extern int intel_setup_gmbus(struct drm_device *dev);
		3311	extern void intel_teardown_gmbus(struct drm_device *dev);
6084	serge	3312	extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
		3313	unsigned int pin);
3031	serge	3314
6084	serge	3315	extern struct i2c_adapter *
		3316	intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
2325	Serge	3317	extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
		3318	extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
4104	Serge	3319	static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2342	Serge	3320	{
		3321	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
		3322	}
2325	Serge	3323	extern void intel_i2c_reset(struct drm_device *dev);
		3324
6935	serge	3325	/* intel_bios.c */
		3326	bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
		3327
2325	Serge	3328	/* intel_opregion.c */
4560	Serge	3329	#ifdef CONFIG_ACPI
2325	Serge	3330	extern int intel_opregion_setup(struct drm_device *dev);
		3331	extern void intel_opregion_init(struct drm_device *dev);
		3332	extern void intel_opregion_fini(struct drm_device *dev);
		3333	extern void intel_opregion_asle_intr(struct drm_device *dev);
4560	Serge	3334	extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
		3335	bool enable);
		3336	extern int intel_opregion_notify_adapter(struct drm_device *dev,
		3337	pci_power_t state);
2325	Serge	3338	#else
4560	Serge	3339	static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2325	Serge	3340	static inline void intel_opregion_init(struct drm_device *dev) { return; }
		3341	static inline void intel_opregion_fini(struct drm_device *dev) { return; }
		3342	static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
4560	Serge	3343	static inline int
		3344	intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
		3345	{
		3346	return 0;
		3347	}
		3348	static inline int
		3349	intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
		3350	{
		3351	return 0;
		3352	}
2325	Serge	3353	#endif
		3354
		3355	/* intel_acpi.c */
		3356	#ifdef CONFIG_ACPI
		3357	extern void intel_register_dsm_handler(void);
		3358	extern void intel_unregister_dsm_handler(void);
		3359	#else
		3360	static inline void intel_register_dsm_handler(void) { return; }
		3361	static inline void intel_unregister_dsm_handler(void) { return; }
		3362	#endif /* CONFIG_ACPI */
		3363
		3364	/* modesetting */
3031	serge	3365	extern void intel_modeset_init_hw(struct drm_device *dev);
2325	Serge	3366	extern void intel_modeset_init(struct drm_device *dev);
		3367	extern void intel_modeset_gem_init(struct drm_device *dev);
		3368	extern void intel_modeset_cleanup(struct drm_device *dev);
5060	serge	3369	extern void intel_connector_unregister(struct intel_connector *);
2325	Serge	3370	extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
6084	serge	3371	extern void intel_display_resume(struct drm_device *dev);
3480	Serge	3372	extern void i915_redisable_vga(struct drm_device *dev);
5060	serge	3373	extern void i915_redisable_vga_power_on(struct drm_device *dev);
2325	Serge	3374	extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3243	Serge	3375	extern void intel_init_pch_refclk(struct drm_device *dev);
6084	serge	3376	extern void intel_set_rps(struct drm_device *dev, u8 val);
5060	serge	3377	extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
		3378	bool enable);
2342	Serge	3379	extern void intel_detect_pch(struct drm_device *dev);
		3380	extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3031	serge	3381	extern int intel_enable_rc6(const struct drm_device *dev);
2325	Serge	3382
3031	serge	3383	extern bool i915_semaphore_is_enabled(struct drm_device *dev);
		3384	int i915_reg_read_ioctl(struct drm_device dev, void data,
		3385	struct drm_file *file);
4560	Serge	3386	int i915_get_reset_stats_ioctl(struct drm_device dev, void data,
		3387	struct drm_file *file);
2342	Serge	3388
2325	Serge	3389	/* overlay */
		3390	extern struct intel_overlay_error_state intel_overlay_capture_error_state(struct drm_device dev);
4104	Serge	3391	extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
		3392	struct intel_overlay_error_state *error);
2325	Serge	3393
		3394	extern struct intel_display_error_state intel_display_capture_error_state(struct drm_device dev);
4104	Serge	3395	extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2325	Serge	3396	struct drm_device *dev,
		3397	struct intel_display_error_state *error);
		3398
5354	serge	3399	int sandybridge_pcode_read(struct drm_i915_private dev_priv, u32 mbox, u32 val);
		3400	int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3243	Serge	3401
4104	Serge	3402	/* intel_sideband.c */
6084	serge	3403	u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
		3404	void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
4104	Serge	3405	u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
4560	Serge	3406	u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
		3407	void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3408	u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
		3409	void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3410	u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
		3411	void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3412	u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
		3413	void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3414	u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
		3415	void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3416	u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
		3417	void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
4104	Serge	3418	u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		3419	enum intel_sbi_destination destination);
		3420	void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		3421	enum intel_sbi_destination destination);
4560	Serge	3422	u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
		3423	void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2325	Serge	3424
6084	serge	3425	int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
		3426	int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
4104	Serge	3427
4560	Serge	3428	#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
		3429	#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2325	Serge	3430
4560	Serge	3431	#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
		3432	#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
		3433	#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
		3434	#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
		3435
		3436	#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
		3437	#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
		3438	#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
		3439	#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
		3440
5060	serge	3441	/* Be very careful with read/write 64-bit values. On 32-bit machines, they
		3442	* will be implemented using 2 32-bit writes in an arbitrary order with
		3443	* an arbitrary delay between them. This can cause the hardware to
		3444	* act upon the intermediate value, possibly leading to corruption and
		3445	* machine death. You have been warned.
		3446	*/
4560	Serge	3447	#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
		3448	#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
		3449
5060	serge	3450	#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
6084	serge	3451	u32 upper, lower, old_upper, loop = 0; \
		3452	upper = I915_READ(upper_reg); \
		3453	do { \
		3454	old_upper = upper; \
		3455	lower = I915_READ(lower_reg); \
		3456	upper = I915_READ(upper_reg); \
		3457	} while (upper != old_upper && loop++ < 2); \
		3458	(u64)upper << 32 \| lower; })
5060	serge	3459
2325	Serge	3460	#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
		3461	#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
		3462
6084	serge	3463	/* These are untraced mmio-accessors that are only valid to be used inside
		3464	* criticial sections inside IRQ handlers where forcewake is explicitly
		3465	* controlled.
		3466	* Think twice, and think again, before using these.
		3467	* Note: Should only be used between intel_uncore_forcewake_irqlock() and
		3468	* intel_uncore_forcewake_irqunlock().
		3469	*/
		3470	#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
		3471	#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
		3472	#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
		3473
3480	Serge	3474	/* "Broadcast RGB" property */
		3475	#define INTEL_BROADCAST_RGB_AUTO 0
		3476	#define INTEL_BROADCAST_RGB_FULL 1
		3477	#define INTEL_BROADCAST_RGB_LIMITED 2
		3478
		3479	static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
		3480	{
5060	serge	3481	if (IS_VALLEYVIEW(dev))
		3482	return VLV_VGACNTRL;
		3483	else if (INTEL_INFO(dev)->gen >= 5)
3480	Serge	3484	return CPU_VGACNTRL;
		3485	else
		3486	return VGACNTRL;
		3487	}
		3488
3746	Serge	3489	static inline void __user *to_user_ptr(u64 address)
		3490	{
		3491	return (void __user *)(uintptr_t)address;
		3492	}
		3493
		3494	static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
		3495	{
		3496	unsigned long j = msecs_to_jiffies(m);
		3497
		3498	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
		3499	}
		3500
5354	serge	3501	static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
		3502	{
		3503	return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
		3504	}
		3505
3746	Serge	3506	static inline unsigned long
		3507	timespec_to_jiffies_timeout(const struct timespec *value)
		3508	{
		3509	unsigned long j = timespec_to_jiffies(value);
		3510
		3511	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
		3512	}
		3513
5060	serge	3514	/*
		3515	* If you need to wait X milliseconds between events A and B, but event B
		3516	* doesn't happen exactly after event A, you record the timestamp (jiffies) of
		3517	* when event A happened, then just before event B you call this function and
		3518	* pass the timestamp as the first argument, and X as the second argument.
		3519	*/
		3520	static inline void
		3521	wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4280	Serge	3522	{
5060	serge	3523	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
		3524
		3525	/*
		3526	* Don't re-read the value of "jiffies" every time since it may change
		3527	* behind our back and break the math.
		3528	*/
		3529	tmp_jiffies = jiffies;
		3530	target_jiffies = timestamp_jiffies +
		3531	msecs_to_jiffies_timeout(to_wait_ms);
		3532
		3533	if (time_after(target_jiffies, tmp_jiffies)) {
		3534	remaining_jiffies = target_jiffies - tmp_jiffies;
6103	serge	3535	delay(remaining_jiffies);
5060	serge	3536	}
4280	Serge	3537	}
3746	Serge	3538
6084	serge	3539	static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
		3540	struct drm_i915_gem_request *req)
2338	Serge	3541	{
6084	serge	3542	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
		3543	i915_gem_request_assign(&ring->trace_irq_req, req);
5354	serge	3544	}
		3545
2325	Serge	3546	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.h – Rev 6935