WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_drv.h

Rev	Author	Line No.	Line
2325	Serge	1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --
		2	*/
		3	/*
		4	*
		5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
		6	* All Rights Reserved.
		7	*
		8	* Permission is hereby granted, free of charge, to any person obtaining a
		9	* copy of this software and associated documentation files (the
		10	* "Software"), to deal in the Software without restriction, including
		11	* without limitation the rights to use, copy, modify, merge, publish,
		12	* distribute, sub license, and/or sell copies of the Software, and to
		13	* permit persons to whom the Software is furnished to do so, subject to
		14	* the following conditions:
		15	*
		16	* The above copyright notice and this permission notice (including the
		17	* next paragraph) shall be included in all copies or substantial portions
		18	* of the Software.
		19	*
		20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
		21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
		23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
		24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
		25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
		26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		27	*
		28	*/
		29
		30	#ifndef _I915_DRV_H_
		31	#define _I915_DRV_H_
		32
3480	Serge	33	#include
6084	serge	34	#include
3480	Serge	35
2325	Serge	36	#include "i915_reg.h"
2327	Serge	37	#include "intel_bios.h"
2326	Serge	38	#include "intel_ringbuffer.h"
5354	serge	39	#include "intel_lrc.h"
5060	serge	40	#include "i915_gem_gtt.h"
5354	serge	41	#include "i915_gem_render_state.h"
6084	serge	42	#include
2330	Serge	43	#include
3031	serge	44	#include
2332	Serge	45	#include
5354	serge	46	#include /* for struct drm_dma_handle */
		47	#include
2325	Serge	48	//#include
5060	serge	49	#include
6084	serge	50	#include
		51	#include "intel_guc.h"
2325	Serge	52
		53	#include
3243	Serge	54	#include
2325	Serge	55
6084	serge	56	extern int i915_fbsize;
		57	extern struct drm_i915_gem_object *main_fb_obj;
		58	extern struct drm_framebuffer *main_framebuffer;
2360	Serge	59
6084	serge	60	static struct drm_i915_gem_object *get_fb_obj()
		61	{
		62	return main_fb_obj;
		63	};
		64
		65	#define ioread32(addr) readl(addr)
		66	static inline u8 inb(u16 port)
		67	{
		68	u8 v;
		69	asm volatile("inb %1,%0" : "=a" (v) : "dN" (port));
		70	return v;
		71	}
		72
		73	static inline void outb(u8 v, u16 port)
		74	{
		75	asm volatile("outb %0,%1" : : "a" (v), "dN" (port));
		76	}
		77
		78
2325	Serge	79	/* General customization:
		80	*/
		81
		82	#define DRIVER_NAME "i915"
		83	#define DRIVER_DESC "Intel Graphics"
6084	serge	84	#define DRIVER_DATE "20151010"
2325	Serge	85
5354	serge	86	#undef WARN_ON
6084	serge	87	/* Many gcc seem to no see through this and fall over :( */
		88	#if 0
		89	#define WARN_ON(x) ({ \
		90	bool __i915_warn_cond = (x); \
		91	if (__builtin_constant_p(__i915_warn_cond)) \
		92	BUILD_BUG_ON(__i915_warn_cond); \
		93	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
		94	#else
		95	#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
		96	#endif
5354	serge	97
6084	serge	98	#undef WARN_ON_ONCE
		99	#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
		100
		101	#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
		102	(long) (x), __func__);
		103
		104	/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
		105	* WARN_ON()) for hw state sanity checks to check for unexpected conditions
		106	* which may not necessarily be a user visible problem. This will either
		107	* WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
		108	* enable distros and users to tailor their preferred amount of i915 abrt
		109	* spam.
		110	*/
		111	#define I915_STATE_WARN(condition, format...) ({ \
		112	int __ret_warn_on = !!(condition); \
		113	if (unlikely(__ret_warn_on)) { \
		114	if (i915.verbose_state_checks) \
		115	WARN(1, format); \
		116	else \
		117	DRM_ERROR(format); \
		118	} \
		119	unlikely(__ret_warn_on); \
		120	})
		121
		122	#define I915_STATE_WARN_ON(condition) ({ \
		123	int __ret_warn_on = !!(condition); \
		124	if (unlikely(__ret_warn_on)) { \
		125	if (i915.verbose_state_checks) \
		126	WARN(1, "WARN_ON(" #condition ")\n"); \
		127	else \
		128	DRM_ERROR("WARN_ON(" #condition ")\n"); \
		129	} \
		130	unlikely(__ret_warn_on); \
		131	})
		132
		133	static inline const char *yesno(bool v)
		134	{
		135	return v ? "yes" : "no";
		136	}
		137
2325	Serge	138	enum pipe {
4560	Serge	139	INVALID_PIPE = -1,
2325	Serge	140	PIPE_A = 0,
		141	PIPE_B,
		142	PIPE_C,
5060	serge	143	_PIPE_EDP,
		144	I915_MAX_PIPES = _PIPE_EDP
2325	Serge	145	};
		146	#define pipe_name(p) ((p) + 'A')
		147
3243	Serge	148	enum transcoder {
		149	TRANSCODER_A = 0,
		150	TRANSCODER_B,
		151	TRANSCODER_C,
5060	serge	152	TRANSCODER_EDP,
		153	I915_MAX_TRANSCODERS
3243	Serge	154	};
		155	#define transcoder_name(t) ((t) + 'A')
		156
5354	serge	157	/*
6084	serge	158	* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
		159	* number of planes per CRTC. Not all platforms really have this many planes,
		160	* which means some arrays of size I915_MAX_PLANES may have unused entries
		161	* between the topmost sprite plane and the cursor plane.
5354	serge	162	*/
2325	Serge	163	enum plane {
		164	PLANE_A = 0,
		165	PLANE_B,
		166	PLANE_C,
6084	serge	167	PLANE_CURSOR,
		168	I915_MAX_PLANES,
2325	Serge	169	};
		170	#define plane_name(p) ((p) + 'A')
		171
5060	serge	172	#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
4104	Serge	173
3031	serge	174	enum port {
		175	PORT_A = 0,
		176	PORT_B,
		177	PORT_C,
		178	PORT_D,
		179	PORT_E,
		180	I915_MAX_PORTS
		181	};
		182	#define port_name(p) ((p) + 'A')
		183
5060	serge	184	#define I915_NUM_PHYS_VLV 2
4560	Serge	185
		186	enum dpio_channel {
		187	DPIO_CH0,
		188	DPIO_CH1
		189	};
		190
		191	enum dpio_phy {
		192	DPIO_PHY0,
		193	DPIO_PHY1
		194	};
		195
4104	Serge	196	enum intel_display_power_domain {
		197	POWER_DOMAIN_PIPE_A,
		198	POWER_DOMAIN_PIPE_B,
		199	POWER_DOMAIN_PIPE_C,
		200	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
		201	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
		202	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
		203	POWER_DOMAIN_TRANSCODER_A,
		204	POWER_DOMAIN_TRANSCODER_B,
		205	POWER_DOMAIN_TRANSCODER_C,
4560	Serge	206	POWER_DOMAIN_TRANSCODER_EDP,
5060	serge	207	POWER_DOMAIN_PORT_DDI_A_2_LANES,
		208	POWER_DOMAIN_PORT_DDI_A_4_LANES,
		209	POWER_DOMAIN_PORT_DDI_B_2_LANES,
		210	POWER_DOMAIN_PORT_DDI_B_4_LANES,
		211	POWER_DOMAIN_PORT_DDI_C_2_LANES,
		212	POWER_DOMAIN_PORT_DDI_C_4_LANES,
		213	POWER_DOMAIN_PORT_DDI_D_2_LANES,
		214	POWER_DOMAIN_PORT_DDI_D_4_LANES,
6084	serge	215	POWER_DOMAIN_PORT_DDI_E_2_LANES,
5060	serge	216	POWER_DOMAIN_PORT_DSI,
		217	POWER_DOMAIN_PORT_CRT,
		218	POWER_DOMAIN_PORT_OTHER,
4560	Serge	219	POWER_DOMAIN_VGA,
		220	POWER_DOMAIN_AUDIO,
5060	serge	221	POWER_DOMAIN_PLLS,
6084	serge	222	POWER_DOMAIN_AUX_A,
		223	POWER_DOMAIN_AUX_B,
		224	POWER_DOMAIN_AUX_C,
		225	POWER_DOMAIN_AUX_D,
		226	POWER_DOMAIN_GMBUS,
4560	Serge	227	POWER_DOMAIN_INIT,
		228
		229	POWER_DOMAIN_NUM,
4104	Serge	230	};
		231
		232	#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
		233	#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		234	((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
4560	Serge	235	#define POWER_DOMAIN_TRANSCODER(tran) \
		236	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
		237	(tran) + POWER_DOMAIN_TRANSCODER_A)
4104	Serge	238
3746	Serge	239	enum hpd_pin {
		240	HPD_NONE = 0,
		241	HPD_TV = HPD_NONE, /* TV is known to be unreliable */
		242	HPD_CRT,
		243	HPD_SDVO_B,
		244	HPD_SDVO_C,
6084	serge	245	HPD_PORT_A,
3746	Serge	246	HPD_PORT_B,
		247	HPD_PORT_C,
		248	HPD_PORT_D,
6084	serge	249	HPD_PORT_E,
3746	Serge	250	HPD_NUM_PINS
		251	};
		252
6084	serge	253	#define for_each_hpd_pin(__pin) \
		254	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
		255
		256	struct i915_hotplug {
		257	struct work_struct hotplug_work;
		258
		259	struct {
		260	unsigned long last_jiffies;
		261	int count;
		262	enum {
		263	HPD_ENABLED = 0,
		264	HPD_DISABLED = 1,
		265	HPD_MARK_DISABLED = 2
		266	} state;
		267	} stats[HPD_NUM_PINS];
		268	u32 event_bits;
		269	struct delayed_work reenable_work;
		270
		271	struct intel_digital_port *irq_port[I915_MAX_PORTS];
		272	u32 long_port_mask;
		273	u32 short_port_mask;
		274	struct work_struct dig_port_work;
		275
		276	/*
		277	* if we get a HPD irq from DP and a HPD irq from non-DP
		278	* the non-DP HPD could block the workqueue on a mode config
		279	* mutex getting, that userspace may have taken. However
		280	* userspace is waiting on the DP workqueue to run which is
		281	* blocked behind the non-DP one.
		282	*/
		283	struct workqueue_struct *dp_wq;
		284	};
		285
3480	Serge	286	#define I915_GEM_GPU_DOMAINS \
		287	(I915_GEM_DOMAIN_RENDER \| \
		288	I915_GEM_DOMAIN_SAMPLER \| \
		289	I915_GEM_DOMAIN_COMMAND \| \
		290	I915_GEM_DOMAIN_INSTRUCTION \| \
		291	I915_GEM_DOMAIN_VERTEX)
2325	Serge	292
5354	serge	293	#define for_each_pipe(__dev_priv, __p) \
		294	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
6084	serge	295	#define for_each_plane(__dev_priv, __pipe, __p) \
		296	for ((__p) = 0; \
		297	(__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
		298	(__p)++)
		299	#define for_each_sprite(__dev_priv, __p, __s) \
		300	for ((__s) = 0; \
		301	(__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
		302	(__s)++)
2325	Serge	303
5060	serge	304	#define for_each_crtc(dev, crtc) \
		305	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
		306
6084	serge	307	#define for_each_intel_plane(dev, intel_plane) \
		308	list_for_each_entry(intel_plane, \
		309	&dev->mode_config.plane_list, \
		310	base.head)
		311
		312	#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
		313	list_for_each_entry(intel_plane, \
		314	&(dev)->mode_config.plane_list, \
		315	base.head) \
		316	if ((intel_plane)->pipe == (intel_crtc)->pipe)
		317
5060	serge	318	#define for_each_intel_crtc(dev, intel_crtc) \
		319	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
		320
5354	serge	321	#define for_each_intel_encoder(dev, intel_encoder) \
		322	list_for_each_entry(intel_encoder, \
		323	&(dev)->mode_config.encoder_list, \
		324	base.head)
		325
6084	serge	326	#define for_each_intel_connector(dev, intel_connector) \
		327	list_for_each_entry(intel_connector, \
		328	&dev->mode_config.connector_list, \
		329	base.head)
		330
3031	serge	331	#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
		332	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
		333	if ((intel_encoder)->base.crtc == (__crtc))
		334
5060	serge	335	#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
		336	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
		337	if ((intel_connector)->base.encoder == (__encoder))
		338
		339	#define for_each_power_domain(domain, mask) \
		340	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
		341	if ((1 << (domain)) & (mask))
		342
4104	Serge	343	struct drm_i915_private;
5128	serge	344	struct i915_mm_struct;
5060	serge	345	struct i915_mmu_object;
4104	Serge	346
6084	serge	347	struct drm_i915_file_private {
		348	struct drm_i915_private *dev_priv;
		349	struct drm_file *file;
		350
		351	struct {
		352	spinlock_t lock;
		353	struct list_head request_list;
		354	/* 20ms is a fairly arbitrary limit (greater than the average frame time)
		355	* chosen to prevent the CPU getting more than a frame ahead of the GPU
		356	* (when using lax throttling for the frontbuffer). We also use it to
		357	* offer free GPU waitboosts for severely congested workloads.
		358	*/
		359	#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
		360	} mm;
		361	struct idr context_idr;
		362
		363	struct intel_rps_client {
		364	struct list_head link;
		365	unsigned boosts;
		366	} rps;
		367
		368	struct intel_engine_cs *bsd_ring;
		369	};
		370
4104	Serge	371	enum intel_dpll_id {
		372	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
		373	/* real shared dpll ids must be >= 0 */
5060	serge	374	DPLL_ID_PCH_PLL_A = 0,
		375	DPLL_ID_PCH_PLL_B = 1,
5354	serge	376	/* hsw/bdw */
5060	serge	377	DPLL_ID_WRPLL1 = 0,
		378	DPLL_ID_WRPLL2 = 1,
6084	serge	379	DPLL_ID_SPLL = 2,
		380
5354	serge	381	/* skl */
		382	DPLL_ID_SKL_DPLL1 = 0,
		383	DPLL_ID_SKL_DPLL2 = 1,
		384	DPLL_ID_SKL_DPLL3 = 2,
4104	Serge	385	};
5354	serge	386	#define I915_NUM_PLLS 3
4104	Serge	387
		388	struct intel_dpll_hw_state {
5354	serge	389	/* i9xx, pch plls */
4104	Serge	390	uint32_t dpll;
		391	uint32_t dpll_md;
		392	uint32_t fp0;
		393	uint32_t fp1;
5354	serge	394
		395	/* hsw, bdw */
5060	serge	396	uint32_t wrpll;
6084	serge	397	uint32_t spll;
5354	serge	398
		399	/* skl */
		400	/*
		401	* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
6084	serge	402	* lower part of ctrl1 and they get shifted into position when writing
5354	serge	403	* the register. This allows us to easily compare the state to share
		404	* the DPLL.
		405	*/
		406	uint32_t ctrl1;
		407	/* HDMI only, 0 when used for DP */
		408	uint32_t cfgcr1, cfgcr2;
6084	serge	409
		410	/* bxt */
		411	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
		412	pcsdw12;
4104	Serge	413	};
		414
5354	serge	415	struct intel_shared_dpll_config {
		416	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
		417	struct intel_dpll_hw_state hw_state;
		418	};
		419
4104	Serge	420	struct intel_shared_dpll {
5354	serge	421	struct intel_shared_dpll_config config;
		422
3031	serge	423	int active; /* count of number of active CRTCs (i.e. DPMS on) */
		424	bool on; /* is the PLL actually active? Disabled during modeset */
4104	Serge	425	const char *name;
		426	/* should match the index in the dev_priv->shared_dplls array */
		427	enum intel_dpll_id id;
5060	serge	428	/* The mode_set hook is optional and should be used together with the
		429	* intel_prepare_shared_dpll function. */
4104	Serge	430	void (mode_set)(struct drm_i915_private dev_priv,
		431	struct intel_shared_dpll *pll);
		432	void (enable)(struct drm_i915_private dev_priv,
		433	struct intel_shared_dpll *pll);
		434	void (disable)(struct drm_i915_private dev_priv,
		435	struct intel_shared_dpll *pll);
		436	bool (get_hw_state)(struct drm_i915_private dev_priv,
		437	struct intel_shared_dpll *pll,
		438	struct intel_dpll_hw_state *hw_state);
3031	serge	439	};
		440
5354	serge	441	#define SKL_DPLL0 0
		442	#define SKL_DPLL1 1
		443	#define SKL_DPLL2 2
		444	#define SKL_DPLL3 3
		445
3480	Serge	446	/* Used by dp and fdi links */
		447	struct intel_link_m_n {
		448	uint32_t tu;
		449	uint32_t gmch_m;
		450	uint32_t gmch_n;
		451	uint32_t link_m;
		452	uint32_t link_n;
		453	};
		454
		455	void intel_link_compute_m_n(int bpp, int nlanes,
		456	int pixel_clock, int link_clock,
		457	struct intel_link_m_n *m_n);
		458
2325	Serge	459	/* Interface history:
		460	*
		461	* 1.1: Original.
		462	* 1.2: Add Power Management
		463	* 1.3: Add vblank support
		464	* 1.4: Fix cmdbuffer path, add heap destroy
		465	* 1.5: Add vblank pipe configuration
		466	* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
		467	* - Support vertical blank on secondary display pipe
		468	*/
		469	#define DRIVER_MAJOR 1
		470	#define DRIVER_MINOR 6
		471	#define DRIVER_PATCHLEVEL 0
		472
		473	#define WATCH_LISTS 0
		474
		475	struct opregion_header;
		476	struct opregion_acpi;
		477	struct opregion_swsci;
		478	struct opregion_asle;
		479
		480	struct intel_opregion {
6084	serge	481	struct opregion_header *header;
		482	struct opregion_acpi *acpi;
		483	struct opregion_swsci *swsci;
4560	Serge	484	u32 swsci_gbda_sub_functions;
		485	u32 swsci_sbcb_sub_functions;
6084	serge	486	struct opregion_asle *asle;
		487	void *vbt;
		488	u32 *lid_state;
4560	Serge	489	struct work_struct asle_work;
2325	Serge	490	};
		491	#define OPREGION_SIZE (8*1024)
		492
		493	struct intel_overlay;
		494	struct intel_overlay_error_state;
		495
		496	#define I915_FENCE_REG_NONE -1
3746	Serge	497	#define I915_MAX_NUM_FENCES 32
		498	/* 32 fences + sign bit for FENCE_REG_NONE */
		499	#define I915_MAX_NUM_FENCE_BITS 6
2325	Serge	500
		501	struct drm_i915_fence_reg {
		502	struct list_head lru_list;
		503	struct drm_i915_gem_object *obj;
3031	serge	504	int pin_count;
2325	Serge	505	};
		506
		507	struct sdvo_device_mapping {
		508	u8 initialized;
		509	u8 dvo_port;
		510	u8 slave_addr;
		511	u8 dvo_wiring;
		512	u8 i2c_pin;
		513	u8 ddc_pin;
		514	};
		515
		516	struct intel_display_error_state;
		517
		518	struct drm_i915_error_state {
3243	Serge	519	struct kref ref;
5060	serge	520	struct timeval time;
		521
		522	char error_msg[128];
6084	serge	523	int iommu;
5060	serge	524	u32 reset_count;
		525	u32 suspend_count;
		526
		527	/* Generic register state */
2325	Serge	528	u32 eir;
		529	u32 pgtbl_er;
3031	serge	530	u32 ier;
5060	serge	531	u32 gtier[4];
3031	serge	532	u32 ccid;
3243	Serge	533	u32 derrmr;
		534	u32 forcewake;
2325	Serge	535	u32 error; /* gen6+ */
3031	serge	536	u32 err_int; /* gen7 */
6084	serge	537	u32 fault_data0; /* gen8, gen9 */
		538	u32 fault_data1; /* gen8, gen9 */
5060	serge	539	u32 done_reg;
		540	u32 gac_eco;
		541	u32 gam_ecochk;
		542	u32 gab_ctl;
		543	u32 gfx_mode;
3031	serge	544	u32 extra_instdone[I915_NUM_INSTDONE_REG];
2342	Serge	545	u64 fence[I915_MAX_NUM_FENCES];
5060	serge	546	struct intel_overlay_error_state *overlay;
		547	struct intel_display_error_state *display;
6084	serge	548	struct drm_i915_error_object *semaphore_obj;
5060	serge	549
3031	serge	550	struct drm_i915_error_ring {
4560	Serge	551	bool valid;
5060	serge	552	/* Software tracked state */
		553	bool waiting;
		554	int hangcheck_score;
		555	enum intel_ring_hangcheck_action hangcheck_action;
		556	int num_requests;
		557
		558	/* our own tracking of ring head and tail */
		559	u32 cpu_ring_head;
		560	u32 cpu_ring_tail;
		561
		562	u32 semaphore_seqno[I915_NUM_RINGS - 1];
		563
		564	/* Register state */
6084	serge	565	u32 start;
5060	serge	566	u32 tail;
		567	u32 head;
		568	u32 ctl;
		569	u32 hws;
		570	u32 ipeir;
		571	u32 ipehr;
		572	u32 instdone;
		573	u32 bbstate;
		574	u32 instpm;
		575	u32 instps;
		576	u32 seqno;
		577	u64 bbaddr;
		578	u64 acthd;
		579	u32 fault_reg;
		580	u64 faddr;
		581	u32 rc_psmi; /* sleep state */
		582	u32 semaphore_mboxes[I915_NUM_RINGS - 1];
		583
6084	serge	584	struct drm_i915_error_object {
		585	int page_count;
		586	u64 gtt_offset;
		587	u32 *pages[0];
5060	serge	588	} ringbuffer, batchbuffer, wa_batchbuffer, ctx, *hws_page;
		589
3031	serge	590	struct drm_i915_error_request {
		591	long jiffies;
		592	u32 seqno;
		593	u32 tail;
		594	} *requests;
5060	serge	595
		596	struct {
		597	u32 gfx_mode;
		598	union {
		599	u64 pdp[4];
		600	u32 pp_dir_base;
		601	};
		602	} vm_info;
		603
		604	pid_t pid;
		605	char comm[TASK_COMM_LEN];
3031	serge	606	} ring[I915_NUM_RINGS];
5354	serge	607
2325	Serge	608	struct drm_i915_error_buffer {
		609	u32 size;
		610	u32 name;
6084	serge	611	u32 rseqno[I915_NUM_RINGS], wseqno;
		612	u64 gtt_offset;
2325	Serge	613	u32 read_domains;
		614	u32 write_domain;
2342	Serge	615	s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
2325	Serge	616	s32 pinned:2;
		617	u32 tiling:2;
		618	u32 dirty:1;
		619	u32 purgeable:1;
5060	serge	620	u32 userptr:1;
3031	serge	621	s32 ring:4;
4560	Serge	622	u32 cache_level:3;
4104	Serge	623	} active_bo, pinned_bo;
5060	serge	624
4104	Serge	625	u32 active_bo_count, pinned_bo_count;
5354	serge	626	u32 vm_count;
2325	Serge	627	};
		628
4560	Serge	629	struct intel_connector;
5354	serge	630	struct intel_encoder;
6084	serge	631	struct intel_crtc_state;
		632	struct intel_initial_plane_config;
3746	Serge	633	struct intel_crtc;
4104	Serge	634	struct intel_limit;
		635	struct dpll;
3746	Serge	636
2325	Serge	637	struct drm_i915_display_funcs {
		638	int (get_display_clock_speed)(struct drm_device dev);
		639	int (get_fifo_size)(struct drm_device dev, int plane);
4104	Serge	640	/**
		641	* find_dpll() - Find the best values for the PLL
		642	* @limit: limits for the PLL
		643	* @crtc: current CRTC
		644	* @target: target frequency in kHz
		645	* @refclk: reference clock frequency in kHz
		646	* @match_clock: if provided, @best_clock P divider must
		647	* match the P divider from @match_clock
		648	* used for LVDS downclocking
		649	* @best_clock: best PLL values found
		650	*
		651	* Returns true on success, false on failure.
		652	*/
		653	bool (find_dpll)(const struct intel_limit limit,
6084	serge	654	struct intel_crtc_state *crtc_state,
4104	Serge	655	int target, int refclk,
		656	struct dpll *match_clock,
		657	struct dpll *best_clock);
4560	Serge	658	void (update_wm)(struct drm_crtc crtc);
4104	Serge	659	void (update_sprite_wm)(struct drm_plane plane,
		660	struct drm_crtc *crtc,
5060	serge	661	uint32_t sprite_width, uint32_t sprite_height,
		662	int pixel_size, bool enable, bool scaled);
6084	serge	663	int (modeset_calc_cdclk)(struct drm_atomic_state state);
		664	void (modeset_commit_cdclk)(struct drm_atomic_state state);
3746	Serge	665	/* Returns the active state of the crtc, and if the crtc is active,
		666	* fills out the pipe-config with the hw state. */
		667	bool (get_pipe_config)(struct intel_crtc ,
6084	serge	668	struct intel_crtc_state *);
		669	void (get_initial_plane_config)(struct intel_crtc ,
		670	struct intel_initial_plane_config *);
		671	int (crtc_compute_clock)(struct intel_crtc crtc,
		672	struct intel_crtc_state *crtc_state);
3031	serge	673	void (crtc_enable)(struct drm_crtc crtc);
		674	void (crtc_disable)(struct drm_crtc crtc);
5354	serge	675	void (audio_codec_enable)(struct drm_connector connector,
		676	struct intel_encoder *encoder,
6084	serge	677	const struct drm_display_mode *adjusted_mode);
5354	serge	678	void (audio_codec_disable)(struct intel_encoder encoder);
2325	Serge	679	void (fdi_link_train)(struct drm_crtc crtc);
		680	void (init_clock_gating)(struct drm_device dev);
		681	int (queue_flip)(struct drm_device dev, struct drm_crtc *crtc,
		682	struct drm_framebuffer *fb,
4104	Serge	683	struct drm_i915_gem_object *obj,
6084	serge	684	struct drm_i915_gem_request *req,
4104	Serge	685	uint32_t flags);
5060	serge	686	void (update_primary_plane)(struct drm_crtc crtc,
6084	serge	687	struct drm_framebuffer *fb,
		688	int x, int y);
3480	Serge	689	void (hpd_irq_setup)(struct drm_device dev);
2325	Serge	690	/* clock updates for mode set */
		691	/* cursor updates */
		692	/* render clock increase/decrease */
		693	/* display clock increase/decrease */
		694	/* pll clock increase/decrease */
6084	serge	695	};
4560	Serge	696
6084	serge	697	enum forcewake_domain_id {
		698	FW_DOMAIN_ID_RENDER = 0,
		699	FW_DOMAIN_ID_BLITTER,
		700	FW_DOMAIN_ID_MEDIA,
		701
		702	FW_DOMAIN_ID_COUNT
2325	Serge	703	};
		704
6084	serge	705	enum forcewake_domains {
		706	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
		707	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
		708	FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
		709	FORCEWAKE_ALL = (FORCEWAKE_RENDER \|
		710	FORCEWAKE_BLITTER \|
		711	FORCEWAKE_MEDIA)
		712	};
		713
4104	Serge	714	struct intel_uncore_funcs {
4560	Serge	715	void (force_wake_get)(struct drm_i915_private dev_priv,
6084	serge	716	enum forcewake_domains domains);
4560	Serge	717	void (force_wake_put)(struct drm_i915_private dev_priv,
6084	serge	718	enum forcewake_domains domains);
4560	Serge	719
		720	uint8_t (mmio_readb)(struct drm_i915_private dev_priv, off_t offset, bool trace);
		721	uint16_t (mmio_readw)(struct drm_i915_private dev_priv, off_t offset, bool trace);
		722	uint32_t (mmio_readl)(struct drm_i915_private dev_priv, off_t offset, bool trace);
		723	uint64_t (mmio_readq)(struct drm_i915_private dev_priv, off_t offset, bool trace);
		724
		725	void (mmio_writeb)(struct drm_i915_private dev_priv, off_t offset,
		726	uint8_t val, bool trace);
		727	void (mmio_writew)(struct drm_i915_private dev_priv, off_t offset,
		728	uint16_t val, bool trace);
		729	void (mmio_writel)(struct drm_i915_private dev_priv, off_t offset,
		730	uint32_t val, bool trace);
		731	void (mmio_writeq)(struct drm_i915_private dev_priv, off_t offset,
		732	uint64_t val, bool trace);
3031	serge	733	};
		734
4104	Serge	735	struct intel_uncore {
		736	spinlock_t lock; /** lock is also taken in irq contexts. */
3031	serge	737
4104	Serge	738	struct intel_uncore_funcs funcs;
		739
		740	unsigned fifo_count;
6084	serge	741	enum forcewake_domains fw_domains;
4560	Serge	742
6084	serge	743	struct intel_uncore_forcewake_domain {
		744	struct drm_i915_private *i915;
		745	enum forcewake_domain_id id;
		746	unsigned wake_count;
		747	struct timer_list timer;
		748	u32 reg_set;
		749	u32 val_set;
		750	u32 val_clear;
		751	u32 reg_ack;
		752	u32 reg_post;
		753	u32 val_reset;
		754	} fw_domain[FW_DOMAIN_ID_COUNT];
		755	};
4560	Serge	756
6084	serge	757	/* Iterate over initialised fw domains */
		758	#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
		759	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
		760	(i__) < FW_DOMAIN_ID_COUNT; \
		761	(i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
		762	if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
		763
		764	#define for_each_fw_domain(domain__, dev_priv__, i__) \
		765	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
		766
		767	enum csr_state {
		768	FW_UNINITIALIZED = 0,
		769	FW_LOADED,
		770	FW_FAILED
4104	Serge	771	};
		772
6084	serge	773	struct intel_csr {
		774	const char *fw_path;
		775	uint32_t *dmc_payload;
		776	uint32_t dmc_fw_size;
		777	uint32_t mmio_count;
		778	uint32_t mmioaddr[8];
		779	uint32_t mmiodata[8];
		780	enum csr_state state;
		781	};
		782
4104	Serge	783	#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
		784	func(is_mobile) sep \
		785	func(is_i85x) sep \
		786	func(is_i915g) sep \
		787	func(is_i945gm) sep \
		788	func(is_g33) sep \
		789	func(need_gfx_hws) sep \
		790	func(is_g4x) sep \
		791	func(is_pineview) sep \
		792	func(is_broadwater) sep \
		793	func(is_crestline) sep \
		794	func(is_ivybridge) sep \
		795	func(is_valleyview) sep \
		796	func(is_haswell) sep \
5354	serge	797	func(is_skylake) sep \
4560	Serge	798	func(is_preliminary) sep \
4104	Serge	799	func(has_fbc) sep \
		800	func(has_pipe_cxsr) sep \
		801	func(has_hotplug) sep \
		802	func(cursor_needs_physical) sep \
		803	func(has_overlay) sep \
		804	func(overlay_needs_physical) sep \
		805	func(supports_tv) sep \
		806	func(has_llc) sep \
		807	func(has_ddi) sep \
		808	func(has_fpga_dbg)
		809
		810	#define DEFINE_FLAG(name) u8 name:1
		811	#define SEP_SEMICOLON ;
		812
2325	Serge	813	struct intel_device_info {
3480	Serge	814	u32 display_mmio_offset;
5354	serge	815	u16 device_id;
3746	Serge	816	u8 num_pipes:3;
5060	serge	817	u8 num_sprites[I915_MAX_PIPES];
2325	Serge	818	u8 gen;
4560	Serge	819	u8 ring_mask; /* Rings supported by the HW */
4104	Serge	820	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
5060	serge	821	/* Register offsets for the various display pipes and transcoders */
		822	int pipe_offsets[I915_MAX_TRANSCODERS];
		823	int trans_offsets[I915_MAX_TRANSCODERS];
		824	int palette_offsets[I915_MAX_PIPES];
		825	int cursor_offsets[I915_MAX_PIPES];
6084	serge	826
		827	/* Slice/subslice/EU info */
		828	u8 slice_total;
		829	u8 subslice_total;
		830	u8 subslice_per_slice;
		831	u8 eu_total;
		832	u8 eu_per_subslice;
		833	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
		834	u8 subslice_7eu[3];
		835	u8 has_slice_pg:1;
		836	u8 has_subslice_pg:1;
		837	u8 has_eu_pg:1;
2325	Serge	838	};
		839
4104	Serge	840	#undef DEFINE_FLAG
		841	#undef SEP_SEMICOLON
		842
3480	Serge	843	enum i915_cache_level {
		844	I915_CACHE_NONE = 0,
4104	Serge	845	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
		846	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
		847	caches, eg sampler/render caches, and the
		848	large Last-Level-Cache. LLC is coherent with
		849	the CPU, but L3 is only visible to the GPU. */
		850	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
3480	Serge	851	};
		852
4104	Serge	853	struct i915_ctx_hang_stats {
		854	/* This context had batch pending when hang was declared */
		855	unsigned batch_pending;
		856
		857	/* This context had batch active when hang was declared */
		858	unsigned batch_active;
4560	Serge	859
		860	/* Time when this context was last blamed for a GPU reset */
		861	unsigned long guilty_ts;
		862
6084	serge	863	/* If the contexts causes a second GPU hang within this time,
		864	* it is permanently banned from submitting any more work.
		865	*/
		866	unsigned long ban_period_seconds;
		867
4560	Serge	868	/* This context is banned to submit more work */
		869	bool banned;
4104	Serge	870	};
		871
3031	serge	872	/* This must match up with the value previously used for execbuf2.rsvd1. */
5060	serge	873	#define DEFAULT_CONTEXT_HANDLE 0
6084	serge	874
		875	#define CONTEXT_NO_ZEROMAP (1<<0)
5060	serge	876	/**
		877	* struct intel_context - as the name implies, represents a context.
		878	* @ref: reference count.
		879	* @user_handle: userspace tracking identity for this context.
		880	* @remap_slice: l3 row remapping information.
6084	serge	881	* @flags: context specific flags:
		882	* CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
5060	serge	883	* @file_priv: filp associated with this context (NULL for global default
		884	* context).
		885	* @hang_stats: information about the role of this context in possible GPU
		886	* hangs.
6084	serge	887	* @ppgtt: virtual memory space used by this context.
5060	serge	888	* @legacy_hw_ctx: render context backing object and whether it is correctly
		889	* initialized (legacy ring submission mechanism only).
		890	* @link: link in the global list of contexts.
		891	*
		892	* Contexts are memory images used by the hardware to store copies of their
		893	* internal state.
		894	*/
		895	struct intel_context {
4104	Serge	896	struct kref ref;
5060	serge	897	int user_handle;
4560	Serge	898	uint8_t remap_slice;
6084	serge	899	struct drm_i915_private *i915;
		900	int flags;
3031	serge	901	struct drm_i915_file_private *file_priv;
4104	Serge	902	struct i915_ctx_hang_stats hang_stats;
5354	serge	903	struct i915_hw_ppgtt *ppgtt;
4560	Serge	904
5354	serge	905	/* Legacy ring buffer submission */
5060	serge	906	struct {
		907	struct drm_i915_gem_object *rcs_state;
		908	bool initialized;
		909	} legacy_hw_ctx;
		910
5354	serge	911	/* Execlists */
		912	struct {
		913	struct drm_i915_gem_object *state;
		914	struct intel_ringbuffer *ringbuf;
6084	serge	915	int pin_count;
5354	serge	916	} engine[I915_NUM_RINGS];
		917
4560	Serge	918	struct list_head link;
3031	serge	919	};
		920
6084	serge	921	enum fb_op_origin {
		922	ORIGIN_GTT,
		923	ORIGIN_CPU,
		924	ORIGIN_CS,
		925	ORIGIN_FLIP,
		926	ORIGIN_DIRTYFB,
		927	};
		928
4104	Serge	929	struct i915_fbc {
6084	serge	930	/* This is always the inner lock when overlapping with struct_mutex and
		931	* it's the outer lock when overlapping with stolen_lock. */
		932	struct mutex lock;
		933	unsigned long uncompressed_size;
5060	serge	934	unsigned threshold;
4104	Serge	935	unsigned int fb_id;
6084	serge	936	unsigned int possible_framebuffer_bits;
		937	unsigned int busy_bits;
		938	struct intel_crtc *crtc;
4104	Serge	939	int y;
		940
5060	serge	941	struct drm_mm_node compressed_fb;
4104	Serge	942	struct drm_mm_node *compressed_llb;
		943
5354	serge	944	bool false_color;
		945
		946	/* Tracks whether the HW is actually enabled, not whether the feature is
		947	* possible. */
		948	bool enabled;
		949
4104	Serge	950	struct intel_fbc_work {
		951	struct delayed_work work;
6084	serge	952	struct intel_crtc *crtc;
4104	Serge	953	struct drm_framebuffer *fb;
		954	} *fbc_work;
		955
4539	Serge	956	enum no_fbc_reason {
4104	Serge	957	FBC_OK, /* FBC is enabled */
		958	FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
6084	serge	959	FBC_NO_OUTPUT, /* no outputs enabled to compress */
4104	Serge	960	FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
6084	serge	961	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
		962	FBC_MODE_TOO_LARGE, /* mode too large for compression */
		963	FBC_BAD_PLANE, /* fbc not supported on plane */
		964	FBC_NOT_TILED, /* buffer not tiled */
		965	FBC_MULTIPLE_PIPES, /* more than one pipe active */
		966	FBC_MODULE_PARAM,
4104	Serge	967	FBC_CHIP_DEFAULT, /* disabled by default on this chip */
6084	serge	968	FBC_ROTATION, /* rotation is not supported */
		969	FBC_IN_DBG_MASTER, /* kernel debugger is active */
		970	FBC_BAD_STRIDE, /* stride is not supported */
		971	FBC_PIXEL_RATE, /* pixel rate is too big */
		972	FBC_PIXEL_FORMAT /* pixel format is invalid */
4104	Serge	973	} no_fbc_reason;
6084	serge	974
		975	bool (fbc_enabled)(struct drm_i915_private dev_priv);
		976	void (enable_fbc)(struct intel_crtc crtc);
		977	void (disable_fbc)(struct drm_i915_private dev_priv);
2325	Serge	978	};
		979
6084	serge	980	/**
		981	* HIGH_RR is the highest eDP panel refresh rate read from EDID
		982	* LOW_RR is the lowest eDP panel refresh rate found from EDID
		983	* parsing for same resolution.
		984	*/
		985	enum drrs_refresh_rate_type {
		986	DRRS_HIGH_RR,
		987	DRRS_LOW_RR,
		988	DRRS_MAX_RR, /* RR count */
		989	};
		990
		991	enum drrs_support_type {
		992	DRRS_NOT_SUPPORTED = 0,
		993	STATIC_DRRS_SUPPORT = 1,
		994	SEAMLESS_DRRS_SUPPORT = 2
		995	};
		996
		997	struct intel_dp;
5060	serge	998	struct i915_drrs {
6084	serge	999	struct mutex mutex;
		1000	struct delayed_work work;
		1001	struct intel_dp *dp;
		1002	unsigned busy_frontbuffer_bits;
		1003	enum drrs_refresh_rate_type refresh_rate_type;
		1004	enum drrs_support_type type;
5060	serge	1005	};
		1006
4560	Serge	1007	struct i915_psr {
5060	serge	1008	struct mutex lock;
4560	Serge	1009	bool sink_support;
		1010	bool source_ok;
5060	serge	1011	struct intel_dp *enabled;
		1012	bool active;
		1013	struct delayed_work work;
		1014	unsigned busy_frontbuffer_bits;
6084	serge	1015	bool psr2_support;
		1016	bool aux_frame_sync;
4104	Serge	1017	};
		1018
2325	Serge	1019	enum intel_pch {
3031	serge	1020	PCH_NONE = 0, /* No PCH present */
2325	Serge	1021	PCH_IBX, /* Ibexpeak PCH */
		1022	PCH_CPT, /* Cougarpoint PCH */
3031	serge	1023	PCH_LPT, /* Lynxpoint PCH */
5354	serge	1024	PCH_SPT, /* Sunrisepoint PCH */
3746	Serge	1025	PCH_NOP,
2325	Serge	1026	};
		1027
3243	Serge	1028	enum intel_sbi_destination {
		1029	SBI_ICLK,
		1030	SBI_MPHY,
		1031	};
		1032
2325	Serge	1033	#define QUIRK_PIPEA_FORCE (1<<0)
		1034	#define QUIRK_LVDS_SSC_DISABLE (1<<1)
3031	serge	1035	#define QUIRK_INVERT_BRIGHTNESS (1<<2)
5060	serge	1036	#define QUIRK_BACKLIGHT_PRESENT (1<<3)
5354	serge	1037	#define QUIRK_PIPEB_FORCE (1<<4)
		1038	#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
2325	Serge	1039
		1040	struct intel_fbdev;
		1041	struct intel_fbc_work;
		1042
3031	serge	1043	struct intel_gmbus {
		1044	struct i2c_adapter adapter;
3243	Serge	1045	u32 force_bit;
3031	serge	1046	u32 reg0;
		1047	u32 gpio_reg;
		1048	struct i2c_algo_bit_data bit_algo;
		1049	struct drm_i915_private *dev_priv;
		1050	};
		1051
3243	Serge	1052	struct i915_suspend_saved_registers {
2325	Serge	1053	u32 saveDSPARB;
		1054	u32 saveLVDS;
		1055	u32 savePP_ON_DELAYS;
		1056	u32 savePP_OFF_DELAYS;
		1057	u32 savePP_ON;
		1058	u32 savePP_OFF;
		1059	u32 savePP_CONTROL;
		1060	u32 savePP_DIVISOR;
		1061	u32 saveFBC_CONTROL;
		1062	u32 saveCACHE_MODE_0;
		1063	u32 saveMI_ARB_STATE;
		1064	u32 saveSWF0[16];
		1065	u32 saveSWF1[16];
6084	serge	1066	u32 saveSWF3[3];
2342	Serge	1067	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
2325	Serge	1068	u32 savePCH_PORT_HOTPLUG;
5354	serge	1069	u16 saveGCDGMBUS;
3243	Serge	1070	};
2325	Serge	1071
5060	serge	1072	struct vlv_s0ix_state {
		1073	/* GAM */
		1074	u32 wr_watermark;
		1075	u32 gfx_prio_ctrl;
		1076	u32 arb_mode;
		1077	u32 gfx_pend_tlb0;
		1078	u32 gfx_pend_tlb1;
		1079	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
		1080	u32 media_max_req_count;
		1081	u32 gfx_max_req_count;
		1082	u32 render_hwsp;
		1083	u32 ecochk;
		1084	u32 bsd_hwsp;
		1085	u32 blt_hwsp;
		1086	u32 tlb_rd_addr;
		1087
		1088	/* MBC */
		1089	u32 g3dctl;
		1090	u32 gsckgctl;
		1091	u32 mbctl;
		1092
		1093	/* GCP */
		1094	u32 ucgctl1;
		1095	u32 ucgctl3;
		1096	u32 rcgctl1;
		1097	u32 rcgctl2;
		1098	u32 rstctl;
		1099	u32 misccpctl;
		1100
		1101	/* GPM */
		1102	u32 gfxpause;
		1103	u32 rpdeuhwtc;
		1104	u32 rpdeuc;
		1105	u32 ecobus;
		1106	u32 pwrdwnupctl;
		1107	u32 rp_down_timeout;
		1108	u32 rp_deucsw;
		1109	u32 rcubmabdtmr;
		1110	u32 rcedata;
		1111	u32 spare2gh;
		1112
		1113	/* Display 1 CZ domain */
		1114	u32 gt_imr;
		1115	u32 gt_ier;
		1116	u32 pm_imr;
		1117	u32 pm_ier;
		1118	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
		1119
		1120	/* GT SA CZ domain */
		1121	u32 tilectl;
		1122	u32 gt_fifoctl;
		1123	u32 gtlc_wake_ctrl;
		1124	u32 gtlc_survive;
		1125	u32 pmwgicz;
		1126
		1127	/* Display 2 CZ domain */
		1128	u32 gu_ctl0;
		1129	u32 gu_ctl1;
6084	serge	1130	u32 pcbr;
5060	serge	1131	u32 clock_gate_dis2;
		1132	};
		1133
		1134	struct intel_rps_ei {
		1135	u32 cz_clock;
		1136	u32 render_c0;
		1137	u32 media_c0;
		1138	};
		1139
3243	Serge	1140	struct intel_gen6_power_mgmt {
5354	serge	1141	/*
		1142	* work, interrupts_enabled and pm_iir are protected by
		1143	* dev_priv->irq_lock
		1144	*/
3243	Serge	1145	struct work_struct work;
5354	serge	1146	bool interrupts_enabled;
3243	Serge	1147	u32 pm_iir;
		1148
5060	serge	1149	/* Frequencies are stored in potentially platform dependent multiples.
		1150	* In other words, *_freq needs to be multiplied by X to be interesting.
		1151	* Soft limits are those which are used for the dynamic reclocking done
		1152	* by the driver (raise frequencies under heavy loads, and lower for
		1153	* lighter loads). Hard limits are those imposed by the hardware.
		1154	*
		1155	* A distinction is made for overclocking, which is never enabled by
		1156	* default, and is considered to be above the hard limit if it's
		1157	* possible at all.
		1158	*/
		1159	u8 cur_freq; /* Current frequency (cached, may not == HW) */
		1160	u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
		1161	u8 max_freq_softlimit; /* Max frequency permitted by the driver */
		1162	u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
		1163	u8 min_freq; /* AKA RPn. Minimum frequency */
6084	serge	1164	u8 idle_freq; /* Frequency to request when we are idle */
5060	serge	1165	u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
		1166	u8 rp1_freq; /* "less than" RP0 power/freqency */
		1167	u8 rp0_freq; /* Non-overclocked max frequency. */
3243	Serge	1168
6084	serge	1169	u8 up_threshold; /* Current %busy required to uplock */
		1170	u8 down_threshold; /* Current %busy required to downclock */
5060	serge	1171
4560	Serge	1172	int last_adj;
		1173	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
		1174
6084	serge	1175	spinlock_t client_lock;
		1176	struct list_head clients;
		1177	bool client_boost;
		1178
4560	Serge	1179	bool enabled;
3243	Serge	1180	struct delayed_work delayed_resume_work;
6084	serge	1181	unsigned boosts;
3243	Serge	1182
6084	serge	1183	struct intel_rps_client semaphores, mmioflips;
		1184
5060	serge	1185	/* manual wa residency calculations */
		1186	struct intel_rps_ei up_ei, down_ei;
		1187
3243	Serge	1188	/*
		1189	* Protects RPS/RC6 register access and PCU communication.
6084	serge	1190	* Must be taken after struct_mutex if nested. Note that
		1191	* this lock may be held for long periods of time when
		1192	* talking to hw - so only take it when talking to hw!
3243	Serge	1193	*/
		1194	struct mutex hw_lock;
		1195	};
		1196
3480	Serge	1197	/* defined intel_pm.c */
		1198	extern spinlock_t mchdev_lock;
		1199
3243	Serge	1200	struct intel_ilk_power_mgmt {
		1201	u8 cur_delay;
		1202	u8 min_delay;
		1203	u8 max_delay;
		1204	u8 fmax;
		1205	u8 fstart;
		1206
		1207	u64 last_count1;
		1208	unsigned long last_time1;
		1209	unsigned long chipset_power;
		1210	u64 last_count2;
5060	serge	1211	u64 last_time2;
3243	Serge	1212	unsigned long gfx_power;
		1213	u8 corr;
		1214
		1215	int c_m;
		1216	int r_t;
		1217	};
		1218
5060	serge	1219	struct drm_i915_private;
		1220	struct i915_power_well;
		1221
		1222	struct i915_power_well_ops {
		1223	/*
		1224	* Synchronize the well's hw state to match the current sw state, for
		1225	* example enable/disable it based on the current refcount. Called
		1226	* during driver init and resume time, possibly after first calling
		1227	* the enable/disable handlers.
		1228	*/
		1229	void (sync_hw)(struct drm_i915_private dev_priv,
		1230	struct i915_power_well *power_well);
		1231	/*
		1232	* Enable the well and resources that depend on it (for example
		1233	* interrupts located on the well). Called after the 0->1 refcount
		1234	* transition.
		1235	*/
		1236	void (enable)(struct drm_i915_private dev_priv,
		1237	struct i915_power_well *power_well);
		1238	/*
		1239	* Disable the well and resources that depend on it. Called after
		1240	* the 1->0 refcount transition.
		1241	*/
		1242	void (disable)(struct drm_i915_private dev_priv,
		1243	struct i915_power_well *power_well);
		1244	/* Returns the hw enabled state. */
		1245	bool (is_enabled)(struct drm_i915_private dev_priv,
		1246	struct i915_power_well *power_well);
		1247	};
		1248
4104	Serge	1249	/* Power well structure for haswell */
		1250	struct i915_power_well {
4560	Serge	1251	const char *name;
		1252	bool always_on;
4104	Serge	1253	/* power well enable/disable usage count */
		1254	int count;
5060	serge	1255	/* cached hw enabled state */
		1256	bool hw_enabled;
4560	Serge	1257	unsigned long domains;
5060	serge	1258	unsigned long data;
		1259	const struct i915_power_well_ops *ops;
4104	Serge	1260	};
		1261
4560	Serge	1262	struct i915_power_domains {
		1263	/*
		1264	* Power wells needed for initialization at driver init and suspend
		1265	* time are on. They are kept on until after the first modeset.
		1266	*/
		1267	bool init_power_on;
5060	serge	1268	bool initializing;
4560	Serge	1269	int power_well_count;
		1270
		1271	struct mutex lock;
		1272	int domain_use_count[POWER_DOMAIN_NUM];
		1273	struct i915_power_well *power_wells;
		1274	};
		1275
		1276	#define MAX_L3_SLICES 2
3243	Serge	1277	struct intel_l3_parity {
4560	Serge	1278	u32 *remap_info[MAX_L3_SLICES];
3243	Serge	1279	struct work_struct error_work;
4560	Serge	1280	int which_slice;
3243	Serge	1281	};
		1282
3480	Serge	1283	struct i915_gem_mm {
		1284	/** Memory allocator for GTT stolen memory */
		1285	struct drm_mm stolen;
6084	serge	1286	/** Protects the usage of the GTT stolen memory allocator. This is
		1287	* always the inner lock when overlapping with struct_mutex. */
		1288	struct mutex stolen_lock;
		1289
3480	Serge	1290	/** List of all objects in gtt_space. Used to restore gtt
		1291	* mappings on resume */
		1292	struct list_head bound_list;
		1293	/**
		1294	* List of objects which are not bound to the GTT (thus
		1295	* are idle and not used by the GPU) but still have
		1296	* (presumably uncached) pages still attached.
		1297	*/
		1298	struct list_head unbound_list;
		1299
		1300	/** Usable portion of the GTT for GEM */
		1301	unsigned long stolen_base; /* limited to low memory (32-bit) */
		1302
		1303	/** PPGTT used for aliasing the PPGTT with the GTT */
		1304	struct i915_hw_ppgtt *aliasing_ppgtt;
		1305
		1306	/** LRU list of objects with fence regs on them. */
		1307	struct list_head fence_list;
		1308
		1309	/**
		1310	* We leave the user IRQ off as much as possible,
		1311	* but this means that requests will finish and never
		1312	* be retired once the system goes idle. Set a timer to
		1313	* fire periodically while the ring is running. When it
		1314	* fires, go retire requests.
		1315	*/
		1316	struct delayed_work retire_work;
		1317
		1318	/**
4560	Serge	1319	* When we detect an idle GPU, we want to turn on
		1320	* powersaving features. So once we see that there
		1321	* are no more requests outstanding and no more
		1322	* arrive within a small period of time, we fire
		1323	* off the idle_work.
		1324	*/
		1325	struct delayed_work idle_work;
		1326
		1327	/**
3480	Serge	1328	* Are we in a non-interruptible section of code like
		1329	* modesetting?
		1330	*/
		1331	bool interruptible;
		1332
5060	serge	1333	/**
		1334	* Is the GPU currently considered idle, or busy executing userspace
		1335	* requests? Whilst idle, we attempt to power down the hardware and
		1336	* display clocks. In order to reduce the effect on performance, there
		1337	* is a slight delay before we do so.
		1338	*/
		1339	bool busy;
		1340
		1341	/* the indicator for dispatch video commands on two BSD rings */
		1342	int bsd_ring_dispatch_index;
		1343
3480	Serge	1344	/** Bit 6 swizzling required for X tiling */
		1345	uint32_t bit_6_swizzle_x;
		1346	/** Bit 6 swizzling required for Y tiling */
		1347	uint32_t bit_6_swizzle_y;
		1348
		1349	/* accounting, useful for userland debugging */
4104	Serge	1350	spinlock_t object_stat_lock;
3480	Serge	1351	size_t object_memory;
		1352	u32 object_count;
		1353	};
		1354
4104	Serge	1355	struct drm_i915_error_state_buf {
5354	serge	1356	struct drm_i915_private *i915;
4104	Serge	1357	unsigned bytes;
		1358	unsigned size;
		1359	int err;
		1360	u8 *buf;
		1361	loff_t start;
		1362	loff_t pos;
		1363	};
		1364
		1365	struct i915_error_state_file_priv {
		1366	struct drm_device *dev;
		1367	struct drm_i915_error_state *error;
		1368	};
		1369
3480	Serge	1370	struct i915_gpu_error {
		1371	/* For hangcheck timer */
		1372	#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
		1373	#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
4560	Serge	1374	/* Hang gpu twice in this window and your context gets banned */
		1375	#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
		1376
6084	serge	1377	struct workqueue_struct *hangcheck_wq;
		1378	struct delayed_work hangcheck_work;
3480	Serge	1379
		1380	/* For reset and error_state handling. */
		1381	spinlock_t lock;
		1382	/* Protected by the above dev->gpu_error.lock. */
		1383	struct drm_i915_error_state *first_error;
		1384
4560	Serge	1385	unsigned long missed_irq_rings;
		1386
3480	Serge	1387	/**
4560	Serge	1388	* State variable controlling the reset flow and count
3480	Serge	1389	*
4560	Serge	1390	* This is a counter which gets incremented when reset is triggered,
		1391	* and again when reset has been handled. So odd values (lowest bit set)
		1392	* means that reset is in progress and even values that
		1393	* (reset_counter >> 1):th reset was successfully completed.
3480	Serge	1394	*
4560	Serge	1395	* If reset is not completed succesfully, the I915_WEDGE bit is
		1396	* set meaning that hardware is terminally sour and there is no
		1397	* recovery. All waiters on the reset_queue will be woken when
		1398	* that happens.
		1399	*
		1400	* This counter is used by the wait_seqno code to notice that reset
		1401	* event happened and it needs to restart the entire ioctl (since most
		1402	* likely the seqno it waited for won't ever signal anytime soon).
		1403	*
3480	Serge	1404	* This is important for lock-free wait paths, where no contended lock
		1405	* naturally enforces the correct ordering between the bail-out of the
		1406	* waiter and the gpu reset work code.
		1407	*/
		1408	atomic_t reset_counter;
		1409
		1410	#define I915_RESET_IN_PROGRESS_FLAG 1
4560	Serge	1411	#define I915_WEDGED (1 << 31)
3480	Serge	1412
		1413	/**
		1414	* Waitqueue to signal when the reset has completed. Used by clients
		1415	* that wait for dev_priv->mm.wedged to settle.
		1416	*/
		1417	wait_queue_head_t reset_queue;
		1418
5060	serge	1419	/* Userspace knobs for gpu hang simulation;
		1420	* combines both a ring mask, and extra flags
		1421	*/
		1422	u32 stop_rings;
		1423	#define I915_STOP_RING_ALLOW_BAN (1 << 31)
		1424	#define I915_STOP_RING_ALLOW_WARN (1 << 30)
4560	Serge	1425
		1426	/* For missed irq/seqno simulation. */
		1427	unsigned int test_irq_rings;
5354	serge	1428
		1429	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
		1430	bool reload_in_reset;
3480	Serge	1431	};
		1432
		1433	enum modeset_restore {
		1434	MODESET_ON_LID_OPEN,
		1435	MODESET_DONE,
		1436	MODESET_SUSPENDED,
		1437	};
		1438
6084	serge	1439	#define DP_AUX_A 0x40
		1440	#define DP_AUX_B 0x10
		1441	#define DP_AUX_C 0x20
		1442	#define DP_AUX_D 0x30
		1443
		1444	#define DDC_PIN_B 0x05
		1445	#define DDC_PIN_C 0x04
		1446	#define DDC_PIN_D 0x06
		1447
4560	Serge	1448	struct ddi_vbt_port_info {
5354	serge	1449	/*
		1450	* This is an index in the HDMI/DVI DDI buffer translation table.
		1451	* The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
		1452	* populate this field.
		1453	*/
		1454	#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
4560	Serge	1455	uint8_t hdmi_level_shift;
		1456
		1457	uint8_t supports_dvi:1;
		1458	uint8_t supports_hdmi:1;
		1459	uint8_t supports_dp:1;
6084	serge	1460
		1461	uint8_t alternate_aux_channel;
		1462	uint8_t alternate_ddc_pin;
		1463
		1464	uint8_t dp_boost_level;
		1465	uint8_t hdmi_boost_level;
4560	Serge	1466	};
		1467
6084	serge	1468	enum psr_lines_to_wait {
		1469	PSR_0_LINES_TO_WAIT = 0,
		1470	PSR_1_LINE_TO_WAIT,
		1471	PSR_4_LINES_TO_WAIT,
		1472	PSR_8_LINES_TO_WAIT
5060	serge	1473	};
		1474
4104	Serge	1475	struct intel_vbt_data {
		1476	struct drm_display_mode lfp_lvds_vbt_mode; / if any */
		1477	struct drm_display_mode sdvo_lvds_vbt_mode; / if any */
		1478
		1479	/* Feature bits */
		1480	unsigned int int_tv_support:1;
		1481	unsigned int lvds_dither:1;
		1482	unsigned int lvds_vbt:1;
		1483	unsigned int int_crt_support:1;
		1484	unsigned int lvds_use_ssc:1;
		1485	unsigned int display_clock_mode:1;
		1486	unsigned int fdi_rx_polarity_inverted:1;
5060	serge	1487	unsigned int has_mipi:1;
4104	Serge	1488	int lvds_ssc_freq;
		1489	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
		1490
5060	serge	1491	enum drrs_support_type drrs_type;
		1492
4104	Serge	1493	/* eDP */
		1494	int edp_rate;
		1495	int edp_lanes;
		1496	int edp_preemphasis;
		1497	int edp_vswing;
		1498	bool edp_initialized;
		1499	bool edp_support;
		1500	int edp_bpp;
		1501	struct edp_power_seq edp_pps;
		1502
4560	Serge	1503	struct {
6084	serge	1504	bool full_link;
		1505	bool require_aux_wakeup;
		1506	int idle_frames;
		1507	enum psr_lines_to_wait lines_to_wait;
		1508	int tp1_wakeup_time;
		1509	int tp2_tp3_wakeup_time;
		1510	} psr;
		1511
		1512	struct {
4560	Serge	1513	u16 pwm_freq_hz;
5060	serge	1514	bool present;
4560	Serge	1515	bool active_low_pwm;
5060	serge	1516	u8 min_brightness; /* min_brightness/255 of max */
4560	Serge	1517	} backlight;
		1518
		1519	/* MIPI DSI */
		1520	struct {
5060	serge	1521	u16 port;
4560	Serge	1522	u16 panel_id;
5060	serge	1523	struct mipi_config *config;
		1524	struct mipi_pps_data *pps;
		1525	u8 seq_version;
		1526	u32 size;
		1527	u8 *data;
		1528	u8 *sequence[MIPI_SEQ_MAX];
4560	Serge	1529	} dsi;
		1530
4104	Serge	1531	int crt_ddc_pin;
		1532
		1533	int child_dev_num;
4560	Serge	1534	union child_device_config *child_dev;
		1535
		1536	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
4104	Serge	1537	};
		1538
		1539	enum intel_ddb_partitioning {
		1540	INTEL_DDB_PART_1_2,
		1541	INTEL_DDB_PART_5_6, /* IVB+ */
		1542	};
		1543
		1544	struct intel_wm_level {
		1545	bool enable;
		1546	uint32_t pri_val;
		1547	uint32_t spr_val;
		1548	uint32_t cur_val;
		1549	uint32_t fbc_val;
		1550	};
		1551
4560	Serge	1552	struct ilk_wm_values {
		1553	uint32_t wm_pipe[3];
		1554	uint32_t wm_lp[3];
		1555	uint32_t wm_lp_spr[3];
		1556	uint32_t wm_linetime[3];
		1557	bool enable_fbc_wm;
		1558	enum intel_ddb_partitioning partitioning;
		1559	};
		1560
6084	serge	1561	struct vlv_pipe_wm {
		1562	uint16_t primary;
		1563	uint16_t sprite[2];
		1564	uint8_t cursor;
		1565	};
		1566
		1567	struct vlv_sr_wm {
		1568	uint16_t plane;
		1569	uint8_t cursor;
		1570	};
		1571
		1572	struct vlv_wm_values {
		1573	struct vlv_pipe_wm pipe[3];
		1574	struct vlv_sr_wm sr;
		1575	struct {
		1576	uint8_t cursor;
		1577	uint8_t sprite[2];
		1578	uint8_t primary;
		1579	} ddl[3];
		1580	uint8_t level;
		1581	bool cxsr;
		1582	};
		1583
5354	serge	1584	struct skl_ddb_entry {
		1585	uint16_t start, end; /* in number of blocks, 'end' is exclusive */
		1586	};
		1587
		1588	static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
		1589	{
		1590	return entry->end - entry->start;
		1591	}
		1592
		1593	static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
		1594	const struct skl_ddb_entry *e2)
		1595	{
		1596	if (e1->start == e2->start && e1->end == e2->end)
		1597	return true;
		1598
		1599	return false;
		1600	}
		1601
		1602	struct skl_ddb_allocation {
		1603	struct skl_ddb_entry pipe[I915_MAX_PIPES];
6084	serge	1604	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
		1605	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
5354	serge	1606	};
		1607
		1608	struct skl_wm_values {
		1609	bool dirty[I915_MAX_PIPES];
		1610	struct skl_ddb_allocation ddb;
		1611	uint32_t wm_linetime[I915_MAX_PIPES];
		1612	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
		1613	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
		1614	};
		1615
		1616	struct skl_wm_level {
		1617	bool plane_en[I915_MAX_PLANES];
		1618	uint16_t plane_res_b[I915_MAX_PLANES];
		1619	uint8_t plane_res_l[I915_MAX_PLANES];
		1620	};
		1621
4104	Serge	1622	/*
5060	serge	1623	* This struct helps tracking the state needed for runtime PM, which puts the
		1624	* device in PCI D3 state. Notice that when this happens, nothing on the
		1625	* graphics device works, even register access, so we don't get interrupts nor
		1626	* anything else.
4104	Serge	1627	*
5060	serge	1628	* Every piece of our code that needs to actually touch the hardware needs to
		1629	* either call intel_runtime_pm_get or call intel_display_power_get with the
		1630	* appropriate power domain.
4104	Serge	1631	*
5060	serge	1632	* Our driver uses the autosuspend delay feature, which means we'll only really
		1633	* suspend if we stay with zero refcount for a certain amount of time. The
5354	serge	1634	* default value is currently very conservative (see intel_runtime_pm_enable), but
5060	serge	1635	* it can be changed with the standard runtime PM files from sysfs.
4104	Serge	1636	*
		1637	* The irqs_disabled variable becomes true exactly after we disable the IRQs and
		1638	* goes back to false exactly before we reenable the IRQs. We use this variable
		1639	* to check if someone is trying to enable/disable IRQs while they're supposed
		1640	* to be disabled. This shouldn't happen and we'll print some error messages in
5060	serge	1641	* case it happens.
4104	Serge	1642	*
5060	serge	1643	* For more, read the Documentation/power/runtime_pm.txt.
4104	Serge	1644	*/
4560	Serge	1645	struct i915_runtime_pm {
		1646	bool suspended;
5354	serge	1647	bool irqs_enabled;
4560	Serge	1648	};
		1649
		1650	enum intel_pipe_crc_source {
		1651	INTEL_PIPE_CRC_SOURCE_NONE,
		1652	INTEL_PIPE_CRC_SOURCE_PLANE1,
		1653	INTEL_PIPE_CRC_SOURCE_PLANE2,
		1654	INTEL_PIPE_CRC_SOURCE_PF,
		1655	INTEL_PIPE_CRC_SOURCE_PIPE,
		1656	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
		1657	INTEL_PIPE_CRC_SOURCE_TV,
		1658	INTEL_PIPE_CRC_SOURCE_DP_B,
		1659	INTEL_PIPE_CRC_SOURCE_DP_C,
		1660	INTEL_PIPE_CRC_SOURCE_DP_D,
		1661	INTEL_PIPE_CRC_SOURCE_AUTO,
		1662	INTEL_PIPE_CRC_SOURCE_MAX,
		1663	};
		1664
		1665	struct intel_pipe_crc_entry {
		1666	uint32_t frame;
		1667	uint32_t crc[5];
		1668	};
		1669
		1670	#define INTEL_PIPE_CRC_ENTRIES_NR 128
		1671	struct intel_pipe_crc {
		1672	spinlock_t lock;
		1673	bool opened; /* exclusive access to the result file */
		1674	struct intel_pipe_crc_entry *entries;
		1675	enum intel_pipe_crc_source source;
		1676	int head, tail;
		1677	wait_queue_head_t wq;
		1678	};
		1679
5060	serge	1680	struct i915_frontbuffer_tracking {
		1681	struct mutex lock;
		1682
		1683	/*
		1684	* Tracking bits for delayed frontbuffer flushing du to gpu activity or
		1685	* scheduled flips.
		1686	*/
		1687	unsigned busy_bits;
		1688	unsigned flip_bits;
		1689	};
		1690
5354	serge	1691	struct i915_wa_reg {
		1692	u32 addr;
		1693	u32 value;
		1694	/* bitmask representing WA bits */
		1695	u32 mask;
		1696	};
		1697
		1698	#define I915_MAX_WA_REGS 16
		1699
		1700	struct i915_workarounds {
		1701	struct i915_wa_reg reg[I915_MAX_WA_REGS];
		1702	u32 count;
		1703	};
		1704
6084	serge	1705	struct i915_virtual_gpu {
		1706	bool active;
		1707	};
		1708
		1709	struct i915_execbuffer_params {
		1710	struct drm_device *dev;
		1711	struct drm_file *file;
		1712	uint32_t dispatch_flags;
		1713	uint32_t args_batch_start_offset;
		1714	uint64_t batch_obj_vm_offset;
		1715	struct intel_engine_cs *ring;
		1716	struct drm_i915_gem_object *batch_obj;
		1717	struct intel_context *ctx;
		1718	struct drm_i915_gem_request *request;
		1719	};
		1720
5060	serge	1721	struct drm_i915_private {
3243	Serge	1722	struct drm_device *dev;
6084	serge	1723	struct kmem_cache *objects;
		1724	struct kmem_cache *vmas;
		1725	struct kmem_cache *requests;
3243	Serge	1726
5060	serge	1727	const struct intel_device_info info;
3243	Serge	1728
		1729	int relative_constants_mode;
		1730
		1731	void __iomem *regs;
		1732
4104	Serge	1733	struct intel_uncore uncore;
3243	Serge	1734
6084	serge	1735	struct i915_virtual_gpu vgpu;
3243	Serge	1736
6084	serge	1737	struct intel_guc guc;
3480	Serge	1738
6084	serge	1739	struct intel_csr csr;
		1740
		1741	/* Display CSR-related protection */
		1742	struct mutex csr_lock;
		1743
		1744	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
		1745
3243	Serge	1746	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
		1747	* controller on different i2c buses. */
		1748	struct mutex gmbus_mutex;
		1749
		1750	/**
		1751	* Base address of the gmbus and gpio block.
		1752	*/
		1753	uint32_t gpio_mmio_base;
		1754
5060	serge	1755	/* MMIO base address for MIPI regs */
		1756	uint32_t mipi_mmio_base;
		1757
3480	Serge	1758	wait_queue_head_t gmbus_wait_queue;
		1759
3243	Serge	1760	struct pci_dev *bridge_dev;
5060	serge	1761	struct intel_engine_cs ring[I915_NUM_RINGS];
		1762	struct drm_i915_gem_object *semaphore_obj;
3480	Serge	1763	uint32_t last_seqno, next_seqno;
3243	Serge	1764
5354	serge	1765	struct drm_dma_handle *status_page_dmah;
3243	Serge	1766	struct resource mch_res;
		1767
		1768	/* protects the irq masks */
		1769	spinlock_t irq_lock;
		1770
5060	serge	1771	/* protects the mmio flip data */
		1772	spinlock_t mmio_flip_lock;
		1773
		1774	bool display_irqs_enabled;
		1775
3480	Serge	1776
6084	serge	1777	/* Sideband mailbox protection */
		1778	struct mutex sb_lock;
3243	Serge	1779
		1780	/** Cached value of IMR to avoid reads in updating the bitfield */
4560	Serge	1781	union {
6084	serge	1782	u32 irq_mask;
4560	Serge	1783	u32 de_irq_mask[I915_MAX_PIPES];
		1784	};
3243	Serge	1785	u32 gt_irq_mask;
4104	Serge	1786	u32 pm_irq_mask;
5060	serge	1787	u32 pm_rps_events;
		1788	u32 pipestat_irq_mask[I915_MAX_PIPES];
3243	Serge	1789
6084	serge	1790	struct i915_hotplug hotplug;
4104	Serge	1791	struct i915_fbc fbc;
5060	serge	1792	struct i915_drrs drrs;
3243	Serge	1793	struct intel_opregion opregion;
4104	Serge	1794	struct intel_vbt_data vbt;
3243	Serge	1795
5354	serge	1796	bool preserve_bios_swizzle;
		1797
3243	Serge	1798	/* overlay */
		1799	struct intel_overlay *overlay;
		1800
4560	Serge	1801	/* backlight registers and fields in struct intel_panel */
5354	serge	1802	struct mutex backlight_lock;
3746	Serge	1803
3243	Serge	1804	/* LVDS info */
		1805	bool no_aux_handshake;
		1806
5354	serge	1807	/* protects panel power sequencer state */
		1808	struct mutex pps_mutex;
		1809
3243	Serge	1810	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
		1811	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
		1812
		1813	unsigned int fsb_freq, mem_freq, is_ddr3;
6084	serge	1814	unsigned int skl_boot_cdclk;
		1815	unsigned int cdclk_freq, max_cdclk_freq;
		1816	unsigned int max_dotclk_freq;
5354	serge	1817	unsigned int hpll_freq;
6084	serge	1818	unsigned int czclk_freq;
3243	Serge	1819
4104	Serge	1820	/**
		1821	* wq - Driver workqueue for GEM.
		1822	*
		1823	* NOTE: Work items scheduled here are not allowed to grab any modeset
		1824	* locks, for otherwise the flushing done in the pageflip code will
		1825	* result in deadlocks.
		1826	*/
3243	Serge	1827	struct workqueue_struct *wq;
		1828
		1829	/* Display functions */
		1830	struct drm_i915_display_funcs display;
		1831
		1832	/* PCH chipset type */
		1833	enum intel_pch pch_type;
		1834	unsigned short pch_id;
		1835
		1836	unsigned long quirks;
		1837
3480	Serge	1838	enum modeset_restore modeset_restore;
		1839	struct mutex modeset_restore_lock;
3243	Serge	1840
4104	Serge	1841	struct list_head vm_list; /* Global list of all address spaces */
5060	serge	1842	struct i915_gtt gtt; /* VM representing the global address space */
2325	Serge	1843
3480	Serge	1844	struct i915_gem_mm mm;
5128	serge	1845	DECLARE_HASHTABLE(mm_structs, 7);
		1846	struct mutex mm_lock;
2325	Serge	1847
3031	serge	1848	/* Kernel Modesetting */
		1849
6084	serge	1850	struct sdvo_device_mapping sdvo_mappings[2];
2325	Serge	1851
5060	serge	1852	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
		1853	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2352	Serge	1854	wait_queue_head_t pending_flip_queue;
2325	Serge	1855
4560	Serge	1856	#ifdef CONFIG_DEBUG_FS
		1857	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
		1858	#endif
		1859
4104	Serge	1860	int num_shared_dpll;
		1861	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
4560	Serge	1862	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
3031	serge	1863
5354	serge	1864	struct i915_workarounds workarounds;
		1865
2325	Serge	1866	/* Reclocking support */
		1867	bool render_reclock_avail;
5060	serge	1868
		1869	struct i915_frontbuffer_tracking fb_tracking;
		1870
2325	Serge	1871	u16 orig_clock;
		1872
		1873	bool mchbar_need_disable;
		1874
3243	Serge	1875	struct intel_l3_parity l3_parity;
		1876
4104	Serge	1877	/* Cannot be determined by PCIID. You must always read a register. */
		1878	size_t ellc_size;
		1879
3031	serge	1880	/* gen6+ rps state */
3243	Serge	1881	struct intel_gen6_power_mgmt rps;
2325	Serge	1882
3031	serge	1883	/* ilk-only ips/rps state. Everything in here is protected by the global
		1884	* mchdev_lock in intel_pm.c */
3243	Serge	1885	struct intel_ilk_power_mgmt ips;
2325	Serge	1886
4560	Serge	1887	struct i915_power_domains power_domains;
2325	Serge	1888
4560	Serge	1889	struct i915_psr psr;
2325	Serge	1890
3480	Serge	1891	struct i915_gpu_error gpu_error;
2325	Serge	1892
4104	Serge	1893	struct drm_i915_gem_object *vlv_pctx;
		1894
6084	serge	1895	#ifdef CONFIG_DRM_FBDEV_EMULATION
2325	Serge	1896	/* list of fbdev register on this device */
6084	serge	1897	struct intel_fbdev *fbdev;
5354	serge	1898	struct work_struct fbdev_suspend_work;
4560	Serge	1899	#endif
2325	Serge	1900
3031	serge	1901	struct drm_property *broadcast_rgb_property;
		1902	struct drm_property *force_audio_property;
		1903
6084	serge	1904	/* hda/i915 audio component */
		1905	struct i915_audio_component *audio_component;
		1906	bool audio_component_registered;
		1907	/**
		1908	* av_mutex - mutex for audio/video sync
		1909	*
		1910	*/
		1911	struct mutex av_mutex;
		1912
3031	serge	1913	uint32_t hw_context_size;
4560	Serge	1914	struct list_head context_list;
3243	Serge	1915
3480	Serge	1916	u32 fdi_rx_config;
3243	Serge	1917
6084	serge	1918	u32 chv_phy_control;
		1919
5060	serge	1920	u32 suspend_count;
3243	Serge	1921	struct i915_suspend_saved_registers regfile;
5060	serge	1922	struct vlv_s0ix_state vlv_s0ix_state;
3243	Serge	1923
4104	Serge	1924	struct {
		1925	/*
		1926	* Raw watermark latency values:
		1927	* in 0.1us units for WM0,
		1928	* in 0.5us units for WM1+.
		1929	*/
		1930	/* primary */
		1931	uint16_t pri_latency[5];
		1932	/* sprite */
		1933	uint16_t spr_latency[5];
		1934	/* cursor */
		1935	uint16_t cur_latency[5];
5354	serge	1936	/*
		1937	* Raw watermark memory latency values
		1938	* for SKL for all 8 levels
		1939	* in 1us units.
		1940	*/
		1941	uint16_t skl_latency[8];
4560	Serge	1942
5354	serge	1943	/*
		1944	* The skl_wm_values structure is a bit too big for stack
		1945	* allocation, so we keep the staging struct where we store
		1946	* intermediate results here instead.
		1947	*/
		1948	struct skl_wm_values skl_results;
		1949
4560	Serge	1950	/* current hardware state */
5354	serge	1951	union {
6084	serge	1952	struct ilk_wm_values hw;
5354	serge	1953	struct skl_wm_values skl_hw;
6084	serge	1954	struct vlv_wm_values vlv;
5354	serge	1955	};
6084	serge	1956
		1957	uint8_t max_level;
4104	Serge	1958	} wm;
		1959
4560	Serge	1960	struct i915_runtime_pm pm;
		1961
5354	serge	1962	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
		1963	struct {
6084	serge	1964	int (execbuf_submit)(struct i915_execbuffer_params params,
		1965	struct drm_i915_gem_execbuffer2 *args,
		1966	struct list_head *vmas);
5354	serge	1967	int (init_rings)(struct drm_device dev);
		1968	void (cleanup_ring)(struct intel_engine_cs ring);
		1969	void (stop_ring)(struct intel_engine_cs ring);
		1970	} gt;
		1971
6084	serge	1972	bool edp_low_vswing;
		1973
		1974	/* perform PHY state sanity checks? */
		1975	bool chv_phy_assert[2];
		1976
5060	serge	1977	/*
		1978	* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
		1979	* will be rejected. Instead look for a better place.
		1980	*/
		1981	};
		1982
4104	Serge	1983	static inline struct drm_i915_private to_i915(const struct drm_device dev)
		1984	{
		1985	return dev->dev_private;
		1986	}
		1987
6084	serge	1988	static inline struct drm_i915_private dev_to_i915(struct device dev)
		1989	{
		1990	return to_i915(dev_get_drvdata(dev));
		1991	}
		1992
		1993	static inline struct drm_i915_private guc_to_i915(struct intel_guc guc)
		1994	{
		1995	return container_of(guc, struct drm_i915_private, guc);
		1996	}
		1997
3031	serge	1998	/* Iterate over initialised rings */
		1999	#define for_each_ring(ring__, dev_priv__, i__) \
		2000	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
		2001	if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
		2002
		2003	enum hdmi_force_audio {
		2004	HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
		2005	HDMI_AUDIO_OFF, /* force turn off HDMI audio */
		2006	HDMI_AUDIO_AUTO, /* trust EDID */
		2007	HDMI_AUDIO_ON, /* force turn on HDMI audio */
		2008	};
		2009
4104	Serge	2010	#define I915_GTT_OFFSET_NONE ((u32)-1)
2325	Serge	2011
3031	serge	2012	struct drm_i915_gem_object_ops {
		2013	/* Interface between the GEM object and its backing storage.
		2014	* get_pages() is called once prior to the use of the associated set
		2015	* of pages before to binding them into the GTT, and put_pages() is
		2016	* called after we no longer need them. As we expect there to be
		2017	* associated cost with migrating pages between the backing storage
		2018	* and making them available for the GPU (e.g. clflush), we may hold
		2019	* onto the pages after they are no longer referenced by the GPU
		2020	* in case they may be used again shortly (for example migrating the
		2021	* pages to a different memory domain within the GTT). put_pages()
		2022	* will therefore most likely be called when the object itself is
		2023	* being released or under memory pressure (where we attempt to
		2024	* reap pages for the shrinker).
		2025	*/
		2026	int (get_pages)(struct drm_i915_gem_object );
		2027	void (put_pages)(struct drm_i915_gem_object );
5060	serge	2028	int (dmabuf_export)(struct drm_i915_gem_object );
		2029	void (release)(struct drm_i915_gem_object );
3031	serge	2030	};
		2031
5060	serge	2032	/*
		2033	* Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
6084	serge	2034	* considered to be the frontbuffer for the given plane interface-wise. This
5060	serge	2035	* doesn't mean that the hw necessarily already scans it out, but that any
		2036	* rendering (by the cpu or gpu) will land in the frontbuffer eventually.
		2037	*
		2038	* We have one bit per pipe and per scanout plane type.
		2039	*/
6084	serge	2040	#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
		2041	#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
5060	serge	2042	#define INTEL_FRONTBUFFER_BITS \
		2043	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
		2044	#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
		2045	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
		2046	#define INTEL_FRONTBUFFER_CURSOR(pipe) \
6084	serge	2047	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
		2048	#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
		2049	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
5060	serge	2050	#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
6084	serge	2051	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
5060	serge	2052	#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
6084	serge	2053	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
5060	serge	2054
2327	Serge	2055	struct drm_i915_gem_object {
6084	serge	2056	struct drm_gem_object base;
2325	Serge	2057
3031	serge	2058	const struct drm_i915_gem_object_ops *ops;
		2059
4104	Serge	2060	/** List of VMAs backed by this object */
		2061	struct list_head vma_list;
		2062
3480	Serge	2063	/** Stolen memory for this object, instead of being backed by shmem. */
		2064	struct drm_mm_node *stolen;
4104	Serge	2065	struct list_head global_list;
2327	Serge	2066
6084	serge	2067	struct list_head ring_list[I915_NUM_RINGS];
4104	Serge	2068	/** Used in execbuf to temporarily hold a ref */
		2069	struct list_head obj_exec_link;
2327	Serge	2070
6084	serge	2071	struct list_head batch_pool_link;
		2072
		2073	/**
3031	serge	2074	* This is set if the object is on the active lists (has pending
		2075	* rendering and so a non-zero seqno), and is not set if it i s on
		2076	* inactive (ready to be unbound) list.
6084	serge	2077	*/
		2078	unsigned int active:I915_NUM_RINGS;
2327	Serge	2079
6084	serge	2080	/**
		2081	* This is set if the object has been written to since last bound
		2082	* to the GTT
		2083	*/
2342	Serge	2084	unsigned int dirty:1;
2327	Serge	2085
6084	serge	2086	/**
		2087	* Fence register bits (if any) for this object. Will be set
		2088	* as needed when mapped into the GTT.
		2089	* Protected by dev->struct_mutex.
		2090	*/
2342	Serge	2091	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2327	Serge	2092
6084	serge	2093	/**
		2094	* Advice: are the backing pages purgeable?
		2095	*/
2342	Serge	2096	unsigned int madv:2;
2327	Serge	2097
6084	serge	2098	/**
		2099	* Current tiling mode for the object.
		2100	*/
2342	Serge	2101	unsigned int tiling_mode:2;
3031	serge	2102	/**
		2103	* Whether the tiling parameters for the currently associated fence
		2104	* register have changed. Note that for the purposes of tracking
		2105	* tiling changes we also treat the unfenced register, the register
		2106	* slot that the object occupies whilst it executes a fenced
		2107	* command (such as BLT on gen2/3), as a "fence".
		2108	*/
		2109	unsigned int fence_dirty:1;
2327	Serge	2110
6084	serge	2111	/**
		2112	* Is the object at the current location in the gtt mappable and
		2113	* fenceable? Used to avoid costly recalculations.
		2114	*/
2342	Serge	2115	unsigned int map_and_fenceable:1;
2327	Serge	2116
6084	serge	2117	/**
		2118	* Whether the current gtt mapping needs to be mappable (and isn't just
		2119	* mappable by accident). Track pin and fault separate for a more
		2120	* accurate mappable working set.
		2121	*/
2342	Serge	2122	unsigned int fault_mappable:1;
2327	Serge	2123
6084	serge	2124	/*
5060	serge	2125	* Is the object to be mapped as read-only to the GPU
		2126	* Only honoured if hardware has relevant pte bit
		2127	*/
		2128	unsigned long gt_ro:1;
4104	Serge	2129	unsigned int cache_level:3;
6084	serge	2130	unsigned int cache_dirty:1;
2327	Serge	2131
5060	serge	2132	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
		2133
6084	serge	2134	unsigned int pin_display;
		2135
3243	Serge	2136	struct sg_table *pages;
3031	serge	2137	int pages_pin_count;
6084	serge	2138	struct get_page {
		2139	struct scatterlist *sg;
		2140	int last;
		2141	} get_page;
2327	Serge	2142
3031	serge	2143	/* prime dma-buf support */
		2144	void *dma_buf_vmapping;
		2145	int vmapping_count;
		2146
6084	serge	2147	/** Breadcrumb of last rendering to the buffer.
		2148	* There can only be one writer, but we allow for multiple readers.
		2149	* If there is a writer that necessarily implies that all other
		2150	* read requests are complete - but we may only be lazily clearing
		2151	* the read requests. A read request is naturally the most recent
		2152	* request on a ring, so we may have two different write and read
		2153	* requests on one ring where the write request is older than the
		2154	* read request. This allows for the CPU to read from an active
		2155	* buffer by only waiting for the write to complete.
		2156	* */
		2157	struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
		2158	struct drm_i915_gem_request *last_write_req;
		2159	/** Breadcrumb of last fenced GPU access to the buffer. */
		2160	struct drm_i915_gem_request *last_fenced_req;
3031	serge	2161
6084	serge	2162	/** Current tiling stride for the object, if it's tiled. */
		2163	uint32_t stride;
2327	Serge	2164
4560	Serge	2165	/** References from framebuffers, locks out tiling changes. */
		2166	unsigned long framebuffer_references;
		2167
6084	serge	2168	/** Record of address bit 17 of each page at last unbind. */
		2169	unsigned long *bit_17;
2327	Serge	2170
5354	serge	2171	union {
6084	serge	2172	/** for phy allocated objects */
5354	serge	2173	struct drm_dma_handle *phys_handle;
5060	serge	2174
		2175	struct i915_gem_userptr {
		2176	uintptr_t ptr;
		2177	unsigned read_only :1;
		2178	unsigned workers :4;
		2179	#define I915_GEM_USERPTR_MAX_WORKERS 15
		2180
5128	serge	2181	struct i915_mm_struct *mm;
		2182	struct i915_mmu_object *mmu_object;
5060	serge	2183	struct work_struct *work;
		2184	} userptr;
		2185	};
2327	Serge	2186	};
2325	Serge	2187	#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
		2188
5060	serge	2189	void i915_gem_track_fb(struct drm_i915_gem_object *old,
		2190	struct drm_i915_gem_object *new,
		2191	unsigned frontbuffer_bits);
		2192
2325	Serge	2193	/**
		2194	* Request queue structure.
		2195	*
		2196	* The request queue allows us to note sequence numbers that have been emitted
		2197	* and may be associated with active buffers to be retired.
		2198	*
6084	serge	2199	* By keeping this list, we can avoid having to do questionable sequence
		2200	* number comparisons on buffer last_read\|write_seqno. It also allows an
		2201	* emission time to be associated with the request for tracking how far ahead
		2202	* of the GPU the submission is.
		2203	*
		2204	* The requests are reference counted, so upon creation they should have an
		2205	* initial reference taken using kref_init
2325	Serge	2206	*/
		2207	struct drm_i915_gem_request {
6084	serge	2208	struct kref ref;
		2209
2325	Serge	2210	/** On Which ring this request was generated */
6084	serge	2211	struct drm_i915_private *i915;
5060	serge	2212	struct intel_engine_cs *ring;
2325	Serge	2213
6084	serge	2214	/** GEM sequence number associated with the previous request,
		2215	* when the HWS breadcrumb is equal to this the GPU is processing
		2216	* this request.
		2217	*/
		2218	u32 previous_seqno;
2325	Serge	2219
6084	serge	2220	/** GEM sequence number associated with this request,
		2221	* when the HWS breadcrumb is equal or greater than this the GPU
		2222	* has finished processing this request.
		2223	*/
		2224	u32 seqno;
		2225
4104	Serge	2226	/** Position in the ringbuffer of the start of the request */
		2227	u32 head;
		2228
6084	serge	2229	/**
		2230	* Position in the ringbuffer of the start of the postfix.
		2231	* This is required to calculate the maximum available ringbuffer
		2232	* space without overwriting the postfix.
		2233	*/
		2234	u32 postfix;
		2235
		2236	/** Position in the ringbuffer of the end of the whole request */
3031	serge	2237	u32 tail;
		2238
6084	serge	2239	/**
		2240	* Context and ring buffer related to this request
		2241	* Contexts are refcounted, so when this request is associated with a
		2242	* context, we must increment the context's refcount, to guarantee that
		2243	* it persists while any request is linked to it. Requests themselves
		2244	* are also refcounted, so the request will only be freed when the last
		2245	* reference to it is dismissed, and the code in
		2246	* i915_gem_request_free() will then decrement the refcount on the
		2247	* context.
		2248	*/
5060	serge	2249	struct intel_context *ctx;
6084	serge	2250	struct intel_ringbuffer *ringbuf;
4104	Serge	2251
6084	serge	2252	/** Batch buffer related to this request if any (used for
		2253	error state dump only) */
4104	Serge	2254	struct drm_i915_gem_object *batch_obj;
		2255
2325	Serge	2256	/** Time at which this request was emitted, in jiffies. */
		2257	unsigned long emitted_jiffies;
		2258
		2259	/** global list entry for this request */
		2260	struct list_head list;
		2261
		2262	struct drm_i915_file_private *file_priv;
		2263	/** file_priv list entry for this request */
		2264	struct list_head client_list;
		2265
6084	serge	2266	/** process identifier submitting this request */
		2267	struct pid *pid;
4560	Serge	2268
6084	serge	2269	/**
		2270	* The ELSP only accepts two elements at a time, so we queue
		2271	* context/tail pairs on a given queue (ring->execlist_queue) until the
		2272	* hardware is available. The queue serves a double purpose: we also use
		2273	* it to keep track of the up to 2 contexts currently in the hardware
		2274	* (usually one in execution and the other queued up by the GPU): We
		2275	* only remove elements from the head of the queue when the hardware
		2276	* informs us that an element has been completed.
		2277	*
		2278	* All accesses to the queue are mediated by a spinlock
		2279	* (ring->execlist_lock).
		2280	*/
4104	Serge	2281
6084	serge	2282	/** Execlist link in the submission queue.*/
		2283	struct list_head execlist_link;
		2284
		2285	/** Execlists no. of times this request has been sent to the ELSP */
		2286	int elsp_submitted;
		2287
2325	Serge	2288	};
		2289
6084	serge	2290	int i915_gem_request_alloc(struct intel_engine_cs *ring,
		2291	struct intel_context *ctx,
		2292	struct drm_i915_gem_request **req_out);
		2293	void i915_gem_request_cancel(struct drm_i915_gem_request *req);
		2294	void i915_gem_request_free(struct kref *req_ref);
		2295	int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
		2296	struct drm_file *file);
		2297
		2298	static inline uint32_t
		2299	i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
		2300	{
		2301	return req ? req->seqno : 0;
		2302	}
		2303
		2304	static inline struct intel_engine_cs *
		2305	i915_gem_request_get_ring(struct drm_i915_gem_request *req)
		2306	{
		2307	return req ? req->ring : NULL;
		2308	}
		2309
		2310	static inline struct drm_i915_gem_request *
		2311	i915_gem_request_reference(struct drm_i915_gem_request *req)
		2312	{
		2313	if (req)
		2314	kref_get(&req->ref);
		2315	return req;
		2316	}
		2317
		2318	static inline void
		2319	i915_gem_request_unreference(struct drm_i915_gem_request *req)
		2320	{
		2321	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
		2322	kref_put(&req->ref, i915_gem_request_free);
		2323	}
		2324
		2325	static inline void
		2326	i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
		2327	{
		2328	struct drm_device *dev;
		2329
		2330	if (!req)
		2331	return;
		2332
		2333	dev = req->ring->dev;
		2334	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
		2335	mutex_unlock(&dev->struct_mutex);
		2336	}
		2337
		2338	static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
		2339	struct drm_i915_gem_request *src)
		2340	{
		2341	if (src)
		2342	i915_gem_request_reference(src);
		2343
		2344	if (*pdst)
		2345	i915_gem_request_unreference(*pdst);
		2346
		2347	*pdst = src;
		2348	}
		2349
5060	serge	2350	/*
6084	serge	2351	* XXX: i915_gem_request_completed should be here but currently needs the
		2352	* definition of i915_seqno_passed() which is below. It will be moved in
		2353	* a later patch when the call to i915_seqno_passed() is obsoleted...
		2354	*/
		2355
		2356	/*
5060	serge	2357	* A command that requires special handling by the command parser.
		2358	*/
		2359	struct drm_i915_cmd_descriptor {
		2360	/*
		2361	* Flags describing how the command parser processes the command.
		2362	*
		2363	* CMD_DESC_FIXED: The command has a fixed length if this is set,
		2364	* a length mask if not set
		2365	* CMD_DESC_SKIP: The command is allowed but does not follow the
		2366	* standard length encoding for the opcode range in
		2367	* which it falls
		2368	* CMD_DESC_REJECT: The command is never allowed
		2369	* CMD_DESC_REGISTER: The command should be checked against the
		2370	* register whitelist for the appropriate ring
		2371	* CMD_DESC_MASTER: The command is allowed if the submitting process
		2372	* is the DRM master
		2373	*/
		2374	u32 flags;
		2375	#define CMD_DESC_FIXED (1<<0)
		2376	#define CMD_DESC_SKIP (1<<1)
		2377	#define CMD_DESC_REJECT (1<<2)
		2378	#define CMD_DESC_REGISTER (1<<3)
		2379	#define CMD_DESC_BITMASK (1<<4)
		2380	#define CMD_DESC_MASTER (1<<5)
2325	Serge	2381
5060	serge	2382	/*
		2383	* The command's unique identification bits and the bitmask to get them.
		2384	* This isn't strictly the opcode field as defined in the spec and may
		2385	* also include type, subtype, and/or subop fields.
		2386	*/
		2387	struct {
		2388	u32 value;
		2389	u32 mask;
		2390	} cmd;
		2391
		2392	/*
		2393	* The command's length. The command is either fixed length (i.e. does
		2394	* not include a length field) or has a length field mask. The flag
		2395	* CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
		2396	* a length mask. All command entries in a command table must include
		2397	* length information.
		2398	*/
		2399	union {
		2400	u32 fixed;
		2401	u32 mask;
		2402	} length;
		2403
		2404	/*
		2405	* Describes where to find a register address in the command to check
		2406	* against the ring's register whitelist. Only valid if flags has the
		2407	* CMD_DESC_REGISTER bit set.
6084	serge	2408	*
		2409	* A non-zero step value implies that the command may access multiple
		2410	* registers in sequence (e.g. LRI), in that case step gives the
		2411	* distance in dwords between individual offset fields.
5060	serge	2412	*/
		2413	struct {
		2414	u32 offset;
		2415	u32 mask;
6084	serge	2416	u32 step;
5060	serge	2417	} reg;
		2418
		2419	#define MAX_CMD_DESC_BITMASKS 3
		2420	/*
		2421	* Describes command checks where a particular dword is masked and
		2422	* compared against an expected value. If the command does not match
		2423	* the expected value, the parser rejects it. Only valid if flags has
		2424	* the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
		2425	* are valid.
		2426	*
		2427	* If the check specifies a non-zero condition_mask then the parser
		2428	* only performs the check when the bits specified by condition_mask
		2429	* are non-zero.
		2430	*/
		2431	struct {
		2432	u32 offset;
		2433	u32 mask;
		2434	u32 expected;
		2435	u32 condition_offset;
		2436	u32 condition_mask;
		2437	} bits[MAX_CMD_DESC_BITMASKS];
		2438	};
		2439
		2440	/*
		2441	* A table of commands requiring special handling by the command parser.
		2442	*
		2443	* Each ring has an array of tables. Each table consists of an array of command
		2444	* descriptors, which must be sorted with command opcodes in ascending order.
		2445	*/
		2446	struct drm_i915_cmd_table {
		2447	const struct drm_i915_cmd_descriptor *table;
		2448	int count;
		2449	};
		2450
5354	serge	2451	/* Note that the (struct drm_i915_private ) cast is just to shut up gcc. /
		2452	#define __I915__(p) ({ \
		2453	struct drm_i915_private *__p; \
		2454	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		2455	__p = (struct drm_i915_private *)p; \
		2456	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		2457	__p = to_i915((struct drm_device *)p); \
		2458	else \
		2459	BUILD_BUG(); \
		2460	__p; \
		2461	})
		2462	#define INTEL_INFO(p) (&__I915__(p)->info)
		2463	#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
6084	serge	2464	#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
5060	serge	2465
5354	serge	2466	#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
		2467	#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2325	Serge	2468	#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
5354	serge	2469	#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2325	Serge	2470	#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
5354	serge	2471	#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
		2472	#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2325	Serge	2473	#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
		2474	#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
		2475	#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
5354	serge	2476	#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2325	Serge	2477	#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
5354	serge	2478	#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
		2479	#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2325	Serge	2480	#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
		2481	#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
5354	serge	2482	#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2325	Serge	2483	#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
5354	serge	2484	#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 \|\| \
		2485	INTEL_DEVID(dev) == 0x0152 \|\| \
		2486	INTEL_DEVID(dev) == 0x015a)
3031	serge	2487	#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
5060	serge	2488	#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
3031	serge	2489	#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
5060	serge	2490	#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
5354	serge	2491	#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
6084	serge	2492	#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2325	Serge	2493	#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
4104	Serge	2494	#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
5354	serge	2495	(INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
4560	Serge	2496	#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
6084	serge	2497	((INTEL_DEVID(dev) & 0xf) == 0x6 \|\| \
		2498	(INTEL_DEVID(dev) & 0xf) == 0xb \|\| \
5354	serge	2499	(INTEL_DEVID(dev) & 0xf) == 0xe))
6084	serge	2500	/* ULX machines are also considered ULT. */
		2501	#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
		2502	(INTEL_DEVID(dev) & 0xf) == 0xe)
5354	serge	2503	#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
		2504	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
4560	Serge	2505	#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
5354	serge	2506	(INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
4560	Serge	2507	#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
5354	serge	2508	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
5060	serge	2509	/* ULX machines are also considered ULT. */
5354	serge	2510	#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E \|\| \
		2511	INTEL_DEVID(dev) == 0x0A1E)
6084	serge	2512	#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 \|\| \
		2513	INTEL_DEVID(dev) == 0x1913 \|\| \
		2514	INTEL_DEVID(dev) == 0x1916 \|\| \
		2515	INTEL_DEVID(dev) == 0x1921 \|\| \
		2516	INTEL_DEVID(dev) == 0x1926)
		2517	#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E \|\| \
		2518	INTEL_DEVID(dev) == 0x1915 \|\| \
		2519	INTEL_DEVID(dev) == 0x191E)
		2520	#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
		2521	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
		2522	#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
		2523	(INTEL_DEVID(dev) & 0x00F0) == 0x0030)
		2524
4560	Serge	2525	#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2325	Serge	2526
6084	serge	2527	#define SKL_REVID_A0 (0x0)
		2528	#define SKL_REVID_B0 (0x1)
		2529	#define SKL_REVID_C0 (0x2)
		2530	#define SKL_REVID_D0 (0x3)
		2531	#define SKL_REVID_E0 (0x4)
		2532	#define SKL_REVID_F0 (0x5)
		2533
		2534	#define BXT_REVID_A0 (0x0)
		2535	#define BXT_REVID_B0 (0x3)
		2536	#define BXT_REVID_C0 (0x9)
		2537
2325	Serge	2538	/*
		2539	* The genX designation typically refers to the render engine, so render
		2540	* capability related checks should use IS_GEN, while display and other checks
		2541	* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
		2542	* chips, etc.).
		2543	*/
		2544	#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
		2545	#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
		2546	#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
		2547	#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
		2548	#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
		2549	#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
4560	Serge	2550	#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
5354	serge	2551	#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2325	Serge	2552
4560	Serge	2553	#define RENDER_RING (1<
		2554	#define BSD_RING (1<
		2555	#define BLT_RING (1<
		2556	#define VEBOX_RING (1<
5060	serge	2557	#define BSD2_RING (1<
6084	serge	2558	#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
5060	serge	2559	#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
6084	serge	2560	#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
		2561	#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
		2562	#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
5060	serge	2563	#define HAS_WT(dev) ((IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) && \
5354	serge	2564	__I915__(dev)->ellc_size)
2325	Serge	2565	#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
		2566
3031	serge	2567	#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
5354	serge	2568	#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
		2569	#define USES_PPGTT(dev) (i915.enable_ppgtt)
6084	serge	2570	#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
		2571	#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
3031	serge	2572
2325	Serge	2573	#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
		2574	#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
		2575
3243	Serge	2576	/* Early gen2 have a totally busted CS tlb and require pinned batches. */
		2577	#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) \|\| IS_845G(dev))
5060	serge	2578	/*
		2579	* dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
		2580	* even when in MSI mode. This results in spurious interrupt warnings if the
		2581	* legacy irq no. is shared with another device. The kernel then disables that
		2582	* interrupt source and so prevents the other device from working properly.
		2583	*/
		2584	#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
		2585	#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
3243	Serge	2586
2325	Serge	2587	/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
		2588	* rows, which changed the alignment requirements and fence programming.
		2589	*/
		2590	#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) \|\| \
		2591	IS_I915GM(dev)))
		2592	#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
		2593	#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
		2594
		2595	#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
		2596	#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
4560	Serge	2597	#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2325	Serge	2598
5354	serge	2599	#define HAS_IPS(dev) (IS_HSW_ULT(dev) \|\| IS_BROADWELL(dev))
2325	Serge	2600
6084	serge	2601	#define HAS_DP_MST(dev) (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| \
		2602	INTEL_INFO(dev)->gen >= 9)
		2603
4104	Serge	2604	#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
		2605	#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
6084	serge	2606	#define HAS_PSR(dev) (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| \
		2607	IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev) \|\| \
		2608	IS_SKYLAKE(dev))
5060	serge	2609	#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) \|\| IS_HASWELL(dev) \|\| \
6084	serge	2610	IS_BROADWELL(dev) \|\| IS_VALLEYVIEW(dev) \|\| \
		2611	IS_SKYLAKE(dev))
5354	serge	2612	#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
		2613	#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 \|\| IS_IVYBRIDGE(dev))
3480	Serge	2614
6084	serge	2615	#define HAS_CSR(dev) (IS_GEN9(dev))
		2616
		2617	#define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
		2618	#define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
		2619
		2620	#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) \|\| \
		2621	INTEL_INFO(dev)->gen >= 8)
		2622
		2623	#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
		2624	!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
		2625
3243	Serge	2626	#define INTEL_PCH_DEVICE_ID_MASK 0xff00
		2627	#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
		2628	#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
		2629	#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
		2630	#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
		2631	#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
5354	serge	2632	#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
		2633	#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
6084	serge	2634	#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
3243	Serge	2635
5354	serge	2636	#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
		2637	#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
3031	serge	2638	#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
6084	serge	2639	#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2325	Serge	2640	#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
		2641	#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
3746	Serge	2642	#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
3031	serge	2643	#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2325	Serge	2644
5060	serge	2645	#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 \|\| IS_VALLEYVIEW(dev))
		2646
4560	Serge	2647	/* DPF == dynamic parity feature */
		2648	#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		2649	#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2325	Serge	2650
3031	serge	2651	#define GT_FREQUENCY_MULTIPLIER 50
6084	serge	2652	#define GEN9_FREQ_SCALER 3
3031	serge	2653
		2654	#include "i915_trace.h"
		2655
6084	serge	2656	extern const struct drm_ioctl_desc i915_ioctls[];
		2657	extern int i915_max_ioctl;
3031	serge	2658
6084	serge	2659	extern int i915_resume_switcheroo(struct drm_device *dev);
2325	Serge	2660
5060	serge	2661	/* i915_params.c */
		2662	struct i915_params {
		2663	int modeset;
		2664	int panel_ignore_lid;
		2665	int semaphores;
		2666	int lvds_channel_mode;
		2667	int panel_use_ssc;
		2668	int vbt_sdvo_panel_type;
		2669	int enable_rc6;
		2670	int enable_fbc;
		2671	int enable_ppgtt;
5354	serge	2672	int enable_execlists;
5060	serge	2673	int enable_psr;
		2674	unsigned int preliminary_hw_support;
		2675	int disable_power_well;
		2676	int enable_ips;
		2677	int invert_brightness;
		2678	int enable_cmd_parser;
		2679	/* leave bools at the end to not create holes */
		2680	bool enable_hangcheck;
		2681	bool fastboot;
		2682	bool prefault_disable;
6084	serge	2683	bool load_detect_test;
5060	serge	2684	bool reset;
		2685	bool disable_display;
		2686	bool disable_vtd_wa;
6084	serge	2687	bool enable_guc_submission;
		2688	int guc_log_level;
5060	serge	2689	int use_mmio_flip;
6084	serge	2690	int mmio_debug;
		2691	bool verbose_state_checks;
		2692	bool nuclear_pageflip;
		2693	int edp_vswing;
5060	serge	2694	};
		2695	extern struct i915_params i915 __read_mostly;
		2696
2325	Serge	2697	/* i915_dma.c */
		2698	extern int i915_driver_load(struct drm_device *, unsigned long flags);
		2699	extern int i915_driver_unload(struct drm_device *);
5060	serge	2700	extern int i915_driver_open(struct drm_device dev, struct drm_file file);
2325	Serge	2701	extern void i915_driver_lastclose(struct drm_device * dev);
		2702	extern void i915_driver_preclose(struct drm_device *dev,
5060	serge	2703	struct drm_file *file);
2325	Serge	2704	extern void i915_driver_postclose(struct drm_device *dev,
5060	serge	2705	struct drm_file *file);
3031	serge	2706	#ifdef CONFIG_COMPAT
2325	Serge	2707	extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
		2708	unsigned long arg);
3031	serge	2709	#endif
		2710	extern int intel_gpu_reset(struct drm_device *dev);
6084	serge	2711	extern bool intel_has_gpu_reset(struct drm_device *dev);
3031	serge	2712	extern int i915_reset(struct drm_device *dev);
2325	Serge	2713	extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
		2714	extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
		2715	extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
		2716	extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
5060	serge	2717	int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
6084	serge	2718	void i915_firmware_load_error_print(const char *fw_path, int err);
		2719
		2720	/* intel_hotplug.c */
		2721	void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
		2722	void intel_hpd_init(struct drm_i915_private *dev_priv);
		2723	void intel_hpd_init_work(struct drm_i915_private *dev_priv);
5060	serge	2724	void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
6084	serge	2725	bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2325	Serge	2726
		2727	/* i915_irq.c */
4104	Serge	2728	void i915_queue_hangcheck(struct drm_device *dev);
5060	serge	2729	__printf(3, 4)
		2730	void i915_handle_error(struct drm_device *dev, bool wedged,
		2731	const char *fmt, ...);
2325	Serge	2732
5354	serge	2733	extern void intel_irq_init(struct drm_i915_private *dev_priv);
		2734	int intel_irq_install(struct drm_i915_private *dev_priv);
		2735	void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2325	Serge	2736
4104	Serge	2737	extern void intel_uncore_sanitize(struct drm_device *dev);
5060	serge	2738	extern void intel_uncore_early_sanitize(struct drm_device *dev,
		2739	bool restore_forcewake);
4104	Serge	2740	extern void intel_uncore_init(struct drm_device *dev);
		2741	extern void intel_uncore_check_errors(struct drm_device *dev);
4560	Serge	2742	extern void intel_uncore_fini(struct drm_device *dev);
5060	serge	2743	extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
6084	serge	2744	const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
		2745	void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
		2746	enum forcewake_domains domains);
		2747	void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
		2748	enum forcewake_domains domains);
		2749	/* Like above but the caller must manage the uncore.lock itself.
		2750	* Must be used with I915_READ_FW and friends.
		2751	*/
		2752	void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
		2753	enum forcewake_domains domains);
		2754	void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
		2755	enum forcewake_domains domains);
		2756	void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
		2757	static inline bool intel_vgpu_active(struct drm_device *dev)
		2758	{
		2759	return to_i915(dev)->vgpu.active;
		2760	}
2325	Serge	2761
		2762	void
5060	serge	2763	i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		2764	u32 status_mask);
2325	Serge	2765
		2766	void
5060	serge	2767	i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		2768	u32 status_mask);
2325	Serge	2769
5060	serge	2770	void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
		2771	void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
6084	serge	2772	void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
		2773	uint32_t mask,
		2774	uint32_t bits);
5354	serge	2775	void
		2776	ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
		2777	void
		2778	ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
		2779	void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
		2780	uint32_t interrupt_mask,
		2781	uint32_t enabled_irq_mask);
		2782	#define ibx_enable_display_interrupt(dev_priv, bits) \
		2783	ibx_display_interrupt_update((dev_priv), (bits), (bits))
		2784	#define ibx_disable_display_interrupt(dev_priv, bits) \
		2785	ibx_display_interrupt_update((dev_priv), (bits), 0)
5060	serge	2786
2325	Serge	2787	/* i915_gem.c */
		2788	int i915_gem_create_ioctl(struct drm_device dev, void data,
		2789	struct drm_file *file_priv);
		2790	int i915_gem_pread_ioctl(struct drm_device dev, void data,
		2791	struct drm_file *file_priv);
		2792	int i915_gem_pwrite_ioctl(struct drm_device dev, void data,
		2793	struct drm_file *file_priv);
		2794	int i915_gem_mmap_ioctl(struct drm_device dev, void data,
		2795	struct drm_file *file_priv);
		2796	int i915_gem_mmap_gtt_ioctl(struct drm_device dev, void data,
		2797	struct drm_file *file_priv);
		2798	int i915_gem_set_domain_ioctl(struct drm_device dev, void data,
		2799	struct drm_file *file_priv);
		2800	int i915_gem_sw_finish_ioctl(struct drm_device dev, void data,
		2801	struct drm_file *file_priv);
5354	serge	2802	void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
6084	serge	2803	struct drm_i915_gem_request *req);
		2804	void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
		2805	int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
5354	serge	2806	struct drm_i915_gem_execbuffer2 *args,
6084	serge	2807	struct list_head *vmas);
2325	Serge	2808	int i915_gem_execbuffer(struct drm_device dev, void data,
		2809	struct drm_file *file_priv);
		2810	int i915_gem_execbuffer2(struct drm_device dev, void data,
		2811	struct drm_file *file_priv);
		2812	int i915_gem_busy_ioctl(struct drm_device dev, void data,
		2813	struct drm_file *file_priv);
3031	serge	2814	int i915_gem_get_caching_ioctl(struct drm_device dev, void data,
		2815	struct drm_file *file);
		2816	int i915_gem_set_caching_ioctl(struct drm_device dev, void data,
		2817	struct drm_file *file);
2325	Serge	2818	int i915_gem_throttle_ioctl(struct drm_device dev, void data,
		2819	struct drm_file *file_priv);
		2820	int i915_gem_madvise_ioctl(struct drm_device dev, void data,
		2821	struct drm_file *file_priv);
		2822	int i915_gem_set_tiling(struct drm_device dev, void data,
		2823	struct drm_file *file_priv);
		2824	int i915_gem_get_tiling(struct drm_device dev, void data,
		2825	struct drm_file *file_priv);
5060	serge	2826	int i915_gem_init_userptr(struct drm_device *dev);
		2827	int i915_gem_userptr_ioctl(struct drm_device dev, void data,
		2828	struct drm_file *file);
2325	Serge	2829	int i915_gem_get_aperture_ioctl(struct drm_device dev, void data,
		2830	struct drm_file *file_priv);
3031	serge	2831	int i915_gem_wait_ioctl(struct drm_device dev, void data,
		2832	struct drm_file *file_priv);
2325	Serge	2833	void i915_gem_load(struct drm_device *dev);
3480	Serge	2834	void i915_gem_object_alloc(struct drm_device dev);
		2835	void i915_gem_object_free(struct drm_i915_gem_object *obj);
3031	serge	2836	void i915_gem_object_init(struct drm_i915_gem_object *obj,
		2837	const struct drm_i915_gem_object_ops *ops);
2325	Serge	2838	struct drm_i915_gem_object i915_gem_alloc_object(struct drm_device dev,
		2839	size_t size);
6084	serge	2840	struct drm_i915_gem_object *i915_gem_object_create_from_data(
		2841	struct drm_device dev, const void data, size_t size);
2325	Serge	2842	void i915_gem_free_object(struct drm_gem_object *obj);
4104	Serge	2843	void i915_gem_vma_destroy(struct i915_vma *vma);
3480	Serge	2844
6084	serge	2845	/* Flags used by pin/bind&friends. */
		2846	#define PIN_MAPPABLE (1<<0)
		2847	#define PIN_NONBLOCK (1<<1)
		2848	#define PIN_GLOBAL (1<<2)
		2849	#define PIN_OFFSET_BIAS (1<<3)
		2850	#define PIN_USER (1<<4)
		2851	#define PIN_UPDATE (1<<5)
		2852	#define PIN_ZONE_4G (1<<6)
		2853	#define PIN_HIGH (1<<7)
5060	serge	2854	#define PIN_OFFSET_MASK (~4095)
6084	serge	2855	int __must_check
		2856	i915_gem_object_pin(struct drm_i915_gem_object *obj,
		2857	struct i915_address_space *vm,
		2858	uint32_t alignment,
		2859	uint64_t flags);
		2860	int __must_check
		2861	i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
		2862	const struct i915_ggtt_view *view,
		2863	uint32_t alignment,
		2864	uint64_t flags);
		2865
		2866	int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		2867	u32 flags);
		2868	void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
4104	Serge	2869	int __must_check i915_vma_unbind(struct i915_vma *vma);
6084	serge	2870	/*
		2871	* BEWARE: Do not use the function below unless you can _absolutely_
		2872	* _guarantee_ VMA in question is _not in use_ anywhere.
		2873	*/
		2874	int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3480	Serge	2875	int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
4560	Serge	2876	void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2325	Serge	2877	void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
		2878
5060	serge	2879	int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
		2880	int *needs_clflush);
		2881
3031	serge	2882	int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
6084	serge	2883
		2884	static inline int __sg_page_count(struct scatterlist *sg)
3031	serge	2885	{
6084	serge	2886	return sg->length >> PAGE_SHIFT;
		2887	}
3031	serge	2888
6084	serge	2889	static inline struct page *
		2890	i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
		2891	{
		2892	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		2893	return NULL;
3746	Serge	2894
6084	serge	2895	if (n < obj->get_page.last) {
		2896	obj->get_page.sg = obj->pages->sgl;
		2897	obj->get_page.last = 0;
		2898	}
		2899
		2900	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		2901	obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		2902	if (unlikely(sg_is_chain(obj->get_page.sg)))
		2903	obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
		2904	}
		2905
		2906	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3243	Serge	2907	}
6084	serge	2908
3031	serge	2909	static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
		2910	{
3243	Serge	2911	BUG_ON(obj->pages == NULL);
3031	serge	2912	obj->pages_pin_count++;
		2913	}
		2914	static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
		2915	{
		2916	BUG_ON(obj->pages_pin_count == 0);
		2917	obj->pages_pin_count--;
		2918	}
		2919
2325	Serge	2920	int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3031	serge	2921	int i915_gem_object_sync(struct drm_i915_gem_object *obj,
6084	serge	2922	struct intel_engine_cs *to,
		2923	struct drm_i915_gem_request **to_req);
4560	Serge	2924	void i915_vma_move_to_active(struct i915_vma *vma,
6084	serge	2925	struct drm_i915_gem_request *req);
2325	Serge	2926	int i915_gem_dumb_create(struct drm_file *file_priv,
		2927	struct drm_device *dev,
		2928	struct drm_mode_create_dumb *args);
		2929	int i915_gem_mmap_gtt(struct drm_file file_priv, struct drm_device dev,
		2930	uint32_t handle, uint64_t *offset);
		2931	/**
		2932	* Returns true if seq1 is later than seq2.
		2933	*/
2340	Serge	2934	static inline bool
		2935	i915_seqno_passed(uint32_t seq1, uint32_t seq2)
		2936	{
		2937	return (int32_t)(seq1 - seq2) >= 0;
		2938	}
2325	Serge	2939
6084	serge	2940	static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
		2941	bool lazy_coherency)
		2942	{
		2943	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
		2944	return i915_seqno_passed(seqno, req->previous_seqno);
		2945	}
		2946
		2947	static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
		2948	bool lazy_coherency)
		2949	{
		2950	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
		2951	return i915_seqno_passed(seqno, req->seqno);
		2952	}
		2953
3480	Serge	2954	int __must_check i915_gem_get_seqno(struct drm_device dev, u32 seqno);
		2955	int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3031	serge	2956
5060	serge	2957	struct drm_i915_gem_request *
		2958	i915_gem_find_active_request(struct intel_engine_cs *ring);
2332	Serge	2959
4560	Serge	2960	bool i915_gem_retire_requests(struct drm_device *dev);
5060	serge	2961	void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3480	Serge	2962	int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3031	serge	2963	bool interruptible);
5060	serge	2964
3480	Serge	2965	static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
		2966	{
		2967	return unlikely(atomic_read(&error->reset_counter)
4560	Serge	2968	& (I915_RESET_IN_PROGRESS_FLAG \| I915_WEDGED));
3480	Serge	2969	}
3031	serge	2970
3480	Serge	2971	static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
		2972	{
4560	Serge	2973	return atomic_read(&error->reset_counter) & I915_WEDGED;
3480	Serge	2974	}
		2975
4560	Serge	2976	static inline u32 i915_reset_count(struct i915_gpu_error *error)
		2977	{
		2978	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
		2979	}
		2980
5060	serge	2981	static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
		2982	{
		2983	return dev_priv->gpu_error.stop_rings == 0 \|\|
		2984	dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
		2985	}
		2986
		2987	static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
		2988	{
		2989	return dev_priv->gpu_error.stop_rings == 0 \|\|
		2990	dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
		2991	}
		2992
2325	Serge	2993	void i915_gem_reset(struct drm_device *dev);
4104	Serge	2994	bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3031	serge	2995	int __must_check i915_gem_init(struct drm_device *dev);
5354	serge	2996	int i915_gem_init_rings(struct drm_device *dev);
3031	serge	2997	int __must_check i915_gem_init_hw(struct drm_device *dev);
6084	serge	2998	int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3031	serge	2999	void i915_gem_init_swizzling(struct drm_device *dev);
2325	Serge	3000	void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
		3001	int __must_check i915_gpu_idle(struct drm_device *dev);
4560	Serge	3002	int __must_check i915_gem_suspend(struct drm_device *dev);
6084	serge	3003	void __i915_add_request(struct drm_i915_gem_request *req,
		3004	struct drm_i915_gem_object *batch_obj,
		3005	bool flush_caches);
		3006	#define i915_add_request(req) \
		3007	__i915_add_request(req, NULL, true)
		3008	#define i915_add_request_no_flush(req) \
		3009	__i915_add_request(req, NULL, false)
		3010	int __i915_wait_request(struct drm_i915_gem_request *req,
5354	serge	3011	unsigned reset_counter,
		3012	bool interruptible,
		3013	s64 *timeout,
6084	serge	3014	struct intel_rps_client *rps);
		3015	int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2325	Serge	3016	int i915_gem_fault(struct vm_area_struct vma, struct vm_fault vmf);
		3017	int __must_check
6084	serge	3018	i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
		3019	bool readonly);
		3020	int __must_check
2325	Serge	3021	i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
		3022	bool write);
		3023	int __must_check
3031	serge	3024	i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
		3025	int __must_check
2325	Serge	3026	i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
		3027	u32 alignment,
6084	serge	3028	struct intel_engine_cs *pipelined,
		3029	struct drm_i915_gem_request **pipelined_request,
		3030	const struct i915_ggtt_view *view);
		3031	void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
		3032	const struct i915_ggtt_view *view);
5060	serge	3033	int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2325	Serge	3034	int align);
4560	Serge	3035	int i915_gem_open(struct drm_device dev, struct drm_file file);
2325	Serge	3036	void i915_gem_release(struct drm_device dev, struct drm_file file);
		3037
		3038	uint32_t
3480	Serge	3039	i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
		3040	uint32_t
		3041	i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
		3042	int tiling_mode, bool fenced);
2325	Serge	3043
		3044	int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
		3045	enum i915_cache_level cache_level);
		3046
4104	Serge	3047	struct drm_gem_object i915_gem_prime_import(struct drm_device dev,
		3048	struct dma_buf *dma_buf);
3031	serge	3049
		3050	struct dma_buf i915_gem_prime_export(struct drm_device dev,
		3051	struct drm_gem_object *gem_obj, int flags);
		3052
6084	serge	3053	u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
		3054	const struct i915_ggtt_view *view);
		3055	u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
		3056	struct i915_address_space *vm);
		3057	static inline u64
		3058	i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
		3059	{
		3060	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
		3061	}
3746	Serge	3062
4104	Serge	3063	bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
6084	serge	3064	bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
		3065	const struct i915_ggtt_view *view);
4104	Serge	3066	bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
		3067	struct i915_address_space *vm);
6084	serge	3068
4104	Serge	3069	unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
		3070	struct i915_address_space *vm);
		3071	struct i915_vma *
6084	serge	3072	i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		3073	struct i915_address_space *vm);
		3074	struct i915_vma *
		3075	i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
		3076	const struct i915_ggtt_view *view);
		3077
		3078	struct i915_vma *
4104	Serge	3079	i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
		3080	struct i915_address_space *vm);
6084	serge	3081	struct i915_vma *
		3082	i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
		3083	const struct i915_ggtt_view *view);
4560	Serge	3084
6084	serge	3085	static inline struct i915_vma *
		3086	i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
		3087	{
		3088	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
5060	serge	3089	}
6084	serge	3090	bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
4560	Serge	3091
4104	Serge	3092	/* Some GGTT VM helpers */
5354	serge	3093	#define i915_obj_to_ggtt(obj) \
4104	Serge	3094	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
		3095	static inline bool i915_is_ggtt(struct i915_address_space *vm)
		3096	{
		3097	struct i915_address_space *ggtt =
		3098	&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
		3099	return vm == ggtt;
		3100	}
		3101
5354	serge	3102	static inline struct i915_hw_ppgtt *
		3103	i915_vm_to_ppgtt(struct i915_address_space *vm)
		3104	{
		3105	WARN_ON(i915_is_ggtt(vm));
		3106
		3107	return container_of(vm, struct i915_hw_ppgtt, base);
		3108	}
		3109
		3110
4104	Serge	3111	static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
		3112	{
6084	serge	3113	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
4104	Serge	3114	}
		3115
		3116	static inline unsigned long
		3117	i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
		3118	{
5354	serge	3119	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
4104	Serge	3120	}
		3121
		3122	static inline int __must_check
		3123	i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		3124	uint32_t alignment,
5060	serge	3125	unsigned flags)
4104	Serge	3126	{
5354	serge	3127	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
		3128	alignment, flags \| PIN_GLOBAL);
4104	Serge	3129	}
		3130
5060	serge	3131	static inline int
		3132	i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
		3133	{
		3134	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
		3135	}
		3136
6084	serge	3137	void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
		3138	const struct i915_ggtt_view *view);
		3139	static inline void
		3140	i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
		3141	{
		3142	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
		3143	}
5060	serge	3144
6084	serge	3145	/* i915_gem_fence.c */
		3146	int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
		3147	int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
		3148
		3149	bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
		3150	void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
		3151
		3152	void i915_gem_restore_fences(struct drm_device *dev);
		3153
		3154	void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
		3155	void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
		3156	void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
		3157
3031	serge	3158	/* i915_gem_context.c */
4560	Serge	3159	int __must_check i915_gem_context_init(struct drm_device *dev);
3031	serge	3160	void i915_gem_context_fini(struct drm_device *dev);
5060	serge	3161	void i915_gem_context_reset(struct drm_device *dev);
		3162	int i915_gem_context_open(struct drm_device dev, struct drm_file file);
6084	serge	3163	int i915_gem_context_enable(struct drm_i915_gem_request *req);
3031	serge	3164	void i915_gem_context_close(struct drm_device dev, struct drm_file file);
6084	serge	3165	int i915_switch_context(struct drm_i915_gem_request *req);
5060	serge	3166	struct intel_context *
		3167	i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
4104	Serge	3168	void i915_gem_context_free(struct kref *ctx_ref);
5354	serge	3169	struct drm_i915_gem_object *
		3170	i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
5060	serge	3171	static inline void i915_gem_context_reference(struct intel_context *ctx)
4104	Serge	3172	{
		3173	kref_get(&ctx->ref);
		3174	}
		3175
5060	serge	3176	static inline void i915_gem_context_unreference(struct intel_context *ctx)
4104	Serge	3177	{
		3178	kref_put(&ctx->ref, i915_gem_context_free);
		3179	}
		3180
5060	serge	3181	static inline bool i915_gem_context_is_default(const struct intel_context *c)
		3182	{
		3183	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
		3184	}
		3185
3031	serge	3186	int i915_gem_context_create_ioctl(struct drm_device dev, void data,
		3187	struct drm_file *file);
		3188	int i915_gem_context_destroy_ioctl(struct drm_device dev, void data,
		3189	struct drm_file *file);
6084	serge	3190	int i915_gem_context_getparam_ioctl(struct drm_device dev, void data,
		3191	struct drm_file *file_priv);
		3192	int i915_gem_context_setparam_ioctl(struct drm_device dev, void data,
		3193	struct drm_file *file_priv);
3031	serge	3194
2325	Serge	3195	/* i915_gem_evict.c */
4104	Serge	3196	int __must_check i915_gem_evict_something(struct drm_device *dev,
		3197	struct i915_address_space *vm,
		3198	int min_size,
3031	serge	3199	unsigned alignment,
		3200	unsigned cache_level,
5060	serge	3201	unsigned long start,
		3202	unsigned long end,
		3203	unsigned flags);
4560	Serge	3204	int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2325	Serge	3205
5060	serge	3206	/* belongs in i915_gem_gtt.h */
		3207	static inline void i915_gem_chipset_flush(struct drm_device *dev)
		3208	{
		3209	if (INTEL_INFO(dev)->gen < 6)
		3210	intel_gtt_chipset_flush();
		3211	}
		3212
3031	serge	3213	/* i915_gem_stolen.c */
6084	serge	3214	int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
		3215	struct drm_mm_node *node, u64 size,
		3216	unsigned alignment);
		3217	int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
		3218	struct drm_mm_node *node, u64 size,
		3219	unsigned alignment, u64 start,
		3220	u64 end);
		3221	void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
		3222	struct drm_mm_node *node);
3031	serge	3223	int i915_gem_init_stolen(struct drm_device *dev);
		3224	void i915_gem_cleanup_stolen(struct drm_device *dev);
3480	Serge	3225	struct drm_i915_gem_object *
		3226	i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3746	Serge	3227	struct drm_i915_gem_object *
		3228	i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
		3229	u32 stolen_offset,
		3230	u32 gtt_offset,
		3231	u32 size);
3031	serge	3232
6084	serge	3233	/* i915_gem_shrinker.c */
		3234	unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
		3235	unsigned long target,
		3236	unsigned flags);
		3237	#define I915_SHRINK_PURGEABLE 0x1
		3238	#define I915_SHRINK_UNBOUND 0x2
		3239	#define I915_SHRINK_BOUND 0x4
		3240	#define I915_SHRINK_ACTIVE 0x8
		3241	unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
		3242	void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
		3243
		3244
2325	Serge	3245	/* i915_gem_tiling.c */
4104	Serge	3246	static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3480	Serge	3247	{
5060	serge	3248	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3480	Serge	3249
		3250	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		3251	obj->tiling_mode != I915_TILING_NONE;
		3252	}
		3253
2325	Serge	3254	/* i915_gem_debug.c */
		3255	#if WATCH_LISTS
		3256	int i915_verify_lists(struct drm_device *dev);
		3257	#else
		3258	#define i915_verify_lists(dev) 0
		3259	#endif
		3260
		3261	/* i915_debugfs.c */
		3262	int i915_debugfs_init(struct drm_minor *minor);
		3263	void i915_debugfs_cleanup(struct drm_minor *minor);
4560	Serge	3264	#ifdef CONFIG_DEBUG_FS
6084	serge	3265	int i915_debugfs_connector_add(struct drm_connector *connector);
4560	Serge	3266	void intel_display_crc_init(struct drm_device *dev);
		3267	#else
6084	serge	3268	static inline int i915_debugfs_connector_add(struct drm_connector *connector)
		3269	{ return 0; }
4560	Serge	3270	static inline void intel_display_crc_init(struct drm_device *dev) {}
		3271	#endif
2325	Serge	3272
4104	Serge	3273	/* i915_gpu_error.c */
		3274	__printf(2, 3)
		3275	void i915_error_printf(struct drm_i915_error_state_buf e, const char f, ...);
		3276	int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
		3277	const struct i915_error_state_file_priv *error);
		3278	int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
5354	serge	3279	struct drm_i915_private *i915,
4104	Serge	3280	size_t count, loff_t pos);
		3281	static inline void i915_error_state_buf_release(
		3282	struct drm_i915_error_state_buf *eb)
		3283	{
		3284	kfree(eb->buf);
		3285	}
5060	serge	3286	void i915_capture_error_state(struct drm_device *dev, bool wedge,
		3287	const char *error_msg);
4104	Serge	3288	void i915_error_state_get(struct drm_device *dev,
		3289	struct i915_error_state_file_priv *error_priv);
		3290	void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
		3291	void i915_destroy_error_state(struct drm_device *dev);
		3292
		3293	void i915_get_extra_instdone(struct drm_device dev, uint32_t instdone);
5354	serge	3294	const char i915_cache_level_str(struct drm_i915_private i915, int type);
4104	Serge	3295
5060	serge	3296	/* i915_cmd_parser.c */
		3297	int i915_cmd_parser_get_version(void);
		3298	int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
		3299	void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
		3300	bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
		3301	int i915_parse_cmds(struct intel_engine_cs *ring,
		3302	struct drm_i915_gem_object *batch_obj,
6084	serge	3303	struct drm_i915_gem_object *shadow_batch_obj,
5060	serge	3304	u32 batch_start_offset,
6084	serge	3305	u32 batch_len,
5060	serge	3306	bool is_master);
		3307
2325	Serge	3308	/* i915_suspend.c */
		3309	extern int i915_save_state(struct drm_device *dev);
		3310	extern int i915_restore_state(struct drm_device *dev);
		3311
3031	serge	3312	/* i915_sysfs.c */
		3313	void i915_setup_sysfs(struct drm_device *dev_priv);
		3314	void i915_teardown_sysfs(struct drm_device *dev_priv);
		3315
2325	Serge	3316	/* intel_i2c.c */
		3317	extern int intel_setup_gmbus(struct drm_device *dev);
		3318	extern void intel_teardown_gmbus(struct drm_device *dev);
6084	serge	3319	extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
		3320	unsigned int pin);
3031	serge	3321
6084	serge	3322	extern struct i2c_adapter *
		3323	intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
2325	Serge	3324	extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
		3325	extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
4104	Serge	3326	static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2342	Serge	3327	{
		3328	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
		3329	}
2325	Serge	3330	extern void intel_i2c_reset(struct drm_device *dev);
		3331
		3332	/* intel_opregion.c */
4560	Serge	3333	#ifdef CONFIG_ACPI
2325	Serge	3334	extern int intel_opregion_setup(struct drm_device *dev);
		3335	extern void intel_opregion_init(struct drm_device *dev);
		3336	extern void intel_opregion_fini(struct drm_device *dev);
		3337	extern void intel_opregion_asle_intr(struct drm_device *dev);
4560	Serge	3338	extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
		3339	bool enable);
		3340	extern int intel_opregion_notify_adapter(struct drm_device *dev,
		3341	pci_power_t state);
2325	Serge	3342	#else
4560	Serge	3343	static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2325	Serge	3344	static inline void intel_opregion_init(struct drm_device *dev) { return; }
		3345	static inline void intel_opregion_fini(struct drm_device *dev) { return; }
		3346	static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
4560	Serge	3347	static inline int
		3348	intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
		3349	{
		3350	return 0;
		3351	}
		3352	static inline int
		3353	intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
		3354	{
		3355	return 0;
		3356	}
2325	Serge	3357	#endif
		3358
		3359	/* intel_acpi.c */
		3360	#ifdef CONFIG_ACPI
		3361	extern void intel_register_dsm_handler(void);
		3362	extern void intel_unregister_dsm_handler(void);
		3363	#else
		3364	static inline void intel_register_dsm_handler(void) { return; }
		3365	static inline void intel_unregister_dsm_handler(void) { return; }
		3366	#endif /* CONFIG_ACPI */
		3367
		3368	/* modesetting */
3031	serge	3369	extern void intel_modeset_init_hw(struct drm_device *dev);
2325	Serge	3370	extern void intel_modeset_init(struct drm_device *dev);
		3371	extern void intel_modeset_gem_init(struct drm_device *dev);
		3372	extern void intel_modeset_cleanup(struct drm_device *dev);
5060	serge	3373	extern void intel_connector_unregister(struct intel_connector *);
2325	Serge	3374	extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
6084	serge	3375	extern void intel_display_resume(struct drm_device *dev);
3480	Serge	3376	extern void i915_redisable_vga(struct drm_device *dev);
5060	serge	3377	extern void i915_redisable_vga_power_on(struct drm_device *dev);
2325	Serge	3378	extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3243	Serge	3379	extern void intel_init_pch_refclk(struct drm_device *dev);
6084	serge	3380	extern void intel_set_rps(struct drm_device *dev, u8 val);
5060	serge	3381	extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
		3382	bool enable);
2342	Serge	3383	extern void intel_detect_pch(struct drm_device *dev);
		3384	extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3031	serge	3385	extern int intel_enable_rc6(const struct drm_device *dev);
2325	Serge	3386
3031	serge	3387	extern bool i915_semaphore_is_enabled(struct drm_device *dev);
		3388	int i915_reg_read_ioctl(struct drm_device dev, void data,
		3389	struct drm_file *file);
4560	Serge	3390	int i915_get_reset_stats_ioctl(struct drm_device dev, void data,
		3391	struct drm_file *file);
2342	Serge	3392
2325	Serge	3393	/* overlay */
		3394	extern struct intel_overlay_error_state intel_overlay_capture_error_state(struct drm_device dev);
4104	Serge	3395	extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
		3396	struct intel_overlay_error_state *error);
2325	Serge	3397
		3398	extern struct intel_display_error_state intel_display_capture_error_state(struct drm_device dev);
4104	Serge	3399	extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2325	Serge	3400	struct drm_device *dev,
		3401	struct intel_display_error_state *error);
		3402
5354	serge	3403	int sandybridge_pcode_read(struct drm_i915_private dev_priv, u32 mbox, u32 val);
		3404	int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3243	Serge	3405
4104	Serge	3406	/* intel_sideband.c */
6084	serge	3407	u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
		3408	void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
4104	Serge	3409	u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
4560	Serge	3410	u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
		3411	void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3412	u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
		3413	void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3414	u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
		3415	void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3416	u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
		3417	void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3418	u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
		3419	void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3420	u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
		3421	void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
4104	Serge	3422	u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		3423	enum intel_sbi_destination destination);
		3424	void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		3425	enum intel_sbi_destination destination);
4560	Serge	3426	u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
		3427	void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2325	Serge	3428
6084	serge	3429	int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
		3430	int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
4104	Serge	3431
4560	Serge	3432	#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
		3433	#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2325	Serge	3434
4560	Serge	3435	#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
		3436	#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
		3437	#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
		3438	#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
		3439
		3440	#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
		3441	#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
		3442	#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
		3443	#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
		3444
5060	serge	3445	/* Be very careful with read/write 64-bit values. On 32-bit machines, they
		3446	* will be implemented using 2 32-bit writes in an arbitrary order with
		3447	* an arbitrary delay between them. This can cause the hardware to
		3448	* act upon the intermediate value, possibly leading to corruption and
		3449	* machine death. You have been warned.
		3450	*/
4560	Serge	3451	#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
		3452	#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
		3453
5060	serge	3454	#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
6084	serge	3455	u32 upper, lower, old_upper, loop = 0; \
		3456	upper = I915_READ(upper_reg); \
		3457	do { \
		3458	old_upper = upper; \
		3459	lower = I915_READ(lower_reg); \
		3460	upper = I915_READ(upper_reg); \
		3461	} while (upper != old_upper && loop++ < 2); \
		3462	(u64)upper << 32 \| lower; })
5060	serge	3463
2325	Serge	3464	#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
		3465	#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
		3466
6084	serge	3467	/* These are untraced mmio-accessors that are only valid to be used inside
		3468	* criticial sections inside IRQ handlers where forcewake is explicitly
		3469	* controlled.
		3470	* Think twice, and think again, before using these.
		3471	* Note: Should only be used between intel_uncore_forcewake_irqlock() and
		3472	* intel_uncore_forcewake_irqunlock().
		3473	*/
		3474	#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
		3475	#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
		3476	#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
		3477
3480	Serge	3478	/* "Broadcast RGB" property */
		3479	#define INTEL_BROADCAST_RGB_AUTO 0
		3480	#define INTEL_BROADCAST_RGB_FULL 1
		3481	#define INTEL_BROADCAST_RGB_LIMITED 2
		3482
		3483	static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
		3484	{
5060	serge	3485	if (IS_VALLEYVIEW(dev))
		3486	return VLV_VGACNTRL;
		3487	else if (INTEL_INFO(dev)->gen >= 5)
3480	Serge	3488	return CPU_VGACNTRL;
		3489	else
		3490	return VGACNTRL;
		3491	}
		3492
3746	Serge	3493	static inline void __user *to_user_ptr(u64 address)
		3494	{
		3495	return (void __user *)(uintptr_t)address;
		3496	}
		3497
		3498	static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
		3499	{
		3500	unsigned long j = msecs_to_jiffies(m);
		3501
		3502	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
		3503	}
		3504
5354	serge	3505	static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
		3506	{
		3507	return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
		3508	}
		3509
3746	Serge	3510	static inline unsigned long
		3511	timespec_to_jiffies_timeout(const struct timespec *value)
		3512	{
		3513	unsigned long j = timespec_to_jiffies(value);
		3514
		3515	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
		3516	}
		3517
5060	serge	3518	/*
		3519	* If you need to wait X milliseconds between events A and B, but event B
		3520	* doesn't happen exactly after event A, you record the timestamp (jiffies) of
		3521	* when event A happened, then just before event B you call this function and
		3522	* pass the timestamp as the first argument, and X as the second argument.
		3523	*/
		3524	static inline void
		3525	wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4280	Serge	3526	{
5060	serge	3527	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
		3528
		3529	/*
		3530	* Don't re-read the value of "jiffies" every time since it may change
		3531	* behind our back and break the math.
		3532	*/
		3533	tmp_jiffies = jiffies;
		3534	target_jiffies = timestamp_jiffies +
		3535	msecs_to_jiffies_timeout(to_wait_ms);
		3536
		3537	if (time_after(target_jiffies, tmp_jiffies)) {
		3538	remaining_jiffies = target_jiffies - tmp_jiffies;
6084	serge	3539	delay(remaining_jiffies);
5060	serge	3540	}
4280	Serge	3541	}
3746	Serge	3542
6084	serge	3543	static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
		3544	struct drm_i915_gem_request *req)
2338	Serge	3545	{
6084	serge	3546	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
		3547	i915_gem_request_assign(&ring->trace_irq_req, req);
5354	serge	3548	}
		3549
2325	Serge	3550	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.h – Rev 6084