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Rev | Author | Line No. | Line |
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2325 | Serge | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ |
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3 | /* |
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4 | * |
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5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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6 | * All Rights Reserved. |
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7 | * |
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8 | * Permission is hereby granted, free of charge, to any person obtaining a |
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9 | * copy of this software and associated documentation files (the |
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10 | * "Software"), to deal in the Software without restriction, including |
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11 | * without limitation the rights to use, copy, modify, merge, publish, |
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12 | * distribute, sub license, and/or sell copies of the Software, and to |
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13 | * permit persons to whom the Software is furnished to do so, subject to |
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14 | * the following conditions: |
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15 | * |
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16 | * The above copyright notice and this permission notice (including the |
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17 | * next paragraph) shall be included in all copies or substantial portions |
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18 | * of the Software. |
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19 | * |
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20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | * |
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28 | */ |
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29 | |||
30 | #ifndef _I915_DRV_H_ |
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31 | #define _I915_DRV_H_ |
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32 | |||
3480 | Serge | 33 | #include |
34 | |||
2325 | Serge | 35 | #include "i915_reg.h" |
2327 | Serge | 36 | #include "intel_bios.h" |
2326 | Serge | 37 | #include "intel_ringbuffer.h" |
3243 | Serge | 38 | #include |
2325 | Serge | 39 | //#include |
2330 | Serge | 40 | #include |
3031 | serge | 41 | #include |
2332 | Serge | 42 | #include |
2325 | Serge | 43 | //#include |
44 | |||
45 | #include |
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3243 | Serge | 46 | #include |
2325 | Serge | 47 | |
2360 | Serge | 48 | |
2325 | Serge | 49 | /* General customization: |
50 | */ |
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51 | |||
3031 | serge | 52 | #define I915_TILING_NONE 0 |
2327 | Serge | 53 | |
3031 | serge | 54 | #define VGA_RSRC_NONE 0x00 |
55 | #define VGA_RSRC_LEGACY_IO 0x01 |
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56 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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57 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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58 | /* Non-legacy access */ |
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59 | #define VGA_RSRC_NORMAL_IO 0x04 |
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60 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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2327 | Serge | 61 | |
2325 | Serge | 62 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
63 | |||
64 | #define DRIVER_NAME "i915" |
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65 | #define DRIVER_DESC "Intel Graphics" |
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66 | #define DRIVER_DATE "20080730" |
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67 | |||
68 | enum pipe { |
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4560 | Serge | 69 | INVALID_PIPE = -1, |
2325 | Serge | 70 | PIPE_A = 0, |
71 | PIPE_B, |
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72 | PIPE_C, |
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73 | I915_MAX_PIPES |
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74 | }; |
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75 | #define pipe_name(p) ((p) + 'A') |
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76 | |||
3243 | Serge | 77 | enum transcoder { |
78 | TRANSCODER_A = 0, |
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79 | TRANSCODER_B, |
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80 | TRANSCODER_C, |
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81 | TRANSCODER_EDP = 0xF, |
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82 | }; |
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83 | #define transcoder_name(t) ((t) + 'A') |
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84 | |||
2325 | Serge | 85 | enum plane { |
86 | PLANE_A = 0, |
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87 | PLANE_B, |
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88 | PLANE_C, |
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89 | }; |
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90 | #define plane_name(p) ((p) + 'A') |
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91 | |||
4104 | Serge | 92 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
93 | |||
3031 | serge | 94 | enum port { |
95 | PORT_A = 0, |
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96 | PORT_B, |
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97 | PORT_C, |
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98 | PORT_D, |
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99 | PORT_E, |
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100 | I915_MAX_PORTS |
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101 | }; |
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102 | #define port_name(p) ((p) + 'A') |
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103 | |||
4560 | Serge | 104 | #define I915_NUM_PHYS_VLV 1 |
105 | |||
106 | enum dpio_channel { |
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107 | DPIO_CH0, |
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108 | DPIO_CH1 |
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109 | }; |
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110 | |||
111 | enum dpio_phy { |
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112 | DPIO_PHY0, |
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113 | DPIO_PHY1 |
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114 | }; |
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115 | |||
4104 | Serge | 116 | enum intel_display_power_domain { |
117 | POWER_DOMAIN_PIPE_A, |
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118 | POWER_DOMAIN_PIPE_B, |
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119 | POWER_DOMAIN_PIPE_C, |
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120 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
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121 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
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122 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
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123 | POWER_DOMAIN_TRANSCODER_A, |
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124 | POWER_DOMAIN_TRANSCODER_B, |
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125 | POWER_DOMAIN_TRANSCODER_C, |
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4560 | Serge | 126 | POWER_DOMAIN_TRANSCODER_EDP, |
127 | POWER_DOMAIN_VGA, |
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128 | POWER_DOMAIN_AUDIO, |
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129 | POWER_DOMAIN_INIT, |
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130 | |||
131 | POWER_DOMAIN_NUM, |
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4104 | Serge | 132 | }; |
133 | |||
4560 | Serge | 134 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
135 | |||
4104 | Serge | 136 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
137 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
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138 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
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4560 | Serge | 139 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
140 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ |
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141 | (tran) + POWER_DOMAIN_TRANSCODER_A) |
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4104 | Serge | 142 | |
4560 | Serge | 143 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
144 | BIT(POWER_DOMAIN_PIPE_A) | \ |
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145 | BIT(POWER_DOMAIN_TRANSCODER_EDP)) |
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146 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
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147 | BIT(POWER_DOMAIN_PIPE_A) | \ |
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148 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
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149 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) |
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150 | |||
3746 | Serge | 151 | enum hpd_pin { |
152 | HPD_NONE = 0, |
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153 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
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154 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
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155 | HPD_CRT, |
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156 | HPD_SDVO_B, |
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157 | HPD_SDVO_C, |
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158 | HPD_PORT_B, |
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159 | HPD_PORT_C, |
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160 | HPD_PORT_D, |
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161 | HPD_NUM_PINS |
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162 | }; |
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163 | |||
3480 | Serge | 164 | #define I915_GEM_GPU_DOMAINS \ |
165 | (I915_GEM_DOMAIN_RENDER | \ |
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166 | I915_GEM_DOMAIN_SAMPLER | \ |
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167 | I915_GEM_DOMAIN_COMMAND | \ |
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168 | I915_GEM_DOMAIN_INSTRUCTION | \ |
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169 | I915_GEM_DOMAIN_VERTEX) |
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2325 | Serge | 170 | |
3746 | Serge | 171 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
2325 | Serge | 172 | |
3031 | serge | 173 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
174 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
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175 | if ((intel_encoder)->base.crtc == (__crtc)) |
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176 | |||
4104 | Serge | 177 | struct drm_i915_private; |
178 | |||
179 | enum intel_dpll_id { |
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180 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
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181 | /* real shared dpll ids must be >= 0 */ |
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182 | DPLL_ID_PCH_PLL_A, |
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183 | DPLL_ID_PCH_PLL_B, |
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184 | }; |
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185 | #define I915_NUM_PLLS 2 |
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186 | |||
187 | struct intel_dpll_hw_state { |
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188 | uint32_t dpll; |
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189 | uint32_t dpll_md; |
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190 | uint32_t fp0; |
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191 | uint32_t fp1; |
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192 | }; |
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193 | |||
194 | struct intel_shared_dpll { |
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3031 | serge | 195 | int refcount; /* count of number of CRTCs sharing this PLL */ |
196 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
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197 | bool on; /* is the PLL actually active? Disabled during modeset */ |
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4104 | Serge | 198 | const char *name; |
199 | /* should match the index in the dev_priv->shared_dplls array */ |
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200 | enum intel_dpll_id id; |
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201 | struct intel_dpll_hw_state hw_state; |
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202 | void (*mode_set)(struct drm_i915_private *dev_priv, |
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203 | struct intel_shared_dpll *pll); |
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204 | void (*enable)(struct drm_i915_private *dev_priv, |
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205 | struct intel_shared_dpll *pll); |
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206 | void (*disable)(struct drm_i915_private *dev_priv, |
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207 | struct intel_shared_dpll *pll); |
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208 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
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209 | struct intel_shared_dpll *pll, |
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210 | struct intel_dpll_hw_state *hw_state); |
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3031 | serge | 211 | }; |
212 | |||
3480 | Serge | 213 | /* Used by dp and fdi links */ |
214 | struct intel_link_m_n { |
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215 | uint32_t tu; |
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216 | uint32_t gmch_m; |
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217 | uint32_t gmch_n; |
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218 | uint32_t link_m; |
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219 | uint32_t link_n; |
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220 | }; |
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221 | |||
222 | void intel_link_compute_m_n(int bpp, int nlanes, |
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223 | int pixel_clock, int link_clock, |
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224 | struct intel_link_m_n *m_n); |
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225 | |||
3243 | Serge | 226 | struct intel_ddi_plls { |
227 | int spll_refcount; |
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228 | int wrpll1_refcount; |
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229 | int wrpll2_refcount; |
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230 | }; |
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231 | |||
2325 | Serge | 232 | /* Interface history: |
233 | * |
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234 | * 1.1: Original. |
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235 | * 1.2: Add Power Management |
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236 | * 1.3: Add vblank support |
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237 | * 1.4: Fix cmdbuffer path, add heap destroy |
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238 | * 1.5: Add vblank pipe configuration |
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239 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
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240 | * - Support vertical blank on secondary display pipe |
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241 | */ |
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242 | #define DRIVER_MAJOR 1 |
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243 | #define DRIVER_MINOR 6 |
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244 | #define DRIVER_PATCHLEVEL 0 |
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245 | |||
246 | #define WATCH_LISTS 0 |
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3031 | serge | 247 | #define WATCH_GTT 0 |
2325 | Serge | 248 | |
249 | #define I915_GEM_PHYS_CURSOR_0 1 |
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250 | #define I915_GEM_PHYS_CURSOR_1 2 |
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251 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
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252 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
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253 | |||
3480 | Serge | 254 | struct drm_i915_gem_phys_object { |
255 | int id; |
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256 | struct page **page_list; |
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257 | drm_dma_handle_t *handle; |
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258 | struct drm_i915_gem_object *cur_obj; |
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259 | }; |
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2325 | Serge | 260 | |
261 | struct opregion_header; |
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262 | struct opregion_acpi; |
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263 | struct opregion_swsci; |
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264 | struct opregion_asle; |
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265 | |||
266 | struct intel_opregion { |
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3031 | serge | 267 | struct opregion_header __iomem *header; |
268 | struct opregion_acpi __iomem *acpi; |
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269 | struct opregion_swsci __iomem *swsci; |
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4560 | Serge | 270 | u32 swsci_gbda_sub_functions; |
271 | u32 swsci_sbcb_sub_functions; |
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3031 | serge | 272 | struct opregion_asle __iomem *asle; |
273 | void __iomem *vbt; |
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2325 | Serge | 274 | u32 __iomem *lid_state; |
4560 | Serge | 275 | struct work_struct asle_work; |
2325 | Serge | 276 | }; |
277 | #define OPREGION_SIZE (8*1024) |
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278 | |||
279 | struct intel_overlay; |
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280 | struct intel_overlay_error_state; |
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281 | |||
2330 | Serge | 282 | struct drm_i915_master_private { |
283 | drm_local_map_t *sarea; |
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284 | struct _drm_i915_sarea *sarea_priv; |
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285 | }; |
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2325 | Serge | 286 | #define I915_FENCE_REG_NONE -1 |
3746 | Serge | 287 | #define I915_MAX_NUM_FENCES 32 |
288 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
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289 | #define I915_MAX_NUM_FENCE_BITS 6 |
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2325 | Serge | 290 | |
291 | struct drm_i915_fence_reg { |
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292 | struct list_head lru_list; |
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293 | struct drm_i915_gem_object *obj; |
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3031 | serge | 294 | int pin_count; |
2325 | Serge | 295 | }; |
296 | |||
297 | struct sdvo_device_mapping { |
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298 | u8 initialized; |
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299 | u8 dvo_port; |
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300 | u8 slave_addr; |
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301 | u8 dvo_wiring; |
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302 | u8 i2c_pin; |
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303 | u8 ddc_pin; |
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304 | }; |
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305 | |||
306 | struct intel_display_error_state; |
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307 | |||
308 | struct drm_i915_error_state { |
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3243 | Serge | 309 | struct kref ref; |
2325 | Serge | 310 | u32 eir; |
311 | u32 pgtbl_er; |
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3031 | serge | 312 | u32 ier; |
313 | u32 ccid; |
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3243 | Serge | 314 | u32 derrmr; |
315 | u32 forcewake; |
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3031 | serge | 316 | bool waiting[I915_NUM_RINGS]; |
2325 | Serge | 317 | u32 pipestat[I915_MAX_PIPES]; |
3031 | serge | 318 | u32 tail[I915_NUM_RINGS]; |
319 | u32 head[I915_NUM_RINGS]; |
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3243 | Serge | 320 | u32 ctl[I915_NUM_RINGS]; |
3031 | serge | 321 | u32 ipeir[I915_NUM_RINGS]; |
322 | u32 ipehr[I915_NUM_RINGS]; |
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323 | u32 instdone[I915_NUM_RINGS]; |
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324 | u32 acthd[I915_NUM_RINGS]; |
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325 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
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3243 | Serge | 326 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
3031 | serge | 327 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
328 | /* our own tracking of ring head and tail */ |
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329 | u32 cpu_ring_head[I915_NUM_RINGS]; |
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330 | u32 cpu_ring_tail[I915_NUM_RINGS]; |
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2325 | Serge | 331 | u32 error; /* gen6+ */ |
3031 | serge | 332 | u32 err_int; /* gen7 */ |
4560 | Serge | 333 | u32 bbstate[I915_NUM_RINGS]; |
3031 | serge | 334 | u32 instpm[I915_NUM_RINGS]; |
335 | u32 instps[I915_NUM_RINGS]; |
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336 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
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337 | u32 seqno[I915_NUM_RINGS]; |
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4560 | Serge | 338 | u64 bbaddr[I915_NUM_RINGS]; |
3031 | serge | 339 | u32 fault_reg[I915_NUM_RINGS]; |
340 | u32 done_reg; |
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341 | u32 faddr[I915_NUM_RINGS]; |
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2342 | Serge | 342 | u64 fence[I915_MAX_NUM_FENCES]; |
2325 | Serge | 343 | struct timeval time; |
3031 | serge | 344 | struct drm_i915_error_ring { |
4560 | Serge | 345 | bool valid; |
2325 | Serge | 346 | struct drm_i915_error_object { |
347 | int page_count; |
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348 | u32 gtt_offset; |
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349 | u32 *pages[0]; |
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3746 | Serge | 350 | } *ringbuffer, *batchbuffer, *ctx; |
3031 | serge | 351 | struct drm_i915_error_request { |
352 | long jiffies; |
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353 | u32 seqno; |
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354 | u32 tail; |
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355 | } *requests; |
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356 | int num_requests; |
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357 | } ring[I915_NUM_RINGS]; |
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2325 | Serge | 358 | struct drm_i915_error_buffer { |
359 | u32 size; |
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360 | u32 name; |
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3031 | serge | 361 | u32 rseqno, wseqno; |
2325 | Serge | 362 | u32 gtt_offset; |
363 | u32 read_domains; |
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364 | u32 write_domain; |
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2342 | Serge | 365 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
2325 | Serge | 366 | s32 pinned:2; |
367 | u32 tiling:2; |
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368 | u32 dirty:1; |
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369 | u32 purgeable:1; |
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3031 | serge | 370 | s32 ring:4; |
4560 | Serge | 371 | u32 cache_level:3; |
4104 | Serge | 372 | } **active_bo, **pinned_bo; |
373 | u32 *active_bo_count, *pinned_bo_count; |
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2325 | Serge | 374 | struct intel_overlay_error_state *overlay; |
375 | struct intel_display_error_state *display; |
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4560 | Serge | 376 | int hangcheck_score[I915_NUM_RINGS]; |
377 | enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS]; |
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2325 | Serge | 378 | }; |
379 | |||
4560 | Serge | 380 | struct intel_connector; |
3746 | Serge | 381 | struct intel_crtc_config; |
382 | struct intel_crtc; |
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4104 | Serge | 383 | struct intel_limit; |
384 | struct dpll; |
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3746 | Serge | 385 | |
2325 | Serge | 386 | struct drm_i915_display_funcs { |
387 | bool (*fbc_enabled)(struct drm_device *dev); |
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4560 | Serge | 388 | void (*enable_fbc)(struct drm_crtc *crtc); |
2325 | Serge | 389 | void (*disable_fbc)(struct drm_device *dev); |
390 | int (*get_display_clock_speed)(struct drm_device *dev); |
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391 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
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4104 | Serge | 392 | /** |
393 | * find_dpll() - Find the best values for the PLL |
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394 | * @limit: limits for the PLL |
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395 | * @crtc: current CRTC |
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396 | * @target: target frequency in kHz |
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397 | * @refclk: reference clock frequency in kHz |
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398 | * @match_clock: if provided, @best_clock P divider must |
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399 | * match the P divider from @match_clock |
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400 | * used for LVDS downclocking |
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401 | * @best_clock: best PLL values found |
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402 | * |
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403 | * Returns true on success, false on failure. |
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404 | */ |
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405 | bool (*find_dpll)(const struct intel_limit *limit, |
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406 | struct drm_crtc *crtc, |
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407 | int target, int refclk, |
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408 | struct dpll *match_clock, |
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409 | struct dpll *best_clock); |
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4560 | Serge | 410 | void (*update_wm)(struct drm_crtc *crtc); |
4104 | Serge | 411 | void (*update_sprite_wm)(struct drm_plane *plane, |
412 | struct drm_crtc *crtc, |
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413 | uint32_t sprite_width, int pixel_size, |
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414 | bool enable, bool scaled); |
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3243 | Serge | 415 | void (*modeset_global_resources)(struct drm_device *dev); |
3746 | Serge | 416 | /* Returns the active state of the crtc, and if the crtc is active, |
417 | * fills out the pipe-config with the hw state. */ |
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418 | bool (*get_pipe_config)(struct intel_crtc *, |
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419 | struct intel_crtc_config *); |
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2325 | Serge | 420 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
421 | int x, int y, |
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422 | struct drm_framebuffer *old_fb); |
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3031 | serge | 423 | void (*crtc_enable)(struct drm_crtc *crtc); |
424 | void (*crtc_disable)(struct drm_crtc *crtc); |
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425 | void (*off)(struct drm_crtc *crtc); |
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2342 | Serge | 426 | void (*write_eld)(struct drm_connector *connector, |
4560 | Serge | 427 | struct drm_crtc *crtc, |
428 | struct drm_display_mode *mode); |
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2325 | Serge | 429 | void (*fdi_link_train)(struct drm_crtc *crtc); |
430 | void (*init_clock_gating)(struct drm_device *dev); |
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431 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
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432 | struct drm_framebuffer *fb, |
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4104 | Serge | 433 | struct drm_i915_gem_object *obj, |
434 | uint32_t flags); |
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2325 | Serge | 435 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
436 | int x, int y); |
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3480 | Serge | 437 | void (*hpd_irq_setup)(struct drm_device *dev); |
2325 | Serge | 438 | /* clock updates for mode set */ |
439 | /* cursor updates */ |
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440 | /* render clock increase/decrease */ |
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441 | /* display clock increase/decrease */ |
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442 | /* pll clock increase/decrease */ |
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4560 | Serge | 443 | |
444 | int (*setup_backlight)(struct intel_connector *connector); |
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445 | uint32_t (*get_backlight)(struct intel_connector *connector); |
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446 | void (*set_backlight)(struct intel_connector *connector, |
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447 | uint32_t level); |
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448 | void (*disable_backlight)(struct intel_connector *connector); |
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449 | void (*enable_backlight)(struct intel_connector *connector); |
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2325 | Serge | 450 | }; |
451 | |||
4104 | Serge | 452 | struct intel_uncore_funcs { |
4560 | Serge | 453 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
454 | int fw_engine); |
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455 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
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456 | int fw_engine); |
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457 | |||
458 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
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459 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
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460 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
||
461 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
||
462 | |||
463 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, |
||
464 | uint8_t val, bool trace); |
||
465 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, |
||
466 | uint16_t val, bool trace); |
||
467 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, |
||
468 | uint32_t val, bool trace); |
||
469 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, |
||
470 | uint64_t val, bool trace); |
||
3031 | serge | 471 | }; |
472 | |||
4104 | Serge | 473 | struct intel_uncore { |
474 | spinlock_t lock; /** lock is also taken in irq contexts. */ |
||
3031 | serge | 475 | |
4104 | Serge | 476 | struct intel_uncore_funcs funcs; |
477 | |||
478 | unsigned fifo_count; |
||
479 | unsigned forcewake_count; |
||
4560 | Serge | 480 | |
481 | unsigned fw_rendercount; |
||
482 | unsigned fw_mediacount; |
||
483 | |||
484 | struct delayed_work force_wake_work; |
||
4104 | Serge | 485 | }; |
486 | |||
487 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
||
488 | func(is_mobile) sep \ |
||
489 | func(is_i85x) sep \ |
||
490 | func(is_i915g) sep \ |
||
491 | func(is_i945gm) sep \ |
||
492 | func(is_g33) sep \ |
||
493 | func(need_gfx_hws) sep \ |
||
494 | func(is_g4x) sep \ |
||
495 | func(is_pineview) sep \ |
||
496 | func(is_broadwater) sep \ |
||
497 | func(is_crestline) sep \ |
||
498 | func(is_ivybridge) sep \ |
||
499 | func(is_valleyview) sep \ |
||
500 | func(is_haswell) sep \ |
||
4560 | Serge | 501 | func(is_preliminary) sep \ |
4104 | Serge | 502 | func(has_fbc) sep \ |
503 | func(has_pipe_cxsr) sep \ |
||
504 | func(has_hotplug) sep \ |
||
505 | func(cursor_needs_physical) sep \ |
||
506 | func(has_overlay) sep \ |
||
507 | func(overlay_needs_physical) sep \ |
||
508 | func(supports_tv) sep \ |
||
509 | func(has_llc) sep \ |
||
510 | func(has_ddi) sep \ |
||
511 | func(has_fpga_dbg) |
||
512 | |||
513 | #define DEFINE_FLAG(name) u8 name:1 |
||
514 | #define SEP_SEMICOLON ; |
||
515 | |||
2325 | Serge | 516 | struct intel_device_info { |
3480 | Serge | 517 | u32 display_mmio_offset; |
3746 | Serge | 518 | u8 num_pipes:3; |
2325 | Serge | 519 | u8 gen; |
4560 | Serge | 520 | u8 ring_mask; /* Rings supported by the HW */ |
4104 | Serge | 521 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
2325 | Serge | 522 | }; |
523 | |||
4104 | Serge | 524 | #undef DEFINE_FLAG |
525 | #undef SEP_SEMICOLON |
||
526 | |||
3480 | Serge | 527 | enum i915_cache_level { |
528 | I915_CACHE_NONE = 0, |
||
4104 | Serge | 529 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
530 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc |
||
531 | caches, eg sampler/render caches, and the |
||
532 | large Last-Level-Cache. LLC is coherent with |
||
533 | the CPU, but L3 is only visible to the GPU. */ |
||
534 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
||
3480 | Serge | 535 | }; |
536 | |||
4104 | Serge | 537 | typedef uint32_t gen6_gtt_pte_t; |
538 | |||
539 | struct i915_address_space { |
||
540 | struct drm_mm mm; |
||
541 | struct drm_device *dev; |
||
542 | struct list_head global_link; |
||
543 | unsigned long start; /* Start offset always 0 for dri2 */ |
||
544 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ |
||
545 | |||
546 | struct { |
||
547 | dma_addr_t addr; |
||
548 | struct page *page; |
||
549 | } scratch; |
||
550 | |||
551 | /** |
||
552 | * List of objects currently involved in rendering. |
||
553 | * |
||
554 | * Includes buffers having the contents of their GPU caches |
||
555 | * flushed, not necessarily primitives. last_rendering_seqno |
||
556 | * represents when the rendering involved will be completed. |
||
557 | * |
||
558 | * A reference is held on the buffer while on this list. |
||
559 | */ |
||
560 | struct list_head active_list; |
||
561 | |||
562 | /** |
||
563 | * LRU list of objects which are not in the ringbuffer and |
||
564 | * are ready to unbind, but are still in the GTT. |
||
565 | * |
||
566 | * last_rendering_seqno is 0 while an object is in this list. |
||
567 | * |
||
568 | * A reference is not held on the buffer while on this list, |
||
569 | * as merely being GTT-bound shouldn't prevent its being |
||
570 | * freed, and we'll pull it off the list in the free path. |
||
571 | */ |
||
572 | struct list_head inactive_list; |
||
573 | |||
574 | /* FIXME: Need a more generic return type */ |
||
575 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, |
||
4280 | Serge | 576 | enum i915_cache_level level, |
577 | bool valid); /* Create a valid PTE */ |
||
4104 | Serge | 578 | void (*clear_range)(struct i915_address_space *vm, |
579 | unsigned int first_entry, |
||
4280 | Serge | 580 | unsigned int num_entries, |
581 | bool use_scratch); |
||
4104 | Serge | 582 | void (*insert_entries)(struct i915_address_space *vm, |
583 | struct sg_table *st, |
||
584 | unsigned int first_entry, |
||
585 | enum i915_cache_level cache_level); |
||
586 | void (*cleanup)(struct i915_address_space *vm); |
||
587 | }; |
||
588 | |||
3480 | Serge | 589 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
590 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
||
591 | * collateral associated with any va->pa translations GEN hardware also has a |
||
592 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
||
593 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
||
594 | * the spec. |
||
595 | */ |
||
596 | struct i915_gtt { |
||
4104 | Serge | 597 | struct i915_address_space base; |
3480 | Serge | 598 | size_t stolen_size; /* Total size of stolen memory */ |
599 | |||
600 | unsigned long mappable_end; /* End offset that we can CPU map */ |
||
4539 | Serge | 601 | void *mappable; /* Mapping to our CPU mappable region */ |
3480 | Serge | 602 | phys_addr_t mappable_base; /* PA of our GMADR */ |
603 | |||
604 | /** "Graphics Stolen Memory" holds the global PTEs */ |
||
605 | void __iomem *gsm; |
||
606 | |||
607 | bool do_idle_maps; |
||
608 | |||
4104 | Serge | 609 | int mtrr; |
610 | |||
3480 | Serge | 611 | /* global gtt ops */ |
612 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
||
613 | size_t *stolen, phys_addr_t *mappable_base, |
||
614 | unsigned long *mappable_end); |
||
615 | }; |
||
4104 | Serge | 616 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
3480 | Serge | 617 | |
3031 | serge | 618 | struct i915_hw_ppgtt { |
4104 | Serge | 619 | struct i915_address_space base; |
3031 | serge | 620 | unsigned num_pd_entries; |
4560 | Serge | 621 | union { |
3243 | Serge | 622 | struct page **pt_pages; |
4560 | Serge | 623 | struct page *gen8_pt_pages; |
624 | }; |
||
625 | struct page **pd_pages; |
||
626 | int num_pd_pages; |
||
627 | int num_pt_pages; |
||
628 | union { |
||
3031 | serge | 629 | uint32_t pd_offset; |
4560 | Serge | 630 | dma_addr_t pd_dma_addr[4]; |
631 | }; |
||
632 | union { |
||
3031 | serge | 633 | dma_addr_t *pt_dma_addr; |
4560 | Serge | 634 | dma_addr_t *gen8_pt_dma_addr[4]; |
635 | }; |
||
3746 | Serge | 636 | int (*enable)(struct drm_device *dev); |
3031 | serge | 637 | }; |
638 | |||
4104 | Serge | 639 | /** |
640 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a |
||
641 | * VMA's presence cannot be guaranteed before binding, or after unbinding the |
||
642 | * object into/from the address space. |
||
643 | * |
||
644 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime |
||
645 | * will always be <= an objects lifetime. So object refcounting should cover us. |
||
646 | */ |
||
647 | struct i915_vma { |
||
648 | struct drm_mm_node node; |
||
649 | struct drm_i915_gem_object *obj; |
||
650 | struct i915_address_space *vm; |
||
3031 | serge | 651 | |
4104 | Serge | 652 | /** This object's place on the active/inactive lists */ |
653 | struct list_head mm_list; |
||
654 | |||
655 | struct list_head vma_link; /* Link in the object's VMA list */ |
||
656 | |||
657 | /** This vma's place in the batchbuffer or on the eviction list */ |
||
658 | struct list_head exec_list; |
||
659 | |||
4560 | Serge | 660 | /** |
661 | * Used for performing relocations during execbuffer insertion. |
||
662 | */ |
||
663 | struct hlist_node exec_node; |
||
664 | unsigned long exec_handle; |
||
665 | struct drm_i915_gem_exec_object2 *exec_entry; |
||
666 | |||
4104 | Serge | 667 | }; |
668 | |||
669 | struct i915_ctx_hang_stats { |
||
670 | /* This context had batch pending when hang was declared */ |
||
671 | unsigned batch_pending; |
||
672 | |||
673 | /* This context had batch active when hang was declared */ |
||
674 | unsigned batch_active; |
||
4560 | Serge | 675 | |
676 | /* Time when this context was last blamed for a GPU reset */ |
||
677 | unsigned long guilty_ts; |
||
678 | |||
679 | /* This context is banned to submit more work */ |
||
680 | bool banned; |
||
4104 | Serge | 681 | }; |
682 | |||
3031 | serge | 683 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
684 | #define DEFAULT_CONTEXT_ID 0 |
||
685 | struct i915_hw_context { |
||
4104 | Serge | 686 | struct kref ref; |
3031 | serge | 687 | int id; |
688 | bool is_initialized; |
||
4560 | Serge | 689 | uint8_t remap_slice; |
3031 | serge | 690 | struct drm_i915_file_private *file_priv; |
691 | struct intel_ring_buffer *ring; |
||
692 | struct drm_i915_gem_object *obj; |
||
4104 | Serge | 693 | struct i915_ctx_hang_stats hang_stats; |
4560 | Serge | 694 | |
695 | struct list_head link; |
||
3031 | serge | 696 | }; |
697 | |||
4104 | Serge | 698 | struct i915_fbc { |
699 | unsigned long size; |
||
700 | unsigned int fb_id; |
||
701 | enum plane plane; |
||
702 | int y; |
||
703 | |||
704 | struct drm_mm_node *compressed_fb; |
||
705 | struct drm_mm_node *compressed_llb; |
||
706 | |||
707 | struct intel_fbc_work { |
||
708 | struct delayed_work work; |
||
709 | struct drm_crtc *crtc; |
||
710 | struct drm_framebuffer *fb; |
||
711 | } *fbc_work; |
||
712 | |||
4539 | Serge | 713 | enum no_fbc_reason { |
4104 | Serge | 714 | FBC_OK, /* FBC is enabled */ |
715 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ |
||
2325 | Serge | 716 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
4104 | Serge | 717 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ |
2325 | Serge | 718 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
719 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
||
720 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
||
721 | FBC_NOT_TILED, /* buffer not tiled */ |
||
722 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
||
723 | FBC_MODULE_PARAM, |
||
4104 | Serge | 724 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
725 | } no_fbc_reason; |
||
2325 | Serge | 726 | }; |
727 | |||
4560 | Serge | 728 | struct i915_psr { |
729 | bool sink_support; |
||
730 | bool source_ok; |
||
4104 | Serge | 731 | }; |
732 | |||
2325 | Serge | 733 | enum intel_pch { |
3031 | serge | 734 | PCH_NONE = 0, /* No PCH present */ |
2325 | Serge | 735 | PCH_IBX, /* Ibexpeak PCH */ |
736 | PCH_CPT, /* Cougarpoint PCH */ |
||
3031 | serge | 737 | PCH_LPT, /* Lynxpoint PCH */ |
3746 | Serge | 738 | PCH_NOP, |
2325 | Serge | 739 | }; |
740 | |||
3243 | Serge | 741 | enum intel_sbi_destination { |
742 | SBI_ICLK, |
||
743 | SBI_MPHY, |
||
744 | }; |
||
745 | |||
2325 | Serge | 746 | #define QUIRK_PIPEA_FORCE (1<<0) |
747 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
||
3031 | serge | 748 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
2325 | Serge | 749 | |
750 | struct intel_fbdev; |
||
751 | struct intel_fbc_work; |
||
752 | |||
3031 | serge | 753 | struct intel_gmbus { |
754 | struct i2c_adapter adapter; |
||
3243 | Serge | 755 | u32 force_bit; |
3031 | serge | 756 | u32 reg0; |
757 | u32 gpio_reg; |
||
758 | struct i2c_algo_bit_data bit_algo; |
||
759 | struct drm_i915_private *dev_priv; |
||
760 | }; |
||
761 | |||
3243 | Serge | 762 | struct i915_suspend_saved_registers { |
2325 | Serge | 763 | u8 saveLBB; |
764 | u32 saveDSPACNTR; |
||
765 | u32 saveDSPBCNTR; |
||
766 | u32 saveDSPARB; |
||
767 | u32 savePIPEACONF; |
||
768 | u32 savePIPEBCONF; |
||
769 | u32 savePIPEASRC; |
||
770 | u32 savePIPEBSRC; |
||
771 | u32 saveFPA0; |
||
772 | u32 saveFPA1; |
||
773 | u32 saveDPLL_A; |
||
774 | u32 saveDPLL_A_MD; |
||
775 | u32 saveHTOTAL_A; |
||
776 | u32 saveHBLANK_A; |
||
777 | u32 saveHSYNC_A; |
||
778 | u32 saveVTOTAL_A; |
||
779 | u32 saveVBLANK_A; |
||
780 | u32 saveVSYNC_A; |
||
781 | u32 saveBCLRPAT_A; |
||
782 | u32 saveTRANSACONF; |
||
783 | u32 saveTRANS_HTOTAL_A; |
||
784 | u32 saveTRANS_HBLANK_A; |
||
785 | u32 saveTRANS_HSYNC_A; |
||
786 | u32 saveTRANS_VTOTAL_A; |
||
787 | u32 saveTRANS_VBLANK_A; |
||
788 | u32 saveTRANS_VSYNC_A; |
||
789 | u32 savePIPEASTAT; |
||
790 | u32 saveDSPASTRIDE; |
||
791 | u32 saveDSPASIZE; |
||
792 | u32 saveDSPAPOS; |
||
793 | u32 saveDSPAADDR; |
||
794 | u32 saveDSPASURF; |
||
795 | u32 saveDSPATILEOFF; |
||
796 | u32 savePFIT_PGM_RATIOS; |
||
797 | u32 saveBLC_HIST_CTL; |
||
798 | u32 saveBLC_PWM_CTL; |
||
799 | u32 saveBLC_PWM_CTL2; |
||
4560 | Serge | 800 | u32 saveBLC_HIST_CTL_B; |
2325 | Serge | 801 | u32 saveBLC_CPU_PWM_CTL; |
802 | u32 saveBLC_CPU_PWM_CTL2; |
||
803 | u32 saveFPB0; |
||
804 | u32 saveFPB1; |
||
805 | u32 saveDPLL_B; |
||
806 | u32 saveDPLL_B_MD; |
||
807 | u32 saveHTOTAL_B; |
||
808 | u32 saveHBLANK_B; |
||
809 | u32 saveHSYNC_B; |
||
810 | u32 saveVTOTAL_B; |
||
811 | u32 saveVBLANK_B; |
||
812 | u32 saveVSYNC_B; |
||
813 | u32 saveBCLRPAT_B; |
||
814 | u32 saveTRANSBCONF; |
||
815 | u32 saveTRANS_HTOTAL_B; |
||
816 | u32 saveTRANS_HBLANK_B; |
||
817 | u32 saveTRANS_HSYNC_B; |
||
818 | u32 saveTRANS_VTOTAL_B; |
||
819 | u32 saveTRANS_VBLANK_B; |
||
820 | u32 saveTRANS_VSYNC_B; |
||
821 | u32 savePIPEBSTAT; |
||
822 | u32 saveDSPBSTRIDE; |
||
823 | u32 saveDSPBSIZE; |
||
824 | u32 saveDSPBPOS; |
||
825 | u32 saveDSPBADDR; |
||
826 | u32 saveDSPBSURF; |
||
827 | u32 saveDSPBTILEOFF; |
||
828 | u32 saveVGA0; |
||
829 | u32 saveVGA1; |
||
830 | u32 saveVGA_PD; |
||
831 | u32 saveVGACNTRL; |
||
832 | u32 saveADPA; |
||
833 | u32 saveLVDS; |
||
834 | u32 savePP_ON_DELAYS; |
||
835 | u32 savePP_OFF_DELAYS; |
||
836 | u32 saveDVOA; |
||
837 | u32 saveDVOB; |
||
838 | u32 saveDVOC; |
||
839 | u32 savePP_ON; |
||
840 | u32 savePP_OFF; |
||
841 | u32 savePP_CONTROL; |
||
842 | u32 savePP_DIVISOR; |
||
843 | u32 savePFIT_CONTROL; |
||
844 | u32 save_palette_a[256]; |
||
845 | u32 save_palette_b[256]; |
||
846 | u32 saveDPFC_CB_BASE; |
||
847 | u32 saveFBC_CFB_BASE; |
||
848 | u32 saveFBC_LL_BASE; |
||
849 | u32 saveFBC_CONTROL; |
||
850 | u32 saveFBC_CONTROL2; |
||
851 | u32 saveIER; |
||
852 | u32 saveIIR; |
||
853 | u32 saveIMR; |
||
854 | u32 saveDEIER; |
||
855 | u32 saveDEIMR; |
||
856 | u32 saveGTIER; |
||
857 | u32 saveGTIMR; |
||
858 | u32 saveFDI_RXA_IMR; |
||
859 | u32 saveFDI_RXB_IMR; |
||
860 | u32 saveCACHE_MODE_0; |
||
861 | u32 saveMI_ARB_STATE; |
||
862 | u32 saveSWF0[16]; |
||
863 | u32 saveSWF1[16]; |
||
864 | u32 saveSWF2[3]; |
||
865 | u8 saveMSR; |
||
866 | u8 saveSR[8]; |
||
867 | u8 saveGR[25]; |
||
868 | u8 saveAR_INDEX; |
||
869 | u8 saveAR[21]; |
||
870 | u8 saveDACMASK; |
||
871 | u8 saveCR[37]; |
||
2342 | Serge | 872 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
2325 | Serge | 873 | u32 saveCURACNTR; |
874 | u32 saveCURAPOS; |
||
875 | u32 saveCURABASE; |
||
876 | u32 saveCURBCNTR; |
||
877 | u32 saveCURBPOS; |
||
878 | u32 saveCURBBASE; |
||
879 | u32 saveCURSIZE; |
||
880 | u32 saveDP_B; |
||
881 | u32 saveDP_C; |
||
882 | u32 saveDP_D; |
||
883 | u32 savePIPEA_GMCH_DATA_M; |
||
884 | u32 savePIPEB_GMCH_DATA_M; |
||
885 | u32 savePIPEA_GMCH_DATA_N; |
||
886 | u32 savePIPEB_GMCH_DATA_N; |
||
887 | u32 savePIPEA_DP_LINK_M; |
||
888 | u32 savePIPEB_DP_LINK_M; |
||
889 | u32 savePIPEA_DP_LINK_N; |
||
890 | u32 savePIPEB_DP_LINK_N; |
||
891 | u32 saveFDI_RXA_CTL; |
||
892 | u32 saveFDI_TXA_CTL; |
||
893 | u32 saveFDI_RXB_CTL; |
||
894 | u32 saveFDI_TXB_CTL; |
||
895 | u32 savePFA_CTL_1; |
||
896 | u32 savePFB_CTL_1; |
||
897 | u32 savePFA_WIN_SZ; |
||
898 | u32 savePFB_WIN_SZ; |
||
899 | u32 savePFA_WIN_POS; |
||
900 | u32 savePFB_WIN_POS; |
||
901 | u32 savePCH_DREF_CONTROL; |
||
902 | u32 saveDISP_ARB_CTL; |
||
903 | u32 savePIPEA_DATA_M1; |
||
904 | u32 savePIPEA_DATA_N1; |
||
905 | u32 savePIPEA_LINK_M1; |
||
906 | u32 savePIPEA_LINK_N1; |
||
907 | u32 savePIPEB_DATA_M1; |
||
908 | u32 savePIPEB_DATA_N1; |
||
909 | u32 savePIPEB_LINK_M1; |
||
910 | u32 savePIPEB_LINK_N1; |
||
911 | u32 saveMCHBAR_RENDER_STANDBY; |
||
912 | u32 savePCH_PORT_HOTPLUG; |
||
3243 | Serge | 913 | }; |
2325 | Serge | 914 | |
3243 | Serge | 915 | struct intel_gen6_power_mgmt { |
4104 | Serge | 916 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
3243 | Serge | 917 | struct work_struct work; |
918 | u32 pm_iir; |
||
919 | |||
920 | /* The below variables an all the rps hw state are protected by |
||
921 | * dev->struct mutext. */ |
||
922 | u8 cur_delay; |
||
923 | u8 min_delay; |
||
924 | u8 max_delay; |
||
4104 | Serge | 925 | u8 rpe_delay; |
4560 | Serge | 926 | u8 rp1_delay; |
927 | u8 rp0_delay; |
||
3746 | Serge | 928 | u8 hw_max; |
3243 | Serge | 929 | |
4560 | Serge | 930 | int last_adj; |
931 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; |
||
932 | |||
933 | bool enabled; |
||
3243 | Serge | 934 | struct delayed_work delayed_resume_work; |
935 | |||
936 | /* |
||
937 | * Protects RPS/RC6 register access and PCU communication. |
||
938 | * Must be taken after struct_mutex if nested. |
||
939 | */ |
||
940 | struct mutex hw_lock; |
||
941 | }; |
||
942 | |||
3480 | Serge | 943 | /* defined intel_pm.c */ |
944 | extern spinlock_t mchdev_lock; |
||
945 | |||
3243 | Serge | 946 | struct intel_ilk_power_mgmt { |
947 | u8 cur_delay; |
||
948 | u8 min_delay; |
||
949 | u8 max_delay; |
||
950 | u8 fmax; |
||
951 | u8 fstart; |
||
952 | |||
953 | u64 last_count1; |
||
954 | unsigned long last_time1; |
||
955 | unsigned long chipset_power; |
||
956 | u64 last_count2; |
||
957 | struct timespec last_time2; |
||
958 | unsigned long gfx_power; |
||
959 | u8 corr; |
||
960 | |||
961 | int c_m; |
||
962 | int r_t; |
||
963 | |||
964 | struct drm_i915_gem_object *pwrctx; |
||
965 | struct drm_i915_gem_object *renderctx; |
||
966 | }; |
||
967 | |||
4104 | Serge | 968 | /* Power well structure for haswell */ |
969 | struct i915_power_well { |
||
4560 | Serge | 970 | const char *name; |
971 | bool always_on; |
||
4104 | Serge | 972 | /* power well enable/disable usage count */ |
973 | int count; |
||
4560 | Serge | 974 | unsigned long domains; |
975 | void *data; |
||
976 | void (*set)(struct drm_device *dev, struct i915_power_well *power_well, |
||
977 | bool enable); |
||
978 | bool (*is_enabled)(struct drm_device *dev, |
||
979 | struct i915_power_well *power_well); |
||
4104 | Serge | 980 | }; |
981 | |||
4560 | Serge | 982 | struct i915_power_domains { |
983 | /* |
||
984 | * Power wells needed for initialization at driver init and suspend |
||
985 | * time are on. They are kept on until after the first modeset. |
||
986 | */ |
||
987 | bool init_power_on; |
||
988 | int power_well_count; |
||
989 | |||
990 | struct mutex lock; |
||
991 | int domain_use_count[POWER_DOMAIN_NUM]; |
||
992 | struct i915_power_well *power_wells; |
||
993 | }; |
||
994 | |||
3243 | Serge | 995 | struct i915_dri1_state { |
996 | unsigned allow_batchbuffer : 1; |
||
997 | u32 __iomem *gfx_hws_cpu_addr; |
||
998 | |||
999 | unsigned int cpp; |
||
1000 | int back_offset; |
||
1001 | int front_offset; |
||
1002 | int current_page; |
||
1003 | int page_flipping; |
||
1004 | |||
1005 | uint32_t counter; |
||
1006 | }; |
||
1007 | |||
4104 | Serge | 1008 | struct i915_ums_state { |
1009 | /** |
||
1010 | * Flag if the X Server, and thus DRM, is not currently in |
||
1011 | * control of the device. |
||
1012 | * |
||
1013 | * This is set between LeaveVT and EnterVT. It needs to be |
||
1014 | * replaced with a semaphore. It also needs to be |
||
1015 | * transitioned away from for kernel modesetting. |
||
1016 | */ |
||
1017 | int mm_suspended; |
||
1018 | }; |
||
1019 | |||
4560 | Serge | 1020 | #define MAX_L3_SLICES 2 |
3243 | Serge | 1021 | struct intel_l3_parity { |
4560 | Serge | 1022 | u32 *remap_info[MAX_L3_SLICES]; |
3243 | Serge | 1023 | struct work_struct error_work; |
4560 | Serge | 1024 | int which_slice; |
3243 | Serge | 1025 | }; |
1026 | |||
3480 | Serge | 1027 | struct i915_gem_mm { |
1028 | /** Memory allocator for GTT stolen memory */ |
||
1029 | struct drm_mm stolen; |
||
1030 | /** List of all objects in gtt_space. Used to restore gtt |
||
1031 | * mappings on resume */ |
||
1032 | struct list_head bound_list; |
||
1033 | /** |
||
1034 | * List of objects which are not bound to the GTT (thus |
||
1035 | * are idle and not used by the GPU) but still have |
||
1036 | * (presumably uncached) pages still attached. |
||
1037 | */ |
||
1038 | struct list_head unbound_list; |
||
1039 | |||
1040 | /** Usable portion of the GTT for GEM */ |
||
1041 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
||
1042 | |||
1043 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
||
1044 | struct i915_hw_ppgtt *aliasing_ppgtt; |
||
1045 | |||
1046 | /** LRU list of objects with fence regs on them. */ |
||
1047 | struct list_head fence_list; |
||
1048 | |||
1049 | /** |
||
1050 | * We leave the user IRQ off as much as possible, |
||
1051 | * but this means that requests will finish and never |
||
1052 | * be retired once the system goes idle. Set a timer to |
||
1053 | * fire periodically while the ring is running. When it |
||
1054 | * fires, go retire requests. |
||
1055 | */ |
||
1056 | struct delayed_work retire_work; |
||
1057 | |||
1058 | /** |
||
4560 | Serge | 1059 | * When we detect an idle GPU, we want to turn on |
1060 | * powersaving features. So once we see that there |
||
1061 | * are no more requests outstanding and no more |
||
1062 | * arrive within a small period of time, we fire |
||
1063 | * off the idle_work. |
||
1064 | */ |
||
1065 | struct delayed_work idle_work; |
||
1066 | |||
1067 | /** |
||
3480 | Serge | 1068 | * Are we in a non-interruptible section of code like |
1069 | * modesetting? |
||
1070 | */ |
||
1071 | bool interruptible; |
||
1072 | |||
1073 | /** Bit 6 swizzling required for X tiling */ |
||
1074 | uint32_t bit_6_swizzle_x; |
||
1075 | /** Bit 6 swizzling required for Y tiling */ |
||
1076 | uint32_t bit_6_swizzle_y; |
||
1077 | |||
1078 | /* storage for physical objects */ |
||
1079 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
||
1080 | |||
1081 | /* accounting, useful for userland debugging */ |
||
4104 | Serge | 1082 | spinlock_t object_stat_lock; |
3480 | Serge | 1083 | size_t object_memory; |
1084 | u32 object_count; |
||
1085 | }; |
||
1086 | |||
4104 | Serge | 1087 | struct drm_i915_error_state_buf { |
1088 | unsigned bytes; |
||
1089 | unsigned size; |
||
1090 | int err; |
||
1091 | u8 *buf; |
||
1092 | loff_t start; |
||
1093 | loff_t pos; |
||
1094 | }; |
||
1095 | |||
1096 | struct i915_error_state_file_priv { |
||
1097 | struct drm_device *dev; |
||
1098 | struct drm_i915_error_state *error; |
||
1099 | }; |
||
1100 | |||
3480 | Serge | 1101 | struct i915_gpu_error { |
1102 | /* For hangcheck timer */ |
||
1103 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
||
1104 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
||
4560 | Serge | 1105 | /* Hang gpu twice in this window and your context gets banned */ |
1106 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) |
||
1107 | |||
3480 | Serge | 1108 | struct timer_list hangcheck_timer; |
1109 | |||
1110 | /* For reset and error_state handling. */ |
||
1111 | spinlock_t lock; |
||
1112 | /* Protected by the above dev->gpu_error.lock. */ |
||
1113 | struct drm_i915_error_state *first_error; |
||
1114 | struct work_struct work; |
||
1115 | |||
1116 | |||
4560 | Serge | 1117 | unsigned long missed_irq_rings; |
1118 | |||
3480 | Serge | 1119 | /** |
4560 | Serge | 1120 | * State variable controlling the reset flow and count |
3480 | Serge | 1121 | * |
4560 | Serge | 1122 | * This is a counter which gets incremented when reset is triggered, |
1123 | * and again when reset has been handled. So odd values (lowest bit set) |
||
1124 | * means that reset is in progress and even values that |
||
1125 | * (reset_counter >> 1):th reset was successfully completed. |
||
3480 | Serge | 1126 | * |
4560 | Serge | 1127 | * If reset is not completed succesfully, the I915_WEDGE bit is |
1128 | * set meaning that hardware is terminally sour and there is no |
||
1129 | * recovery. All waiters on the reset_queue will be woken when |
||
1130 | * that happens. |
||
1131 | * |
||
1132 | * This counter is used by the wait_seqno code to notice that reset |
||
1133 | * event happened and it needs to restart the entire ioctl (since most |
||
1134 | * likely the seqno it waited for won't ever signal anytime soon). |
||
1135 | * |
||
3480 | Serge | 1136 | * This is important for lock-free wait paths, where no contended lock |
1137 | * naturally enforces the correct ordering between the bail-out of the |
||
1138 | * waiter and the gpu reset work code. |
||
1139 | */ |
||
1140 | atomic_t reset_counter; |
||
1141 | |||
1142 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
||
4560 | Serge | 1143 | #define I915_WEDGED (1 << 31) |
3480 | Serge | 1144 | |
1145 | /** |
||
1146 | * Waitqueue to signal when the reset has completed. Used by clients |
||
1147 | * that wait for dev_priv->mm.wedged to settle. |
||
1148 | */ |
||
1149 | wait_queue_head_t reset_queue; |
||
1150 | |||
1151 | /* For gpu hang simulation. */ |
||
1152 | unsigned int stop_rings; |
||
4560 | Serge | 1153 | |
1154 | /* For missed irq/seqno simulation. */ |
||
1155 | unsigned int test_irq_rings; |
||
3480 | Serge | 1156 | }; |
1157 | |||
1158 | enum modeset_restore { |
||
1159 | MODESET_ON_LID_OPEN, |
||
1160 | MODESET_DONE, |
||
1161 | MODESET_SUSPENDED, |
||
1162 | }; |
||
1163 | |||
4560 | Serge | 1164 | struct ddi_vbt_port_info { |
1165 | uint8_t hdmi_level_shift; |
||
1166 | |||
1167 | uint8_t supports_dvi:1; |
||
1168 | uint8_t supports_hdmi:1; |
||
1169 | uint8_t supports_dp:1; |
||
1170 | }; |
||
1171 | |||
4104 | Serge | 1172 | struct intel_vbt_data { |
1173 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
||
1174 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
||
1175 | |||
1176 | /* Feature bits */ |
||
1177 | unsigned int int_tv_support:1; |
||
1178 | unsigned int lvds_dither:1; |
||
1179 | unsigned int lvds_vbt:1; |
||
1180 | unsigned int int_crt_support:1; |
||
1181 | unsigned int lvds_use_ssc:1; |
||
1182 | unsigned int display_clock_mode:1; |
||
1183 | unsigned int fdi_rx_polarity_inverted:1; |
||
1184 | int lvds_ssc_freq; |
||
1185 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
||
1186 | |||
1187 | /* eDP */ |
||
1188 | int edp_rate; |
||
1189 | int edp_lanes; |
||
1190 | int edp_preemphasis; |
||
1191 | int edp_vswing; |
||
1192 | bool edp_initialized; |
||
1193 | bool edp_support; |
||
1194 | int edp_bpp; |
||
1195 | struct edp_power_seq edp_pps; |
||
1196 | |||
4560 | Serge | 1197 | struct { |
1198 | u16 pwm_freq_hz; |
||
1199 | bool active_low_pwm; |
||
1200 | } backlight; |
||
1201 | |||
1202 | /* MIPI DSI */ |
||
1203 | struct { |
||
1204 | u16 panel_id; |
||
1205 | } dsi; |
||
1206 | |||
4104 | Serge | 1207 | int crt_ddc_pin; |
1208 | |||
1209 | int child_dev_num; |
||
4560 | Serge | 1210 | union child_device_config *child_dev; |
1211 | |||
1212 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; |
||
4104 | Serge | 1213 | }; |
1214 | |||
1215 | enum intel_ddb_partitioning { |
||
1216 | INTEL_DDB_PART_1_2, |
||
1217 | INTEL_DDB_PART_5_6, /* IVB+ */ |
||
1218 | }; |
||
1219 | |||
1220 | struct intel_wm_level { |
||
1221 | bool enable; |
||
1222 | uint32_t pri_val; |
||
1223 | uint32_t spr_val; |
||
1224 | uint32_t cur_val; |
||
1225 | uint32_t fbc_val; |
||
1226 | }; |
||
1227 | |||
4560 | Serge | 1228 | struct ilk_wm_values { |
1229 | uint32_t wm_pipe[3]; |
||
1230 | uint32_t wm_lp[3]; |
||
1231 | uint32_t wm_lp_spr[3]; |
||
1232 | uint32_t wm_linetime[3]; |
||
1233 | bool enable_fbc_wm; |
||
1234 | enum intel_ddb_partitioning partitioning; |
||
1235 | }; |
||
1236 | |||
4104 | Serge | 1237 | /* |
1238 | * This struct tracks the state needed for the Package C8+ feature. |
||
1239 | * |
||
1240 | * Package states C8 and deeper are really deep PC states that can only be |
||
1241 | * reached when all the devices on the system allow it, so even if the graphics |
||
1242 | * device allows PC8+, it doesn't mean the system will actually get to these |
||
1243 | * states. |
||
1244 | * |
||
1245 | * Our driver only allows PC8+ when all the outputs are disabled, the power well |
||
1246 | * is disabled and the GPU is idle. When these conditions are met, we manually |
||
1247 | * do the other conditions: disable the interrupts, clocks and switch LCPLL |
||
1248 | * refclk to Fclk. |
||
1249 | * |
||
1250 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
||
1251 | * the state of some registers, so when we come back from PC8+ we need to |
||
1252 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
||
1253 | * need to take care of the registers kept by RC6. |
||
1254 | * |
||
1255 | * The interrupt disabling is part of the requirements. We can only leave the |
||
1256 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we |
||
1257 | * can lock the machine. |
||
1258 | * |
||
1259 | * Ideally every piece of our code that needs PC8+ disabled would call |
||
1260 | * hsw_disable_package_c8, which would increment disable_count and prevent the |
||
1261 | * system from reaching PC8+. But we don't have a symmetric way to do this for |
||
1262 | * everything, so we have the requirements_met and gpu_idle variables. When we |
||
1263 | * switch requirements_met or gpu_idle to true we decrease disable_count, and |
||
1264 | * increase it in the opposite case. The requirements_met variable is true when |
||
1265 | * all the CRTCs, encoders and the power well are disabled. The gpu_idle |
||
1266 | * variable is true when the GPU is idle. |
||
1267 | * |
||
1268 | * In addition to everything, we only actually enable PC8+ if disable_count |
||
1269 | * stays at zero for at least some seconds. This is implemented with the |
||
1270 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of |
||
1271 | * consecutive times when all screens are disabled and some background app |
||
1272 | * queries the state of our connectors, or we have some application constantly |
||
1273 | * waking up to use the GPU. Only after the enable_work function actually |
||
1274 | * enables PC8+ the "enable" variable will become true, which means that it can |
||
1275 | * be false even if disable_count is 0. |
||
1276 | * |
||
1277 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and |
||
1278 | * goes back to false exactly before we reenable the IRQs. We use this variable |
||
1279 | * to check if someone is trying to enable/disable IRQs while they're supposed |
||
1280 | * to be disabled. This shouldn't happen and we'll print some error messages in |
||
1281 | * case it happens, but if it actually happens we'll also update the variables |
||
1282 | * inside struct regsave so when we restore the IRQs they will contain the |
||
1283 | * latest expected values. |
||
1284 | * |
||
1285 | * For more, read "Display Sequences for Package C8" on our documentation. |
||
1286 | */ |
||
1287 | struct i915_package_c8 { |
||
1288 | bool requirements_met; |
||
1289 | bool gpu_idle; |
||
1290 | bool irqs_disabled; |
||
1291 | /* Only true after the delayed work task actually enables it. */ |
||
1292 | bool enabled; |
||
1293 | int disable_count; |
||
1294 | struct mutex lock; |
||
1295 | struct delayed_work enable_work; |
||
1296 | |||
1297 | struct { |
||
1298 | uint32_t deimr; |
||
1299 | uint32_t sdeimr; |
||
1300 | uint32_t gtimr; |
||
1301 | uint32_t gtier; |
||
1302 | uint32_t gen6_pmimr; |
||
1303 | } regsave; |
||
1304 | }; |
||
1305 | |||
4560 | Serge | 1306 | struct i915_runtime_pm { |
1307 | bool suspended; |
||
1308 | }; |
||
1309 | |||
1310 | enum intel_pipe_crc_source { |
||
1311 | INTEL_PIPE_CRC_SOURCE_NONE, |
||
1312 | INTEL_PIPE_CRC_SOURCE_PLANE1, |
||
1313 | INTEL_PIPE_CRC_SOURCE_PLANE2, |
||
1314 | INTEL_PIPE_CRC_SOURCE_PF, |
||
1315 | INTEL_PIPE_CRC_SOURCE_PIPE, |
||
1316 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
||
1317 | INTEL_PIPE_CRC_SOURCE_TV, |
||
1318 | INTEL_PIPE_CRC_SOURCE_DP_B, |
||
1319 | INTEL_PIPE_CRC_SOURCE_DP_C, |
||
1320 | INTEL_PIPE_CRC_SOURCE_DP_D, |
||
1321 | INTEL_PIPE_CRC_SOURCE_AUTO, |
||
1322 | INTEL_PIPE_CRC_SOURCE_MAX, |
||
1323 | }; |
||
1324 | |||
1325 | struct intel_pipe_crc_entry { |
||
1326 | uint32_t frame; |
||
1327 | uint32_t crc[5]; |
||
1328 | }; |
||
1329 | |||
1330 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
||
1331 | struct intel_pipe_crc { |
||
1332 | spinlock_t lock; |
||
1333 | bool opened; /* exclusive access to the result file */ |
||
1334 | struct intel_pipe_crc_entry *entries; |
||
1335 | enum intel_pipe_crc_source source; |
||
1336 | int head, tail; |
||
1337 | wait_queue_head_t wq; |
||
1338 | }; |
||
1339 | |||
3243 | Serge | 1340 | typedef struct drm_i915_private { |
1341 | struct drm_device *dev; |
||
1342 | |||
1343 | const struct intel_device_info *info; |
||
1344 | |||
1345 | int relative_constants_mode; |
||
1346 | |||
1347 | void __iomem *regs; |
||
1348 | |||
4104 | Serge | 1349 | struct intel_uncore uncore; |
3243 | Serge | 1350 | |
1351 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
||
1352 | |||
3480 | Serge | 1353 | |
3243 | Serge | 1354 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1355 | * controller on different i2c buses. */ |
||
1356 | struct mutex gmbus_mutex; |
||
1357 | |||
1358 | /** |
||
1359 | * Base address of the gmbus and gpio block. |
||
1360 | */ |
||
1361 | uint32_t gpio_mmio_base; |
||
1362 | |||
3480 | Serge | 1363 | wait_queue_head_t gmbus_wait_queue; |
1364 | |||
3243 | Serge | 1365 | struct pci_dev *bridge_dev; |
1366 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
||
3480 | Serge | 1367 | uint32_t last_seqno, next_seqno; |
3243 | Serge | 1368 | |
1369 | drm_dma_handle_t *status_page_dmah; |
||
1370 | struct resource mch_res; |
||
1371 | |||
1372 | atomic_t irq_received; |
||
1373 | |||
1374 | /* protects the irq masks */ |
||
1375 | spinlock_t irq_lock; |
||
1376 | |||
3480 | Serge | 1377 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1378 | // struct pm_qos_request pm_qos; |
||
1379 | |||
3243 | Serge | 1380 | /* DPIO indirect register protection */ |
3480 | Serge | 1381 | struct mutex dpio_lock; |
3243 | Serge | 1382 | |
1383 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
||
4560 | Serge | 1384 | union { |
3243 | Serge | 1385 | u32 irq_mask; |
4560 | Serge | 1386 | u32 de_irq_mask[I915_MAX_PIPES]; |
1387 | }; |
||
3243 | Serge | 1388 | u32 gt_irq_mask; |
4104 | Serge | 1389 | u32 pm_irq_mask; |
3243 | Serge | 1390 | |
1391 | struct work_struct hotplug_work; |
||
3480 | Serge | 1392 | bool enable_hotplug_processing; |
3746 | Serge | 1393 | struct { |
1394 | unsigned long hpd_last_jiffies; |
||
1395 | int hpd_cnt; |
||
1396 | enum { |
||
1397 | HPD_ENABLED = 0, |
||
1398 | HPD_DISABLED = 1, |
||
1399 | HPD_MARK_DISABLED = 2 |
||
1400 | } hpd_mark; |
||
1401 | } hpd_stats[HPD_NUM_PINS]; |
||
4104 | Serge | 1402 | u32 hpd_event_bits; |
4126 | Serge | 1403 | struct timer_list hotplug_reenable_timer; |
3243 | Serge | 1404 | |
3746 | Serge | 1405 | int num_plane; |
3243 | Serge | 1406 | |
4104 | Serge | 1407 | struct i915_fbc fbc; |
3243 | Serge | 1408 | struct intel_opregion opregion; |
4104 | Serge | 1409 | struct intel_vbt_data vbt; |
3243 | Serge | 1410 | |
1411 | /* overlay */ |
||
1412 | struct intel_overlay *overlay; |
||
1413 | |||
4560 | Serge | 1414 | /* backlight registers and fields in struct intel_panel */ |
1415 | spinlock_t backlight_lock; |
||
3746 | Serge | 1416 | |
3243 | Serge | 1417 | /* LVDS info */ |
1418 | bool no_aux_handshake; |
||
1419 | |||
1420 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
||
1421 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
||
1422 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
||
1423 | |||
1424 | unsigned int fsb_freq, mem_freq, is_ddr3; |
||
1425 | |||
4104 | Serge | 1426 | /** |
1427 | * wq - Driver workqueue for GEM. |
||
1428 | * |
||
1429 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
||
1430 | * locks, for otherwise the flushing done in the pageflip code will |
||
1431 | * result in deadlocks. |
||
1432 | */ |
||
3243 | Serge | 1433 | struct workqueue_struct *wq; |
1434 | |||
1435 | /* Display functions */ |
||
1436 | struct drm_i915_display_funcs display; |
||
1437 | |||
1438 | /* PCH chipset type */ |
||
1439 | enum intel_pch pch_type; |
||
1440 | unsigned short pch_id; |
||
1441 | |||
1442 | unsigned long quirks; |
||
1443 | |||
3480 | Serge | 1444 | enum modeset_restore modeset_restore; |
1445 | struct mutex modeset_restore_lock; |
||
3243 | Serge | 1446 | |
4104 | Serge | 1447 | struct list_head vm_list; /* Global list of all address spaces */ |
1448 | struct i915_gtt gtt; /* VMA representing the global address space */ |
||
2325 | Serge | 1449 | |
3480 | Serge | 1450 | struct i915_gem_mm mm; |
2325 | Serge | 1451 | |
3031 | serge | 1452 | /* Kernel Modesetting */ |
1453 | |||
2327 | Serge | 1454 | struct sdvo_device_mapping sdvo_mappings[2]; |
2325 | Serge | 1455 | |
2342 | Serge | 1456 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1457 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
||
2352 | Serge | 1458 | wait_queue_head_t pending_flip_queue; |
2325 | Serge | 1459 | |
4560 | Serge | 1460 | #ifdef CONFIG_DEBUG_FS |
1461 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; |
||
1462 | #endif |
||
1463 | |||
4104 | Serge | 1464 | int num_shared_dpll; |
1465 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
||
3243 | Serge | 1466 | struct intel_ddi_plls ddi_plls; |
4560 | Serge | 1467 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
3031 | serge | 1468 | |
2325 | Serge | 1469 | /* Reclocking support */ |
1470 | bool render_reclock_avail; |
||
1471 | bool lvds_downclock_avail; |
||
1472 | /* indicates the reduced downclock for LVDS*/ |
||
1473 | int lvds_downclock; |
||
1474 | u16 orig_clock; |
||
1475 | |||
1476 | bool mchbar_need_disable; |
||
1477 | |||
3243 | Serge | 1478 | struct intel_l3_parity l3_parity; |
1479 | |||
4104 | Serge | 1480 | /* Cannot be determined by PCIID. You must always read a register. */ |
1481 | size_t ellc_size; |
||
1482 | |||
3031 | serge | 1483 | /* gen6+ rps state */ |
3243 | Serge | 1484 | struct intel_gen6_power_mgmt rps; |
2325 | Serge | 1485 | |
3031 | serge | 1486 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1487 | * mchdev_lock in intel_pm.c */ |
||
3243 | Serge | 1488 | struct intel_ilk_power_mgmt ips; |
2325 | Serge | 1489 | |
4560 | Serge | 1490 | struct i915_power_domains power_domains; |
2325 | Serge | 1491 | |
4560 | Serge | 1492 | struct i915_psr psr; |
2325 | Serge | 1493 | |
3480 | Serge | 1494 | struct i915_gpu_error gpu_error; |
2325 | Serge | 1495 | |
4104 | Serge | 1496 | struct drm_i915_gem_object *vlv_pctx; |
1497 | |||
4560 | Serge | 1498 | #ifdef CONFIG_DRM_I915_FBDEV |
2325 | Serge | 1499 | /* list of fbdev register on this device */ |
2332 | Serge | 1500 | struct intel_fbdev *fbdev; |
4560 | Serge | 1501 | #endif |
2325 | Serge | 1502 | |
3243 | Serge | 1503 | /* |
1504 | * The console may be contended at resume, but we don't |
||
1505 | * want it to block on it. |
||
1506 | */ |
||
1507 | struct work_struct console_resume_work; |
||
1508 | |||
3031 | serge | 1509 | struct drm_property *broadcast_rgb_property; |
1510 | struct drm_property *force_audio_property; |
||
1511 | |||
1512 | uint32_t hw_context_size; |
||
4560 | Serge | 1513 | struct list_head context_list; |
3243 | Serge | 1514 | |
3480 | Serge | 1515 | u32 fdi_rx_config; |
3243 | Serge | 1516 | |
1517 | struct i915_suspend_saved_registers regfile; |
||
1518 | |||
4104 | Serge | 1519 | struct { |
1520 | /* |
||
1521 | * Raw watermark latency values: |
||
1522 | * in 0.1us units for WM0, |
||
1523 | * in 0.5us units for WM1+. |
||
1524 | */ |
||
1525 | /* primary */ |
||
1526 | uint16_t pri_latency[5]; |
||
1527 | /* sprite */ |
||
1528 | uint16_t spr_latency[5]; |
||
1529 | /* cursor */ |
||
1530 | uint16_t cur_latency[5]; |
||
4560 | Serge | 1531 | |
1532 | /* current hardware state */ |
||
1533 | struct ilk_wm_values hw; |
||
4104 | Serge | 1534 | } wm; |
1535 | |||
1536 | struct i915_package_c8 pc8; |
||
1537 | |||
4560 | Serge | 1538 | struct i915_runtime_pm pm; |
1539 | |||
3243 | Serge | 1540 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
1541 | * here! */ |
||
1542 | struct i915_dri1_state dri1; |
||
4104 | Serge | 1543 | /* Old ums support infrastructure, same warning applies. */ |
1544 | struct i915_ums_state ums; |
||
2325 | Serge | 1545 | } drm_i915_private_t; |
1546 | |||
4104 | Serge | 1547 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1548 | { |
||
1549 | return dev->dev_private; |
||
1550 | } |
||
1551 | |||
3031 | serge | 1552 | /* Iterate over initialised rings */ |
1553 | #define for_each_ring(ring__, dev_priv__, i__) \ |
||
1554 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
||
1555 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
||
1556 | |||
1557 | enum hdmi_force_audio { |
||
1558 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
||
1559 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
||
1560 | HDMI_AUDIO_AUTO, /* trust EDID */ |
||
1561 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
||
1562 | }; |
||
1563 | |||
4104 | Serge | 1564 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
2325 | Serge | 1565 | |
3031 | serge | 1566 | struct drm_i915_gem_object_ops { |
1567 | /* Interface between the GEM object and its backing storage. |
||
1568 | * get_pages() is called once prior to the use of the associated set |
||
1569 | * of pages before to binding them into the GTT, and put_pages() is |
||
1570 | * called after we no longer need them. As we expect there to be |
||
1571 | * associated cost with migrating pages between the backing storage |
||
1572 | * and making them available for the GPU (e.g. clflush), we may hold |
||
1573 | * onto the pages after they are no longer referenced by the GPU |
||
1574 | * in case they may be used again shortly (for example migrating the |
||
1575 | * pages to a different memory domain within the GTT). put_pages() |
||
1576 | * will therefore most likely be called when the object itself is |
||
1577 | * being released or under memory pressure (where we attempt to |
||
1578 | * reap pages for the shrinker). |
||
1579 | */ |
||
1580 | int (*get_pages)(struct drm_i915_gem_object *); |
||
1581 | void (*put_pages)(struct drm_i915_gem_object *); |
||
1582 | }; |
||
1583 | |||
2327 | Serge | 1584 | struct drm_i915_gem_object { |
1585 | struct drm_gem_object base; |
||
2325 | Serge | 1586 | |
3031 | serge | 1587 | const struct drm_i915_gem_object_ops *ops; |
1588 | |||
4104 | Serge | 1589 | /** List of VMAs backed by this object */ |
1590 | struct list_head vma_list; |
||
1591 | |||
3480 | Serge | 1592 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1593 | struct drm_mm_node *stolen; |
||
4104 | Serge | 1594 | struct list_head global_list; |
2327 | Serge | 1595 | |
1596 | struct list_head ring_list; |
||
4104 | Serge | 1597 | /** Used in execbuf to temporarily hold a ref */ |
1598 | struct list_head obj_exec_link; |
||
2327 | Serge | 1599 | |
1600 | /** |
||
3031 | serge | 1601 | * This is set if the object is on the active lists (has pending |
1602 | * rendering and so a non-zero seqno), and is not set if it i s on |
||
1603 | * inactive (ready to be unbound) list. |
||
2327 | Serge | 1604 | */ |
2342 | Serge | 1605 | unsigned int active:1; |
2327 | Serge | 1606 | |
1607 | /** |
||
1608 | * This is set if the object has been written to since last bound |
||
1609 | * to the GTT |
||
1610 | */ |
||
2342 | Serge | 1611 | unsigned int dirty:1; |
2327 | Serge | 1612 | |
1613 | /** |
||
1614 | * Fence register bits (if any) for this object. Will be set |
||
1615 | * as needed when mapped into the GTT. |
||
1616 | * Protected by dev->struct_mutex. |
||
1617 | */ |
||
2342 | Serge | 1618 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
2327 | Serge | 1619 | |
1620 | /** |
||
1621 | * Advice: are the backing pages purgeable? |
||
1622 | */ |
||
2342 | Serge | 1623 | unsigned int madv:2; |
2327 | Serge | 1624 | |
1625 | /** |
||
1626 | * Current tiling mode for the object. |
||
1627 | */ |
||
2342 | Serge | 1628 | unsigned int tiling_mode:2; |
3031 | serge | 1629 | /** |
1630 | * Whether the tiling parameters for the currently associated fence |
||
1631 | * register have changed. Note that for the purposes of tracking |
||
1632 | * tiling changes we also treat the unfenced register, the register |
||
1633 | * slot that the object occupies whilst it executes a fenced |
||
1634 | * command (such as BLT on gen2/3), as a "fence". |
||
1635 | */ |
||
1636 | unsigned int fence_dirty:1; |
||
2327 | Serge | 1637 | |
1638 | /** How many users have pinned this object in GTT space. The following |
||
1639 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
||
1640 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
||
1641 | * times for the same batchbuffer), and the framebuffer code. When |
||
1642 | * switching/pageflipping, the framebuffer code has at most two buffers |
||
1643 | * pinned per crtc. |
||
1644 | * |
||
1645 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
||
1646 | * bits with absolutely no headroom. So use 4 bits. */ |
||
2342 | Serge | 1647 | unsigned int pin_count:4; |
2327 | Serge | 1648 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
1649 | |||
1650 | /** |
||
1651 | * Is the object at the current location in the gtt mappable and |
||
1652 | * fenceable? Used to avoid costly recalculations. |
||
1653 | */ |
||
2342 | Serge | 1654 | unsigned int map_and_fenceable:1; |
2327 | Serge | 1655 | |
1656 | /** |
||
1657 | * Whether the current gtt mapping needs to be mappable (and isn't just |
||
1658 | * mappable by accident). Track pin and fault separate for a more |
||
1659 | * accurate mappable working set. |
||
1660 | */ |
||
2342 | Serge | 1661 | unsigned int fault_mappable:1; |
1662 | unsigned int pin_mappable:1; |
||
4104 | Serge | 1663 | unsigned int pin_display:1; |
2327 | Serge | 1664 | |
1665 | /* |
||
1666 | * Is the GPU currently using a fence to access this buffer, |
||
1667 | */ |
||
1668 | unsigned int pending_fenced_gpu_access:1; |
||
1669 | unsigned int fenced_gpu_access:1; |
||
1670 | |||
4104 | Serge | 1671 | unsigned int cache_level:3; |
2327 | Serge | 1672 | |
3031 | serge | 1673 | unsigned int has_aliasing_ppgtt_mapping:1; |
1674 | unsigned int has_global_gtt_mapping:1; |
||
1675 | unsigned int has_dma_mapping:1; |
||
2327 | Serge | 1676 | |
3243 | Serge | 1677 | struct sg_table *pages; |
3031 | serge | 1678 | int pages_pin_count; |
2327 | Serge | 1679 | |
3031 | serge | 1680 | /* prime dma-buf support */ |
1681 | void *dma_buf_vmapping; |
||
1682 | int vmapping_count; |
||
1683 | |||
1684 | struct intel_ring_buffer *ring; |
||
1685 | |||
2327 | Serge | 1686 | /** Breadcrumb of last rendering to the buffer. */ |
3031 | serge | 1687 | uint32_t last_read_seqno; |
1688 | uint32_t last_write_seqno; |
||
2327 | Serge | 1689 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1690 | uint32_t last_fenced_seqno; |
||
1691 | |||
1692 | /** Current tiling stride for the object, if it's tiled. */ |
||
1693 | uint32_t stride; |
||
1694 | |||
4560 | Serge | 1695 | /** References from framebuffers, locks out tiling changes. */ |
1696 | unsigned long framebuffer_references; |
||
1697 | |||
2327 | Serge | 1698 | /** Record of address bit 17 of each page at last unbind. */ |
1699 | unsigned long *bit_17; |
||
1700 | |||
1701 | /** User space pin count and filp owning the pin */ |
||
4560 | Serge | 1702 | unsigned long user_pin_count; |
2327 | Serge | 1703 | struct drm_file *pin_filp; |
1704 | |||
1705 | /** for phy allocated objects */ |
||
1706 | struct drm_i915_gem_phys_object *phys_obj; |
||
1707 | }; |
||
3243 | Serge | 1708 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
2327 | Serge | 1709 | |
2325 | Serge | 1710 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
1711 | |||
1712 | /** |
||
1713 | * Request queue structure. |
||
1714 | * |
||
1715 | * The request queue allows us to note sequence numbers that have been emitted |
||
1716 | * and may be associated with active buffers to be retired. |
||
1717 | * |
||
1718 | * By keeping this list, we can avoid having to do questionable |
||
1719 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
||
1720 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
||
1721 | */ |
||
1722 | struct drm_i915_gem_request { |
||
1723 | /** On Which ring this request was generated */ |
||
1724 | struct intel_ring_buffer *ring; |
||
1725 | |||
1726 | /** GEM sequence number associated with this request. */ |
||
1727 | uint32_t seqno; |
||
1728 | |||
4104 | Serge | 1729 | /** Position in the ringbuffer of the start of the request */ |
1730 | u32 head; |
||
1731 | |||
1732 | /** Position in the ringbuffer of the end of the request */ |
||
3031 | serge | 1733 | u32 tail; |
1734 | |||
4104 | Serge | 1735 | /** Context related to this request */ |
1736 | struct i915_hw_context *ctx; |
||
1737 | |||
1738 | /** Batch buffer related to this request if any */ |
||
1739 | struct drm_i915_gem_object *batch_obj; |
||
1740 | |||
2325 | Serge | 1741 | /** Time at which this request was emitted, in jiffies. */ |
1742 | unsigned long emitted_jiffies; |
||
1743 | |||
1744 | /** global list entry for this request */ |
||
1745 | struct list_head list; |
||
1746 | |||
1747 | struct drm_i915_file_private *file_priv; |
||
1748 | /** file_priv list entry for this request */ |
||
1749 | struct list_head client_list; |
||
1750 | }; |
||
1751 | |||
1752 | struct drm_i915_file_private { |
||
4560 | Serge | 1753 | struct drm_i915_private *dev_priv; |
1754 | |||
2325 | Serge | 1755 | struct { |
3480 | Serge | 1756 | spinlock_t lock; |
2325 | Serge | 1757 | struct list_head request_list; |
4560 | Serge | 1758 | struct delayed_work idle_work; |
2325 | Serge | 1759 | } mm; |
3031 | serge | 1760 | struct idr context_idr; |
4104 | Serge | 1761 | |
1762 | struct i915_ctx_hang_stats hang_stats; |
||
4560 | Serge | 1763 | atomic_t rps_wait_boost; |
2325 | Serge | 1764 | }; |
1765 | |||
4104 | Serge | 1766 | #define INTEL_INFO(dev) (to_i915(dev)->info) |
2325 | Serge | 1767 | |
4560 | Serge | 1768 | #define IS_I830(dev) ((dev)->pdev->device == 0x3577) |
1769 | #define IS_845G(dev) ((dev)->pdev->device == 0x2562) |
||
2325 | Serge | 1770 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
4560 | Serge | 1771 | #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) |
2325 | Serge | 1772 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
4560 | Serge | 1773 | #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) |
1774 | #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) |
||
2325 | Serge | 1775 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
1776 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
||
1777 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
||
4560 | Serge | 1778 | #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) |
2325 | Serge | 1779 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
4560 | Serge | 1780 | #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) |
1781 | #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) |
||
2325 | Serge | 1782 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
1783 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
||
4560 | Serge | 1784 | #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) |
2325 | Serge | 1785 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
4560 | Serge | 1786 | #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ |
1787 | (dev)->pdev->device == 0x0152 || \ |
||
1788 | (dev)->pdev->device == 0x015a) |
||
1789 | #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ |
||
1790 | (dev)->pdev->device == 0x0106 || \ |
||
1791 | (dev)->pdev->device == 0x010A) |
||
3031 | serge | 1792 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
1793 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
||
4560 | Serge | 1794 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) |
2325 | Serge | 1795 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
4104 | Serge | 1796 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
4560 | Serge | 1797 | ((dev)->pdev->device & 0xFF00) == 0x0C00) |
1798 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
||
1799 | (((dev)->pdev->device & 0xf) == 0x2 || \ |
||
1800 | ((dev)->pdev->device & 0xf) == 0x6 || \ |
||
1801 | ((dev)->pdev->device & 0xf) == 0xe)) |
||
1802 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
||
1803 | ((dev)->pdev->device & 0xFF00) == 0x0A00) |
||
1804 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
||
1805 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
||
1806 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
||
1807 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
||
2325 | Serge | 1808 | |
1809 | /* |
||
1810 | * The genX designation typically refers to the render engine, so render |
||
1811 | * capability related checks should use IS_GEN, while display and other checks |
||
1812 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
||
1813 | * chips, etc.). |
||
1814 | */ |
||
1815 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
||
1816 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
||
1817 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
||
1818 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
||
1819 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
||
1820 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
||
4560 | Serge | 1821 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
2325 | Serge | 1822 | |
4560 | Serge | 1823 | #define RENDER_RING (1< |
1824 | #define BSD_RING (1< |
||
1825 | #define BLT_RING (1< |
||
1826 | #define VEBOX_RING (1< |
||
1827 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
||
1828 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
||
1829 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) |
||
3031 | serge | 1830 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
4104 | Serge | 1831 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
2325 | Serge | 1832 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1833 | |||
3031 | serge | 1834 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
1835 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
||
1836 | |||
2325 | Serge | 1837 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
1838 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
||
1839 | |||
3243 | Serge | 1840 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1841 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
||
1842 | |||
2325 | Serge | 1843 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1844 | * rows, which changed the alignment requirements and fence programming. |
||
1845 | */ |
||
1846 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
||
1847 | IS_I915GM(dev))) |
||
1848 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
||
1849 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
||
1850 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
||
1851 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
||
1852 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
||
1853 | |||
1854 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
||
1855 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
||
4560 | Serge | 1856 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
2325 | Serge | 1857 | |
4560 | Serge | 1858 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
2325 | Serge | 1859 | |
4104 | Serge | 1860 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
1861 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
||
4560 | Serge | 1862 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1863 | #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */ |
||
1864 | #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev)) |
||
3480 | Serge | 1865 | |
3243 | Serge | 1866 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1867 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
||
1868 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
||
1869 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
||
1870 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
||
1871 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
||
1872 | |||
4104 | Serge | 1873 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
3031 | serge | 1874 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
2325 | Serge | 1875 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1876 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
||
3746 | Serge | 1877 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
3031 | serge | 1878 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
2325 | Serge | 1879 | |
4560 | Serge | 1880 | /* DPF == dynamic parity feature */ |
1881 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
||
1882 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) |
||
2325 | Serge | 1883 | |
3031 | serge | 1884 | #define GT_FREQUENCY_MULTIPLIER 50 |
1885 | |||
1886 | #include "i915_trace.h" |
||
1887 | |||
1888 | extern unsigned int i915_fbpercrtc __always_unused; |
||
1889 | extern int i915_panel_ignore_lid __read_mostly; |
||
1890 | extern unsigned int i915_powersave __read_mostly; |
||
1891 | extern int i915_semaphores __read_mostly; |
||
1892 | extern unsigned int i915_lvds_downclock __read_mostly; |
||
1893 | extern int i915_lvds_channel_mode __read_mostly; |
||
1894 | extern int i915_panel_use_ssc __read_mostly; |
||
1895 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
||
1896 | extern int i915_enable_rc6 __read_mostly; |
||
1897 | extern int i915_enable_fbc __read_mostly; |
||
1898 | extern bool i915_enable_hangcheck __read_mostly; |
||
1899 | extern int i915_enable_ppgtt __read_mostly; |
||
4104 | Serge | 1900 | extern int i915_enable_psr __read_mostly; |
3031 | serge | 1901 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
3480 | Serge | 1902 | extern int i915_disable_power_well __read_mostly; |
4104 | Serge | 1903 | extern int i915_enable_ips __read_mostly; |
1904 | extern bool i915_fastboot __read_mostly; |
||
1905 | extern int i915_enable_pc8 __read_mostly; |
||
1906 | extern int i915_pc8_timeout __read_mostly; |
||
1907 | extern bool i915_prefault_disable __read_mostly; |
||
3031 | serge | 1908 | |
2325 | Serge | 1909 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1910 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
||
1911 | |||
1912 | /* i915_dma.c */ |
||
3031 | serge | 1913 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
2325 | Serge | 1914 | extern void i915_kernel_lost_context(struct drm_device * dev); |
1915 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
||
1916 | extern int i915_driver_unload(struct drm_device *); |
||
1917 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
||
1918 | extern void i915_driver_lastclose(struct drm_device * dev); |
||
1919 | extern void i915_driver_preclose(struct drm_device *dev, |
||
1920 | struct drm_file *file_priv); |
||
1921 | extern void i915_driver_postclose(struct drm_device *dev, |
||
1922 | struct drm_file *file_priv); |
||
1923 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
||
3031 | serge | 1924 | #ifdef CONFIG_COMPAT |
2325 | Serge | 1925 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1926 | unsigned long arg); |
||
3031 | serge | 1927 | #endif |
2325 | Serge | 1928 | extern int i915_emit_box(struct drm_device *dev, |
1929 | struct drm_clip_rect *box, |
||
1930 | int DR1, int DR4); |
||
3031 | serge | 1931 | extern int intel_gpu_reset(struct drm_device *dev); |
1932 | extern int i915_reset(struct drm_device *dev); |
||
2325 | Serge | 1933 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1934 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
||
1935 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
||
1936 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
||
1937 | |||
4104 | Serge | 1938 | extern void intel_console_resume(struct work_struct *work); |
2325 | Serge | 1939 | |
1940 | /* i915_irq.c */ |
||
4104 | Serge | 1941 | void i915_queue_hangcheck(struct drm_device *dev); |
2325 | Serge | 1942 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1943 | |||
1944 | extern void intel_irq_init(struct drm_device *dev); |
||
3480 | Serge | 1945 | extern void intel_hpd_init(struct drm_device *dev); |
2325 | Serge | 1946 | |
4104 | Serge | 1947 | extern void intel_uncore_sanitize(struct drm_device *dev); |
1948 | extern void intel_uncore_early_sanitize(struct drm_device *dev); |
||
1949 | extern void intel_uncore_init(struct drm_device *dev); |
||
1950 | extern void intel_uncore_check_errors(struct drm_device *dev); |
||
4560 | Serge | 1951 | extern void intel_uncore_fini(struct drm_device *dev); |
2325 | Serge | 1952 | |
1953 | void |
||
4560 | Serge | 1954 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
2325 | Serge | 1955 | |
1956 | void |
||
4560 | Serge | 1957 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
2325 | Serge | 1958 | |
1959 | /* i915_gem.c */ |
||
1960 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
||
1961 | struct drm_file *file_priv); |
||
1962 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
||
1963 | struct drm_file *file_priv); |
||
1964 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
||
1965 | struct drm_file *file_priv); |
||
1966 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
||
1967 | struct drm_file *file_priv); |
||
1968 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
||
1969 | struct drm_file *file_priv); |
||
1970 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
||
1971 | struct drm_file *file_priv); |
||
1972 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
||
1973 | struct drm_file *file_priv); |
||
1974 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
||
1975 | struct drm_file *file_priv); |
||
1976 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
||
1977 | struct drm_file *file_priv); |
||
1978 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
||
1979 | struct drm_file *file_priv); |
||
1980 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
||
1981 | struct drm_file *file_priv); |
||
1982 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
||
1983 | struct drm_file *file_priv); |
||
1984 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
||
1985 | struct drm_file *file_priv); |
||
3031 | serge | 1986 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1987 | struct drm_file *file); |
||
1988 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
||
1989 | struct drm_file *file); |
||
2325 | Serge | 1990 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1991 | struct drm_file *file_priv); |
||
1992 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
||
1993 | struct drm_file *file_priv); |
||
1994 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
||
1995 | struct drm_file *file_priv); |
||
1996 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
||
1997 | struct drm_file *file_priv); |
||
1998 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
||
1999 | struct drm_file *file_priv); |
||
2000 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
||
2001 | struct drm_file *file_priv); |
||
2002 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
||
2003 | struct drm_file *file_priv); |
||
3031 | serge | 2004 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2005 | struct drm_file *file_priv); |
||
2325 | Serge | 2006 | void i915_gem_load(struct drm_device *dev); |
3480 | Serge | 2007 | void *i915_gem_object_alloc(struct drm_device *dev); |
2008 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
||
3031 | serge | 2009 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2010 | const struct drm_i915_gem_object_ops *ops); |
||
2325 | Serge | 2011 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2012 | size_t size); |
||
2013 | void i915_gem_free_object(struct drm_gem_object *obj); |
||
4104 | Serge | 2014 | void i915_gem_vma_destroy(struct i915_vma *vma); |
3480 | Serge | 2015 | |
2325 | Serge | 2016 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
4104 | Serge | 2017 | struct i915_address_space *vm, |
2325 | Serge | 2018 | uint32_t alignment, |
3031 | serge | 2019 | bool map_and_fenceable, |
2020 | bool nonblocking); |
||
2325 | Serge | 2021 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
4104 | Serge | 2022 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
2023 | int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); |
||
3480 | Serge | 2024 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
4560 | Serge | 2025 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
2325 | Serge | 2026 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
2027 | void i915_gem_lastclose(struct drm_device *dev); |
||
2028 | |||
3031 | serge | 2029 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
3243 | Serge | 2030 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
3031 | serge | 2031 | { |
3746 | Serge | 2032 | struct sg_page_iter sg_iter; |
3031 | serge | 2033 | |
3746 | Serge | 2034 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
2035 | return sg_page_iter_page(&sg_iter); |
||
2036 | |||
2037 | return NULL; |
||
3243 | Serge | 2038 | } |
3031 | serge | 2039 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2040 | { |
||
3243 | Serge | 2041 | BUG_ON(obj->pages == NULL); |
3031 | serge | 2042 | obj->pages_pin_count++; |
2043 | } |
||
2044 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
||
2045 | { |
||
2046 | BUG_ON(obj->pages_pin_count == 0); |
||
2047 | obj->pages_pin_count--; |
||
2048 | } |
||
2049 | |||
2325 | Serge | 2050 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
3031 | serge | 2051 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2052 | struct intel_ring_buffer *to); |
||
4560 | Serge | 2053 | void i915_vma_move_to_active(struct i915_vma *vma, |
3243 | Serge | 2054 | struct intel_ring_buffer *ring); |
2325 | Serge | 2055 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2056 | struct drm_device *dev, |
||
2057 | struct drm_mode_create_dumb *args); |
||
2058 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
||
2059 | uint32_t handle, uint64_t *offset); |
||
2060 | /** |
||
2061 | * Returns true if seq1 is later than seq2. |
||
2062 | */ |
||
2340 | Serge | 2063 | static inline bool |
2064 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
||
2065 | { |
||
2066 | return (int32_t)(seq1 - seq2) >= 0; |
||
2067 | } |
||
2325 | Serge | 2068 | |
3480 | Serge | 2069 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2070 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
||
3031 | serge | 2071 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
2072 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
||
2073 | |||
2074 | static inline bool |
||
2075 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
||
2332 | Serge | 2076 | { |
3031 | serge | 2077 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2078 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
2079 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
||
2080 | return true; |
||
2081 | } else |
||
2082 | return false; |
||
2332 | Serge | 2083 | } |
2325 | Serge | 2084 | |
3031 | serge | 2085 | static inline void |
2086 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
||
2087 | { |
||
2088 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
||
2089 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
4104 | Serge | 2090 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
3031 | serge | 2091 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
2092 | } |
||
2093 | } |
||
2332 | Serge | 2094 | |
4560 | Serge | 2095 | bool i915_gem_retire_requests(struct drm_device *dev); |
3031 | serge | 2096 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
3480 | Serge | 2097 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
3031 | serge | 2098 | bool interruptible); |
3480 | Serge | 2099 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2100 | { |
||
2101 | return unlikely(atomic_read(&error->reset_counter) |
||
4560 | Serge | 2102 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
3480 | Serge | 2103 | } |
3031 | serge | 2104 | |
3480 | Serge | 2105 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
2106 | { |
||
4560 | Serge | 2107 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
3480 | Serge | 2108 | } |
2109 | |||
4560 | Serge | 2110 | static inline u32 i915_reset_count(struct i915_gpu_error *error) |
2111 | { |
||
2112 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; |
||
2113 | } |
||
2114 | |||
2325 | Serge | 2115 | void i915_gem_reset(struct drm_device *dev); |
4104 | Serge | 2116 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
2325 | Serge | 2117 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
3031 | serge | 2118 | int __must_check i915_gem_init(struct drm_device *dev); |
2119 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
||
4560 | Serge | 2120 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); |
3031 | serge | 2121 | void i915_gem_init_swizzling(struct drm_device *dev); |
2325 | Serge | 2122 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
2123 | int __must_check i915_gpu_idle(struct drm_device *dev); |
||
4560 | Serge | 2124 | int __must_check i915_gem_suspend(struct drm_device *dev); |
4104 | Serge | 2125 | int __i915_add_request(struct intel_ring_buffer *ring, |
2325 | Serge | 2126 | struct drm_file *file, |
4104 | Serge | 2127 | struct drm_i915_gem_object *batch_obj, |
3031 | serge | 2128 | u32 *seqno); |
4104 | Serge | 2129 | #define i915_add_request(ring, seqno) \ |
2130 | __i915_add_request(ring, NULL, NULL, seqno) |
||
3031 | serge | 2131 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
2325 | Serge | 2132 | uint32_t seqno); |
2133 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
||
2134 | int __must_check |
||
2135 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
||
2136 | bool write); |
||
2137 | int __must_check |
||
3031 | serge | 2138 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2139 | int __must_check |
||
2325 | Serge | 2140 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2141 | u32 alignment, |
||
2142 | struct intel_ring_buffer *pipelined); |
||
4104 | Serge | 2143 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
2325 | Serge | 2144 | int i915_gem_attach_phys_object(struct drm_device *dev, |
2145 | struct drm_i915_gem_object *obj, |
||
2146 | int id, |
||
2147 | int align); |
||
2148 | void i915_gem_detach_phys_object(struct drm_device *dev, |
||
2149 | struct drm_i915_gem_object *obj); |
||
2150 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
||
4560 | Serge | 2151 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
2325 | Serge | 2152 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
2153 | |||
2154 | uint32_t |
||
3480 | Serge | 2155 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
2156 | uint32_t |
||
2157 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
||
2158 | int tiling_mode, bool fenced); |
||
2325 | Serge | 2159 | |
2160 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
||
2161 | enum i915_cache_level cache_level); |
||
2162 | |||
4104 | Serge | 2163 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2164 | struct dma_buf *dma_buf); |
||
3031 | serge | 2165 | |
2166 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
||
2167 | struct drm_gem_object *gem_obj, int flags); |
||
2168 | |||
3746 | Serge | 2169 | void i915_gem_restore_fences(struct drm_device *dev); |
2170 | |||
4104 | Serge | 2171 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
2172 | struct i915_address_space *vm); |
||
2173 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
||
2174 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
||
2175 | struct i915_address_space *vm); |
||
2176 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
||
2177 | struct i915_address_space *vm); |
||
2178 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
||
2179 | struct i915_address_space *vm); |
||
2180 | struct i915_vma * |
||
2181 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
||
2182 | struct i915_address_space *vm); |
||
4560 | Serge | 2183 | |
2184 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); |
||
2185 | |||
4104 | Serge | 2186 | /* Some GGTT VM helpers */ |
2187 | #define obj_to_ggtt(obj) \ |
||
2188 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
||
2189 | static inline bool i915_is_ggtt(struct i915_address_space *vm) |
||
2190 | { |
||
2191 | struct i915_address_space *ggtt = |
||
2192 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; |
||
2193 | return vm == ggtt; |
||
2194 | } |
||
2195 | |||
2196 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
||
2197 | { |
||
2198 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); |
||
2199 | } |
||
2200 | |||
2201 | static inline unsigned long |
||
2202 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) |
||
2203 | { |
||
2204 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); |
||
2205 | } |
||
2206 | |||
2207 | static inline unsigned long |
||
2208 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) |
||
2209 | { |
||
2210 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); |
||
2211 | } |
||
2212 | |||
2213 | static inline int __must_check |
||
2214 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, |
||
2215 | uint32_t alignment, |
||
2216 | bool map_and_fenceable, |
||
2217 | bool nonblocking) |
||
2218 | { |
||
2219 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, |
||
2220 | map_and_fenceable, nonblocking); |
||
2221 | } |
||
2222 | |||
3031 | serge | 2223 | /* i915_gem_context.c */ |
4560 | Serge | 2224 | int __must_check i915_gem_context_init(struct drm_device *dev); |
3031 | serge | 2225 | void i915_gem_context_fini(struct drm_device *dev); |
2226 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
||
2227 | int i915_switch_context(struct intel_ring_buffer *ring, |
||
2228 | struct drm_file *file, int to_id); |
||
4104 | Serge | 2229 | void i915_gem_context_free(struct kref *ctx_ref); |
2230 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) |
||
2231 | { |
||
2232 | kref_get(&ctx->ref); |
||
2233 | } |
||
2234 | |||
2235 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) |
||
2236 | { |
||
2237 | kref_put(&ctx->ref, i915_gem_context_free); |
||
2238 | } |
||
2239 | |||
2240 | struct i915_ctx_hang_stats * __must_check |
||
2241 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
||
2242 | struct drm_file *file, |
||
2243 | u32 id); |
||
3031 | serge | 2244 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2245 | struct drm_file *file); |
||
2246 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
||
2247 | struct drm_file *file); |
||
2248 | |||
2325 | Serge | 2249 | /* i915_gem_gtt.c */ |
3031 | serge | 2250 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
2251 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
||
2252 | struct drm_i915_gem_object *obj, |
||
2253 | enum i915_cache_level cache_level); |
||
2254 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, |
||
2255 | struct drm_i915_gem_object *obj); |
||
2256 | |||
4280 | Serge | 2257 | void i915_check_and_clear_faults(struct drm_device *dev); |
2258 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); |
||
2325 | Serge | 2259 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
3031 | serge | 2260 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
2261 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
||
2325 | Serge | 2262 | enum i915_cache_level cache_level); |
2263 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
||
3031 | serge | 2264 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
3480 | Serge | 2265 | void i915_gem_init_global_gtt(struct drm_device *dev); |
2266 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, |
||
2267 | unsigned long mappable_end, unsigned long end); |
||
3243 | Serge | 2268 | int i915_gem_gtt_init(struct drm_device *dev); |
2269 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
||
2270 | { |
||
2271 | if (INTEL_INFO(dev)->gen < 6) |
||
2272 | intel_gtt_chipset_flush(); |
||
2273 | } |
||
2325 | Serge | 2274 | |
3243 | Serge | 2275 | |
2325 | Serge | 2276 | /* i915_gem_evict.c */ |
4104 | Serge | 2277 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
2278 | struct i915_address_space *vm, |
||
2279 | int min_size, |
||
3031 | serge | 2280 | unsigned alignment, |
2281 | unsigned cache_level, |
||
2282 | bool mappable, |
||
2283 | bool nonblock); |
||
4560 | Serge | 2284 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
3031 | serge | 2285 | int i915_gem_evict_everything(struct drm_device *dev); |
2325 | Serge | 2286 | |
3031 | serge | 2287 | /* i915_gem_stolen.c */ |
2288 | int i915_gem_init_stolen(struct drm_device *dev); |
||
3480 | Serge | 2289 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
2290 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
||
3031 | serge | 2291 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
3480 | Serge | 2292 | struct drm_i915_gem_object * |
2293 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
||
3746 | Serge | 2294 | struct drm_i915_gem_object * |
2295 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
||
2296 | u32 stolen_offset, |
||
2297 | u32 gtt_offset, |
||
2298 | u32 size); |
||
3480 | Serge | 2299 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
3031 | serge | 2300 | |
2325 | Serge | 2301 | /* i915_gem_tiling.c */ |
4104 | Serge | 2302 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
3480 | Serge | 2303 | { |
2304 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
||
2305 | |||
2306 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
||
2307 | obj->tiling_mode != I915_TILING_NONE; |
||
2308 | } |
||
2309 | |||
2325 | Serge | 2310 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
2311 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
||
2312 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
||
2313 | |||
2314 | /* i915_gem_debug.c */ |
||
2315 | #if WATCH_LISTS |
||
2316 | int i915_verify_lists(struct drm_device *dev); |
||
2317 | #else |
||
2318 | #define i915_verify_lists(dev) 0 |
||
2319 | #endif |
||
2320 | |||
2321 | /* i915_debugfs.c */ |
||
2322 | int i915_debugfs_init(struct drm_minor *minor); |
||
2323 | void i915_debugfs_cleanup(struct drm_minor *minor); |
||
4560 | Serge | 2324 | #ifdef CONFIG_DEBUG_FS |
2325 | void intel_display_crc_init(struct drm_device *dev); |
||
2326 | #else |
||
2327 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
||
2328 | #endif |
||
2325 | Serge | 2329 | |
4104 | Serge | 2330 | /* i915_gpu_error.c */ |
2331 | __printf(2, 3) |
||
2332 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
||
2333 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
||
2334 | const struct i915_error_state_file_priv *error); |
||
2335 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
||
2336 | size_t count, loff_t pos); |
||
2337 | static inline void i915_error_state_buf_release( |
||
2338 | struct drm_i915_error_state_buf *eb) |
||
2339 | { |
||
2340 | kfree(eb->buf); |
||
2341 | } |
||
2342 | void i915_capture_error_state(struct drm_device *dev); |
||
2343 | void i915_error_state_get(struct drm_device *dev, |
||
2344 | struct i915_error_state_file_priv *error_priv); |
||
2345 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); |
||
2346 | void i915_destroy_error_state(struct drm_device *dev); |
||
2347 | |||
2348 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); |
||
2349 | const char *i915_cache_level_str(int type); |
||
2350 | |||
2325 | Serge | 2351 | /* i915_suspend.c */ |
2352 | extern int i915_save_state(struct drm_device *dev); |
||
2353 | extern int i915_restore_state(struct drm_device *dev); |
||
2354 | |||
3480 | Serge | 2355 | /* i915_ums.c */ |
2356 | void i915_save_display_reg(struct drm_device *dev); |
||
2357 | void i915_restore_display_reg(struct drm_device *dev); |
||
2325 | Serge | 2358 | |
3031 | serge | 2359 | /* i915_sysfs.c */ |
2360 | void i915_setup_sysfs(struct drm_device *dev_priv); |
||
2361 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
||
2362 | |||
2325 | Serge | 2363 | /* intel_i2c.c */ |
2364 | extern int intel_setup_gmbus(struct drm_device *dev); |
||
2365 | extern void intel_teardown_gmbus(struct drm_device *dev); |
||
4104 | Serge | 2366 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3031 | serge | 2367 | { |
2368 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
||
2369 | } |
||
2370 | |||
2371 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
||
2372 | struct drm_i915_private *dev_priv, unsigned port); |
||
2325 | Serge | 2373 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2374 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
||
4104 | Serge | 2375 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
2342 | Serge | 2376 | { |
2377 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
||
2378 | } |
||
2325 | Serge | 2379 | extern void intel_i2c_reset(struct drm_device *dev); |
2380 | |||
2381 | /* intel_opregion.c */ |
||
4560 | Serge | 2382 | struct intel_encoder; |
2383 | #ifdef CONFIG_ACPI |
||
2325 | Serge | 2384 | extern int intel_opregion_setup(struct drm_device *dev); |
2385 | extern void intel_opregion_init(struct drm_device *dev); |
||
2386 | extern void intel_opregion_fini(struct drm_device *dev); |
||
2387 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
||
4560 | Serge | 2388 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
2389 | bool enable); |
||
2390 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
||
2391 | pci_power_t state); |
||
2325 | Serge | 2392 | #else |
4560 | Serge | 2393 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
2325 | Serge | 2394 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
2395 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
||
2396 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
||
4560 | Serge | 2397 | static inline int |
2398 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) |
||
2399 | { |
||
2400 | return 0; |
||
2401 | } |
||
2402 | static inline int |
||
2403 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) |
||
2404 | { |
||
2405 | return 0; |
||
2406 | } |
||
2325 | Serge | 2407 | #endif |
2408 | |||
2409 | /* intel_acpi.c */ |
||
2410 | #ifdef CONFIG_ACPI |
||
2411 | extern void intel_register_dsm_handler(void); |
||
2412 | extern void intel_unregister_dsm_handler(void); |
||
2413 | #else |
||
2414 | static inline void intel_register_dsm_handler(void) { return; } |
||
2415 | static inline void intel_unregister_dsm_handler(void) { return; } |
||
2416 | #endif /* CONFIG_ACPI */ |
||
2417 | |||
2418 | /* modesetting */ |
||
3031 | serge | 2419 | extern void intel_modeset_init_hw(struct drm_device *dev); |
4104 | Serge | 2420 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
2325 | Serge | 2421 | extern void intel_modeset_init(struct drm_device *dev); |
2422 | extern void intel_modeset_gem_init(struct drm_device *dev); |
||
2423 | extern void intel_modeset_cleanup(struct drm_device *dev); |
||
2424 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
||
3243 | Serge | 2425 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2426 | bool force_restore); |
||
3480 | Serge | 2427 | extern void i915_redisable_vga(struct drm_device *dev); |
2325 | Serge | 2428 | extern bool intel_fbc_enabled(struct drm_device *dev); |
2429 | extern void intel_disable_fbc(struct drm_device *dev); |
||
2430 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
||
3243 | Serge | 2431 | extern void intel_init_pch_refclk(struct drm_device *dev); |
2325 | Serge | 2432 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
4104 | Serge | 2433 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
2434 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); |
||
2435 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); |
||
2342 | Serge | 2436 | extern void intel_detect_pch(struct drm_device *dev); |
2437 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
||
3031 | serge | 2438 | extern int intel_enable_rc6(const struct drm_device *dev); |
2325 | Serge | 2439 | |
3031 | serge | 2440 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
2441 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
||
2442 | struct drm_file *file); |
||
4560 | Serge | 2443 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
2444 | struct drm_file *file); |
||
2342 | Serge | 2445 | |
2325 | Serge | 2446 | /* overlay */ |
2447 | #ifdef CONFIG_DEBUG_FS |
||
2448 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
||
4104 | Serge | 2449 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2450 | struct intel_overlay_error_state *error); |
||
2325 | Serge | 2451 | |
2452 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
||
4104 | Serge | 2453 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
2325 | Serge | 2454 | struct drm_device *dev, |
2455 | struct intel_display_error_state *error); |
||
2456 | #endif |
||
2457 | |||
2458 | /* On SNB platform, before reading ring registers forcewake bit |
||
2459 | * must be set to prevent GT core from power down and stale values being |
||
2460 | * returned. |
||
2461 | */ |
||
4560 | Serge | 2462 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
2463 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); |
||
2325 | Serge | 2464 | |
3243 | Serge | 2465 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
2466 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
||
2467 | |||
4104 | Serge | 2468 | /* intel_sideband.c */ |
2469 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
||
2470 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
||
2471 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
||
4560 | Serge | 2472 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
2473 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
||
2474 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
||
2475 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
||
2476 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); |
||
2477 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
||
2478 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
||
2479 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
||
2480 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
||
2481 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
||
2482 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
||
2483 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); |
||
4104 | Serge | 2484 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
2485 | enum intel_sbi_destination destination); |
||
2486 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
||
2487 | enum intel_sbi_destination destination); |
||
4560 | Serge | 2488 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
2489 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
||
2325 | Serge | 2490 | |
4560 | Serge | 2491 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); |
2492 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); |
||
4104 | Serge | 2493 | |
4560 | Serge | 2494 | void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
2495 | void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); |
||
2325 | Serge | 2496 | |
4560 | Serge | 2497 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
2498 | (((reg) >= 0x2000 && (reg) < 0x4000) ||\ |
||
2499 | ((reg) >= 0x5000 && (reg) < 0x8000) ||\ |
||
2500 | ((reg) >= 0xB000 && (reg) < 0x12000) ||\ |
||
2501 | ((reg) >= 0x2E000 && (reg) < 0x30000)) |
||
2325 | Serge | 2502 | |
4560 | Serge | 2503 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\ |
2504 | (((reg) >= 0x12000 && (reg) < 0x14000) ||\ |
||
2505 | ((reg) >= 0x22000 && (reg) < 0x24000) ||\ |
||
2506 | ((reg) >= 0x30000 && (reg) < 0x40000)) |
||
2325 | Serge | 2507 | |
4560 | Serge | 2508 | #define FORCEWAKE_RENDER (1 << 0) |
2509 | #define FORCEWAKE_MEDIA (1 << 1) |
||
2510 | #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) |
||
2325 | Serge | 2511 | |
2512 | |||
4560 | Serge | 2513 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
2514 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) |
||
2325 | Serge | 2515 | |
4560 | Serge | 2516 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) |
2517 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) |
||
2518 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) |
||
2519 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) |
||
2520 | |||
2521 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) |
||
2522 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) |
||
2523 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) |
||
2524 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) |
||
2525 | |||
2526 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
||
2527 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
||
2528 | |||
2325 | Serge | 2529 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
2530 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
||
2531 | |||
3480 | Serge | 2532 | /* "Broadcast RGB" property */ |
2533 | #define INTEL_BROADCAST_RGB_AUTO 0 |
||
2534 | #define INTEL_BROADCAST_RGB_FULL 1 |
||
2535 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
||
2536 | |||
2537 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
||
2538 | { |
||
2539 | if (HAS_PCH_SPLIT(dev)) |
||
2540 | return CPU_VGACNTRL; |
||
2541 | else if (IS_VALLEYVIEW(dev)) |
||
2542 | return VLV_VGACNTRL; |
||
2543 | else |
||
2544 | return VGACNTRL; |
||
2545 | } |
||
2546 | |||
3746 | Serge | 2547 | static inline void __user *to_user_ptr(u64 address) |
2548 | { |
||
2549 | return (void __user *)(uintptr_t)address; |
||
2550 | } |
||
2551 | |||
2552 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
||
2553 | { |
||
2554 | unsigned long j = msecs_to_jiffies(m); |
||
2555 | |||
2556 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
||
2557 | } |
||
2558 | |||
2559 | static inline unsigned long |
||
2560 | timespec_to_jiffies_timeout(const struct timespec *value) |
||
2561 | { |
||
2562 | unsigned long j = timespec_to_jiffies(value); |
||
2563 | |||
2564 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
||
2565 | } |
||
2566 | |||
4280 | Serge | 2567 | static inline int mutex_trylock(struct mutex *lock) |
2568 | { |
||
2569 | if (likely(atomic_cmpxchg(&lock->count, 1, 0) == 1)) |
||
2570 | return 1; |
||
2571 | return 0; |
||
2572 | } |
||
3746 | Serge | 2573 | |
2338 | Serge | 2574 | typedef struct |
2575 | { |
||
2576 | int width; |
||
2577 | int height; |
||
2578 | int bpp; |
||
2579 | int freq; |
||
2580 | }videomode_t; |
||
2325 | Serge | 2581 | |
4280 | Serge | 2582 | struct cmdtable |
2360 | Serge | 2583 | { |
4280 | Serge | 2584 | char *key; |
2585 | int size; |
||
2586 | int *val; |
||
2587 | }; |
||
2360 | Serge | 2588 | |
4280 | Serge | 2589 | #define CMDENTRY(key, val) {(key), (sizeof(key)-1), &val} |
2360 | Serge | 2590 | |
4280 | Serge | 2591 | void parse_cmdline(char *cmdline, struct cmdtable *table, char *log, videomode_t *mode); |
2592 | struct drm_i915_gem_object |
||
2593 | *kos_gem_fb_object_create(struct drm_device *dev, u32 gtt_offset, u32 size); |
||
2360 | Serge | 2594 | |
4560 | Serge | 2595 | extern struct drm_i915_gem_object *main_fb_obj; |
2596 | |||
4280 | Serge | 2597 | static struct drm_i915_gem_object *get_fb_obj() |
2598 | { |
||
4560 | Serge | 2599 | return main_fb_obj; |
4280 | Serge | 2600 | }; |
2360 | Serge | 2601 | |
4280 | Serge | 2602 | #define ioread32(addr) readl(addr) |
2360 | Serge | 2603 | |
2604 | |||
2325 | Serge | 2605 | #endif><>><>>>>>>>>=>>=> |