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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-

 */

/*

 *

 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation the rights to use, copy, modify, merge, publish,

 * distribute, sub license, and/or sell copies of the Software, and to

 * permit persons to whom the Software is furnished to do so, subject to

 * the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial portions

 * of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef _I915_DRV_H_

#define _I915_DRV_H_

#include 

#include "i915_reg.h"

#include "intel_bios.h"

#include "intel_ringbuffer.h"

#include 

//#include 

#include 

#include 

#include 

//#include 

#include 

#include 

/* General customization:

 */

#define I915_TILING_NONE          0

#define VGA_RSRC_NONE          0x00

#define VGA_RSRC_LEGACY_IO     0x01

#define VGA_RSRC_LEGACY_MEM    0x02

#define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)

/* Non-legacy access */

#define VGA_RSRC_NORMAL_IO     0x04

#define VGA_RSRC_NORMAL_MEM    0x08

#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."

#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20080730"

enum pipe {

	PIPE_A = 0,

	PIPE_B,

	PIPE_C,

	I915_MAX_PIPES

};

#define pipe_name(p) ((p) + 'A')

enum transcoder {

	TRANSCODER_A = 0,

	TRANSCODER_B,

	TRANSCODER_C,

	TRANSCODER_EDP = 0xF,

};

#define transcoder_name(t) ((t) + 'A')

enum plane {

	PLANE_A = 0,

	PLANE_B,

	PLANE_C,

};

#define plane_name(p) ((p) + 'A')

#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')

enum port {

	PORT_A = 0,

	PORT_B,

	PORT_C,

	PORT_D,

	PORT_E,

	I915_MAX_PORTS

};

#define port_name(p) ((p) + 'A')

enum intel_display_power_domain {

	POWER_DOMAIN_PIPE_A,

	POWER_DOMAIN_PIPE_B,

	POWER_DOMAIN_PIPE_C,

	POWER_DOMAIN_PIPE_A_PANEL_FITTER,

	POWER_DOMAIN_PIPE_B_PANEL_FITTER,

	POWER_DOMAIN_PIPE_C_PANEL_FITTER,

	POWER_DOMAIN_TRANSCODER_A,

	POWER_DOMAIN_TRANSCODER_B,

	POWER_DOMAIN_TRANSCODER_C,

	POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,

};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)

#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \

		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)

#define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)

enum hpd_pin {

	HPD_NONE = 0,

	HPD_PORT_A = HPD_NONE, /* PORT_A is internal */

	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */

	HPD_CRT,

	HPD_SDVO_B,

	HPD_SDVO_C,

	HPD_PORT_B,

	HPD_PORT_C,

	HPD_PORT_D,

	HPD_NUM_PINS

};

#define I915_GEM_GPU_DOMAINS \

	(I915_GEM_DOMAIN_RENDER | \

	 I915_GEM_DOMAIN_SAMPLER | \

	 I915_GEM_DOMAIN_COMMAND | \

	 I915_GEM_DOMAIN_INSTRUCTION | \

	 I915_GEM_DOMAIN_VERTEX)

#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)

#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \

	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \

		if ((intel_encoder)->base.crtc == (__crtc))

struct drm_i915_private;

enum intel_dpll_id {

	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */

	/* real shared dpll ids must be >= 0 */

	DPLL_ID_PCH_PLL_A,

	DPLL_ID_PCH_PLL_B,

};

#define I915_NUM_PLLS 2

struct intel_dpll_hw_state {

	uint32_t dpll;

	uint32_t dpll_md;

	uint32_t fp0;

	uint32_t fp1;

};

struct intel_shared_dpll {

	int refcount; /* count of number of CRTCs sharing this PLL */

	int active; /* count of number of active CRTCs (i.e. DPMS on) */

	bool on; /* is the PLL actually active? Disabled during modeset */

	const char *name;

	/* should match the index in the dev_priv->shared_dplls array */

	enum intel_dpll_id id;

	struct intel_dpll_hw_state hw_state;

	void (*mode_set)(struct drm_i915_private *dev_priv,

			 struct intel_shared_dpll *pll);

	void (*enable)(struct drm_i915_private *dev_priv,

		       struct intel_shared_dpll *pll);

	void (*disable)(struct drm_i915_private *dev_priv,

			struct intel_shared_dpll *pll);

	bool (*get_hw_state)(struct drm_i915_private *dev_priv,

			     struct intel_shared_dpll *pll,

			     struct intel_dpll_hw_state *hw_state);

};

/* Used by dp and fdi links */

struct intel_link_m_n {

	uint32_t	tu;

	uint32_t	gmch_m;

	uint32_t	gmch_n;

	uint32_t	link_m;

	uint32_t	link_n;

};

void intel_link_compute_m_n(int bpp, int nlanes,

			    int pixel_clock, int link_clock,

			    struct intel_link_m_n *m_n);

struct intel_ddi_plls {

	int spll_refcount;

	int wrpll1_refcount;

	int wrpll2_refcount;

};

/* Interface history:

 *

 * 1.1: Original.

 * 1.2: Add Power Management

 * 1.3: Add vblank support

 * 1.4: Fix cmdbuffer path, add heap destroy

 * 1.5: Add vblank pipe configuration

 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank

 *      - Support vertical blank on secondary display pipe

 */

#define DRIVER_MAJOR		1

#define DRIVER_MINOR		6

#define DRIVER_PATCHLEVEL	0

#define WATCH_LISTS	0

#define WATCH_GTT	0

#define I915_GEM_PHYS_CURSOR_0 1

#define I915_GEM_PHYS_CURSOR_1 2

#define I915_GEM_PHYS_OVERLAY_REGS 3

#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)

struct drm_i915_gem_phys_object {

	int id;

	struct page **page_list;

	drm_dma_handle_t *handle;

	struct drm_i915_gem_object *cur_obj;

};

struct opregion_header;

struct opregion_acpi;

struct opregion_swsci;

struct opregion_asle;

struct intel_opregion {

	struct opregion_header __iomem *header;

	struct opregion_acpi __iomem *acpi;

	struct opregion_swsci __iomem *swsci;

	struct opregion_asle __iomem *asle;

	void __iomem *vbt;

	u32 __iomem *lid_state;

};

#define OPREGION_SIZE            (8*1024)

struct intel_overlay;

struct intel_overlay_error_state;

struct drm_i915_master_private {

	drm_local_map_t *sarea;

	struct _drm_i915_sarea *sarea_priv;

};

#define I915_FENCE_REG_NONE -1

#define I915_MAX_NUM_FENCES 32

/* 32 fences + sign bit for FENCE_REG_NONE */

#define I915_MAX_NUM_FENCE_BITS 6

struct drm_i915_fence_reg {

	struct list_head lru_list;

	struct drm_i915_gem_object *obj;

	int pin_count;

};

struct sdvo_device_mapping {

	u8 initialized;

	u8 dvo_port;

	u8 slave_addr;

	u8 dvo_wiring;

	u8 i2c_pin;

	u8 ddc_pin;

};

struct intel_display_error_state;

struct drm_i915_error_state {

	struct kref ref;

	u32 eir;

	u32 pgtbl_er;

	u32 ier;

	u32 ccid;

	u32 derrmr;

	u32 forcewake;

	bool waiting[I915_NUM_RINGS];

	u32 pipestat[I915_MAX_PIPES];

	u32 tail[I915_NUM_RINGS];

	u32 head[I915_NUM_RINGS];

	u32 ctl[I915_NUM_RINGS];

	u32 ipeir[I915_NUM_RINGS];

	u32 ipehr[I915_NUM_RINGS];

	u32 instdone[I915_NUM_RINGS];

	u32 acthd[I915_NUM_RINGS];

	u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];

	u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];

	u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */

	/* our own tracking of ring head and tail */

	u32 cpu_ring_head[I915_NUM_RINGS];

	u32 cpu_ring_tail[I915_NUM_RINGS];

	u32 error; /* gen6+ */

	u32 err_int; /* gen7 */

	u32 instpm[I915_NUM_RINGS];

	u32 instps[I915_NUM_RINGS];

	u32 extra_instdone[I915_NUM_INSTDONE_REG];

	u32 seqno[I915_NUM_RINGS];

	u64 bbaddr;

	u32 fault_reg[I915_NUM_RINGS];

	u32 done_reg;

	u32 faddr[I915_NUM_RINGS];

	u64 fence[I915_MAX_NUM_FENCES];

	struct timeval time;

	struct drm_i915_error_ring {

	struct drm_i915_error_object {

		int page_count;

		u32 gtt_offset;

		u32 *pages[0];

		} *ringbuffer, *batchbuffer, *ctx;

		struct drm_i915_error_request {

			long jiffies;

			u32 seqno;

			u32 tail;

		} *requests;

		int num_requests;

	} ring[I915_NUM_RINGS];

	struct drm_i915_error_buffer {

		u32 size;

		u32 name;

		u32 rseqno, wseqno;

		u32 gtt_offset;

		u32 read_domains;

		u32 write_domain;

		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;

		s32 pinned:2;

		u32 tiling:2;

		u32 dirty:1;

		u32 purgeable:1;

		s32 ring:4;

		u32 cache_level:2;

	} **active_bo, **pinned_bo;

	u32 *active_bo_count, *pinned_bo_count;

	struct intel_overlay_error_state *overlay;

	struct intel_display_error_state *display;

};

struct intel_crtc_config;

struct intel_crtc;

struct intel_limit;

struct dpll;

struct drm_i915_display_funcs {

	bool (*fbc_enabled)(struct drm_device *dev);

	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);

	void (*disable_fbc)(struct drm_device *dev);

	int (*get_display_clock_speed)(struct drm_device *dev);

	int (*get_fifo_size)(struct drm_device *dev, int plane);

	/**

	 * find_dpll() - Find the best values for the PLL

	 * @limit: limits for the PLL

	 * @crtc: current CRTC

	 * @target: target frequency in kHz

	 * @refclk: reference clock frequency in kHz

	 * @match_clock: if provided, @best_clock P divider must

	 *               match the P divider from @match_clock

	 *               used for LVDS downclocking

	 * @best_clock: best PLL values found

	 *

	 * Returns true on success, false on failure.

	 */

	bool (*find_dpll)(const struct intel_limit *limit,

			  struct drm_crtc *crtc,

			  int target, int refclk,

			  struct dpll *match_clock,

			  struct dpll *best_clock);

	void (*update_wm)(struct drm_device *dev);

	void (*update_sprite_wm)(struct drm_plane *plane,

				 struct drm_crtc *crtc,

				 uint32_t sprite_width, int pixel_size,

				 bool enable, bool scaled);

	void (*modeset_global_resources)(struct drm_device *dev);

	/* Returns the active state of the crtc, and if the crtc is active,

	 * fills out the pipe-config with the hw state. */

	bool (*get_pipe_config)(struct intel_crtc *,

				struct intel_crtc_config *);

	void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);

	int (*crtc_mode_set)(struct drm_crtc *crtc,

			     int x, int y,

			     struct drm_framebuffer *old_fb);

	void (*crtc_enable)(struct drm_crtc *crtc);

	void (*crtc_disable)(struct drm_crtc *crtc);

	void (*off)(struct drm_crtc *crtc);

	void (*write_eld)(struct drm_connector *connector,

			  struct drm_crtc *crtc);

	void (*fdi_link_train)(struct drm_crtc *crtc);

	void (*init_clock_gating)(struct drm_device *dev);

	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,

			  struct drm_framebuffer *fb,

			  struct drm_i915_gem_object *obj,

			  uint32_t flags);

	int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,

			    int x, int y);

	void (*hpd_irq_setup)(struct drm_device *dev);

	/* clock updates for mode set */

	/* cursor updates */

	/* render clock increase/decrease */

	/* display clock increase/decrease */

	/* pll clock increase/decrease */

};

struct intel_uncore_funcs {

	void (*force_wake_get)(struct drm_i915_private *dev_priv);

	void (*force_wake_put)(struct drm_i915_private *dev_priv);

};

struct intel_uncore {

	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;

	unsigned forcewake_count;

};

#define DEV_INFO_FOR_EACH_FLAG(func, sep) \

	func(is_mobile) sep \

	func(is_i85x) sep \

	func(is_i915g) sep \

	func(is_i945gm) sep \

	func(is_g33) sep \

	func(need_gfx_hws) sep \

	func(is_g4x) sep \

	func(is_pineview) sep \

	func(is_broadwater) sep \

	func(is_crestline) sep \

	func(is_ivybridge) sep \

	func(is_valleyview) sep \

	func(is_haswell) sep \

	func(has_force_wake) sep \

	func(has_fbc) sep \

	func(has_pipe_cxsr) sep \

	func(has_hotplug) sep \

	func(cursor_needs_physical) sep \

	func(has_overlay) sep \

	func(overlay_needs_physical) sep \

	func(supports_tv) sep \

	func(has_bsd_ring) sep \

	func(has_blt_ring) sep \

	func(has_vebox_ring) sep \

	func(has_llc) sep \

	func(has_ddi) sep \

	func(has_fpga_dbg)

#define DEFINE_FLAG(name) u8 name:1

#define SEP_SEMICOLON ;

struct intel_device_info {

	u32 display_mmio_offset;

	u8 num_pipes:3;

	u8 gen;

	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);

};

#undef DEFINE_FLAG

#undef SEP_SEMICOLON

enum i915_cache_level {

	I915_CACHE_NONE = 0,

	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */

	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc

			      caches, eg sampler/render caches, and the

			      large Last-Level-Cache. LLC is coherent with

			      the CPU, but L3 is only visible to the GPU. */

	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */

};

typedef uint32_t gen6_gtt_pte_t;

struct i915_address_space {

	struct drm_mm mm;

	struct drm_device *dev;

	struct list_head global_link;

	unsigned long start;		/* Start offset always 0 for dri2 */

	size_t total;		/* size addr space maps (ex. 2GB for ggtt) */

	struct {

		dma_addr_t addr;

		struct page *page;

	} scratch;

	/**

	 * List of objects currently involved in rendering.

	 *

	 * Includes buffers having the contents of their GPU caches

	 * flushed, not necessarily primitives.  last_rendering_seqno

	 * represents when the rendering involved will be completed.

	 *

	 * A reference is held on the buffer while on this list.

	 */

	struct list_head active_list;

	/**

	 * LRU list of objects which are not in the ringbuffer and

	 * are ready to unbind, but are still in the GTT.

	 *

	 * last_rendering_seqno is 0 while an object is in this list.

	 *

	 * A reference is not held on the buffer while on this list,

	 * as merely being GTT-bound shouldn't prevent its being

	 * freed, and we'll pull it off the list in the free path.

	 */

	struct list_head inactive_list;

	/* FIXME: Need a more generic return type */

	gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,

				     enum i915_cache_level level,

				     bool valid); /* Create a valid PTE */

	void (*clear_range)(struct i915_address_space *vm,

			    unsigned int first_entry,

			    unsigned int num_entries,

			    bool use_scratch);

	void (*insert_entries)(struct i915_address_space *vm,

			       struct sg_table *st,

			       unsigned int first_entry,

			       enum i915_cache_level cache_level);

	void (*cleanup)(struct i915_address_space *vm);

};

/* The Graphics Translation Table is the way in which GEN hardware translates a

 * Graphics Virtual Address into a Physical Address. In addition to the normal

 * collateral associated with any va->pa translations GEN hardware also has a

 * portion of the GTT which can be mapped by the CPU and remain both coherent

 * and correct (in cases like swizzling). That region is referred to as GMADR in

 * the spec.

 */

struct i915_gtt {

	struct i915_address_space base;

	size_t stolen_size;		/* Total size of stolen memory */

	unsigned long mappable_end;	/* End offset that we can CPU map */

	struct io_mapping *mappable;	/* Mapping to our CPU mappable region */

	phys_addr_t mappable_base;	/* PA of our GMADR */

	/** "Graphics Stolen Memory" holds the global PTEs */

	void __iomem *gsm;

	bool do_idle_maps;

	int mtrr;

	/* global gtt ops */

	int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,

			  size_t *stolen, phys_addr_t *mappable_base,

			  unsigned long *mappable_end);

};

#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)

struct i915_hw_ppgtt {

	struct i915_address_space base;

	unsigned num_pd_entries;

	struct page **pt_pages;

	uint32_t pd_offset;

	dma_addr_t *pt_dma_addr;

	int (*enable)(struct drm_device *dev);

};

/**

 * A VMA represents a GEM BO that is bound into an address space. Therefore, a

 * VMA's presence cannot be guaranteed before binding, or after unbinding the

 * object into/from the address space.

 *

 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime

 * will always be <= an objects lifetime. So object refcounting should cover us.

 */

struct i915_vma {

	struct drm_mm_node node;

	struct drm_i915_gem_object *obj;

	struct i915_address_space *vm;

	/** This object's place on the active/inactive lists */

	struct list_head mm_list;

	struct list_head vma_link; /* Link in the object's VMA list */

	/** This vma's place in the batchbuffer or on the eviction list */

	struct list_head exec_list;

};

struct i915_ctx_hang_stats {

	/* This context had batch pending when hang was declared */

	unsigned batch_pending;

	/* This context had batch active when hang was declared */

	unsigned batch_active;

};

/* This must match up with the value previously used for execbuf2.rsvd1. */

#define DEFAULT_CONTEXT_ID 0

struct i915_hw_context {

	struct kref ref;

	int id;

	bool is_initialized;

	struct drm_i915_file_private *file_priv;

	struct intel_ring_buffer *ring;

	struct drm_i915_gem_object *obj;

	struct i915_ctx_hang_stats hang_stats;

};

struct i915_fbc {

	unsigned long size;

	unsigned int fb_id;

	enum plane plane;

	int y;

	struct drm_mm_node *compressed_fb;

	struct drm_mm_node *compressed_llb;

	struct intel_fbc_work {

		struct delayed_work work;

		struct drm_crtc *crtc;

		struct drm_framebuffer *fb;

		int interval;

	} *fbc_work;

enum no_fbc_reason {

		FBC_OK, /* FBC is enabled */

		FBC_UNSUPPORTED, /* FBC is not supported by this chipset */

	FBC_NO_OUTPUT, /* no outputs enabled to compress */

		FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */

	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */

	FBC_MODE_TOO_LARGE, /* mode too large for compression */

	FBC_BAD_PLANE, /* fbc not supported on plane */

	FBC_NOT_TILED, /* buffer not tiled */

	FBC_MULTIPLE_PIPES, /* more than one pipe active */

	FBC_MODULE_PARAM,

		FBC_CHIP_DEFAULT, /* disabled by default on this chip */

	} no_fbc_reason;

};

enum no_psr_reason {

	PSR_NO_SOURCE, /* Not supported on platform */

	PSR_NO_SINK, /* Not supported by panel */

	PSR_MODULE_PARAM,

	PSR_CRTC_NOT_ACTIVE,

	PSR_PWR_WELL_ENABLED,

	PSR_NOT_TILED,

	PSR_SPRITE_ENABLED,

	PSR_S3D_ENABLED,

	PSR_INTERLACED_ENABLED,

	PSR_HSW_NOT_DDIA,

};

enum intel_pch {

	PCH_NONE = 0,	/* No PCH present */

	PCH_IBX,	/* Ibexpeak PCH */

	PCH_CPT,	/* Cougarpoint PCH */

	PCH_LPT,	/* Lynxpoint PCH */

	PCH_NOP,

};

enum intel_sbi_destination {

	SBI_ICLK,

	SBI_MPHY,

};

#define QUIRK_PIPEA_FORCE (1<<0)

#define QUIRK_LVDS_SSC_DISABLE (1<<1)

#define QUIRK_INVERT_BRIGHTNESS (1<<2)

#define QUIRK_NO_PCH_PWM_ENABLE (1<<3)

struct intel_fbdev;

struct intel_fbc_work;

struct intel_gmbus {

	struct i2c_adapter adapter;

	u32 force_bit;

	u32 reg0;

	u32 gpio_reg;

	struct i2c_algo_bit_data bit_algo;

	struct drm_i915_private *dev_priv;

};

struct i915_suspend_saved_registers {

	u8 saveLBB;

	u32 saveDSPACNTR;

	u32 saveDSPBCNTR;

	u32 saveDSPARB;

	u32 savePIPEACONF;

	u32 savePIPEBCONF;

	u32 savePIPEASRC;

	u32 savePIPEBSRC;

	u32 saveFPA0;

	u32 saveFPA1;

	u32 saveDPLL_A;

	u32 saveDPLL_A_MD;

	u32 saveHTOTAL_A;

	u32 saveHBLANK_A;

	u32 saveHSYNC_A;

	u32 saveVTOTAL_A;

	u32 saveVBLANK_A;

	u32 saveVSYNC_A;

	u32 saveBCLRPAT_A;

	u32 saveTRANSACONF;

	u32 saveTRANS_HTOTAL_A;

	u32 saveTRANS_HBLANK_A;

	u32 saveTRANS_HSYNC_A;

	u32 saveTRANS_VTOTAL_A;

	u32 saveTRANS_VBLANK_A;

	u32 saveTRANS_VSYNC_A;

	u32 savePIPEASTAT;

	u32 saveDSPASTRIDE;

	u32 saveDSPASIZE;

	u32 saveDSPAPOS;

	u32 saveDSPAADDR;

	u32 saveDSPASURF;

	u32 saveDSPATILEOFF;

	u32 savePFIT_PGM_RATIOS;

	u32 saveBLC_HIST_CTL;

	u32 saveBLC_PWM_CTL;

	u32 saveBLC_PWM_CTL2;

	u32 saveBLC_CPU_PWM_CTL;

	u32 saveBLC_CPU_PWM_CTL2;

	u32 saveFPB0;

	u32 saveFPB1;

	u32 saveDPLL_B;

	u32 saveDPLL_B_MD;

	u32 saveHTOTAL_B;

	u32 saveHBLANK_B;

	u32 saveHSYNC_B;

	u32 saveVTOTAL_B;

	u32 saveVBLANK_B;

	u32 saveVSYNC_B;

	u32 saveBCLRPAT_B;

	u32 saveTRANSBCONF;

	u32 saveTRANS_HTOTAL_B;

	u32 saveTRANS_HBLANK_B;

	u32 saveTRANS_HSYNC_B;

	u32 saveTRANS_VTOTAL_B;

	u32 saveTRANS_VBLANK_B;

	u32 saveTRANS_VSYNC_B;

	u32 savePIPEBSTAT;

	u32 saveDSPBSTRIDE;

	u32 saveDSPBSIZE;

	u32 saveDSPBPOS;

	u32 saveDSPBADDR;

	u32 saveDSPBSURF;

	u32 saveDSPBTILEOFF;

	u32 saveVGA0;

	u32 saveVGA1;

	u32 saveVGA_PD;

	u32 saveVGACNTRL;

	u32 saveADPA;

	u32 saveLVDS;

	u32 savePP_ON_DELAYS;

	u32 savePP_OFF_DELAYS;

	u32 saveDVOA;

	u32 saveDVOB;

	u32 saveDVOC;

	u32 savePP_ON;

	u32 savePP_OFF;

	u32 savePP_CONTROL;

	u32 savePP_DIVISOR;

	u32 savePFIT_CONTROL;

	u32 save_palette_a[256];

	u32 save_palette_b[256];

	u32 saveDPFC_CB_BASE;

	u32 saveFBC_CFB_BASE;

	u32 saveFBC_LL_BASE;

	u32 saveFBC_CONTROL;

	u32 saveFBC_CONTROL2;

	u32 saveIER;

	u32 saveIIR;

	u32 saveIMR;

	u32 saveDEIER;

	u32 saveDEIMR;

	u32 saveGTIER;

	u32 saveGTIMR;

	u32 saveFDI_RXA_IMR;

	u32 saveFDI_RXB_IMR;

	u32 saveCACHE_MODE_0;

	u32 saveMI_ARB_STATE;

	u32 saveSWF0[16];

	u32 saveSWF1[16];

	u32 saveSWF2[3];

	u8 saveMSR;

	u8 saveSR[8];

	u8 saveGR[25];

	u8 saveAR_INDEX;

	u8 saveAR[21];

	u8 saveDACMASK;

	u8 saveCR[37];

	uint64_t saveFENCE[I915_MAX_NUM_FENCES];

	u32 saveCURACNTR;

	u32 saveCURAPOS;

	u32 saveCURABASE;

	u32 saveCURBCNTR;

	u32 saveCURBPOS;

	u32 saveCURBBASE;

	u32 saveCURSIZE;

	u32 saveDP_B;

	u32 saveDP_C;

	u32 saveDP_D;

	u32 savePIPEA_GMCH_DATA_M;

	u32 savePIPEB_GMCH_DATA_M;

	u32 savePIPEA_GMCH_DATA_N;

	u32 savePIPEB_GMCH_DATA_N;

	u32 savePIPEA_DP_LINK_M;

	u32 savePIPEB_DP_LINK_M;

	u32 savePIPEA_DP_LINK_N;

	u32 savePIPEB_DP_LINK_N;

	u32 saveFDI_RXA_CTL;

	u32 saveFDI_TXA_CTL;

	u32 saveFDI_RXB_CTL;

	u32 saveFDI_TXB_CTL;

	u32 savePFA_CTL_1;

	u32 savePFB_CTL_1;

	u32 savePFA_WIN_SZ;

	u32 savePFB_WIN_SZ;

	u32 savePFA_WIN_POS;

	u32 savePFB_WIN_POS;

	u32 savePCH_DREF_CONTROL;

	u32 saveDISP_ARB_CTL;

	u32 savePIPEA_DATA_M1;

	u32 savePIPEA_DATA_N1;

	u32 savePIPEA_LINK_M1;

	u32 savePIPEA_LINK_N1;

	u32 savePIPEB_DATA_M1;

	u32 savePIPEB_DATA_N1;

	u32 savePIPEB_LINK_M1;

	u32 savePIPEB_LINK_N1;

	u32 saveMCHBAR_RENDER_STANDBY;

	u32 savePCH_PORT_HOTPLUG;

};

struct intel_gen6_power_mgmt {

	/* work and pm_iir are protected by dev_priv->irq_lock */

	struct work_struct work;

	u32 pm_iir;

	/* On vlv we need to manually drop to Vmin with a delayed work. */

	struct delayed_work vlv_work;

	/* The below variables an all the rps hw state are protected by

	 * dev->struct mutext. */

	u8 cur_delay;

	u8 min_delay;

	u8 max_delay;

	u8 rpe_delay;

	u8 hw_max;

	struct delayed_work delayed_resume_work;

	/*

	 * Protects RPS/RC6 register access and PCU communication.

	 * Must be taken after struct_mutex if nested.

	 */

	struct mutex hw_lock;

};

/* defined intel_pm.c */

extern spinlock_t mchdev_lock;

struct intel_ilk_power_mgmt {

	u8 cur_delay;

	u8 min_delay;

	u8 max_delay;

	u8 fmax;

	u8 fstart;

	u64 last_count1;

	unsigned long last_time1;

	unsigned long chipset_power;

	u64 last_count2;

	struct timespec last_time2;

	unsigned long gfx_power;

	u8 corr;

	int c_m;

	int r_t;

	struct drm_i915_gem_object *pwrctx;

	struct drm_i915_gem_object *renderctx;

};

/* Power well structure for haswell */

struct i915_power_well {

	struct drm_device *device;

	spinlock_t lock;

	/* power well enable/disable usage count */

	int count;

	int i915_request;

};

struct i915_dri1_state {

	unsigned allow_batchbuffer : 1;

	u32 __iomem *gfx_hws_cpu_addr;

	unsigned int cpp;

	int back_offset;

	int front_offset;

	int current_page;

	int page_flipping;

	uint32_t counter;

};

struct i915_ums_state {

	/**

	 * Flag if the X Server, and thus DRM, is not currently in

	 * control of the device.

	 *

	 * This is set between LeaveVT and EnterVT.  It needs to be

	 * replaced with a semaphore.  It also needs to be

	 * transitioned away from for kernel modesetting.

	 */

	int mm_suspended;

};

struct intel_l3_parity {

	u32 *remap_info;

	struct work_struct error_work;

};

struct i915_gem_mm {

	/** Memory allocator for GTT stolen memory */

	struct drm_mm stolen;

	/** List of all objects in gtt_space. Used to restore gtt

	 * mappings on resume */

	struct list_head bound_list;

	/**

	 * List of objects which are not bound to the GTT (thus

	 * are idle and not used by the GPU) but still have

	 * (presumably uncached) pages still attached.

	 */

	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */

	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */

	struct i915_hw_ppgtt *aliasing_ppgtt;

	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */

	struct list_head fence_list;

	/**

	 * We leave the user IRQ off as much as possible,

	 * but this means that requests will finish and never

	 * be retired once the system goes idle. Set a timer to

	 * fire periodically while the ring is running. When it

	 * fires, go retire requests.

	 */

	struct delayed_work retire_work;

	/**

	 * Are we in a non-interruptible section of code like

	 * modesetting?

	 */

	bool interruptible;

	/** Bit 6 swizzling required for X tiling */

	uint32_t bit_6_swizzle_x;

	/** Bit 6 swizzling required for Y tiling */

	uint32_t bit_6_swizzle_y;

	/* storage for physical objects */

	struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];

	/* accounting, useful for userland debugging */

	spinlock_t object_stat_lock;

	size_t object_memory;

	u32 object_count;

};

struct drm_i915_error_state_buf {

	unsigned bytes;

	unsigned size;

	int err;

	u8 *buf;

	loff_t start;

	loff_t pos;

};

struct i915_error_state_file_priv {

	struct drm_device *dev;

	struct drm_i915_error_state *error;

};

struct i915_gpu_error {

	/* For hangcheck timer */

#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */

#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)

	struct timer_list hangcheck_timer;

	/* For reset and error_state handling. */

	spinlock_t lock;

	/* Protected by the above dev->gpu_error.lock. */

	struct drm_i915_error_state *first_error;

	struct work_struct work;

	unsigned long last_reset;

	/**

	 * State variable and reset counter controlling the reset flow

	 *

	 * Upper bits are for the reset counter.  This counter is used by the

	 * wait_seqno code to race-free noticed that a reset event happened and

	 * that it needs to restart the entire ioctl (since most likely the

	 * seqno it waited for won't ever signal anytime soon).

	 *

	 * This is important for lock-free wait paths, where no contended lock

	 * naturally enforces the correct ordering between the bail-out of the

	 * waiter and the gpu reset work code.

	 *

	 * Lowest bit controls the reset state machine: Set means a reset is in

	 * progress. This state will (presuming we don't have any bugs) decay

	 * into either unset (successful reset) or the special WEDGED value (hw

	 * terminally sour). All waiters on the reset_queue will be woken when

	 * that happens.

	 */

	atomic_t reset_counter;

	/**

	 * Special values/flags for reset_counter

	 *

	 * Note that the code relies on

	 * 	I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG

	 * being true.

	 */

#define I915_RESET_IN_PROGRESS_FLAG	1

#define I915_WEDGED			0xffffffff

	/**

	 * Waitqueue to signal when the reset has completed. Used by clients

	 * that wait for dev_priv->mm.wedged to settle.

	 */

	wait_queue_head_t reset_queue;

	/* For gpu hang simulation. */

	unsigned int stop_rings;

};

enum modeset_restore {

	MODESET_ON_LID_OPEN,

	MODESET_DONE,

	MODESET_SUSPENDED,

};

struct intel_vbt_data {

	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */

	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */

	unsigned int int_tv_support:1;

	unsigned int lvds_dither:1;

	unsigned int lvds_vbt:1;

	unsigned int int_crt_support:1;

	unsigned int lvds_use_ssc:1;

	unsigned int display_clock_mode:1;

	unsigned int fdi_rx_polarity_inverted:1;

	int lvds_ssc_freq;

	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

	/* eDP */

	int edp_rate;

	int edp_lanes;

	int edp_preemphasis;

	int edp_vswing;

	bool edp_initialized;

	bool edp_support;

	int edp_bpp;

	struct edp_power_seq edp_pps;

	int crt_ddc_pin;

	int child_dev_num;

	struct child_device_config *child_dev;

};

enum intel_ddb_partitioning {

	INTEL_DDB_PART_1_2,

	INTEL_DDB_PART_5_6, /* IVB+ */

};

struct intel_wm_level {

	bool enable;

	uint32_t pri_val;

	uint32_t spr_val;

	uint32_t cur_val;

	uint32_t fbc_val;

};

/*

 * This struct tracks the state needed for the Package C8+ feature.

 *

 * Package states C8 and deeper are really deep PC states that can only be

 * reached when all the devices on the system allow it, so even if the graphics

 * device allows PC8+, it doesn't mean the system will actually get to these

 * states.

 *