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2325 | Serge | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ |
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3 | /* |
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4 | * |
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5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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6 | * All Rights Reserved. |
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7 | * |
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8 | * Permission is hereby granted, free of charge, to any person obtaining a |
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9 | * copy of this software and associated documentation files (the |
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10 | * "Software"), to deal in the Software without restriction, including |
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11 | * without limitation the rights to use, copy, modify, merge, publish, |
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12 | * distribute, sub license, and/or sell copies of the Software, and to |
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13 | * permit persons to whom the Software is furnished to do so, subject to |
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14 | * the following conditions: |
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15 | * |
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16 | * The above copyright notice and this permission notice (including the |
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17 | * next paragraph) shall be included in all copies or substantial portions |
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18 | * of the Software. |
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19 | * |
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20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | * |
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28 | */ |
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29 | |||
30 | #ifndef _I915_DRV_H_ |
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31 | #define _I915_DRV_H_ |
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32 | |||
3480 | Serge | 33 | #include |
34 | |||
2325 | Serge | 35 | #include "i915_reg.h" |
2327 | Serge | 36 | #include "intel_bios.h" |
2326 | Serge | 37 | #include "intel_ringbuffer.h" |
3243 | Serge | 38 | #include |
2325 | Serge | 39 | //#include |
2330 | Serge | 40 | #include |
3031 | serge | 41 | #include |
2332 | Serge | 42 | #include |
2325 | Serge | 43 | //#include |
44 | |||
45 | #include |
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3243 | Serge | 46 | #include |
2325 | Serge | 47 | |
2360 | Serge | 48 | |
2325 | Serge | 49 | /* General customization: |
50 | */ |
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51 | |||
3031 | serge | 52 | #define I915_TILING_NONE 0 |
2327 | Serge | 53 | |
3031 | serge | 54 | #define VGA_RSRC_NONE 0x00 |
55 | #define VGA_RSRC_LEGACY_IO 0x01 |
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56 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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57 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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58 | /* Non-legacy access */ |
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59 | #define VGA_RSRC_NORMAL_IO 0x04 |
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60 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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2327 | Serge | 61 | |
2325 | Serge | 62 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
63 | |||
64 | #define DRIVER_NAME "i915" |
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65 | #define DRIVER_DESC "Intel Graphics" |
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66 | #define DRIVER_DATE "20080730" |
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67 | |||
68 | enum pipe { |
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69 | PIPE_A = 0, |
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70 | PIPE_B, |
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71 | PIPE_C, |
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72 | I915_MAX_PIPES |
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73 | }; |
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74 | #define pipe_name(p) ((p) + 'A') |
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75 | |||
3243 | Serge | 76 | enum transcoder { |
77 | TRANSCODER_A = 0, |
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78 | TRANSCODER_B, |
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79 | TRANSCODER_C, |
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80 | TRANSCODER_EDP = 0xF, |
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81 | }; |
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82 | #define transcoder_name(t) ((t) + 'A') |
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83 | |||
2325 | Serge | 84 | enum plane { |
85 | PLANE_A = 0, |
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86 | PLANE_B, |
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87 | PLANE_C, |
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88 | }; |
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89 | #define plane_name(p) ((p) + 'A') |
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90 | |||
4104 | Serge | 91 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
92 | |||
3031 | serge | 93 | enum port { |
94 | PORT_A = 0, |
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95 | PORT_B, |
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96 | PORT_C, |
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97 | PORT_D, |
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98 | PORT_E, |
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99 | I915_MAX_PORTS |
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100 | }; |
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101 | #define port_name(p) ((p) + 'A') |
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102 | |||
4104 | Serge | 103 | enum intel_display_power_domain { |
104 | POWER_DOMAIN_PIPE_A, |
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105 | POWER_DOMAIN_PIPE_B, |
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106 | POWER_DOMAIN_PIPE_C, |
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107 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
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108 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
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109 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
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110 | POWER_DOMAIN_TRANSCODER_A, |
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111 | POWER_DOMAIN_TRANSCODER_B, |
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112 | POWER_DOMAIN_TRANSCODER_C, |
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113 | POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF, |
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114 | }; |
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115 | |||
116 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
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117 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
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118 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
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119 | #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A) |
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120 | |||
3746 | Serge | 121 | enum hpd_pin { |
122 | HPD_NONE = 0, |
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123 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
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124 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
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125 | HPD_CRT, |
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126 | HPD_SDVO_B, |
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127 | HPD_SDVO_C, |
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128 | HPD_PORT_B, |
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129 | HPD_PORT_C, |
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130 | HPD_PORT_D, |
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131 | HPD_NUM_PINS |
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132 | }; |
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133 | |||
3480 | Serge | 134 | #define I915_GEM_GPU_DOMAINS \ |
135 | (I915_GEM_DOMAIN_RENDER | \ |
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136 | I915_GEM_DOMAIN_SAMPLER | \ |
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137 | I915_GEM_DOMAIN_COMMAND | \ |
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138 | I915_GEM_DOMAIN_INSTRUCTION | \ |
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139 | I915_GEM_DOMAIN_VERTEX) |
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2325 | Serge | 140 | |
3746 | Serge | 141 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
2325 | Serge | 142 | |
3031 | serge | 143 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
144 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
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145 | if ((intel_encoder)->base.crtc == (__crtc)) |
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146 | |||
4104 | Serge | 147 | struct drm_i915_private; |
148 | |||
149 | enum intel_dpll_id { |
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150 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
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151 | /* real shared dpll ids must be >= 0 */ |
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152 | DPLL_ID_PCH_PLL_A, |
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153 | DPLL_ID_PCH_PLL_B, |
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154 | }; |
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155 | #define I915_NUM_PLLS 2 |
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156 | |||
157 | struct intel_dpll_hw_state { |
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158 | uint32_t dpll; |
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159 | uint32_t dpll_md; |
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160 | uint32_t fp0; |
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161 | uint32_t fp1; |
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162 | }; |
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163 | |||
164 | struct intel_shared_dpll { |
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3031 | serge | 165 | int refcount; /* count of number of CRTCs sharing this PLL */ |
166 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
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167 | bool on; /* is the PLL actually active? Disabled during modeset */ |
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4104 | Serge | 168 | const char *name; |
169 | /* should match the index in the dev_priv->shared_dplls array */ |
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170 | enum intel_dpll_id id; |
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171 | struct intel_dpll_hw_state hw_state; |
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172 | void (*mode_set)(struct drm_i915_private *dev_priv, |
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173 | struct intel_shared_dpll *pll); |
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174 | void (*enable)(struct drm_i915_private *dev_priv, |
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175 | struct intel_shared_dpll *pll); |
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176 | void (*disable)(struct drm_i915_private *dev_priv, |
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177 | struct intel_shared_dpll *pll); |
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178 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
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179 | struct intel_shared_dpll *pll, |
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180 | struct intel_dpll_hw_state *hw_state); |
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3031 | serge | 181 | }; |
182 | |||
3480 | Serge | 183 | /* Used by dp and fdi links */ |
184 | struct intel_link_m_n { |
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185 | uint32_t tu; |
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186 | uint32_t gmch_m; |
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187 | uint32_t gmch_n; |
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188 | uint32_t link_m; |
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189 | uint32_t link_n; |
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190 | }; |
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191 | |||
192 | void intel_link_compute_m_n(int bpp, int nlanes, |
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193 | int pixel_clock, int link_clock, |
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194 | struct intel_link_m_n *m_n); |
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195 | |||
3243 | Serge | 196 | struct intel_ddi_plls { |
197 | int spll_refcount; |
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198 | int wrpll1_refcount; |
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199 | int wrpll2_refcount; |
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200 | }; |
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201 | |||
2325 | Serge | 202 | /* Interface history: |
203 | * |
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204 | * 1.1: Original. |
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205 | * 1.2: Add Power Management |
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206 | * 1.3: Add vblank support |
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207 | * 1.4: Fix cmdbuffer path, add heap destroy |
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208 | * 1.5: Add vblank pipe configuration |
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209 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
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210 | * - Support vertical blank on secondary display pipe |
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211 | */ |
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212 | #define DRIVER_MAJOR 1 |
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213 | #define DRIVER_MINOR 6 |
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214 | #define DRIVER_PATCHLEVEL 0 |
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215 | |||
216 | #define WATCH_LISTS 0 |
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3031 | serge | 217 | #define WATCH_GTT 0 |
2325 | Serge | 218 | |
219 | #define I915_GEM_PHYS_CURSOR_0 1 |
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220 | #define I915_GEM_PHYS_CURSOR_1 2 |
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221 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
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222 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
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223 | |||
3480 | Serge | 224 | struct drm_i915_gem_phys_object { |
225 | int id; |
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226 | struct page **page_list; |
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227 | drm_dma_handle_t *handle; |
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228 | struct drm_i915_gem_object *cur_obj; |
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229 | }; |
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2325 | Serge | 230 | |
231 | struct opregion_header; |
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232 | struct opregion_acpi; |
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233 | struct opregion_swsci; |
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234 | struct opregion_asle; |
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235 | |||
236 | struct intel_opregion { |
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3031 | serge | 237 | struct opregion_header __iomem *header; |
238 | struct opregion_acpi __iomem *acpi; |
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239 | struct opregion_swsci __iomem *swsci; |
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240 | struct opregion_asle __iomem *asle; |
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241 | void __iomem *vbt; |
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2325 | Serge | 242 | u32 __iomem *lid_state; |
243 | }; |
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244 | #define OPREGION_SIZE (8*1024) |
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245 | |||
246 | struct intel_overlay; |
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247 | struct intel_overlay_error_state; |
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248 | |||
2330 | Serge | 249 | struct drm_i915_master_private { |
250 | drm_local_map_t *sarea; |
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251 | struct _drm_i915_sarea *sarea_priv; |
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252 | }; |
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2325 | Serge | 253 | #define I915_FENCE_REG_NONE -1 |
3746 | Serge | 254 | #define I915_MAX_NUM_FENCES 32 |
255 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
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256 | #define I915_MAX_NUM_FENCE_BITS 6 |
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2325 | Serge | 257 | |
258 | struct drm_i915_fence_reg { |
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259 | struct list_head lru_list; |
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260 | struct drm_i915_gem_object *obj; |
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3031 | serge | 261 | int pin_count; |
2325 | Serge | 262 | }; |
263 | |||
264 | struct sdvo_device_mapping { |
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265 | u8 initialized; |
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266 | u8 dvo_port; |
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267 | u8 slave_addr; |
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268 | u8 dvo_wiring; |
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269 | u8 i2c_pin; |
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270 | u8 ddc_pin; |
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271 | }; |
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272 | |||
273 | struct intel_display_error_state; |
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274 | |||
275 | struct drm_i915_error_state { |
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3243 | Serge | 276 | struct kref ref; |
2325 | Serge | 277 | u32 eir; |
278 | u32 pgtbl_er; |
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3031 | serge | 279 | u32 ier; |
280 | u32 ccid; |
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3243 | Serge | 281 | u32 derrmr; |
282 | u32 forcewake; |
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3031 | serge | 283 | bool waiting[I915_NUM_RINGS]; |
2325 | Serge | 284 | u32 pipestat[I915_MAX_PIPES]; |
3031 | serge | 285 | u32 tail[I915_NUM_RINGS]; |
286 | u32 head[I915_NUM_RINGS]; |
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3243 | Serge | 287 | u32 ctl[I915_NUM_RINGS]; |
3031 | serge | 288 | u32 ipeir[I915_NUM_RINGS]; |
289 | u32 ipehr[I915_NUM_RINGS]; |
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290 | u32 instdone[I915_NUM_RINGS]; |
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291 | u32 acthd[I915_NUM_RINGS]; |
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292 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
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3243 | Serge | 293 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
3031 | serge | 294 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
295 | /* our own tracking of ring head and tail */ |
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296 | u32 cpu_ring_head[I915_NUM_RINGS]; |
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297 | u32 cpu_ring_tail[I915_NUM_RINGS]; |
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2325 | Serge | 298 | u32 error; /* gen6+ */ |
3031 | serge | 299 | u32 err_int; /* gen7 */ |
300 | u32 instpm[I915_NUM_RINGS]; |
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301 | u32 instps[I915_NUM_RINGS]; |
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302 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
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303 | u32 seqno[I915_NUM_RINGS]; |
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2325 | Serge | 304 | u64 bbaddr; |
3031 | serge | 305 | u32 fault_reg[I915_NUM_RINGS]; |
306 | u32 done_reg; |
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307 | u32 faddr[I915_NUM_RINGS]; |
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2342 | Serge | 308 | u64 fence[I915_MAX_NUM_FENCES]; |
2325 | Serge | 309 | struct timeval time; |
3031 | serge | 310 | struct drm_i915_error_ring { |
2325 | Serge | 311 | struct drm_i915_error_object { |
312 | int page_count; |
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313 | u32 gtt_offset; |
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314 | u32 *pages[0]; |
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3746 | Serge | 315 | } *ringbuffer, *batchbuffer, *ctx; |
3031 | serge | 316 | struct drm_i915_error_request { |
317 | long jiffies; |
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318 | u32 seqno; |
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319 | u32 tail; |
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320 | } *requests; |
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321 | int num_requests; |
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322 | } ring[I915_NUM_RINGS]; |
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2325 | Serge | 323 | struct drm_i915_error_buffer { |
324 | u32 size; |
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325 | u32 name; |
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3031 | serge | 326 | u32 rseqno, wseqno; |
2325 | Serge | 327 | u32 gtt_offset; |
328 | u32 read_domains; |
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329 | u32 write_domain; |
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2342 | Serge | 330 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
2325 | Serge | 331 | s32 pinned:2; |
332 | u32 tiling:2; |
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333 | u32 dirty:1; |
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334 | u32 purgeable:1; |
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3031 | serge | 335 | s32 ring:4; |
2325 | Serge | 336 | u32 cache_level:2; |
4104 | Serge | 337 | } **active_bo, **pinned_bo; |
338 | u32 *active_bo_count, *pinned_bo_count; |
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2325 | Serge | 339 | struct intel_overlay_error_state *overlay; |
340 | struct intel_display_error_state *display; |
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341 | }; |
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342 | |||
3746 | Serge | 343 | struct intel_crtc_config; |
344 | struct intel_crtc; |
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4104 | Serge | 345 | struct intel_limit; |
346 | struct dpll; |
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3746 | Serge | 347 | |
2325 | Serge | 348 | struct drm_i915_display_funcs { |
349 | bool (*fbc_enabled)(struct drm_device *dev); |
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350 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
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351 | void (*disable_fbc)(struct drm_device *dev); |
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352 | int (*get_display_clock_speed)(struct drm_device *dev); |
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353 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
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4104 | Serge | 354 | /** |
355 | * find_dpll() - Find the best values for the PLL |
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356 | * @limit: limits for the PLL |
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357 | * @crtc: current CRTC |
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358 | * @target: target frequency in kHz |
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359 | * @refclk: reference clock frequency in kHz |
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360 | * @match_clock: if provided, @best_clock P divider must |
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361 | * match the P divider from @match_clock |
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362 | * used for LVDS downclocking |
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363 | * @best_clock: best PLL values found |
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364 | * |
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365 | * Returns true on success, false on failure. |
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366 | */ |
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367 | bool (*find_dpll)(const struct intel_limit *limit, |
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368 | struct drm_crtc *crtc, |
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369 | int target, int refclk, |
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370 | struct dpll *match_clock, |
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371 | struct dpll *best_clock); |
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2325 | Serge | 372 | void (*update_wm)(struct drm_device *dev); |
4104 | Serge | 373 | void (*update_sprite_wm)(struct drm_plane *plane, |
374 | struct drm_crtc *crtc, |
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375 | uint32_t sprite_width, int pixel_size, |
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376 | bool enable, bool scaled); |
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3243 | Serge | 377 | void (*modeset_global_resources)(struct drm_device *dev); |
3746 | Serge | 378 | /* Returns the active state of the crtc, and if the crtc is active, |
379 | * fills out the pipe-config with the hw state. */ |
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380 | bool (*get_pipe_config)(struct intel_crtc *, |
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381 | struct intel_crtc_config *); |
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4104 | Serge | 382 | void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *); |
2325 | Serge | 383 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
384 | int x, int y, |
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385 | struct drm_framebuffer *old_fb); |
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3031 | serge | 386 | void (*crtc_enable)(struct drm_crtc *crtc); |
387 | void (*crtc_disable)(struct drm_crtc *crtc); |
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388 | void (*off)(struct drm_crtc *crtc); |
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2342 | Serge | 389 | void (*write_eld)(struct drm_connector *connector, |
390 | struct drm_crtc *crtc); |
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2325 | Serge | 391 | void (*fdi_link_train)(struct drm_crtc *crtc); |
392 | void (*init_clock_gating)(struct drm_device *dev); |
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393 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
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394 | struct drm_framebuffer *fb, |
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4104 | Serge | 395 | struct drm_i915_gem_object *obj, |
396 | uint32_t flags); |
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2325 | Serge | 397 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
398 | int x, int y); |
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3480 | Serge | 399 | void (*hpd_irq_setup)(struct drm_device *dev); |
2325 | Serge | 400 | /* clock updates for mode set */ |
401 | /* cursor updates */ |
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402 | /* render clock increase/decrease */ |
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403 | /* display clock increase/decrease */ |
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404 | /* pll clock increase/decrease */ |
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405 | }; |
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406 | |||
4104 | Serge | 407 | struct intel_uncore_funcs { |
3031 | serge | 408 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
409 | void (*force_wake_put)(struct drm_i915_private *dev_priv); |
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410 | }; |
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411 | |||
4104 | Serge | 412 | struct intel_uncore { |
413 | spinlock_t lock; /** lock is also taken in irq contexts. */ |
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3031 | serge | 414 | |
4104 | Serge | 415 | struct intel_uncore_funcs funcs; |
416 | |||
417 | unsigned fifo_count; |
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418 | unsigned forcewake_count; |
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419 | }; |
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420 | |||
421 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
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422 | func(is_mobile) sep \ |
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423 | func(is_i85x) sep \ |
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424 | func(is_i915g) sep \ |
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425 | func(is_i945gm) sep \ |
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426 | func(is_g33) sep \ |
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427 | func(need_gfx_hws) sep \ |
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428 | func(is_g4x) sep \ |
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429 | func(is_pineview) sep \ |
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430 | func(is_broadwater) sep \ |
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431 | func(is_crestline) sep \ |
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432 | func(is_ivybridge) sep \ |
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433 | func(is_valleyview) sep \ |
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434 | func(is_haswell) sep \ |
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435 | func(has_force_wake) sep \ |
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436 | func(has_fbc) sep \ |
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437 | func(has_pipe_cxsr) sep \ |
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438 | func(has_hotplug) sep \ |
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439 | func(cursor_needs_physical) sep \ |
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440 | func(has_overlay) sep \ |
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441 | func(overlay_needs_physical) sep \ |
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442 | func(supports_tv) sep \ |
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443 | func(has_bsd_ring) sep \ |
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444 | func(has_blt_ring) sep \ |
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445 | func(has_vebox_ring) sep \ |
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446 | func(has_llc) sep \ |
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447 | func(has_ddi) sep \ |
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448 | func(has_fpga_dbg) |
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449 | |||
450 | #define DEFINE_FLAG(name) u8 name:1 |
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451 | #define SEP_SEMICOLON ; |
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452 | |||
2325 | Serge | 453 | struct intel_device_info { |
3480 | Serge | 454 | u32 display_mmio_offset; |
3746 | Serge | 455 | u8 num_pipes:3; |
2325 | Serge | 456 | u8 gen; |
4104 | Serge | 457 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
2325 | Serge | 458 | }; |
459 | |||
4104 | Serge | 460 | #undef DEFINE_FLAG |
461 | #undef SEP_SEMICOLON |
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462 | |||
3480 | Serge | 463 | enum i915_cache_level { |
464 | I915_CACHE_NONE = 0, |
||
4104 | Serge | 465 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
466 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc |
||
467 | caches, eg sampler/render caches, and the |
||
468 | large Last-Level-Cache. LLC is coherent with |
||
469 | the CPU, but L3 is only visible to the GPU. */ |
||
470 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
||
3480 | Serge | 471 | }; |
472 | |||
4104 | Serge | 473 | typedef uint32_t gen6_gtt_pte_t; |
474 | |||
475 | struct i915_address_space { |
||
476 | struct drm_mm mm; |
||
477 | struct drm_device *dev; |
||
478 | struct list_head global_link; |
||
479 | unsigned long start; /* Start offset always 0 for dri2 */ |
||
480 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ |
||
481 | |||
482 | struct { |
||
483 | dma_addr_t addr; |
||
484 | struct page *page; |
||
485 | } scratch; |
||
486 | |||
487 | /** |
||
488 | * List of objects currently involved in rendering. |
||
489 | * |
||
490 | * Includes buffers having the contents of their GPU caches |
||
491 | * flushed, not necessarily primitives. last_rendering_seqno |
||
492 | * represents when the rendering involved will be completed. |
||
493 | * |
||
494 | * A reference is held on the buffer while on this list. |
||
495 | */ |
||
496 | struct list_head active_list; |
||
497 | |||
498 | /** |
||
499 | * LRU list of objects which are not in the ringbuffer and |
||
500 | * are ready to unbind, but are still in the GTT. |
||
501 | * |
||
502 | * last_rendering_seqno is 0 while an object is in this list. |
||
503 | * |
||
504 | * A reference is not held on the buffer while on this list, |
||
505 | * as merely being GTT-bound shouldn't prevent its being |
||
506 | * freed, and we'll pull it off the list in the free path. |
||
507 | */ |
||
508 | struct list_head inactive_list; |
||
509 | |||
510 | /* FIXME: Need a more generic return type */ |
||
511 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, |
||
512 | enum i915_cache_level level); |
||
513 | void (*clear_range)(struct i915_address_space *vm, |
||
514 | unsigned int first_entry, |
||
515 | unsigned int num_entries); |
||
516 | void (*insert_entries)(struct i915_address_space *vm, |
||
517 | struct sg_table *st, |
||
518 | unsigned int first_entry, |
||
519 | enum i915_cache_level cache_level); |
||
520 | void (*cleanup)(struct i915_address_space *vm); |
||
521 | }; |
||
522 | |||
3480 | Serge | 523 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
524 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
||
525 | * collateral associated with any va->pa translations GEN hardware also has a |
||
526 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
||
527 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
||
528 | * the spec. |
||
529 | */ |
||
530 | struct i915_gtt { |
||
4104 | Serge | 531 | struct i915_address_space base; |
3480 | Serge | 532 | size_t stolen_size; /* Total size of stolen memory */ |
533 | |||
534 | unsigned long mappable_end; /* End offset that we can CPU map */ |
||
535 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
||
536 | phys_addr_t mappable_base; /* PA of our GMADR */ |
||
537 | |||
538 | /** "Graphics Stolen Memory" holds the global PTEs */ |
||
539 | void __iomem *gsm; |
||
540 | |||
541 | bool do_idle_maps; |
||
542 | |||
4104 | Serge | 543 | int mtrr; |
544 | |||
3480 | Serge | 545 | /* global gtt ops */ |
546 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
||
547 | size_t *stolen, phys_addr_t *mappable_base, |
||
548 | unsigned long *mappable_end); |
||
549 | }; |
||
4104 | Serge | 550 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
3480 | Serge | 551 | |
3031 | serge | 552 | struct i915_hw_ppgtt { |
4104 | Serge | 553 | struct i915_address_space base; |
3031 | serge | 554 | unsigned num_pd_entries; |
3243 | Serge | 555 | struct page **pt_pages; |
3031 | serge | 556 | uint32_t pd_offset; |
557 | dma_addr_t *pt_dma_addr; |
||
3480 | Serge | 558 | |
3746 | Serge | 559 | int (*enable)(struct drm_device *dev); |
3031 | serge | 560 | }; |
561 | |||
4104 | Serge | 562 | /** |
563 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a |
||
564 | * VMA's presence cannot be guaranteed before binding, or after unbinding the |
||
565 | * object into/from the address space. |
||
566 | * |
||
567 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime |
||
568 | * will always be <= an objects lifetime. So object refcounting should cover us. |
||
569 | */ |
||
570 | struct i915_vma { |
||
571 | struct drm_mm_node node; |
||
572 | struct drm_i915_gem_object *obj; |
||
573 | struct i915_address_space *vm; |
||
3031 | serge | 574 | |
4104 | Serge | 575 | /** This object's place on the active/inactive lists */ |
576 | struct list_head mm_list; |
||
577 | |||
578 | struct list_head vma_link; /* Link in the object's VMA list */ |
||
579 | |||
580 | /** This vma's place in the batchbuffer or on the eviction list */ |
||
581 | struct list_head exec_list; |
||
582 | |||
583 | }; |
||
584 | |||
585 | struct i915_ctx_hang_stats { |
||
586 | /* This context had batch pending when hang was declared */ |
||
587 | unsigned batch_pending; |
||
588 | |||
589 | /* This context had batch active when hang was declared */ |
||
590 | unsigned batch_active; |
||
591 | }; |
||
592 | |||
3031 | serge | 593 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
594 | #define DEFAULT_CONTEXT_ID 0 |
||
595 | struct i915_hw_context { |
||
4104 | Serge | 596 | struct kref ref; |
3031 | serge | 597 | int id; |
598 | bool is_initialized; |
||
599 | struct drm_i915_file_private *file_priv; |
||
600 | struct intel_ring_buffer *ring; |
||
601 | struct drm_i915_gem_object *obj; |
||
4104 | Serge | 602 | struct i915_ctx_hang_stats hang_stats; |
3031 | serge | 603 | }; |
604 | |||
4104 | Serge | 605 | struct i915_fbc { |
606 | unsigned long size; |
||
607 | unsigned int fb_id; |
||
608 | enum plane plane; |
||
609 | int y; |
||
610 | |||
611 | struct drm_mm_node *compressed_fb; |
||
612 | struct drm_mm_node *compressed_llb; |
||
613 | |||
614 | struct intel_fbc_work { |
||
615 | struct delayed_work work; |
||
616 | struct drm_crtc *crtc; |
||
617 | struct drm_framebuffer *fb; |
||
618 | int interval; |
||
619 | } *fbc_work; |
||
620 | |||
2325 | Serge | 621 | enum no_fbc_reason { |
4104 | Serge | 622 | FBC_OK, /* FBC is enabled */ |
623 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ |
||
2325 | Serge | 624 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
4104 | Serge | 625 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ |
2325 | Serge | 626 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
627 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
||
628 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
||
629 | FBC_NOT_TILED, /* buffer not tiled */ |
||
630 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
||
631 | FBC_MODULE_PARAM, |
||
4104 | Serge | 632 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
633 | } no_fbc_reason; |
||
2325 | Serge | 634 | }; |
635 | |||
4104 | Serge | 636 | enum no_psr_reason { |
637 | PSR_NO_SOURCE, /* Not supported on platform */ |
||
638 | PSR_NO_SINK, /* Not supported by panel */ |
||
639 | PSR_MODULE_PARAM, |
||
640 | PSR_CRTC_NOT_ACTIVE, |
||
641 | PSR_PWR_WELL_ENABLED, |
||
642 | PSR_NOT_TILED, |
||
643 | PSR_SPRITE_ENABLED, |
||
644 | PSR_S3D_ENABLED, |
||
645 | PSR_INTERLACED_ENABLED, |
||
646 | PSR_HSW_NOT_DDIA, |
||
647 | }; |
||
648 | |||
2325 | Serge | 649 | enum intel_pch { |
3031 | serge | 650 | PCH_NONE = 0, /* No PCH present */ |
2325 | Serge | 651 | PCH_IBX, /* Ibexpeak PCH */ |
652 | PCH_CPT, /* Cougarpoint PCH */ |
||
3031 | serge | 653 | PCH_LPT, /* Lynxpoint PCH */ |
3746 | Serge | 654 | PCH_NOP, |
2325 | Serge | 655 | }; |
656 | |||
3243 | Serge | 657 | enum intel_sbi_destination { |
658 | SBI_ICLK, |
||
659 | SBI_MPHY, |
||
660 | }; |
||
661 | |||
2325 | Serge | 662 | #define QUIRK_PIPEA_FORCE (1<<0) |
663 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
||
3031 | serge | 664 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
4104 | Serge | 665 | #define QUIRK_NO_PCH_PWM_ENABLE (1<<3) |
2325 | Serge | 666 | |
667 | struct intel_fbdev; |
||
668 | struct intel_fbc_work; |
||
669 | |||
3031 | serge | 670 | struct intel_gmbus { |
671 | struct i2c_adapter adapter; |
||
3243 | Serge | 672 | u32 force_bit; |
3031 | serge | 673 | u32 reg0; |
674 | u32 gpio_reg; |
||
675 | struct i2c_algo_bit_data bit_algo; |
||
676 | struct drm_i915_private *dev_priv; |
||
677 | }; |
||
678 | |||
3243 | Serge | 679 | struct i915_suspend_saved_registers { |
2325 | Serge | 680 | u8 saveLBB; |
681 | u32 saveDSPACNTR; |
||
682 | u32 saveDSPBCNTR; |
||
683 | u32 saveDSPARB; |
||
684 | u32 savePIPEACONF; |
||
685 | u32 savePIPEBCONF; |
||
686 | u32 savePIPEASRC; |
||
687 | u32 savePIPEBSRC; |
||
688 | u32 saveFPA0; |
||
689 | u32 saveFPA1; |
||
690 | u32 saveDPLL_A; |
||
691 | u32 saveDPLL_A_MD; |
||
692 | u32 saveHTOTAL_A; |
||
693 | u32 saveHBLANK_A; |
||
694 | u32 saveHSYNC_A; |
||
695 | u32 saveVTOTAL_A; |
||
696 | u32 saveVBLANK_A; |
||
697 | u32 saveVSYNC_A; |
||
698 | u32 saveBCLRPAT_A; |
||
699 | u32 saveTRANSACONF; |
||
700 | u32 saveTRANS_HTOTAL_A; |
||
701 | u32 saveTRANS_HBLANK_A; |
||
702 | u32 saveTRANS_HSYNC_A; |
||
703 | u32 saveTRANS_VTOTAL_A; |
||
704 | u32 saveTRANS_VBLANK_A; |
||
705 | u32 saveTRANS_VSYNC_A; |
||
706 | u32 savePIPEASTAT; |
||
707 | u32 saveDSPASTRIDE; |
||
708 | u32 saveDSPASIZE; |
||
709 | u32 saveDSPAPOS; |
||
710 | u32 saveDSPAADDR; |
||
711 | u32 saveDSPASURF; |
||
712 | u32 saveDSPATILEOFF; |
||
713 | u32 savePFIT_PGM_RATIOS; |
||
714 | u32 saveBLC_HIST_CTL; |
||
715 | u32 saveBLC_PWM_CTL; |
||
716 | u32 saveBLC_PWM_CTL2; |
||
717 | u32 saveBLC_CPU_PWM_CTL; |
||
718 | u32 saveBLC_CPU_PWM_CTL2; |
||
719 | u32 saveFPB0; |
||
720 | u32 saveFPB1; |
||
721 | u32 saveDPLL_B; |
||
722 | u32 saveDPLL_B_MD; |
||
723 | u32 saveHTOTAL_B; |
||
724 | u32 saveHBLANK_B; |
||
725 | u32 saveHSYNC_B; |
||
726 | u32 saveVTOTAL_B; |
||
727 | u32 saveVBLANK_B; |
||
728 | u32 saveVSYNC_B; |
||
729 | u32 saveBCLRPAT_B; |
||
730 | u32 saveTRANSBCONF; |
||
731 | u32 saveTRANS_HTOTAL_B; |
||
732 | u32 saveTRANS_HBLANK_B; |
||
733 | u32 saveTRANS_HSYNC_B; |
||
734 | u32 saveTRANS_VTOTAL_B; |
||
735 | u32 saveTRANS_VBLANK_B; |
||
736 | u32 saveTRANS_VSYNC_B; |
||
737 | u32 savePIPEBSTAT; |
||
738 | u32 saveDSPBSTRIDE; |
||
739 | u32 saveDSPBSIZE; |
||
740 | u32 saveDSPBPOS; |
||
741 | u32 saveDSPBADDR; |
||
742 | u32 saveDSPBSURF; |
||
743 | u32 saveDSPBTILEOFF; |
||
744 | u32 saveVGA0; |
||
745 | u32 saveVGA1; |
||
746 | u32 saveVGA_PD; |
||
747 | u32 saveVGACNTRL; |
||
748 | u32 saveADPA; |
||
749 | u32 saveLVDS; |
||
750 | u32 savePP_ON_DELAYS; |
||
751 | u32 savePP_OFF_DELAYS; |
||
752 | u32 saveDVOA; |
||
753 | u32 saveDVOB; |
||
754 | u32 saveDVOC; |
||
755 | u32 savePP_ON; |
||
756 | u32 savePP_OFF; |
||
757 | u32 savePP_CONTROL; |
||
758 | u32 savePP_DIVISOR; |
||
759 | u32 savePFIT_CONTROL; |
||
760 | u32 save_palette_a[256]; |
||
761 | u32 save_palette_b[256]; |
||
762 | u32 saveDPFC_CB_BASE; |
||
763 | u32 saveFBC_CFB_BASE; |
||
764 | u32 saveFBC_LL_BASE; |
||
765 | u32 saveFBC_CONTROL; |
||
766 | u32 saveFBC_CONTROL2; |
||
767 | u32 saveIER; |
||
768 | u32 saveIIR; |
||
769 | u32 saveIMR; |
||
770 | u32 saveDEIER; |
||
771 | u32 saveDEIMR; |
||
772 | u32 saveGTIER; |
||
773 | u32 saveGTIMR; |
||
774 | u32 saveFDI_RXA_IMR; |
||
775 | u32 saveFDI_RXB_IMR; |
||
776 | u32 saveCACHE_MODE_0; |
||
777 | u32 saveMI_ARB_STATE; |
||
778 | u32 saveSWF0[16]; |
||
779 | u32 saveSWF1[16]; |
||
780 | u32 saveSWF2[3]; |
||
781 | u8 saveMSR; |
||
782 | u8 saveSR[8]; |
||
783 | u8 saveGR[25]; |
||
784 | u8 saveAR_INDEX; |
||
785 | u8 saveAR[21]; |
||
786 | u8 saveDACMASK; |
||
787 | u8 saveCR[37]; |
||
2342 | Serge | 788 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
2325 | Serge | 789 | u32 saveCURACNTR; |
790 | u32 saveCURAPOS; |
||
791 | u32 saveCURABASE; |
||
792 | u32 saveCURBCNTR; |
||
793 | u32 saveCURBPOS; |
||
794 | u32 saveCURBBASE; |
||
795 | u32 saveCURSIZE; |
||
796 | u32 saveDP_B; |
||
797 | u32 saveDP_C; |
||
798 | u32 saveDP_D; |
||
799 | u32 savePIPEA_GMCH_DATA_M; |
||
800 | u32 savePIPEB_GMCH_DATA_M; |
||
801 | u32 savePIPEA_GMCH_DATA_N; |
||
802 | u32 savePIPEB_GMCH_DATA_N; |
||
803 | u32 savePIPEA_DP_LINK_M; |
||
804 | u32 savePIPEB_DP_LINK_M; |
||
805 | u32 savePIPEA_DP_LINK_N; |
||
806 | u32 savePIPEB_DP_LINK_N; |
||
807 | u32 saveFDI_RXA_CTL; |
||
808 | u32 saveFDI_TXA_CTL; |
||
809 | u32 saveFDI_RXB_CTL; |
||
810 | u32 saveFDI_TXB_CTL; |
||
811 | u32 savePFA_CTL_1; |
||
812 | u32 savePFB_CTL_1; |
||
813 | u32 savePFA_WIN_SZ; |
||
814 | u32 savePFB_WIN_SZ; |
||
815 | u32 savePFA_WIN_POS; |
||
816 | u32 savePFB_WIN_POS; |
||
817 | u32 savePCH_DREF_CONTROL; |
||
818 | u32 saveDISP_ARB_CTL; |
||
819 | u32 savePIPEA_DATA_M1; |
||
820 | u32 savePIPEA_DATA_N1; |
||
821 | u32 savePIPEA_LINK_M1; |
||
822 | u32 savePIPEA_LINK_N1; |
||
823 | u32 savePIPEB_DATA_M1; |
||
824 | u32 savePIPEB_DATA_N1; |
||
825 | u32 savePIPEB_LINK_M1; |
||
826 | u32 savePIPEB_LINK_N1; |
||
827 | u32 saveMCHBAR_RENDER_STANDBY; |
||
828 | u32 savePCH_PORT_HOTPLUG; |
||
3243 | Serge | 829 | }; |
2325 | Serge | 830 | |
3243 | Serge | 831 | struct intel_gen6_power_mgmt { |
4104 | Serge | 832 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
3243 | Serge | 833 | struct work_struct work; |
834 | u32 pm_iir; |
||
835 | |||
4104 | Serge | 836 | /* On vlv we need to manually drop to Vmin with a delayed work. */ |
837 | struct delayed_work vlv_work; |
||
838 | |||
3243 | Serge | 839 | /* The below variables an all the rps hw state are protected by |
840 | * dev->struct mutext. */ |
||
841 | u8 cur_delay; |
||
842 | u8 min_delay; |
||
843 | u8 max_delay; |
||
4104 | Serge | 844 | u8 rpe_delay; |
3746 | Serge | 845 | u8 hw_max; |
3243 | Serge | 846 | |
847 | struct delayed_work delayed_resume_work; |
||
848 | |||
849 | /* |
||
850 | * Protects RPS/RC6 register access and PCU communication. |
||
851 | * Must be taken after struct_mutex if nested. |
||
852 | */ |
||
853 | struct mutex hw_lock; |
||
854 | }; |
||
855 | |||
3480 | Serge | 856 | /* defined intel_pm.c */ |
857 | extern spinlock_t mchdev_lock; |
||
858 | |||
3243 | Serge | 859 | struct intel_ilk_power_mgmt { |
860 | u8 cur_delay; |
||
861 | u8 min_delay; |
||
862 | u8 max_delay; |
||
863 | u8 fmax; |
||
864 | u8 fstart; |
||
865 | |||
866 | u64 last_count1; |
||
867 | unsigned long last_time1; |
||
868 | unsigned long chipset_power; |
||
869 | u64 last_count2; |
||
870 | struct timespec last_time2; |
||
871 | unsigned long gfx_power; |
||
872 | u8 corr; |
||
873 | |||
874 | int c_m; |
||
875 | int r_t; |
||
876 | |||
877 | struct drm_i915_gem_object *pwrctx; |
||
878 | struct drm_i915_gem_object *renderctx; |
||
879 | }; |
||
880 | |||
4104 | Serge | 881 | /* Power well structure for haswell */ |
882 | struct i915_power_well { |
||
883 | struct drm_device *device; |
||
884 | spinlock_t lock; |
||
885 | /* power well enable/disable usage count */ |
||
886 | int count; |
||
887 | int i915_request; |
||
888 | }; |
||
889 | |||
3243 | Serge | 890 | struct i915_dri1_state { |
891 | unsigned allow_batchbuffer : 1; |
||
892 | u32 __iomem *gfx_hws_cpu_addr; |
||
893 | |||
894 | unsigned int cpp; |
||
895 | int back_offset; |
||
896 | int front_offset; |
||
897 | int current_page; |
||
898 | int page_flipping; |
||
899 | |||
900 | uint32_t counter; |
||
901 | }; |
||
902 | |||
4104 | Serge | 903 | struct i915_ums_state { |
904 | /** |
||
905 | * Flag if the X Server, and thus DRM, is not currently in |
||
906 | * control of the device. |
||
907 | * |
||
908 | * This is set between LeaveVT and EnterVT. It needs to be |
||
909 | * replaced with a semaphore. It also needs to be |
||
910 | * transitioned away from for kernel modesetting. |
||
911 | */ |
||
912 | int mm_suspended; |
||
913 | }; |
||
914 | |||
3243 | Serge | 915 | struct intel_l3_parity { |
916 | u32 *remap_info; |
||
917 | struct work_struct error_work; |
||
918 | }; |
||
919 | |||
3480 | Serge | 920 | struct i915_gem_mm { |
921 | /** Memory allocator for GTT stolen memory */ |
||
922 | struct drm_mm stolen; |
||
923 | /** List of all objects in gtt_space. Used to restore gtt |
||
924 | * mappings on resume */ |
||
925 | struct list_head bound_list; |
||
926 | /** |
||
927 | * List of objects which are not bound to the GTT (thus |
||
928 | * are idle and not used by the GPU) but still have |
||
929 | * (presumably uncached) pages still attached. |
||
930 | */ |
||
931 | struct list_head unbound_list; |
||
932 | |||
933 | /** Usable portion of the GTT for GEM */ |
||
934 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
||
935 | |||
936 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
||
937 | struct i915_hw_ppgtt *aliasing_ppgtt; |
||
938 | |||
939 | bool shrinker_no_lock_stealing; |
||
940 | |||
941 | /** LRU list of objects with fence regs on them. */ |
||
942 | struct list_head fence_list; |
||
943 | |||
944 | /** |
||
945 | * We leave the user IRQ off as much as possible, |
||
946 | * but this means that requests will finish and never |
||
947 | * be retired once the system goes idle. Set a timer to |
||
948 | * fire periodically while the ring is running. When it |
||
949 | * fires, go retire requests. |
||
950 | */ |
||
951 | struct delayed_work retire_work; |
||
952 | |||
953 | /** |
||
954 | * Are we in a non-interruptible section of code like |
||
955 | * modesetting? |
||
956 | */ |
||
957 | bool interruptible; |
||
958 | |||
959 | /** Bit 6 swizzling required for X tiling */ |
||
960 | uint32_t bit_6_swizzle_x; |
||
961 | /** Bit 6 swizzling required for Y tiling */ |
||
962 | uint32_t bit_6_swizzle_y; |
||
963 | |||
964 | /* storage for physical objects */ |
||
965 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
||
966 | |||
967 | /* accounting, useful for userland debugging */ |
||
4104 | Serge | 968 | spinlock_t object_stat_lock; |
3480 | Serge | 969 | size_t object_memory; |
970 | u32 object_count; |
||
971 | }; |
||
972 | |||
4104 | Serge | 973 | struct drm_i915_error_state_buf { |
974 | unsigned bytes; |
||
975 | unsigned size; |
||
976 | int err; |
||
977 | u8 *buf; |
||
978 | loff_t start; |
||
979 | loff_t pos; |
||
980 | }; |
||
981 | |||
982 | struct i915_error_state_file_priv { |
||
983 | struct drm_device *dev; |
||
984 | struct drm_i915_error_state *error; |
||
985 | }; |
||
986 | |||
3480 | Serge | 987 | struct i915_gpu_error { |
988 | /* For hangcheck timer */ |
||
989 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
||
990 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
||
991 | struct timer_list hangcheck_timer; |
||
992 | |||
993 | /* For reset and error_state handling. */ |
||
994 | spinlock_t lock; |
||
995 | /* Protected by the above dev->gpu_error.lock. */ |
||
996 | struct drm_i915_error_state *first_error; |
||
997 | struct work_struct work; |
||
998 | |||
999 | unsigned long last_reset; |
||
1000 | |||
1001 | /** |
||
1002 | * State variable and reset counter controlling the reset flow |
||
1003 | * |
||
1004 | * Upper bits are for the reset counter. This counter is used by the |
||
1005 | * wait_seqno code to race-free noticed that a reset event happened and |
||
1006 | * that it needs to restart the entire ioctl (since most likely the |
||
1007 | * seqno it waited for won't ever signal anytime soon). |
||
1008 | * |
||
1009 | * This is important for lock-free wait paths, where no contended lock |
||
1010 | * naturally enforces the correct ordering between the bail-out of the |
||
1011 | * waiter and the gpu reset work code. |
||
1012 | * |
||
1013 | * Lowest bit controls the reset state machine: Set means a reset is in |
||
1014 | * progress. This state will (presuming we don't have any bugs) decay |
||
1015 | * into either unset (successful reset) or the special WEDGED value (hw |
||
1016 | * terminally sour). All waiters on the reset_queue will be woken when |
||
1017 | * that happens. |
||
1018 | */ |
||
1019 | atomic_t reset_counter; |
||
1020 | |||
1021 | /** |
||
1022 | * Special values/flags for reset_counter |
||
1023 | * |
||
1024 | * Note that the code relies on |
||
1025 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG |
||
1026 | * being true. |
||
1027 | */ |
||
1028 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
||
1029 | #define I915_WEDGED 0xffffffff |
||
1030 | |||
1031 | /** |
||
1032 | * Waitqueue to signal when the reset has completed. Used by clients |
||
1033 | * that wait for dev_priv->mm.wedged to settle. |
||
1034 | */ |
||
1035 | wait_queue_head_t reset_queue; |
||
1036 | |||
1037 | /* For gpu hang simulation. */ |
||
1038 | unsigned int stop_rings; |
||
1039 | }; |
||
1040 | |||
1041 | enum modeset_restore { |
||
1042 | MODESET_ON_LID_OPEN, |
||
1043 | MODESET_DONE, |
||
1044 | MODESET_SUSPENDED, |
||
1045 | }; |
||
1046 | |||
4104 | Serge | 1047 | struct intel_vbt_data { |
1048 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
||
1049 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
||
1050 | |||
1051 | /* Feature bits */ |
||
1052 | unsigned int int_tv_support:1; |
||
1053 | unsigned int lvds_dither:1; |
||
1054 | unsigned int lvds_vbt:1; |
||
1055 | unsigned int int_crt_support:1; |
||
1056 | unsigned int lvds_use_ssc:1; |
||
1057 | unsigned int display_clock_mode:1; |
||
1058 | unsigned int fdi_rx_polarity_inverted:1; |
||
1059 | int lvds_ssc_freq; |
||
1060 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
||
1061 | |||
1062 | /* eDP */ |
||
1063 | int edp_rate; |
||
1064 | int edp_lanes; |
||
1065 | int edp_preemphasis; |
||
1066 | int edp_vswing; |
||
1067 | bool edp_initialized; |
||
1068 | bool edp_support; |
||
1069 | int edp_bpp; |
||
1070 | struct edp_power_seq edp_pps; |
||
1071 | |||
1072 | int crt_ddc_pin; |
||
1073 | |||
1074 | int child_dev_num; |
||
1075 | struct child_device_config *child_dev; |
||
1076 | }; |
||
1077 | |||
1078 | enum intel_ddb_partitioning { |
||
1079 | INTEL_DDB_PART_1_2, |
||
1080 | INTEL_DDB_PART_5_6, /* IVB+ */ |
||
1081 | }; |
||
1082 | |||
1083 | struct intel_wm_level { |
||
1084 | bool enable; |
||
1085 | uint32_t pri_val; |
||
1086 | uint32_t spr_val; |
||
1087 | uint32_t cur_val; |
||
1088 | uint32_t fbc_val; |
||
1089 | }; |
||
1090 | |||
1091 | /* |
||
1092 | * This struct tracks the state needed for the Package C8+ feature. |
||
1093 | * |
||
1094 | * Package states C8 and deeper are really deep PC states that can only be |
||
1095 | * reached when all the devices on the system allow it, so even if the graphics |
||
1096 | * device allows PC8+, it doesn't mean the system will actually get to these |
||
1097 | * states. |
||
1098 | * |
||
1099 | * Our driver only allows PC8+ when all the outputs are disabled, the power well |
||
1100 | * is disabled and the GPU is idle. When these conditions are met, we manually |
||
1101 | * do the other conditions: disable the interrupts, clocks and switch LCPLL |
||
1102 | * refclk to Fclk. |
||
1103 | * |
||
1104 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
||
1105 | * the state of some registers, so when we come back from PC8+ we need to |
||
1106 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
||
1107 | * need to take care of the registers kept by RC6. |
||
1108 | * |
||
1109 | * The interrupt disabling is part of the requirements. We can only leave the |
||
1110 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we |
||
1111 | * can lock the machine. |
||
1112 | * |
||
1113 | * Ideally every piece of our code that needs PC8+ disabled would call |
||
1114 | * hsw_disable_package_c8, which would increment disable_count and prevent the |
||
1115 | * system from reaching PC8+. But we don't have a symmetric way to do this for |
||
1116 | * everything, so we have the requirements_met and gpu_idle variables. When we |
||
1117 | * switch requirements_met or gpu_idle to true we decrease disable_count, and |
||
1118 | * increase it in the opposite case. The requirements_met variable is true when |
||
1119 | * all the CRTCs, encoders and the power well are disabled. The gpu_idle |
||
1120 | * variable is true when the GPU is idle. |
||
1121 | * |
||
1122 | * In addition to everything, we only actually enable PC8+ if disable_count |
||
1123 | * stays at zero for at least some seconds. This is implemented with the |
||
1124 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of |
||
1125 | * consecutive times when all screens are disabled and some background app |
||
1126 | * queries the state of our connectors, or we have some application constantly |
||
1127 | * waking up to use the GPU. Only after the enable_work function actually |
||
1128 | * enables PC8+ the "enable" variable will become true, which means that it can |
||
1129 | * be false even if disable_count is 0. |
||
1130 | * |
||
1131 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and |
||
1132 | * goes back to false exactly before we reenable the IRQs. We use this variable |
||
1133 | * to check if someone is trying to enable/disable IRQs while they're supposed |
||
1134 | * to be disabled. This shouldn't happen and we'll print some error messages in |
||
1135 | * case it happens, but if it actually happens we'll also update the variables |
||
1136 | * inside struct regsave so when we restore the IRQs they will contain the |
||
1137 | * latest expected values. |
||
1138 | * |
||
1139 | * For more, read "Display Sequences for Package C8" on our documentation. |
||
1140 | */ |
||
1141 | struct i915_package_c8 { |
||
1142 | bool requirements_met; |
||
1143 | bool gpu_idle; |
||
1144 | bool irqs_disabled; |
||
1145 | /* Only true after the delayed work task actually enables it. */ |
||
1146 | bool enabled; |
||
1147 | int disable_count; |
||
1148 | struct mutex lock; |
||
1149 | struct delayed_work enable_work; |
||
1150 | |||
1151 | struct { |
||
1152 | uint32_t deimr; |
||
1153 | uint32_t sdeimr; |
||
1154 | uint32_t gtimr; |
||
1155 | uint32_t gtier; |
||
1156 | uint32_t gen6_pmimr; |
||
1157 | } regsave; |
||
1158 | }; |
||
1159 | |||
3243 | Serge | 1160 | typedef struct drm_i915_private { |
1161 | struct drm_device *dev; |
||
1162 | |||
1163 | const struct intel_device_info *info; |
||
1164 | |||
1165 | int relative_constants_mode; |
||
1166 | |||
1167 | void __iomem *regs; |
||
1168 | |||
4104 | Serge | 1169 | struct intel_uncore uncore; |
3243 | Serge | 1170 | |
1171 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
||
1172 | |||
3480 | Serge | 1173 | |
3243 | Serge | 1174 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1175 | * controller on different i2c buses. */ |
||
1176 | struct mutex gmbus_mutex; |
||
1177 | |||
1178 | /** |
||
1179 | * Base address of the gmbus and gpio block. |
||
1180 | */ |
||
1181 | uint32_t gpio_mmio_base; |
||
1182 | |||
3480 | Serge | 1183 | wait_queue_head_t gmbus_wait_queue; |
1184 | |||
3243 | Serge | 1185 | struct pci_dev *bridge_dev; |
1186 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
||
3480 | Serge | 1187 | uint32_t last_seqno, next_seqno; |
3243 | Serge | 1188 | |
1189 | drm_dma_handle_t *status_page_dmah; |
||
1190 | struct resource mch_res; |
||
1191 | |||
1192 | atomic_t irq_received; |
||
1193 | |||
1194 | /* protects the irq masks */ |
||
1195 | spinlock_t irq_lock; |
||
1196 | |||
3480 | Serge | 1197 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1198 | // struct pm_qos_request pm_qos; |
||
1199 | |||
3243 | Serge | 1200 | /* DPIO indirect register protection */ |
3480 | Serge | 1201 | struct mutex dpio_lock; |
3243 | Serge | 1202 | |
1203 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
||
1204 | u32 irq_mask; |
||
1205 | u32 gt_irq_mask; |
||
4104 | Serge | 1206 | u32 pm_irq_mask; |
3243 | Serge | 1207 | |
1208 | struct work_struct hotplug_work; |
||
3480 | Serge | 1209 | bool enable_hotplug_processing; |
3746 | Serge | 1210 | struct { |
1211 | unsigned long hpd_last_jiffies; |
||
1212 | int hpd_cnt; |
||
1213 | enum { |
||
1214 | HPD_ENABLED = 0, |
||
1215 | HPD_DISABLED = 1, |
||
1216 | HPD_MARK_DISABLED = 2 |
||
1217 | } hpd_mark; |
||
1218 | } hpd_stats[HPD_NUM_PINS]; |
||
4104 | Serge | 1219 | u32 hpd_event_bits; |
4126 | Serge | 1220 | struct timer_list hotplug_reenable_timer; |
3243 | Serge | 1221 | |
3746 | Serge | 1222 | int num_plane; |
3243 | Serge | 1223 | |
4104 | Serge | 1224 | struct i915_fbc fbc; |
3243 | Serge | 1225 | struct intel_opregion opregion; |
4104 | Serge | 1226 | struct intel_vbt_data vbt; |
3243 | Serge | 1227 | |
1228 | /* overlay */ |
||
1229 | struct intel_overlay *overlay; |
||
3480 | Serge | 1230 | unsigned int sprite_scaling_enabled; |
3243 | Serge | 1231 | |
3746 | Serge | 1232 | /* backlight */ |
1233 | struct { |
||
1234 | int level; |
||
1235 | bool enabled; |
||
4104 | Serge | 1236 | spinlock_t lock; /* bl registers and the above bl fields */ |
3746 | Serge | 1237 | struct backlight_device *device; |
1238 | } backlight; |
||
1239 | |||
3243 | Serge | 1240 | /* LVDS info */ |
1241 | bool no_aux_handshake; |
||
1242 | |||
1243 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
||
1244 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
||
1245 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
||
1246 | |||
1247 | unsigned int fsb_freq, mem_freq, is_ddr3; |
||
1248 | |||
4104 | Serge | 1249 | /** |
1250 | * wq - Driver workqueue for GEM. |
||
1251 | * |
||
1252 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
||
1253 | * locks, for otherwise the flushing done in the pageflip code will |
||
1254 | * result in deadlocks. |
||
1255 | */ |
||
3243 | Serge | 1256 | struct workqueue_struct *wq; |
1257 | |||
1258 | /* Display functions */ |
||
1259 | struct drm_i915_display_funcs display; |
||
1260 | |||
1261 | /* PCH chipset type */ |
||
1262 | enum intel_pch pch_type; |
||
1263 | unsigned short pch_id; |
||
1264 | |||
1265 | unsigned long quirks; |
||
1266 | |||
3480 | Serge | 1267 | enum modeset_restore modeset_restore; |
1268 | struct mutex modeset_restore_lock; |
||
3243 | Serge | 1269 | |
4104 | Serge | 1270 | struct list_head vm_list; /* Global list of all address spaces */ |
1271 | struct i915_gtt gtt; /* VMA representing the global address space */ |
||
2325 | Serge | 1272 | |
3480 | Serge | 1273 | struct i915_gem_mm mm; |
2325 | Serge | 1274 | |
3031 | serge | 1275 | /* Kernel Modesetting */ |
1276 | |||
2327 | Serge | 1277 | struct sdvo_device_mapping sdvo_mappings[2]; |
2325 | Serge | 1278 | |
2342 | Serge | 1279 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1280 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
||
2352 | Serge | 1281 | wait_queue_head_t pending_flip_queue; |
2325 | Serge | 1282 | |
4104 | Serge | 1283 | int num_shared_dpll; |
1284 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
||
3243 | Serge | 1285 | struct intel_ddi_plls ddi_plls; |
3031 | serge | 1286 | |
2325 | Serge | 1287 | /* Reclocking support */ |
1288 | bool render_reclock_avail; |
||
1289 | bool lvds_downclock_avail; |
||
1290 | /* indicates the reduced downclock for LVDS*/ |
||
1291 | int lvds_downclock; |
||
1292 | u16 orig_clock; |
||
1293 | |||
1294 | bool mchbar_need_disable; |
||
1295 | |||
3243 | Serge | 1296 | struct intel_l3_parity l3_parity; |
1297 | |||
4104 | Serge | 1298 | /* Cannot be determined by PCIID. You must always read a register. */ |
1299 | size_t ellc_size; |
||
1300 | |||
3031 | serge | 1301 | /* gen6+ rps state */ |
3243 | Serge | 1302 | struct intel_gen6_power_mgmt rps; |
2325 | Serge | 1303 | |
3031 | serge | 1304 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1305 | * mchdev_lock in intel_pm.c */ |
||
3243 | Serge | 1306 | struct intel_ilk_power_mgmt ips; |
2325 | Serge | 1307 | |
4104 | Serge | 1308 | /* Haswell power well */ |
1309 | struct i915_power_well power_well; |
||
2325 | Serge | 1310 | |
4104 | Serge | 1311 | enum no_psr_reason no_psr_reason; |
2325 | Serge | 1312 | |
3480 | Serge | 1313 | struct i915_gpu_error gpu_error; |
2325 | Serge | 1314 | |
4104 | Serge | 1315 | struct drm_i915_gem_object *vlv_pctx; |
1316 | |||
2325 | Serge | 1317 | /* list of fbdev register on this device */ |
2332 | Serge | 1318 | struct intel_fbdev *fbdev; |
2325 | Serge | 1319 | |
3243 | Serge | 1320 | /* |
1321 | * The console may be contended at resume, but we don't |
||
1322 | * want it to block on it. |
||
1323 | */ |
||
1324 | struct work_struct console_resume_work; |
||
1325 | |||
3031 | serge | 1326 | struct drm_property *broadcast_rgb_property; |
1327 | struct drm_property *force_audio_property; |
||
1328 | |||
1329 | bool hw_contexts_disabled; |
||
1330 | uint32_t hw_context_size; |
||
3243 | Serge | 1331 | |
3480 | Serge | 1332 | u32 fdi_rx_config; |
3243 | Serge | 1333 | |
1334 | struct i915_suspend_saved_registers regfile; |
||
1335 | |||
4104 | Serge | 1336 | struct { |
1337 | /* |
||
1338 | * Raw watermark latency values: |
||
1339 | * in 0.1us units for WM0, |
||
1340 | * in 0.5us units for WM1+. |
||
1341 | */ |
||
1342 | /* primary */ |
||
1343 | uint16_t pri_latency[5]; |
||
1344 | /* sprite */ |
||
1345 | uint16_t spr_latency[5]; |
||
1346 | /* cursor */ |
||
1347 | uint16_t cur_latency[5]; |
||
1348 | } wm; |
||
1349 | |||
1350 | struct i915_package_c8 pc8; |
||
1351 | |||
3243 | Serge | 1352 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
1353 | * here! */ |
||
1354 | struct i915_dri1_state dri1; |
||
4104 | Serge | 1355 | /* Old ums support infrastructure, same warning applies. */ |
1356 | struct i915_ums_state ums; |
||
2325 | Serge | 1357 | } drm_i915_private_t; |
1358 | |||
4104 | Serge | 1359 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1360 | { |
||
1361 | return dev->dev_private; |
||
1362 | } |
||
1363 | |||
3031 | serge | 1364 | /* Iterate over initialised rings */ |
1365 | #define for_each_ring(ring__, dev_priv__, i__) \ |
||
1366 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
||
1367 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
||
1368 | |||
1369 | enum hdmi_force_audio { |
||
1370 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
||
1371 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
||
1372 | HDMI_AUDIO_AUTO, /* trust EDID */ |
||
1373 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
||
1374 | }; |
||
1375 | |||
4104 | Serge | 1376 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
2325 | Serge | 1377 | |
3031 | serge | 1378 | struct drm_i915_gem_object_ops { |
1379 | /* Interface between the GEM object and its backing storage. |
||
1380 | * get_pages() is called once prior to the use of the associated set |
||
1381 | * of pages before to binding them into the GTT, and put_pages() is |
||
1382 | * called after we no longer need them. As we expect there to be |
||
1383 | * associated cost with migrating pages between the backing storage |
||
1384 | * and making them available for the GPU (e.g. clflush), we may hold |
||
1385 | * onto the pages after they are no longer referenced by the GPU |
||
1386 | * in case they may be used again shortly (for example migrating the |
||
1387 | * pages to a different memory domain within the GTT). put_pages() |
||
1388 | * will therefore most likely be called when the object itself is |
||
1389 | * being released or under memory pressure (where we attempt to |
||
1390 | * reap pages for the shrinker). |
||
1391 | */ |
||
1392 | int (*get_pages)(struct drm_i915_gem_object *); |
||
1393 | void (*put_pages)(struct drm_i915_gem_object *); |
||
1394 | }; |
||
1395 | |||
2327 | Serge | 1396 | struct drm_i915_gem_object { |
1397 | struct drm_gem_object base; |
||
2325 | Serge | 1398 | |
3031 | serge | 1399 | const struct drm_i915_gem_object_ops *ops; |
1400 | |||
4104 | Serge | 1401 | /** List of VMAs backed by this object */ |
1402 | struct list_head vma_list; |
||
1403 | |||
3480 | Serge | 1404 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1405 | struct drm_mm_node *stolen; |
||
4104 | Serge | 1406 | struct list_head global_list; |
2327 | Serge | 1407 | |
1408 | struct list_head ring_list; |
||
4104 | Serge | 1409 | /** Used in execbuf to temporarily hold a ref */ |
1410 | struct list_head obj_exec_link; |
||
2327 | Serge | 1411 | /** This object's place in the batchbuffer or on the eviction list */ |
1412 | struct list_head exec_list; |
||
1413 | |||
1414 | /** |
||
3031 | serge | 1415 | * This is set if the object is on the active lists (has pending |
1416 | * rendering and so a non-zero seqno), and is not set if it i s on |
||
1417 | * inactive (ready to be unbound) list. |
||
2327 | Serge | 1418 | */ |
2342 | Serge | 1419 | unsigned int active:1; |
2327 | Serge | 1420 | |
1421 | /** |
||
1422 | * This is set if the object has been written to since last bound |
||
1423 | * to the GTT |
||
1424 | */ |
||
2342 | Serge | 1425 | unsigned int dirty:1; |
2327 | Serge | 1426 | |
1427 | /** |
||
1428 | * Fence register bits (if any) for this object. Will be set |
||
1429 | * as needed when mapped into the GTT. |
||
1430 | * Protected by dev->struct_mutex. |
||
1431 | */ |
||
2342 | Serge | 1432 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
2327 | Serge | 1433 | |
1434 | /** |
||
1435 | * Advice: are the backing pages purgeable? |
||
1436 | */ |
||
2342 | Serge | 1437 | unsigned int madv:2; |
2327 | Serge | 1438 | |
1439 | /** |
||
1440 | * Current tiling mode for the object. |
||
1441 | */ |
||
2342 | Serge | 1442 | unsigned int tiling_mode:2; |
3031 | serge | 1443 | /** |
1444 | * Whether the tiling parameters for the currently associated fence |
||
1445 | * register have changed. Note that for the purposes of tracking |
||
1446 | * tiling changes we also treat the unfenced register, the register |
||
1447 | * slot that the object occupies whilst it executes a fenced |
||
1448 | * command (such as BLT on gen2/3), as a "fence". |
||
1449 | */ |
||
1450 | unsigned int fence_dirty:1; |
||
2327 | Serge | 1451 | |
1452 | /** How many users have pinned this object in GTT space. The following |
||
1453 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
||
1454 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
||
1455 | * times for the same batchbuffer), and the framebuffer code. When |
||
1456 | * switching/pageflipping, the framebuffer code has at most two buffers |
||
1457 | * pinned per crtc. |
||
1458 | * |
||
1459 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
||
1460 | * bits with absolutely no headroom. So use 4 bits. */ |
||
2342 | Serge | 1461 | unsigned int pin_count:4; |
2327 | Serge | 1462 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
1463 | |||
1464 | /** |
||
1465 | * Is the object at the current location in the gtt mappable and |
||
1466 | * fenceable? Used to avoid costly recalculations. |
||
1467 | */ |
||
2342 | Serge | 1468 | unsigned int map_and_fenceable:1; |
2327 | Serge | 1469 | |
1470 | /** |
||
1471 | * Whether the current gtt mapping needs to be mappable (and isn't just |
||
1472 | * mappable by accident). Track pin and fault separate for a more |
||
1473 | * accurate mappable working set. |
||
1474 | */ |
||
2342 | Serge | 1475 | unsigned int fault_mappable:1; |
1476 | unsigned int pin_mappable:1; |
||
4104 | Serge | 1477 | unsigned int pin_display:1; |
2327 | Serge | 1478 | |
1479 | /* |
||
1480 | * Is the GPU currently using a fence to access this buffer, |
||
1481 | */ |
||
1482 | unsigned int pending_fenced_gpu_access:1; |
||
1483 | unsigned int fenced_gpu_access:1; |
||
1484 | |||
4104 | Serge | 1485 | unsigned int cache_level:3; |
2327 | Serge | 1486 | |
3031 | serge | 1487 | unsigned int has_aliasing_ppgtt_mapping:1; |
1488 | unsigned int has_global_gtt_mapping:1; |
||
1489 | unsigned int has_dma_mapping:1; |
||
2327 | Serge | 1490 | |
3243 | Serge | 1491 | struct sg_table *pages; |
3031 | serge | 1492 | int pages_pin_count; |
2327 | Serge | 1493 | |
3031 | serge | 1494 | /* prime dma-buf support */ |
1495 | void *dma_buf_vmapping; |
||
1496 | int vmapping_count; |
||
1497 | |||
2327 | Serge | 1498 | /** |
1499 | * Used for performing relocations during execbuffer insertion. |
||
1500 | */ |
||
1501 | struct hlist_node exec_node; |
||
1502 | unsigned long exec_handle; |
||
1503 | struct drm_i915_gem_exec_object2 *exec_entry; |
||
1504 | |||
3031 | serge | 1505 | struct intel_ring_buffer *ring; |
1506 | |||
2327 | Serge | 1507 | /** Breadcrumb of last rendering to the buffer. */ |
3031 | serge | 1508 | uint32_t last_read_seqno; |
1509 | uint32_t last_write_seqno; |
||
2327 | Serge | 1510 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1511 | uint32_t last_fenced_seqno; |
||
1512 | |||
1513 | /** Current tiling stride for the object, if it's tiled. */ |
||
1514 | uint32_t stride; |
||
1515 | |||
1516 | /** Record of address bit 17 of each page at last unbind. */ |
||
1517 | unsigned long *bit_17; |
||
1518 | |||
1519 | /** User space pin count and filp owning the pin */ |
||
1520 | uint32_t user_pin_count; |
||
1521 | struct drm_file *pin_filp; |
||
1522 | |||
1523 | /** for phy allocated objects */ |
||
1524 | struct drm_i915_gem_phys_object *phys_obj; |
||
1525 | }; |
||
3243 | Serge | 1526 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
2327 | Serge | 1527 | |
2325 | Serge | 1528 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
1529 | |||
1530 | /** |
||
1531 | * Request queue structure. |
||
1532 | * |
||
1533 | * The request queue allows us to note sequence numbers that have been emitted |
||
1534 | * and may be associated with active buffers to be retired. |
||
1535 | * |
||
1536 | * By keeping this list, we can avoid having to do questionable |
||
1537 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
||
1538 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
||
1539 | */ |
||
1540 | struct drm_i915_gem_request { |
||
1541 | /** On Which ring this request was generated */ |
||
1542 | struct intel_ring_buffer *ring; |
||
1543 | |||
1544 | /** GEM sequence number associated with this request. */ |
||
1545 | uint32_t seqno; |
||
1546 | |||
4104 | Serge | 1547 | /** Position in the ringbuffer of the start of the request */ |
1548 | u32 head; |
||
1549 | |||
1550 | /** Position in the ringbuffer of the end of the request */ |
||
3031 | serge | 1551 | u32 tail; |
1552 | |||
4104 | Serge | 1553 | /** Context related to this request */ |
1554 | struct i915_hw_context *ctx; |
||
1555 | |||
1556 | /** Batch buffer related to this request if any */ |
||
1557 | struct drm_i915_gem_object *batch_obj; |
||
1558 | |||
2325 | Serge | 1559 | /** Time at which this request was emitted, in jiffies. */ |
1560 | unsigned long emitted_jiffies; |
||
1561 | |||
1562 | /** global list entry for this request */ |
||
1563 | struct list_head list; |
||
1564 | |||
1565 | struct drm_i915_file_private *file_priv; |
||
1566 | /** file_priv list entry for this request */ |
||
1567 | struct list_head client_list; |
||
1568 | }; |
||
1569 | |||
1570 | struct drm_i915_file_private { |
||
1571 | struct { |
||
3480 | Serge | 1572 | spinlock_t lock; |
2325 | Serge | 1573 | struct list_head request_list; |
1574 | } mm; |
||
3031 | serge | 1575 | struct idr context_idr; |
4104 | Serge | 1576 | |
1577 | struct i915_ctx_hang_stats hang_stats; |
||
2325 | Serge | 1578 | }; |
1579 | |||
4104 | Serge | 1580 | #define INTEL_INFO(dev) (to_i915(dev)->info) |
2325 | Serge | 1581 | |
1582 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
||
1583 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
||
1584 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
||
1585 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
||
1586 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
||
1587 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
||
1588 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
||
1589 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
||
1590 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
||
1591 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
||
1592 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
||
1593 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
||
1594 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
||
1595 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
||
1596 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
||
1597 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
||
1598 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
||
1599 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
||
3243 | Serge | 1600 | #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ |
1601 | (dev)->pci_device == 0x0152 || \ |
||
1602 | (dev)->pci_device == 0x015a) |
||
1603 | #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ |
||
1604 | (dev)->pci_device == 0x0106 || \ |
||
1605 | (dev)->pci_device == 0x010A) |
||
3031 | serge | 1606 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
1607 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
||
2325 | Serge | 1608 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
4104 | Serge | 1609 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
1610 | ((dev)->pci_device & 0xFF00) == 0x0C00) |
||
3243 | Serge | 1611 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
1612 | ((dev)->pci_device & 0xFF00) == 0x0A00) |
||
2325 | Serge | 1613 | |
1614 | /* |
||
1615 | * The genX designation typically refers to the render engine, so render |
||
1616 | * capability related checks should use IS_GEN, while display and other checks |
||
1617 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
||
1618 | * chips, etc.). |
||
1619 | */ |
||
1620 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
||
1621 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
||
1622 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
||
1623 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
||
1624 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
||
1625 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
||
1626 | |||
1627 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
||
1628 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
||
4104 | Serge | 1629 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring) |
3031 | serge | 1630 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
4104 | Serge | 1631 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
2325 | Serge | 1632 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1633 | |||
3031 | serge | 1634 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
1635 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
||
1636 | |||
2325 | Serge | 1637 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
1638 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
||
1639 | |||
3243 | Serge | 1640 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1641 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
||
1642 | |||
2325 | Serge | 1643 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1644 | * rows, which changed the alignment requirements and fence programming. |
||
1645 | */ |
||
1646 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
||
1647 | IS_I915GM(dev))) |
||
1648 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
||
1649 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
||
1650 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
||
1651 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
||
1652 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
||
1653 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
||
1654 | |||
1655 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
||
1656 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
||
1657 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
||
1658 | |||
4104 | Serge | 1659 | #define HAS_IPS(dev) (IS_ULT(dev)) |
2325 | Serge | 1660 | |
4104 | Serge | 1661 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
3746 | Serge | 1662 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
4104 | Serge | 1663 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
3480 | Serge | 1664 | |
3243 | Serge | 1665 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1666 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
||
1667 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
||
1668 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
||
1669 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
||
1670 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
||
1671 | |||
4104 | Serge | 1672 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
3031 | serge | 1673 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
2325 | Serge | 1674 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1675 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
||
3746 | Serge | 1676 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
3031 | serge | 1677 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
2325 | Serge | 1678 | |
3031 | serge | 1679 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
2325 | Serge | 1680 | |
3031 | serge | 1681 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
2325 | Serge | 1682 | |
3031 | serge | 1683 | #define GT_FREQUENCY_MULTIPLIER 50 |
1684 | |||
1685 | #include "i915_trace.h" |
||
1686 | |||
1687 | /** |
||
1688 | * RC6 is a special power stage which allows the GPU to enter an very |
||
1689 | * low-voltage mode when idle, using down to 0V while at this stage. This |
||
1690 | * stage is entered automatically when the GPU is idle when RC6 support is |
||
1691 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
||
1692 | * |
||
1693 | * There are different RC6 modes available in Intel GPU, which differentiate |
||
1694 | * among each other with the latency required to enter and leave RC6 and |
||
1695 | * voltage consumed by the GPU in different states. |
||
1696 | * |
||
1697 | * The combination of the following flags define which states GPU is allowed |
||
1698 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
||
1699 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
||
1700 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
||
1701 | * which brings the most power savings; deeper states save more power, but |
||
1702 | * require higher latency to switch to and wake up. |
||
1703 | */ |
||
1704 | #define INTEL_RC6_ENABLE (1<<0) |
||
1705 | #define INTEL_RC6p_ENABLE (1<<1) |
||
1706 | #define INTEL_RC6pp_ENABLE (1<<2) |
||
1707 | |||
1708 | extern unsigned int i915_fbpercrtc __always_unused; |
||
1709 | extern int i915_panel_ignore_lid __read_mostly; |
||
1710 | extern unsigned int i915_powersave __read_mostly; |
||
1711 | extern int i915_semaphores __read_mostly; |
||
1712 | extern unsigned int i915_lvds_downclock __read_mostly; |
||
1713 | extern int i915_lvds_channel_mode __read_mostly; |
||
1714 | extern int i915_panel_use_ssc __read_mostly; |
||
1715 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
||
1716 | extern int i915_enable_rc6 __read_mostly; |
||
1717 | extern int i915_enable_fbc __read_mostly; |
||
1718 | extern bool i915_enable_hangcheck __read_mostly; |
||
1719 | extern int i915_enable_ppgtt __read_mostly; |
||
4104 | Serge | 1720 | extern int i915_enable_psr __read_mostly; |
3031 | serge | 1721 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
3480 | Serge | 1722 | extern int i915_disable_power_well __read_mostly; |
4104 | Serge | 1723 | extern int i915_enable_ips __read_mostly; |
1724 | extern bool i915_fastboot __read_mostly; |
||
1725 | extern int i915_enable_pc8 __read_mostly; |
||
1726 | extern int i915_pc8_timeout __read_mostly; |
||
1727 | extern bool i915_prefault_disable __read_mostly; |
||
3031 | serge | 1728 | |
2325 | Serge | 1729 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1730 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
||
1731 | |||
1732 | /* i915_dma.c */ |
||
3031 | serge | 1733 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
2325 | Serge | 1734 | extern void i915_kernel_lost_context(struct drm_device * dev); |
1735 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
||
1736 | extern int i915_driver_unload(struct drm_device *); |
||
1737 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
||
1738 | extern void i915_driver_lastclose(struct drm_device * dev); |
||
1739 | extern void i915_driver_preclose(struct drm_device *dev, |
||
1740 | struct drm_file *file_priv); |
||
1741 | extern void i915_driver_postclose(struct drm_device *dev, |
||
1742 | struct drm_file *file_priv); |
||
1743 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
||
3031 | serge | 1744 | #ifdef CONFIG_COMPAT |
2325 | Serge | 1745 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1746 | unsigned long arg); |
||
3031 | serge | 1747 | #endif |
2325 | Serge | 1748 | extern int i915_emit_box(struct drm_device *dev, |
1749 | struct drm_clip_rect *box, |
||
1750 | int DR1, int DR4); |
||
3031 | serge | 1751 | extern int intel_gpu_reset(struct drm_device *dev); |
1752 | extern int i915_reset(struct drm_device *dev); |
||
2325 | Serge | 1753 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1754 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
||
1755 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
||
1756 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
||
1757 | |||
4104 | Serge | 1758 | extern void intel_console_resume(struct work_struct *work); |
2325 | Serge | 1759 | |
1760 | /* i915_irq.c */ |
||
4104 | Serge | 1761 | void i915_queue_hangcheck(struct drm_device *dev); |
2325 | Serge | 1762 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1763 | |||
1764 | extern void intel_irq_init(struct drm_device *dev); |
||
4104 | Serge | 1765 | extern void intel_pm_init(struct drm_device *dev); |
3480 | Serge | 1766 | extern void intel_hpd_init(struct drm_device *dev); |
4104 | Serge | 1767 | extern void intel_pm_init(struct drm_device *dev); |
2325 | Serge | 1768 | |
4104 | Serge | 1769 | extern void intel_uncore_sanitize(struct drm_device *dev); |
1770 | extern void intel_uncore_early_sanitize(struct drm_device *dev); |
||
1771 | extern void intel_uncore_init(struct drm_device *dev); |
||
1772 | extern void intel_uncore_clear_errors(struct drm_device *dev); |
||
1773 | extern void intel_uncore_check_errors(struct drm_device *dev); |
||
2325 | Serge | 1774 | |
1775 | void |
||
1776 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
||
1777 | |||
1778 | void |
||
1779 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
||
1780 | |||
1781 | /* i915_gem.c */ |
||
1782 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
||
1783 | struct drm_file *file_priv); |
||
1784 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
||
1785 | struct drm_file *file_priv); |
||
1786 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
||
1787 | struct drm_file *file_priv); |
||
1788 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
||
1789 | struct drm_file *file_priv); |
||
1790 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
||
1791 | struct drm_file *file_priv); |
||
1792 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
||
1793 | struct drm_file *file_priv); |
||
1794 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
||
1795 | struct drm_file *file_priv); |
||
1796 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
||
1797 | struct drm_file *file_priv); |
||
1798 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
||
1799 | struct drm_file *file_priv); |
||
1800 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
||
1801 | struct drm_file *file_priv); |
||
1802 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
||
1803 | struct drm_file *file_priv); |
||
1804 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
||
1805 | struct drm_file *file_priv); |
||
1806 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
||
1807 | struct drm_file *file_priv); |
||
3031 | serge | 1808 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1809 | struct drm_file *file); |
||
1810 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
||
1811 | struct drm_file *file); |
||
2325 | Serge | 1812 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1813 | struct drm_file *file_priv); |
||
1814 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
||
1815 | struct drm_file *file_priv); |
||
1816 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
||
1817 | struct drm_file *file_priv); |
||
1818 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
||
1819 | struct drm_file *file_priv); |
||
1820 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
||
1821 | struct drm_file *file_priv); |
||
1822 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
||
1823 | struct drm_file *file_priv); |
||
1824 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
||
1825 | struct drm_file *file_priv); |
||
3031 | serge | 1826 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1827 | struct drm_file *file_priv); |
||
2325 | Serge | 1828 | void i915_gem_load(struct drm_device *dev); |
3480 | Serge | 1829 | void *i915_gem_object_alloc(struct drm_device *dev); |
1830 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
||
2325 | Serge | 1831 | int i915_gem_init_object(struct drm_gem_object *obj); |
3031 | serge | 1832 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1833 | const struct drm_i915_gem_object_ops *ops); |
||
2325 | Serge | 1834 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1835 | size_t size); |
||
1836 | void i915_gem_free_object(struct drm_gem_object *obj); |
||
4104 | Serge | 1837 | struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj, |
1838 | struct i915_address_space *vm); |
||
1839 | void i915_gem_vma_destroy(struct i915_vma *vma); |
||
3480 | Serge | 1840 | |
2325 | Serge | 1841 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
4104 | Serge | 1842 | struct i915_address_space *vm, |
2325 | Serge | 1843 | uint32_t alignment, |
3031 | serge | 1844 | bool map_and_fenceable, |
1845 | bool nonblocking); |
||
2325 | Serge | 1846 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
4104 | Serge | 1847 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
1848 | int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); |
||
3480 | Serge | 1849 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
2325 | Serge | 1850 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
1851 | void i915_gem_lastclose(struct drm_device *dev); |
||
1852 | |||
3031 | serge | 1853 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
3243 | Serge | 1854 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
3031 | serge | 1855 | { |
3746 | Serge | 1856 | struct sg_page_iter sg_iter; |
3031 | serge | 1857 | |
3746 | Serge | 1858 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
1859 | return sg_page_iter_page(&sg_iter); |
||
1860 | |||
1861 | return NULL; |
||
3243 | Serge | 1862 | } |
3031 | serge | 1863 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1864 | { |
||
3243 | Serge | 1865 | BUG_ON(obj->pages == NULL); |
3031 | serge | 1866 | obj->pages_pin_count++; |
1867 | } |
||
1868 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
||
1869 | { |
||
1870 | BUG_ON(obj->pages_pin_count == 0); |
||
1871 | obj->pages_pin_count--; |
||
1872 | } |
||
1873 | |||
2325 | Serge | 1874 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
3031 | serge | 1875 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1876 | struct intel_ring_buffer *to); |
||
2325 | Serge | 1877 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
3243 | Serge | 1878 | struct intel_ring_buffer *ring); |
2325 | Serge | 1879 | |
1880 | int i915_gem_dumb_create(struct drm_file *file_priv, |
||
1881 | struct drm_device *dev, |
||
1882 | struct drm_mode_create_dumb *args); |
||
1883 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
||
1884 | uint32_t handle, uint64_t *offset); |
||
1885 | /** |
||
1886 | * Returns true if seq1 is later than seq2. |
||
1887 | */ |
||
2340 | Serge | 1888 | static inline bool |
1889 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
||
1890 | { |
||
1891 | return (int32_t)(seq1 - seq2) >= 0; |
||
1892 | } |
||
2325 | Serge | 1893 | |
3480 | Serge | 1894 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
1895 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
||
3031 | serge | 1896 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
1897 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
||
1898 | |||
1899 | static inline bool |
||
1900 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
||
2332 | Serge | 1901 | { |
3031 | serge | 1902 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
1903 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
1904 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
||
1905 | return true; |
||
1906 | } else |
||
1907 | return false; |
||
2332 | Serge | 1908 | } |
2325 | Serge | 1909 | |
3031 | serge | 1910 | static inline void |
1911 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
||
1912 | { |
||
1913 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
||
1914 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
4104 | Serge | 1915 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
3031 | serge | 1916 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
1917 | } |
||
1918 | } |
||
2332 | Serge | 1919 | |
2325 | Serge | 1920 | void i915_gem_retire_requests(struct drm_device *dev); |
3031 | serge | 1921 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
3480 | Serge | 1922 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
3031 | serge | 1923 | bool interruptible); |
3480 | Serge | 1924 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
1925 | { |
||
1926 | return unlikely(atomic_read(&error->reset_counter) |
||
1927 | & I915_RESET_IN_PROGRESS_FLAG); |
||
1928 | } |
||
3031 | serge | 1929 | |
3480 | Serge | 1930 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
1931 | { |
||
1932 | return atomic_read(&error->reset_counter) == I915_WEDGED; |
||
1933 | } |
||
1934 | |||
2325 | Serge | 1935 | void i915_gem_reset(struct drm_device *dev); |
4104 | Serge | 1936 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
2325 | Serge | 1937 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
3031 | serge | 1938 | int __must_check i915_gem_init(struct drm_device *dev); |
1939 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
||
1940 | void i915_gem_l3_remap(struct drm_device *dev); |
||
1941 | void i915_gem_init_swizzling(struct drm_device *dev); |
||
2325 | Serge | 1942 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1943 | int __must_check i915_gpu_idle(struct drm_device *dev); |
||
1944 | int __must_check i915_gem_idle(struct drm_device *dev); |
||
4104 | Serge | 1945 | int __i915_add_request(struct intel_ring_buffer *ring, |
2325 | Serge | 1946 | struct drm_file *file, |
4104 | Serge | 1947 | struct drm_i915_gem_object *batch_obj, |
3031 | serge | 1948 | u32 *seqno); |
4104 | Serge | 1949 | #define i915_add_request(ring, seqno) \ |
1950 | __i915_add_request(ring, NULL, NULL, seqno) |
||
3031 | serge | 1951 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
2325 | Serge | 1952 | uint32_t seqno); |
1953 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
||
1954 | int __must_check |
||
1955 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
||
1956 | bool write); |
||
1957 | int __must_check |
||
3031 | serge | 1958 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1959 | int __must_check |
||
2325 | Serge | 1960 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1961 | u32 alignment, |
||
1962 | struct intel_ring_buffer *pipelined); |
||
4104 | Serge | 1963 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
2325 | Serge | 1964 | int i915_gem_attach_phys_object(struct drm_device *dev, |
1965 | struct drm_i915_gem_object *obj, |
||
1966 | int id, |
||
1967 | int align); |
||
1968 | void i915_gem_detach_phys_object(struct drm_device *dev, |
||
1969 | struct drm_i915_gem_object *obj); |
||
1970 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
||
1971 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
||
1972 | |||
1973 | uint32_t |
||
3480 | Serge | 1974 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
1975 | uint32_t |
||
1976 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
||
1977 | int tiling_mode, bool fenced); |
||
2325 | Serge | 1978 | |
1979 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
||
1980 | enum i915_cache_level cache_level); |
||
1981 | |||
4104 | Serge | 1982 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
1983 | struct dma_buf *dma_buf); |
||
3031 | serge | 1984 | |
1985 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
||
1986 | struct drm_gem_object *gem_obj, int flags); |
||
1987 | |||
3746 | Serge | 1988 | void i915_gem_restore_fences(struct drm_device *dev); |
1989 | |||
4104 | Serge | 1990 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
1991 | struct i915_address_space *vm); |
||
1992 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
||
1993 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
||
1994 | struct i915_address_space *vm); |
||
1995 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
||
1996 | struct i915_address_space *vm); |
||
1997 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
||
1998 | struct i915_address_space *vm); |
||
1999 | struct i915_vma * |
||
2000 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
||
2001 | struct i915_address_space *vm); |
||
2002 | /* Some GGTT VM helpers */ |
||
2003 | #define obj_to_ggtt(obj) \ |
||
2004 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
||
2005 | static inline bool i915_is_ggtt(struct i915_address_space *vm) |
||
2006 | { |
||
2007 | struct i915_address_space *ggtt = |
||
2008 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; |
||
2009 | return vm == ggtt; |
||
2010 | } |
||
2011 | |||
2012 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
||
2013 | { |
||
2014 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); |
||
2015 | } |
||
2016 | |||
2017 | static inline unsigned long |
||
2018 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) |
||
2019 | { |
||
2020 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); |
||
2021 | } |
||
2022 | |||
2023 | static inline unsigned long |
||
2024 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) |
||
2025 | { |
||
2026 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); |
||
2027 | } |
||
2028 | |||
2029 | static inline int __must_check |
||
2030 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, |
||
2031 | uint32_t alignment, |
||
2032 | bool map_and_fenceable, |
||
2033 | bool nonblocking) |
||
2034 | { |
||
2035 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, |
||
2036 | map_and_fenceable, nonblocking); |
||
2037 | } |
||
2038 | #undef obj_to_ggtt |
||
2039 | |||
3031 | serge | 2040 | /* i915_gem_context.c */ |
2041 | void i915_gem_context_init(struct drm_device *dev); |
||
2042 | void i915_gem_context_fini(struct drm_device *dev); |
||
2043 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
||
2044 | int i915_switch_context(struct intel_ring_buffer *ring, |
||
2045 | struct drm_file *file, int to_id); |
||
4104 | Serge | 2046 | void i915_gem_context_free(struct kref *ctx_ref); |
2047 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) |
||
2048 | { |
||
2049 | kref_get(&ctx->ref); |
||
2050 | } |
||
2051 | |||
2052 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) |
||
2053 | { |
||
2054 | kref_put(&ctx->ref, i915_gem_context_free); |
||
2055 | } |
||
2056 | |||
2057 | struct i915_ctx_hang_stats * __must_check |
||
2058 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
||
2059 | struct drm_file *file, |
||
2060 | u32 id); |
||
3031 | serge | 2061 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2062 | struct drm_file *file); |
||
2063 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
||
2064 | struct drm_file *file); |
||
2065 | |||
2325 | Serge | 2066 | /* i915_gem_gtt.c */ |
3031 | serge | 2067 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
2068 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
||
2069 | struct drm_i915_gem_object *obj, |
||
2070 | enum i915_cache_level cache_level); |
||
2071 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, |
||
2072 | struct drm_i915_gem_object *obj); |
||
2073 | |||
2325 | Serge | 2074 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
3031 | serge | 2075 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
2076 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
||
2325 | Serge | 2077 | enum i915_cache_level cache_level); |
2078 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
||
3031 | serge | 2079 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
3480 | Serge | 2080 | void i915_gem_init_global_gtt(struct drm_device *dev); |
2081 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, |
||
2082 | unsigned long mappable_end, unsigned long end); |
||
3243 | Serge | 2083 | int i915_gem_gtt_init(struct drm_device *dev); |
2084 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
||
2085 | { |
||
2086 | if (INTEL_INFO(dev)->gen < 6) |
||
2087 | intel_gtt_chipset_flush(); |
||
2088 | } |
||
2325 | Serge | 2089 | |
3243 | Serge | 2090 | |
2325 | Serge | 2091 | /* i915_gem_evict.c */ |
4104 | Serge | 2092 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
2093 | struct i915_address_space *vm, |
||
2094 | int min_size, |
||
3031 | serge | 2095 | unsigned alignment, |
2096 | unsigned cache_level, |
||
2097 | bool mappable, |
||
2098 | bool nonblock); |
||
2099 | int i915_gem_evict_everything(struct drm_device *dev); |
||
2325 | Serge | 2100 | |
3031 | serge | 2101 | /* i915_gem_stolen.c */ |
2102 | int i915_gem_init_stolen(struct drm_device *dev); |
||
3480 | Serge | 2103 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
2104 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
||
3031 | serge | 2105 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
3480 | Serge | 2106 | struct drm_i915_gem_object * |
2107 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
||
3746 | Serge | 2108 | struct drm_i915_gem_object * |
2109 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
||
2110 | u32 stolen_offset, |
||
2111 | u32 gtt_offset, |
||
2112 | u32 size); |
||
3480 | Serge | 2113 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
3031 | serge | 2114 | |
2325 | Serge | 2115 | /* i915_gem_tiling.c */ |
4104 | Serge | 2116 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
3480 | Serge | 2117 | { |
2118 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
||
2119 | |||
2120 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
||
2121 | obj->tiling_mode != I915_TILING_NONE; |
||
2122 | } |
||
2123 | |||
2325 | Serge | 2124 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
2125 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
||
2126 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
||
2127 | |||
2128 | /* i915_gem_debug.c */ |
||
2129 | #if WATCH_LISTS |
||
2130 | int i915_verify_lists(struct drm_device *dev); |
||
2131 | #else |
||
2132 | #define i915_verify_lists(dev) 0 |
||
2133 | #endif |
||
2134 | |||
2135 | /* i915_debugfs.c */ |
||
2136 | int i915_debugfs_init(struct drm_minor *minor); |
||
2137 | void i915_debugfs_cleanup(struct drm_minor *minor); |
||
2138 | |||
4104 | Serge | 2139 | /* i915_gpu_error.c */ |
2140 | __printf(2, 3) |
||
2141 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
||
2142 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
||
2143 | const struct i915_error_state_file_priv *error); |
||
2144 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
||
2145 | size_t count, loff_t pos); |
||
2146 | static inline void i915_error_state_buf_release( |
||
2147 | struct drm_i915_error_state_buf *eb) |
||
2148 | { |
||
2149 | kfree(eb->buf); |
||
2150 | } |
||
2151 | void i915_capture_error_state(struct drm_device *dev); |
||
2152 | void i915_error_state_get(struct drm_device *dev, |
||
2153 | struct i915_error_state_file_priv *error_priv); |
||
2154 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); |
||
2155 | void i915_destroy_error_state(struct drm_device *dev); |
||
2156 | |||
2157 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); |
||
2158 | const char *i915_cache_level_str(int type); |
||
2159 | |||
2325 | Serge | 2160 | /* i915_suspend.c */ |
2161 | extern int i915_save_state(struct drm_device *dev); |
||
2162 | extern int i915_restore_state(struct drm_device *dev); |
||
2163 | |||
3480 | Serge | 2164 | /* i915_ums.c */ |
2165 | void i915_save_display_reg(struct drm_device *dev); |
||
2166 | void i915_restore_display_reg(struct drm_device *dev); |
||
2325 | Serge | 2167 | |
3031 | serge | 2168 | /* i915_sysfs.c */ |
2169 | void i915_setup_sysfs(struct drm_device *dev_priv); |
||
2170 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
||
2171 | |||
2325 | Serge | 2172 | /* intel_i2c.c */ |
2173 | extern int intel_setup_gmbus(struct drm_device *dev); |
||
2174 | extern void intel_teardown_gmbus(struct drm_device *dev); |
||
4104 | Serge | 2175 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3031 | serge | 2176 | { |
2177 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
||
2178 | } |
||
2179 | |||
2180 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
||
2181 | struct drm_i915_private *dev_priv, unsigned port); |
||
2325 | Serge | 2182 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2183 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
||
4104 | Serge | 2184 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
2342 | Serge | 2185 | { |
2186 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
||
2187 | } |
||
2325 | Serge | 2188 | extern void intel_i2c_reset(struct drm_device *dev); |
2189 | |||
2190 | /* intel_opregion.c */ |
||
2191 | extern int intel_opregion_setup(struct drm_device *dev); |
||
2192 | #ifdef CONFIG_ACPI |
||
2193 | extern void intel_opregion_init(struct drm_device *dev); |
||
2194 | extern void intel_opregion_fini(struct drm_device *dev); |
||
2195 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
||
2196 | #else |
||
2197 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
||
2198 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
||
2199 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
||
2200 | #endif |
||
2201 | |||
2202 | /* intel_acpi.c */ |
||
2203 | #ifdef CONFIG_ACPI |
||
2204 | extern void intel_register_dsm_handler(void); |
||
2205 | extern void intel_unregister_dsm_handler(void); |
||
2206 | #else |
||
2207 | static inline void intel_register_dsm_handler(void) { return; } |
||
2208 | static inline void intel_unregister_dsm_handler(void) { return; } |
||
2209 | #endif /* CONFIG_ACPI */ |
||
2210 | |||
2211 | /* modesetting */ |
||
3031 | serge | 2212 | extern void intel_modeset_init_hw(struct drm_device *dev); |
4104 | Serge | 2213 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
2325 | Serge | 2214 | extern void intel_modeset_init(struct drm_device *dev); |
2215 | extern void intel_modeset_gem_init(struct drm_device *dev); |
||
2216 | extern void intel_modeset_cleanup(struct drm_device *dev); |
||
2217 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
||
3243 | Serge | 2218 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2219 | bool force_restore); |
||
3480 | Serge | 2220 | extern void i915_redisable_vga(struct drm_device *dev); |
2325 | Serge | 2221 | extern bool intel_fbc_enabled(struct drm_device *dev); |
2222 | extern void intel_disable_fbc(struct drm_device *dev); |
||
2223 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
||
3243 | Serge | 2224 | extern void intel_init_pch_refclk(struct drm_device *dev); |
2325 | Serge | 2225 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
4104 | Serge | 2226 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
2227 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); |
||
2228 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); |
||
2342 | Serge | 2229 | extern void intel_detect_pch(struct drm_device *dev); |
2230 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
||
3031 | serge | 2231 | extern int intel_enable_rc6(const struct drm_device *dev); |
2325 | Serge | 2232 | |
3031 | serge | 2233 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
2234 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
||
2235 | struct drm_file *file); |
||
2342 | Serge | 2236 | |
2325 | Serge | 2237 | /* overlay */ |
2238 | #ifdef CONFIG_DEBUG_FS |
||
2239 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
||
4104 | Serge | 2240 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2241 | struct intel_overlay_error_state *error); |
||
2325 | Serge | 2242 | |
2243 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
||
4104 | Serge | 2244 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
2325 | Serge | 2245 | struct drm_device *dev, |
2246 | struct intel_display_error_state *error); |
||
2247 | #endif |
||
2248 | |||
2249 | /* On SNB platform, before reading ring registers forcewake bit |
||
2250 | * must be set to prevent GT core from power down and stale values being |
||
2251 | * returned. |
||
2252 | */ |
||
2253 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
||
2254 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
||
2255 | |||
3243 | Serge | 2256 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
2257 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
||
2258 | |||
4104 | Serge | 2259 | /* intel_sideband.c */ |
2260 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
||
2261 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
||
2262 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
||
2263 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg); |
||
2264 | void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val); |
||
2265 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
||
2266 | enum intel_sbi_destination destination); |
||
2267 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
||
2268 | enum intel_sbi_destination destination); |
||
2325 | Serge | 2269 | |
4104 | Serge | 2270 | int vlv_gpu_freq(int ddr_freq, int val); |
2271 | int vlv_freq_opcode(int ddr_freq, int val); |
||
2272 | |||
2273 | #define __i915_read(x) \ |
||
2274 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace); |
||
2275 | __i915_read(8) |
||
2276 | __i915_read(16) |
||
2277 | __i915_read(32) |
||
2278 | __i915_read(64) |
||
2325 | Serge | 2279 | #undef __i915_read |
2280 | |||
4104 | Serge | 2281 | #define __i915_write(x) \ |
2282 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace); |
||
2283 | __i915_write(8) |
||
2284 | __i915_write(16) |
||
2285 | __i915_write(32) |
||
2286 | __i915_write(64) |
||
2325 | Serge | 2287 | #undef __i915_write |
2288 | |||
4104 | Serge | 2289 | #define I915_READ8(reg) i915_read8(dev_priv, (reg), true) |
2290 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val), true) |
||
2325 | Serge | 2291 | |
4104 | Serge | 2292 | #define I915_READ16(reg) i915_read16(dev_priv, (reg), true) |
2293 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true) |
||
2294 | #define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false) |
||
2295 | #define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), false) |
||
2325 | Serge | 2296 | |
4104 | Serge | 2297 | #define I915_READ(reg) i915_read32(dev_priv, (reg), true) |
2298 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true) |
||
2299 | #define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false) |
||
2300 | #define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), false) |
||
2325 | Serge | 2301 | |
4104 | Serge | 2302 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true) |
2303 | #define I915_READ64(reg) i915_read64(dev_priv, (reg), true) |
||
2325 | Serge | 2304 | |
2305 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
||
2306 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
||
2307 | |||
3480 | Serge | 2308 | /* "Broadcast RGB" property */ |
2309 | #define INTEL_BROADCAST_RGB_AUTO 0 |
||
2310 | #define INTEL_BROADCAST_RGB_FULL 1 |
||
2311 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
||
2312 | |||
2313 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
||
2314 | { |
||
2315 | if (HAS_PCH_SPLIT(dev)) |
||
2316 | return CPU_VGACNTRL; |
||
2317 | else if (IS_VALLEYVIEW(dev)) |
||
2318 | return VLV_VGACNTRL; |
||
2319 | else |
||
2320 | return VGACNTRL; |
||
2321 | } |
||
2322 | |||
3746 | Serge | 2323 | static inline void __user *to_user_ptr(u64 address) |
2324 | { |
||
2325 | return (void __user *)(uintptr_t)address; |
||
2326 | } |
||
2327 | |||
2328 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
||
2329 | { |
||
2330 | unsigned long j = msecs_to_jiffies(m); |
||
2331 | |||
2332 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
||
2333 | } |
||
2334 | |||
2335 | static inline unsigned long |
||
2336 | timespec_to_jiffies_timeout(const struct timespec *value) |
||
2337 | { |
||
2338 | unsigned long j = timespec_to_jiffies(value); |
||
2339 | |||
2340 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
||
2341 | } |
||
2342 | |||
2343 | |||
2338 | Serge | 2344 | typedef struct |
2345 | { |
||
2346 | int width; |
||
2347 | int height; |
||
2348 | int bpp; |
||
2349 | int freq; |
||
2350 | }videomode_t; |
||
2325 | Serge | 2351 | |
2360 | Serge | 2352 | |
2353 | static inline int mutex_trylock(struct mutex *lock) |
||
2354 | { |
||
2355 | if (likely(atomic_cmpxchg(&lock->count, 1, 0) == 1)) |
||
2356 | return 1; |
||
2357 | return 0; |
||
2358 | } |
||
2359 | |||
2360 | |||
3031 | serge | 2361 | #define ioread32(addr) readl(addr) |
2360 | Serge | 2362 | |
2363 | |||
2364 | |||
2365 | |||
2366 | |||
2325 | Serge | 2367 | #endif=>>=>2) |