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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-

 */

/*

 *

 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation the rights to use, copy, modify, merge, publish,

 * distribute, sub license, and/or sell copies of the Software, and to

 * permit persons to whom the Software is furnished to do so, subject to

 * the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial portions

 * of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef _I915_DRV_H_

#define _I915_DRV_H_

#include "i915_reg.h"

#include "intel_bios.h"

#include "intel_ringbuffer.h"

//#include 

#include 

#include 

#include 

//#include 

#include 

/* General customization:

 */

#define I915_TILING_NONE          0

#define VGA_RSRC_NONE          0x00

#define VGA_RSRC_LEGACY_IO     0x01

#define VGA_RSRC_LEGACY_MEM    0x02

#define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)

/* Non-legacy access */

#define VGA_RSRC_NORMAL_IO     0x04

#define VGA_RSRC_NORMAL_MEM    0x08

#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."

#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20080730"

enum pipe {

	PIPE_A = 0,

	PIPE_B,

	PIPE_C,

	I915_MAX_PIPES

};

#define pipe_name(p) ((p) + 'A')

enum plane {

	PLANE_A = 0,

	PLANE_B,

	PLANE_C,

};

#define plane_name(p) ((p) + 'A')

enum port {

	PORT_A = 0,

	PORT_B,

	PORT_C,

	PORT_D,

	PORT_E,

	I915_MAX_PORTS

};

#define port_name(p) ((p) + 'A')

#define I915_GEM_GPU_DOMAINS	(~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))

#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)

#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \

	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \

		if ((intel_encoder)->base.crtc == (__crtc))

struct intel_pch_pll {

	int refcount; /* count of number of CRTCs sharing this PLL */

	int active; /* count of number of active CRTCs (i.e. DPMS on) */

	bool on; /* is the PLL actually active? Disabled during modeset */

	int pll_reg;

	int fp0_reg;

	int fp1_reg;

};

#define I915_NUM_PLLS 2

/* Interface history:

 *

 * 1.1: Original.

 * 1.2: Add Power Management

 * 1.3: Add vblank support

 * 1.4: Fix cmdbuffer path, add heap destroy

 * 1.5: Add vblank pipe configuration

 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank

 *      - Support vertical blank on secondary display pipe

 */

#define DRIVER_MAJOR		1

#define DRIVER_MINOR		6

#define DRIVER_PATCHLEVEL	0

#define WATCH_COHERENCY	0

#define WATCH_LISTS	0

#define WATCH_GTT	0

#define I915_GEM_PHYS_CURSOR_0 1

#define I915_GEM_PHYS_CURSOR_1 2

#define I915_GEM_PHYS_OVERLAY_REGS 3

#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)

struct mem_block {

	struct mem_block *next;

	struct mem_block *prev;

	int start;

	int size;

	struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */

};

struct opregion_header;

struct opregion_acpi;

struct opregion_swsci;

struct opregion_asle;

struct drm_i915_private;

struct intel_opregion {

	struct opregion_header __iomem *header;

	struct opregion_acpi __iomem *acpi;

	struct opregion_swsci __iomem *swsci;

	struct opregion_asle __iomem *asle;

	void __iomem *vbt;

	u32 __iomem *lid_state;

};

#define OPREGION_SIZE            (8*1024)

struct intel_overlay;

struct intel_overlay_error_state;

struct drm_i915_master_private {

	drm_local_map_t *sarea;

	struct _drm_i915_sarea *sarea_priv;

};

#define I915_FENCE_REG_NONE -1

#define I915_MAX_NUM_FENCES 16

/* 16 fences + sign bit for FENCE_REG_NONE */

#define I915_MAX_NUM_FENCE_BITS 5

struct drm_i915_fence_reg {

	struct list_head lru_list;

	struct drm_i915_gem_object *obj;

	int pin_count;

};

struct sdvo_device_mapping {

	u8 initialized;

	u8 dvo_port;

	u8 slave_addr;

	u8 dvo_wiring;

	u8 i2c_pin;

	u8 ddc_pin;

};

struct intel_display_error_state;

struct drm_i915_error_state {

	u32 eir;

	u32 pgtbl_er;

	u32 ier;

	u32 ccid;

	bool waiting[I915_NUM_RINGS];

	u32 pipestat[I915_MAX_PIPES];

	u32 tail[I915_NUM_RINGS];

	u32 head[I915_NUM_RINGS];

	u32 ipeir[I915_NUM_RINGS];

	u32 ipehr[I915_NUM_RINGS];

	u32 instdone[I915_NUM_RINGS];

	u32 acthd[I915_NUM_RINGS];

	u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];

	u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */

	/* our own tracking of ring head and tail */

	u32 cpu_ring_head[I915_NUM_RINGS];

	u32 cpu_ring_tail[I915_NUM_RINGS];

	u32 error; /* gen6+ */

	u32 err_int; /* gen7 */

	u32 instpm[I915_NUM_RINGS];

	u32 instps[I915_NUM_RINGS];

	u32 extra_instdone[I915_NUM_INSTDONE_REG];

	u32 seqno[I915_NUM_RINGS];

	u64 bbaddr;

	u32 fault_reg[I915_NUM_RINGS];

	u32 done_reg;

	u32 faddr[I915_NUM_RINGS];

	u64 fence[I915_MAX_NUM_FENCES];

	struct timeval time;

	struct drm_i915_error_ring {

	struct drm_i915_error_object {

		int page_count;

		u32 gtt_offset;

		u32 *pages[0];

		} *ringbuffer, *batchbuffer;

		struct drm_i915_error_request {

			long jiffies;

			u32 seqno;

			u32 tail;

		} *requests;

		int num_requests;

	} ring[I915_NUM_RINGS];

	struct drm_i915_error_buffer {

		u32 size;

		u32 name;

		u32 rseqno, wseqno;

		u32 gtt_offset;

		u32 read_domains;

		u32 write_domain;

		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;

		s32 pinned:2;

		u32 tiling:2;

		u32 dirty:1;

		u32 purgeable:1;

		s32 ring:4;

		u32 cache_level:2;

	} *active_bo, *pinned_bo;

	u32 active_bo_count, pinned_bo_count;

	struct intel_overlay_error_state *overlay;

	struct intel_display_error_state *display;

};

struct drm_i915_display_funcs {

	bool (*fbc_enabled)(struct drm_device *dev);

	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);

	void (*disable_fbc)(struct drm_device *dev);

	int (*get_display_clock_speed)(struct drm_device *dev);

	int (*get_fifo_size)(struct drm_device *dev, int plane);

	void (*update_wm)(struct drm_device *dev);

	void (*update_sprite_wm)(struct drm_device *dev, int pipe,

				 uint32_t sprite_width, int pixel_size);

	void (*update_linetime_wm)(struct drm_device *dev, int pipe,

				 struct drm_display_mode *mode);

	int (*crtc_mode_set)(struct drm_crtc *crtc,

			     struct drm_display_mode *mode,

			     struct drm_display_mode *adjusted_mode,

			     int x, int y,

			     struct drm_framebuffer *old_fb);

	void (*crtc_enable)(struct drm_crtc *crtc);

	void (*crtc_disable)(struct drm_crtc *crtc);

	void (*off)(struct drm_crtc *crtc);

	void (*write_eld)(struct drm_connector *connector,

			  struct drm_crtc *crtc);

	void (*fdi_link_train)(struct drm_crtc *crtc);

	void (*init_clock_gating)(struct drm_device *dev);

	void (*init_pch_clock_gating)(struct drm_device *dev);

	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,

			  struct drm_framebuffer *fb,

			  struct drm_i915_gem_object *obj);

	int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,

			    int x, int y);

	/* clock updates for mode set */

	/* cursor updates */

	/* render clock increase/decrease */

	/* display clock increase/decrease */

	/* pll clock increase/decrease */

};

struct drm_i915_gt_funcs {

	void (*force_wake_get)(struct drm_i915_private *dev_priv);

	void (*force_wake_put)(struct drm_i915_private *dev_priv);

};

#define DEV_INFO_FLAGS \

	DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \

	DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \

	DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \

	DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \

	DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \

	DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \

	DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \

	DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \

	DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \

	DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \

	DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \

	DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \

	DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \

	DEV_INFO_FLAG(has_llc)

struct intel_device_info {

	u8 gen;

	u8 is_mobile:1;

	u8 is_i85x:1;

	u8 is_i915g:1;

	u8 is_i945gm:1;

	u8 is_g33:1;

	u8 need_gfx_hws:1;

	u8 is_g4x:1;

	u8 is_pineview:1;

	u8 is_broadwater:1;

	u8 is_crestline:1;

	u8 is_ivybridge:1;

	u8 is_valleyview:1;

	u8 has_force_wake:1;

	u8 is_haswell:1;

	u8 has_fbc:1;

	u8 has_pipe_cxsr:1;

	u8 has_hotplug:1;

	u8 cursor_needs_physical:1;

	u8 has_overlay:1;

	u8 overlay_needs_physical:1;

	u8 supports_tv:1;

	u8 has_bsd_ring:1;

	u8 has_blt_ring:1;

	u8 has_llc:1;

};

#define I915_PPGTT_PD_ENTRIES 512

#define I915_PPGTT_PT_ENTRIES 1024

struct i915_hw_ppgtt {

	unsigned num_pd_entries;

    dma_addr_t *pt_pages;

	uint32_t pd_offset;

	dma_addr_t *pt_dma_addr;

	dma_addr_t scratch_page_dma_addr;

};

/* This must match up with the value previously used for execbuf2.rsvd1. */

#define DEFAULT_CONTEXT_ID 0

struct i915_hw_context {

	int id;

	bool is_initialized;

	struct drm_i915_file_private *file_priv;

	struct intel_ring_buffer *ring;

	struct drm_i915_gem_object *obj;

};

enum no_fbc_reason {

	FBC_NO_OUTPUT, /* no outputs enabled to compress */

	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */

	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */

	FBC_MODE_TOO_LARGE, /* mode too large for compression */

	FBC_BAD_PLANE, /* fbc not supported on plane */

	FBC_NOT_TILED, /* buffer not tiled */

	FBC_MULTIPLE_PIPES, /* more than one pipe active */

	FBC_MODULE_PARAM,

};

enum intel_pch {

	PCH_NONE = 0,	/* No PCH present */

	PCH_IBX,	/* Ibexpeak PCH */

	PCH_CPT,	/* Cougarpoint PCH */

	PCH_LPT,	/* Lynxpoint PCH */

};

#define QUIRK_PIPEA_FORCE (1<<0)

#define QUIRK_LVDS_SSC_DISABLE (1<<1)

#define QUIRK_INVERT_BRIGHTNESS (1<<2)

struct intel_fbdev;

struct intel_fbc_work;

struct intel_gmbus {

	struct i2c_adapter adapter;

	bool force_bit;

	u32 reg0;

	u32 gpio_reg;

	struct i2c_algo_bit_data bit_algo;

	struct drm_i915_private *dev_priv;

};

typedef struct drm_i915_private {

	struct drm_device *dev;

	const struct intel_device_info *info;

	int relative_constants_mode;

	void __iomem *regs;

	struct drm_i915_gt_funcs gt;

	/** gt_fifo_count and the subsequent register write are synchronized

	 * with dev->struct_mutex. */

	unsigned gt_fifo_count;

	/** forcewake_count is protected by gt_lock */

	unsigned forcewake_count;

	/** gt_lock is also taken in irq contexts. */

    spinlock_t gt_lock;

	struct intel_gmbus gmbus[GMBUS_NUM_PORTS];

	/** gmbus_mutex protects against concurrent usage of the single hw gmbus

	 * controller on different i2c buses. */

	struct mutex gmbus_mutex;

	/**

	 * Base address of the gmbus and gpio block.

	 */

	uint32_t gpio_mmio_base;

	struct pci_dev *bridge_dev;

    struct intel_ring_buffer ring[I915_NUM_RINGS];

	uint32_t next_seqno;

    drm_dma_handle_t *status_page_dmah;

	uint32_t counter;

    struct drm_i915_gem_object *pwrctx;

    struct drm_i915_gem_object *renderctx;

//   struct resource mch_res;

	atomic_t irq_received;

	/* protects the irq masks */

	spinlock_t irq_lock;

	/* DPIO indirect register protection */

	spinlock_t dpio_lock;

	/** Cached value of IMR to avoid reads in updating the bitfield */

	u32 pipestat[2];

	u32 irq_mask;

	u32 gt_irq_mask;

	u32 pch_irq_mask;

	u32 hotplug_supported_mask;

	struct work_struct hotplug_work;

	int num_pipe;

	int num_pch_pll;

	/* For hangcheck timer */

#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */

    struct timer_list hangcheck_timer;

	int hangcheck_count;

	uint32_t last_acthd[I915_NUM_RINGS];

	uint32_t prev_instdone[I915_NUM_INSTDONE_REG];

	unsigned int stop_rings;

	unsigned long cfb_size;

	unsigned int cfb_fb;

	enum plane cfb_plane;

	int cfb_y;

//   struct intel_fbc_work *fbc_work;

    struct intel_opregion opregion;

	/* overlay */

//   struct intel_overlay *overlay;

	bool sprite_scaling_enabled;

	/* LVDS info */

	int backlight_level;  /* restore backlight to this value */

	bool backlight_enabled;

	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */

	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits from the VBIOS */

	unsigned int int_tv_support:1;

	unsigned int lvds_dither:1;

	unsigned int lvds_vbt:1;

	unsigned int int_crt_support:1;

	unsigned int lvds_use_ssc:1;

	unsigned int display_clock_mode:1;

	int lvds_ssc_freq;

	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

	unsigned int lvds_val; /* used for checking LVDS channel mode */

	struct {

		int rate;

		int lanes;

		int preemphasis;

		int vswing;

		bool initialized;

		bool support;

		int bpp;

        struct edp_power_seq pps;

	} edp;

	bool no_aux_handshake;

//   struct notifier_block lid_notifier;

	int crt_ddc_pin;

	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */

	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */

	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;

	spinlock_t error_lock;

	/* Protected by dev->error_lock. */

	struct drm_i915_error_state *first_error;

	struct work_struct error_work;

	struct completion error_completion;

    struct workqueue_struct *wq;

	/* Display functions */

    struct drm_i915_display_funcs display;

	/* PCH chipset type */

	enum intel_pch pch_type;

	unsigned long quirks;

	/* Register state */

	bool modeset_on_lid;

	u8 saveLBB;

	u32 saveDSPACNTR;

	u32 saveDSPBCNTR;

	u32 saveDSPARB;

	u32 saveHWS;

	u32 savePIPEACONF;

	u32 savePIPEBCONF;

	u32 savePIPEASRC;

	u32 savePIPEBSRC;

	u32 saveFPA0;

	u32 saveFPA1;

	u32 saveDPLL_A;

	u32 saveDPLL_A_MD;

	u32 saveHTOTAL_A;

	u32 saveHBLANK_A;

	u32 saveHSYNC_A;

	u32 saveVTOTAL_A;

	u32 saveVBLANK_A;

	u32 saveVSYNC_A;

	u32 saveBCLRPAT_A;

	u32 saveTRANSACONF;

	u32 saveTRANS_HTOTAL_A;

	u32 saveTRANS_HBLANK_A;

	u32 saveTRANS_HSYNC_A;

	u32 saveTRANS_VTOTAL_A;

	u32 saveTRANS_VBLANK_A;

	u32 saveTRANS_VSYNC_A;

	u32 savePIPEASTAT;

	u32 saveDSPASTRIDE;

	u32 saveDSPASIZE;

	u32 saveDSPAPOS;

	u32 saveDSPAADDR;

	u32 saveDSPASURF;

	u32 saveDSPATILEOFF;

	u32 savePFIT_PGM_RATIOS;

	u32 saveBLC_HIST_CTL;

	u32 saveBLC_PWM_CTL;

	u32 saveBLC_PWM_CTL2;

	u32 saveBLC_CPU_PWM_CTL;

	u32 saveBLC_CPU_PWM_CTL2;

	u32 saveFPB0;

	u32 saveFPB1;

	u32 saveDPLL_B;

	u32 saveDPLL_B_MD;

	u32 saveHTOTAL_B;

	u32 saveHBLANK_B;

	u32 saveHSYNC_B;

	u32 saveVTOTAL_B;

	u32 saveVBLANK_B;

	u32 saveVSYNC_B;

	u32 saveBCLRPAT_B;

	u32 saveTRANSBCONF;

	u32 saveTRANS_HTOTAL_B;

	u32 saveTRANS_HBLANK_B;

	u32 saveTRANS_HSYNC_B;

	u32 saveTRANS_VTOTAL_B;

	u32 saveTRANS_VBLANK_B;

	u32 saveTRANS_VSYNC_B;

	u32 savePIPEBSTAT;

	u32 saveDSPBSTRIDE;

	u32 saveDSPBSIZE;

	u32 saveDSPBPOS;

	u32 saveDSPBADDR;

	u32 saveDSPBSURF;

	u32 saveDSPBTILEOFF;

	u32 saveVGA0;

	u32 saveVGA1;

	u32 saveVGA_PD;

	u32 saveVGACNTRL;

	u32 saveADPA;

	u32 saveLVDS;

	u32 savePP_ON_DELAYS;

	u32 savePP_OFF_DELAYS;

	u32 saveDVOA;

	u32 saveDVOB;

	u32 saveDVOC;

	u32 savePP_ON;

	u32 savePP_OFF;

	u32 savePP_CONTROL;

	u32 savePP_DIVISOR;

	u32 savePFIT_CONTROL;

	u32 save_palette_a[256];

	u32 save_palette_b[256];

	u32 saveDPFC_CB_BASE;

	u32 saveFBC_CFB_BASE;

	u32 saveFBC_LL_BASE;

	u32 saveFBC_CONTROL;

	u32 saveFBC_CONTROL2;

	u32 saveIER;

	u32 saveIIR;

	u32 saveIMR;

	u32 saveDEIER;

	u32 saveDEIMR;

	u32 saveGTIER;

	u32 saveGTIMR;

	u32 saveFDI_RXA_IMR;

	u32 saveFDI_RXB_IMR;

	u32 saveCACHE_MODE_0;

	u32 saveMI_ARB_STATE;

	u32 saveSWF0[16];

	u32 saveSWF1[16];

	u32 saveSWF2[3];

	u8 saveMSR;

	u8 saveSR[8];

	u8 saveGR[25];

	u8 saveAR_INDEX;

	u8 saveAR[21];

	u8 saveDACMASK;

	u8 saveCR[37];

	uint64_t saveFENCE[I915_MAX_NUM_FENCES];

	u32 saveCURACNTR;

	u32 saveCURAPOS;

	u32 saveCURABASE;

	u32 saveCURBCNTR;

	u32 saveCURBPOS;

	u32 saveCURBBASE;

	u32 saveCURSIZE;

	u32 saveDP_B;

	u32 saveDP_C;

	u32 saveDP_D;

	u32 savePIPEA_GMCH_DATA_M;

	u32 savePIPEB_GMCH_DATA_M;

	u32 savePIPEA_GMCH_DATA_N;

	u32 savePIPEB_GMCH_DATA_N;

	u32 savePIPEA_DP_LINK_M;

	u32 savePIPEB_DP_LINK_M;

	u32 savePIPEA_DP_LINK_N;

	u32 savePIPEB_DP_LINK_N;

	u32 saveFDI_RXA_CTL;

	u32 saveFDI_TXA_CTL;

	u32 saveFDI_RXB_CTL;

	u32 saveFDI_TXB_CTL;

	u32 savePFA_CTL_1;

	u32 savePFB_CTL_1;

	u32 savePFA_WIN_SZ;

	u32 savePFB_WIN_SZ;

	u32 savePFA_WIN_POS;

	u32 savePFB_WIN_POS;

	u32 savePCH_DREF_CONTROL;

	u32 saveDISP_ARB_CTL;

	u32 savePIPEA_DATA_M1;

	u32 savePIPEA_DATA_N1;

	u32 savePIPEA_LINK_M1;

	u32 savePIPEA_LINK_N1;

	u32 savePIPEB_DATA_M1;

	u32 savePIPEB_DATA_N1;

	u32 savePIPEB_LINK_M1;

	u32 savePIPEB_LINK_N1;

	u32 saveMCHBAR_RENDER_STANDBY;

	u32 savePCH_PORT_HOTPLUG;

	struct {

		/** Bridge to intel-gtt-ko */

		const struct intel_gtt *gtt;

		/** Memory allocator for GTT stolen memory */

        struct drm_mm stolen;

		/** Memory allocator for GTT */

        struct drm_mm gtt_space;

		/** List of all objects in gtt_space. Used to restore gtt

		 * mappings on resume */

		struct list_head bound_list;

		/**

		 * List of objects which are not bound to the GTT (thus

		 * are idle and not used by the GPU) but still have

		 * (presumably uncached) pages still attached.

		 */

		struct list_head unbound_list;

		/** Usable portion of the GTT for GEM */

		unsigned long gtt_start;

		unsigned long gtt_mappable_end;

		unsigned long gtt_end;

//       struct io_mapping *gtt_mapping;

		phys_addr_t gtt_base_addr;

		int gtt_mtrr;

		/** PPGTT used for aliasing the PPGTT with the GTT */

		struct i915_hw_ppgtt *aliasing_ppgtt;

		u32 *l3_remap_info;

//       struct shrinker inactive_shrinker;

		/**

		 * List of objects currently involved in rendering.

		 *

		 * Includes buffers having the contents of their GPU caches

		 * flushed, not necessarily primitives.  last_rendering_seqno

		 * represents when the rendering involved will be completed.

		 *

		 * A reference is held on the buffer while on this list.

		 */

		struct list_head active_list;

		/**

		 * LRU list of objects which are not in the ringbuffer and

		 * are ready to unbind, but are still in the GTT.

		 *

		 * last_rendering_seqno is 0 while an object is in this list.

		 *

		 * A reference is not held on the buffer while on this list,

		 * as merely being GTT-bound shouldn't prevent its being

		 * freed, and we'll pull it off the list in the free path.

		 */

		struct list_head inactive_list;

		/** LRU list of objects with fence regs on them. */

		struct list_head fence_list;

		/**

		 * We leave the user IRQ off as much as possible,

		 * but this means that requests will finish and never

		 * be retired once the system goes idle. Set a timer to

		 * fire periodically while the ring is running. When it

		 * fires, go retire requests.

		 */

		struct delayed_work retire_work;

		/**

		 * Are we in a non-interruptible section of code like

		 * modesetting?

		 */

		bool interruptible;

		/**

		 * Flag if the X Server, and thus DRM, is not currently in

		 * control of the device.

		 *

		 * This is set between LeaveVT and EnterVT.  It needs to be

		 * replaced with a semaphore.  It also needs to be

		 * transitioned away from for kernel modesetting.

		 */

		int suspended;

		/**

		 * Flag if the hardware appears to be wedged.

		 *

		 * This is set when attempts to idle the device timeout.

		 * It prevents command submission from occurring and makes

		 * every pending request fail

		 */

		atomic_t wedged;

		/** Bit 6 swizzling required for X tiling */

		uint32_t bit_6_swizzle_x;

		/** Bit 6 swizzling required for Y tiling */

		uint32_t bit_6_swizzle_y;

		/* storage for physical objects */

//       struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];

		/* accounting, useful for userland debugging */

		size_t gtt_total;

		size_t mappable_gtt_total;

		size_t object_memory;

		u32 object_count;

	} mm;

	/* Old dri1 support infrastructure, beware the dragons ya fools entering

	 * here! */

	struct {

		unsigned allow_batchbuffer : 1;

		u32 __iomem *gfx_hws_cpu_addr;

		unsigned int cpp;

		int back_offset;

		int front_offset;

		int current_page;

		int page_flipping;

	} dri1;

	/* Kernel Modesetting */

    struct sdvo_device_mapping sdvo_mappings[2];

	/* indicate whether the LVDS_BORDER should be enabled or not */

	unsigned int lvds_border_bits;

	/* Panel fitter placement and size for Ironlake+ */

	u32 pch_pf_pos, pch_pf_size;

    struct drm_crtc *plane_to_crtc_mapping[3];

    struct drm_crtc *pipe_to_crtc_mapping[3];

	wait_queue_head_t pending_flip_queue;

	struct intel_pch_pll pch_plls[I915_NUM_PLLS];

	/* Reclocking support */

	bool render_reclock_avail;

	bool lvds_downclock_avail;

	/* indicates the reduced downclock for LVDS*/

	int lvds_downclock;

	u16 orig_clock;

	int child_dev_num;

    struct child_device_config *child_dev;

    struct drm_connector *int_lvds_connector;

    struct drm_connector *int_edp_connector;

	bool mchbar_need_disable;

	/* gen6+ rps state */

	struct {

		struct work_struct work;

	u32 pm_iir;

		/* lock - irqsave spinlock that protectects the work_struct and

		 * pm_iir. */

		spinlock_t lock;

		/* The below variables an all the rps hw state are protected by

		 * dev->struct mutext. */

		u8 cur_delay;

		u8 min_delay;

		u8 max_delay;

	} rps;

	/* ilk-only ips/rps state. Everything in here is protected by the global

	 * mchdev_lock in intel_pm.c */

	struct {

	u8 cur_delay;

	u8 min_delay;

	u8 max_delay;

	u8 fmax;

	u8 fstart;

	u64 last_count1;

	unsigned long last_time1;

	unsigned long chipset_power;

	u64 last_count2;

    struct timespec last_time2;

	unsigned long gfx_power;

		u8 corr;

	int c_m;

	int r_t;

	} ips;

	enum no_fbc_reason no_fbc_reason;

	struct drm_mm_node *compressed_fb;

	struct drm_mm_node *compressed_llb;

	unsigned long last_gpu_reset;

	/* list of fbdev register on this device */

    struct intel_fbdev *fbdev;

//   struct backlight_device *backlight;

	struct drm_property *broadcast_rgb_property;

	struct drm_property *force_audio_property;

	bool hw_contexts_disabled;

	uint32_t hw_context_size;

} drm_i915_private_t;

/* Iterate over initialised rings */

#define for_each_ring(ring__, dev_priv__, i__) \

	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \

		if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))

enum hdmi_force_audio {

	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */

	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */

	HDMI_AUDIO_AUTO,		/* trust EDID */

	HDMI_AUDIO_ON,			/* force turn on HDMI audio */

};

enum i915_cache_level {

	I915_CACHE_NONE = 0,

	I915_CACHE_LLC,

	I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */

};

struct drm_i915_gem_object_ops {

	/* Interface between the GEM object and its backing storage.

	 * get_pages() is called once prior to the use of the associated set

	 * of pages before to binding them into the GTT, and put_pages() is

	 * called after we no longer need them. As we expect there to be

	 * associated cost with migrating pages between the backing storage

	 * and making them available for the GPU (e.g. clflush), we may hold

	 * onto the pages after they are no longer referenced by the GPU

	 * in case they may be used again shortly (for example migrating the

	 * pages to a different memory domain within the GTT). put_pages()

	 * will therefore most likely be called when the object itself is

	 * being released or under memory pressure (where we attempt to

	 * reap pages for the shrinker).

	 */

	int (*get_pages)(struct drm_i915_gem_object *);

	void (*put_pages)(struct drm_i915_gem_object *);

};

struct drm_i915_gem_object {

    struct drm_gem_object base;

	const struct drm_i915_gem_object_ops *ops;

    void  *mapped;

    /** Current space allocated to this object in the GTT, if any. */

    struct drm_mm_node *gtt_space;

    struct list_head gtt_list;

	/** This object's place on the active/inactive lists */

    struct list_head ring_list;

    struct list_head mm_list;

    /** This object's place in the batchbuffer or on the eviction list */

    struct list_head exec_list;

    /**

	 * This is set if the object is on the active lists (has pending

	 * rendering and so a non-zero seqno), and is not set if it i s on

	 * inactive (ready to be unbound) list.

     */

	unsigned int active:1;

    /**

     * This is set if the object has been written to since last bound

     * to the GTT

     */

	unsigned int dirty:1;

    /**

     * Fence register bits (if any) for this object.  Will be set

     * as needed when mapped into the GTT.

     * Protected by dev->struct_mutex.

     */

	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;

    /**

     * Advice: are the backing pages purgeable?

     */

	unsigned int madv:2;

    /**

     * Current tiling mode for the object.

     */

	unsigned int tiling_mode:2;

	/**

	 * Whether the tiling parameters for the currently associated fence

	 * register have changed. Note that for the purposes of tracking

	 * tiling changes we also treat the unfenced register, the register

	 * slot that the object occupies whilst it executes a fenced

	 * command (such as BLT on gen2/3), as a "fence".

	 */

	unsigned int fence_dirty:1;

    /** How many users have pinned this object in GTT space. The following

     * users can each hold at most one reference: pwrite/pread, pin_ioctl

     * (via user_pin_count), execbuffer (objects are not allowed multiple

     * times for the same batchbuffer), and the framebuffer code. When

     * switching/pageflipping, the framebuffer code has at most two buffers

     * pinned per crtc.

     *

     * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3

     * bits with absolutely no headroom. So use 4 bits. */

	unsigned int pin_count:4;

#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf

    /**

     * Is the object at the current location in the gtt mappable and

     * fenceable? Used to avoid costly recalculations.

     */

	unsigned int map_and_fenceable:1;

    /**

     * Whether the current gtt mapping needs to be mappable (and isn't just

     * mappable by accident). Track pin and fault separate for a more

     * accurate mappable working set.

     */

	unsigned int fault_mappable:1;

	unsigned int pin_mappable:1;

    /*

     * Is the GPU currently using a fence to access this buffer,

     */

    unsigned int pending_fenced_gpu_access:1;

    unsigned int fenced_gpu_access:1;

    unsigned int cache_level:2;

	unsigned int has_aliasing_ppgtt_mapping:1;

	unsigned int has_global_gtt_mapping:1;

	unsigned int has_dma_mapping:1;

    struct pagelist pages;

	int pages_pin_count;

	/* prime dma-buf support */

	void *dma_buf_vmapping;

	int vmapping_count;

    /**

     * Used for performing relocations during execbuffer insertion.

     */

    struct hlist_node exec_node;

    unsigned long exec_handle;

    struct drm_i915_gem_exec_object2 *exec_entry;

    /**

     * Current offset of the object in GTT space.

     *

     * This is the same as gtt_space->start

     */

    uint32_t gtt_offset;

	struct intel_ring_buffer *ring;

    /** Breadcrumb of last rendering to the buffer. */

	uint32_t last_read_seqno;

	uint32_t last_write_seqno;

    /** Breadcrumb of last fenced GPU access to the buffer. */

    uint32_t last_fenced_seqno;

    /** Current tiling stride for the object, if it's tiled. */

    uint32_t stride;

    /** Record of address bit 17 of each page at last unbind. */

    unsigned long *bit_17;

    /** User space pin count and filp owning the pin */

    uint32_t user_pin_count;

    struct drm_file *pin_filp;

    /** for phy allocated objects */

    struct drm_i915_gem_phys_object *phys_obj;

    /**

     * Number of crtcs where this object is currently the fb, but

     * will be page flipped away on the next vblank.  When it

     * reaches 0, dev_priv->pending_flip_queue will be woken up.

     */

    atomic_t pending_flip;

};

#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)

/**

 * Request queue structure.

 *

 * The request queue allows us to note sequence numbers that have been emitted

 * and may be associated with active buffers to be retired.

 *

 * By keeping this list, we can avoid having to do questionable

 * sequence-number comparisons on buffer last_rendering_seqnos, and associate

 * an emission time with seqnos for tracking how far ahead of the GPU we are.

 */

struct drm_i915_gem_request {

	/** On Which ring this request was generated */

	struct intel_ring_buffer *ring;

	/** GEM sequence number associated with this request. */

	uint32_t seqno;

	/** Postion in the ringbuffer of the end of the request */

	u32 tail;

	/** Time at which this request was emitted, in jiffies. */

	unsigned long emitted_jiffies;

	/** global list entry for this request */

	struct list_head list;

	struct drm_i915_file_private *file_priv;

	/** file_priv list entry for this request */

	struct list_head client_list;

};

struct drm_i915_file_private {