WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_drv.c

Rev	Author	Line No.	Line
2325	Serge	1	/* i915_drv.c -- i830,i845,i855,i865,i915 driver -- linux-c --
		2	*/
		3	/*
		4	*
		5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
		6	* All Rights Reserved.
		7	*
		8	* Permission is hereby granted, free of charge, to any person obtaining a
		9	* copy of this software and associated documentation files (the
		10	* "Software"), to deal in the Software without restriction, including
		11	* without limitation the rights to use, copy, modify, merge, publish,
		12	* distribute, sub license, and/or sell copies of the Software, and to
		13	* permit persons to whom the Software is furnished to do so, subject to
		14	* the following conditions:
		15	*
		16	* The above copyright notice and this permission notice (including the
		17	* next paragraph) shall be included in all copies or substantial portions
		18	* of the Software.
		19	*
		20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
		21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
		23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
		24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
		25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
		26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		27	*
		28	*/
		29
2330	Serge	30	//#include
3031	serge	31	#include
		32	#include
2330	Serge	33	#include "i915_drv.h"
		34	#include "intel_drv.h"
2325	Serge	35
		36	#include
		37	#include
		38	#include
		39	#include
		40	#include
		41
3031	serge	42	#include
		43
2325	Serge	44	#include
		45
2330	Serge	46	#define __read_mostly
2327	Serge	47
2338	Serge	48	int init_display_kms(struct drm_device *dev);
2330	Serge	49
2340	Serge	50	struct drm_device *main_device;
2338	Serge	51
3255	Serge	52	struct drm_file *drm_file_handlers[256];
		53
3031	serge	54	static int i915_modeset __read_mostly = 1;
3480	Serge	55	module_param_named(modeset, i915_modeset, int, 0400);
3031	serge	56	MODULE_PARM_DESC(modeset,
		57	"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
		58	"1=on, -1=force vga console preference [default])");
		59
3746	Serge	60	unsigned int i915_fbpercrtc __always_unused = 0;
		61	module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
3031	serge	62
3480	Serge	63	int i915_panel_ignore_lid __read_mostly = 1;
		64	module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
3031	serge	65	MODULE_PARM_DESC(panel_ignore_lid,
3480	Serge	66	"Override lid status (0=autodetect, 1=autodetect disabled [default], "
		67	"-1=force lid closed, -2=force lid open)");
2330	Serge	68
3482	Serge	69	unsigned int i915_powersave __read_mostly = 1;
3480	Serge	70	module_param_named(powersave, i915_powersave, int, 0600);
3031	serge	71	MODULE_PARM_DESC(powersave,
		72	"Enable powersavings, fbc, downclocking, etc. (default: true)");
2330	Serge	73
3031	serge	74	int i915_semaphores __read_mostly = -1;
3480	Serge	75	module_param_named(semaphores, i915_semaphores, int, 0600);
3031	serge	76	MODULE_PARM_DESC(semaphores,
		77	"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
2330	Serge	78
3482	Serge	79	int i915_enable_rc6 __read_mostly = -1;
3480	Serge	80	module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
3031	serge	81	MODULE_PARM_DESC(i915_enable_rc6,
		82	"Enable power-saving render C-state 6. "
		83	"Different stages can be selected via bitmask values "
		84	"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
		85	"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
		86	"default: -1 (use per-chip default)");
		87
3482	Serge	88	int i915_enable_fbc __read_mostly = -1;
3480	Serge	89	module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
3031	serge	90	MODULE_PARM_DESC(i915_enable_fbc,
		91	"Enable frame buffer compression for power savings "
		92	"(default: -1 (use per-chip default))");
		93
2330	Serge	94	unsigned int i915_lvds_downclock __read_mostly = 0;
3480	Serge	95	module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
3031	serge	96	MODULE_PARM_DESC(lvds_downclock,
		97	"Use panel (LVDS/eDP) downclocking for power savings "
		98	"(default: false)");
2330	Serge	99
3031	serge	100	int i915_lvds_channel_mode __read_mostly;
3480	Serge	101	module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
3031	serge	102	MODULE_PARM_DESC(lvds_channel_mode,
		103	"Specify LVDS channel mode "
		104	"(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
2330	Serge	105
3031	serge	106	int i915_panel_use_ssc __read_mostly = -1;
3480	Serge	107	module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
3031	serge	108	MODULE_PARM_DESC(lvds_use_ssc,
		109	"Use Spread Spectrum Clock with panels [LVDS/eDP] "
		110	"(default: auto from VBT)");
		111
2332	Serge	112	int i915_vbt_sdvo_panel_type __read_mostly = -1;
3480	Serge	113	module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
3031	serge	114	MODULE_PARM_DESC(vbt_sdvo_panel_type,
		115	"Override/Ignore selection of SDVO panel mode in the VBT "
		116	"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
2330	Serge	117
3031	serge	118	static bool i915_try_reset __read_mostly = true;
3480	Serge	119	module_param_named(reset, i915_try_reset, bool, 0600);
3031	serge	120	MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
		121
		122	bool i915_enable_hangcheck __read_mostly = false;
3480	Serge	123	module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
3031	serge	124	MODULE_PARM_DESC(enable_hangcheck,
		125	"Periodically check GPU activity for detecting hangs. "
		126	"WARNING: Disabling this can cause system wide hangs. "
		127	"(default: true)");
		128
3746	Serge	129	int i915_enable_ppgtt __read_mostly = 0;
3480	Serge	130	module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
3031	serge	131	MODULE_PARM_DESC(i915_enable_ppgtt,
		132	"Enable PPGTT (default: true)");
		133
		134	unsigned int i915_preliminary_hw_support __read_mostly = true;
3480	Serge	135	module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
3031	serge	136	MODULE_PARM_DESC(preliminary_hw_support,
3746	Serge	137	"Enable preliminary hardware support. (default: false)");
3031	serge	138
3482	Serge	139	int i915_disable_power_well __read_mostly = 0;
		140	module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
		141	MODULE_PARM_DESC(disable_power_well,
		142	"Disable the power well when possible (default: false)");
3031	serge	143
2326	Serge	144	#define PCI_VENDOR_ID_INTEL 0x8086
		145
2325	Serge	146	#define INTEL_VGA_DEVICE(id, info) { \
2342	Serge	147	.class = PCI_BASE_CLASS_DISPLAY << 16, \
2325	Serge	148	.class_mask = 0xff0000, \
		149	.vendor = 0x8086, \
		150	.device = id, \
		151	.subvendor = PCI_ANY_ID, \
		152	.subdevice = PCI_ANY_ID, \
		153	.driver_data = (unsigned long) info }
		154
3746	Serge	155	#define INTEL_QUANTA_VGA_DEVICE(info) { \
		156	.class = PCI_BASE_CLASS_DISPLAY << 16, \
		157	.class_mask = 0xff0000, \
		158	.vendor = 0x8086, \
		159	.device = 0x16a, \
		160	.subvendor = 0x152d, \
		161	.subdevice = 0x8990, \
		162	.driver_data = (unsigned long) info }
2339	Serge	163
		164	static const struct intel_device_info intel_i915g_info = {
3746	Serge	165	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
2339	Serge	166	.has_overlay = 1, .overlay_needs_physical = 1,
		167	};
		168	static const struct intel_device_info intel_i915gm_info = {
3746	Serge	169	.gen = 3, .is_mobile = 1, .num_pipes = 2,
2339	Serge	170	.cursor_needs_physical = 1,
		171	.has_overlay = 1, .overlay_needs_physical = 1,
		172	.supports_tv = 1,
		173	};
		174	static const struct intel_device_info intel_i945g_info = {
3746	Serge	175	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
2339	Serge	176	.has_overlay = 1, .overlay_needs_physical = 1,
		177	};
		178	static const struct intel_device_info intel_i945gm_info = {
3746	Serge	179	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
2339	Serge	180	.has_hotplug = 1, .cursor_needs_physical = 1,
		181	.has_overlay = 1, .overlay_needs_physical = 1,
		182	.supports_tv = 1,
		183	};
		184
		185	static const struct intel_device_info intel_i965g_info = {
3746	Serge	186	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
2339	Serge	187	.has_hotplug = 1,
		188	.has_overlay = 1,
		189	};
		190
		191	static const struct intel_device_info intel_i965gm_info = {
3746	Serge	192	.gen = 4, .is_crestline = 1, .num_pipes = 2,
2339	Serge	193	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
		194	.has_overlay = 1,
		195	.supports_tv = 1,
		196	};
		197
		198	static const struct intel_device_info intel_g33_info = {
3746	Serge	199	.gen = 3, .is_g33 = 1, .num_pipes = 2,
2339	Serge	200	.need_gfx_hws = 1, .has_hotplug = 1,
		201	.has_overlay = 1,
		202	};
		203
		204	static const struct intel_device_info intel_g45_info = {
3746	Serge	205	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
2339	Serge	206	.has_pipe_cxsr = 1, .has_hotplug = 1,
		207	.has_bsd_ring = 1,
		208	};
		209
		210	static const struct intel_device_info intel_gm45_info = {
3746	Serge	211	.gen = 4, .is_g4x = 1, .num_pipes = 2,
2339	Serge	212	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
		213	.has_pipe_cxsr = 1, .has_hotplug = 1,
		214	.supports_tv = 1,
		215	.has_bsd_ring = 1,
		216	};
		217
		218	static const struct intel_device_info intel_pineview_info = {
3746	Serge	219	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
2339	Serge	220	.need_gfx_hws = 1, .has_hotplug = 1,
		221	.has_overlay = 1,
		222	};
		223
		224	static const struct intel_device_info intel_ironlake_d_info = {
3746	Serge	225	.gen = 5, .num_pipes = 2,
3031	serge	226	.need_gfx_hws = 1, .has_hotplug = 1,
2339	Serge	227	.has_bsd_ring = 1,
		228	};
		229
		230	static const struct intel_device_info intel_ironlake_m_info = {
3746	Serge	231	.gen = 5, .is_mobile = 1, .num_pipes = 2,
2339	Serge	232	.need_gfx_hws = 1, .has_hotplug = 1,
		233	.has_fbc = 1,
		234	.has_bsd_ring = 1,
		235	};
		236
2325	Serge	237	static const struct intel_device_info intel_sandybridge_d_info = {
3746	Serge	238	.gen = 6, .num_pipes = 2,
2330	Serge	239	.need_gfx_hws = 1, .has_hotplug = 1,
2325	Serge	240	.has_bsd_ring = 1,
		241	.has_blt_ring = 1,
3031	serge	242	.has_llc = 1,
		243	.has_force_wake = 1,
2325	Serge	244	};
		245
		246	static const struct intel_device_info intel_sandybridge_m_info = {
3746	Serge	247	.gen = 6, .is_mobile = 1, .num_pipes = 2,
2330	Serge	248	.need_gfx_hws = 1, .has_hotplug = 1,
2325	Serge	249	.has_fbc = 1,
		250	.has_bsd_ring = 1,
		251	.has_blt_ring = 1,
3031	serge	252	.has_llc = 1,
		253	.has_force_wake = 1,
2325	Serge	254	};
		255
3746	Serge	256	#define GEN7_FEATURES \
		257	.gen = 7, .num_pipes = 3, \
		258	.need_gfx_hws = 1, .has_hotplug = 1, \
		259	.has_bsd_ring = 1, \
		260	.has_blt_ring = 1, \
		261	.has_llc = 1, \
		262	.has_force_wake = 1
		263
2339	Serge	264	static const struct intel_device_info intel_ivybridge_d_info = {
3746	Serge	265	GEN7_FEATURES,
		266	.is_ivybridge = 1,
2339	Serge	267	};
2325	Serge	268
2339	Serge	269	static const struct intel_device_info intel_ivybridge_m_info = {
3746	Serge	270	GEN7_FEATURES,
		271	.is_ivybridge = 1,
		272	.is_mobile = 1,
2339	Serge	273	};
		274
3746	Serge	275	static const struct intel_device_info intel_ivybridge_q_info = {
		276	GEN7_FEATURES,
		277	.is_ivybridge = 1,
		278	.num_pipes = 0, /* legal, last one wins */
		279	};
		280
3031	serge	281	static const struct intel_device_info intel_valleyview_m_info = {
3746	Serge	282	GEN7_FEATURES,
		283	.is_mobile = 1,
		284	.num_pipes = 2,
3031	serge	285	.is_valleyview = 1,
3480	Serge	286	.display_mmio_offset = VLV_DISPLAY_BASE,
3746	Serge	287	.has_llc = 0, /* legal, last one wins */
3031	serge	288	};
		289
		290	static const struct intel_device_info intel_valleyview_d_info = {
3746	Serge	291	GEN7_FEATURES,
		292	.num_pipes = 2,
3031	serge	293	.is_valleyview = 1,
3480	Serge	294	.display_mmio_offset = VLV_DISPLAY_BASE,
3746	Serge	295	.has_llc = 0, /* legal, last one wins */
3031	serge	296	};
		297
		298	static const struct intel_device_info intel_haswell_d_info = {
3746	Serge	299	GEN7_FEATURES,
		300	.is_haswell = 1,
3031	serge	301	};
		302
		303	static const struct intel_device_info intel_haswell_m_info = {
3746	Serge	304	GEN7_FEATURES,
		305	.is_haswell = 1,
		306	.is_mobile = 1,
3031	serge	307	};
		308
2325	Serge	309	static const struct pci_device_id pciidlist[] = { /* aka */
2339	Serge	310	INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
		311	INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
		312	INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
		313	INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
		314	INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
		315	INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
		316	INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
		317	INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
		318	INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
		319	INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
		320	INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
		321	INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
		322	INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
		323	INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
		324	INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
		325	INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
		326	INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
		327	INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
		328	INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
		329	INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
		330	INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
		331	INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
		332	INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
		333	INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
		334	INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
		335	INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
2325	Serge	336	INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
		337	INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
		338	INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
		339	INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
		340	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
		341	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
		342	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
2339	Serge	343	INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
		344	INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
		345	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
		346	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
		347	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
3746	Serge	348	INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
3031	serge	349	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
		350	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
		351	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
3746	Serge	352	INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
3031	serge	353	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
		354	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
3746	Serge	355	INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
3031	serge	356	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
		357	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
		358	INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
3746	Serge	359	INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
		360	INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
		361	INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
		362	INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
		363	INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
		364	INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
3031	serge	365	INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
		366	INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
3746	Serge	367	INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
3031	serge	368	INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
		369	INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
3746	Serge	370	INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
3031	serge	371	INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
		372	INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
3746	Serge	373	INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
		374	INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
		375	INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
		376	INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
		377	INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
		378	INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
		379	INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
3031	serge	380	INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
		381	INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
3746	Serge	382	INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
3031	serge	383	INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
		384	INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
3746	Serge	385	INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
3031	serge	386	INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
		387	INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
3746	Serge	388	INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
		389	INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
		390	INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
		391	INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
		392	INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
		393	INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
		394	INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
3480	Serge	395	INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
		396	INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
3746	Serge	397	INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
3480	Serge	398	INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
		399	INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
3746	Serge	400	INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
3480	Serge	401	INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
		402	INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
3746	Serge	403	INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
		404	INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
		405	INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
		406	INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
		407	INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
		408	INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
		409	INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
3031	serge	410	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
3746	Serge	411	INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
		412	INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
		413	INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
3031	serge	414	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
		415	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
2325	Serge	416	{0, 0, 0}
		417	};
		418
2326	Serge	419	#define INTEL_PCH_DEVICE_ID_MASK 0xff00
		420	#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
		421	#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
		422	#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3031	serge	423	#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2325	Serge	424
2342	Serge	425	void intel_detect_pch(struct drm_device *dev)
2326	Serge	426	{
		427	struct drm_i915_private *dev_priv = dev->dev_private;
		428	struct pci_dev *pch;
		429
3746	Serge	430	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
		431	* (which really amounts to a PCH but no South Display).
		432	*/
		433	if (INTEL_INFO(dev)->num_pipes == 0) {
		434	dev_priv->pch_type = PCH_NOP;
		435	dev_priv->num_pch_pll = 0;
		436	return;
		437	}
		438
2326	Serge	439	/*
		440	* The reason to probe ISA bridge instead of Dev31:Fun0 is to
		441	* make graphics device passthrough work easy for VMM, that only
		442	* need to expose ISA bridge to let driver know the real hardware
		443	* underneath. This is a requirement from virtualization team.
		444	*/
		445	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
		446	if (pch) {
		447	if (pch->vendor == PCI_VENDOR_ID_INTEL) {
3243	Serge	448	unsigned short id;
2326	Serge	449	id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
3243	Serge	450	dev_priv->pch_id = id;
2326	Serge	451
		452	if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
		453	dev_priv->pch_type = PCH_IBX;
3031	serge	454	dev_priv->num_pch_pll = 2;
2326	Serge	455	DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
3243	Serge	456	WARN_ON(!IS_GEN5(dev));
2326	Serge	457	} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
		458	dev_priv->pch_type = PCH_CPT;
3031	serge	459	dev_priv->num_pch_pll = 2;
2326	Serge	460	DRM_DEBUG_KMS("Found CougarPoint PCH\n");
3243	Serge	461	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));
2326	Serge	462	} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
		463	/* PantherPoint is CPT compatible */
		464	dev_priv->pch_type = PCH_CPT;
3031	serge	465	dev_priv->num_pch_pll = 2;
2326	Serge	466	DRM_DEBUG_KMS("Found PatherPoint PCH\n");
3243	Serge	467	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));
3031	serge	468	} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		469	dev_priv->pch_type = PCH_LPT;
		470	dev_priv->num_pch_pll = 0;
		471	DRM_DEBUG_KMS("Found LynxPoint PCH\n");
3243	Serge	472	WARN_ON(!IS_HASWELL(dev));
3746	Serge	473	WARN_ON(IS_ULT(dev));
3243	Serge	474	} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		475	dev_priv->pch_type = PCH_LPT;
		476	dev_priv->num_pch_pll = 0;
		477	DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
		478	WARN_ON(!IS_HASWELL(dev));
3746	Serge	479	WARN_ON(!IS_ULT(dev));
2326	Serge	480	}
3031	serge	481	BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
2326	Serge	482	}
		483	}
		484	}
		485
3031	serge	486	bool i915_semaphore_is_enabled(struct drm_device *dev)
2326	Serge	487	{
3031	serge	488	if (INTEL_INFO(dev)->gen < 6)
		489	return 0;
2326	Serge	490
3031	serge	491	if (i915_semaphores >= 0)
		492	return i915_semaphores;
2326	Serge	493
3031	serge	494	#ifdef CONFIG_INTEL_IOMMU
		495	/* Enable semaphores on SNB when IO remapping is off */
		496	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
		497	return false;
		498	#endif
2326	Serge	499
3031	serge	500	return 1;
2326	Serge	501	}
		502
2342	Serge	503
		504
		505
		506
2325	Serge	507	int drm_get_dev(struct pci_dev pdev, const struct pci_device_id ent);
		508
		509	int i915_init(void)
		510	{
		511	static pci_dev_t device;
		512	const struct pci_device_id *ent;
		513	int err;
		514
		515	ent = find_pci_device(&device, pciidlist);
		516	if( unlikely(ent == NULL) )
		517	{
		518	dbgprintf("device not found\n");
3480	Serge	519	return -ENODEV;
2325	Serge	520	};
		521
3031	serge	522	struct intel_device_info *intel_info =
		523	(struct intel_device_info *) ent->driver_data;
		524
3243	Serge	525	if (intel_info->is_valleyview)
3031	serge	526	if(!i915_preliminary_hw_support) {
		527	DRM_ERROR("Preliminary hardware support disabled\n");
		528	return -ENODEV;
		529	}
		530
3037	serge	531	DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
2325	Serge	532	device.pci_dev.device);
		533
3031	serge	534	if (intel_info->gen != 3) {
		535
		536	} else if (init_agp() != 0) {
		537	DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
		538	return -ENODEV;
		539	}
		540
2325	Serge	541	err = drm_get_dev(&device.pci_dev, ent);
		542
		543	return err;
		544	}
		545
3260	Serge	546
		547
		548	static struct drm_driver driver = {
		549	/* Don't use MTRRs here; the Xserver or userspace app should
		550	* deal with them for Intel hardware.
		551	*/
3482	Serge	552	.driver_features =
		553	DRIVER_USE_AGP \| DRIVER_REQUIRE_AGP \| /* DRIVER_USE_MTRR \|*/
		554	DRIVER_HAVE_IRQ \| DRIVER_IRQ_SHARED \| DRIVER_GEM \| DRIVER_MODESET,
3260	Serge	555	// .load = i915_driver_load,
		556	// .unload = i915_driver_unload,
3263	Serge	557	.open = i915_driver_open,
3260	Serge	558	// .lastclose = i915_driver_lastclose,
		559	// .preclose = i915_driver_preclose,
		560	// .postclose = i915_driver_postclose,
		561
		562	/* Used in place of i915_pm_ops for non-DRIVER_MODESET */
		563	// .suspend = i915_suspend,
		564	// .resume = i915_resume,
		565
		566	// .device_is_agp = i915_driver_device_is_agp,
		567	// .master_create = i915_master_create,
		568	// .master_destroy = i915_master_destroy,
		569	.gem_init_object = i915_gem_init_object,
		570	.gem_free_object = i915_gem_free_object,
		571	// .gem_vm_ops = &i915_gem_vm_ops,
		572
		573	// .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
		574	// .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
		575	// .gem_prime_export = i915_gem_prime_export,
		576	// .gem_prime_import = i915_gem_prime_import,
		577
		578	// .dumb_create = i915_gem_dumb_create,
		579	// .dumb_map_offset = i915_gem_mmap_gtt,
		580	// .dumb_destroy = i915_gem_dumb_destroy,
		581	// .ioctls = i915_ioctls,
		582	// .fops = &i915_driver_fops,
		583	// .name = DRIVER_NAME,
		584	// .desc = DRIVER_DESC,
		585	// .date = DRIVER_DATE,
		586	// .major = DRIVER_MAJOR,
		587	// .minor = DRIVER_MINOR,
		588	// .patchlevel = DRIVER_PATCHLEVEL,
		589	};
		590
		591
2325	Serge	592	int drm_get_dev(struct pci_dev pdev, const struct pci_device_id ent)
		593	{
3255	Serge	594	static struct drm_device drm_dev;
		595	static struct drm_file drm_file;
3243	Serge	596
3255	Serge	597	struct drm_device *dev;
		598	struct drm_file *priv;
		599
2325	Serge	600	int ret;
		601
3255	Serge	602	dev = &drm_dev;
		603	priv = &drm_file;
2325	Serge	604
3255	Serge	605	drm_file_handlers[0] = priv;
		606
2325	Serge	607	// ret = pci_enable_device(pdev);
		608	// if (ret)
		609	// goto err_g1;
		610
3031	serge	611	pci_set_master(pdev);
2325	Serge	612
		613	// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
		614	// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
		615	// goto err_g2;
		616	// }
		617
		618	dev->pdev = pdev;
		619	dev->pci_device = pdev->device;
		620	dev->pci_vendor = pdev->vendor;
		621
		622	INIT_LIST_HEAD(&dev->filelist);
		623	INIT_LIST_HEAD(&dev->ctxlist);
		624	INIT_LIST_HEAD(&dev->vmalist);
		625	INIT_LIST_HEAD(&dev->maplist);
		626
		627	spin_lock_init(&dev->count_lock);
		628	mutex_init(&dev->struct_mutex);
		629	mutex_init(&dev->ctxlist_mutex);
		630
3255	Serge	631	INIT_LIST_HEAD(&priv->lhead);
		632	INIT_LIST_HEAD(&priv->fbs);
		633	INIT_LIST_HEAD(&priv->event_list);
		634	init_waitqueue_head(&priv->event_wait);
		635	priv->event_space = 4096; /* set aside 4k for event buffer */
		636
		637	idr_init(&priv->object_idr);
		638	spin_lock_init(&priv->table_lock);
		639
3243	Serge	640	dev->driver = &driver;
		641
3263	Serge	642	if (dev->driver->open) {
		643	ret = dev->driver->open(dev, priv);
		644	if (ret < 0)
		645	goto err_g4;
		646	}
		647
2336	Serge	648	ret = i915_driver_load(dev, ent->driver_data );
2325	Serge	649
2338	Serge	650	if (ret)
		651	goto err_g4;
2330	Serge	652
2338	Serge	653	ret = init_display_kms(dev);
2336	Serge	654
2338	Serge	655	if (ret)
		656	goto err_g4;
2336	Serge	657
2325	Serge	658	return 0;
		659
		660	err_g4:
		661	//err_g3:
		662	// if (drm_core_check_feature(dev, DRIVER_MODESET))
		663	// drm_put_minor(&dev->control);
		664	//err_g2:
		665	// pci_disable_device(pdev);
		666	//err_g1:
		667
		668	return ret;
		669	}
		670
3031	serge	671	/* We give fast paths for the really cool registers */
		672	#define NEEDS_FORCE_WAKE(dev_priv, reg) \
		673	((HAS_FORCE_WAKE((dev_priv)->dev)) && \
		674	((reg) < 0x40000) && \
		675	((reg) != FORCEWAKE))
2325	Serge	676
3031	serge	677	static bool IS_DISPLAYREG(u32 reg)
		678	{
		679	/*
		680	* This should make it easier to transition modules over to the
		681	* new register block scheme, since we can do it incrementally.
		682	*/
		683	if (reg >= VLV_DISPLAY_BASE)
		684	return false;
		685
		686	if (reg >= RENDER_RING_BASE &&
		687	reg < RENDER_RING_BASE + 0xff)
		688	return false;
		689	if (reg >= GEN6_BSD_RING_BASE &&
		690	reg < GEN6_BSD_RING_BASE + 0xff)
		691	return false;
		692	if (reg >= BLT_RING_BASE &&
		693	reg < BLT_RING_BASE + 0xff)
		694	return false;
		695
		696	if (reg == PGTBL_ER)
		697	return false;
		698
		699	if (reg >= IPEIR_I965 &&
		700	reg < HWSTAM)
		701	return false;
		702
		703	if (reg == MI_MODE)
		704	return false;
		705
		706	if (reg == GFX_MODE_GEN7)
		707	return false;
		708
		709	if (reg == RENDER_HWS_PGA_GEN7 \|\|
		710	reg == BSD_HWS_PGA_GEN7 \|\|
		711	reg == BLT_HWS_PGA_GEN7)
		712	return false;
		713
		714	if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL \|\|
		715	reg == GEN6_BSD_RNCID)
		716	return false;
		717
		718	if (reg == GEN6_BLITTER_ECOSKPD)
		719	return false;
		720
		721	if (reg >= 0x4000c &&
		722	reg <= 0x4002c)
		723	return false;
		724
		725	if (reg >= 0x4f000 &&
		726	reg <= 0x4f08f)
		727	return false;
		728
		729	if (reg >= 0x4f100 &&
		730	reg <= 0x4f11f)
		731	return false;
		732
		733	if (reg >= VLV_MASTER_IER &&
		734	reg <= GEN6_PMIER)
		735	return false;
		736
		737	if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
		738	reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
		739	return false;
		740
		741	if (reg >= VLV_IIR_RW &&
		742	reg <= VLV_ISR)
		743	return false;
		744
		745	if (reg == FORCEWAKE_VLV \|\|
		746	reg == FORCEWAKE_ACK_VLV)
		747	return false;
		748
		749	if (reg == GEN6_GDRST)
		750	return false;
		751
3243	Serge	752	switch (reg) {
		753	case _3D_CHICKEN3:
		754	case IVB_CHICKEN3:
		755	case GEN7_COMMON_SLICE_CHICKEN1:
		756	case GEN7_L3CNTLREG1:
		757	case GEN7_L3_CHICKEN_MODE_REGISTER:
		758	case GEN7_ROW_CHICKEN2:
		759	case GEN7_L3SQCREG4:
		760	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
		761	case GEN7_HALF_SLICE_CHICKEN1:
		762	case GEN6_MBCTL:
		763	case GEN6_UCGCTL2:
		764	return false;
		765	default:
		766	break;
		767	}
		768
3031	serge	769	return true;
		770	}
		771
3746	Serge	772	/* We give fast paths for the really cool registers */
		773	#define NEEDS_FORCE_WAKE(dev_priv, reg) \
		774	((HAS_FORCE_WAKE((dev_priv)->dev)) && \
		775	((reg) < 0x40000) && \
		776	((reg) != FORCEWAKE))
3243	Serge	777	static void
		778	ilk_dummy_write(struct drm_i915_private *dev_priv)
		779	{
		780	/* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
		781	* chip from rc6 before touching it for real. MI_MODE is masked, hence
		782	* harmless to write 0 into. */
		783	I915_WRITE_NOTRACE(MI_MODE, 0);
		784	}
		785
3746	Serge	786	static void
		787	hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
		788	{
		789	if (IS_HASWELL(dev_priv->dev) &&
		790	(I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
		791	DRM_ERROR("Unknown unclaimed register before writing to %x\n",
		792	reg);
		793	I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
		794	}
		795	}
		796
		797	static void
		798	hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
		799	{
		800	if (IS_HASWELL(dev_priv->dev) &&
		801	(I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
		802	DRM_ERROR("Unclaimed write to %x\n", reg);
		803	I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
		804	}
		805	}
		806
2342	Serge	807	#define __i915_read(x, y) \
		808	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
		809	u##x val = 0; \
3243	Serge	810	if (IS_GEN5(dev_priv->dev)) \
		811	ilk_dummy_write(dev_priv); \
2342	Serge	812	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
		813	unsigned long irqflags; \
		814	spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
		815	if (dev_priv->forcewake_count == 0) \
3031	serge	816	dev_priv->gt.force_wake_get(dev_priv); \
2342	Serge	817	val = read##y(dev_priv->regs + reg); \
		818	if (dev_priv->forcewake_count == 0) \
3031	serge	819	dev_priv->gt.force_wake_put(dev_priv); \
2342	Serge	820	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
		821	} else { \
		822	val = read##y(dev_priv->regs + reg); \
		823	} \
		824	return val; \
		825	}
		826
		827	__i915_read(8, b)
		828	__i915_read(16, w)
		829	__i915_read(32, l)
		830	__i915_read(64, q)
		831	#undef __i915_read
		832
		833	#define __i915_write(x, y) \
		834	void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
3120	serge	835	u32 __fifo_ret = 0; \
		836	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
2342	Serge	837	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
3120	serge	838	__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
2342	Serge	839	} \
3243	Serge	840	if (IS_GEN5(dev_priv->dev)) \
		841	ilk_dummy_write(dev_priv); \
3746	Serge	842	hsw_unclaimed_reg_clear(dev_priv, reg); \
2342	Serge	843	write##y(val, dev_priv->regs + reg); \
3120	serge	844	if (unlikely(__fifo_ret)) { \
		845	gen6_gt_check_fifodbg(dev_priv); \
		846	} \
3746	Serge	847	hsw_unclaimed_reg_check(dev_priv, reg); \
2342	Serge	848	}
		849	__i915_write(8, b)
		850	__i915_write(16, w)
		851	__i915_write(32, l)
		852	__i915_write(64, q)
		853	#undef __i915_write

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(root)/drivers/video/drm/i915/i915_drv.c – Rev 3746