WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_dma.c

Rev	Author	Line No.	Line
2326	Serge	1	/* i915_dma.c -- DMA support for the I915 -- linux-c --
		2	*/
		3	/*
		4	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
		5	* All Rights Reserved.
		6	*
		7	* Permission is hereby granted, free of charge, to any person obtaining a
		8	* copy of this software and associated documentation files (the
		9	* "Software"), to deal in the Software without restriction, including
		10	* without limitation the rights to use, copy, modify, merge, publish,
		11	* distribute, sub license, and/or sell copies of the Software, and to
		12	* permit persons to whom the Software is furnished to do so, subject to
		13	* the following conditions:
		14	*
		15	* The above copyright notice and this permission notice (including the
		16	* next paragraph) shall be included in all copies or substantial portions
		17	* of the Software.
		18	*
		19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
		20	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		21	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
		22	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
		23	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
		24	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
		25	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		26	*
		27	*/
		28
3031	serge	29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
		30
		31	#include
		32	#include
		33	#include
2326	Serge	34	#include "intel_drv.h"
3031	serge	35	#include
2326	Serge	36	#include "i915_drv.h"
2351	Serge	37	#include "i915_trace.h"
2326	Serge	38	#include
		39	//#include
		40	//#include
		41	//#include
		42	//#include
2330	Serge	43	#include
2326	Serge	44	//#include
		45
		46	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long maxlen);
		47
3031	serge	48
		49	#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
		50
		51	#define BEGIN_LP_RING(n) \
		52	intel_ring_begin(LP_RING(dev_priv), (n))
		53
		54	#define OUT_RING(x) \
		55	intel_ring_emit(LP_RING(dev_priv), x)
		56
		57	#define ADVANCE_LP_RING() \
		58	intel_ring_advance(LP_RING(dev_priv))
		59
		60	/**
		61	* Lock test for when it's just for synchronization of ring access.
		62	*
		63	* In that case, we don't need to do it when GEM is initialized as nobody else
		64	* has access to the ring.
		65	*/
		66	#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
		67	if (LP_RING(dev->dev_private)->obj == NULL) \
		68	LOCK_TEST_WITH_RETURN(dev, file); \
		69	} while (0)
		70
		71	static inline u32
		72	intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
2330	Serge	73	{
3031	serge	74	if (I915_NEED_GFX_HWS(dev_priv->dev))
		75	return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
		76	else
		77	return intel_read_status_page(LP_RING(dev_priv), reg);
2330	Serge	78	}
		79
3031	serge	80	#define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
		81	#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
		82	#define I915_BREADCRUMB_INDEX 0x21
2330	Serge	83
3031	serge	84	void i915_update_dri1_breadcrumb(struct drm_device *dev)
		85	{
		86	drm_i915_private_t *dev_priv = dev->dev_private;
		87	struct drm_i915_master_private *master_priv;
2330	Serge	88
3031	serge	89	if (dev->primary->master) {
		90	master_priv = dev->primary->master->driver_priv;
		91	if (master_priv->sarea_priv)
		92	master_priv->sarea_priv->last_dispatch =
		93	READ_BREADCRUMB(dev_priv);
		94	}
		95	}
		96
2326	Serge	97	static void i915_write_hws_pga(struct drm_device *dev)
		98	{
3031	serge	99	drm_i915_private_t *dev_priv = dev->dev_private;
		100	u32 addr;
2326	Serge	101
3031	serge	102	addr = dev_priv->status_page_dmah->busaddr;
		103	if (INTEL_INFO(dev)->gen >= 4)
		104	addr \|= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
		105	I915_WRITE(HWS_PGA, addr);
2326	Serge	106	}
		107
		108	/**
3031	serge	109	* Frees the hardware status page, whether it's a physical address or a virtual
		110	* address set up by the X Server.
		111	*/
		112	static void i915_free_hws(struct drm_device *dev)
		113	{
		114	drm_i915_private_t *dev_priv = dev->dev_private;
		115	struct intel_ring_buffer *ring = LP_RING(dev_priv);
2330	Serge	116
3031	serge	117	if (dev_priv->status_page_dmah) {
		118	drm_pci_free(dev, dev_priv->status_page_dmah);
		119	dev_priv->status_page_dmah = NULL;
		120	}
2330	Serge	121
3031	serge	122	if (ring->status_page.gfx_addr) {
		123	ring->status_page.gfx_addr = 0;
		124	iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
		125	}
2330	Serge	126
3031	serge	127	/* Need to rewrite hardware status page */
		128	I915_WRITE(HWS_PGA, 0x1ffff000);
		129	}
2330	Serge	130
3031	serge	131	#if 0
2330	Serge	132
3031	serge	133	void i915_kernel_lost_context(struct drm_device * dev)
		134	{
		135	drm_i915_private_t *dev_priv = dev->dev_private;
		136	struct drm_i915_master_private *master_priv;
		137	struct intel_ring_buffer *ring = LP_RING(dev_priv);
2330	Serge	138
3031	serge	139	/*
		140	* We should never lose context on the ring with modesetting
		141	* as we don't expose it to userspace
		142	*/
		143	if (drm_core_check_feature(dev, DRIVER_MODESET))
		144	return;
2330	Serge	145
3031	serge	146	ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
		147	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
3243	Serge	148	ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
3031	serge	149	if (ring->space < 0)
		150	ring->space += ring->size;
2330	Serge	151
3031	serge	152	if (!dev->primary->master)
		153	return;
2330	Serge	154
3031	serge	155	master_priv = dev->primary->master->driver_priv;
		156	if (ring->head == ring->tail && master_priv->sarea_priv)
		157	master_priv->sarea_priv->perf_boxes \|= I915_BOX_RING_EMPTY;
		158	}
		159
		160	static int i915_dma_cleanup(struct drm_device * dev)
		161	{
		162	drm_i915_private_t *dev_priv = dev->dev_private;
		163	int i;
		164
		165	/* Make sure interrupts are disabled here because the uninstall ioctl
		166	* may not have been called from userspace and after dev_private
		167	* is freed, it's too late.
		168	*/
		169	if (dev->irq_enabled)
		170	drm_irq_uninstall(dev);
		171
		172	mutex_lock(&dev->struct_mutex);
		173	for (i = 0; i < I915_NUM_RINGS; i++)
		174	intel_cleanup_ring_buffer(&dev_priv->ring[i]);
		175	mutex_unlock(&dev->struct_mutex);
		176
		177	/* Clear the HWS virtual address at teardown */
		178	if (I915_NEED_GFX_HWS(dev))
		179	i915_free_hws(dev);
		180
		181	return 0;
		182	}
		183
		184	static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
		185	{
		186	drm_i915_private_t *dev_priv = dev->dev_private;
		187	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
		188	int ret;
		189
		190	master_priv->sarea = drm_getsarea(dev);
		191	if (master_priv->sarea) {
		192	master_priv->sarea_priv = (drm_i915_sarea_t *)
		193	((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
		194	} else {
		195	DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
		196	}
		197
		198	if (init->ring_size != 0) {
		199	if (LP_RING(dev_priv)->obj != NULL) {
		200	i915_dma_cleanup(dev);
		201	DRM_ERROR("Client tried to initialize ringbuffer in "
		202	"GEM mode\n");
		203	return -EINVAL;
		204	}
		205
		206	ret = intel_render_ring_init_dri(dev,
		207	init->ring_start,
		208	init->ring_size);
		209	if (ret) {
		210	i915_dma_cleanup(dev);
		211	return ret;
		212	}
		213	}
		214
		215	dev_priv->dri1.cpp = init->cpp;
		216	dev_priv->dri1.back_offset = init->back_offset;
		217	dev_priv->dri1.front_offset = init->front_offset;
		218	dev_priv->dri1.current_page = 0;
		219	if (master_priv->sarea_priv)
		220	master_priv->sarea_priv->pf_current_page = 0;
		221
		222	/* Allow hardware batchbuffers unless told otherwise.
		223	*/
		224	dev_priv->dri1.allow_batchbuffer = 1;
		225
		226	return 0;
		227	}
		228
		229	static int i915_dma_resume(struct drm_device * dev)
		230	{
		231	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
		232	struct intel_ring_buffer *ring = LP_RING(dev_priv);
		233
		234	DRM_DEBUG_DRIVER("%s\n", __func__);
		235
		236	if (ring->virtual_start == NULL) {
		237	DRM_ERROR("can not ioremap virtual address for"
		238	" ring buffer\n");
		239	return -ENOMEM;
		240	}
		241
		242	/* Program Hardware Status Page */
		243	if (!ring->status_page.page_addr) {
		244	DRM_ERROR("Can not find hardware status page\n");
		245	return -EINVAL;
		246	}
		247	DRM_DEBUG_DRIVER("hw status page @ %p\n",
		248	ring->status_page.page_addr);
		249	if (ring->status_page.gfx_addr != 0)
		250	intel_ring_setup_status_page(ring);
		251	else
		252	i915_write_hws_pga(dev);
		253
		254	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
		255
		256	return 0;
		257	}
		258
		259	static int i915_dma_init(struct drm_device dev, void data,
		260	struct drm_file *file_priv)
		261	{
		262	drm_i915_init_t *init = data;
		263	int retcode = 0;
		264
		265	if (drm_core_check_feature(dev, DRIVER_MODESET))
		266	return -ENODEV;
		267
		268	switch (init->func) {
		269	case I915_INIT_DMA:
		270	retcode = i915_initialize(dev, init);
		271	break;
		272	case I915_CLEANUP_DMA:
		273	retcode = i915_dma_cleanup(dev);
		274	break;
		275	case I915_RESUME_DMA:
		276	retcode = i915_dma_resume(dev);
		277	break;
		278	default:
		279	retcode = -EINVAL;
		280	break;
		281	}
		282
		283	return retcode;
		284	}
		285
		286	/* Implement basically the same security restrictions as hardware does
		287	* for MI_BATCH_NON_SECURE. These can be made stricter at any time.
		288	*
		289	* Most of the calculations below involve calculating the size of a
		290	* particular instruction. It's important to get the size right as
		291	* that tells us where the next instruction to check is. Any illegal
		292	* instruction detected will be given a size of zero, which is a
		293	* signal to abort the rest of the buffer.
		294	*/
		295	static int validate_cmd(int cmd)
		296	{
		297	switch (((cmd >> 29) & 0x7)) {
		298	case 0x0:
		299	switch ((cmd >> 23) & 0x3f) {
		300	case 0x0:
		301	return 1; /* MI_NOOP */
		302	case 0x4:
		303	return 1; /* MI_FLUSH */
		304	default:
		305	return 0; /* disallow everything else */
		306	}
		307	break;
		308	case 0x1:
		309	return 0; /* reserved */
		310	case 0x2:
		311	return (cmd & 0xff) + 2; /* 2d commands */
		312	case 0x3:
		313	if (((cmd >> 24) & 0x1f) <= 0x18)
		314	return 1;
		315
		316	switch ((cmd >> 24) & 0x1f) {
		317	case 0x1c:
		318	return 1;
		319	case 0x1d:
		320	switch ((cmd >> 16) & 0xff) {
		321	case 0x3:
		322	return (cmd & 0x1f) + 2;
		323	case 0x4:
		324	return (cmd & 0xf) + 2;
		325	default:
		326	return (cmd & 0xffff) + 2;
		327	}
		328	case 0x1e:
		329	if (cmd & (1 << 23))
		330	return (cmd & 0xffff) + 1;
		331	else
		332	return 1;
		333	case 0x1f:
		334	if ((cmd & (1 << 23)) == 0) /* inline vertices */
		335	return (cmd & 0x1ffff) + 2;
		336	else if (cmd & (1 << 17)) /* indirect random */
		337	if ((cmd & 0xffff) == 0)
		338	return 0; /* unknown length, too hard */
		339	else
		340	return (((cmd & 0xffff) + 1) / 2) + 1;
		341	else
		342	return 2; /* indirect sequential */
		343	default:
		344	return 0;
		345	}
		346	default:
		347	return 0;
		348	}
		349
		350	return 0;
		351	}
		352
		353	static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
		354	{
		355	drm_i915_private_t *dev_priv = dev->dev_private;
		356	int i, ret;
		357
		358	if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
		359	return -EINVAL;
		360
		361	for (i = 0; i < dwords;) {
		362	int sz = validate_cmd(buffer[i]);
		363	if (sz == 0 \|\| i + sz > dwords)
		364	return -EINVAL;
		365	i += sz;
		366	}
		367
		368	ret = BEGIN_LP_RING((dwords+1)&~1);
		369	if (ret)
		370	return ret;
		371
		372	for (i = 0; i < dwords; i++)
		373	OUT_RING(buffer[i]);
		374	if (dwords & 1)
		375	OUT_RING(0);
		376
		377	ADVANCE_LP_RING();
		378
		379	return 0;
		380	}
		381
		382	int
		383	i915_emit_box(struct drm_device *dev,
		384	struct drm_clip_rect *box,
		385	int DR1, int DR4)
		386	{
		387	struct drm_i915_private *dev_priv = dev->dev_private;
		388	int ret;
		389
		390	if (box->y2 <= box->y1 \|\| box->x2 <= box->x1 \|\|
		391	box->y2 <= 0 \|\| box->x2 <= 0) {
		392	DRM_ERROR("Bad box %d,%d..%d,%d\n",
		393	box->x1, box->y1, box->x2, box->y2);
		394	return -EINVAL;
		395	}
		396
		397	if (INTEL_INFO(dev)->gen >= 4) {
		398	ret = BEGIN_LP_RING(4);
		399	if (ret)
		400	return ret;
		401
		402	OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
		403	OUT_RING((box->x1 & 0xffff) \| (box->y1 << 16));
		404	OUT_RING(((box->x2 - 1) & 0xffff) \| ((box->y2 - 1) << 16));
		405	OUT_RING(DR4);
		406	} else {
		407	ret = BEGIN_LP_RING(6);
		408	if (ret)
		409	return ret;
		410
		411	OUT_RING(GFX_OP_DRAWRECT_INFO);
		412	OUT_RING(DR1);
		413	OUT_RING((box->x1 & 0xffff) \| (box->y1 << 16));
		414	OUT_RING(((box->x2 - 1) & 0xffff) \| ((box->y2 - 1) << 16));
		415	OUT_RING(DR4);
		416	OUT_RING(0);
		417	}
		418	ADVANCE_LP_RING();
		419
		420	return 0;
		421	}
		422
		423	/* XXX: Emitting the counter should really be moved to part of the IRQ
		424	* emit. For now, do it in both places:
		425	*/
		426
		427	static void i915_emit_breadcrumb(struct drm_device *dev)
		428	{
		429	drm_i915_private_t *dev_priv = dev->dev_private;
		430	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
		431
3243	Serge	432	dev_priv->dri1.counter++;
		433	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
		434	dev_priv->dri1.counter = 0;
3031	serge	435	if (master_priv->sarea_priv)
3243	Serge	436	master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
3031	serge	437
		438	if (BEGIN_LP_RING(4) == 0) {
		439	OUT_RING(MI_STORE_DWORD_INDEX);
		440	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
3243	Serge	441	OUT_RING(dev_priv->dri1.counter);
3031	serge	442	OUT_RING(0);
		443	ADVANCE_LP_RING();
		444	}
		445	}
		446
		447	static int i915_dispatch_cmdbuffer(struct drm_device * dev,
		448	drm_i915_cmdbuffer_t *cmd,
		449	struct drm_clip_rect *cliprects,
		450	void *cmdbuf)
		451	{
		452	int nbox = cmd->num_cliprects;
		453	int i = 0, count, ret;
		454
		455	if (cmd->sz & 0x3) {
		456	DRM_ERROR("alignment");
		457	return -EINVAL;
		458	}
		459
		460	i915_kernel_lost_context(dev);
		461
		462	count = nbox ? nbox : 1;
		463
		464	for (i = 0; i < count; i++) {
		465	if (i < nbox) {
		466	ret = i915_emit_box(dev, &cliprects[i],
		467	cmd->DR1, cmd->DR4);
		468	if (ret)
		469	return ret;
		470	}
		471
		472	ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
		473	if (ret)
		474	return ret;
		475	}
		476
		477	i915_emit_breadcrumb(dev);
		478	return 0;
		479	}
		480
		481	static int i915_dispatch_batchbuffer(struct drm_device * dev,
		482	drm_i915_batchbuffer_t * batch,
		483	struct drm_clip_rect *cliprects)
		484	{
		485	struct drm_i915_private *dev_priv = dev->dev_private;
		486	int nbox = batch->num_cliprects;
		487	int i, count, ret;
		488
		489	if ((batch->start \| batch->used) & 0x7) {
		490	DRM_ERROR("alignment");
		491	return -EINVAL;
		492	}
		493
		494	i915_kernel_lost_context(dev);
		495
		496	count = nbox ? nbox : 1;
		497	for (i = 0; i < count; i++) {
		498	if (i < nbox) {
		499	ret = i915_emit_box(dev, &cliprects[i],
		500	batch->DR1, batch->DR4);
		501	if (ret)
		502	return ret;
		503	}
		504
		505	if (!IS_I830(dev) && !IS_845G(dev)) {
		506	ret = BEGIN_LP_RING(2);
		507	if (ret)
		508	return ret;
		509
		510	if (INTEL_INFO(dev)->gen >= 4) {
		511	OUT_RING(MI_BATCH_BUFFER_START \| (2 << 6) \| MI_BATCH_NON_SECURE_I965);
		512	OUT_RING(batch->start);
		513	} else {
		514	OUT_RING(MI_BATCH_BUFFER_START \| (2 << 6));
		515	OUT_RING(batch->start \| MI_BATCH_NON_SECURE);
		516	}
		517	} else {
		518	ret = BEGIN_LP_RING(4);
		519	if (ret)
		520	return ret;
		521
		522	OUT_RING(MI_BATCH_BUFFER);
		523	OUT_RING(batch->start \| MI_BATCH_NON_SECURE);
		524	OUT_RING(batch->start + batch->used - 4);
		525	OUT_RING(0);
		526	}
		527	ADVANCE_LP_RING();
		528	}
		529
		530
		531	if (IS_G4X(dev) \|\| IS_GEN5(dev)) {
		532	if (BEGIN_LP_RING(2) == 0) {
		533	OUT_RING(MI_FLUSH \| MI_NO_WRITE_FLUSH \| MI_INVALIDATE_ISP);
		534	OUT_RING(MI_NOOP);
		535	ADVANCE_LP_RING();
		536	}
		537	}
		538
		539	i915_emit_breadcrumb(dev);
		540	return 0;
		541	}
		542
		543	static int i915_dispatch_flip(struct drm_device * dev)
		544	{
		545	drm_i915_private_t *dev_priv = dev->dev_private;
		546	struct drm_i915_master_private *master_priv =
		547	dev->primary->master->driver_priv;
		548	int ret;
		549
		550	if (!master_priv->sarea_priv)
		551	return -EINVAL;
		552
		553	DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
		554	__func__,
		555	dev_priv->dri1.current_page,
		556	master_priv->sarea_priv->pf_current_page);
		557
		558	i915_kernel_lost_context(dev);
		559
		560	ret = BEGIN_LP_RING(10);
		561	if (ret)
		562	return ret;
		563
		564	OUT_RING(MI_FLUSH \| MI_READ_FLUSH);
		565	OUT_RING(0);
		566
		567	OUT_RING(CMD_OP_DISPLAYBUFFER_INFO \| ASYNC_FLIP);
		568	OUT_RING(0);
		569	if (dev_priv->dri1.current_page == 0) {
		570	OUT_RING(dev_priv->dri1.back_offset);
		571	dev_priv->dri1.current_page = 1;
		572	} else {
		573	OUT_RING(dev_priv->dri1.front_offset);
		574	dev_priv->dri1.current_page = 0;
		575	}
		576	OUT_RING(0);
		577
		578	OUT_RING(MI_WAIT_FOR_EVENT \| MI_WAIT_FOR_PLANE_A_FLIP);
		579	OUT_RING(0);
		580
		581	ADVANCE_LP_RING();
		582
3243	Serge	583	master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
3031	serge	584
		585	if (BEGIN_LP_RING(4) == 0) {
		586	OUT_RING(MI_STORE_DWORD_INDEX);
		587	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
3243	Serge	588	OUT_RING(dev_priv->dri1.counter);
3031	serge	589	OUT_RING(0);
		590	ADVANCE_LP_RING();
		591	}
		592
		593	master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
		594	return 0;
		595	}
		596
		597	static int i915_quiescent(struct drm_device *dev)
		598	{
		599	i915_kernel_lost_context(dev);
3243	Serge	600	return intel_ring_idle(LP_RING(dev->dev_private));
3031	serge	601	}
		602
		603	static int i915_flush_ioctl(struct drm_device dev, void data,
		604	struct drm_file *file_priv)
		605	{
		606	int ret;
		607
		608	if (drm_core_check_feature(dev, DRIVER_MODESET))
		609	return -ENODEV;
		610
		611	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
		612
		613	mutex_lock(&dev->struct_mutex);
		614	ret = i915_quiescent(dev);
		615	mutex_unlock(&dev->struct_mutex);
		616
		617	return ret;
		618	}
		619
		620	static int i915_batchbuffer(struct drm_device dev, void data,
		621	struct drm_file *file_priv)
		622	{
		623	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
		624	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
		625	drm_i915_sarea_t sarea_priv = (drm_i915_sarea_t )
		626	master_priv->sarea_priv;
		627	drm_i915_batchbuffer_t *batch = data;
		628	int ret;
		629	struct drm_clip_rect *cliprects = NULL;
		630
		631	if (drm_core_check_feature(dev, DRIVER_MODESET))
		632	return -ENODEV;
		633
		634	if (!dev_priv->dri1.allow_batchbuffer) {
		635	DRM_ERROR("Batchbuffer ioctl disabled\n");
		636	return -EINVAL;
		637	}
		638
		639	DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
		640	batch->start, batch->used, batch->num_cliprects);
		641
		642	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
		643
		644	if (batch->num_cliprects < 0)
		645	return -EINVAL;
		646
		647	if (batch->num_cliprects) {
		648	cliprects = kcalloc(batch->num_cliprects,
		649	sizeof(struct drm_clip_rect),
		650	GFP_KERNEL);
		651	if (cliprects == NULL)
		652	return -ENOMEM;
		653
		654	ret = copy_from_user(cliprects, batch->cliprects,
		655	batch->num_cliprects *
		656	sizeof(struct drm_clip_rect));
		657	if (ret != 0) {
		658	ret = -EFAULT;
		659	goto fail_free;
		660	}
		661	}
		662
		663	mutex_lock(&dev->struct_mutex);
		664	ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
		665	mutex_unlock(&dev->struct_mutex);
		666
		667	if (sarea_priv)
		668	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
		669
		670	fail_free:
		671	kfree(cliprects);
		672
		673	return ret;
		674	}
		675
		676	static int i915_cmdbuffer(struct drm_device dev, void data,
		677	struct drm_file *file_priv)
		678	{
		679	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
		680	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
		681	drm_i915_sarea_t sarea_priv = (drm_i915_sarea_t )
		682	master_priv->sarea_priv;
		683	drm_i915_cmdbuffer_t *cmdbuf = data;
		684	struct drm_clip_rect *cliprects = NULL;
		685	void *batch_data;
		686	int ret;
		687
		688	DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
		689	cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
		690
		691	if (drm_core_check_feature(dev, DRIVER_MODESET))
		692	return -ENODEV;
		693
		694	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
		695
		696	if (cmdbuf->num_cliprects < 0)
		697	return -EINVAL;
		698
		699	batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
		700	if (batch_data == NULL)
		701	return -ENOMEM;
		702
		703	ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
		704	if (ret != 0) {
		705	ret = -EFAULT;
		706	goto fail_batch_free;
		707	}
		708
		709	if (cmdbuf->num_cliprects) {
		710	cliprects = kcalloc(cmdbuf->num_cliprects,
		711	sizeof(struct drm_clip_rect), GFP_KERNEL);
		712	if (cliprects == NULL) {
		713	ret = -ENOMEM;
		714	goto fail_batch_free;
		715	}
		716
		717	ret = copy_from_user(cliprects, cmdbuf->cliprects,
		718	cmdbuf->num_cliprects *
		719	sizeof(struct drm_clip_rect));
		720	if (ret != 0) {
		721	ret = -EFAULT;
		722	goto fail_clip_free;
		723	}
		724	}
		725
		726	mutex_lock(&dev->struct_mutex);
		727	ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
		728	mutex_unlock(&dev->struct_mutex);
		729	if (ret) {
		730	DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
		731	goto fail_clip_free;
		732	}
		733
		734	if (sarea_priv)
		735	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
		736
		737	fail_clip_free:
		738	kfree(cliprects);
		739	fail_batch_free:
		740	kfree(batch_data);
		741
		742	return ret;
		743	}
		744
		745	static int i915_emit_irq(struct drm_device * dev)
		746	{
		747	drm_i915_private_t *dev_priv = dev->dev_private;
		748	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
		749
		750	i915_kernel_lost_context(dev);
		751
		752	DRM_DEBUG_DRIVER("\n");
		753
3243	Serge	754	dev_priv->dri1.counter++;
		755	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
		756	dev_priv->dri1.counter = 1;
3031	serge	757	if (master_priv->sarea_priv)
3243	Serge	758	master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
3031	serge	759
		760	if (BEGIN_LP_RING(4) == 0) {
		761	OUT_RING(MI_STORE_DWORD_INDEX);
		762	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
3243	Serge	763	OUT_RING(dev_priv->dri1.counter);
3031	serge	764	OUT_RING(MI_USER_INTERRUPT);
		765	ADVANCE_LP_RING();
		766	}
		767
3243	Serge	768	return dev_priv->dri1.counter;
3031	serge	769	}
		770
		771	static int i915_wait_irq(struct drm_device * dev, int irq_nr)
		772	{
		773	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
		774	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
		775	int ret = 0;
		776	struct intel_ring_buffer *ring = LP_RING(dev_priv);
		777
		778	DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
		779	READ_BREADCRUMB(dev_priv));
		780
		781	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
		782	if (master_priv->sarea_priv)
		783	master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
		784	return 0;
		785	}
		786
		787	if (master_priv->sarea_priv)
		788	master_priv->sarea_priv->perf_boxes \|= I915_BOX_WAIT;
		789
		790	if (ring->irq_get(ring)) {
		791	DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
		792	READ_BREADCRUMB(dev_priv) >= irq_nr);
		793	ring->irq_put(ring);
		794	} else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
		795	ret = -EBUSY;
		796
		797	if (ret == -EBUSY) {
		798	DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
3243	Serge	799	READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
3031	serge	800	}
		801
		802	return ret;
		803	}
		804
		805	/* Needs the lock as it touches the ring.
		806	*/
		807	static int i915_irq_emit(struct drm_device dev, void data,
		808	struct drm_file *file_priv)
		809	{
		810	drm_i915_private_t *dev_priv = dev->dev_private;
		811	drm_i915_irq_emit_t *emit = data;
		812	int result;
		813
		814	if (drm_core_check_feature(dev, DRIVER_MODESET))
		815	return -ENODEV;
		816
		817	if (!dev_priv \|\| !LP_RING(dev_priv)->virtual_start) {
		818	DRM_ERROR("called with no initialization\n");
		819	return -EINVAL;
		820	}
		821
		822	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
		823
		824	mutex_lock(&dev->struct_mutex);
		825	result = i915_emit_irq(dev);
		826	mutex_unlock(&dev->struct_mutex);
		827
		828	if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
		829	DRM_ERROR("copy_to_user\n");
		830	return -EFAULT;
		831	}
		832
		833	return 0;
		834	}
		835
		836	/* Doesn't need the hardware lock.
		837	*/
		838	static int i915_irq_wait(struct drm_device dev, void data,
		839	struct drm_file *file_priv)
		840	{
		841	drm_i915_private_t *dev_priv = dev->dev_private;
		842	drm_i915_irq_wait_t *irqwait = data;
		843
		844	if (drm_core_check_feature(dev, DRIVER_MODESET))
		845	return -ENODEV;
		846
		847	if (!dev_priv) {
		848	DRM_ERROR("called with no initialization\n");
		849	return -EINVAL;
		850	}
		851
		852	return i915_wait_irq(dev, irqwait->irq_seq);
		853	}
		854
		855	static int i915_vblank_pipe_get(struct drm_device dev, void data,
		856	struct drm_file *file_priv)
		857	{
		858	drm_i915_private_t *dev_priv = dev->dev_private;
		859	drm_i915_vblank_pipe_t *pipe = data;
		860
		861	if (drm_core_check_feature(dev, DRIVER_MODESET))
		862	return -ENODEV;
		863
		864	if (!dev_priv) {
		865	DRM_ERROR("called with no initialization\n");
		866	return -EINVAL;
		867	}
		868
		869	pipe->pipe = DRM_I915_VBLANK_PIPE_A \| DRM_I915_VBLANK_PIPE_B;
		870
		871	return 0;
		872	}
		873
		874	/**
		875	* Schedule buffer swap at given vertical blank.
		876	*/
		877	static int i915_vblank_swap(struct drm_device dev, void data,
		878	struct drm_file *file_priv)
		879	{
		880	/* The delayed swap mechanism was fundamentally racy, and has been
		881	* removed. The model was that the client requested a delayed flip/swap
		882	* from the kernel, then waited for vblank before continuing to perform
		883	* rendering. The problem was that the kernel might wake the client
		884	* up before it dispatched the vblank swap (since the lock has to be
		885	* held while touching the ringbuffer), in which case the client would
		886	* clear and start the next frame before the swap occurred, and
		887	* flicker would occur in addition to likely missing the vblank.
		888	*
		889	* In the absence of this ioctl, userland falls back to a correct path
		890	* of waiting for a vblank, then dispatching the swap on its own.
		891	* Context switching to userland and back is plenty fast enough for
		892	* meeting the requirements of vblank swapping.
		893	*/
		894	return -EINVAL;
		895	}
		896
		897	static int i915_flip_bufs(struct drm_device dev, void data,
		898	struct drm_file *file_priv)
		899	{
		900	int ret;
		901
		902	if (drm_core_check_feature(dev, DRIVER_MODESET))
		903	return -ENODEV;
		904
		905	DRM_DEBUG_DRIVER("%s\n", __func__);
		906
		907	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
		908
		909	mutex_lock(&dev->struct_mutex);
		910	ret = i915_dispatch_flip(dev);
		911	mutex_unlock(&dev->struct_mutex);
		912
		913	return ret;
		914	}
		915
		916	static int i915_getparam(struct drm_device dev, void data,
		917	struct drm_file *file_priv)
		918	{
		919	drm_i915_private_t *dev_priv = dev->dev_private;
		920	drm_i915_getparam_t *param = data;
		921	int value;
		922
		923	if (!dev_priv) {
		924	DRM_ERROR("called with no initialization\n");
		925	return -EINVAL;
		926	}
		927
		928	switch (param->param) {
		929	case I915_PARAM_IRQ_ACTIVE:
		930	value = dev->pdev->irq ? 1 : 0;
		931	break;
		932	case I915_PARAM_ALLOW_BATCHBUFFER:
		933	value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
		934	break;
		935	case I915_PARAM_LAST_DISPATCH:
		936	value = READ_BREADCRUMB(dev_priv);
		937	break;
		938	case I915_PARAM_CHIPSET_ID:
		939	value = dev->pci_device;
		940	break;
		941	case I915_PARAM_HAS_GEM:
		942	value = 1;
		943	break;
		944	case I915_PARAM_NUM_FENCES_AVAIL:
		945	value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
		946	break;
		947	case I915_PARAM_HAS_OVERLAY:
		948	value = dev_priv->overlay ? 1 : 0;
		949	break;
		950	case I915_PARAM_HAS_PAGEFLIPPING:
		951	value = 1;
		952	break;
		953	case I915_PARAM_HAS_EXECBUF2:
		954	/* depends on GEM */
		955	value = 1;
		956	break;
		957	case I915_PARAM_HAS_BSD:
		958	value = intel_ring_initialized(&dev_priv->ring[VCS]);
		959	break;
		960	case I915_PARAM_HAS_BLT:
		961	value = intel_ring_initialized(&dev_priv->ring[BCS]);
		962	break;
		963	case I915_PARAM_HAS_RELAXED_FENCING:
		964	value = 1;
		965	break;
		966	case I915_PARAM_HAS_COHERENT_RINGS:
		967	value = 1;
		968	break;
		969	case I915_PARAM_HAS_EXEC_CONSTANTS:
		970	value = INTEL_INFO(dev)->gen >= 4;
		971	break;
		972	case I915_PARAM_HAS_RELAXED_DELTA:
		973	value = 1;
		974	break;
		975	case I915_PARAM_HAS_GEN7_SOL_RESET:
		976	value = 1;
		977	break;
		978	case I915_PARAM_HAS_LLC:
		979	value = HAS_LLC(dev);
		980	break;
		981	case I915_PARAM_HAS_ALIASING_PPGTT:
		982	value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
		983	break;
		984	case I915_PARAM_HAS_WAIT_TIMEOUT:
		985	value = 1;
		986	break;
		987	case I915_PARAM_HAS_SEMAPHORES:
		988	value = i915_semaphore_is_enabled(dev);
		989	break;
		990	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
		991	value = 1;
		992	break;
3243	Serge	993	case I915_PARAM_HAS_SECURE_BATCHES:
		994	value = capable(CAP_SYS_ADMIN);
		995	break;
		996	case I915_PARAM_HAS_PINNED_BATCHES:
		997	value = 1;
		998	break;
3031	serge	999	default:
		1000	DRM_DEBUG_DRIVER("Unknown parameter %d\n",
		1001	param->param);
		1002	return -EINVAL;
		1003	}
		1004
		1005	if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
		1006	DRM_ERROR("DRM_COPY_TO_USER failed\n");
		1007	return -EFAULT;
		1008	}
		1009
		1010	return 0;
		1011	}
		1012
		1013	static int i915_setparam(struct drm_device dev, void data,
		1014	struct drm_file *file_priv)
		1015	{
		1016	drm_i915_private_t *dev_priv = dev->dev_private;
		1017	drm_i915_setparam_t *param = data;
		1018
		1019	if (!dev_priv) {
		1020	DRM_ERROR("called with no initialization\n");
		1021	return -EINVAL;
		1022	}
		1023
		1024	switch (param->param) {
		1025	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
		1026	break;
		1027	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
		1028	break;
		1029	case I915_SETPARAM_ALLOW_BATCHBUFFER:
		1030	dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
		1031	break;
		1032	case I915_SETPARAM_NUM_USED_FENCES:
		1033	if (param->value > dev_priv->num_fence_regs \|\|
		1034	param->value < 0)
		1035	return -EINVAL;
		1036	/* Userspace can use first N regs */
		1037	dev_priv->fence_reg_start = param->value;
		1038	break;
		1039	default:
		1040	DRM_DEBUG_DRIVER("unknown parameter %d\n",
		1041	param->param);
		1042	return -EINVAL;
		1043	}
		1044
		1045	return 0;
		1046	}
		1047	#endif
		1048
		1049
		1050	static int i915_set_status_page(struct drm_device dev, void data,
		1051	struct drm_file *file_priv)
		1052	{
		1053	drm_i915_private_t *dev_priv = dev->dev_private;
		1054	drm_i915_hws_addr_t *hws = data;
3243	Serge	1055	struct intel_ring_buffer *ring;
3031	serge	1056
		1057	if (drm_core_check_feature(dev, DRIVER_MODESET))
		1058	return -ENODEV;
		1059
		1060	if (!I915_NEED_GFX_HWS(dev))
		1061	return -EINVAL;
		1062
		1063	if (!dev_priv) {
		1064	DRM_ERROR("called with no initialization\n");
		1065	return -EINVAL;
		1066	}
		1067
		1068	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		1069	WARN(1, "tried to set status page when mode setting active\n");
		1070	return 0;
		1071	}
		1072
		1073	DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
		1074
3243	Serge	1075	ring = LP_RING(dev_priv);
3031	serge	1076	ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
		1077
		1078	dev_priv->dri1.gfx_hws_cpu_addr =
		1079	ioremap(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
		1080	if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
		1081	i915_dma_cleanup(dev);
		1082	ring->status_page.gfx_addr = 0;
		1083	DRM_ERROR("can not ioremap virtual address for"
		1084	" G33 hw status page\n");
		1085	return -ENOMEM;
		1086	}
		1087
		1088	memset(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
		1089	I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
		1090
		1091	DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
		1092	ring->status_page.gfx_addr);
		1093	DRM_DEBUG_DRIVER("load hws at %p\n",
		1094	ring->status_page.page_addr);
		1095	return 0;
		1096	}
		1097
		1098	static int i915_get_bridge_dev(struct drm_device *dev)
		1099	{
		1100	struct drm_i915_private *dev_priv = dev->dev_private;
		1101
		1102	dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
		1103	if (!dev_priv->bridge_dev) {
		1104	DRM_ERROR("bridge device not found\n");
		1105	return -1;
		1106	}
		1107	return 0;
		1108	}
		1109
2330	Serge	1110	#define MCHBAR_I915 0x44
		1111	#define MCHBAR_I965 0x48
		1112	#define MCHBAR_SIZE (4*4096)
		1113
		1114	#define DEVEN_REG 0x54
		1115	#define DEVEN_MCHBAR_EN (1 << 28)
		1116
		1117
		1118
		1119
		1120	/* Setup MCHBAR if possible, return true if we should disable it again */
		1121	static void
		1122	intel_setup_mchbar(struct drm_device *dev)
		1123	{
		1124	drm_i915_private_t *dev_priv = dev->dev_private;
		1125	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
		1126	u32 temp;
		1127	bool enabled;
		1128
		1129	dev_priv->mchbar_need_disable = false;
		1130
		1131	if (IS_I915G(dev) \|\| IS_I915GM(dev)) {
		1132	pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
		1133	enabled = !!(temp & DEVEN_MCHBAR_EN);
		1134	} else {
		1135	pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		1136	enabled = temp & 1;
		1137	}
		1138
		1139	/* If it's already enabled, don't have to do anything */
		1140	if (enabled)
		1141	return;
		1142
		1143	dbgprintf("Epic fail\n");
		1144
		1145	#if 0
		1146	if (intel_alloc_mchbar_resource(dev))
		1147	return;
		1148
		1149	dev_priv->mchbar_need_disable = true;
		1150
		1151	/* Space is allocated or reserved, so enable it. */
		1152	if (IS_I915G(dev) \|\| IS_I915GM(dev)) {
		1153	pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
		1154	temp \| DEVEN_MCHBAR_EN);
		1155	} else {
		1156	pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		1157	pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp \| 1);
		1158	}
		1159	#endif
		1160	}
		1161
		1162
3031	serge	1163	/* true = enable decode, false = disable decoder */
		1164	static unsigned int i915_vga_set_decode(void *cookie, bool state)
2330	Serge	1165	{
3031	serge	1166	struct drm_device *dev = cookie;
2330	Serge	1167
3031	serge	1168	intel_modeset_vga_set_state(dev, state);
		1169	if (state)
		1170	return VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM \|
		1171	VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		1172	else
		1173	return VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		1174	}
2330	Serge	1175
		1176
		1177
		1178
		1179
		1180
2327	Serge	1181	static int i915_load_modeset_init(struct drm_device *dev)
		1182	{
		1183	struct drm_i915_private *dev_priv = dev->dev_private;
		1184	int ret;
		1185
		1186	ret = intel_parse_bios(dev);
		1187	if (ret)
		1188	DRM_INFO("failed to find VBIOS tables\n");
		1189
		1190	// intel_register_dsm_handler();
		1191
3031	serge	1192	/* Initialise stolen first so that we may reserve preallocated
		1193	* objects for the BIOS to KMS transition.
		1194	*/
		1195	ret = i915_gem_init_stolen(dev);
		1196	if (ret)
		1197	goto cleanup_vga_switcheroo;
2327	Serge	1198
		1199	intel_modeset_init(dev);
		1200
3031	serge	1201	ret = i915_gem_init(dev);
2327	Serge	1202	if (ret)
3031	serge	1203	goto cleanup_gem_stolen;
2327	Serge	1204
		1205	intel_modeset_gem_init(dev);
		1206
2351	Serge	1207	ret = drm_irq_install(dev);
		1208	if (ret)
		1209	goto cleanup_gem;
2327	Serge	1210
		1211	/* Always safe in the mode setting case. */
		1212	/* FIXME: do pre/post-mode set stuff in core KMS code */
		1213	dev->vblank_disable_allowed = 1;
		1214
		1215	ret = intel_fbdev_init(dev);
		1216	if (ret)
		1217	goto cleanup_irq;
		1218
2332	Serge	1219	// drm_kms_helper_poll_init(dev);
2327	Serge	1220
		1221	/* We're off and running w/KMS */
		1222	dev_priv->mm.suspended = 0;
		1223
		1224	return 0;
		1225
		1226	cleanup_irq:
		1227	// drm_irq_uninstall(dev);
		1228	cleanup_gem:
		1229	// mutex_lock(&dev->struct_mutex);
		1230	// i915_gem_cleanup_ringbuffer(dev);
		1231	// mutex_unlock(&dev->struct_mutex);
3031	serge	1232	// i915_gem_cleanup_aliasing_ppgtt(dev);
		1233	cleanup_gem_stolen:
		1234	// i915_gem_cleanup_stolen(dev);
2327	Serge	1235	cleanup_vga_switcheroo:
		1236	// vga_switcheroo_unregister_client(dev->pdev);
		1237	cleanup_vga_client:
		1238	// vga_client_register(dev->pdev, NULL, NULL, NULL);
		1239	out:
		1240	return ret;
		1241	}
		1242
		1243
		1244
2326	Serge	1245
3031	serge	1246	static void i915_dump_device_info(struct drm_i915_private *dev_priv)
2326	Serge	1247	{
3031	serge	1248	const struct intel_device_info *info = dev_priv->info;
2326	Serge	1249
3031	serge	1250	#define DEV_INFO_FLAG(name) info->name ? #name "," : ""
		1251	#define DEV_INFO_SEP ,
		1252	DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
		1253	"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
		1254	info->gen,
		1255	dev_priv->dev->pdev->device,
		1256	DEV_INFO_FLAGS);
		1257	#undef DEV_INFO_FLAG
		1258	#undef DEV_INFO_SEP
2326	Serge	1259	}
		1260
		1261	/**
		1262	* i915_driver_load - setup chip and create an initial config
		1263	* @dev: DRM device
		1264	* @flags: startup flags
		1265	*
		1266	* The driver load routine has to do several things:
		1267	* - drive output discovery via intel_modeset_init()
		1268	* - initialize the memory manager
		1269	* - allocate initial config memory
		1270	* - setup the DRM framebuffer with the allocated memory
		1271	*/
		1272	int i915_driver_load(struct drm_device *dev, unsigned long flags)
		1273	{
		1274	struct drm_i915_private *dev_priv;
3031	serge	1275	struct intel_device_info *info;
		1276	int ret = 0, mmio_bar, mmio_size;
		1277	uint32_t aperture_size;
2326	Serge	1278
3031	serge	1279	info = (struct intel_device_info *) flags;
		1280
		1281
2326	Serge	1282	dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
		1283	if (dev_priv == NULL)
		1284	return -ENOMEM;
		1285
		1286	dev->dev_private = (void *)dev_priv;
		1287	dev_priv->dev = dev;
3031	serge	1288	dev_priv->info = info;
2326	Serge	1289
3031	serge	1290	i915_dump_device_info(dev_priv);
		1291
2326	Serge	1292	if (i915_get_bridge_dev(dev)) {
		1293	ret = -EIO;
		1294	goto free_priv;
		1295	}
		1296
3243	Serge	1297	ret = i915_gem_gtt_init(dev);
		1298	if (ret)
3031	serge	1299	goto put_bridge;
		1300
		1301
		1302	pci_set_master(dev->pdev);
		1303
2326	Serge	1304	/* overlay on gen2 is broken and can't address above 1G */
		1305
		1306	/* 965GM sometimes incorrectly writes to hardware status page (HWS)
		1307	* using 32bit addressing, overwriting memory if HWS is located
		1308	* above 4GB.
		1309	*
		1310	* The documentation also mentions an issue with undefined
		1311	* behaviour if any general state is accessed within a page above 4GB,
		1312	* which also needs to be handled carefully.
		1313	*/
		1314
		1315	mmio_bar = IS_GEN2(dev) ? 1 : 0;
3031	serge	1316	/* Before gen4, the registers and the GTT are behind different BARs.
		1317	* However, from gen4 onwards, the registers and the GTT are shared
		1318	* in the same BAR, so we want to restrict this ioremap from
		1319	* clobbering the GTT which we want ioremap_wc instead. Fortunately,
		1320	* the register BAR remains the same size for all the earlier
		1321	* generations up to Ironlake.
		1322	*/
		1323	if (info->gen < 5)
		1324	mmio_size = 512*1024;
		1325	else
		1326	mmio_size = 210241024;
		1327
		1328	dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
2326	Serge	1329	if (!dev_priv->regs) {
		1330	DRM_ERROR("failed to map registers\n");
		1331	ret = -EIO;
3031	serge	1332	goto put_gmch;
2326	Serge	1333	}
		1334
3031	serge	1335	aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
		1336	dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
2326	Serge	1337
		1338
		1339
		1340	/* The i915 workqueue is primarily used for batched retirement of
		1341	* requests (and thus managing bo) once the task has been completed
		1342	* by the GPU. i915_gem_retire_requests() is called directly when we
		1343	* need high-priority retirement, such as waiting for an explicit
		1344	* bo.
		1345	*
		1346	* It is also used for periodic low-priority events, such as
		1347	* idle-timers and recording error state.
		1348	*
		1349	* All tasks on the workqueue are expected to acquire the dev mutex
		1350	* so there is no point in running more than one instance of the
3031	serge	1351	* workqueue at any time. Use an ordered one.
2326	Serge	1352	*/
3031	serge	1353	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
2360	Serge	1354	if (dev_priv->wq == NULL) {
		1355	DRM_ERROR("Failed to create our workqueue.\n");
		1356	ret = -ENOMEM;
		1357	goto out_mtrrfree;
		1358	}
2326	Serge	1359
3031	serge	1360	/* This must be called before any calls to HAS_PCH_* */
		1361	intel_detect_pch(dev);
2326	Serge	1362
2351	Serge	1363	intel_irq_init(dev);
3031	serge	1364	intel_gt_init(dev);
2326	Serge	1365
		1366	/* Try to make sure MCHBAR is enabled before poking at it */
2330	Serge	1367	intel_setup_mchbar(dev);
2326	Serge	1368	intel_setup_gmbus(dev);
2327	Serge	1369	intel_opregion_setup(dev);
2326	Serge	1370
2330	Serge	1371	intel_setup_bios(dev);
2326	Serge	1372
		1373	i915_gem_load(dev);
		1374
		1375	/* On the 945G/GM, the chipset reports the MSI capability on the
		1376	* integrated graphics even though the support isn't actually there
		1377	* according to the published specs. It doesn't appear to function
		1378	* correctly in testing on 945G.
		1379	* This may be a side effect of MSI having been made available for PEG
		1380	* and the registers being closely associated.
		1381	*
		1382	* According to chipset errata, on the 965GM, MSI interrupts may
		1383	* be lost or delayed, but we use them anyways to avoid
		1384	* stuck interrupts on some machines.
		1385	*/
		1386
		1387	spin_lock_init(&dev_priv->irq_lock);
		1388	spin_lock_init(&dev_priv->error_lock);
3031	serge	1389	spin_lock_init(&dev_priv->rps.lock);
		1390	spin_lock_init(&dev_priv->dpio_lock);
2326	Serge	1391
3243	Serge	1392	mutex_init(&dev_priv->rps.hw_lock);
		1393
3031	serge	1394	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
2342	Serge	1395	dev_priv->num_pipe = 3;
		1396	else if (IS_MOBILE(dev) \|\| !IS_GEN2(dev))
2326	Serge	1397	dev_priv->num_pipe = 2;
		1398	else
		1399	dev_priv->num_pipe = 1;
		1400
		1401	// ret = drm_vblank_init(dev, dev_priv->num_pipe);
		1402	// if (ret)
		1403	// goto out_gem_unload;
		1404
		1405	/* Start out suspended */
		1406	dev_priv->mm.suspended = 1;
		1407
2327	Serge	1408	ret = i915_load_modeset_init(dev);
		1409	if (ret < 0) {
		1410	DRM_ERROR("failed to init modeset\n");
		1411	goto out_gem_unload;
		1412	}
2326	Serge	1413
		1414	/* Must be done after probing outputs */
		1415
		1416
3031	serge	1417	if (IS_GEN5(dev))
		1418	intel_gpu_ips_init(dev_priv);
2326	Serge	1419
		1420	return 0;
		1421
		1422	out_gem_unload:
		1423	// if (dev_priv->mm.inactive_shrinker.shrink)
		1424	// unregister_shrinker(&dev_priv->mm.inactive_shrinker);
		1425
		1426	// if (dev->pdev->msi_enabled)
		1427	// pci_disable_msi(dev->pdev);
		1428
		1429	// intel_teardown_gmbus(dev);
		1430	// intel_teardown_mchbar(dev);
		1431	// destroy_workqueue(dev_priv->wq);
		1432	out_mtrrfree:
3031	serge	1433	// if (dev_priv->mm.gtt_mtrr >= 0) {
		1434	// mtrr_del(dev_priv->mm.gtt_mtrr,
		1435	// dev_priv->mm.gtt_base_addr,
		1436	// aperture_size);
		1437	// dev_priv->mm.gtt_mtrr = -1;
		1438	// }
		1439	// io_mapping_free(dev_priv->mm.gtt_mapping);
2326	Serge	1440	out_rmmap:
		1441	pci_iounmap(dev->pdev, dev_priv->regs);
3031	serge	1442	put_gmch:
		1443	// intel_gmch_remove();
2326	Serge	1444	put_bridge:
		1445	// pci_dev_put(dev_priv->bridge_dev);
		1446	free_priv:
		1447	kfree(dev_priv);
		1448	return ret;
		1449	}
		1450
3031	serge	1451	#if 0
		1452
		1453	int i915_driver_unload(struct drm_device *dev)
		1454	{
		1455	struct drm_i915_private *dev_priv = dev->dev_private;
		1456	int ret;
		1457
		1458	intel_gpu_ips_teardown();
		1459
		1460	i915_teardown_sysfs(dev);
		1461
		1462	if (dev_priv->mm.inactive_shrinker.shrink)
		1463	unregister_shrinker(&dev_priv->mm.inactive_shrinker);
		1464
		1465	mutex_lock(&dev->struct_mutex);
		1466	ret = i915_gpu_idle(dev);
		1467	if (ret)
		1468	DRM_ERROR("failed to idle hardware: %d\n", ret);
		1469	i915_gem_retire_requests(dev);
		1470	mutex_unlock(&dev->struct_mutex);
		1471
		1472	/* Cancel the retire work handler, which should be idle now. */
		1473	cancel_delayed_work_sync(&dev_priv->mm.retire_work);
		1474
		1475	io_mapping_free(dev_priv->mm.gtt_mapping);
		1476	if (dev_priv->mm.gtt_mtrr >= 0) {
		1477	mtrr_del(dev_priv->mm.gtt_mtrr,
		1478	dev_priv->mm.gtt_base_addr,
		1479	dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
		1480	dev_priv->mm.gtt_mtrr = -1;
		1481	}
		1482
		1483	acpi_video_unregister();
		1484
		1485	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		1486	intel_fbdev_fini(dev);
		1487	intel_modeset_cleanup(dev);
3243	Serge	1488	cancel_work_sync(&dev_priv->console_resume_work);
3031	serge	1489
		1490	/*
		1491	* free the memory space allocated for the child device
		1492	* config parsed from VBT
		1493	*/
		1494	if (dev_priv->child_dev && dev_priv->child_dev_num) {
		1495	kfree(dev_priv->child_dev);
		1496	dev_priv->child_dev = NULL;
		1497	dev_priv->child_dev_num = 0;
		1498	}
		1499
		1500	vga_switcheroo_unregister_client(dev->pdev);
		1501	vga_client_register(dev->pdev, NULL, NULL, NULL);
		1502	}
		1503
		1504	/* Free error state after interrupts are fully disabled. */
		1505	del_timer_sync(&dev_priv->hangcheck_timer);
		1506	cancel_work_sync(&dev_priv->error_work);
		1507	i915_destroy_error_state(dev);
		1508
		1509	if (dev->pdev->msi_enabled)
		1510	pci_disable_msi(dev->pdev);
		1511
		1512	intel_opregion_fini(dev);
		1513
		1514	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		1515	/* Flush any outstanding unpin_work. */
		1516	flush_workqueue(dev_priv->wq);
		1517
		1518	mutex_lock(&dev->struct_mutex);
		1519	i915_gem_free_all_phys_object(dev);
		1520	i915_gem_cleanup_ringbuffer(dev);
		1521	i915_gem_context_fini(dev);
		1522	mutex_unlock(&dev->struct_mutex);
		1523	i915_gem_cleanup_aliasing_ppgtt(dev);
		1524	i915_gem_cleanup_stolen(dev);
		1525	drm_mm_takedown(&dev_priv->mm.stolen);
		1526
		1527	intel_cleanup_overlay(dev);
		1528
		1529	if (!I915_NEED_GFX_HWS(dev))
		1530	i915_free_hws(dev);
		1531	}
		1532
		1533	if (dev_priv->regs != NULL)
		1534	pci_iounmap(dev->pdev, dev_priv->regs);
		1535
		1536	intel_teardown_gmbus(dev);
		1537	intel_teardown_mchbar(dev);
		1538
		1539	destroy_workqueue(dev_priv->wq);
		1540
		1541	pci_dev_put(dev_priv->bridge_dev);
		1542	kfree(dev->dev_private);
		1543
		1544	return 0;
		1545	}
		1546
		1547	int i915_driver_open(struct drm_device dev, struct drm_file file)
		1548	{
		1549	struct drm_i915_file_private *file_priv;
		1550
		1551	DRM_DEBUG_DRIVER("\n");
		1552	file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
		1553	if (!file_priv)
		1554	return -ENOMEM;
		1555
		1556	file->driver_priv = file_priv;
		1557
		1558	spin_lock_init(&file_priv->mm.lock);
		1559	INIT_LIST_HEAD(&file_priv->mm.request_list);
		1560
		1561	idr_init(&file_priv->context_idr);
		1562
		1563	return 0;
		1564	}
		1565
		1566	/**
		1567	* i915_driver_lastclose - clean up after all DRM clients have exited
		1568	* @dev: DRM device
		1569	*
		1570	* Take care of cleaning up after all DRM clients have exited. In the
		1571	* mode setting case, we want to restore the kernel's initial mode (just
		1572	* in case the last client left us in a bad state).
		1573	*
		1574	* Additionally, in the non-mode setting case, we'll tear down the GTT
		1575	* and DMA structures, since the kernel won't be using them, and clea
		1576	* up any GEM state.
		1577	*/
		1578	void i915_driver_lastclose(struct drm_device * dev)
		1579	{
		1580	drm_i915_private_t *dev_priv = dev->dev_private;
		1581
		1582	/* On gen6+ we refuse to init without kms enabled, but then the drm core
		1583	* goes right around and calls lastclose. Check for this and don't clean
		1584	* up anything. */
		1585	if (!dev_priv)
		1586	return;
		1587
		1588	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		1589	intel_fb_restore_mode(dev);
		1590	vga_switcheroo_process_delayed_switch();
		1591	return;
		1592	}
		1593
		1594	i915_gem_lastclose(dev);
		1595
		1596	i915_dma_cleanup(dev);
		1597	}
		1598
		1599	void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
		1600	{
		1601	i915_gem_context_close(dev, file_priv);
		1602	i915_gem_release(dev, file_priv);
		1603	}
		1604
		1605	void i915_driver_postclose(struct drm_device dev, struct drm_file file)
		1606	{
		1607	struct drm_i915_file_private *file_priv = file->driver_priv;
		1608
		1609	kfree(file_priv);
		1610	}
		1611
		1612	struct drm_ioctl_desc i915_ioctls[] = {
		1613	DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
		1614	DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
		1615	DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
		1616	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
		1617	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
		1618	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
		1619	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
		1620	DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
		1621	DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
		1622	DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
		1623	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
		1624	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
		1625	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
		1626	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
		1627	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
		1628	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
		1629	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
		1630	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY\|DRM_UNLOCKED),
		1631	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH\|DRM_UNLOCKED),
		1632	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH\|DRM_UNLOCKED),
		1633	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH\|DRM_ROOT_ONLY\|DRM_UNLOCKED),
		1634	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH\|DRM_ROOT_ONLY\|DRM_UNLOCKED),
		1635	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH\|DRM_UNLOCKED),
		1636	DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
		1637	DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
		1638	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH\|DRM_UNLOCKED),
		1639	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY\|DRM_UNLOCKED),
		1640	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY\|DRM_UNLOCKED),
		1641	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
		1642	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
		1643	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
		1644	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
		1645	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
		1646	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
		1647	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
		1648	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
		1649	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
		1650	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
		1651	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
		1652	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
		1653	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER\|DRM_CONTROL_ALLOW\|DRM_UNLOCKED),
		1654	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER\|DRM_CONTROL_ALLOW\|DRM_UNLOCKED),
		1655	DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER\|DRM_CONTROL_ALLOW\|DRM_UNLOCKED),
		1656	DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER\|DRM_CONTROL_ALLOW\|DRM_UNLOCKED),
		1657	DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH\|DRM_UNLOCKED),
		1658	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
		1659	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
		1660	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
		1661	};
		1662
		1663	int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
		1664
		1665	/*
		1666	* This is really ugly: Because old userspace abused the linux agp interface to
		1667	* manage the gtt, we need to claim that all intel devices are agp. For
		1668	* otherwise the drm core refuses to initialize the agp support code.
		1669	*/
		1670	int i915_driver_device_is_agp(struct drm_device * dev)
		1671	{
		1672	return 1;
		1673	}
		1674	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_dma.c @ 4560 – Rev 3243