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2326 | Serge | 1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ |
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3 | /* |
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4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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5 | * All Rights Reserved. |
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6 | * |
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7 | * Permission is hereby granted, free of charge, to any person obtaining a |
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8 | * copy of this software and associated documentation files (the |
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9 | * "Software"), to deal in the Software without restriction, including |
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10 | * without limitation the rights to use, copy, modify, merge, publish, |
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11 | * distribute, sub license, and/or sell copies of the Software, and to |
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12 | * permit persons to whom the Software is furnished to do so, subject to |
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13 | * the following conditions: |
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14 | * |
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15 | * The above copyright notice and this permission notice (including the |
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16 | * next paragraph) shall be included in all copies or substantial portions |
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17 | * of the Software. |
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18 | * |
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19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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26 | * |
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27 | */ |
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28 | |||
29 | #include "drmP.h" |
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30 | #include "drm.h" |
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31 | #include "drm_crtc_helper.h" |
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32 | #include "drm_fb_helper.h" |
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33 | #include "intel_drv.h" |
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34 | //#include "i915_drm.h" |
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35 | #include "i915_drv.h" |
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36 | #include |
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37 | //#include "i915_trace.h" |
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38 | //#include "../../../platform/x86/intel_ips.h" |
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39 | #include |
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40 | //#include |
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41 | //#include |
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42 | //#include |
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43 | //#include |
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44 | //#include |
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45 | //#include |
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46 | |||
47 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); |
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48 | |||
49 | static void i915_write_hws_pga(struct drm_device *dev) |
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50 | { |
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51 | drm_i915_private_t *dev_priv = dev->dev_private; |
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52 | u32 addr; |
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53 | |||
54 | addr = dev_priv->status_page_dmah->busaddr; |
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55 | if (INTEL_INFO(dev)->gen >= 4) |
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56 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
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57 | I915_WRITE(HWS_PGA, addr); |
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58 | } |
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59 | |||
60 | |||
61 | /** |
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62 | * Sets up the hardware status page for devices that need a physical address |
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63 | * in the register. |
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64 | */ |
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65 | static int i915_init_phys_hws(struct drm_device *dev) |
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66 | { |
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67 | drm_i915_private_t *dev_priv = dev->dev_private; |
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68 | |||
69 | /* Program Hardware Status Page */ |
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70 | dev_priv->status_page_dmah = |
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71 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
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72 | |||
73 | if (!dev_priv->status_page_dmah) { |
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74 | DRM_ERROR("Can not allocate hardware status page\n"); |
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75 | return -ENOMEM; |
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76 | } |
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77 | |||
78 | i915_write_hws_pga(dev); |
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79 | |||
80 | dbgprintf("Enabled hardware status page\n"); |
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81 | return 0; |
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82 | } |
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83 | |||
84 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
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85 | { |
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86 | drm_i915_private_t *dev_priv = dev->dev_private; |
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87 | u32 tmp; |
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88 | |||
89 | tmp = I915_READ(CLKCFG); |
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90 | |||
91 | switch (tmp & CLKCFG_FSB_MASK) { |
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92 | case CLKCFG_FSB_533: |
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93 | dev_priv->fsb_freq = 533; /* 133*4 */ |
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94 | break; |
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95 | case CLKCFG_FSB_800: |
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96 | dev_priv->fsb_freq = 800; /* 200*4 */ |
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97 | break; |
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98 | case CLKCFG_FSB_667: |
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99 | dev_priv->fsb_freq = 667; /* 167*4 */ |
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100 | break; |
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101 | case CLKCFG_FSB_400: |
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102 | dev_priv->fsb_freq = 400; /* 100*4 */ |
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103 | break; |
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104 | } |
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105 | |||
106 | switch (tmp & CLKCFG_MEM_MASK) { |
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107 | case CLKCFG_MEM_533: |
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108 | dev_priv->mem_freq = 533; |
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109 | break; |
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110 | case CLKCFG_MEM_667: |
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111 | dev_priv->mem_freq = 667; |
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112 | break; |
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113 | case CLKCFG_MEM_800: |
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114 | dev_priv->mem_freq = 800; |
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115 | break; |
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116 | } |
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117 | |||
118 | /* detect pineview DDR3 setting */ |
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119 | tmp = I915_READ(CSHRDDR3CTL); |
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120 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
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121 | } |
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122 | |||
123 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
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124 | { |
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125 | drm_i915_private_t *dev_priv = dev->dev_private; |
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126 | u16 ddrpll, csipll; |
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127 | |||
128 | ddrpll = I915_READ16(DDRMPLL1); |
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129 | csipll = I915_READ16(CSIPLL0); |
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130 | |||
131 | switch (ddrpll & 0xff) { |
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132 | case 0xc: |
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133 | dev_priv->mem_freq = 800; |
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134 | break; |
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135 | case 0x10: |
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136 | dev_priv->mem_freq = 1066; |
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137 | break; |
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138 | case 0x14: |
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139 | dev_priv->mem_freq = 1333; |
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140 | break; |
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141 | case 0x18: |
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142 | dev_priv->mem_freq = 1600; |
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143 | break; |
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144 | default: |
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145 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
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146 | ddrpll & 0xff); |
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147 | dev_priv->mem_freq = 0; |
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148 | break; |
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149 | } |
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150 | |||
151 | dev_priv->r_t = dev_priv->mem_freq; |
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152 | |||
153 | switch (csipll & 0x3ff) { |
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154 | case 0x00c: |
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155 | dev_priv->fsb_freq = 3200; |
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156 | break; |
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157 | case 0x00e: |
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158 | dev_priv->fsb_freq = 3733; |
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159 | break; |
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160 | case 0x010: |
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161 | dev_priv->fsb_freq = 4266; |
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162 | break; |
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163 | case 0x012: |
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164 | dev_priv->fsb_freq = 4800; |
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165 | break; |
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166 | case 0x014: |
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167 | dev_priv->fsb_freq = 5333; |
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168 | break; |
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169 | case 0x016: |
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170 | dev_priv->fsb_freq = 5866; |
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171 | break; |
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172 | case 0x018: |
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173 | dev_priv->fsb_freq = 6400; |
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174 | break; |
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175 | default: |
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176 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
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177 | csipll & 0x3ff); |
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178 | dev_priv->fsb_freq = 0; |
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179 | break; |
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180 | } |
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181 | |||
182 | if (dev_priv->fsb_freq == 3200) { |
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183 | dev_priv->c_m = 0; |
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184 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
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185 | dev_priv->c_m = 1; |
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186 | } else { |
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187 | dev_priv->c_m = 2; |
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188 | } |
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189 | } |
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190 | |||
191 | static int i915_get_bridge_dev(struct drm_device *dev) |
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192 | { |
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193 | struct drm_i915_private *dev_priv = dev->dev_private; |
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194 | |||
195 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); |
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196 | if (!dev_priv->bridge_dev) { |
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197 | DRM_ERROR("bridge device not found\n"); |
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198 | return -1; |
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199 | } |
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200 | return 0; |
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201 | } |
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202 | |||
203 | |||
204 | /* Global for IPS driver to get at the current i915 device */ |
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205 | static struct drm_i915_private *i915_mch_dev; |
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206 | /* |
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207 | * Lock protecting IPS related data structures |
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208 | * - i915_mch_dev |
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209 | * - dev_priv->max_delay |
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210 | * - dev_priv->min_delay |
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211 | * - dev_priv->fmax |
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212 | * - dev_priv->gpu_busy |
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213 | */ |
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214 | static DEFINE_SPINLOCK(mchdev_lock); |
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215 | |||
216 | |||
217 | /** |
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218 | * i915_driver_load - setup chip and create an initial config |
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219 | * @dev: DRM device |
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220 | * @flags: startup flags |
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221 | * |
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222 | * The driver load routine has to do several things: |
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223 | * - drive output discovery via intel_modeset_init() |
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224 | * - initialize the memory manager |
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225 | * - allocate initial config memory |
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226 | * - setup the DRM framebuffer with the allocated memory |
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227 | */ |
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228 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
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229 | { |
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230 | struct drm_i915_private *dev_priv; |
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231 | int ret = 0, mmio_bar; |
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232 | uint32_t agp_size; |
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233 | |||
234 | ENTER(); |
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235 | |||
236 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
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237 | if (dev_priv == NULL) |
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238 | return -ENOMEM; |
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239 | |||
240 | dev->dev_private = (void *)dev_priv; |
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241 | dev_priv->dev = dev; |
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242 | dev_priv->info = (struct intel_device_info *) flags; |
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243 | |||
244 | if (i915_get_bridge_dev(dev)) { |
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245 | ret = -EIO; |
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246 | goto free_priv; |
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247 | } |
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248 | |||
249 | /* overlay on gen2 is broken and can't address above 1G */ |
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250 | // if (IS_GEN2(dev)) |
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251 | // dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
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252 | |||
253 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
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254 | * using 32bit addressing, overwriting memory if HWS is located |
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255 | * above 4GB. |
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256 | * |
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257 | * The documentation also mentions an issue with undefined |
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258 | * behaviour if any general state is accessed within a page above 4GB, |
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259 | * which also needs to be handled carefully. |
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260 | */ |
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261 | // if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
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262 | // dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); |
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263 | |||
264 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
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265 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0); |
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266 | if (!dev_priv->regs) { |
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267 | DRM_ERROR("failed to map registers\n"); |
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268 | ret = -EIO; |
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269 | goto put_bridge; |
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270 | } |
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271 | |||
272 | dev_priv->mm.gtt = intel_gtt_get(); |
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