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2330 | Serge | 1 | /* |
2 | * Copyright © 2006 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
28 | #include "dvo.h" |
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29 | |||
30 | /* |
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31 | * register definitions for the i82807aa. |
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32 | * |
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33 | * Documentation on this chipset can be found in datasheet #29069001 at |
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34 | * intel.com. |
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35 | */ |
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36 | |||
37 | /* |
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38 | * VCH Revision & GMBus Base Addr |
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39 | */ |
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40 | #define VR00 0x00 |
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41 | # define VR00_BASE_ADDRESS_MASK 0x007f |
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42 | |||
43 | /* |
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44 | * Functionality Enable |
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45 | */ |
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46 | #define VR01 0x01 |
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47 | |||
48 | /* |
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49 | * Enable the panel fitter |
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50 | */ |
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51 | # define VR01_PANEL_FIT_ENABLE (1 << 3) |
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52 | /* |
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53 | * Enables the LCD display. |
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54 | * |
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55 | * This must not be set while VR01_DVO_BYPASS_ENABLE is set. |
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56 | */ |
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57 | # define VR01_LCD_ENABLE (1 << 2) |
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58 | /** Enables the DVO repeater. */ |
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59 | # define VR01_DVO_BYPASS_ENABLE (1 << 1) |
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60 | /** Enables the DVO clock */ |
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61 | # define VR01_DVO_ENABLE (1 << 0) |
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62 | |||
63 | /* |
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64 | * LCD Interface Format |
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65 | */ |
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66 | #define VR10 0x10 |
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67 | /** Enables LVDS output instead of CMOS */ |
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68 | # define VR10_LVDS_ENABLE (1 << 4) |
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69 | /** Enables 18-bit LVDS output. */ |
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70 | # define VR10_INTERFACE_1X18 (0 << 2) |
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71 | /** Enables 24-bit LVDS or CMOS output */ |
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72 | # define VR10_INTERFACE_1X24 (1 << 2) |
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73 | /** Enables 2x18-bit LVDS or CMOS output. */ |
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74 | # define VR10_INTERFACE_2X18 (2 << 2) |
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75 | /** Enables 2x24-bit LVDS output */ |
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76 | # define VR10_INTERFACE_2X24 (3 << 2) |
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77 | |||
78 | /* |
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79 | * VR20 LCD Horizontal Display Size |
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80 | */ |
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81 | #define VR20 0x20 |
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82 | |||
83 | /* |
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84 | * LCD Vertical Display Size |
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85 | */ |
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86 | #define VR21 0x20 |
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87 | |||
88 | /* |
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89 | * Panel power down status |
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90 | */ |
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91 | #define VR30 0x30 |
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92 | /** Read only bit indicating that the panel is not in a safe poweroff state. */ |
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93 | # define VR30_PANEL_ON (1 << 15) |
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94 | |||
95 | #define VR40 0x40 |
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96 | # define VR40_STALL_ENABLE (1 << 13) |
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97 | # define VR40_VERTICAL_INTERP_ENABLE (1 << 12) |
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98 | # define VR40_ENHANCED_PANEL_FITTING (1 << 11) |
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99 | # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10) |
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100 | # define VR40_AUTO_RATIO_ENABLE (1 << 9) |
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101 | # define VR40_CLOCK_GATING_ENABLE (1 << 8) |
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102 | |||
103 | /* |
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104 | * Panel Fitting Vertical Ratio |
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105 | * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 |
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106 | */ |
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107 | #define VR41 0x41 |
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108 | |||
109 | /* |
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110 | * Panel Fitting Horizontal Ratio |
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111 | * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 |
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112 | */ |
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113 | #define VR42 0x42 |
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114 | |||
115 | /* |
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116 | * Horizontal Image Size |
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117 | */ |
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118 | #define VR43 0x43 |
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119 | |||
120 | /* VR80 GPIO 0 |
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121 | */ |
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122 | #define VR80 0x80 |
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123 | #define VR81 0x81 |
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124 | #define VR82 0x82 |
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125 | #define VR83 0x83 |
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126 | #define VR84 0x84 |
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127 | #define VR85 0x85 |
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128 | #define VR86 0x86 |
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129 | #define VR87 0x87 |
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130 | |||
131 | /* VR88 GPIO 8 |
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132 | */ |
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133 | #define VR88 0x88 |
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134 | |||
135 | /* Graphics BIOS scratch 0 |
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136 | */ |
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137 | #define VR8E 0x8E |
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138 | # define VR8E_PANEL_TYPE_MASK (0xf << 0) |
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139 | # define VR8E_PANEL_INTERFACE_CMOS (0 << 4) |
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140 | # define VR8E_PANEL_INTERFACE_LVDS (1 << 4) |
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141 | # define VR8E_FORCE_DEFAULT_PANEL (1 << 5) |
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142 | |||
143 | /* Graphics BIOS scratch 1 |
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144 | */ |
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145 | #define VR8F 0x8F |
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146 | # define VR8F_VCH_PRESENT (1 << 0) |
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147 | # define VR8F_DISPLAY_CONN (1 << 1) |
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148 | # define VR8F_POWER_MASK (0x3c) |
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149 | # define VR8F_POWER_POS (2) |
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150 | |||
151 | |||
152 | struct ivch_priv { |
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153 | bool quiet; |
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154 | |||
155 | uint16_t width, height; |
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156 | }; |
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157 | |||
158 | |||
159 | static void ivch_dump_regs(struct intel_dvo_device *dvo); |
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160 | |||
161 | /** |
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162 | * Reads a register on the ivch. |
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163 | * |
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164 | * Each of the 256 registers are 16 bits long. |
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165 | */ |
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166 | static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data) |
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167 | { |
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168 | struct ivch_priv *priv = dvo->dev_priv; |
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169 | struct i2c_adapter *adapter = dvo->i2c_bus; |
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170 | u8 out_buf[1]; |
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171 | u8 in_buf[2]; |
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172 | |||
173 | struct i2c_msg msgs[] = { |
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174 | { |
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175 | .addr = dvo->slave_addr, |
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176 | .flags = I2C_M_RD, |
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177 | .len = 0, |
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178 | }, |
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179 | { |
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180 | .addr = 0, |
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181 | .flags = I2C_M_NOSTART, |
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182 | .len = 1, |
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183 | .buf = out_buf, |
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184 | }, |
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185 | { |
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186 | .addr = dvo->slave_addr, |
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187 | .flags = I2C_M_RD | I2C_M_NOSTART, |
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188 | .len = 2, |
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189 | .buf = in_buf, |
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190 | } |
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191 | }; |
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192 | |||
193 | out_buf[0] = addr; |
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194 | |||
195 | if (i2c_transfer(adapter, msgs, 3) == 3) { |
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196 | *data = (in_buf[1] << 8) | in_buf[0]; |
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197 | return true; |
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198 | }; |
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199 | |||
200 | if (!priv->quiet) { |
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201 | DRM_DEBUG_KMS("Unable to read register 0x%02x from " |
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202 | "%s:%02x.\n", |
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203 | addr, adapter->name, dvo->slave_addr); |
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204 | } |
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205 | return false; |
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206 | } |
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207 | |||
208 | /** Writes a 16-bit register on the ivch */ |
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209 | static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data) |
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210 | { |
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211 | struct ivch_priv *priv = dvo->dev_priv; |
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212 | struct i2c_adapter *adapter = dvo->i2c_bus; |
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213 | u8 out_buf[3]; |
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214 | struct i2c_msg msg = { |
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215 | .addr = dvo->slave_addr, |
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216 | .flags = 0, |
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217 | .len = 3, |
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218 | .buf = out_buf, |
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219 | }; |
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220 | |||
221 | out_buf[0] = addr; |
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222 | out_buf[1] = data & 0xff; |
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223 | out_buf[2] = data >> 8; |
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224 | |||
225 | if (i2c_transfer(adapter, &msg, 1) == 1) |
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226 | return true; |
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227 | |||
228 | if (!priv->quiet) { |
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229 | DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", |
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230 | addr, adapter->name, dvo->slave_addr); |
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231 | } |
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232 | |||
233 | return false; |
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234 | } |
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235 | |||
236 | /** Probes the given bus and slave address for an ivch */ |
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237 | static bool ivch_init(struct intel_dvo_device *dvo, |
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238 | struct i2c_adapter *adapter) |
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239 | { |
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240 | struct ivch_priv *priv; |
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241 | uint16_t temp; |
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242 | |||
243 | priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL); |
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244 | if (priv == NULL) |
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245 | return false; |
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246 | |||
247 | dvo->i2c_bus = adapter; |
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248 | dvo->dev_priv = priv; |
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249 | priv->quiet = true; |
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250 | |||
251 | if (!ivch_read(dvo, VR00, &temp)) |
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252 | goto out; |
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253 | priv->quiet = false; |
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254 | |||
255 | /* Since the identification bits are probably zeroes, which doesn't seem |
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256 | * very unique, check that the value in the base address field matches |
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257 | * the address it's responding on. |
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258 | */ |
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259 | if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { |
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260 | DRM_DEBUG_KMS("ivch detect failed due to address mismatch " |
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261 | "(%d vs %d)\n", |
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262 | (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); |
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263 | goto out; |
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264 | } |
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265 | |||
266 | ivch_read(dvo, VR20, &priv->width); |
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267 | ivch_read(dvo, VR21, &priv->height); |
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268 | |||
269 | return true; |
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270 | |||
271 | out: |
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272 | kfree(priv); |
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273 | return false; |
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274 | } |
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275 | |||
276 | static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) |
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277 | { |
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278 | return connector_status_connected; |
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279 | } |
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280 | |||
281 | static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, |
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282 | struct drm_display_mode *mode) |
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283 | { |
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284 | if (mode->clock > 112000) |
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285 | return MODE_CLOCK_HIGH; |
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286 | |||
287 | return MODE_OK; |
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288 | } |
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289 | |||
290 | /** Sets the power state of the panel connected to the ivch */ |
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291 | static void ivch_dpms(struct intel_dvo_device *dvo, int mode) |
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292 | { |
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293 | int i; |
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294 | uint16_t vr01, vr30, backlight; |
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295 | |||
296 | /* Set the new power state of the panel. */ |
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297 | if (!ivch_read(dvo, VR01, &vr01)) |
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298 | return; |
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299 | |||
300 | if (mode == DRM_MODE_DPMS_ON) |
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301 | backlight = 1; |
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302 | else |
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303 | backlight = 0; |
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304 | ivch_write(dvo, VR80, backlight); |
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305 | |||
306 | if (mode == DRM_MODE_DPMS_ON) |
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307 | vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE; |
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308 | else |
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309 | vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE); |
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310 | |||
311 | ivch_write(dvo, VR01, vr01); |
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312 | |||
313 | /* Wait for the panel to make its state transition */ |
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314 | for (i = 0; i < 100; i++) { |
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315 | if (!ivch_read(dvo, VR30, &vr30)) |
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316 | break; |
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317 | |||
318 | if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DRM_MODE_DPMS_ON)) |
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319 | break; |
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320 | udelay(1000); |
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321 | } |
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322 | /* wait some more; vch may fail to resync sometimes without this */ |
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323 | udelay(16 * 1000); |
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324 | } |
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325 | |||
326 | static void ivch_mode_set(struct intel_dvo_device *dvo, |
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327 | struct drm_display_mode *mode, |
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328 | struct drm_display_mode *adjusted_mode) |
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329 | { |
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330 | uint16_t vr40 = 0; |
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331 | uint16_t vr01; |
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332 | |||
333 | vr01 = 0; |
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334 | vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | |
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335 | VR40_HORIZONTAL_INTERP_ENABLE); |
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336 | |||
337 | if (mode->hdisplay != adjusted_mode->hdisplay || |
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338 | mode->vdisplay != adjusted_mode->vdisplay) { |
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339 | uint16_t x_ratio, y_ratio; |
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340 | |||
341 | vr01 |= VR01_PANEL_FIT_ENABLE; |
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342 | vr40 |= VR40_CLOCK_GATING_ENABLE; |
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343 | x_ratio = (((mode->hdisplay - 1) << 16) / |
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344 | (adjusted_mode->hdisplay - 1)) >> 2; |
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345 | y_ratio = (((mode->vdisplay - 1) << 16) / |
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346 | (adjusted_mode->vdisplay - 1)) >> 2; |
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347 | ivch_write (dvo, VR42, x_ratio); |
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348 | ivch_write (dvo, VR41, y_ratio); |
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349 | } else { |
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350 | vr01 &= ~VR01_PANEL_FIT_ENABLE; |
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351 | vr40 &= ~VR40_CLOCK_GATING_ENABLE; |
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352 | } |
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353 | vr40 &= ~VR40_AUTO_RATIO_ENABLE; |
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354 | |||
355 | ivch_write(dvo, VR01, vr01); |
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356 | ivch_write(dvo, VR40, vr40); |
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357 | |||
358 | ivch_dump_regs(dvo); |
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359 | } |
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360 | |||
361 | static void ivch_dump_regs(struct intel_dvo_device *dvo) |
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362 | { |
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363 | uint16_t val; |
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364 | |||
365 | ivch_read(dvo, VR00, &val); |
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366 | DRM_LOG_KMS("VR00: 0x%04x\n", val); |
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367 | ivch_read(dvo, VR01, &val); |
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368 | DRM_LOG_KMS("VR01: 0x%04x\n", val); |
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369 | ivch_read(dvo, VR30, &val); |
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370 | DRM_LOG_KMS("VR30: 0x%04x\n", val); |
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371 | ivch_read(dvo, VR40, &val); |
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372 | DRM_LOG_KMS("VR40: 0x%04x\n", val); |
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373 | |||
374 | /* GPIO registers */ |
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375 | ivch_read(dvo, VR80, &val); |
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376 | DRM_LOG_KMS("VR80: 0x%04x\n", val); |
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377 | ivch_read(dvo, VR81, &val); |
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378 | DRM_LOG_KMS("VR81: 0x%04x\n", val); |
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379 | ivch_read(dvo, VR82, &val); |
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380 | DRM_LOG_KMS("VR82: 0x%04x\n", val); |
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381 | ivch_read(dvo, VR83, &val); |
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382 | DRM_LOG_KMS("VR83: 0x%04x\n", val); |
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383 | ivch_read(dvo, VR84, &val); |
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384 | DRM_LOG_KMS("VR84: 0x%04x\n", val); |
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385 | ivch_read(dvo, VR85, &val); |
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386 | DRM_LOG_KMS("VR85: 0x%04x\n", val); |
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387 | ivch_read(dvo, VR86, &val); |
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388 | DRM_LOG_KMS("VR86: 0x%04x\n", val); |
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389 | ivch_read(dvo, VR87, &val); |
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390 | DRM_LOG_KMS("VR87: 0x%04x\n", val); |
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391 | ivch_read(dvo, VR88, &val); |
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392 | DRM_LOG_KMS("VR88: 0x%04x\n", val); |
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393 | |||
394 | /* Scratch register 0 - AIM Panel type */ |
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395 | ivch_read(dvo, VR8E, &val); |
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396 | DRM_LOG_KMS("VR8E: 0x%04x\n", val); |
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397 | |||
398 | /* Scratch register 1 - Status register */ |
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399 | ivch_read(dvo, VR8F, &val); |
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400 | DRM_LOG_KMS("VR8F: 0x%04x\n", val); |
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401 | } |
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402 | |||
403 | static void ivch_destroy(struct intel_dvo_device *dvo) |
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404 | { |
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405 | struct ivch_priv *priv = dvo->dev_priv; |
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406 | |||
407 | if (priv) { |
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408 | kfree(priv); |
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409 | dvo->dev_priv = NULL; |
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410 | } |
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411 | } |
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412 | |||
413 | struct intel_dvo_dev_ops ivch_ops= { |
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414 | .init = ivch_init, |
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415 | .dpms = ivch_dpms, |
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416 | .mode_valid = ivch_mode_valid, |
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417 | .mode_set = ivch_mode_set, |
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418 | .detect = ivch_detect, |
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419 | .dump_regs = ivch_dump_regs, |
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420 | .destroy = ivch_destroy, |
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421 | };><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |