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2330 | Serge | 1 | /************************************************************************** |
2 | |||
3 | Copyright © 2006 Dave Airlie |
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4 | |||
5 | All Rights Reserved. |
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6 | |||
7 | Permission is hereby granted, free of charge, to any person obtaining a |
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8 | copy of this software and associated documentation files (the |
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9 | "Software"), to deal in the Software without restriction, including |
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10 | without limitation the rights to use, copy, modify, merge, publish, |
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11 | distribute, sub license, and/or sell copies of the Software, and to |
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12 | permit persons to whom the Software is furnished to do so, subject to |
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13 | the following conditions: |
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14 | |||
15 | The above copyright notice and this permission notice (including the |
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16 | next paragraph) shall be included in all copies or substantial portions |
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17 | of the Software. |
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18 | |||
19 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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20 | OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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21 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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22 | IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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23 | ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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24 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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25 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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26 | |||
27 | **************************************************************************/ |
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28 | |||
29 | #include "dvo.h" |
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30 | |||
31 | #define CH7xxx_REG_VID 0x4a |
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32 | #define CH7xxx_REG_DID 0x4b |
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33 | |||
34 | #define CH7011_VID 0x83 /* 7010 as well */ |
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35 | #define CH7009A_VID 0x84 |
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36 | #define CH7009B_VID 0x85 |
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37 | #define CH7301_VID 0x95 |
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38 | |||
39 | #define CH7xxx_VID 0x84 |
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40 | #define CH7xxx_DID 0x17 |
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41 | |||
42 | #define CH7xxx_NUM_REGS 0x4c |
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43 | |||
44 | #define CH7xxx_CM 0x1c |
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45 | #define CH7xxx_CM_XCM (1<<0) |
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46 | #define CH7xxx_CM_MCP (1<<2) |
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47 | #define CH7xxx_INPUT_CLOCK 0x1d |
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48 | #define CH7xxx_GPIO 0x1e |
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49 | #define CH7xxx_GPIO_HPIR (1<<3) |
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50 | #define CH7xxx_IDF 0x1f |
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51 | |||
52 | #define CH7xxx_IDF_HSP (1<<3) |
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53 | #define CH7xxx_IDF_VSP (1<<4) |
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54 | |||
55 | #define CH7xxx_CONNECTION_DETECT 0x20 |
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56 | #define CH7xxx_CDET_DVI (1<<5) |
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57 | |||
58 | #define CH7301_DAC_CNTL 0x21 |
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59 | #define CH7301_HOTPLUG 0x23 |
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60 | #define CH7xxx_TCTL 0x31 |
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61 | #define CH7xxx_TVCO 0x32 |
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62 | #define CH7xxx_TPCP 0x33 |
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63 | #define CH7xxx_TPD 0x34 |
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64 | #define CH7xxx_TPVT 0x35 |
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65 | #define CH7xxx_TLPF 0x36 |
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66 | #define CH7xxx_TCT 0x37 |
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67 | #define CH7301_TEST_PATTERN 0x48 |
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68 | |||
69 | #define CH7xxx_PM 0x49 |
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70 | #define CH7xxx_PM_FPD (1<<0) |
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71 | #define CH7301_PM_DACPD0 (1<<1) |
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72 | #define CH7301_PM_DACPD1 (1<<2) |
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73 | #define CH7301_PM_DACPD2 (1<<3) |
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74 | #define CH7xxx_PM_DVIL (1<<6) |
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75 | #define CH7xxx_PM_DVIP (1<<7) |
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76 | |||
77 | #define CH7301_SYNC_POLARITY 0x56 |
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78 | #define CH7301_SYNC_RGB_YUV (1<<0) |
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79 | #define CH7301_SYNC_POL_DVI (1<<5) |
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80 | |||
81 | /** @file |
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82 | * driver for the Chrontel 7xxx DVI chip over DVO. |
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83 | */ |
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84 | |||
85 | static struct ch7xxx_id_struct { |
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86 | uint8_t vid; |
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87 | char *name; |
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88 | } ch7xxx_ids[] = { |
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89 | { CH7011_VID, "CH7011" }, |
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90 | { CH7009A_VID, "CH7009A" }, |
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91 | { CH7009B_VID, "CH7009B" }, |
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92 | { CH7301_VID, "CH7301" }, |
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93 | }; |
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94 | |||
95 | struct ch7xxx_priv { |
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96 | bool quiet; |
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97 | }; |
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98 | |||
99 | static char *ch7xxx_get_id(uint8_t vid) |
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100 | { |
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101 | int i; |
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102 | |||
103 | for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) { |
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104 | if (ch7xxx_ids[i].vid == vid) |
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105 | return ch7xxx_ids[i].name; |
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106 | } |
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107 | |||
108 | return NULL; |
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109 | } |
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110 | |||
111 | /** Reads an 8 bit register */ |
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112 | static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) |
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113 | { |
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2342 | Serge | 114 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
2330 | Serge | 115 | struct i2c_adapter *adapter = dvo->i2c_bus; |
116 | u8 out_buf[2]; |
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117 | u8 in_buf[2]; |
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118 | |||
119 | struct i2c_msg msgs[] = { |
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120 | { |
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121 | .addr = dvo->slave_addr, |
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122 | .flags = 0, |
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123 | .len = 1, |
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124 | .buf = out_buf, |
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125 | }, |
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126 | { |
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127 | .addr = dvo->slave_addr, |
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128 | .flags = I2C_M_RD, |
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129 | .len = 1, |
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130 | .buf = in_buf, |
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131 | } |
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132 | }; |
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133 | |||
134 | out_buf[0] = addr; |
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135 | out_buf[1] = 0; |
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136 | |||
137 | if (i2c_transfer(adapter, msgs, 2) == 2) { |
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138 | *ch = in_buf[0]; |
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139 | return true; |
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140 | }; |
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141 | |||
142 | if (!ch7xxx->quiet) { |
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143 | DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", |
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144 | addr, adapter->name, dvo->slave_addr); |
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145 | } |
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146 | return false; |
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147 | } |
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148 | |||
149 | /** Writes an 8 bit register */ |
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150 | static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) |
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151 | { |
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152 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
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153 | struct i2c_adapter *adapter = dvo->i2c_bus; |
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154 | uint8_t out_buf[2]; |
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155 | struct i2c_msg msg = { |
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156 | .addr = dvo->slave_addr, |
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157 | .flags = 0, |
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158 | .len = 2, |
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159 | .buf = out_buf, |
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160 | }; |
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161 | |||
162 | out_buf[0] = addr; |
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163 | out_buf[1] = ch; |
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164 | |||
165 | if (i2c_transfer(adapter, &msg, 1) == 1) |
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166 | return true; |
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167 | |||
168 | if (!ch7xxx->quiet) { |
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169 | DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", |
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170 | addr, adapter->name, dvo->slave_addr); |
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171 | } |
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172 | |||
173 | return false; |
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174 | } |
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175 | |||
176 | static bool ch7xxx_init(struct intel_dvo_device *dvo, |
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177 | struct i2c_adapter *adapter) |
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178 | { |
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179 | /* this will detect the CH7xxx chip on the specified i2c bus */ |
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180 | struct ch7xxx_priv *ch7xxx; |
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181 | uint8_t vendor, device; |
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182 | char *name; |
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183 | |||
184 | ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL); |
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185 | if (ch7xxx == NULL) |
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186 | return false; |
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187 | |||
188 | dvo->i2c_bus = adapter; |
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189 | dvo->dev_priv = ch7xxx; |
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190 | ch7xxx->quiet = true; |
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191 | |||
192 | if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor)) |
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193 | goto out; |
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194 | |||
195 | name = ch7xxx_get_id(vendor); |
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196 | if (!name) { |
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197 | DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " |
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198 | "slave %d.\n", |
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199 | vendor, adapter->name, dvo->slave_addr); |
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200 | goto out; |
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201 | } |
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202 | |||
203 | |||
204 | if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device)) |
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205 | goto out; |
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206 | |||
207 | if (device != CH7xxx_DID) { |
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208 | DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " |
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209 | "slave %d.\n", |
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210 | vendor, adapter->name, dvo->slave_addr); |
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211 | goto out; |
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212 | } |
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213 | |||
214 | ch7xxx->quiet = false; |
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215 | DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", |
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216 | name, vendor, device); |
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217 | return true; |
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218 | out: |
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219 | kfree(ch7xxx); |
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220 | return false; |
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221 | } |
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222 | |||
223 | static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo) |
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224 | { |
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225 | uint8_t cdet, orig_pm, pm; |
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226 | |||
227 | ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm); |
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228 | |||
229 | pm = orig_pm; |
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230 | pm &= ~CH7xxx_PM_FPD; |
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231 | pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP; |
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232 | |||
233 | ch7xxx_writeb(dvo, CH7xxx_PM, pm); |
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234 | |||
235 | ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet); |
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236 | |||
237 | ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm); |
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238 | |||
239 | if (cdet & CH7xxx_CDET_DVI) |
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240 | return connector_status_connected; |
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241 | return connector_status_disconnected; |
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242 | } |
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243 | |||
244 | static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo, |
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245 | struct drm_display_mode *mode) |
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246 | { |
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247 | if (mode->clock > 165000) |
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248 | return MODE_CLOCK_HIGH; |
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249 | |||
250 | return MODE_OK; |
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251 | } |
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252 | |||
253 | static void ch7xxx_mode_set(struct intel_dvo_device *dvo, |
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254 | struct drm_display_mode *mode, |
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255 | struct drm_display_mode *adjusted_mode) |
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256 | { |
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257 | uint8_t tvco, tpcp, tpd, tlpf, idf; |
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258 | |||
259 | if (mode->clock <= 65000) { |
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260 | tvco = 0x23; |
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261 | tpcp = 0x08; |
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262 | tpd = 0x16; |
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263 | tlpf = 0x60; |
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264 | } else { |
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265 | tvco = 0x2d; |
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266 | tpcp = 0x06; |
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267 | tpd = 0x26; |
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268 | tlpf = 0xa0; |
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269 | } |
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270 | |||
271 | ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00); |
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272 | ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco); |
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273 | ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp); |
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274 | ch7xxx_writeb(dvo, CH7xxx_TPD, tpd); |
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275 | ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30); |
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276 | ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf); |
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277 | ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00); |
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278 | |||
279 | ch7xxx_readb(dvo, CH7xxx_IDF, &idf); |
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280 | |||
281 | idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); |
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282 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
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283 | idf |= CH7xxx_IDF_HSP; |
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284 | |||
285 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
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286 | idf |= CH7xxx_IDF_HSP; |
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287 | |||
288 | ch7xxx_writeb(dvo, CH7xxx_IDF, idf); |
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289 | } |
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290 | |||
291 | /* set the CH7xxx power state */ |
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292 | static void ch7xxx_dpms(struct intel_dvo_device *dvo, int mode) |
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293 | { |
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294 | if (mode == DRM_MODE_DPMS_ON) |
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295 | ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP); |
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296 | else |
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297 | ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD); |
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298 | } |
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299 | |||
300 | static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) |
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301 | { |
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302 | int i; |
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303 | |||
304 | for (i = 0; i < CH7xxx_NUM_REGS; i++) { |
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305 | uint8_t val; |
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2342 | Serge | 306 | if ((i % 8) == 0) |
2330 | Serge | 307 | DRM_LOG_KMS("\n %02X: ", i); |
308 | ch7xxx_readb(dvo, i, &val); |
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309 | DRM_LOG_KMS("%02X ", val); |
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310 | } |
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311 | } |
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312 | |||
313 | static void ch7xxx_destroy(struct intel_dvo_device *dvo) |
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314 | { |
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315 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
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316 | |||
317 | if (ch7xxx) { |
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318 | kfree(ch7xxx); |
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319 | dvo->dev_priv = NULL; |
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320 | } |
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321 | } |
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322 | |||
323 | struct intel_dvo_dev_ops ch7xxx_ops = { |
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324 | .init = ch7xxx_init, |
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325 | .detect = ch7xxx_detect, |
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326 | .mode_valid = ch7xxx_mode_valid, |
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327 | .mode_set = ch7xxx_mode_set, |
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328 | .dpms = ch7xxx_dpms, |
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329 | .dump_regs = ch7xxx_dump_regs, |
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330 | .destroy = ch7xxx_destroy, |
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331 | };>=>>5) |