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/*

 * Intel GTT (Graphics Translation Table) routines

 *

 * Caveat: This driver implements the linux agp interface, but this is far from

 * a agp driver! GTT support ended up here for purely historical reasons: The

 * old userspace intel graphics drivers needed an interface to map memory into

 * the GTT. And the drm provides a default interface for graphic devices sitting

 * on an agp port. So it made sense to fake the GTT support as an agp port to

 * avoid having to create a new api.

 *

 * With gem this does not make much sense anymore, just needlessly complicates

 * the code. But as long as the old graphics stack is still support, it's stuck

 * here.

 *

 * /fairy-tale-mode off

 */

#include 

#include 

#include 

#include 

#include 

#include 

//#include 

//#include 

//#include 

#include 

#include "agp.h"

#include "intel-agp.h"

#include 

#include 

struct pci_dev *

pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from);

#define PCI_VENDOR_ID_INTEL             0x8086

#define PCI_DEVICE_ID_INTEL_82830_HB    0x3575

#define PCI_DEVICE_ID_INTEL_82845G_HB   0x2560

#define PCI_DEVICE_ID_INTEL_82915G_IG   0x2582

#define PCI_DEVICE_ID_INTEL_82915GM_IG  0x2592

#define PCI_DEVICE_ID_INTEL_82945G_IG   0x2772

#define PCI_DEVICE_ID_INTEL_82945GM_IG  0x27A2

#define AGP_NORMAL_MEMORY 0

#define AGP_USER_TYPES (1 << 16)

#define AGP_USER_MEMORY (AGP_USER_TYPES)

#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)

/*

 * If we have Intel graphics, we're not going to have anything other than

 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent

 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).

 * Only newer chipsets need to bother with this, of course.

 */

#ifdef CONFIG_INTEL_IOMMU

#define USE_PCI_DMA_API 1

#else

#define USE_PCI_DMA_API 0

#endif

struct intel_gtt_driver {

    unsigned int gen : 8;

    unsigned int is_g33 : 1;

    unsigned int is_pineview : 1;

    unsigned int is_ironlake : 1;

    unsigned int has_pgtbl_enable : 1;

    unsigned int dma_mask_size : 8;

    /* Chipset specific GTT setup */

    int (*setup)(void);

    /* This should undo anything done in ->setup() save the unmapping

     * of the mmio register file, that's done in the generic code. */

    void (*cleanup)(void);

    void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);

    /* Flags is a more or less chipset specific opaque value.

     * For chipsets that need to support old ums (non-gem) code, this

     * needs to be identical to the various supported agp memory types! */

    bool (*check_flags)(unsigned int flags);

    void (*chipset_flush)(void);

};

static struct _intel_private {

    struct intel_gtt base;

    const struct intel_gtt_driver *driver;

    struct pci_dev *pcidev; /* device one */

    struct pci_dev *bridge_dev;

    u8 __iomem *registers;

    phys_addr_t gtt_bus_addr;

    u32 PGETBL_save;

    u32 __iomem *gtt;       /* I915G */

    bool clear_fake_agp; /* on first access via agp, fill with scratch */

    int num_dcache_entries;

    void __iomem *i9xx_flush_page;

    char *i81x_gtt_table;

    struct resource ifp_resource;

    int resource_valid;

    struct page *scratch_page;

	int refcount;

} intel_private;

#define INTEL_GTT_GEN   intel_private.driver->gen

#define IS_G33          intel_private.driver->is_g33

#define IS_PINEVIEW     intel_private.driver->is_pineview

#define IS_IRONLAKE     intel_private.driver->is_ironlake

#define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable

static int intel_gtt_setup_scratch_page(void)

{

	struct page *page;

	dma_addr_t dma_addr;

	page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);

	if (page == NULL)

        return -ENOMEM;

    intel_private.base.scratch_page_dma = page_to_phys(page);

	intel_private.scratch_page = page;

    return 0;

}

static unsigned int intel_gtt_stolen_size(void)

{

    u16 gmch_ctrl;

    u8 rdct;

    int local = 0;

    static const int ddt[4] = { 0, 16, 32, 64 };

    unsigned int stolen_size = 0;

    if (INTEL_GTT_GEN == 1)

        return 0; /* no stolen mem on i81x */

    pci_read_config_word(intel_private.bridge_dev,

                 I830_GMCH_CTRL, &gmch_ctrl);

    if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||

        intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {

        switch (gmch_ctrl & I830_GMCH_GMS_MASK) {

        case I830_GMCH_GMS_STOLEN_512:

            stolen_size = KB(512);

            break;

        case I830_GMCH_GMS_STOLEN_1024:

            stolen_size = MB(1);

            break;

        case I830_GMCH_GMS_STOLEN_8192:

            stolen_size = MB(8);

            break;

        case I830_GMCH_GMS_LOCAL:

            rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);

            stolen_size = (I830_RDRAM_ND(rdct) + 1) *

                    MB(ddt[I830_RDRAM_DDT(rdct)]);

            local = 1;

            break;

        default:

            stolen_size = 0;

            break;

        }

    } else {

        switch (gmch_ctrl & I855_GMCH_GMS_MASK) {

        case I855_GMCH_GMS_STOLEN_1M:

            stolen_size = MB(1);

            break;

        case I855_GMCH_GMS_STOLEN_4M:

            stolen_size = MB(4);

            break;

        case I855_GMCH_GMS_STOLEN_8M:

            stolen_size = MB(8);

            break;

        case I855_GMCH_GMS_STOLEN_16M:

            stolen_size = MB(16);

            break;

        case I855_GMCH_GMS_STOLEN_32M:

            stolen_size = MB(32);

            break;

        case I915_GMCH_GMS_STOLEN_48M:

            stolen_size = MB(48);

            break;

        case I915_GMCH_GMS_STOLEN_64M:

            stolen_size = MB(64);

            break;

        case G33_GMCH_GMS_STOLEN_128M:

            stolen_size = MB(128);

            break;

        case G33_GMCH_GMS_STOLEN_256M:

            stolen_size = MB(256);

            break;

        case INTEL_GMCH_GMS_STOLEN_96M:

            stolen_size = MB(96);

            break;

        case INTEL_GMCH_GMS_STOLEN_160M:

            stolen_size = MB(160);

            break;

        case INTEL_GMCH_GMS_STOLEN_224M:

            stolen_size = MB(224);

            break;

        case INTEL_GMCH_GMS_STOLEN_352M:

            stolen_size = MB(352);

            break;

        default:

            stolen_size = 0;

            break;

        }

    }

    if (stolen_size > 0) {

		dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",

               stolen_size / KB(1), local ? "local" : "stolen");

    } else {

		dev_info(&intel_private.bridge_dev->dev,

		       "no pre-allocated video memory detected\n");

        stolen_size = 0;

    }

    return stolen_size;

}

static void i965_adjust_pgetbl_size(unsigned int size_flag)

{

    u32 pgetbl_ctl, pgetbl_ctl2;

    /* ensure that ppgtt is disabled */

    pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);

    pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;

    writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);

    /* write the new ggtt size */

    pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);

    pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;

    pgetbl_ctl |= size_flag;

    writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);

}

static unsigned int i965_gtt_total_entries(void)

{

    int size;

    u32 pgetbl_ctl;

    u16 gmch_ctl;