WebSVN – Kolibri OS – Blame – /drivers/video/drm/drm_edid.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright (c) 2006 Luc Verhaegen (quirks list)
		3	* Copyright (c) 2007-2008 Intel Corporation
		4	* Jesse Barnes
1963	serge	5	* Copyright 2010 Red Hat, Inc.
1123	serge	6	*
		7	* DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
		8	* FB layer.
		9	* Copyright (C) 2006 Dennis Munsie
		10	*
		11	* Permission is hereby granted, free of charge, to any person obtaining a
		12	* copy of this software and associated documentation files (the "Software"),
		13	* to deal in the Software without restriction, including without limitation
		14	* the rights to use, copy, modify, merge, publish, distribute, sub license,
		15	* and/or sell copies of the Software, and to permit persons to whom the
		16	* Software is furnished to do so, subject to the following conditions:
		17	*
		18	* The above copyright notice and this permission notice (including the
		19	* next paragraph) shall be included in all copies or substantial portions
		20	* of the Software.
		21	*
		22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		23	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		24	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
		25	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		26	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		27	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		28	* DEALINGS IN THE SOFTWARE.
		29	*/
1221	serge	30	#include
1963	serge	31	#include
3480	Serge	32	#include
1125	serge	33	#include
3031	serge	34	#include
		35	#include
		36	#include
5271	serge	37	#include
1123	serge	38
1963	serge	39	#define version_greater(edid, maj, min) \
		40	(((edid)->version > (maj)) \|\| \
		41	((edid)->version == (maj) && (edid)->revision > (min)))
1123	serge	42
1963	serge	43	#define EDID_EST_TIMINGS 16
		44	#define EDID_STD_TIMINGS 8
		45	#define EDID_DETAILED_TIMINGS 4
		46
1123	serge	47	/*
		48	* EDID blocks out in the wild have a variety of bugs, try to collect
		49	* them here (note that userspace may work around broken monitors first,
		50	* but fixes should make their way here so that the kernel "just works"
		51	* on as many displays as possible).
		52	*/
		53
		54	/* First detailed mode wrong, use largest 60Hz mode */
		55	#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
		56	/* Reported 135MHz pixel clock is too high, needs adjustment */
		57	#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
		58	/* Prefer the largest mode at 75 Hz */
		59	#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
		60	/* Detail timing is in cm not mm */
		61	#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
		62	/* Detailed timing descriptors have bogus size values, so just take the
		63	* maximum size and use that.
		64	*/
		65	#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
		66	/* Monitor forgot to set the first detailed is preferred bit. */
		67	#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
		68	/* use +hsync +vsync for detailed mode */
		69	#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
3031	serge	70	/* Force reduced-blanking timings for detailed modes */
		71	#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
4539	Serge	72	/* Force 8bpc */
		73	#define EDID_QUIRK_FORCE_8BPC (1 << 8)
5060	serge	74	/* Force 12bpc */
		75	#define EDID_QUIRK_FORCE_12BPC (1 << 9)
6660	serge	76	/* Force 6bpc */
		77	#define EDID_QUIRK_FORCE_6BPC (1 << 10)
6935	serge	78	/* Force 10bpc */
		79	#define EDID_QUIRK_FORCE_10BPC (1 << 11)
1123	serge	80
1963	serge	81	struct detailed_mode_closure {
		82	struct drm_connector *connector;
		83	struct edid *edid;
		84	bool preferred;
		85	u32 quirks;
		86	int modes;
		87	};
1430	serge	88
1179	serge	89	#define LEVEL_DMT 0
		90	#define LEVEL_GTF 1
1963	serge	91	#define LEVEL_GTF2 2
		92	#define LEVEL_CVT 3
1179	serge	93
1123	serge	94	static struct edid_quirk {
3031	serge	95	char vendor[4];
1123	serge	96	int product_id;
		97	u32 quirks;
		98	} edid_quirk_list[] = {
		99	/* Acer AL1706 */
		100	{ "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
		101	/* Acer F51 */
		102	{ "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
		103	/* Unknown Acer */
		104	{ "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
		105
6660	serge	106	/* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
		107	{ "AEO", 0, EDID_QUIRK_FORCE_6BPC },
		108
1123	serge	109	/* Belinea 10 15 55 */
		110	{ "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
		111	{ "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
		112
		113	/* Envision Peripherals, Inc. EN-7100e */
		114	{ "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
1963	serge	115	/* Envision EN2028 */
		116	{ "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
1123	serge	117
		118	/* Funai Electronics PM36B */
		119	{ "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 \|
		120	EDID_QUIRK_DETAILED_IN_CM },
		121
6935	serge	122	/* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
		123	{ "LGD", 764, EDID_QUIRK_FORCE_10BPC },
		124
1123	serge	125	/* LG Philips LCD LP154W01-A5 */
		126	{ "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
		127	{ "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
		128
		129	/* Philips 107p5 CRT */
		130	{ "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
		131
		132	/* Proview AY765C */
		133	{ "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
		134
		135	/* Samsung SyncMaster 205BW. Note: irony */
		136	{ "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
		137	/* Samsung SyncMaster 22[5-6]BW */
		138	{ "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
		139	{ "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
3031	serge	140
5060	serge	141	/* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
		142	{ "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
		143
3031	serge	144	/* ViewSonic VA2026w */
		145	{ "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
4104	Serge	146
		147	/* Medion MD 30217 PG */
		148	{ "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
4539	Serge	149
		150	/* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
		151	{ "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
6935	serge	152
		153	/* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
		154	{ "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
1123	serge	155	};
		156
3480	Serge	157	/*
		158	* Autogenerated from the DMT spec.
		159	* This table is copied from xfree86/modes/xf86EdidModes.c.
		160	*/
		161	static const struct drm_display_mode drm_dmt_modes[] = {
6084	serge	162	/* 0x01 - 640x350@85Hz */
3480	Serge	163	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
		164	736, 832, 0, 350, 382, 385, 445, 0,
		165	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	166	/* 0x02 - 640x400@85Hz */
3480	Serge	167	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
		168	736, 832, 0, 400, 401, 404, 445, 0,
		169	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	170	/* 0x03 - 720x400@85Hz */
3480	Serge	171	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
		172	828, 936, 0, 400, 401, 404, 446, 0,
		173	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	174	/* 0x04 - 640x480@60Hz */
3480	Serge	175	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
6084	serge	176	752, 800, 0, 480, 490, 492, 525, 0,
3480	Serge	177	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	178	/* 0x05 - 640x480@72Hz */
3480	Serge	179	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
		180	704, 832, 0, 480, 489, 492, 520, 0,
		181	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	182	/* 0x06 - 640x480@75Hz */
3480	Serge	183	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
		184	720, 840, 0, 480, 481, 484, 500, 0,
		185	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	186	/* 0x07 - 640x480@85Hz */
3480	Serge	187	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
		188	752, 832, 0, 480, 481, 484, 509, 0,
		189	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	190	/* 0x08 - 800x600@56Hz */
3480	Serge	191	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
		192	896, 1024, 0, 600, 601, 603, 625, 0,
		193	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	194	/* 0x09 - 800x600@60Hz */
3480	Serge	195	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
		196	968, 1056, 0, 600, 601, 605, 628, 0,
		197	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	198	/* 0x0a - 800x600@72Hz */
3480	Serge	199	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
		200	976, 1040, 0, 600, 637, 643, 666, 0,
		201	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	202	/* 0x0b - 800x600@75Hz */
3480	Serge	203	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
		204	896, 1056, 0, 600, 601, 604, 625, 0,
		205	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	206	/* 0x0c - 800x600@85Hz */
3480	Serge	207	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
		208	896, 1048, 0, 600, 601, 604, 631, 0,
		209	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	210	/* 0x0d - 800x600@120Hz RB */
3480	Serge	211	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
		212	880, 960, 0, 600, 603, 607, 636, 0,
		213	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	214	/* 0x0e - 848x480@60Hz */
3480	Serge	215	{ DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
		216	976, 1088, 0, 480, 486, 494, 517, 0,
		217	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	218	/* 0x0f - 1024x768@43Hz, interlace */
3480	Serge	219	{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
		220	1208, 1264, 0, 768, 768, 772, 817, 0,
		221	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC \|
6084	serge	222	DRM_MODE_FLAG_INTERLACE) },
		223	/* 0x10 - 1024x768@60Hz */
3480	Serge	224	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
		225	1184, 1344, 0, 768, 771, 777, 806, 0,
		226	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	227	/* 0x11 - 1024x768@70Hz */
3480	Serge	228	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
		229	1184, 1328, 0, 768, 771, 777, 806, 0,
		230	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	231	/* 0x12 - 1024x768@75Hz */
3480	Serge	232	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
		233	1136, 1312, 0, 768, 769, 772, 800, 0,
		234	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	235	/* 0x13 - 1024x768@85Hz */
3480	Serge	236	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
		237	1168, 1376, 0, 768, 769, 772, 808, 0,
		238	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	239	/* 0x14 - 1024x768@120Hz RB */
3480	Serge	240	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
		241	1104, 1184, 0, 768, 771, 775, 813, 0,
		242	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	243	/* 0x15 - 1152x864@75Hz */
3480	Serge	244	{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
		245	1344, 1600, 0, 864, 865, 868, 900, 0,
		246	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	247	/* 0x55 - 1280x720@60Hz */
		248	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
		249	1430, 1650, 0, 720, 725, 730, 750, 0,
		250	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		251	/* 0x16 - 1280x768@60Hz RB */
3480	Serge	252	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
		253	1360, 1440, 0, 768, 771, 778, 790, 0,
		254	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	255	/* 0x17 - 1280x768@60Hz */
3480	Serge	256	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
		257	1472, 1664, 0, 768, 771, 778, 798, 0,
		258	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	259	/* 0x18 - 1280x768@75Hz */
3480	Serge	260	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
		261	1488, 1696, 0, 768, 771, 778, 805, 0,
6084	serge	262	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		263	/* 0x19 - 1280x768@85Hz */
3480	Serge	264	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
		265	1496, 1712, 0, 768, 771, 778, 809, 0,
		266	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	267	/* 0x1a - 1280x768@120Hz RB */
3480	Serge	268	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
		269	1360, 1440, 0, 768, 771, 778, 813, 0,
		270	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	271	/* 0x1b - 1280x800@60Hz RB */
3480	Serge	272	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
		273	1360, 1440, 0, 800, 803, 809, 823, 0,
		274	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	275	/* 0x1c - 1280x800@60Hz */
3480	Serge	276	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
		277	1480, 1680, 0, 800, 803, 809, 831, 0,
6084	serge	278	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		279	/* 0x1d - 1280x800@75Hz */
3480	Serge	280	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
		281	1488, 1696, 0, 800, 803, 809, 838, 0,
		282	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	283	/* 0x1e - 1280x800@85Hz */
3480	Serge	284	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
		285	1496, 1712, 0, 800, 803, 809, 843, 0,
		286	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	287	/* 0x1f - 1280x800@120Hz RB */
3480	Serge	288	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
		289	1360, 1440, 0, 800, 803, 809, 847, 0,
		290	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	291	/* 0x20 - 1280x960@60Hz */
3480	Serge	292	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
		293	1488, 1800, 0, 960, 961, 964, 1000, 0,
		294	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	295	/* 0x21 - 1280x960@85Hz */
3480	Serge	296	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
		297	1504, 1728, 0, 960, 961, 964, 1011, 0,
		298	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	299	/* 0x22 - 1280x960@120Hz RB */
3480	Serge	300	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
		301	1360, 1440, 0, 960, 963, 967, 1017, 0,
		302	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	303	/* 0x23 - 1280x1024@60Hz */
3480	Serge	304	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
		305	1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
		306	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	307	/* 0x24 - 1280x1024@75Hz */
3480	Serge	308	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
		309	1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
		310	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	311	/* 0x25 - 1280x1024@85Hz */
3480	Serge	312	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
		313	1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
		314	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	315	/* 0x26 - 1280x1024@120Hz RB */
3480	Serge	316	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
		317	1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
		318	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	319	/* 0x27 - 1360x768@60Hz */
3480	Serge	320	{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
		321	1536, 1792, 0, 768, 771, 777, 795, 0,
		322	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	323	/* 0x28 - 1360x768@120Hz RB */
3480	Serge	324	{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
		325	1440, 1520, 0, 768, 771, 776, 813, 0,
		326	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	327	/* 0x51 - 1366x768@60Hz */
		328	{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
		329	1579, 1792, 0, 768, 771, 774, 798, 0,
		330	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		331	/* 0x56 - 1366x768@60Hz */
		332	{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
		333	1436, 1500, 0, 768, 769, 772, 800, 0,
		334	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		335	/* 0x29 - 1400x1050@60Hz RB */
3480	Serge	336	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
		337	1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
		338	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	339	/* 0x2a - 1400x1050@60Hz */
3480	Serge	340	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
		341	1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
		342	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	343	/* 0x2b - 1400x1050@75Hz */
3480	Serge	344	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
		345	1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
		346	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	347	/* 0x2c - 1400x1050@85Hz */
3480	Serge	348	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
		349	1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
		350	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	351	/* 0x2d - 1400x1050@120Hz RB */
3480	Serge	352	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
		353	1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
		354	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	355	/* 0x2e - 1440x900@60Hz RB */
3480	Serge	356	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
		357	1520, 1600, 0, 900, 903, 909, 926, 0,
		358	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	359	/* 0x2f - 1440x900@60Hz */
3480	Serge	360	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
		361	1672, 1904, 0, 900, 903, 909, 934, 0,
		362	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	363	/* 0x30 - 1440x900@75Hz */
3480	Serge	364	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
		365	1688, 1936, 0, 900, 903, 909, 942, 0,
		366	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	367	/* 0x31 - 1440x900@85Hz */
3480	Serge	368	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
		369	1696, 1952, 0, 900, 903, 909, 948, 0,
		370	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	371	/* 0x32 - 1440x900@120Hz RB */
3480	Serge	372	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
		373	1520, 1600, 0, 900, 903, 909, 953, 0,
		374	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	375	/* 0x53 - 1600x900@60Hz */
		376	{ DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
		377	1704, 1800, 0, 900, 901, 904, 1000, 0,
		378	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		379	/* 0x33 - 1600x1200@60Hz */
3480	Serge	380	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
		381	1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
		382	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	383	/* 0x34 - 1600x1200@65Hz */
3480	Serge	384	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
		385	1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
		386	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	387	/* 0x35 - 1600x1200@70Hz */
3480	Serge	388	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
		389	1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
		390	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	391	/* 0x36 - 1600x1200@75Hz */
3480	Serge	392	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
		393	1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
		394	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	395	/* 0x37 - 1600x1200@85Hz */
3480	Serge	396	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
		397	1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
		398	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	399	/* 0x38 - 1600x1200@120Hz RB */
3480	Serge	400	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
		401	1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
		402	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	403	/* 0x39 - 1680x1050@60Hz RB */
3480	Serge	404	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
		405	1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
		406	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	407	/* 0x3a - 1680x1050@60Hz */
3480	Serge	408	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
		409	1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
		410	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	411	/* 0x3b - 1680x1050@75Hz */
3480	Serge	412	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
		413	1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
		414	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	415	/* 0x3c - 1680x1050@85Hz */
3480	Serge	416	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
		417	1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
		418	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	419	/* 0x3d - 1680x1050@120Hz RB */
3480	Serge	420	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
		421	1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
		422	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	423	/* 0x3e - 1792x1344@60Hz */
3480	Serge	424	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
		425	2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
		426	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	427	/* 0x3f - 1792x1344@75Hz */
3480	Serge	428	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
		429	2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
		430	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	431	/* 0x40 - 1792x1344@120Hz RB */
3480	Serge	432	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
		433	1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
		434	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	435	/* 0x41 - 1856x1392@60Hz */
3480	Serge	436	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
		437	2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
		438	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	439	/* 0x42 - 1856x1392@75Hz */
3480	Serge	440	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
6084	serge	441	2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
3480	Serge	442	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	443	/* 0x43 - 1856x1392@120Hz RB */
3480	Serge	444	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
		445	1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
		446	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	447	/* 0x52 - 1920x1080@60Hz */
		448	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
		449	2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
		450	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
		451	/* 0x44 - 1920x1200@60Hz RB */
3480	Serge	452	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
		453	2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
		454	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	455	/* 0x45 - 1920x1200@60Hz */
3480	Serge	456	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
		457	2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
		458	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	459	/* 0x46 - 1920x1200@75Hz */
3480	Serge	460	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
		461	2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
		462	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	463	/* 0x47 - 1920x1200@85Hz */
3480	Serge	464	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
		465	2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
		466	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	467	/* 0x48 - 1920x1200@120Hz RB */
3480	Serge	468	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
		469	2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
		470	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	471	/* 0x49 - 1920x1440@60Hz */
3480	Serge	472	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
		473	2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
		474	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	475	/* 0x4a - 1920x1440@75Hz */
3480	Serge	476	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
		477	2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
		478	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	479	/* 0x4b - 1920x1440@120Hz RB */
3480	Serge	480	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
		481	2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
		482	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	483	/* 0x54 - 2048x1152@60Hz */
		484	{ DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
		485	2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
		486	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		487	/* 0x4c - 2560x1600@60Hz RB */
3480	Serge	488	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
		489	2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
		490	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	491	/* 0x4d - 2560x1600@60Hz */
3480	Serge	492	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
		493	3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
		494	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	495	/* 0x4e - 2560x1600@75Hz */
3480	Serge	496	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
		497	3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
		498	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	499	/* 0x4f - 2560x1600@85Hz */
3480	Serge	500	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
		501	3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
		502	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) },
6084	serge	503	/* 0x50 - 2560x1600@120Hz RB */
3480	Serge	504	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
		505	2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
		506	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
6084	serge	507	/* 0x57 - 4096x2160@60Hz RB */
		508	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
		509	4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
		510	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
		511	/* 0x58 - 4096x2160@59.94Hz RB */
		512	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
		513	4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
		514	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC) },
3480	Serge	515	};
		516
4560	Serge	517	/*
		518	* These more or less come from the DMT spec. The 720x400 modes are
		519	* inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
		520	* modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
		521	* should be 1152x870, again for the Mac, but instead we use the x864 DMT
		522	* mode.
		523	*
		524	* The DMT modes have been fact-checked; the rest are mild guesses.
		525	*/
3480	Serge	526	static const struct drm_display_mode edid_est_modes[] = {
		527	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
		528	968, 1056, 0, 600, 601, 605, 628, 0,
		529	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
		530	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
		531	896, 1024, 0, 600, 601, 603, 625, 0,
		532	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
		533	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
		534	720, 840, 0, 480, 481, 484, 500, 0,
		535	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
		536	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
		537	704, 832, 0, 480, 489, 491, 520, 0,
		538	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
		539	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
		540	768, 864, 0, 480, 483, 486, 525, 0,
		541	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
		542	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
		543	752, 800, 0, 480, 490, 492, 525, 0,
		544	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
		545	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
		546	846, 900, 0, 400, 421, 423, 449, 0,
		547	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
		548	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
		549	846, 900, 0, 400, 412, 414, 449, 0,
		550	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
		551	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
		552	1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
		553	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
		554	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
		555	1136, 1312, 0, 768, 769, 772, 800, 0,
		556	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
		557	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
		558	1184, 1328, 0, 768, 771, 777, 806, 0,
		559	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
		560	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
		561	1184, 1344, 0, 768, 771, 777, 806, 0,
		562	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
		563	{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
		564	1208, 1264, 0, 768, 768, 776, 817, 0,
		565	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC \| DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
		566	{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
		567	928, 1152, 0, 624, 625, 628, 667, 0,
		568	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
		569	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
		570	896, 1056, 0, 600, 601, 604, 625, 0,
		571	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
		572	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
		573	976, 1040, 0, 600, 637, 643, 666, 0,
		574	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
		575	{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
		576	1344, 1600, 0, 864, 865, 868, 900, 0,
		577	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
		578	};
		579
		580	struct minimode {
		581	short w;
		582	short h;
		583	short r;
		584	short rb;
		585	};
		586
		587	static const struct minimode est3_modes[] = {
		588	/* byte 6 */
		589	{ 640, 350, 85, 0 },
		590	{ 640, 400, 85, 0 },
		591	{ 720, 400, 85, 0 },
		592	{ 640, 480, 85, 0 },
		593	{ 848, 480, 60, 0 },
		594	{ 800, 600, 85, 0 },
		595	{ 1024, 768, 85, 0 },
		596	{ 1152, 864, 75, 0 },
		597	/* byte 7 */
		598	{ 1280, 768, 60, 1 },
		599	{ 1280, 768, 60, 0 },
		600	{ 1280, 768, 75, 0 },
		601	{ 1280, 768, 85, 0 },
		602	{ 1280, 960, 60, 0 },
		603	{ 1280, 960, 85, 0 },
		604	{ 1280, 1024, 60, 0 },
		605	{ 1280, 1024, 85, 0 },
		606	/* byte 8 */
		607	{ 1360, 768, 60, 0 },
		608	{ 1440, 900, 60, 1 },
		609	{ 1440, 900, 60, 0 },
		610	{ 1440, 900, 75, 0 },
		611	{ 1440, 900, 85, 0 },
		612	{ 1400, 1050, 60, 1 },
		613	{ 1400, 1050, 60, 0 },
		614	{ 1400, 1050, 75, 0 },
		615	/* byte 9 */
		616	{ 1400, 1050, 85, 0 },
		617	{ 1680, 1050, 60, 1 },
		618	{ 1680, 1050, 60, 0 },
		619	{ 1680, 1050, 75, 0 },
		620	{ 1680, 1050, 85, 0 },
		621	{ 1600, 1200, 60, 0 },
		622	{ 1600, 1200, 65, 0 },
		623	{ 1600, 1200, 70, 0 },
		624	/* byte 10 */
		625	{ 1600, 1200, 75, 0 },
		626	{ 1600, 1200, 85, 0 },
		627	{ 1792, 1344, 60, 0 },
4560	Serge	628	{ 1792, 1344, 75, 0 },
3480	Serge	629	{ 1856, 1392, 60, 0 },
		630	{ 1856, 1392, 75, 0 },
		631	{ 1920, 1200, 60, 1 },
		632	{ 1920, 1200, 60, 0 },
		633	/* byte 11 */
		634	{ 1920, 1200, 75, 0 },
		635	{ 1920, 1200, 85, 0 },
		636	{ 1920, 1440, 60, 0 },
		637	{ 1920, 1440, 75, 0 },
		638	};
		639
		640	static const struct minimode extra_modes[] = {
		641	{ 1024, 576, 60, 0 },
		642	{ 1366, 768, 60, 0 },
		643	{ 1600, 900, 60, 0 },
		644	{ 1680, 945, 60, 0 },
		645	{ 1920, 1080, 60, 0 },
		646	{ 2048, 1152, 60, 0 },
		647	{ 2048, 1536, 60, 0 },
		648	};
		649
		650	/*
		651	* Probably taken from CEA-861 spec.
		652	* This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
		653	*/
		654	static const struct drm_display_mode edid_cea_modes[] = {
		655	/* 1 - 640x480@60Hz */
		656	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
		657	752, 800, 0, 480, 490, 492, 525, 0,
3746	Serge	658	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	659	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	660	/* 2 - 720x480@60Hz */
		661	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
		662	798, 858, 0, 480, 489, 495, 525, 0,
3746	Serge	663	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	664	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	665	/* 3 - 720x480@60Hz */
		666	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
		667	798, 858, 0, 480, 489, 495, 525, 0,
3746	Serge	668	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	669	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	670	/* 4 - 1280x720@60Hz */
		671	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
		672	1430, 1650, 0, 720, 725, 730, 750, 0,
3746	Serge	673	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	674	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	675	/* 5 - 1920x1080i@60Hz */
		676	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
		677	2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
		678	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC \|
3746	Serge	679	DRM_MODE_FLAG_INTERLACE),
4560	Serge	680	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
5271	serge	681	/* 6 - 720(1440)x480i@60Hz */
		682	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
		683	801, 858, 0, 480, 488, 494, 525, 0,
3480	Serge	684	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	685	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	686	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
5271	serge	687	/* 7 - 720(1440)x480i@60Hz */
		688	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
		689	801, 858, 0, 480, 488, 494, 525, 0,
3480	Serge	690	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	691	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	692	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
5271	serge	693	/* 8 - 720(1440)x240@60Hz */
		694	{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
		695	801, 858, 0, 240, 244, 247, 262, 0,
3480	Serge	696	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	697	DRM_MODE_FLAG_DBLCLK),
4560	Serge	698	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
5271	serge	699	/* 9 - 720(1440)x240@60Hz */
		700	{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
		701	801, 858, 0, 240, 244, 247, 262, 0,
3480	Serge	702	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	703	DRM_MODE_FLAG_DBLCLK),
4560	Serge	704	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	705	/* 10 - 2880x480i@60Hz */
		706	{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
		707	3204, 3432, 0, 480, 488, 494, 525, 0,
		708	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	709	DRM_MODE_FLAG_INTERLACE),
4560	Serge	710	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	711	/* 11 - 2880x480i@60Hz */
		712	{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
		713	3204, 3432, 0, 480, 488, 494, 525, 0,
		714	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	715	DRM_MODE_FLAG_INTERLACE),
4560	Serge	716	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	717	/* 12 - 2880x240@60Hz */
		718	{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
		719	3204, 3432, 0, 240, 244, 247, 262, 0,
3746	Serge	720	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	721	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	722	/* 13 - 2880x240@60Hz */
		723	{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
		724	3204, 3432, 0, 240, 244, 247, 262, 0,
3746	Serge	725	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	726	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	727	/* 14 - 1440x480@60Hz */
		728	{ DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
		729	1596, 1716, 0, 480, 489, 495, 525, 0,
3746	Serge	730	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	731	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	732	/* 15 - 1440x480@60Hz */
		733	{ DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
		734	1596, 1716, 0, 480, 489, 495, 525, 0,
3746	Serge	735	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	736	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	737	/* 16 - 1920x1080@60Hz */
		738	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
		739	2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
3746	Serge	740	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	741	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	742	/* 17 - 720x576@50Hz */
		743	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
		744	796, 864, 0, 576, 581, 586, 625, 0,
3746	Serge	745	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	746	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	747	/* 18 - 720x576@50Hz */
		748	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
		749	796, 864, 0, 576, 581, 586, 625, 0,
3746	Serge	750	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	751	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	752	/* 19 - 1280x720@50Hz */
		753	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
		754	1760, 1980, 0, 720, 725, 730, 750, 0,
3746	Serge	755	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	756	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	757	/* 20 - 1920x1080i@50Hz */
		758	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
		759	2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
		760	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC \|
3746	Serge	761	DRM_MODE_FLAG_INTERLACE),
4560	Serge	762	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
5271	serge	763	/* 21 - 720(1440)x576i@50Hz */
		764	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
		765	795, 864, 0, 576, 580, 586, 625, 0,
3480	Serge	766	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	767	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	768	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
5271	serge	769	/* 22 - 720(1440)x576i@50Hz */
		770	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
		771	795, 864, 0, 576, 580, 586, 625, 0,
3480	Serge	772	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	773	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	774	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
5271	serge	775	/* 23 - 720(1440)x288@50Hz */
		776	{ DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
		777	795, 864, 0, 288, 290, 293, 312, 0,
3480	Serge	778	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	779	DRM_MODE_FLAG_DBLCLK),
4560	Serge	780	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
5271	serge	781	/* 24 - 720(1440)x288@50Hz */
		782	{ DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
		783	795, 864, 0, 288, 290, 293, 312, 0,
3480	Serge	784	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	785	DRM_MODE_FLAG_DBLCLK),
4560	Serge	786	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	787	/* 25 - 2880x576i@50Hz */
		788	{ DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
		789	3180, 3456, 0, 576, 580, 586, 625, 0,
		790	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	791	DRM_MODE_FLAG_INTERLACE),
4560	Serge	792	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	793	/* 26 - 2880x576i@50Hz */
		794	{ DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
		795	3180, 3456, 0, 576, 580, 586, 625, 0,
		796	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	797	DRM_MODE_FLAG_INTERLACE),
4560	Serge	798	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	799	/* 27 - 2880x288@50Hz */
		800	{ DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
		801	3180, 3456, 0, 288, 290, 293, 312, 0,
3746	Serge	802	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	803	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	804	/* 28 - 2880x288@50Hz */
		805	{ DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
		806	3180, 3456, 0, 288, 290, 293, 312, 0,
3746	Serge	807	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	808	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	809	/* 29 - 1440x576@50Hz */
		810	{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
		811	1592, 1728, 0, 576, 581, 586, 625, 0,
3746	Serge	812	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	813	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	814	/* 30 - 1440x576@50Hz */
		815	{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
		816	1592, 1728, 0, 576, 581, 586, 625, 0,
3746	Serge	817	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	818	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	819	/* 31 - 1920x1080@50Hz */
		820	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
		821	2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
3746	Serge	822	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	823	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	824	/* 32 - 1920x1080@24Hz */
		825	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
		826	2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
3746	Serge	827	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	828	.vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	829	/* 33 - 1920x1080@25Hz */
		830	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
		831	2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
3746	Serge	832	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	833	.vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	834	/* 34 - 1920x1080@30Hz */
		835	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
		836	2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
3746	Serge	837	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	838	.vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	839	/* 35 - 2880x480@60Hz */
		840	{ DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
		841	3192, 3432, 0, 480, 489, 495, 525, 0,
3746	Serge	842	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	843	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	844	/* 36 - 2880x480@60Hz */
		845	{ DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
		846	3192, 3432, 0, 480, 489, 495, 525, 0,
3746	Serge	847	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	848	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	849	/* 37 - 2880x576@50Hz */
		850	{ DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
		851	3184, 3456, 0, 576, 581, 586, 625, 0,
3746	Serge	852	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	853	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	854	/* 38 - 2880x576@50Hz */
		855	{ DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
		856	3184, 3456, 0, 576, 581, 586, 625, 0,
3746	Serge	857	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	858	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	859	/* 39 - 1920x1080i@50Hz */
		860	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
		861	2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
		862	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	863	DRM_MODE_FLAG_INTERLACE),
4560	Serge	864	.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	865	/* 40 - 1920x1080i@100Hz */
		866	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
		867	2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
		868	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC \|
3746	Serge	869	DRM_MODE_FLAG_INTERLACE),
4560	Serge	870	.vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	871	/* 41 - 1280x720@100Hz */
		872	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
		873	1760, 1980, 0, 720, 725, 730, 750, 0,
3746	Serge	874	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	875	.vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	876	/* 42 - 720x576@100Hz */
		877	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
		878	796, 864, 0, 576, 581, 586, 625, 0,
3746	Serge	879	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	880	.vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	881	/* 43 - 720x576@100Hz */
		882	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
		883	796, 864, 0, 576, 581, 586, 625, 0,
3746	Serge	884	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	885	.vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
5271	serge	886	/* 44 - 720(1440)x576i@100Hz */
		887	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
		888	795, 864, 0, 576, 580, 586, 625, 0,
3480	Serge	889	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
5271	serge	890	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	891	.vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
5271	serge	892	/* 45 - 720(1440)x576i@100Hz */
		893	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
		894	795, 864, 0, 576, 580, 586, 625, 0,
3480	Serge	895	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
5271	serge	896	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	897	.vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	898	/* 46 - 1920x1080i@120Hz */
		899	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
		900	2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
		901	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC \|
3746	Serge	902	DRM_MODE_FLAG_INTERLACE),
4560	Serge	903	.vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	904	/* 47 - 1280x720@120Hz */
		905	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
		906	1430, 1650, 0, 720, 725, 730, 750, 0,
3746	Serge	907	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	908	.vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	909	/* 48 - 720x480@120Hz */
		910	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
		911	798, 858, 0, 480, 489, 495, 525, 0,
3746	Serge	912	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	913	.vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	914	/* 49 - 720x480@120Hz */
		915	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
		916	798, 858, 0, 480, 489, 495, 525, 0,
3746	Serge	917	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	918	.vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
5271	serge	919	/* 50 - 720(1440)x480i@120Hz */
		920	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
		921	801, 858, 0, 480, 488, 494, 525, 0,
3480	Serge	922	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	923	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	924	.vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
5271	serge	925	/* 51 - 720(1440)x480i@120Hz */
		926	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
		927	801, 858, 0, 480, 488, 494, 525, 0,
3480	Serge	928	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	929	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	930	.vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	931	/* 52 - 720x576@200Hz */
		932	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
		933	796, 864, 0, 576, 581, 586, 625, 0,
3746	Serge	934	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	935	.vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	936	/* 53 - 720x576@200Hz */
		937	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
		938	796, 864, 0, 576, 581, 586, 625, 0,
3746	Serge	939	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	940	.vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
5271	serge	941	/* 54 - 720(1440)x576i@200Hz */
		942	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
		943	795, 864, 0, 576, 580, 586, 625, 0,
3480	Serge	944	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	945	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	946	.vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
5271	serge	947	/* 55 - 720(1440)x576i@200Hz */
		948	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
		949	795, 864, 0, 576, 580, 586, 625, 0,
3480	Serge	950	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	951	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	952	.vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	953	/* 56 - 720x480@240Hz */
		954	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
		955	798, 858, 0, 480, 489, 495, 525, 0,
3746	Serge	956	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	957	.vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
3480	Serge	958	/* 57 - 720x480@240Hz */
		959	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
		960	798, 858, 0, 480, 489, 495, 525, 0,
3746	Serge	961	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
4560	Serge	962	.vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
5271	serge	963	/* 58 - 720(1440)x480i@240 */
		964	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
		965	801, 858, 0, 480, 488, 494, 525, 0,
3480	Serge	966	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	967	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	968	.vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
5271	serge	969	/* 59 - 720(1440)x480i@240 */
		970	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
		971	801, 858, 0, 480, 488, 494, 525, 0,
3480	Serge	972	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC \|
3746	Serge	973	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
4560	Serge	974	.vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	975	/* 60 - 1280x720@24Hz */
		976	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
		977	3080, 3300, 0, 720, 725, 730, 750, 0,
3746	Serge	978	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	979	.vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	980	/* 61 - 1280x720@25Hz */
		981	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
		982	3740, 3960, 0, 720, 725, 730, 750, 0,
3746	Serge	983	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	984	.vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	985	/* 62 - 1280x720@30Hz */
		986	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
		987	3080, 3300, 0, 720, 725, 730, 750, 0,
3746	Serge	988	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	989	.vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	990	/* 63 - 1920x1080@120Hz */
		991	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
		992	2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
3746	Serge	993	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	994	.vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	995	/* 64 - 1920x1080@100Hz */
		996	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
		997	2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
3746	Serge	998	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
4560	Serge	999	.vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
3480	Serge	1000	};
		1001
4104	Serge	1002	/*
		1003	* HDMI 1.4 4k modes.
		1004	*/
		1005	static const struct drm_display_mode edid_4k_modes[] = {
		1006	/* 1 - 3840x2160@30Hz */
		1007	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
		1008	3840, 4016, 4104, 4400, 0,
		1009	2160, 2168, 2178, 2250, 0,
		1010	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
		1011	.vrefresh = 30, },
		1012	/* 2 - 3840x2160@25Hz */
		1013	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
		1014	3840, 4896, 4984, 5280, 0,
		1015	2160, 2168, 2178, 2250, 0,
		1016	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
		1017	.vrefresh = 25, },
		1018	/* 3 - 3840x2160@24Hz */
		1019	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
		1020	3840, 5116, 5204, 5500, 0,
		1021	2160, 2168, 2178, 2250, 0,
		1022	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
		1023	.vrefresh = 24, },
		1024	/* 4 - 4096x2160@24Hz (SMPTE) */
		1025	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
		1026	4096, 5116, 5204, 5500, 0,
		1027	2160, 2168, 2178, 2250, 0,
		1028	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
		1029	.vrefresh = 24, },
		1030	};
		1031
1963	serge	1032	/* DDC fetch and block validation */
1123	serge	1033
1221	serge	1034	static const u8 edid_header[] = {
		1035	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
		1036	};
1123	serge	1037
5060	serge	1038	/**
		1039	* drm_edid_header_is_valid - sanity check the header of the base EDID block
		1040	* @raw_edid: pointer to raw base EDID block
		1041	*
		1042	* Sanity check the header of the base EDID block.
		1043	*
		1044	* Return: 8 if the header is perfect, down to 0 if it's totally wrong.
2160	serge	1045	*/
		1046	int drm_edid_header_is_valid(const u8 *raw_edid)
		1047	{
		1048	int i, score = 0;
		1049
		1050	for (i = 0; i < sizeof(edid_header); i++)
		1051	if (raw_edid[i] == edid_header[i])
		1052	score++;
		1053
		1054	return score;
		1055	}
		1056	EXPORT_SYMBOL(drm_edid_header_is_valid);
		1057
3031	serge	1058	static int edid_fixup __read_mostly = 6;
3480	Serge	1059	module_param_named(edid_fixup, edid_fixup, int, 0400);
		1060	MODULE_PARM_DESC(edid_fixup,
		1061	"Minimum number of valid EDID header bytes (0-8, default 6)");
2160	serge	1062
5271	serge	1063	static void drm_get_displayid(struct drm_connector *connector,
		1064	struct edid *edid);
		1065
		1066	static int drm_edid_block_checksum(const u8 *raw_edid)
		1067	{
		1068	int i;
		1069	u8 csum = 0;
		1070	for (i = 0; i < EDID_LENGTH; i++)
		1071	csum += raw_edid[i];
		1072
		1073	return csum;
		1074	}
		1075
		1076	static bool drm_edid_is_zero(const u8 *in_edid, int length)
		1077	{
		1078	if (memchr_inv(in_edid, 0, length))
		1079	return false;
		1080
		1081	return true;
		1082	}
		1083
5060	serge	1084	/**
		1085	* drm_edid_block_valid - Sanity check the EDID block (base or extension)
		1086	* @raw_edid: pointer to raw EDID block
		1087	* @block: type of block to validate (0 for base, extension otherwise)
		1088	* @print_bad_edid: if true, dump bad EDID blocks to the console
6084	serge	1089	* @edid_corrupt: if true, the header or checksum is invalid
5060	serge	1090	*
		1091	* Validate a base or extension EDID block and optionally dump bad blocks to
		1092	* the console.
		1093	*
		1094	* Return: True if the block is valid, false otherwise.
1123	serge	1095	*/
6084	serge	1096	bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
		1097	bool *edid_corrupt)
1123	serge	1098	{
5271	serge	1099	u8 csum;
1963	serge	1100	struct edid edid = (struct edid )raw_edid;
1123	serge	1101
4075	Serge	1102	if (WARN_ON(!raw_edid))
		1103	return false;
		1104
3031	serge	1105	if (edid_fixup > 8 \|\| edid_fixup < 0)
		1106	edid_fixup = 6;
		1107
		1108	if (block == 0) {
2160	serge	1109	int score = drm_edid_header_is_valid(raw_edid);
6084	serge	1110	if (score == 8) {
		1111	if (edid_corrupt)
		1112	*edid_corrupt = false;
		1113	} else if (score >= edid_fixup) {
		1114	/* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
		1115	* The corrupt flag needs to be set here otherwise, the
		1116	* fix-up code here will correct the problem, the
		1117	* checksum is correct and the test fails
		1118	*/
		1119	if (edid_corrupt)
		1120	*edid_corrupt = true;
		1121	DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
		1122	memcpy(raw_edid, edid_header, sizeof(edid_header));
1963	serge	1123	} else {
6084	serge	1124	if (edid_corrupt)
		1125	*edid_corrupt = true;
		1126	goto bad;
1963	serge	1127	}
		1128	}
1123	serge	1129
5271	serge	1130	csum = drm_edid_block_checksum(raw_edid);
1123	serge	1131	if (csum) {
3120	serge	1132	if (print_bad_edid) {
6084	serge	1133	DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
3120	serge	1134	}
1963	serge	1135
6084	serge	1136	if (edid_corrupt)
		1137	*edid_corrupt = true;
		1138
1963	serge	1139	/* allow CEA to slide through, switches mangle this */
		1140	if (raw_edid[0] != 0x02)
6084	serge	1141	goto bad;
1123	serge	1142	}
		1143
1963	serge	1144	/* per-block-type checks */
		1145	switch (raw_edid[0]) {
		1146	case 0: /* base */
6084	serge	1147	if (edid->version != 1) {
		1148	DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
		1149	goto bad;
		1150	}
1321	serge	1151
6084	serge	1152	if (edid->revision > 4)
		1153	DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1963	serge	1154	break;
1321	serge	1155
1963	serge	1156	default:
		1157	break;
		1158	}
		1159
4075	Serge	1160	return true;
1123	serge	1161
		1162	bad:
4075	Serge	1163	if (print_bad_edid) {
5271	serge	1164	if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
		1165	printk(KERN_ERR "EDID block is all zeroes\n");
		1166	} else {
6084	serge	1167	printk(KERN_ERR "Raw EDID:\n");
		1168	print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
3480	Serge	1169	raw_edid, EDID_LENGTH, false);
6084	serge	1170	}
1123	serge	1171	}
4075	Serge	1172	return false;
1123	serge	1173	}
3031	serge	1174	EXPORT_SYMBOL(drm_edid_block_valid);
1963	serge	1175
		1176	/**
		1177	* drm_edid_is_valid - sanity check EDID data
		1178	* @edid: EDID data
		1179	*
		1180	* Sanity-check an entire EDID record (including extensions)
5060	serge	1181	*
		1182	* Return: True if the EDID data is valid, false otherwise.
1963	serge	1183	*/
		1184	bool drm_edid_is_valid(struct edid *edid)
		1185	{
		1186	int i;
		1187	u8 raw = (u8 )edid;
		1188
		1189	if (!edid)
		1190	return false;
		1191
		1192	for (i = 0; i <= edid->extensions; i++)
6084	serge	1193	if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1963	serge	1194	return false;
		1195
		1196	return true;
		1197	}
1430	serge	1198	EXPORT_SYMBOL(drm_edid_is_valid);
1123	serge	1199
1963	serge	1200	#define DDC_SEGMENT_ADDR 0x30
1123	serge	1201	/**
5060	serge	1202	* drm_do_probe_ddc_edid() - get EDID information via I2C
5271	serge	1203	* @data: I2C device adapter
5060	serge	1204	* @buf: EDID data buffer to be filled
		1205	* @block: 128 byte EDID block to start fetching from
		1206	* @len: EDID data buffer length to fetch
1963	serge	1207	*
5060	serge	1208	* Try to fetch EDID information by calling I2C driver functions.
1963	serge	1209	*
5060	serge	1210	* Return: 0 on success or -1 on failure.
1963	serge	1211	*/
		1212	static int
5271	serge	1213	drm_do_probe_ddc_edid(void data, u8 buf, unsigned int block, size_t len)
1963	serge	1214	{
5271	serge	1215	struct i2c_adapter *adapter = data;
1963	serge	1216	unsigned char start = block * EDID_LENGTH;
3031	serge	1217	unsigned char segment = block >> 1;
		1218	unsigned char xfers = segment ? 3 : 2;
1963	serge	1219	int ret, retries = 5;
		1220
5060	serge	1221	/*
		1222	* The core I2C driver will automatically retry the transfer if the
1963	serge	1223	* adapter reports EAGAIN. However, we find that bit-banging transfers
		1224	* are susceptible to errors under a heavily loaded machine and
		1225	* generate spurious NAKs and timeouts. Retrying the transfer
		1226	* of the individual block a few times seems to overcome this.
		1227	*/
		1228	do {
6084	serge	1229	struct i2c_msg msgs[] = {
		1230	{
3031	serge	1231	.addr = DDC_SEGMENT_ADDR,
		1232	.flags = 0,
		1233	.len = 1,
		1234	.buf = &segment,
		1235	}, {
6084	serge	1236	.addr = DDC_ADDR,
		1237	.flags = 0,
		1238	.len = 1,
		1239	.buf = &start,
		1240	}, {
		1241	.addr = DDC_ADDR,
		1242	.flags = I2C_M_RD,
		1243	.len = len,
		1244	.buf = buf,
		1245	}
		1246	};
1963	serge	1247
6084	serge	1248	/*
5060	serge	1249	* Avoid sending the segment addr to not upset non-compliant
		1250	* DDC monitors.
6084	serge	1251	*/
3031	serge	1252	ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
		1253
		1254	if (ret == -ENXIO) {
		1255	DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
		1256	adapter->name);
		1257	break;
		1258	}
		1259	} while (ret != xfers && --retries);
		1260
		1261	return ret == xfers ? 0 : -1;
1963	serge	1262	}
		1263
5271	serge	1264	/**
		1265	* drm_do_get_edid - get EDID data using a custom EDID block read function
		1266	* @connector: connector we're probing
		1267	* @get_edid_block: EDID block read function
		1268	* @data: private data passed to the block read function
		1269	*
		1270	* When the I2C adapter connected to the DDC bus is hidden behind a device that
		1271	* exposes a different interface to read EDID blocks this function can be used
		1272	* to get EDID data using a custom block read function.
		1273	*
		1274	* As in the general case the DDC bus is accessible by the kernel at the I2C
		1275	* level, drivers must make all reasonable efforts to expose it as an I2C
		1276	* adapter and use drm_get_edid() instead of abusing this function.
		1277	*
		1278	* Return: Pointer to valid EDID or NULL if we couldn't find any.
		1279	*/
		1280	struct edid drm_do_get_edid(struct drm_connector connector,
		1281	int (get_edid_block)(void data, u8 *buf, unsigned int block,
		1282	size_t len),
		1283	void *data)
2004	serge	1284	{
1963	serge	1285	int i, j = 0, valid_extensions = 0;
		1286	u8 block, new;
3031	serge	1287	bool print_bad_edid = !connector->bad_edid_counter \|\| (drm_debug & DRM_UT_KMS);
1963	serge	1288
		1289	if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
		1290	return NULL;
		1291
		1292	/* base block fetch */
		1293	for (i = 0; i < 4; i++) {
5271	serge	1294	if (get_edid_block(data, block, 0, EDID_LENGTH))
6084	serge	1295	goto out;
		1296	if (drm_edid_block_valid(block, 0, print_bad_edid,
		1297	&connector->edid_corrupt))
1963	serge	1298	break;
2004	serge	1299	if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
		1300	connector->null_edid_counter++;
		1301	goto carp;
		1302	}
1963	serge	1303	}
		1304	if (i == 4)
		1305	goto carp;
		1306
		1307	/* if there's no extensions, we're done */
		1308	if (block[0x7e] == 0)
5271	serge	1309	return (struct edid *)block;
1963	serge	1310
3480	Serge	1311	new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1963	serge	1312	if (!new)
		1313	goto out;
		1314	block = new;
		1315
		1316	for (j = 1; j <= block[0x7e]; j++) {
		1317	for (i = 0; i < 4; i++) {
5271	serge	1318	if (get_edid_block(data,
1963	serge	1319	block + (valid_extensions + 1) * EDID_LENGTH,
		1320	j, EDID_LENGTH))
		1321	goto out;
6084	serge	1322	if (drm_edid_block_valid(block + (valid_extensions + 1)
		1323	* EDID_LENGTH, j,
		1324	print_bad_edid,
		1325	NULL)) {
1963	serge	1326	valid_extensions++;
		1327	break;
6084	serge	1328	}
1963	serge	1329	}
3480	Serge	1330
		1331	if (i == 4 && print_bad_edid) {
1963	serge	1332	dev_warn(connector->dev->dev,
		1333	"%s: Ignoring invalid EDID block %d.\n",
5060	serge	1334	connector->name, j);
3480	Serge	1335
		1336	connector->bad_edid_counter++;
		1337	}
1963	serge	1338	}
		1339
		1340	if (valid_extensions != block[0x7e]) {
		1341	block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
		1342	block[0x7e] = valid_extensions;
3480	Serge	1343	new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
6084	serge	1344	if (!new)
1963	serge	1345	goto out;
		1346	block = new;
		1347	}
		1348
5271	serge	1349	return (struct edid *)block;
1963	serge	1350
		1351	carp:
3031	serge	1352	if (print_bad_edid) {
6084	serge	1353	dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
5060	serge	1354	connector->name, j);
3031	serge	1355	}
		1356	connector->bad_edid_counter++;
1963	serge	1357
		1358	out:
		1359	kfree(block);
		1360	return NULL;
		1361	}
5271	serge	1362	EXPORT_SYMBOL_GPL(drm_do_get_edid);
1963	serge	1363
		1364	/**
5060	serge	1365	* drm_probe_ddc() - probe DDC presence
		1366	* @adapter: I2C adapter to probe
1963	serge	1367	*
5060	serge	1368	* Return: True on success, false on failure.
1963	serge	1369	*/
3031	serge	1370	bool
1963	serge	1371	drm_probe_ddc(struct i2c_adapter *adapter)
		1372	{
		1373	unsigned char out;
		1374
		1375	return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
		1376	}
3031	serge	1377	EXPORT_SYMBOL(drm_probe_ddc);
1963	serge	1378
		1379	/**
		1380	* drm_get_edid - get EDID data, if available
		1381	* @connector: connector we're probing
5060	serge	1382	* @adapter: I2C adapter to use for DDC
1963	serge	1383	*
5060	serge	1384	* Poke the given I2C channel to grab EDID data if possible. If found,
1963	serge	1385	* attach it to the connector.
		1386	*
5060	serge	1387	* Return: Pointer to valid EDID or NULL if we couldn't find any.
1963	serge	1388	*/
		1389	struct edid drm_get_edid(struct drm_connector connector,
		1390	struct i2c_adapter *adapter)
		1391	{
5271	serge	1392	struct edid *edid;
1963	serge	1393
5271	serge	1394	if (!drm_probe_ddc(adapter))
		1395	return NULL;
1963	serge	1396
5271	serge	1397	edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
		1398	if (edid)
		1399	drm_get_displayid(connector, edid);
1963	serge	1400	return edid;
		1401	}
		1402	EXPORT_SYMBOL(drm_get_edid);
		1403
4560	Serge	1404	/**
		1405	* drm_edid_duplicate - duplicate an EDID and the extensions
		1406	* @edid: EDID to duplicate
		1407	*
5060	serge	1408	* Return: Pointer to duplicated EDID or NULL on allocation failure.
4560	Serge	1409	*/
		1410	struct edid drm_edid_duplicate(const struct edid edid)
		1411	{
		1412	return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
		1413	}
		1414	EXPORT_SYMBOL(drm_edid_duplicate);
		1415
1963	serge	1416	/* EDID parsing */
		1417
		1418	/**
1123	serge	1419	* edid_vendor - match a string against EDID's obfuscated vendor field
		1420	* @edid: EDID to match
		1421	* @vendor: vendor string
		1422	*
		1423	* Returns true if @vendor is in @edid, false otherwise
		1424	*/
		1425	static bool edid_vendor(struct edid edid, char vendor)
		1426	{
		1427	char edid_vendor[3];
		1428
		1429	edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
		1430	edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) \|
		1431	((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
		1432	edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
		1433
		1434	return !strncmp(edid_vendor, vendor, 3);
		1435	}
		1436
		1437	/**
		1438	* edid_get_quirks - return quirk flags for a given EDID
		1439	* @edid: EDID to process
		1440	*
		1441	* This tells subsequent routines what fixes they need to apply.
		1442	*/
		1443	static u32 edid_get_quirks(struct edid *edid)
		1444	{
		1445	struct edid_quirk *quirk;
		1446	int i;
		1447
		1448	for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
		1449	quirk = &edid_quirk_list[i];
		1450
		1451	if (edid_vendor(edid, quirk->vendor) &&
		1452	(EDID_PRODUCT_ID(edid) == quirk->product_id))
		1453	return quirk->quirks;
		1454	}
		1455
		1456	return 0;
		1457	}
		1458
		1459	#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
4560	Serge	1460	#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1123	serge	1461
		1462	/**
		1463	* edid_fixup_preferred - set preferred modes based on quirk list
		1464	* @connector: has mode list to fix up
		1465	* @quirks: quirks list
		1466	*
		1467	* Walk the mode list for @connector, clearing the preferred status
		1468	* on existing modes and setting it anew for the right mode ala @quirks.
		1469	*/
		1470	static void edid_fixup_preferred(struct drm_connector *connector,
		1471	u32 quirks)
		1472	{
		1473	struct drm_display_mode t, cur_mode, *preferred_mode;
		1474	int target_refresh = 0;
4560	Serge	1475	int cur_vrefresh, preferred_vrefresh;
1123	serge	1476
		1477	if (list_empty(&connector->probed_modes))
		1478	return;
		1479
		1480	if (quirks & EDID_QUIRK_PREFER_LARGE_60)
		1481	target_refresh = 60;
		1482	if (quirks & EDID_QUIRK_PREFER_LARGE_75)
		1483	target_refresh = 75;
		1484
		1485	preferred_mode = list_first_entry(&connector->probed_modes,
		1486	struct drm_display_mode, head);
		1487
		1488	list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
		1489	cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
		1490
		1491	if (cur_mode == preferred_mode)
		1492	continue;
		1493
		1494	/* Largest mode is preferred */
		1495	if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
		1496	preferred_mode = cur_mode;
		1497
4560	Serge	1498	cur_vrefresh = cur_mode->vrefresh ?
		1499	cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
		1500	preferred_vrefresh = preferred_mode->vrefresh ?
		1501	preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1123	serge	1502	/* At a given size, try to get closest to target refresh */
		1503	if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
4560	Serge	1504	MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
		1505	MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1123	serge	1506	preferred_mode = cur_mode;
		1507	}
		1508	}
		1509
		1510	preferred_mode->type \|= DRM_MODE_TYPE_PREFERRED;
		1511	}
		1512
3031	serge	1513	static bool
		1514	mode_is_rb(const struct drm_display_mode *mode)
		1515	{
		1516	return (mode->htotal - mode->hdisplay == 160) &&
		1517	(mode->hsync_end - mode->hdisplay == 80) &&
		1518	(mode->hsync_end - mode->hsync_start == 32) &&
		1519	(mode->vsync_start - mode->vdisplay == 3);
		1520	}
		1521
		1522	/*
		1523	* drm_mode_find_dmt - Create a copy of a mode if present in DMT
		1524	* @dev: Device to duplicate against
		1525	* @hsize: Mode width
		1526	* @vsize: Mode height
		1527	* @fresh: Mode refresh rate
		1528	* @rb: Mode reduced-blanking-ness
		1529	*
		1530	* Walk the DMT mode list looking for a match for the given parameters.
5060	serge	1531	*
		1532	* Return: A newly allocated copy of the mode, or NULL if not found.
3031	serge	1533	*/
1963	serge	1534	struct drm_display_mode drm_mode_find_dmt(struct drm_device dev,
3031	serge	1535	int hsize, int vsize, int fresh,
		1536	bool rb)
1179	serge	1537	{
1321	serge	1538	int i;
1179	serge	1539
3480	Serge	1540	for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1963	serge	1541	const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3031	serge	1542	if (hsize != ptr->hdisplay)
		1543	continue;
		1544	if (vsize != ptr->vdisplay)
		1545	continue;
		1546	if (fresh != drm_mode_vrefresh(ptr))
		1547	continue;
		1548	if (rb != mode_is_rb(ptr))
		1549	continue;
		1550
		1551	return drm_mode_duplicate(dev, ptr);
6084	serge	1552	}
3031	serge	1553
		1554	return NULL;
1179	serge	1555	}
1963	serge	1556	EXPORT_SYMBOL(drm_mode_find_dmt);
1221	serge	1557
1963	serge	1558	typedef void detailed_cb(struct detailed_timing timing, void closure);
		1559
		1560	static void
		1561	cea_for_each_detailed_block(u8 ext, detailed_cb cb, void *closure)
		1562	{
		1563	int i, n = 0;
3031	serge	1564	u8 d = ext[0x02];
1963	serge	1565	u8 *det_base = ext + d;
		1566
3031	serge	1567	n = (127 - d) / 18;
1963	serge	1568	for (i = 0; i < n; i++)
		1569	cb((struct detailed_timing )(det_base + 18 i), closure);
		1570	}
		1571
		1572	static void
		1573	vtb_for_each_detailed_block(u8 ext, detailed_cb cb, void *closure)
		1574	{
		1575	unsigned int i, n = min((int)ext[0x02], 6);
		1576	u8 *det_base = ext + 5;
		1577
		1578	if (ext[0x01] != 1)
		1579	return; /* unknown version */
		1580
		1581	for (i = 0; i < n; i++)
		1582	cb((struct detailed_timing )(det_base + 18 i), closure);
		1583	}
		1584
		1585	static void
		1586	drm_for_each_detailed_block(u8 raw_edid, detailed_cb cb, void *closure)
		1587	{
		1588	int i;
		1589	struct edid edid = (struct edid )raw_edid;
		1590
		1591	if (edid == NULL)
		1592	return;
		1593
		1594	for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
		1595	cb(&(edid->detailed_timings[i]), closure);
		1596
		1597	for (i = 1; i <= raw_edid[0x7e]; i++) {
		1598	u8 ext = raw_edid + (i EDID_LENGTH);
		1599	switch (*ext) {
		1600	case CEA_EXT:
		1601	cea_for_each_detailed_block(ext, cb, closure);
		1602	break;
		1603	case VTB_EXT:
		1604	vtb_for_each_detailed_block(ext, cb, closure);
		1605	break;
		1606	default:
		1607	break;
		1608	}
		1609	}
		1610	}
		1611
		1612	static void
		1613	is_rb(struct detailed_timing t, void data)
		1614	{
		1615	u8 r = (u8 )t;
		1616	if (r[3] == EDID_DETAIL_MONITOR_RANGE)
		1617	if (r[15] & 0x10)
		1618	(bool )data = true;
		1619	}
		1620
		1621	/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
		1622	static bool
		1623	drm_monitor_supports_rb(struct edid *edid)
		1624	{
		1625	if (edid->revision >= 4) {
3031	serge	1626	bool ret = false;
1963	serge	1627	drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
		1628	return ret;
		1629	}
		1630
		1631	return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
		1632	}
		1633
		1634	static void
		1635	find_gtf2(struct detailed_timing t, void data)
		1636	{
		1637	u8 r = (u8 )t;
		1638	if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
		1639	(u8 *)data = r;
		1640	}
		1641
		1642	/* Secondary GTF curve kicks in above some break frequency */
		1643	static int
		1644	drm_gtf2_hbreak(struct edid *edid)
		1645	{
		1646	u8 *r = NULL;
		1647	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
		1648	return r ? (r[12] * 2) : 0;
		1649	}
		1650
		1651	static int
		1652	drm_gtf2_2c(struct edid *edid)
		1653	{
		1654	u8 *r = NULL;
		1655	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
		1656	return r ? r[13] : 0;
		1657	}
		1658
		1659	static int
		1660	drm_gtf2_m(struct edid *edid)
		1661	{
		1662	u8 *r = NULL;
		1663	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
		1664	return r ? (r[15] << 8) + r[14] : 0;
		1665	}
		1666
		1667	static int
		1668	drm_gtf2_k(struct edid *edid)
		1669	{
		1670	u8 *r = NULL;
		1671	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
		1672	return r ? r[16] : 0;
		1673	}
		1674
		1675	static int
		1676	drm_gtf2_2j(struct edid *edid)
		1677	{
		1678	u8 *r = NULL;
		1679	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
		1680	return r ? r[17] : 0;
		1681	}
		1682
		1683	/**
		1684	* standard_timing_level - get std. timing level(CVT/GTF/DMT)
		1685	* @edid: EDID block to scan
		1686	*/
		1687	static int standard_timing_level(struct edid *edid)
		1688	{
		1689	if (edid->revision >= 2) {
		1690	if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
		1691	return LEVEL_CVT;
		1692	if (drm_gtf2_hbreak(edid))
		1693	return LEVEL_GTF2;
		1694	return LEVEL_GTF;
		1695	}
		1696	return LEVEL_DMT;
		1697	}
		1698
1221	serge	1699	/*
		1700	* 0 is reserved. The spec says 0x01 fill for unused timings. Some old
		1701	* monitors fill with ascii space (0x20) instead.
		1702	*/
		1703	static int
		1704	bad_std_timing(u8 a, u8 b)
		1705	{
		1706	return (a == 0x00 && b == 0x00) \|\|
		1707	(a == 0x01 && b == 0x01) \|\|
		1708	(a == 0x20 && b == 0x20);
		1709	}
		1710
1123	serge	1711	/**
		1712	* drm_mode_std - convert standard mode info (width, height, refresh) into mode
5060	serge	1713	* @connector: connector of for the EDID block
		1714	* @edid: EDID block to scan
1123	serge	1715	* @t: standard timing params
		1716	*
		1717	* Take the standard timing params (in this case width, aspect, and refresh)
1221	serge	1718	* and convert them into a real mode using CVT/GTF/DMT.
1123	serge	1719	*/
1963	serge	1720	static struct drm_display_mode *
		1721	drm_mode_std(struct drm_connector connector, struct edid edid,
5060	serge	1722	struct std_timing *t)
1123	serge	1723	{
1963	serge	1724	struct drm_device *dev = connector->dev;
		1725	struct drm_display_mode m, mode = NULL;
1179	serge	1726	int hsize, vsize;
		1727	int vrefresh_rate;
1123	serge	1728	unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
		1729	>> EDID_TIMING_ASPECT_SHIFT;
1179	serge	1730	unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
		1731	>> EDID_TIMING_VFREQ_SHIFT;
1963	serge	1732	int timing_level = standard_timing_level(edid);
1123	serge	1733
1221	serge	1734	if (bad_std_timing(t->hsize, t->vfreq_aspect))
		1735	return NULL;
		1736
1179	serge	1737	/* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
		1738	hsize = t->hsize * 8 + 248;
		1739	/* vrefresh_rate = vfreq + 60 */
		1740	vrefresh_rate = vfreq + 60;
		1741	/* the vdisplay is calculated based on the aspect ratio */
1221	serge	1742	if (aspect_ratio == 0) {
5060	serge	1743	if (edid->revision < 3)
1221	serge	1744	vsize = hsize;
		1745	else
6084	serge	1746	vsize = (hsize * 10) / 16;
1221	serge	1747	} else if (aspect_ratio == 1)
1123	serge	1748	vsize = (hsize * 3) / 4;
		1749	else if (aspect_ratio == 2)
		1750	vsize = (hsize * 4) / 5;
		1751	else
		1752	vsize = (hsize * 9) / 16;
1963	serge	1753
		1754	/* HDTV hack, part 1 */
		1755	if (vrefresh_rate == 60 &&
		1756	((hsize == 1360 && vsize == 765) \|\|
		1757	(hsize == 1368 && vsize == 769))) {
		1758	hsize = 1366;
		1759	vsize = 768;
		1760	}
		1761
		1762	/*
		1763	* If this connector already has a mode for this size and refresh
		1764	* rate (because it came from detailed or CVT info), use that
		1765	* instead. This way we don't have to guess at interlace or
		1766	* reduced blanking.
		1767	*/
		1768	list_for_each_entry(m, &connector->probed_modes, head)
		1769	if (m->hdisplay == hsize && m->vdisplay == vsize &&
		1770	drm_mode_vrefresh(m) == vrefresh_rate)
		1771	return NULL;
		1772
		1773	/* HDTV hack, part 2 */
		1774	if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
		1775	mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1221	serge	1776	false);
1179	serge	1777	mode->hdisplay = 1366;
1963	serge	1778	mode->hsync_start = mode->hsync_start - 1;
		1779	mode->hsync_end = mode->hsync_end - 1;
1179	serge	1780	return mode;
		1781	}
1963	serge	1782
1179	serge	1783	/* check whether it can be found in default mode table */
3031	serge	1784	if (drm_monitor_supports_rb(edid)) {
		1785	mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
		1786	true);
		1787	if (mode)
		1788	return mode;
		1789	}
		1790	mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1179	serge	1791	if (mode)
		1792	return mode;
1123	serge	1793
3031	serge	1794	/* okay, generate it */
1179	serge	1795	switch (timing_level) {
		1796	case LEVEL_DMT:
		1797	break;
		1798	case LEVEL_GTF:
		1799	mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
		1800	break;
1963	serge	1801	case LEVEL_GTF2:
		1802	/*
		1803	* This is potentially wrong if there's ever a monitor with
		1804	* more than one ranges section, each claiming a different
		1805	* secondary GTF curve. Please don't do that.
		1806	*/
		1807	mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3031	serge	1808	if (!mode)
		1809	return NULL;
1963	serge	1810	if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
3031	serge	1811	drm_mode_destroy(dev, mode);
1963	serge	1812	mode = drm_gtf_mode_complex(dev, hsize, vsize,
		1813	vrefresh_rate, 0, 0,
		1814	drm_gtf2_m(edid),
		1815	drm_gtf2_2c(edid),
		1816	drm_gtf2_k(edid),
		1817	drm_gtf2_2j(edid));
		1818	}
		1819	break;
1179	serge	1820	case LEVEL_CVT:
1221	serge	1821	mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
		1822	false);
1179	serge	1823	break;
		1824	}
1123	serge	1825	return mode;
		1826	}
		1827
1428	serge	1828	/*
		1829	* EDID is delightfully ambiguous about how interlaced modes are to be
		1830	* encoded. Our internal representation is of frame height, but some
		1831	* HDTV detailed timings are encoded as field height.
		1832	*
		1833	* The format list here is from CEA, in frame size. Technically we
		1834	* should be checking refresh rate too. Whatever.
		1835	*/
		1836	static void
		1837	drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
		1838	struct detailed_pixel_timing *pt)
		1839	{
		1840	int i;
		1841	static const struct {
		1842	int w, h;
		1843	} cea_interlaced[] = {
		1844	{ 1920, 1080 },
		1845	{ 720, 480 },
		1846	{ 1440, 480 },
		1847	{ 2880, 480 },
		1848	{ 720, 576 },
		1849	{ 1440, 576 },
		1850	{ 2880, 576 },
		1851	};
		1852
		1853	if (!(pt->misc & DRM_EDID_PT_INTERLACED))
		1854	return;
		1855
1963	serge	1856	for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1428	serge	1857	if ((mode->hdisplay == cea_interlaced[i].w) &&
		1858	(mode->vdisplay == cea_interlaced[i].h / 2)) {
		1859	mode->vdisplay *= 2;
		1860	mode->vsync_start *= 2;
		1861	mode->vsync_end *= 2;
		1862	mode->vtotal *= 2;
		1863	mode->vtotal \|= 1;
		1864	}
		1865	}
		1866
		1867	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1868	}
		1869
1123	serge	1870	/**
		1871	* drm_mode_detailed - create a new mode from an EDID detailed timing section
		1872	* @dev: DRM device (needed to create new mode)
		1873	* @edid: EDID block
		1874	* @timing: EDID detailed timing info
		1875	* @quirks: quirks to apply
		1876	*
		1877	* An EDID detailed timing block contains enough info for us to create and
		1878	* return a new struct drm_display_mode.
		1879	*/
		1880	static struct drm_display_mode drm_mode_detailed(struct drm_device dev,
		1881	struct edid *edid,
		1882	struct detailed_timing *timing,
		1883	u32 quirks)
		1884	{
		1885	struct drm_display_mode *mode;
		1886	struct detailed_pixel_timing *pt = &timing->data.pixel_data;
		1887	unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 \| pt->hactive_lo;
		1888	unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 \| pt->vactive_lo;
		1889	unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 \| pt->hblank_lo;
		1890	unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 \| pt->vblank_lo;
		1891	unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 \| pt->hsync_offset_lo;
		1892	unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 \| pt->hsync_pulse_width_lo;
3480	Serge	1893	unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 \| pt->vsync_offset_pulse_width_lo >> 4;
1123	serge	1894	unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 \| (pt->vsync_offset_pulse_width_lo & 0xf);
		1895
		1896	/* ignore tiny modes */
		1897	if (hactive < 64 \|\| vactive < 64)
		1898	return NULL;
		1899
		1900	if (pt->misc & DRM_EDID_PT_STEREO) {
4075	Serge	1901	DRM_DEBUG_KMS("stereo mode not supported\n");
1123	serge	1902	return NULL;
		1903	}
		1904	if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
4075	Serge	1905	DRM_DEBUG_KMS("composite sync not supported\n");
1123	serge	1906	}
		1907
1246	serge	1908	/* it is incorrect if hsync/vsync width is zero */
		1909	if (!hsync_pulse_width \|\| !vsync_pulse_width) {
		1910	DRM_DEBUG_KMS("Incorrect Detailed timing. "
		1911	"Wrong Hsync/Vsync pulse width\n");
		1912	return NULL;
		1913	}
3031	serge	1914
		1915	if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
		1916	mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
		1917	if (!mode)
		1918	return NULL;
		1919
		1920	goto set_size;
		1921	}
		1922
1123	serge	1923	mode = drm_mode_create(dev);
		1924	if (!mode)
		1925	return NULL;
		1926
		1927	if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
		1928	timing->pixel_clock = cpu_to_le16(1088);
		1929
		1930	mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
		1931
		1932	mode->hdisplay = hactive;
		1933	mode->hsync_start = mode->hdisplay + hsync_offset;
		1934	mode->hsync_end = mode->hsync_start + hsync_pulse_width;
		1935	mode->htotal = mode->hdisplay + hblank;
		1936
		1937	mode->vdisplay = vactive;
		1938	mode->vsync_start = mode->vdisplay + vsync_offset;
		1939	mode->vsync_end = mode->vsync_start + vsync_pulse_width;
		1940	mode->vtotal = mode->vdisplay + vblank;
		1941
1313	serge	1942	/* Some EDIDs have bogus h/vtotal values */
		1943	if (mode->hsync_end > mode->htotal)
		1944	mode->htotal = mode->hsync_end + 1;
		1945	if (mode->vsync_end > mode->vtotal)
		1946	mode->vtotal = mode->vsync_end + 1;
		1947
1963	serge	1948	drm_mode_do_interlace_quirk(mode, pt);
		1949
1123	serge	1950	if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
		1951	pt->misc \|= DRM_EDID_PT_HSYNC_POSITIVE \| DRM_EDID_PT_VSYNC_POSITIVE;
		1952	}
		1953
		1954	mode->flags \|= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
		1955	DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
		1956	mode->flags \|= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
		1957	DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
		1958
3031	serge	1959	set_size:
1123	serge	1960	mode->width_mm = pt->width_mm_lo \| (pt->width_height_mm_hi & 0xf0) << 4;
		1961	mode->height_mm = pt->height_mm_lo \| (pt->width_height_mm_hi & 0xf) << 8;
		1962
		1963	if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
		1964	mode->width_mm *= 10;
		1965	mode->height_mm *= 10;
		1966	}
		1967
		1968	if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
		1969	mode->width_mm = edid->width_cm * 10;
		1970	mode->height_mm = edid->height_cm * 10;
		1971	}
		1972
3031	serge	1973	mode->type = DRM_MODE_TYPE_DRIVER;
3480	Serge	1974	mode->vrefresh = drm_mode_vrefresh(mode);
3031	serge	1975	drm_mode_set_name(mode);
		1976
1123	serge	1977	return mode;
		1978	}
		1979
1963	serge	1980	static bool
		1981	mode_in_hsync_range(const struct drm_display_mode *mode,
		1982	struct edid edid, u8 t)
		1983	{
		1984	int hsync, hmin, hmax;
		1985
		1986	hmin = t[7];
		1987	if (edid->revision >= 4)
		1988	hmin += ((t[4] & 0x04) ? 255 : 0);
		1989	hmax = t[8];
		1990	if (edid->revision >= 4)
		1991	hmax += ((t[4] & 0x08) ? 255 : 0);
		1992	hsync = drm_mode_hsync(mode);
		1993
		1994	return (hsync <= hmax && hsync >= hmin);
		1995	}
		1996
		1997	static bool
		1998	mode_in_vsync_range(const struct drm_display_mode *mode,
		1999	struct edid edid, u8 t)
		2000	{
		2001	int vsync, vmin, vmax;
		2002
		2003	vmin = t[5];
		2004	if (edid->revision >= 4)
		2005	vmin += ((t[4] & 0x01) ? 255 : 0);
		2006	vmax = t[6];
		2007	if (edid->revision >= 4)
		2008	vmax += ((t[4] & 0x02) ? 255 : 0);
		2009	vsync = drm_mode_vrefresh(mode);
		2010
		2011	return (vsync <= vmax && vsync >= vmin);
		2012	}
		2013
		2014	static u32
		2015	range_pixel_clock(struct edid edid, u8 t)
		2016	{
		2017	/* unspecified */
		2018	if (t[9] == 0 \|\| t[9] == 255)
		2019	return 0;
		2020
		2021	/* 1.4 with CVT support gives us real precision, yay */
		2022	if (edid->revision >= 4 && t[10] == 0x04)
		2023	return (t[9] * 10000) - ((t[12] >> 2) * 250);
		2024
		2025	/* 1.3 is pathetic, so fuzz up a bit */
		2026	return t[9] * 10000 + 5001;
		2027	}
		2028
		2029	static bool
		2030	mode_in_range(const struct drm_display_mode mode, struct edid edid,
		2031	struct detailed_timing *timing)
		2032	{
		2033	u32 max_clock;
		2034	u8 t = (u8 )timing;
		2035
		2036	if (!mode_in_hsync_range(mode, edid, t))
		2037	return false;
		2038
		2039	if (!mode_in_vsync_range(mode, edid, t))
		2040	return false;
		2041
		2042	if ((max_clock = range_pixel_clock(edid, t)))
		2043	if (mode->clock > max_clock)
		2044	return false;
		2045
		2046	/* 1.4 max horizontal check */
		2047	if (edid->revision >= 4 && t[10] == 0x04)
		2048	if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
		2049	return false;
		2050
		2051	if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
		2052	return false;
		2053
		2054	return true;
		2055	}
		2056
3031	serge	2057	static bool valid_inferred_mode(const struct drm_connector *connector,
		2058	const struct drm_display_mode *mode)
		2059	{
6084	serge	2060	const struct drm_display_mode *m;
3031	serge	2061	bool ok = false;
		2062
		2063	list_for_each_entry(m, &connector->probed_modes, head) {
		2064	if (mode->hdisplay == m->hdisplay &&
		2065	mode->vdisplay == m->vdisplay &&
		2066	drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
		2067	return false; /* duplicated */
		2068	if (mode->hdisplay <= m->hdisplay &&
		2069	mode->vdisplay <= m->vdisplay)
		2070	ok = true;
		2071	}
		2072	return ok;
		2073	}
		2074
1963	serge	2075	static int
3031	serge	2076	drm_dmt_modes_for_range(struct drm_connector connector, struct edid edid,
6084	serge	2077	struct detailed_timing *timing)
1963	serge	2078	{
		2079	int i, modes = 0;
		2080	struct drm_display_mode *newmode;
		2081	struct drm_device *dev = connector->dev;
1123	serge	2082
3480	Serge	2083	for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3031	serge	2084	if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
		2085	valid_inferred_mode(connector, drm_dmt_modes + i)) {
1963	serge	2086	newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
		2087	if (newmode) {
		2088	drm_mode_probed_add(connector, newmode);
		2089	modes++;
		2090	}
		2091	}
		2092	}
1123	serge	2093
1963	serge	2094	return modes;
		2095	}
		2096
3031	serge	2097	/* fix up 1366x768 mode from 1368x768;
		2098	* GFT/CVT can't express 1366 width which isn't dividable by 8
		2099	*/
		2100	static void fixup_mode_1366x768(struct drm_display_mode *mode)
		2101	{
		2102	if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
		2103	mode->hdisplay = 1366;
		2104	mode->hsync_start--;
		2105	mode->hsync_end--;
		2106	drm_mode_set_name(mode);
		2107	}
		2108	}
		2109
		2110	static int
		2111	drm_gtf_modes_for_range(struct drm_connector connector, struct edid edid,
		2112	struct detailed_timing *timing)
		2113	{
		2114	int i, modes = 0;
		2115	struct drm_display_mode *newmode;
		2116	struct drm_device *dev = connector->dev;
		2117
3480	Serge	2118	for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3031	serge	2119	const struct minimode *m = &extra_modes[i];
		2120	newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
		2121	if (!newmode)
		2122	return modes;
		2123
		2124	fixup_mode_1366x768(newmode);
		2125	if (!mode_in_range(newmode, edid, timing) \|\|
		2126	!valid_inferred_mode(connector, newmode)) {
		2127	drm_mode_destroy(dev, newmode);
		2128	continue;
		2129	}
		2130
		2131	drm_mode_probed_add(connector, newmode);
		2132	modes++;
		2133	}
		2134
		2135	return modes;
		2136	}
		2137
		2138	static int
		2139	drm_cvt_modes_for_range(struct drm_connector connector, struct edid edid,
		2140	struct detailed_timing *timing)
		2141	{
		2142	int i, modes = 0;
		2143	struct drm_display_mode *newmode;
		2144	struct drm_device *dev = connector->dev;
		2145	bool rb = drm_monitor_supports_rb(edid);
		2146
3480	Serge	2147	for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3031	serge	2148	const struct minimode *m = &extra_modes[i];
		2149	newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
		2150	if (!newmode)
		2151	return modes;
		2152
		2153	fixup_mode_1366x768(newmode);
		2154	if (!mode_in_range(newmode, edid, timing) \|\|
		2155	!valid_inferred_mode(connector, newmode)) {
		2156	drm_mode_destroy(dev, newmode);
		2157	continue;
		2158	}
		2159
		2160	drm_mode_probed_add(connector, newmode);
		2161	modes++;
		2162	}
		2163
		2164	return modes;
		2165	}
		2166
1963	serge	2167	static void
		2168	do_inferred_modes(struct detailed_timing timing, void c)
		2169	{
		2170	struct detailed_mode_closure *closure = c;
		2171	struct detailed_non_pixel *data = &timing->data.other_data;
3031	serge	2172	struct detailed_data_monitor_range *range = &data->data.range;
1963	serge	2173
3031	serge	2174	if (data->type != EDID_DETAIL_MONITOR_RANGE)
		2175	return;
		2176
		2177	closure->modes += drm_dmt_modes_for_range(closure->connector,
		2178	closure->edid,
		2179	timing);
6084	serge	2180
3031	serge	2181	if (!version_greater(closure->edid, 1, 1))
		2182	return; /* GTF not defined yet */
		2183
		2184	switch (range->flags) {
		2185	case 0x02: /* secondary gtf, XXX could do more */
		2186	case 0x00: /* default gtf */
1963	serge	2187	closure->modes += drm_gtf_modes_for_range(closure->connector,
		2188	closure->edid,
		2189	timing);
3031	serge	2190	break;
		2191	case 0x04: /* cvt, only in 1.4+ */
		2192	if (!version_greater(closure->edid, 1, 3))
		2193	break;
		2194
		2195	closure->modes += drm_cvt_modes_for_range(closure->connector,
		2196	closure->edid,
		2197	timing);
		2198	break;
		2199	case 0x01: /* just the ranges, no formula */
		2200	default:
		2201	break;
		2202	}
1963	serge	2203	}
		2204
		2205	static int
		2206	add_inferred_modes(struct drm_connector connector, struct edid edid)
		2207	{
		2208	struct detailed_mode_closure closure = {
5271	serge	2209	.connector = connector,
		2210	.edid = edid,
1963	serge	2211	};
		2212
		2213	if (version_greater(edid, 1, 0))
		2214	drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
		2215	&closure);
		2216
		2217	return closure.modes;
		2218	}
		2219
		2220	static int
		2221	drm_est3_modes(struct drm_connector connector, struct detailed_timing timing)
		2222	{
		2223	int i, j, m, modes = 0;
		2224	struct drm_display_mode *mode;
		2225	u8 est = ((u8 )timing) + 5;
		2226
		2227	for (i = 0; i < 6; i++) {
4560	Serge	2228	for (j = 7; j >= 0; j--) {
1963	serge	2229	m = (i * 8) + (7 - j);
		2230	if (m >= ARRAY_SIZE(est3_modes))
		2231	break;
		2232	if (est[i] & (1 << j)) {
		2233	mode = drm_mode_find_dmt(connector->dev,
		2234	est3_modes[m].w,
		2235	est3_modes[m].h,
3031	serge	2236	est3_modes[m].r,
		2237	est3_modes[m].rb);
1963	serge	2238	if (mode) {
		2239	drm_mode_probed_add(connector, mode);
		2240	modes++;
		2241	}
		2242	}
		2243	}
		2244	}
		2245
		2246	return modes;
		2247	}
		2248
		2249	static void
		2250	do_established_modes(struct detailed_timing timing, void c)
		2251	{
		2252	struct detailed_mode_closure *closure = c;
6084	serge	2253	struct detailed_non_pixel *data = &timing->data.other_data;
1963	serge	2254
		2255	if (data->type == EDID_DETAIL_EST_TIMINGS)
		2256	closure->modes += drm_est3_modes(closure->connector, timing);
		2257	}
		2258
1123	serge	2259	/**
		2260	* add_established_modes - get est. modes from EDID and add them
5060	serge	2261	* @connector: connector to add mode(s) to
1123	serge	2262	* @edid: EDID block to scan
		2263	*
		2264	* Each EDID block contains a bitmap of the supported "established modes" list
		2265	* (defined above). Tease them out and add them to the global modes list.
		2266	*/
1963	serge	2267	static int
		2268	add_established_modes(struct drm_connector connector, struct edid edid)
1123	serge	2269	{
		2270	struct drm_device *dev = connector->dev;
		2271	unsigned long est_bits = edid->established_timings.t1 \|
		2272	(edid->established_timings.t2 << 8) \|
		2273	((edid->established_timings.mfg_rsvd & 0x80) << 9);
		2274	int i, modes = 0;
1963	serge	2275	struct detailed_mode_closure closure = {
5271	serge	2276	.connector = connector,
		2277	.edid = edid,
1963	serge	2278	};
1123	serge	2279
1963	serge	2280	for (i = 0; i <= EDID_EST_TIMINGS; i++) {
1123	serge	2281	if (est_bits & (1<
		2282	struct drm_display_mode *newmode;
		2283	newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
		2284	if (newmode) {
6084	serge	2285	drm_mode_probed_add(connector, newmode);
1123	serge	2286	modes++;
		2287	}
		2288	}
1963	serge	2289	}
1123	serge	2290
1963	serge	2291	if (version_greater(edid, 1, 0))
		2292	drm_for_each_detailed_block((u8 *)edid,
		2293	do_established_modes, &closure);
		2294
		2295	return modes + closure.modes;
1123	serge	2296	}
1963	serge	2297
		2298	static void
		2299	do_standard_modes(struct detailed_timing timing, void c)
1179	serge	2300	{
1963	serge	2301	struct detailed_mode_closure *closure = c;
		2302	struct detailed_non_pixel *data = &timing->data.other_data;
		2303	struct drm_connector *connector = closure->connector;
		2304	struct edid *edid = closure->edid;
		2305
		2306	if (data->type == EDID_DETAIL_STD_MODES) {
		2307	int i;
		2308	for (i = 0; i < 6; i++) {
6084	serge	2309	struct std_timing *std;
		2310	struct drm_display_mode *newmode;
1963	serge	2311
		2312	std = &data->data.timings[i];
5060	serge	2313	newmode = drm_mode_std(connector, edid, std);
6084	serge	2314	if (newmode) {
		2315	drm_mode_probed_add(connector, newmode);
1963	serge	2316	closure->modes++;
		2317	}
		2318	}
6084	serge	2319	}
1179	serge	2320	}
1123	serge	2321
		2322	/**
		2323	* add_standard_modes - get std. modes from EDID and add them
5060	serge	2324	* @connector: connector to add mode(s) to
1123	serge	2325	* @edid: EDID block to scan
		2326	*
1963	serge	2327	* Standard modes can be calculated using the appropriate standard (DMT,
		2328	* GTF or CVT. Grab them from @edid and add them to the list.
1123	serge	2329	*/
1963	serge	2330	static int
		2331	add_standard_modes(struct drm_connector connector, struct edid edid)
1123	serge	2332	{
		2333	int i, modes = 0;
1963	serge	2334	struct detailed_mode_closure closure = {
5271	serge	2335	.connector = connector,
		2336	.edid = edid,
1963	serge	2337	};
1123	serge	2338
		2339	for (i = 0; i < EDID_STD_TIMINGS; i++) {
		2340	struct drm_display_mode *newmode;
		2341
1963	serge	2342	newmode = drm_mode_std(connector, edid,
5060	serge	2343	&edid->standard_timings[i]);
1123	serge	2344	if (newmode) {
		2345	drm_mode_probed_add(connector, newmode);
		2346	modes++;
		2347	}
		2348	}
		2349
1963	serge	2350	if (version_greater(edid, 1, 0))
		2351	drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
		2352	&closure);
1123	serge	2353
1963	serge	2354	/* XXX should also look for standard codes in VTB blocks */
1321	serge	2355
1963	serge	2356	return modes + closure.modes;
1321	serge	2357	}
		2358
		2359	static int drm_cvt_modes(struct drm_connector *connector,
		2360	struct detailed_timing *timing)
		2361	{
1123	serge	2362	int i, j, modes = 0;
1321	serge	2363	struct drm_display_mode *newmode;
		2364	struct drm_device *dev = connector->dev;
		2365	struct cvt_timing *cvt;
		2366	const int rates[] = { 60, 85, 75, 60, 50 };
1404	serge	2367	const u8 empty[3] = { 0, 0, 0 };
1123	serge	2368
1321	serge	2369	for (i = 0; i < 4; i++) {
1404	serge	2370	int uninitialized_var(width), height;
1321	serge	2371	cvt = &(timing->data.other_data.data.cvt[i]);
1179	serge	2372
1404	serge	2373	if (!memcmp(cvt->code, empty, 3))
6084	serge	2374	continue;
1404	serge	2375
		2376	height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
		2377	switch (cvt->code[1] & 0x0c) {
1321	serge	2378	case 0x00:
		2379	width = height * 4 / 3;
		2380	break;
1404	serge	2381	case 0x04:
1321	serge	2382	width = height * 16 / 9;
		2383	break;
1404	serge	2384	case 0x08:
1321	serge	2385	width = height * 16 / 10;
		2386	break;
1404	serge	2387	case 0x0c:
1321	serge	2388	width = height * 15 / 9;
		2389	break;
		2390	}
		2391
		2392	for (j = 1; j < 5; j++) {
		2393	if (cvt->code[2] & (1 << j)) {
		2394	newmode = drm_cvt_mode(dev, width, height,
		2395	rates[j], j == 0,
		2396	false, false);
		2397	if (newmode) {
		2398	drm_mode_probed_add(connector, newmode);
		2399	modes++;
		2400	}
		2401	}
		2402	}
6084	serge	2403	}
1321	serge	2404
		2405	return modes;
		2406	}
		2407
1963	serge	2408	static void
		2409	do_cvt_mode(struct detailed_timing timing, void c)
1321	serge	2410	{
1963	serge	2411	struct detailed_mode_closure *closure = c;
		2412	struct detailed_non_pixel *data = &timing->data.other_data;
1123	serge	2413
1963	serge	2414	if (data->type == EDID_DETAIL_CVT_3BYTE)
		2415	closure->modes += drm_cvt_modes(closure->connector, timing);
		2416	}
1321	serge	2417
1963	serge	2418	static int
		2419	add_cvt_modes(struct drm_connector connector, struct edid edid)
6084	serge	2420	{
1963	serge	2421	struct detailed_mode_closure closure = {
5271	serge	2422	.connector = connector,
		2423	.edid = edid,
1963	serge	2424	};
1321	serge	2425
1963	serge	2426	if (version_greater(edid, 1, 2))
		2427	drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
1321	serge	2428
1963	serge	2429	/* XXX should also look for CVT codes in VTB blocks */
1123	serge	2430
1963	serge	2431	return closure.modes;
1321	serge	2432	}
		2433
6084	serge	2434	static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
		2435
1963	serge	2436	static void
		2437	do_detailed_mode(struct detailed_timing timing, void c)
1321	serge	2438	{
1963	serge	2439	struct detailed_mode_closure *closure = c;
		2440	struct drm_display_mode *newmode;
1321	serge	2441
1963	serge	2442	if (timing->pixel_clock) {
		2443	newmode = drm_mode_detailed(closure->connector->dev,
		2444	closure->edid, timing,
		2445	closure->quirks);
		2446	if (!newmode)
		2447	return;
1321	serge	2448
1963	serge	2449	if (closure->preferred)
		2450	newmode->type \|= DRM_MODE_TYPE_PREFERRED;
1123	serge	2451
6084	serge	2452	/*
		2453	* Detailed modes are limited to 10kHz pixel clock resolution,
		2454	* so fix up anything that looks like CEA/HDMI mode, but the clock
		2455	* is just slightly off.
		2456	*/
		2457	fixup_detailed_cea_mode_clock(newmode);
		2458
1963	serge	2459	drm_mode_probed_add(closure->connector, newmode);
		2460	closure->modes++;
		2461	closure->preferred = 0;
		2462	}
1179	serge	2463	}
1321	serge	2464
1963	serge	2465	/*
		2466	* add_detailed_modes - Add modes from detailed timings
1179	serge	2467	* @connector: attached connector
1963	serge	2468	* @edid: EDID block to scan
1179	serge	2469	* @quirks: quirks to apply
		2470	*/
1963	serge	2471	static int
		2472	add_detailed_modes(struct drm_connector connector, struct edid edid,
		2473	u32 quirks)
1179	serge	2474	{
1963	serge	2475	struct detailed_mode_closure closure = {
5271	serge	2476	.connector = connector,
		2477	.edid = edid,
		2478	.preferred = 1,
		2479	.quirks = quirks,
1963	serge	2480	};
1179	serge	2481
1963	serge	2482	if (closure.preferred && !version_greater(edid, 1, 3))
		2483	closure.preferred =
		2484	(edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
1179	serge	2485
1963	serge	2486	drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
1179	serge	2487
1963	serge	2488	return closure.modes;
		2489	}
1179	serge	2490
1963	serge	2491	#define AUDIO_BLOCK 0x01
3031	serge	2492	#define VIDEO_BLOCK 0x02
1963	serge	2493	#define VENDOR_BLOCK 0x03
3031	serge	2494	#define SPEAKER_BLOCK 0x04
3480	Serge	2495	#define VIDEO_CAPABILITY_BLOCK 0x07
1963	serge	2496	#define EDID_BASIC_AUDIO (1 << 6)
3031	serge	2497	#define EDID_CEA_YCRCB444 (1 << 5)
		2498	#define EDID_CEA_YCRCB422 (1 << 4)
3480	Serge	2499	#define EDID_CEA_VCDB_QS (1 << 6)
1179	serge	2500
4104	Serge	2501	/*
1963	serge	2502	* Search EDID for CEA extension block.
1123	serge	2503	*/
5271	serge	2504	static u8 drm_find_edid_extension(struct edid edid, int ext_id)
1123	serge	2505	{
1963	serge	2506	u8 *edid_ext = NULL;
1321	serge	2507	int i;
1123	serge	2508
1963	serge	2509	/* No EDID or EDID extensions */
		2510	if (edid == NULL \|\| edid->extensions == 0)
		2511	return NULL;
1321	serge	2512
1963	serge	2513	/* Find CEA extension */
		2514	for (i = 0; i < edid->extensions; i++) {
		2515	edid_ext = (u8 )edid + EDID_LENGTH (i + 1);
5271	serge	2516	if (edid_ext[0] == ext_id)
1963	serge	2517	break;
1123	serge	2518	}
		2519
1963	serge	2520	if (i == edid->extensions)
		2521	return NULL;
1123	serge	2522
1963	serge	2523	return edid_ext;
1123	serge	2524	}
		2525
5271	serge	2526	static u8 drm_find_cea_extension(struct edid edid)
		2527	{
		2528	return drm_find_edid_extension(edid, CEA_EXT);
		2529	}
		2530
		2531	static u8 drm_find_displayid_extension(struct edid edid)
		2532	{
		2533	return drm_find_edid_extension(edid, DISPLAYID_EXT);
		2534	}
		2535
4075	Serge	2536	/*
		2537	* Calculate the alternate clock for the CEA mode
		2538	* (60Hz vs. 59.94Hz etc.)
		2539	*/
		2540	static unsigned int
		2541	cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
		2542	{
		2543	unsigned int clock = cea_mode->clock;
		2544
		2545	if (cea_mode->vrefresh % 6 != 0)
		2546	return clock;
		2547
		2548	/*
		2549	* edid_cea_modes contains the 59.94Hz
		2550	* variant for 240 and 480 line modes,
		2551	* and the 60Hz variant otherwise.
		2552	*/
		2553	if (cea_mode->vdisplay == 240 \|\| cea_mode->vdisplay == 480)
6084	serge	2554	clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4075	Serge	2555	else
6084	serge	2556	clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4075	Serge	2557
		2558	return clock;
		2559	}
		2560
3480	Serge	2561	/**
		2562	* drm_match_cea_mode - look for a CEA mode matching given mode
		2563	* @to_match: display mode
		2564	*
5060	serge	2565	* Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3480	Serge	2566	* mode.
3192	Serge	2567	*/
3480	Serge	2568	u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3192	Serge	2569	{
		2570	u8 mode;
		2571
3746	Serge	2572	if (!to_match->clock)
		2573	return 0;
		2574
3480	Serge	2575	for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) {
3746	Serge	2576	const struct drm_display_mode *cea_mode = &edid_cea_modes[mode];
		2577	unsigned int clock1, clock2;
3192	Serge	2578
3746	Serge	2579	/* Check both 60Hz and 59.94Hz */
4075	Serge	2580	clock1 = cea_mode->clock;
		2581	clock2 = cea_mode_alternate_clock(cea_mode);
3746	Serge	2582
		2583	if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) \|\|
		2584	KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4560	Serge	2585	drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
3192	Serge	2586	return mode + 1;
		2587	}
		2588	return 0;
		2589	}
		2590	EXPORT_SYMBOL(drm_match_cea_mode);
		2591
5060	serge	2592	/**
		2593	* drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
		2594	* the input VIC from the CEA mode list
		2595	* @video_code: ID given to each of the CEA modes
		2596	*
		2597	* Returns picture aspect ratio
		2598	*/
		2599	enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
		2600	{
		2601	/* return picture aspect ratio for video_code - 1 to access the
		2602	* right array element
		2603	*/
		2604	return edid_cea_modes[video_code-1].picture_aspect_ratio;
		2605	}
		2606	EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
		2607
4104	Serge	2608	/*
		2609	* Calculate the alternate clock for HDMI modes (those from the HDMI vendor
		2610	* specific block).
		2611	*
		2612	* It's almost like cea_mode_alternate_clock(), we just need to add an
		2613	* exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
		2614	* one.
		2615	*/
		2616	static unsigned int
		2617	hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
		2618	{
		2619	if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
		2620	return hdmi_mode->clock;
		2621
		2622	return cea_mode_alternate_clock(hdmi_mode);
		2623	}
		2624
		2625	/*
		2626	* drm_match_hdmi_mode - look for a HDMI mode matching given mode
		2627	* @to_match: display mode
		2628	*
		2629	* An HDMI mode is one defined in the HDMI vendor specific block.
		2630	*
		2631	* Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
		2632	*/
		2633	static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
		2634	{
		2635	u8 mode;
		2636
		2637	if (!to_match->clock)
		2638	return 0;
		2639
		2640	for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) {
		2641	const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode];
		2642	unsigned int clock1, clock2;
		2643
		2644	/* Make sure to also match alternate clocks */
		2645	clock1 = hdmi_mode->clock;
		2646	clock2 = hdmi_mode_alternate_clock(hdmi_mode);
		2647
		2648	if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) \|\|
		2649	KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4560	Serge	2650	drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
4104	Serge	2651	return mode + 1;
		2652	}
		2653	return 0;
		2654	}
		2655
4075	Serge	2656	static int
		2657	add_alternate_cea_modes(struct drm_connector connector, struct edid edid)
		2658	{
		2659	struct drm_device *dev = connector->dev;
		2660	struct drm_display_mode mode, tmp;
		2661	LIST_HEAD(list);
		2662	int modes = 0;
3192	Serge	2663
4075	Serge	2664	/* Don't add CEA modes if the CEA extension block is missing */
		2665	if (!drm_find_cea_extension(edid))
		2666	return 0;
		2667
		2668	/*
		2669	* Go through all probed modes and create a new mode
		2670	* with the alternate clock for certain CEA modes.
		2671	*/
		2672	list_for_each_entry(mode, &connector->probed_modes, head) {
4104	Serge	2673	const struct drm_display_mode *cea_mode = NULL;
4075	Serge	2674	struct drm_display_mode *newmode;
4104	Serge	2675	u8 mode_idx = drm_match_cea_mode(mode) - 1;
4075	Serge	2676	unsigned int clock1, clock2;
		2677
4104	Serge	2678	if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
		2679	cea_mode = &edid_cea_modes[mode_idx];
		2680	clock2 = cea_mode_alternate_clock(cea_mode);
		2681	} else {
		2682	mode_idx = drm_match_hdmi_mode(mode) - 1;
		2683	if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
		2684	cea_mode = &edid_4k_modes[mode_idx];
		2685	clock2 = hdmi_mode_alternate_clock(cea_mode);
		2686	}
		2687	}
		2688
		2689	if (!cea_mode)
4075	Serge	2690	continue;
		2691
		2692	clock1 = cea_mode->clock;
		2693
		2694	if (clock1 == clock2)
		2695	continue;
		2696
		2697	if (mode->clock != clock1 && mode->clock != clock2)
		2698	continue;
		2699
		2700	newmode = drm_mode_duplicate(dev, cea_mode);
		2701	if (!newmode)
		2702	continue;
		2703
4560	Serge	2704	/* Carry over the stereo flags */
		2705	newmode->flags \|= mode->flags & DRM_MODE_FLAG_3D_MASK;
		2706
4075	Serge	2707	/*
		2708	* The current mode could be either variant. Make
		2709	* sure to pick the "other" clock for the new mode.
		2710	*/
		2711	if (mode->clock != clock1)
		2712	newmode->clock = clock1;
		2713	else
		2714	newmode->clock = clock2;
		2715
		2716	list_add_tail(&newmode->head, &list);
		2717	}
		2718
		2719	list_for_each_entry_safe(mode, tmp, &list, head) {
		2720	list_del(&mode->head);
		2721	drm_mode_probed_add(connector, mode);
		2722	modes++;
		2723	}
		2724
		2725	return modes;
		2726	}
		2727
4560	Serge	2728	static struct drm_display_mode *
		2729	drm_display_mode_from_vic_index(struct drm_connector *connector,
		2730	const u8 *video_db, u8 video_len,
		2731	u8 video_index)
		2732	{
		2733	struct drm_device *dev = connector->dev;
		2734	struct drm_display_mode *newmode;
		2735	u8 cea_mode;
		2736
		2737	if (video_db == NULL \|\| video_index >= video_len)
		2738	return NULL;
		2739
		2740	/* CEA modes are numbered 1..127 */
		2741	cea_mode = (video_db[video_index] & 127) - 1;
		2742	if (cea_mode >= ARRAY_SIZE(edid_cea_modes))
		2743	return NULL;
		2744
		2745	newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
5060	serge	2746	if (!newmode)
		2747	return NULL;
		2748
4560	Serge	2749	newmode->vrefresh = 0;
		2750
		2751	return newmode;
		2752	}
		2753
3031	serge	2754	static int
4104	Serge	2755	do_cea_modes(struct drm_connector connector, const u8 db, u8 len)
3031	serge	2756	{
4560	Serge	2757	int i, modes = 0;
		2758
		2759	for (i = 0; i < len; i++) {
		2760	struct drm_display_mode *mode;
		2761	mode = drm_display_mode_from_vic_index(connector, db, len, i);
		2762	if (mode) {
		2763	drm_mode_probed_add(connector, mode);
		2764	modes++;
		2765	}
		2766	}
		2767
		2768	return modes;
		2769	}
		2770
		2771	struct stereo_mandatory_mode {
		2772	int width, height, vrefresh;
		2773	unsigned int flags;
		2774	};
		2775
		2776	static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
		2777	{ 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
		2778	{ 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
		2779	{ 1920, 1080, 50,
		2780	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
		2781	{ 1920, 1080, 60,
		2782	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
		2783	{ 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
		2784	{ 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
		2785	{ 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
		2786	{ 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
		2787	};
		2788
		2789	static bool
		2790	stereo_match_mandatory(const struct drm_display_mode *mode,
		2791	const struct stereo_mandatory_mode *stereo_mode)
		2792	{
		2793	unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
		2794
		2795	return mode->hdisplay == stereo_mode->width &&
		2796	mode->vdisplay == stereo_mode->height &&
		2797	interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
		2798	drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
		2799	}
		2800
		2801	static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
		2802	{
3031	serge	2803	struct drm_device *dev = connector->dev;
4560	Serge	2804	const struct drm_display_mode *mode;
		2805	struct list_head stereo_modes;
		2806	int modes = 0, i;
		2807
		2808	INIT_LIST_HEAD(&stereo_modes);
		2809
		2810	list_for_each_entry(mode, &connector->probed_modes, head) {
		2811	for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
		2812	const struct stereo_mandatory_mode *mandatory;
		2813	struct drm_display_mode *new_mode;
		2814
		2815	if (!stereo_match_mandatory(mode,
		2816	&stereo_mandatory_modes[i]))
		2817	continue;
		2818
		2819	mandatory = &stereo_mandatory_modes[i];
		2820	new_mode = drm_mode_duplicate(dev, mode);
		2821	if (!new_mode)
		2822	continue;
		2823
		2824	new_mode->flags \|= mandatory->flags;
		2825	list_add_tail(&new_mode->head, &stereo_modes);
		2826	modes++;
		2827	}
		2828	}
		2829
		2830	list_splice_tail(&stereo_modes, &connector->probed_modes);
		2831
		2832	return modes;
		2833	}
		2834
		2835	static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
		2836	{
		2837	struct drm_device *dev = connector->dev;
		2838	struct drm_display_mode *newmode;
		2839
		2840	vic--; /* VICs start at 1 */
		2841	if (vic >= ARRAY_SIZE(edid_4k_modes)) {
		2842	DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
		2843	return 0;
		2844	}
		2845
		2846	newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
		2847	if (!newmode)
		2848	return 0;
		2849
		2850	drm_mode_probed_add(connector, newmode);
		2851
		2852	return 1;
		2853	}
		2854
		2855	static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
		2856	const u8 *video_db, u8 video_len, u8 video_index)
		2857	{
		2858	struct drm_display_mode *newmode;
3031	serge	2859	int modes = 0;
		2860
4560	Serge	2861	if (structure & (1 << 0)) {
		2862	newmode = drm_display_mode_from_vic_index(connector, video_db,
		2863	video_len,
		2864	video_index);
5271	serge	2865	if (newmode) {
4560	Serge	2866	newmode->flags \|= DRM_MODE_FLAG_3D_FRAME_PACKING;
5271	serge	2867	drm_mode_probed_add(connector, newmode);
		2868	modes++;
3031	serge	2869	}
5271	serge	2870	}
4560	Serge	2871	if (structure & (1 << 6)) {
		2872	newmode = drm_display_mode_from_vic_index(connector, video_db,
		2873	video_len,
		2874	video_index);
6084	serge	2875	if (newmode) {
4560	Serge	2876	newmode->flags \|= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
6084	serge	2877	drm_mode_probed_add(connector, newmode);
		2878	modes++;
4560	Serge	2879	}
6084	serge	2880	}
4560	Serge	2881	if (structure & (1 << 8)) {
		2882	newmode = drm_display_mode_from_vic_index(connector, video_db,
		2883	video_len,
		2884	video_index);
		2885	if (newmode) {
		2886	newmode->flags \|= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
		2887	drm_mode_probed_add(connector, newmode);
		2888	modes++;
		2889	}
3031	serge	2890	}
		2891
		2892	return modes;
		2893	}
		2894
4104	Serge	2895	/*
		2896	* do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
		2897	* @connector: connector corresponding to the HDMI sink
		2898	* @db: start of the CEA vendor specific block
		2899	* @len: length of the CEA block payload, ie. one can access up to db[len]
		2900	*
4560	Serge	2901	* Parses the HDMI VSDB looking for modes to add to @connector. This function
		2902	* also adds the stereo 3d modes when applicable.
4104	Serge	2903	*/
3031	serge	2904	static int
4560	Serge	2905	do_hdmi_vsdb_modes(struct drm_connector connector, const u8 db, u8 len,
		2906	const u8 *video_db, u8 video_len)
4104	Serge	2907	{
4560	Serge	2908	int modes = 0, offset = 0, i, multi_present = 0, multi_len;
		2909	u8 vic_len, hdmi_3d_len = 0;
		2910	u16 mask;
		2911	u16 structure_all;
4104	Serge	2912
		2913	if (len < 8)
		2914	goto out;
		2915
		2916	/* no HDMI_Video_Present */
		2917	if (!(db[8] & (1 << 5)))
		2918	goto out;
		2919
		2920	/* Latency_Fields_Present */
		2921	if (db[8] & (1 << 7))
		2922	offset += 2;
		2923
		2924	/* I_Latency_Fields_Present */
		2925	if (db[8] & (1 << 6))
		2926	offset += 2;
		2927
		2928	/* the declared length is not long enough for the 2 first bytes
		2929	* of additional video format capabilities */
4560	Serge	2930	if (len < (8 + offset + 2))
4104	Serge	2931	goto out;
		2932
4560	Serge	2933	/* 3D_Present */
		2934	offset++;
		2935	if (db[8 + offset] & (1 << 7)) {
		2936	modes += add_hdmi_mandatory_stereo_modes(connector);
		2937
		2938	/* 3D_Multi_present */
		2939	multi_present = (db[8 + offset] & 0x60) >> 5;
		2940	}
		2941
		2942	offset++;
4104	Serge	2943	vic_len = db[8 + offset] >> 5;
4560	Serge	2944	hdmi_3d_len = db[8 + offset] & 0x1f;
4104	Serge	2945
		2946	for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
		2947	u8 vic;
		2948
		2949	vic = db[9 + offset + i];
4560	Serge	2950	modes += add_hdmi_mode(connector, vic);
		2951	}
		2952	offset += 1 + vic_len;
4104	Serge	2953
4560	Serge	2954	if (multi_present == 1)
		2955	multi_len = 2;
		2956	else if (multi_present == 2)
		2957	multi_len = 4;
		2958	else
		2959	multi_len = 0;
		2960
		2961	if (len < (8 + offset + hdmi_3d_len - 1))
		2962	goto out;
		2963
		2964	if (hdmi_3d_len < multi_len)
		2965	goto out;
		2966
		2967	if (multi_present == 1 \|\| multi_present == 2) {
		2968	/* 3D_Structure_ALL */
		2969	structure_all = (db[8 + offset] << 8) \| db[9 + offset];
		2970
		2971	/* check if 3D_MASK is present */
		2972	if (multi_present == 2)
		2973	mask = (db[10 + offset] << 8) \| db[11 + offset];
		2974	else
		2975	mask = 0xffff;
		2976
		2977	for (i = 0; i < 16; i++) {
		2978	if (mask & (1 << i))
		2979	modes += add_3d_struct_modes(connector,
		2980	structure_all,
		2981	video_db,
		2982	video_len, i);
4104	Serge	2983	}
4560	Serge	2984	}
4104	Serge	2985
4560	Serge	2986	offset += multi_len;
4104	Serge	2987
4560	Serge	2988	for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
		2989	int vic_index;
		2990	struct drm_display_mode *newmode = NULL;
		2991	unsigned int newflag = 0;
		2992	bool detail_present;
		2993
		2994	detail_present = ((db[8 + offset + i] & 0x0f) > 7);
		2995
		2996	if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
		2997	break;
		2998
		2999	/* 2D_VIC_order_X */
		3000	vic_index = db[8 + offset + i] >> 4;
		3001
		3002	/* 3D_Structure_X */
		3003	switch (db[8 + offset + i] & 0x0f) {
		3004	case 0:
		3005	newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
		3006	break;
		3007	case 6:
		3008	newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
		3009	break;
		3010	case 8:
		3011	/* 3D_Detail_X */
		3012	if ((db[9 + offset + i] >> 4) == 1)
		3013	newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
		3014	break;
		3015	}
		3016
		3017	if (newflag != 0) {
		3018	newmode = drm_display_mode_from_vic_index(connector,
		3019	video_db,
		3020	video_len,
		3021	vic_index);
		3022
		3023	if (newmode) {
		3024	newmode->flags \|= newflag;
6084	serge	3025	drm_mode_probed_add(connector, newmode);
		3026	modes++;
		3027	}
4560	Serge	3028	}
4104	Serge	3029
4560	Serge	3030	if (detail_present)
		3031	i++;
		3032	}
		3033
4104	Serge	3034	out:
		3035	return modes;
		3036	}
		3037
		3038	static int
3031	serge	3039	cea_db_payload_len(const u8 *db)
		3040	{
		3041	return db[0] & 0x1f;
		3042	}
		3043
		3044	static int
		3045	cea_db_tag(const u8 *db)
		3046	{
		3047	return db[0] >> 5;
		3048	}
		3049
		3050	static int
		3051	cea_revision(const u8 *cea)
		3052	{
		3053	return cea[1];
		3054	}
		3055
		3056	static int
		3057	cea_db_offsets(const u8 cea, int start, int *end)
		3058	{
		3059	/* Data block offset in CEA extension block */
		3060	*start = 4;
		3061	*end = cea[2];
		3062	if (*end == 0)
		3063	*end = 127;
		3064	if (end < 4 \|\| end > 127)
		3065	return -ERANGE;
		3066	return 0;
		3067	}
		3068
4104	Serge	3069	static bool cea_db_is_hdmi_vsdb(const u8 *db)
		3070	{
		3071	int hdmi_id;
		3072
		3073	if (cea_db_tag(db) != VENDOR_BLOCK)
		3074	return false;
		3075
		3076	if (cea_db_payload_len(db) < 5)
		3077	return false;
		3078
		3079	hdmi_id = db[1] \| (db[2] << 8) \| (db[3] << 16);
		3080
		3081	return hdmi_id == HDMI_IEEE_OUI;
		3082	}
		3083
3031	serge	3084	#define for_each_cea_db(cea, i, start, end) \
		3085	for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
		3086
		3087	static int
		3088	add_cea_modes(struct drm_connector connector, struct edid edid)
		3089	{
4104	Serge	3090	const u8 *cea = drm_find_cea_extension(edid);
4560	Serge	3091	const u8 db, hdmi = NULL, *video = NULL;
		3092	u8 dbl, hdmi_len, video_len = 0;
3031	serge	3093	int modes = 0;
		3094
		3095	if (cea && cea_revision(cea) >= 3) {
		3096	int i, start, end;
		3097
		3098	if (cea_db_offsets(cea, &start, &end))
		3099	return 0;
		3100
		3101	for_each_cea_db(cea, i, start, end) {
		3102	db = &cea[i];
		3103	dbl = cea_db_payload_len(db);
		3104
4560	Serge	3105	if (cea_db_tag(db) == VIDEO_BLOCK) {
		3106	video = db + 1;
		3107	video_len = dbl;
		3108	modes += do_cea_modes(connector, video, dbl);
		3109	}
		3110	else if (cea_db_is_hdmi_vsdb(db)) {
		3111	hdmi = db;
		3112	hdmi_len = dbl;
6084	serge	3113	}
3031	serge	3114	}
		3115	}
		3116
4560	Serge	3117	/*
		3118	* We parse the HDMI VSDB after having added the cea modes as we will
		3119	* be patching their flags when the sink supports stereo 3D.
		3120	*/
		3121	if (hdmi)
		3122	modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
		3123	video_len);
		3124
3031	serge	3125	return modes;
		3126	}
		3127
6084	serge	3128	static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
		3129	{
		3130	const struct drm_display_mode *cea_mode;
		3131	int clock1, clock2, clock;
		3132	u8 mode_idx;
		3133	const char *type;
		3134
		3135	mode_idx = drm_match_cea_mode(mode) - 1;
		3136	if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
		3137	type = "CEA";
		3138	cea_mode = &edid_cea_modes[mode_idx];
		3139	clock1 = cea_mode->clock;
		3140	clock2 = cea_mode_alternate_clock(cea_mode);
		3141	} else {
		3142	mode_idx = drm_match_hdmi_mode(mode) - 1;
		3143	if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
		3144	type = "HDMI";
		3145	cea_mode = &edid_4k_modes[mode_idx];
		3146	clock1 = cea_mode->clock;
		3147	clock2 = hdmi_mode_alternate_clock(cea_mode);
		3148	} else {
		3149	return;
		3150	}
		3151	}
		3152
		3153	/* pick whichever is closest */
		3154	if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
		3155	clock = clock1;
		3156	else
		3157	clock = clock2;
		3158
		3159	if (mode->clock == clock)
		3160	return;
		3161
		3162	DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
		3163	type, mode_idx + 1, mode->clock, clock);
		3164	mode->clock = clock;
		3165	}
		3166
3031	serge	3167	static void
		3168	parse_hdmi_vsdb(struct drm_connector connector, const u8 db)
		3169	{
		3170	u8 len = cea_db_payload_len(db);
		3171
		3172	if (len >= 6) {
6084	serge	3173	connector->eld[5] \|= (db[6] >> 7) << 1; /* Supports_AI */
		3174	connector->dvi_dual = db[6] & 1;
3031	serge	3175	}
		3176	if (len >= 7)
6084	serge	3177	connector->max_tmds_clock = db[7] * 5;
3031	serge	3178	if (len >= 8) {
6084	serge	3179	connector->latency_present[0] = db[8] >> 7;
		3180	connector->latency_present[1] = (db[8] >> 6) & 1;
3031	serge	3181	}
		3182	if (len >= 9)
6084	serge	3183	connector->video_latency[0] = db[9];
3031	serge	3184	if (len >= 10)
6084	serge	3185	connector->audio_latency[0] = db[10];
3031	serge	3186	if (len >= 11)
6084	serge	3187	connector->video_latency[1] = db[11];
3031	serge	3188	if (len >= 12)
6084	serge	3189	connector->audio_latency[1] = db[12];
3031	serge	3190
3192	Serge	3191	DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3031	serge	3192	"max TMDS clock %d, "
		3193	"latency present %d %d, "
		3194	"video latency %d %d, "
		3195	"audio latency %d %d\n",
		3196	connector->dvi_dual,
		3197	connector->max_tmds_clock,
		3198	(int) connector->latency_present[0],
		3199	(int) connector->latency_present[1],
		3200	connector->video_latency[0],
		3201	connector->video_latency[1],
		3202	connector->audio_latency[0],
		3203	connector->audio_latency[1]);
		3204	}
		3205
		3206	static void
		3207	monitor_name(struct detailed_timing t, void data)
		3208	{
		3209	if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
		3210	(u8 *)data = t->data.other_data.data.str.str;
		3211	}
		3212
1123	serge	3213	/**
3031	serge	3214	* drm_edid_to_eld - build ELD from EDID
		3215	* @connector: connector corresponding to the HDMI/DP sink
		3216	* @edid: EDID to parse
		3217	*
5060	serge	3218	* Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
		3219	* Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
		3220	* fill in.
3031	serge	3221	*/
		3222	void drm_edid_to_eld(struct drm_connector connector, struct edid edid)
		3223	{
		3224	uint8_t *eld = connector->eld;
		3225	u8 *cea;
		3226	u8 *name;
		3227	u8 *db;
		3228	int sad_count = 0;
		3229	int mnl;
		3230	int dbl;
		3231
		3232	memset(eld, 0, sizeof(connector->eld));
		3233
		3234	cea = drm_find_cea_extension(edid);
		3235	if (!cea) {
		3236	DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
		3237	return;
		3238	}
		3239
		3240	name = NULL;
		3241	drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
		3242	for (mnl = 0; name && mnl < 13; mnl++) {
		3243	if (name[mnl] == 0x0a)
		3244	break;
		3245	eld[20 + mnl] = name[mnl];
		3246	}
		3247	eld[4] = (cea[1] << 5) \| mnl;
		3248	DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
		3249
		3250	eld[0] = 2 << 3; /* ELD version: 2 */
		3251
		3252	eld[16] = edid->mfg_id[0];
		3253	eld[17] = edid->mfg_id[1];
		3254	eld[18] = edid->prod_code[0];
		3255	eld[19] = edid->prod_code[1];
		3256
		3257	if (cea_revision(cea) >= 3) {
		3258	int i, start, end;
		3259
		3260	if (cea_db_offsets(cea, &start, &end)) {
		3261	start = 0;
		3262	end = 0;
		3263	}
		3264
		3265	for_each_cea_db(cea, i, start, end) {
		3266	db = &cea[i];
		3267	dbl = cea_db_payload_len(db);
4539	Serge	3268
3031	serge	3269	switch (cea_db_tag(db)) {
		3270	case AUDIO_BLOCK:
		3271	/* Audio Data Block, contains SADs */
		3272	sad_count = dbl / 3;
		3273	if (dbl >= 1)
6084	serge	3274	memcpy(eld + 20 + mnl, &db[1], dbl);
3031	serge	3275	break;
		3276	case SPEAKER_BLOCK:
6084	serge	3277	/* Speaker Allocation Data Block */
3031	serge	3278	if (dbl >= 1)
6084	serge	3279	eld[7] = db[1];
3031	serge	3280	break;
		3281	case VENDOR_BLOCK:
		3282	/* HDMI Vendor-Specific Data Block */
		3283	if (cea_db_is_hdmi_vsdb(db))
		3284	parse_hdmi_vsdb(connector, db);
		3285	break;
		3286	default:
		3287	break;
		3288	}
		3289	}
		3290	}
		3291	eld[5] \|= sad_count << 4;
		3292
5271	serge	3293	eld[DRM_ELD_BASELINE_ELD_LEN] =
		3294	DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
		3295
		3296	DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
		3297	drm_eld_size(eld), sad_count);
3031	serge	3298	}
		3299	EXPORT_SYMBOL(drm_edid_to_eld);
		3300
		3301	/**
3746	Serge	3302	* drm_edid_to_sad - extracts SADs from EDID
		3303	* @edid: EDID to parse
		3304	* @sads: pointer that will be set to the extracted SADs
		3305	*
		3306	* Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
		3307	*
5060	serge	3308	* Note: The returned pointer needs to be freed using kfree().
		3309	*
		3310	* Return: The number of found SADs or negative number on error.
3746	Serge	3311	*/
		3312	int drm_edid_to_sad(struct edid edid, struct cea_sad *sads)
		3313	{
		3314	int count = 0;
		3315	int i, start, end, dbl;
		3316	u8 *cea;
		3317
		3318	cea = drm_find_cea_extension(edid);
		3319	if (!cea) {
		3320	DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
		3321	return -ENOENT;
		3322	}
		3323
		3324	if (cea_revision(cea) < 3) {
		3325	DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
		3326	return -ENOTSUPP;
		3327	}
		3328
		3329	if (cea_db_offsets(cea, &start, &end)) {
		3330	DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
		3331	return -EPROTO;
		3332	}
		3333
		3334	for_each_cea_db(cea, i, start, end) {
		3335	u8 *db = &cea[i];
		3336
		3337	if (cea_db_tag(db) == AUDIO_BLOCK) {
		3338	int j;
		3339	dbl = cea_db_payload_len(db);
		3340
		3341	count = dbl / 3; /* SAD is 3B */
		3342	sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
		3343	if (!*sads)
		3344	return -ENOMEM;
		3345	for (j = 0; j < count; j++) {
		3346	u8 sad = &db[1 + j 3];
		3347
		3348	(*sads)[j].format = (sad[0] & 0x78) >> 3;
		3349	(*sads)[j].channels = sad[0] & 0x7;
		3350	(*sads)[j].freq = sad[1] & 0x7F;
		3351	(*sads)[j].byte2 = sad[2];
		3352	}
		3353	break;
		3354	}
		3355	}
		3356
		3357	return count;
		3358	}
		3359	EXPORT_SYMBOL(drm_edid_to_sad);
		3360
		3361	/**
4104	Serge	3362	* drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
		3363	* @edid: EDID to parse
		3364	* @sadb: pointer to the speaker block
		3365	*
		3366	* Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
		3367	*
5060	serge	3368	* Note: The returned pointer needs to be freed using kfree().
		3369	*
		3370	* Return: The number of found Speaker Allocation Blocks or negative number on
		3371	* error.
4104	Serge	3372	*/
		3373	int drm_edid_to_speaker_allocation(struct edid edid, u8 *sadb)
		3374	{
		3375	int count = 0;
		3376	int i, start, end, dbl;
		3377	const u8 *cea;
		3378
		3379	cea = drm_find_cea_extension(edid);
		3380	if (!cea) {
		3381	DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
		3382	return -ENOENT;
		3383	}
		3384
		3385	if (cea_revision(cea) < 3) {
		3386	DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
		3387	return -ENOTSUPP;
		3388	}
		3389
		3390	if (cea_db_offsets(cea, &start, &end)) {
		3391	DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
		3392	return -EPROTO;
		3393	}
		3394
		3395	for_each_cea_db(cea, i, start, end) {
		3396	const u8 *db = &cea[i];
		3397
		3398	if (cea_db_tag(db) == SPEAKER_BLOCK) {
		3399	dbl = cea_db_payload_len(db);
		3400
		3401	/* Speaker Allocation Data Block */
		3402	if (dbl == 3) {
5060	serge	3403	*sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4104	Serge	3404	if (!*sadb)
		3405	return -ENOMEM;
		3406	count = dbl;
		3407	break;
		3408	}
		3409	}
		3410	}
		3411
		3412	return count;
		3413	}
		3414	EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
		3415
		3416	/**
5060	serge	3417	* drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3031	serge	3418	* @connector: connector associated with the HDMI/DP sink
		3419	* @mode: the display mode
5060	serge	3420	*
		3421	* Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
		3422	* the sink doesn't support audio or video.
3031	serge	3423	*/
		3424	int drm_av_sync_delay(struct drm_connector *connector,
6084	serge	3425	const struct drm_display_mode *mode)
3031	serge	3426	{
		3427	int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
		3428	int a, v;
		3429
		3430	if (!connector->latency_present[0])
		3431	return 0;
		3432	if (!connector->latency_present[1])
		3433	i = 0;
		3434
		3435	a = connector->audio_latency[i];
		3436	v = connector->video_latency[i];
		3437
		3438	/*
		3439	* HDMI/DP sink doesn't support audio or video?
		3440	*/
		3441	if (a == 255 \|\| v == 255)
		3442	return 0;
		3443
		3444	/*
		3445	* Convert raw EDID values to millisecond.
		3446	* Treat unknown latency as 0ms.
		3447	*/
		3448	if (a)
		3449	a = min(2 * (a - 1), 500);
		3450	if (v)
		3451	v = min(2 * (v - 1), 500);
		3452
		3453	return max(v - a, 0);
		3454	}
		3455	EXPORT_SYMBOL(drm_av_sync_delay);
		3456
		3457	/**
		3458	* drm_select_eld - select one ELD from multiple HDMI/DP sinks
		3459	* @encoder: the encoder just changed display mode
		3460	*
		3461	* It's possible for one encoder to be associated with multiple HDMI/DP sinks.
		3462	* The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
5060	serge	3463	*
		3464	* Return: The connector associated with the first HDMI/DP sink that has ELD
		3465	* attached to it.
3031	serge	3466	*/
6084	serge	3467	struct drm_connector drm_select_eld(struct drm_encoder encoder)
3031	serge	3468	{
		3469	struct drm_connector *connector;
		3470	struct drm_device *dev = encoder->dev;
		3471
5060	serge	3472	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
		3473	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
		3474
6084	serge	3475	drm_for_each_connector(connector, dev)
3031	serge	3476	if (connector->encoder == encoder && connector->eld[0])
		3477	return connector;
		3478
		3479	return NULL;
		3480	}
		3481	EXPORT_SYMBOL(drm_select_eld);
		3482
		3483	/**
5060	serge	3484	* drm_detect_hdmi_monitor - detect whether monitor is HDMI
1123	serge	3485	* @edid: monitor EDID information
		3486	*
		3487	* Parse the CEA extension according to CEA-861-B.
5060	serge	3488	*
		3489	* Return: True if the monitor is HDMI, false if not or unknown.
1123	serge	3490	*/
		3491	bool drm_detect_hdmi_monitor(struct edid *edid)
		3492	{
1963	serge	3493	u8 *edid_ext;
3031	serge	3494	int i;
1123	serge	3495	int start_offset, end_offset;
		3496
1963	serge	3497	edid_ext = drm_find_cea_extension(edid);
		3498	if (!edid_ext)
3031	serge	3499	return false;
1123	serge	3500
3031	serge	3501	if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
		3502	return false;
1123	serge	3503
		3504	/*
		3505	* Because HDMI identifier is in Vendor Specific Block,
		3506	* search it from all data blocks of CEA extension.
		3507	*/
3031	serge	3508	for_each_cea_db(edid_ext, i, start_offset, end_offset) {
		3509	if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
		3510	return true;
1123	serge	3511	}
		3512
3031	serge	3513	return false;
1123	serge	3514	}
		3515	EXPORT_SYMBOL(drm_detect_hdmi_monitor);
		3516
		3517	/**
1963	serge	3518	* drm_detect_monitor_audio - check monitor audio capability
5060	serge	3519	* @edid: EDID block to scan
1963	serge	3520	*
		3521	* Monitor should have CEA extension block.
		3522	* If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
		3523	* audio' only. If there is any audio extension block and supported
		3524	* audio format, assume at least 'basic audio' support, even if 'basic
		3525	* audio' is not defined in EDID.
		3526	*
5060	serge	3527	* Return: True if the monitor supports audio, false otherwise.
1963	serge	3528	*/
		3529	bool drm_detect_monitor_audio(struct edid *edid)
		3530	{
		3531	u8 *edid_ext;
		3532	int i, j;
		3533	bool has_audio = false;
		3534	int start_offset, end_offset;
		3535
		3536	edid_ext = drm_find_cea_extension(edid);
		3537	if (!edid_ext)
		3538	goto end;
		3539
		3540	has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
		3541
		3542	if (has_audio) {
		3543	DRM_DEBUG_KMS("Monitor has basic audio support\n");
		3544	goto end;
		3545	}
		3546
3031	serge	3547	if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
		3548	goto end;
1963	serge	3549
3031	serge	3550	for_each_cea_db(edid_ext, i, start_offset, end_offset) {
		3551	if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
1963	serge	3552	has_audio = true;
3031	serge	3553	for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
1963	serge	3554	DRM_DEBUG_KMS("CEA audio format %d\n",
		3555	(edid_ext[i + j] >> 3) & 0xf);
		3556	goto end;
		3557	}
		3558	}
		3559	end:
		3560	return has_audio;
		3561	}
		3562	EXPORT_SYMBOL(drm_detect_monitor_audio);
		3563
		3564	/**
3480	Serge	3565	* drm_rgb_quant_range_selectable - is RGB quantization range selectable?
5060	serge	3566	* @edid: EDID block to scan
3480	Serge	3567	*
		3568	* Check whether the monitor reports the RGB quantization range selection
		3569	* as supported. The AVI infoframe can then be used to inform the monitor
		3570	* which quantization range (full or limited) is used.
5060	serge	3571	*
		3572	* Return: True if the RGB quantization range is selectable, false otherwise.
3480	Serge	3573	*/
		3574	bool drm_rgb_quant_range_selectable(struct edid *edid)
		3575	{
		3576	u8 *edid_ext;
		3577	int i, start, end;
		3578
		3579	edid_ext = drm_find_cea_extension(edid);
		3580	if (!edid_ext)
		3581	return false;
		3582
		3583	if (cea_db_offsets(edid_ext, &start, &end))
		3584	return false;
		3585
		3586	for_each_cea_db(edid_ext, i, start, end) {
		3587	if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
		3588	cea_db_payload_len(&edid_ext[i]) == 2) {
		3589	DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
		3590	return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
		3591	}
		3592	}
		3593
		3594	return false;
		3595	}
		3596	EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
		3597
		3598	/**
5060	serge	3599	* drm_assign_hdmi_deep_color_info - detect whether monitor supports
		3600	* hdmi deep color modes and update drm_display_info if so.
		3601	* @edid: monitor EDID information
		3602	* @info: Updated with maximum supported deep color bpc and color format
		3603	* if deep color supported.
5271	serge	3604	* @connector: DRM connector, used only for debug output
5060	serge	3605	*
		3606	* Parse the CEA extension according to CEA-861-B.
		3607	* Return true if HDMI deep color supported, false if not or unknown.
		3608	*/
		3609	static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
		3610	struct drm_display_info *info,
		3611	struct drm_connector *connector)
		3612	{
		3613	u8 edid_ext, hdmi;
		3614	int i;
		3615	int start_offset, end_offset;
		3616	unsigned int dc_bpc = 0;
		3617
		3618	edid_ext = drm_find_cea_extension(edid);
		3619	if (!edid_ext)
		3620	return false;
		3621
		3622	if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
		3623	return false;
		3624
		3625	/*
		3626	* Because HDMI identifier is in Vendor Specific Block,
		3627	* search it from all data blocks of CEA extension.
		3628	*/
		3629	for_each_cea_db(edid_ext, i, start_offset, end_offset) {
		3630	if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
		3631	/* HDMI supports at least 8 bpc */
		3632	info->bpc = 8;
		3633
		3634	hdmi = &edid_ext[i];
		3635	if (cea_db_payload_len(hdmi) < 6)
		3636	return false;
		3637
		3638	if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
		3639	dc_bpc = 10;
		3640	info->edid_hdmi_dc_modes \|= DRM_EDID_HDMI_DC_30;
		3641	DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
		3642	connector->name);
		3643	}
		3644
		3645	if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
		3646	dc_bpc = 12;
		3647	info->edid_hdmi_dc_modes \|= DRM_EDID_HDMI_DC_36;
		3648	DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
		3649	connector->name);
		3650	}
		3651
		3652	if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
		3653	dc_bpc = 16;
		3654	info->edid_hdmi_dc_modes \|= DRM_EDID_HDMI_DC_48;
		3655	DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
		3656	connector->name);
		3657	}
		3658
		3659	if (dc_bpc > 0) {
		3660	DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
		3661	connector->name, dc_bpc);
		3662	info->bpc = dc_bpc;
		3663
		3664	/*
		3665	* Deep color support mandates RGB444 support for all video
		3666	* modes and forbids YCRCB422 support for all video modes per
		3667	* HDMI 1.3 spec.
		3668	*/
		3669	info->color_formats = DRM_COLOR_FORMAT_RGB444;
		3670
		3671	/* YCRCB444 is optional according to spec. */
		3672	if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
		3673	info->color_formats \|= DRM_COLOR_FORMAT_YCRCB444;
		3674	DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
		3675	connector->name);
		3676	}
		3677
		3678	/*
		3679	* Spec says that if any deep color mode is supported at all,
		3680	* then deep color 36 bit must be supported.
		3681	*/
		3682	if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
		3683	DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
		3684	connector->name);
		3685	}
		3686
		3687	return true;
		3688	}
		3689	else {
		3690	DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
		3691	connector->name);
		3692	}
		3693	}
		3694	}
		3695
		3696	return false;
		3697	}
		3698
		3699	/**
1963	serge	3700	* drm_add_display_info - pull display info out if present
		3701	* @edid: EDID data
		3702	* @info: display info (attached to connector)
5060	serge	3703	* @connector: connector whose edid is used to build display info
1963	serge	3704	*
		3705	* Grab any available display info and stuff it into the drm_display_info
		3706	* structure that's part of the connector. Useful for tracking bpp and
		3707	* color spaces.
		3708	*/
		3709	static void drm_add_display_info(struct edid *edid,
5060	serge	3710	struct drm_display_info *info,
		3711	struct drm_connector *connector)
1963	serge	3712	{
2160	serge	3713	u8 *edid_ext;
		3714
1963	serge	3715	info->width_mm = edid->width_cm * 10;
		3716	info->height_mm = edid->height_cm * 10;
		3717
		3718	/* driver figures it out in this case */
		3719	info->bpc = 0;
		3720	info->color_formats = 0;
		3721
3031	serge	3722	if (edid->revision < 3)
1963	serge	3723	return;
		3724
		3725	if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
		3726	return;
		3727
3031	serge	3728	/* Get data from CEA blocks if present */
		3729	edid_ext = drm_find_cea_extension(edid);
		3730	if (edid_ext) {
		3731	info->cea_rev = edid_ext[1];
		3732
		3733	/* The existence of a CEA block should imply RGB support */
		3734	info->color_formats = DRM_COLOR_FORMAT_RGB444;
		3735	if (edid_ext[3] & EDID_CEA_YCRCB444)
		3736	info->color_formats \|= DRM_COLOR_FORMAT_YCRCB444;
		3737	if (edid_ext[3] & EDID_CEA_YCRCB422)
		3738	info->color_formats \|= DRM_COLOR_FORMAT_YCRCB422;
		3739	}
		3740
5060	serge	3741	/* HDMI deep color modes supported? Assign to info, if so */
		3742	drm_assign_hdmi_deep_color_info(edid, info, connector);
		3743
3031	serge	3744	/* Only defined for 1.4 with digital displays */
		3745	if (edid->revision < 4)
		3746	return;
		3747
1963	serge	3748	switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
		3749	case DRM_EDID_DIGITAL_DEPTH_6:
		3750	info->bpc = 6;
		3751	break;
		3752	case DRM_EDID_DIGITAL_DEPTH_8:
		3753	info->bpc = 8;
		3754	break;
		3755	case DRM_EDID_DIGITAL_DEPTH_10:
		3756	info->bpc = 10;
		3757	break;
		3758	case DRM_EDID_DIGITAL_DEPTH_12:
		3759	info->bpc = 12;
		3760	break;
		3761	case DRM_EDID_DIGITAL_DEPTH_14:
		3762	info->bpc = 14;
		3763	break;
		3764	case DRM_EDID_DIGITAL_DEPTH_16:
		3765	info->bpc = 16;
		3766	break;
		3767	case DRM_EDID_DIGITAL_DEPTH_UNDEF:
		3768	default:
		3769	info->bpc = 0;
		3770	break;
		3771	}
		3772
5060	serge	3773	DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
		3774	connector->name, info->bpc);
		3775
3031	serge	3776	info->color_formats \|= DRM_COLOR_FORMAT_RGB444;
		3777	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
		3778	info->color_formats \|= DRM_COLOR_FORMAT_YCRCB444;
		3779	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
		3780	info->color_formats \|= DRM_COLOR_FORMAT_YCRCB422;
1963	serge	3781	}
		3782
		3783	/**
1123	serge	3784	* drm_add_edid_modes - add modes from EDID data, if available
		3785	* @connector: connector we're probing
5060	serge	3786	* @edid: EDID data
1123	serge	3787	*
		3788	* Add the specified modes to the connector's mode list.
		3789	*
5060	serge	3790	* Return: The number of modes added or 0 if we couldn't find any.
1123	serge	3791	*/
		3792	int drm_add_edid_modes(struct drm_connector connector, struct edid edid)
		3793	{
		3794	int num_modes = 0;
		3795	u32 quirks;
		3796
		3797	if (edid == NULL) {
		3798	return 0;
		3799	}
1430	serge	3800	if (!drm_edid_is_valid(edid)) {
1963	serge	3801	dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
5060	serge	3802	connector->name);
1123	serge	3803	return 0;
		3804	}
		3805
		3806	quirks = edid_get_quirks(edid);
		3807
1963	serge	3808	/*
		3809	* EDID spec says modes should be preferred in this order:
		3810	* - preferred detailed mode
		3811	* - other detailed modes from base block
		3812	* - detailed modes from extension blocks
		3813	* - CVT 3-byte code modes
		3814	* - standard timing codes
		3815	* - established timing codes
		3816	* - modes inferred from GTF or CVT range information
		3817	*
		3818	* We get this pretty much right.
		3819	*
		3820	* XXX order for additional mode types in extension blocks?
		3821	*/
		3822	num_modes += add_detailed_modes(connector, edid, quirks);
		3823	num_modes += add_cvt_modes(connector, edid);
		3824	num_modes += add_standard_modes(connector, edid);
1123	serge	3825	num_modes += add_established_modes(connector, edid);
3031	serge	3826	num_modes += add_cea_modes(connector, edid);
4075	Serge	3827	num_modes += add_alternate_cea_modes(connector, edid);
6084	serge	3828	if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
		3829	num_modes += add_inferred_modes(connector, edid);
1123	serge	3830
		3831	if (quirks & (EDID_QUIRK_PREFER_LARGE_60 \| EDID_QUIRK_PREFER_LARGE_75))
		3832	edid_fixup_preferred(connector, quirks);
		3833
5060	serge	3834	drm_add_display_info(edid, &connector->display_info, connector);
1123	serge	3835
6660	serge	3836	if (quirks & EDID_QUIRK_FORCE_6BPC)
		3837	connector->display_info.bpc = 6;
		3838
4539	Serge	3839	if (quirks & EDID_QUIRK_FORCE_8BPC)
		3840	connector->display_info.bpc = 8;
		3841
6935	serge	3842	if (quirks & EDID_QUIRK_FORCE_10BPC)
		3843	connector->display_info.bpc = 10;
		3844
5060	serge	3845	if (quirks & EDID_QUIRK_FORCE_12BPC)
		3846	connector->display_info.bpc = 12;
		3847
1123	serge	3848	return num_modes;
		3849	}
		3850	EXPORT_SYMBOL(drm_add_edid_modes);
1179	serge	3851
		3852	/**
		3853	* drm_add_modes_noedid - add modes for the connectors without EDID
		3854	* @connector: connector we're probing
		3855	* @hdisplay: the horizontal display limit
		3856	* @vdisplay: the vertical display limit
		3857	*
		3858	* Add the specified modes to the connector's mode list. Only when the
		3859	* hdisplay/vdisplay is not beyond the given limit, it will be added.
		3860	*
5060	serge	3861	* Return: The number of modes added or 0 if we couldn't find any.
1179	serge	3862	*/
		3863	int drm_add_modes_noedid(struct drm_connector *connector,
		3864	int hdisplay, int vdisplay)
		3865	{
		3866	int i, count, num_modes = 0;
1963	serge	3867	struct drm_display_mode *mode;
1179	serge	3868	struct drm_device *dev = connector->dev;
		3869
6084	serge	3870	count = ARRAY_SIZE(drm_dmt_modes);
1179	serge	3871	if (hdisplay < 0)
		3872	hdisplay = 0;
		3873	if (vdisplay < 0)
		3874	vdisplay = 0;
		3875
		3876	for (i = 0; i < count; i++) {
1963	serge	3877	const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1179	serge	3878	if (hdisplay && vdisplay) {
		3879	/*
		3880	* Only when two are valid, they will be used to check
		3881	* whether the mode should be added to the mode list of
		3882	* the connector.
		3883	*/
		3884	if (ptr->hdisplay > hdisplay \|\|
		3885	ptr->vdisplay > vdisplay)
		3886	continue;
		3887	}
1321	serge	3888	if (drm_mode_vrefresh(ptr) > 61)
		3889	continue;
1179	serge	3890	mode = drm_mode_duplicate(dev, ptr);
		3891	if (mode) {
		3892	drm_mode_probed_add(connector, mode);
		3893	num_modes++;
		3894	}
		3895	}
		3896	return num_modes;
		3897	}
		3898	EXPORT_SYMBOL(drm_add_modes_noedid);
3192	Serge	3899
5060	serge	3900	/**
		3901	* drm_set_preferred_mode - Sets the preferred mode of a connector
		3902	* @connector: connector whose mode list should be processed
		3903	* @hpref: horizontal resolution of preferred mode
		3904	* @vpref: vertical resolution of preferred mode
		3905	*
		3906	* Marks a mode as preferred if it matches the resolution specified by @hpref
		3907	* and @vpref.
		3908	*/
4560	Serge	3909	void drm_set_preferred_mode(struct drm_connector *connector,
		3910	int hpref, int vpref)
		3911	{
		3912	struct drm_display_mode *mode;
		3913
		3914	list_for_each_entry(mode, &connector->probed_modes, head) {
6084	serge	3915	if (mode->hdisplay == hpref &&
5060	serge	3916	mode->vdisplay == vpref)
4560	Serge	3917	mode->type \|= DRM_MODE_TYPE_PREFERRED;
		3918	}
		3919	}
		3920	EXPORT_SYMBOL(drm_set_preferred_mode);
		3921
3192	Serge	3922	/**
3480	Serge	3923	* drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
		3924	* data from a DRM display mode
		3925	* @frame: HDMI AVI infoframe
		3926	* @mode: DRM display mode
3192	Serge	3927	*
5060	serge	3928	* Return: 0 on success or a negative error code on failure.
3192	Serge	3929	*/
3480	Serge	3930	int
		3931	drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
		3932	const struct drm_display_mode *mode)
3192	Serge	3933	{
3480	Serge	3934	int err;
3192	Serge	3935
3480	Serge	3936	if (!frame \|\| !mode)
		3937	return -EINVAL;
3192	Serge	3938
3480	Serge	3939	err = hdmi_avi_infoframe_init(frame);
		3940	if (err < 0)
		3941	return err;
		3942
4104	Serge	3943	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		3944	frame->pixel_repeat = 1;
		3945
3480	Serge	3946	frame->video_code = drm_match_cea_mode(mode);
		3947
		3948	frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5060	serge	3949
		3950	/*
		3951	* Populate picture aspect ratio from either
		3952	* user input (if specified) or from the CEA mode list.
		3953	*/
		3954	if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 \|\|
		3955	mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
		3956	frame->picture_aspect = mode->picture_aspect_ratio;
		3957	else if (frame->video_code > 0)
		3958	frame->picture_aspect = drm_get_cea_aspect_ratio(
		3959	frame->video_code);
		3960
3480	Serge	3961	frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5060	serge	3962	frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
3480	Serge	3963
3192	Serge	3964	return 0;
		3965	}
3480	Serge	3966	EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4104	Serge	3967
4560	Serge	3968	static enum hdmi_3d_structure
		3969	s3d_structure_from_display_mode(const struct drm_display_mode *mode)
		3970	{
		3971	u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
		3972
		3973	switch (layout) {
		3974	case DRM_MODE_FLAG_3D_FRAME_PACKING:
		3975	return HDMI_3D_STRUCTURE_FRAME_PACKING;
		3976	case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
		3977	return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
		3978	case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
		3979	return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
		3980	case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
		3981	return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
		3982	case DRM_MODE_FLAG_3D_L_DEPTH:
		3983	return HDMI_3D_STRUCTURE_L_DEPTH;
		3984	case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
		3985	return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
		3986	case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
		3987	return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
		3988	case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
		3989	return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
		3990	default:
		3991	return HDMI_3D_STRUCTURE_INVALID;
		3992	}
		3993	}
		3994
4104	Serge	3995	/**
		3996	* drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
		3997	* data from a DRM display mode
		3998	* @frame: HDMI vendor infoframe
		3999	* @mode: DRM display mode
		4000	*
		4001	* Note that there's is a need to send HDMI vendor infoframes only when using a
		4002	* 4k or stereoscopic 3D mode. So when giving any other mode as input this
		4003	* function will return -EINVAL, error that can be safely ignored.
		4004	*
5060	serge	4005	* Return: 0 on success or a negative error code on failure.
4104	Serge	4006	*/
		4007	int
		4008	drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
		4009	const struct drm_display_mode *mode)
		4010	{
		4011	int err;
4560	Serge	4012	u32 s3d_flags;
4104	Serge	4013	u8 vic;
		4014
		4015	if (!frame \|\| !mode)
		4016	return -EINVAL;
		4017
		4018	vic = drm_match_hdmi_mode(mode);
4560	Serge	4019	s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
		4020
		4021	if (!vic && !s3d_flags)
4104	Serge	4022	return -EINVAL;
		4023
4560	Serge	4024	if (vic && s3d_flags)
		4025	return -EINVAL;
		4026
4104	Serge	4027	err = hdmi_vendor_infoframe_init(frame);
		4028	if (err < 0)
		4029	return err;
		4030
4560	Serge	4031	if (vic)
6084	serge	4032	frame->vic = vic;
4560	Serge	4033	else
		4034	frame->s3d_struct = s3d_structure_from_display_mode(mode);
4104	Serge	4035
		4036	return 0;
		4037	}
		4038	EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5271	serge	4039
		4040	static int drm_parse_display_id(struct drm_connector *connector,
		4041	u8 *displayid, int length,
		4042	bool is_edid_extension)
		4043	{
		4044	/* if this is an EDID extension the first byte will be 0x70 */
		4045	int idx = 0;
		4046	struct displayid_hdr *base;
		4047	struct displayid_block *block;
		4048	u8 csum = 0;
		4049	int i;
		4050
		4051	if (is_edid_extension)
		4052	idx = 1;
		4053
		4054	base = (struct displayid_hdr *)&displayid[idx];
		4055
		4056	DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
		4057	base->rev, base->bytes, base->prod_id, base->ext_count);
		4058
		4059	if (base->bytes + 5 > length - idx)
		4060	return -EINVAL;
		4061
		4062	for (i = idx; i <= base->bytes + 5; i++) {
		4063	csum += displayid[i];
		4064	}
		4065	if (csum) {
		4066	DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
		4067	return -EINVAL;
		4068	}
		4069
		4070	block = (struct displayid_block *)&displayid[idx + 4];
		4071	DRM_DEBUG_KMS("block id %d, rev %d, len %d\n",
		4072	block->tag, block->rev, block->num_bytes);
		4073
		4074	switch (block->tag) {
		4075	case DATA_BLOCK_TILED_DISPLAY: {
		4076	struct displayid_tiled_block tile = (struct displayid_tiled_block )block;
		4077
		4078	u16 w, h;
		4079	u8 tile_v_loc, tile_h_loc;
		4080	u8 num_v_tile, num_h_tile;
		4081	struct drm_tile_group *tg;
		4082
		4083	w = tile->tile_size[0] \| tile->tile_size[1] << 8;
		4084	h = tile->tile_size[2] \| tile->tile_size[3] << 8;
		4085
		4086	num_v_tile = (tile->topo[0] & 0xf) \| (tile->topo[2] & 0x30);
		4087	num_h_tile = (tile->topo[0] >> 4) \| ((tile->topo[2] >> 2) & 0x30);
		4088	tile_v_loc = (tile->topo[1] & 0xf) \| ((tile->topo[2] & 0x3) << 4);
		4089	tile_h_loc = (tile->topo[1] >> 4) \| (((tile->topo[2] >> 2) & 0x3) << 4);
		4090
		4091	connector->has_tile = true;
		4092	if (tile->tile_cap & 0x80)
		4093	connector->tile_is_single_monitor = true;
		4094
		4095	connector->num_h_tile = num_h_tile + 1;
		4096	connector->num_v_tile = num_v_tile + 1;
		4097	connector->tile_h_loc = tile_h_loc;
		4098	connector->tile_v_loc = tile_v_loc;
		4099	connector->tile_h_size = w + 1;
		4100	connector->tile_v_size = h + 1;
		4101
		4102	DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
		4103	DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
		4104	DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
		4105	num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
		4106	DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
		4107
		4108	tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
		4109	if (!tg) {
		4110	tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
		4111	}
		4112	if (!tg)
		4113	return -ENOMEM;
		4114
		4115	if (connector->tile_group != tg) {
		4116	/* if we haven't got a pointer,
		4117	take the reference, drop ref to old tile group */
		4118	if (connector->tile_group) {
		4119	drm_mode_put_tile_group(connector->dev, connector->tile_group);
		4120	}
		4121	connector->tile_group = tg;
		4122	} else
		4123	/* if same tile group, then release the ref we just took. */
		4124	drm_mode_put_tile_group(connector->dev, tg);
		4125	}
		4126	break;
		4127	default:
		4128	printk("unknown displayid tag %d\n", block->tag);
		4129	break;
		4130	}
		4131	return 0;
		4132	}
		4133
		4134	static void drm_get_displayid(struct drm_connector *connector,
		4135	struct edid *edid)
		4136	{
		4137	void *displayid = NULL;
		4138	int ret;
		4139	connector->has_tile = false;
		4140	displayid = drm_find_displayid_extension(edid);
		4141	if (!displayid) {
		4142	/* drop reference to any tile group we had */
		4143	goto out_drop_ref;
		4144	}
		4145
		4146	ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
		4147	if (ret < 0)
		4148	goto out_drop_ref;
		4149	if (!connector->has_tile)
		4150	goto out_drop_ref;
		4151	return;
		4152	out_drop_ref:
		4153	if (connector->tile_group) {
		4154	drm_mode_put_tile_group(connector->dev, connector->tile_group);
		4155	connector->tile_group = NULL;
		4156	}
		4157	return;
		4158	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/drm_edid.c – Rev 6935