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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1029 | serge | 1 | |
| 2 | #include "radeon_chipset_gen.h" |
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| 3 | #include "radeon_chipinfo_gen.h" |
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| 4 | |||
| 5 | |||
| 6 | |||
| 7 | |||
| 8 | xf86TokenToString(SymTabPtr table, int token) |
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| 9 | { |
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| 10 | int i; |
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| 11 | |||
| 12 | |||
| 13 | |||
| 14 | |||
| 15 | return NULL; |
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| 16 | else |
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| 17 | return(table[i].name); |
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| 18 | } |
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| 19 | |||
| 20 | |||
| 21 | |||
| 22 | |||
| 23 | { |
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| 24 | while(list->pci_device_id) |
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| 25 | { |
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| 26 | if(dev == list->pci_device_id) |
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| 27 | return list; |
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| 28 | list++; |
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| 29 | } |
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| 30 | return 0; |
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| 31 | } |
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| 32 | |||
| 33 | |||
| 34 | |||
| 35 | { |
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| 36 | const RADEONCardInfo *dev; |
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| 37 | u32_t bus, last_bus; |
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| 38 | |||
| 39 | |||
| 40 | return 0; |
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| 41 | |||
| 42 | |||
| 43 | { |
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| 44 | u32_t devfn; |
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| 45 | |||
| 46 | |||
| 47 | { |
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| 48 | u32_t id; |
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| 49 | id = PciRead32(bus,devfn, 0); |
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| 50 | |||
| 51 | |||
| 52 | continue; |
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| 53 | |||
| 54 | |||
| 55 | |||
| 56 | |||
| 57 | { |
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| 58 | u32_t reg2C; |
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| 59 | int i; |
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| 60 | |||
| 61 | |||
| 62 | if (!rhd.chipset){ |
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| 63 | dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID); |
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| 64 | return FALSE; |
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| 65 | } |
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| 66 | dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n", |
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| 67 | rhd.chipset,rhd.PciDeviceID); |
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| 68 | |||
| 69 | |||
| 70 | rhd.devfn = devfn; |
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| 71 | rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
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| 72 | |||
| 73 | |||
| 74 | rhd.IsMobility = dev->mobility; |
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| 75 | rhd.IsIGP = dev->igp; |
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| 76 | rhd.HasCRTC2 = !dev->nocrtc2; |
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| 77 | |||
| 78 | |||
| 79 | |||
| 80 | |||
| 81 | rhd.subdevice_id = reg2C >> 16; |
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| 82 | |||
| 83 | |||
| 84 | dbgprintf("R600 unsupported yet.\nExit\n"); |
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| 85 | |||
| 86 | |||
| 87 | rhd.gart_type = RADEON_IS_PCIE; |
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| 88 | else |
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| 89 | rhd.gart_type = RADEON_IS_PCI; |
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| 90 | |||
| 91 | |||
| 92 | { |
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| 93 | u32_t base; |
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| 94 | Bool validSize; |
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| 95 | |||
| 96 | |||
| 97 | if(base) |
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| 98 | { |
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| 99 | if (base & PCI_MAP_IO){ |
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| 100 | rhd.ioBase[i] = (u32_t)PCIGETIO(base); |
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| 101 | rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; |
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| 102 | } |
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| 103 | else{ |
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| 104 | rhd.memBase[i] = (u32_t)PCIGETMEMORY(base); |
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| 105 | rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
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| 106 | } |
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| 107 | } |
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| 108 | rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); |
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| 109 | } |
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| 110 | return &rhd; |
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| 111 | } |
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| 112 | } |
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| 113 | }; |
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| 114 | return NULL; |
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| 115 | } |
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| 116 | |||
| 117 | |||
| 118 | |||
| 119 | |||
| 120 | { |
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| 121 | int offset; |
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| 122 | u32_t addr1; |
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| 123 | u32_t addr2; |
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| 124 | u32_t mask1; |
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| 125 | u32_t mask2; |
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| 126 | int bits = 0; |
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| 127 | |||
| 128 | |||
| 129 | * silently ignore bogus index values. Valid values are 0-6. 0-5 are |
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| 130 | * the 6 base address registers, and 6 is the ROM base address register. |
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| 131 | */ |
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| 132 | if (index < 0 || index > 6) |
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| 133 | return 0; |
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| 134 | |||
| 135 | |||
| 136 | *min = destructive; |
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| 137 | |||
| 138 | |||
| 139 | if (index == 6) |
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| 140 | offset = PCI_MAP_ROM_REG; |
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| 141 | else |
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| 142 | offset = PCI_MAP_REG_START + (index << 2); |
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| 143 | |||
| 144 | |||
| 145 | /* |
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| 146 | * Check if this is the second part of a 64 bit address. |
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| 147 | * XXX need to check how endianness affects 64 bit addresses. |
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| 148 | */ |
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| 149 | if (index > 0 && index < 6) { |
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| 150 | addr2 = PciRead32(bus, devfn, offset - 4); |
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| 151 | if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) |
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| 152 | return 0; |
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| 153 | } |
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| 154 | |||
| 155 | |||
| 156 | PciWrite32(bus, devfn, offset, 0xffffffff); |
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| 157 | mask1 = PciRead32(bus, devfn, offset); |
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| 158 | PciWrite32(bus, devfn, offset, addr1); |
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| 159 | } else { |
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| 160 | mask1 = addr1; |
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| 161 | } |
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| 162 | |||
| 163 | |||
| 164 | if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) |
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| 165 | { |
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| 166 | if (PCIGETMEMORY(mask1) == 0) |
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| 167 | { |
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| 168 | addr2 = PciRead32(bus, devfn, offset + 4); |
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| 169 | if (destructive) |
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| 170 | { |
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| 171 | PciWrite32(bus, devfn, offset + 4, 0xffffffff); |
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| 172 | mask2 = PciRead32(bus, devfn, offset + 4); |
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| 173 | PciWrite32(bus, devfn, offset + 4, addr2); |
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| 174 | } |
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| 175 | else |
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| 176 | { |
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| 177 | mask2 = addr2; |
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| 178 | } |
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| 179 | if (mask2 == 0) |
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| 180 | return 0; |
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| 181 | bits = 32; |
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| 182 | while ((mask2 & 1) == 0) |
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| 183 | { |
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| 184 | bits++; |
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| 185 | mask2 >>= 1; |
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| 186 | } |
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| 187 | if (bits > 32) |
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| 188 | return bits; |
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| 189 | } |
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| 190 | } |
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| 191 | if (index < 6) |
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| 192 | if (PCI_MAP_IS_MEM(mask1)) |
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| 193 | mask1 = PCIGETMEMORY(mask1); |
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| 194 | else |
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| 195 | mask1 = PCIGETIO(mask1); |
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| 196 | else |
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| 197 | mask1 = PCIGETROM(mask1); |
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| 198 | if (mask1 == 0) |
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| 199 | return 0; |
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| 200 | bits = 0; |
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| 201 | while ((mask1 & 1) == 0) { |
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| 202 | bits++; |
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| 203 | mask1 >>= 1; |
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| 204 | } |
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| 205 | /* I/O maps can be no larger than 8 bits */ |
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| 206 | |||
| 207 | |||
| 208 | bits = 8; |
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| 209 | /* ROM maps can be no larger than 24 bits */ |
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| 210 | if (index == 6 && bits > 24) |
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| 211 | bits = 24; |
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| 212 | return bits; |
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| 213 | } |
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| 214 | |||
| 215 | |||
| 216 | |||
| 217 | |||
| 218 | |||
| 219 | |||
| 220 | int cap, int *ttl) |
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| 221 | { |
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| 222 | u8_t id; |
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| 223 | |||
| 224 | |||
| 225 | { |
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| 226 | pos = pciReadByte(pciTag, pos); |
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| 227 | if (pos < 0x40) |
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| 228 | break; |
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| 229 | pos &= ~3; |
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| 230 | id = pciReadByte(pciTag, pos + PCI_CAP_LIST_ID); |
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| 231 | if (id == 0xff) |
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| 232 | break; |
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| 233 | if (id == cap) |
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| 234 | return pos; |
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| 235 | pos += PCI_CAP_LIST_NEXT; |
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| 236 | } |
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| 237 | return 0; |
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| 238 | } |
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| 239 | |||
| 240 | |||
| 241 | { |
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| 242 | int ttl = PCI_FIND_CAP_TTL; |
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| 243 | |||
| 244 | |||
| 245 | } |
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| 246 | |||
| 247 | |||
| 248 | { |
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| 249 | u16_t status; |
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| 250 | u8_t hdr_type; |
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| 251 | |||
| 252 | |||
| 253 | if (!(status & PCI_STATUS_CAP_LIST)) |
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| 254 | return 0; |
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| 255 | |||
| 256 | |||
| 257 | switch (hdr_type) |
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| 258 | { |
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| 259 | case PCI_HEADER_TYPE_NORMAL: |
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| 260 | case PCI_HEADER_TYPE_BRIDGE: |
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| 261 | return PCI_CAPABILITY_LIST; |
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| 262 | case PCI_HEADER_TYPE_CARDBUS: |
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| 263 | return PCI_CB_CAPABILITY_LIST; |
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| 264 | default: |
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| 265 | return 0; |
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| 266 | } |
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| 267 | return 0; |
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| 268 | } |
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| 269 | |||
| 270 | |||
| 271 | |||
| 272 | { |
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| 273 | int pos; |
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| 274 | |||
| 275 | |||
| 276 | if (pos) |
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| 277 | pos = __pci_find_next_cap(pciTag, pos, cap); |
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| 278 | |||
| 279 | |||
| 280 | } |
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| 281 | |||
| 282 | |||
| 283 | |||
| 284 | { |
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| 285 | return pci_find_capability(pciTag, PCI_CAP_ID_EXP); |
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| 286 | } |
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| 287 | > |
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| 288 |