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Rev | Author | Line No. | Line |
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1029 | serge | 1 | |
2 | Bool dst_alpha; |
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3 | Bool src_alpha; |
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4 | u32_t blend_cntl; |
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5 | }; |
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6 | |||
7 | |||
8 | /* 0 - Clear */ |
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9 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, |
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10 | /* 1 - Src */ |
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11 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, |
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12 | /* 2 - Dst */ |
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13 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, |
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14 | /* 3 - Over */ |
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15 | {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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16 | /* 4 - OverReverse */ |
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17 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, |
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18 | /* 5 - In */ |
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19 | {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
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20 | /* 6 - InReverse */ |
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21 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
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22 | /* 7 - Out */ |
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23 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
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24 | /* 8 - OutReverse */ |
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25 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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26 | /* 9 - Atop */ |
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27 | {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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28 | /* 10- AtopReverse */ |
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29 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
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30 | /* 11 - Xor */ |
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31 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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32 | /* 12 - Add */ |
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33 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, |
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34 | }; |
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35 | |||
36 | |||
37 | |||
38 | { |
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39 | u32_t txfilter, txformat0, txformat1, txoffset, txpitch; |
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40 | |||
41 | |||
42 | |||
43 | |||
44 | |||
45 | txoffset = (u32_t)srcpix->local; |
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46 | |||
47 | |||
48 | dbgprintf("Bad texture offset 0x%x\n", (int)txoffset); |
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49 | if ((txpitch & 0x1f) != 0) |
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50 | dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch); |
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51 | |||
52 | |||
53 | pixel_shift = 32 >> 4; |
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54 | txpitch >>= pixel_shift; |
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55 | txpitch -= 1; |
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56 | |||
57 | |||
58 | |||
59 | |||
60 | (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); |
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61 | |||
62 | |||
63 | txpitch |= R500_TXWIDTH_11; |
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64 | |||
65 | |||
66 | txpitch |= R500_TXHEIGHT_11; |
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67 | |||
68 | |||
69 | * omit this if there is no padding, but there is no apparent advantage |
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70 | * in doing so. |
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71 | */ |
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72 | txformat0 |= R300_TXPITCH_EN; |
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73 | |||
74 | |||
75 | |||
76 | |||
77 | |||
78 | |||
79 | |||
80 | |||
81 | |||
82 | |||
83 | |||
84 | u32_t *ring; |
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85 | |||
86 | |||
87 | |||
88 | |||
89 | OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); |
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90 | OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); |
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91 | OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); |
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92 | OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); |
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93 | OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); |
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94 | // if (!pPict->repeat) |
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95 | OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); |
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96 | |||
97 | |||
98 | } |
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99 | |||
100 | |||
101 | } |
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102 | |||
103 | |||
104 | { |
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105 | u32_t sblend, dblend; |
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106 | |||
107 | |||
108 | |||
109 | } |
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110 | |||
111 | |||
112 | |||
113 | local_pixmap_t *srcpix, int srcX, int srcY, |
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114 | int w, int h, int op) |
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115 | { |
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116 | u32_t dst_format, dst_offset, dst_pitch; |
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117 | u32_t txenable, colorpitch; |
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118 | u32_t blendcntl; |
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119 | int pixel_shift; |
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120 | u32_t *ring; |
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121 | |||
122 | |||
123 | |||
124 | |||
125 | |||
126 | |||
127 | |||
128 | |||
129 | |||
130 | |||
131 | |||
132 | |||
133 | |||
134 | |||
135 | |||
136 | |||
137 | dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset); |
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138 | if (((dst_pitch >> pixel_shift) & 0x7) != 0) |
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139 | dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch); |
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140 | |||
141 | |||
142 | |||
143 | return FALSE; |
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144 | |||
145 | |||
146 | |||
147 | |||
148 | |||
149 | |||
150 | |||
151 | |||
152 | |||
153 | |||
154 | * to the PVS unit of GA input (when PVS is disabled) |
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155 | * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is |
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156 | * enabled. This memory provides the imputs to the vertex shader program |
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157 | * and ordering is not important. When PVS/TCL is disabled, this field maps |
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158 | * directly to the GA input memory and the order is signifigant. In |
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159 | * PVS_BYPASS mode the order is as follows: |
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160 | * 0 Position |
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161 | * 1 Point Size |
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162 | * 2 Color 0 |
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163 | * 3 Color 1 |
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164 | * 4 Color 2 |
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165 | * 5 Color 3 |
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166 | * 6 Textures 0 |
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167 | * 7 Textures 1 |
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168 | * 8 Textures 2 |
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169 | * 9 Textures 3 - 7 |
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170 | * 14 Fog |
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171 | */ |
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172 | |||
173 | |||
174 | ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | |
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175 | (0 << R300_SKIP_DWORDS_0_SHIFT) | |
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176 | (0 << R300_DST_VEC_LOC_0_SHIFT) | |
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177 | R300_SIGNED_0 | |
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178 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | |
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179 | (0 << R300_SKIP_DWORDS_1_SHIFT) | |
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180 | (6 << R300_DST_VEC_LOC_1_SHIFT) | |
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181 | R300_LAST_VEC_1 | |
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182 | R300_SIGNED_1)); |
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183 | |||
184 | |||
185 | * We pre-load vertex programs in RADEONInit3DEngine(): |
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186 | * - exa no mask |
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187 | * - exa mask |
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188 | * - Xv |
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189 | * Here we select the offset of the vertex program we want to use |
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190 | */ |
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191 | if (info->has_tcl) { |
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192 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, |
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193 | ((3 << R300_PVS_FIRST_INST_SHIFT) | |
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194 | (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | |
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195 | (4 << R300_PVS_LAST_INST_SHIFT))); |
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196 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, |
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197 | (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); |
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198 | } |
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199 | |||
200 | |||
201 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); //VTX_COLOR_0_PRESENT |
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202 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); |
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203 | |||
204 | |||
205 | OUT_ACCEL_REG(R300_TX_ENABLE, txenable); |
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206 | FINISH_ACCEL(); |
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207 | |||
208 | |||
209 | |||
210 | |||
211 | |||
212 | if (IS_R300_3D) |
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213 | { |
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214 | u32_t output_fmt; |
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215 | int src_color, src_alpha; |
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216 | int mask_color, mask_alpha; |
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217 | |||
218 | |||
219 | |||
220 | |||
221 | |||
222 | |||
223 | mask_alpha = R300_ALU_ALPHA_1_0; |
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224 | |||
225 | |||
226 | output_fmt = (R300_OUT_FMT_C4_8 | |
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227 | R300_OUT_FMT_C0_SEL_BLUE | |
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228 | R300_OUT_FMT_C1_SEL_GREEN | |
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229 | R300_OUT_FMT_C2_SEL_RED | |
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230 | R300_OUT_FMT_C3_SEL_ALPHA); |
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231 | |||
232 | |||
233 | |||
234 | BEGIN_ACCEL(10); |
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235 | /* 2 components: 2 for tex0 */ |
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236 | OUT_ACCEL_REG(R300_RS_COUNT, |
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237 | ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
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238 | R300_RS_COUNT_HIRES_EN)); |
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239 | |||
240 | |||
241 | |||
242 | |||
243 | R300_ALU_CODE_SIZE(0) | |
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244 | R300_TEX_CODE_OFFSET(0) | |
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245 | R300_TEX_CODE_SIZE(0))); |
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246 | |||
247 | |||
248 | (R300_ALU_START(0) | |
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249 | R300_ALU_SIZE(0) | |
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250 | R300_TEX_START(0) | |
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251 | R300_TEX_SIZE(0) | |
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252 | R300_RGBA_OUT)); |
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253 | |||
254 | |||
255 | /* shader output swizzling */ |
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256 | OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); |
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257 | |||
258 | |||
259 | /* tex inst for mask texture is pre-loaded in RADEONInit3DEngine() */ |
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260 | |||
261 | |||
262 | * temp addresses for texture inputs |
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263 | * ALU_RGB_ADDR0 is src tex (temp 0) |
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264 | * ALU_RGB_ADDR1 is mask tex (temp 1) |
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265 | * R300_ALU_RGB_OMASK - output components to write |
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266 | * R300_ALU_RGB_TARGET_A - render target |
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267 | */ |
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268 | OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), |
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269 | (R300_ALU_RGB_ADDR0(0) | |
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270 | R300_ALU_RGB_ADDR1(1) | |
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271 | R300_ALU_RGB_ADDR2(0) | |
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272 | R300_ALU_RGB_ADDRD(0) | |
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273 | R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R | |
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274 | R300_ALU_RGB_MASK_G | |
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275 | R300_ALU_RGB_MASK_B)) | |
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276 | R300_ALU_RGB_TARGET_A)); |
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277 | /* RGB inst |
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278 | * ALU operation |
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279 | */ |
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280 | OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), |
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281 | (R300_ALU_RGB_SEL_A(src_color) | |
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282 | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | |
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283 | R300_ALU_RGB_SEL_B(mask_color) | |
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284 | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | |
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285 | R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | |
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286 | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | |
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287 | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | |
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288 | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | |
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289 | R300_ALU_RGB_CLAMP)); |
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290 | /* Alpha inst |
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291 | * temp addresses for texture inputs |
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292 | * ALU_ALPHA_ADDR0 is src tex (0) |
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293 | * ALU_ALPHA_ADDR1 is mask tex (1) |
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294 | * R300_ALU_ALPHA_OMASK - output components to write |
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295 | * R300_ALU_ALPHA_TARGET_A - render target |
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296 | */ |
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297 | OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), |
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298 | (R300_ALU_ALPHA_ADDR0(0) | |
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299 | R300_ALU_ALPHA_ADDR1(1) | |
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300 | R300_ALU_ALPHA_ADDR2(0) | |
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301 | R300_ALU_ALPHA_ADDRD(0) | |
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302 | R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | |
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303 | R300_ALU_ALPHA_TARGET_A | |
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304 | R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); |
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305 | /* Alpha inst |
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306 | * ALU operation |
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307 | */ |
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308 | OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), |
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309 | (R300_ALU_ALPHA_SEL_A(src_alpha) | |
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310 | R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | |
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311 | R300_ALU_ALPHA_SEL_B(mask_alpha) | |
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312 | R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) | |
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313 | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) | |
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314 | R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) | |
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315 | R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | |
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316 | R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | |
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317 | R300_ALU_ALPHA_CLAMP)); |
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318 | FINISH_ACCEL(); |
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319 | } |
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320 | else |
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321 | { |
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322 | u32_t output_fmt; |
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323 | u32_t src_color, src_alpha; |
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324 | u32_t mask_color, mask_alpha; |
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325 | |||
326 | |||
327 | R500_ALU_RGB_G_SWIZ_A_G | |
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328 | R500_ALU_RGB_B_SWIZ_A_B); |
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329 | |||
330 | |||
331 | |||
332 | |||
333 | R500_ALU_RGB_G_SWIZ_B_1 | |
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334 | R500_ALU_RGB_B_SWIZ_B_1); |
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335 | mask_alpha = R500_ALPHA_SWIZ_B_1; |
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336 | |||
337 | |||
338 | output_fmt = (R300_OUT_FMT_C4_8 | |
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339 | R300_OUT_FMT_C0_SEL_BLUE | |
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340 | R300_OUT_FMT_C1_SEL_GREEN | |
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341 | R300_OUT_FMT_C2_SEL_RED | |
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342 | R300_OUT_FMT_C3_SEL_ALPHA); |
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343 | |||
344 | |||
345 | OUT_ACCEL_REG(R300_RS_COUNT, |
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346 | ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
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347 | R300_RS_COUNT_HIRES_EN)); |
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348 | |||
349 | |||
350 | |||
351 | |||
352 | R500_US_CODE_END_ADDR(1))); |
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353 | OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | |
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354 | R500_US_CODE_RANGE_SIZE(1))); |
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355 | OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); |
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356 | |||
357 | |||
358 | COMMIT_RING(); |
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359 | |||
360 | |||
361 | OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); |
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362 | /* tex inst for src texture */ |
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363 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | |
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364 | R500_INST_TEX_SEM_WAIT | |
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365 | R500_INST_RGB_WMASK_R | |
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366 | R500_INST_RGB_WMASK_G | |
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367 | R500_INST_RGB_WMASK_B | |
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368 | R500_INST_ALPHA_WMASK | |
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369 | R500_INST_RGB_CLAMP | |
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370 | R500_INST_ALPHA_CLAMP)); |
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371 | |||
372 | |||
373 | R500_TEX_INST_LD | |
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374 | R500_TEX_SEM_ACQUIRE | |
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375 | R500_TEX_IGNORE_UNCOVERED)); |
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376 | |||
377 | |||
378 | R500_TEX_SRC_S_SWIZ_R | |
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379 | R500_TEX_SRC_T_SWIZ_G | |
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380 | R500_TEX_DST_ADDR(0) | |
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381 | R500_TEX_DST_R_SWIZ_R | |
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382 | R500_TEX_DST_G_SWIZ_G | |
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383 | R500_TEX_DST_B_SWIZ_B | |
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384 | R500_TEX_DST_A_SWIZ_A)); |
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385 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | |
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386 | R500_DX_S_SWIZ_R | |
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387 | R500_DX_T_SWIZ_R | |
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388 | R500_DX_R_SWIZ_R | |
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389 | R500_DX_Q_SWIZ_R | |
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390 | R500_DY_ADDR(0) | |
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391 | R500_DY_S_SWIZ_R | |
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392 | R500_DY_T_SWIZ_R | |
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393 | R500_DY_R_SWIZ_R | |
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394 | R500_DY_Q_SWIZ_R)); |
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395 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
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396 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
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397 | |||
398 | |||
399 | /* *_OMASK* - output component write mask */ |
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400 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | |
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401 | R500_INST_TEX_SEM_WAIT | |
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402 | R500_INST_LAST | |
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403 | R500_INST_RGB_OMASK_R | |
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404 | R500_INST_RGB_OMASK_G | |
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405 | R500_INST_RGB_OMASK_B | |
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406 | R500_INST_ALPHA_OMASK | |
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407 | R500_INST_RGB_CLAMP | |
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408 | R500_INST_ALPHA_CLAMP)); |
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409 | /* ALU inst |
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410 | * temp addresses for texture inputs |
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411 | * RGB_ADDR0 is src tex (temp 0) |
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412 | * RGB_ADDR1 is mask tex (temp 1) |
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413 | */ |
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414 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | |
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415 | R500_RGB_ADDR1(1) | |
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416 | R500_RGB_ADDR2(0))); |
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417 | /* ALU inst |
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418 | * temp addresses for texture inputs |
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419 | * ALPHA_ADDR0 is src tex (temp 0) |
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420 | * ALPHA_ADDR1 is mask tex (temp 1) |
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421 | */ |
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422 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | |
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423 | R500_ALPHA_ADDR1(1) | |
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424 | R500_ALPHA_ADDR2(0))); |
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425 | |||
426 | |||
427 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | |
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428 | src_color | |
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429 | R500_ALU_RGB_SEL_B_SRC1 | |
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430 | mask_color | |
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431 | R500_ALU_RGB_TARGET(0))); |
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432 | |||
433 | |||
434 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | |
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435 | R500_ALPHA_ADDRD(0) | |
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436 | R500_ALPHA_SEL_A_SRC0 | |
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437 | src_alpha | |
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438 | R500_ALPHA_SEL_B_SRC1 | |
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439 | mask_alpha | |
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440 | R500_ALPHA_TARGET(0))); |
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441 | |||
442 | |||
443 | R500_ALU_RGBA_ADDRD(0) | |
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444 | R500_ALU_RGBA_R_SWIZ_0 | |
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445 | R500_ALU_RGBA_G_SWIZ_0 | |
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446 | R500_ALU_RGBA_B_SWIZ_0 | |
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447 | R500_ALU_RGBA_A_SWIZ_0)); |
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448 | FINISH_ACCEL(); |
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449 | } |
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450 | |||
451 | |||
452 | OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); |
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453 | OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); |
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454 | |||
455 | |||
456 | OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | |
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457 | R300_READ_ENABLE); |
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458 | |||
459 | |||
460 | |||
461 | |||
462 | } |
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463 | |||
464 | |||
465 | |||
466 | |||
467 | |||
468 | { |
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469 | union { |
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470 | float f; |
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471 | u32_t l; |
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472 | }tmp; |
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473 | tmp.f = val; |
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474 | return tmp.l; |
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475 | } |
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476 | |||
477 | |||
478 | |||
479 | |||
480 | |||
481 | |||
482 | do { \ |
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483 | OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ |
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484 | OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ |
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485 | OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ |
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486 | OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ |
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487 | } while (0) |
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488 | |||
489 | |||
490 | |||
491 | |||
492 | |||
493 | |||
494 | do { \ |
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495 | OUT_RING_F(_dstX); \ |
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496 | OUT_RING_F(_dstY); \ |
||
497 | OUT_RING_F(_srcX); \ |
||
498 | OUT_RING_F(_srcY); \ |
||
499 | } while (0) |
||
500 | |||
501 | |||
502 | |||
503 | |||
504 | int dstX, int dstY, |
||
505 | int w, int h) |
||
506 | { |
||
507 | int vtx_count; |
||
508 | xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; |
||
509 | xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; |
||
510 | |||
511 | |||
512 | |||
513 | |||
514 | |||
515 | |||
516 | srcTopLeft.y = IntToxFixed(srcY); |
||
517 | srcTopRight.x = IntToxFixed(srcX + w); |
||
518 | srcTopRight.y = IntToxFixed(srcY); |
||
519 | srcBottomLeft.x = IntToxFixed(srcX); |
||
520 | srcBottomLeft.y = IntToxFixed(srcY + h); |
||
521 | srcBottomRight.x = IntToxFixed(srcX + w); |
||
522 | srcBottomRight.y = IntToxFixed(srcY + h); |
||
523 | |||
524 | |||
525 | |||
526 | |||
527 | |||
528 | |||
529 | OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
||
530 | OUT_ACCEL_REG(RADEON_SE_VF_CNTL, |
||
531 | (RADEON_VF_PRIM_TYPE_QUAD_LIST | |
||
532 | RADEON_VF_PRIM_WALK_DATA | |
||
533 | (4 << RADEON_VF_NUM_VERTICES_SHIFT))); |
||
534 | |||
535 | |||
536 | BEGIN_ACCEL(7 + 4 * vtx_count); |
||
537 | OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
||
538 | |||
539 | |||
540 | 4 * vtx_count)); |
||
541 | OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | |
||
542 | RADEON_CP_VC_CNTL_PRIM_WALK_RING | |
||
543 | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); |
||
544 | |||
545 | |||
546 | |||
547 | |||
548 | xFixedToFloat(srcTopLeft.x) / w, // info->texW[0], |
||
549 | xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]); |
||
550 | |||
551 | |||
552 | xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0], |
||
553 | xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]); |
||
554 | |||
555 | |||
556 | xFixedToFloat(srcBottomRight.x) / w, // info->texW[0], |
||
557 | xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]); |
||
558 | |||
559 | |||
560 | xFixedToFloat(srcTopRight.x) / w, // info->texW[0], |
||
561 | xFixedToFloat(srcTopRight.y) / h); // info->texH[0]); |
||
562 | |||
563 | |||
564 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); |
||
565 | OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
||
566 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); |
||
567 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); |
||
568 | |||
569 | |||
570 | } |
||
571 | |||
572 | |||
573 | |||
574 | #undef VTX_OUT_MASK |
||
575 | |||
576 | |||
577 | |||
578 | { |
||
579 | int tileSrcY, tileMaskY, tileDstY; |
||
580 | int remainingHeight; |
||
581 | |||
582 | |||
583 | local_pixmap_t *dstpixmap; |
||
584 | |||
585 | |||
586 | |||
587 | |||
588 | srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ; |
||
589 | |||
590 | |||
591 | |||
592 | |||
593 | u32_t *ring; |
||
594 | |||
595 | |||
596 | |||
597 | |||
598 | |||
599 | |||
600 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
||
601 | RADEON_GMC_BRUSH_SOLID_COLOR | |
||
602 | RADEON_GMC_DST_32BPP | |
||
603 | RADEON_GMC_SRC_DATATYPE_COLOR | |
||
604 | R5XX_GMC_CLR_CMP_CNTL_DIS | |
||
605 | R5XX_ROP3_P |
||
606 | ); |
||
607 | |||
608 | |||
609 | OUTREG(R5XX_DP_BRUSH_FRGD_CLR, blit->alpha<<24); |
||
610 | OUTREG(R5XX_DP_WRITE_MASK, 0xFF000000); |
||
611 | OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
||
612 | OUTREG(R5XX_DST_Y_X, 0); |
||
613 | OUTREG(R5XX_DST_WIDTH_HEIGHT,(srcpixmap->width<<16)|srcpixmap->height); |
||
614 | |||
615 | |||
616 | | RADEON_WAIT_HOST_IDLECLEAN ); |
||
617 | |||
618 | |||
619 | OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_HOST_IDLECLEAN | |
||
620 | RADEON_WAIT_2D_IDLECLEAN); |
||
621 | |||
622 | |||
623 | BEGIN_RING(2 + 6); |
||
624 | |||
625 | |||
626 | |||
627 | |||
628 | |||
629 | |||
630 | RADEON_GMC_BRUSH_SOLID_COLOR | |
||
631 | RADEON_GMC_DST_32BPP | |
||
632 | RADEON_GMC_SRC_DATATYPE_COLOR | |
||
633 | R5XX_GMC_CLR_CMP_CNTL_DIS | |
||
634 | R5XX_ROP3_P |
||
635 | ); |
||
636 | |||
637 | |||
638 | OUT_RING(blit->alpha<<24); |
||
639 | OUT_RING( 0 ); |
||
640 | OUT_RING((srcpixmap->width<<16)|srcpixmap->height); |
||
641 | |||
642 | |||
643 | #endif |
||
644 | RHDPtr info = &rhd; |
||
645 | |||
646 | |||
647 | delay(2); |
||
648 | |||
649 | |||
650 | { |
||
651 | R300PrepareComposite(dstpixmap, blit->dst_x, blit->dst_y, |
||
652 | srcpixmap, blit->src_x, blit->src_y, |
||
653 | blit->w, blit->h, 3); |
||
654 | |||
655 | |||
656 | blit->dst_x, blit->dst_y, |
||
657 | blit->w, blit->h); |
||
658 | } |
||
659 | else if ((info->ChipFamily == CHIP_FAMILY_RV250) || |
||
660 | (info->ChipFamily == CHIP_FAMILY_RV280) || |
||
661 | (info->ChipFamily == CHIP_FAMILY_RS300) || |
||
662 | (info->ChipFamily == CHIP_FAMILY_R200)) |
||
663 | { |
||
664 | }; |
||
665 | |||
666 | |||
667 | |||
668 | |||
669 | delay(2); |
||
670 | |||
671 | |||
672 | |||
673 | |||
674 | };16)|srcpixmap-><16)|srcpixmap->24); |
||
675 | ><24); |
||
676 | |||
677 |