WebSVN – Kolibri OS – Blame – /drivers/video/Intel-2D/gen6_render.c

Rev	Author	Line No.	Line
3254	Serge	1	/*
		2	* Copyright © 2006,2008,2011 Intel Corporation
		3	* Copyright © 2007 Red Hat, Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice (including the next
		13	* paragraph) shall be included in all copies or substantial portions of the
		14	* Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
		21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
		22	* SOFTWARE.
		23	*
		24	* Authors:
		25	* Wang Zhenyu
		26	* Eric Anholt
		27	* Carl Worth
		28	* Keith Packard
		29	* Chris Wilson
		30	*
		31	*/
		32
		33	#ifdef HAVE_CONFIG_H
		34	#include "config.h"
		35	#endif
		36
		37	#include "sna.h"
		38	#include "sna_reg.h"
		39	#include "sna_render.h"
3278	Serge	40	#include "sna_render_inline.h"
3254	Serge	41	//#include "sna_video.h"
		42
		43	#include "brw/brw.h"
		44	#include "gen6_render.h"
3291	Serge	45	#include "gen4_source.h"
3254	Serge	46	#include "gen4_vertex.h"
		47
		48	#define NO_COMPOSITE 0
		49	#define NO_COMPOSITE_SPANS 0
		50	#define NO_COPY 0
		51	#define NO_COPY_BOXES 0
		52	#define NO_FILL 0
		53	#define NO_FILL_BOXES 0
		54	#define NO_FILL_ONE 0
		55	#define NO_FILL_CLEAR 0
		56
		57	#define NO_RING_SWITCH 1
		58	#define PREFER_RENDER 0
		59
		60	#define USE_8_PIXEL_DISPATCH 1
		61	#define USE_16_PIXEL_DISPATCH 1
		62	#define USE_32_PIXEL_DISPATCH 0
		63
		64	#if !USE_8_PIXEL_DISPATCH && !USE_16_PIXEL_DISPATCH && !USE_32_PIXEL_DISPATCH
		65	#error "Must select at least 8, 16 or 32 pixel dispatch"
		66	#endif
		67
		68	#define GEN6_MAX_SIZE 8192
		69
		70	struct gt_info {
		71	int max_vs_threads;
		72	int max_gs_threads;
		73	int max_wm_threads;
		74	struct {
		75	int size;
		76	int max_vs_entries;
		77	int max_gs_entries;
		78	} urb;
		79	};
		80
		81	static const struct gt_info gt1_info = {
		82	.max_vs_threads = 24,
		83	.max_gs_threads = 21,
		84	.max_wm_threads = 40,
		85	.urb = { 32, 256, 256 },
		86	};
		87
		88	static const struct gt_info gt2_info = {
		89	.max_vs_threads = 60,
		90	.max_gs_threads = 60,
		91	.max_wm_threads = 80,
		92	.urb = { 64, 256, 256 },
		93	};
		94
		95	static const uint32_t ps_kernel_packed[][4] = {
		96	#include "exa_wm_src_affine.g6b"
		97	#include "exa_wm_src_sample_argb.g6b"
		98	#include "exa_wm_yuv_rgb.g6b"
		99	#include "exa_wm_write.g6b"
		100	};
		101
		102	static const uint32_t ps_kernel_planar[][4] = {
		103	#include "exa_wm_src_affine.g6b"
		104	#include "exa_wm_src_sample_planar.g6b"
		105	#include "exa_wm_yuv_rgb.g6b"
		106	#include "exa_wm_write.g6b"
		107	};
		108
		109	#define NOKERNEL(kernel_enum, func, ns) \
		110	[GEN6_WM_KERNEL_##kernel_enum] = {#kernel_enum, func, 0, ns}
		111	#define KERNEL(kernel_enum, kernel, ns) \
		112	[GEN6_WM_KERNEL_##kernel_enum] = {#kernel_enum, kernel, sizeof(kernel), ns}
		113
		114	static const struct wm_kernel_info {
		115	const char *name;
		116	const void *data;
		117	unsigned int size;
		118	unsigned int num_surfaces;
		119	} wm_kernels[] = {
		120	NOKERNEL(NOMASK, brw_wm_kernel__affine, 2),
		121	NOKERNEL(NOMASK_P, brw_wm_kernel__projective, 2),
		122
		123	NOKERNEL(MASK, brw_wm_kernel__affine_mask, 3),
		124	NOKERNEL(MASK_P, brw_wm_kernel__projective_mask, 3),
		125
		126	NOKERNEL(MASKCA, brw_wm_kernel__affine_mask_ca, 3),
		127	NOKERNEL(MASKCA_P, brw_wm_kernel__projective_mask_ca, 3),
		128
		129	NOKERNEL(MASKSA, brw_wm_kernel__affine_mask_sa, 3),
		130	NOKERNEL(MASKSA_P, brw_wm_kernel__projective_mask_sa, 3),
		131
		132	NOKERNEL(OPACITY, brw_wm_kernel__affine_opacity, 2),
		133	NOKERNEL(OPACITY_P, brw_wm_kernel__projective_opacity, 2),
		134
		135	KERNEL(VIDEO_PLANAR, ps_kernel_planar, 7),
		136	KERNEL(VIDEO_PACKED, ps_kernel_packed, 2),
		137	};
		138	#undef KERNEL
		139
		140	static const struct blendinfo {
		141	bool src_alpha;
		142	uint32_t src_blend;
		143	uint32_t dst_blend;
		144	} gen6_blend_op[] = {
		145	/* Clear */ {0, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_ZERO},
		146	/* Src */ {0, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_ZERO},
		147	/* Dst */ {0, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_ONE},
		148	/* Over */ {1, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_INV_SRC_ALPHA},
		149	/* OverReverse */ {0, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_ONE},
		150	/* In */ {0, GEN6_BLENDFACTOR_DST_ALPHA, GEN6_BLENDFACTOR_ZERO},
		151	/* InReverse */ {1, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_SRC_ALPHA},
		152	/* Out */ {0, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_ZERO},
		153	/* OutReverse */ {1, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_INV_SRC_ALPHA},
		154	/* Atop */ {1, GEN6_BLENDFACTOR_DST_ALPHA, GEN6_BLENDFACTOR_INV_SRC_ALPHA},
		155	/* AtopReverse */ {1, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_SRC_ALPHA},
		156	/* Xor */ {1, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_INV_SRC_ALPHA},
		157	/* Add */ {0, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_ONE},
		158	};
		159
		160	/**
		161	* Highest-valued BLENDFACTOR used in gen6_blend_op.
		162	*
		163	* This leaves out GEN6_BLENDFACTOR_INV_DST_COLOR,
		164	* GEN6_BLENDFACTOR_INV_CONST_{COLOR,ALPHA},
		165	* GEN6_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA}
		166	*/
		167	#define GEN6_BLENDFACTOR_COUNT (GEN6_BLENDFACTOR_INV_DST_ALPHA + 1)
		168
		169	#define GEN6_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen6_blend_state), 64)
		170
		171	#define BLEND_OFFSET(s, d) \
		172	(((s) * GEN6_BLENDFACTOR_COUNT + (d)) * GEN6_BLEND_STATE_PADDED_SIZE)
		173
		174	#define NO_BLEND BLEND_OFFSET(GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_ZERO)
		175	#define CLEAR BLEND_OFFSET(GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_ZERO)
		176
		177	#define SAMPLER_OFFSET(sf, se, mf, me) \
		178	(((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me) + 2) * 2 * sizeof(struct gen6_sampler_state))
		179
		180	#define VERTEX_2s2s 0
		181
		182	#define COPY_SAMPLER 0
		183	#define COPY_VERTEX VERTEX_2s2s
		184	#define COPY_FLAGS(a) GEN6_SET_FLAGS(COPY_SAMPLER, (a) == GXcopy ? NO_BLEND : CLEAR, GEN6_WM_KERNEL_NOMASK, COPY_VERTEX)
		185
		186	#define FILL_SAMPLER (2 * sizeof(struct gen6_sampler_state))
		187	#define FILL_VERTEX VERTEX_2s2s
		188	#define FILL_FLAGS(op, format) GEN6_SET_FLAGS(FILL_SAMPLER, gen6_get_blend((op), false, (format)), GEN6_WM_KERNEL_NOMASK, FILL_VERTEX)
		189	#define FILL_FLAGS_NOBLEND GEN6_SET_FLAGS(FILL_SAMPLER, NO_BLEND, GEN6_WM_KERNEL_NOMASK, FILL_VERTEX)
		190
		191	#define GEN6_SAMPLER(f) (((f) >> 16) & 0xfff0)
		192	#define GEN6_BLEND(f) (((f) >> 0) & 0xfff0)
		193	#define GEN6_KERNEL(f) (((f) >> 16) & 0xf)
		194	#define GEN6_VERTEX(f) (((f) >> 0) & 0xf)
		195	#define GEN6_SET_FLAGS(S, B, K, V) (((S) \| (K)) << 16 \| ((B) \| (V)))
		196
		197	#define OUT_BATCH(v) batch_emit(sna, v)
		198	#define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y)
		199	#define OUT_VERTEX_F(v) vertex_emit(sna, v)
		200
		201	static inline bool too_large(int width, int height)
		202	{
		203	return width > GEN6_MAX_SIZE \|\| height > GEN6_MAX_SIZE;
		204	}
		205
		206	static uint32_t gen6_get_blend(int op,
		207	bool has_component_alpha,
		208	uint32_t dst_format)
		209	{
		210	uint32_t src, dst;
		211
		212
		213	src = GEN6_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend;
		214	dst = GEN6_BLENDFACTOR_INV_SRC_ALPHA; //gen6_blend_op[op].dst_blend;
		215
3291	Serge	216	// dst = GEN6_BLENDFACTOR_ZERO; //gen6_blend_op[op].dst_blend;
		217
3254	Serge	218	#if 0
		219	/* If there's no dst alpha channel, adjust the blend op so that
		220	* we'll treat it always as 1.
		221	*/
		222	if (PICT_FORMAT_A(dst_format) == 0) {
		223	if (src == GEN6_BLENDFACTOR_DST_ALPHA)
		224	src = GEN6_BLENDFACTOR_ONE;
		225	else if (src == GEN6_BLENDFACTOR_INV_DST_ALPHA)
		226	src = GEN6_BLENDFACTOR_ZERO;
		227	}
		228
		229	/* If the source alpha is being used, then we should only be in a
		230	* case where the source blend factor is 0, and the source blend
		231	* value is the mask channels multiplied by the source picture's alpha.
		232	*/
		233	if (has_component_alpha && gen6_blend_op[op].src_alpha) {
		234	if (dst == GEN6_BLENDFACTOR_SRC_ALPHA)
		235	dst = GEN6_BLENDFACTOR_SRC_COLOR;
		236	else if (dst == GEN6_BLENDFACTOR_INV_SRC_ALPHA)
		237	dst = GEN6_BLENDFACTOR_INV_SRC_COLOR;
		238	}
		239
		240	DBG(("blend op=%d, dst=%x [A=%d] => src=%d, dst=%d => offset=%x\n",
		241	op, dst_format, PICT_FORMAT_A(dst_format),
		242	src, dst, (int)BLEND_OFFSET(src, dst)));
		243	#endif
		244
		245	return BLEND_OFFSET(src, dst);
		246	}
		247
		248	static uint32_t gen6_get_card_format(PictFormat format)
		249	{
3278	Serge	250	switch (format) {
		251	default:
		252	return -1;
		253	case PICT_a8r8g8b8:
3254	Serge	254	return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM;
3278	Serge	255	case PICT_x8r8g8b8:
		256	return GEN6_SURFACEFORMAT_B8G8R8X8_UNORM;
		257	case PICT_a8:
		258	return GEN6_SURFACEFORMAT_A8_UNORM;
		259	};
3254	Serge	260
		261	/*
		262	switch (format) {
		263	default:
		264	return -1;
		265	case PICT_a8r8g8b8:
		266	return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM;
		267	case PICT_x8r8g8b8:
		268	return GEN6_SURFACEFORMAT_B8G8R8X8_UNORM;
		269	case PICT_a8b8g8r8:
		270	return GEN6_SURFACEFORMAT_R8G8B8A8_UNORM;
		271	case PICT_x8b8g8r8:
		272	return GEN6_SURFACEFORMAT_R8G8B8X8_UNORM;
		273	case PICT_a2r10g10b10:
		274	return GEN6_SURFACEFORMAT_B10G10R10A2_UNORM;
		275	case PICT_x2r10g10b10:
		276	return GEN6_SURFACEFORMAT_B10G10R10X2_UNORM;
		277	case PICT_r8g8b8:
		278	return GEN6_SURFACEFORMAT_R8G8B8_UNORM;
		279	case PICT_r5g6b5:
		280	return GEN6_SURFACEFORMAT_B5G6R5_UNORM;
		281	case PICT_a1r5g5b5:
		282	return GEN6_SURFACEFORMAT_B5G5R5A1_UNORM;
		283	case PICT_a8:
		284	return GEN6_SURFACEFORMAT_A8_UNORM;
		285	case PICT_a4r4g4b4:
		286	return GEN6_SURFACEFORMAT_B4G4R4A4_UNORM;
		287	}
		288	*/
		289	}
		290
		291	static uint32_t gen6_get_dest_format(PictFormat format)
		292	{
		293	return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM;
		294
		295	#if 0
		296
		297	switch (format) {
		298	default:
		299	return -1;
		300	case PICT_a8r8g8b8:
		301	case PICT_x8r8g8b8:
		302	return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM;
		303	case PICT_a8b8g8r8:
		304	case PICT_x8b8g8r8:
		305	return GEN6_SURFACEFORMAT_R8G8B8A8_UNORM;
		306	case PICT_a2r10g10b10:
		307	case PICT_x2r10g10b10:
		308	return GEN6_SURFACEFORMAT_B10G10R10A2_UNORM;
		309	case PICT_r5g6b5:
		310	return GEN6_SURFACEFORMAT_B5G6R5_UNORM;
		311	case PICT_x1r5g5b5:
		312	case PICT_a1r5g5b5:
		313	return GEN6_SURFACEFORMAT_B5G5R5A1_UNORM;
		314	case PICT_a8:
		315	return GEN6_SURFACEFORMAT_A8_UNORM;
		316	case PICT_a4r4g4b4:
		317	case PICT_x4r4g4b4:
		318	return GEN6_SURFACEFORMAT_B4G4R4A4_UNORM;
		319	}
		320	#endif
		321
		322	}
		323
		324	#if 0
		325
		326	static bool gen6_check_dst_format(PictFormat format)
		327	{
		328	if (gen6_get_dest_format(format) != -1)
		329	return true;
		330
		331	DBG(("%s: unhandled format: %x\n", __FUNCTION__, (int)format));
		332	return false;
		333	}
		334
		335	static bool gen6_check_format(uint32_t format)
		336	{
		337	if (gen6_get_card_format(format) != -1)
		338	return true;
		339
		340	DBG(("%s: unhandled format: %x\n", __FUNCTION__, (int)format));
		341	return false;
		342	}
		343
		344	static uint32_t gen6_filter(uint32_t filter)
		345	{
		346	switch (filter) {
		347	default:
		348	assert(0);
		349	case PictFilterNearest:
		350	return SAMPLER_FILTER_NEAREST;
		351	case PictFilterBilinear:
		352	return SAMPLER_FILTER_BILINEAR;
		353	}
		354	}
		355
		356	static uint32_t gen6_check_filter(PicturePtr picture)
		357	{
		358	switch (picture->filter) {
		359	case PictFilterNearest:
		360	case PictFilterBilinear:
		361	return true;
		362	default:
		363	return false;
		364	}
		365	}
		366
		367	static uint32_t gen6_repeat(uint32_t repeat)
		368	{
		369	switch (repeat) {
		370	default:
		371	assert(0);
		372	case RepeatNone:
		373	return SAMPLER_EXTEND_NONE;
		374	case RepeatNormal:
		375	return SAMPLER_EXTEND_REPEAT;
		376	case RepeatPad:
		377	return SAMPLER_EXTEND_PAD;
		378	case RepeatReflect:
		379	return SAMPLER_EXTEND_REFLECT;
		380	}
		381	}
		382
		383	static bool gen6_check_repeat(PicturePtr picture)
		384	{
		385	if (!picture->repeat)
		386	return true;
		387
		388	switch (picture->repeatType) {
		389	case RepeatNone:
		390	case RepeatNormal:
		391	case RepeatPad:
		392	case RepeatReflect:
		393	return true;
		394	default:
		395	return false;
		396	}
		397	}
		398	#endif
		399
		400	static int
		401	gen6_choose_composite_kernel(int op, bool has_mask, bool is_ca, bool is_affine)
		402	{
		403	int base;
		404
		405	if (has_mask) {
3278	Serge	406
3254	Serge	407	if (is_ca) {
		408	if (gen6_blend_op[op].src_alpha)
3258	Serge	409	base = GEN6_WM_KERNEL_MASKSA;
3254	Serge	410	else
		411	base = GEN6_WM_KERNEL_MASKCA;
		412	} else
		413	base = GEN6_WM_KERNEL_MASK;
3278	Serge	414
3254	Serge	415	} else
		416	base = GEN6_WM_KERNEL_NOMASK;
		417
		418	return base + !is_affine;
		419	}
		420
		421	static void
		422	gen6_emit_urb(struct sna *sna)
		423	{
		424	OUT_BATCH(GEN6_3DSTATE_URB \| (3 - 2));
		425	OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) \|
		426	(sna->render_state.gen6.info->urb.max_vs_entries << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
		427	OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) \|
		428	(0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
		429	}
		430
		431	static void
		432	gen6_emit_state_base_address(struct sna *sna)
		433	{
		434	OUT_BATCH(GEN6_STATE_BASE_ADDRESS \| (10 - 2));
		435	OUT_BATCH(0); /* general */
		436	OUT_BATCH(kgem_add_reloc(&sna->kgem, /* surface */
		437	sna->kgem.nbatch,
		438	NULL,
		439	I915_GEM_DOMAIN_INSTRUCTION << 16,
		440	BASE_ADDRESS_MODIFY));
		441	OUT_BATCH(kgem_add_reloc(&sna->kgem, /* instruction */
		442	sna->kgem.nbatch,
		443	sna->render_state.gen6.general_bo,
		444	I915_GEM_DOMAIN_INSTRUCTION << 16,
		445	BASE_ADDRESS_MODIFY));
		446	OUT_BATCH(0); /* indirect */
		447	OUT_BATCH(kgem_add_reloc(&sna->kgem,
		448	sna->kgem.nbatch,
		449	sna->render_state.gen6.general_bo,
		450	I915_GEM_DOMAIN_INSTRUCTION << 16,
		451	BASE_ADDRESS_MODIFY));
		452
		453	/* upper bounds, disable */
		454	OUT_BATCH(0);
		455	OUT_BATCH(BASE_ADDRESS_MODIFY);
		456	OUT_BATCH(0);
		457	OUT_BATCH(BASE_ADDRESS_MODIFY);
		458	}
		459
		460	static void
		461	gen6_emit_viewports(struct sna *sna)
		462	{
		463	OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS \|
		464	GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC \|
		465	(4 - 2));
		466	OUT_BATCH(0);
		467	OUT_BATCH(0);
		468	OUT_BATCH(0);
		469	}
		470
		471	static void
		472	gen6_emit_vs(struct sna *sna)
		473	{
		474	/* disable VS constant buffer */
		475	OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS \| (5 - 2));
		476	OUT_BATCH(0);
		477	OUT_BATCH(0);
		478	OUT_BATCH(0);
		479	OUT_BATCH(0);
		480
		481	OUT_BATCH(GEN6_3DSTATE_VS \| (6 - 2));
		482	OUT_BATCH(0); /* no VS kernel */
		483	OUT_BATCH(0);
		484	OUT_BATCH(0);
		485	OUT_BATCH(0);
		486	OUT_BATCH(0); /* pass-through */
		487	}
		488
		489	static void
		490	gen6_emit_gs(struct sna *sna)
		491	{
		492	/* disable GS constant buffer */
		493	OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS \| (5 - 2));
		494	OUT_BATCH(0);
		495	OUT_BATCH(0);
		496	OUT_BATCH(0);
		497	OUT_BATCH(0);
		498
		499	OUT_BATCH(GEN6_3DSTATE_GS \| (7 - 2));
		500	OUT_BATCH(0); /* no GS kernel */
		501	OUT_BATCH(0);
		502	OUT_BATCH(0);
		503	OUT_BATCH(0);
		504	OUT_BATCH(0);
		505	OUT_BATCH(0); /* pass-through */
		506	}
		507
		508	static void
		509	gen6_emit_clip(struct sna *sna)
		510	{
		511	OUT_BATCH(GEN6_3DSTATE_CLIP \| (4 - 2));
		512	OUT_BATCH(0);
		513	OUT_BATCH(0); /* pass-through */
		514	OUT_BATCH(0);
		515	}
		516
		517	static void
		518	gen6_emit_wm_constants(struct sna *sna)
		519	{
		520	/* disable WM constant buffer */
		521	OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS \| (5 - 2));
		522	OUT_BATCH(0);
		523	OUT_BATCH(0);
		524	OUT_BATCH(0);
		525	OUT_BATCH(0);
		526	}
		527
		528	static void
		529	gen6_emit_null_depth_buffer(struct sna *sna)
		530	{
		531	OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER \| (7 - 2));
		532	OUT_BATCH(GEN6_SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT \|
		533	GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
		534	OUT_BATCH(0);
		535	OUT_BATCH(0);
		536	OUT_BATCH(0);
		537	OUT_BATCH(0);
		538	OUT_BATCH(0);
		539
		540	OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS \| (2 - 2));
		541	OUT_BATCH(0);
		542	}
		543
		544	static void
		545	gen6_emit_invariant(struct sna *sna)
		546	{
		547	OUT_BATCH(GEN6_PIPELINE_SELECT \| PIPELINE_SELECT_3D);
		548
		549	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE \| (3 - 2));
		550	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER \|
		551	GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
		552	OUT_BATCH(0);
		553
		554	OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK \| (2 - 2));
		555	OUT_BATCH(1);
		556
		557	gen6_emit_urb(sna);
		558
		559	gen6_emit_state_base_address(sna);
		560
		561	gen6_emit_viewports(sna);
		562	gen6_emit_vs(sna);
		563	gen6_emit_gs(sna);
		564	gen6_emit_clip(sna);
		565	gen6_emit_wm_constants(sna);
		566	gen6_emit_null_depth_buffer(sna);
		567
		568	sna->render_state.gen6.needs_invariant = false;
		569	}
		570
		571	static bool
		572	gen6_emit_cc(struct sna *sna, int blend)
		573	{
		574	struct gen6_render_state *render = &sna->render_state.gen6;
		575
		576	if (render->blend == blend)
		577	return blend != NO_BLEND;
		578
		579	DBG(("%s: blend = %x\n", __FUNCTION__, blend));
		580
		581	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS \| (4 - 2));
		582	OUT_BATCH((render->cc_blend + blend) \| 1);
		583	if (render->blend == (unsigned)-1) {
		584	OUT_BATCH(1);
		585	OUT_BATCH(1);
		586	} else {
		587	OUT_BATCH(0);
		588	OUT_BATCH(0);
		589	}
		590
		591	render->blend = blend;
		592	return blend != NO_BLEND;
		593	}
		594
		595	static void
		596	gen6_emit_sampler(struct sna *sna, uint32_t state)
		597	{
		598	if (sna->render_state.gen6.samplers == state)
		599	return;
		600
		601	sna->render_state.gen6.samplers = state;
		602
		603	DBG(("%s: sampler = %x\n", __FUNCTION__, state));
		604
		605	OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS \|
		606	GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS \|
		607	(4 - 2));
		608	OUT_BATCH(0); /* VS */
		609	OUT_BATCH(0); /* GS */
		610	OUT_BATCH(sna->render_state.gen6.wm_state + state);
		611	}
		612
		613	static void
		614	gen6_emit_sf(struct sna *sna, bool has_mask)
		615	{
		616	int num_sf_outputs = has_mask ? 2 : 1;
		617
		618	if (sna->render_state.gen6.num_sf_outputs == num_sf_outputs)
		619	return;
		620
		621	DBG(("%s: num_sf_outputs=%d, read_length=%d, read_offset=%d\n",
		622	__FUNCTION__, num_sf_outputs, 1, 0));
		623
		624	sna->render_state.gen6.num_sf_outputs = num_sf_outputs;
		625
		626	OUT_BATCH(GEN6_3DSTATE_SF \| (20 - 2));
		627	OUT_BATCH(num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT \|
		628	1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT \|
		629	1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT);
		630	OUT_BATCH(0);
		631	OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
		632	OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
		633	OUT_BATCH(0);
		634	OUT_BATCH(0);
		635	OUT_BATCH(0);
		636	OUT_BATCH(0);
		637	OUT_BATCH(0); /* DW9 */
		638	OUT_BATCH(0);
		639	OUT_BATCH(0);
		640	OUT_BATCH(0);
		641	OUT_BATCH(0);
		642	OUT_BATCH(0); /* DW14 */
		643	OUT_BATCH(0);
		644	OUT_BATCH(0);
		645	OUT_BATCH(0);
		646	OUT_BATCH(0);
		647	OUT_BATCH(0); /* DW19 */
		648	}
		649
		650	static void
		651	gen6_emit_wm(struct sna *sna, unsigned int kernel, bool has_mask)
		652	{
		653	const uint32_t *kernels;
		654
		655	if (sna->render_state.gen6.kernel == kernel)
		656	return;
		657
		658	sna->render_state.gen6.kernel = kernel;
		659	kernels = sna->render_state.gen6.wm_kernel[kernel];
		660
		661	DBG(("%s: switching to %s, num_surfaces=%d (8-pixel? %d, 16-pixel? %d,32-pixel? %d)\n",
		662	__FUNCTION__,
		663	wm_kernels[kernel].name, wm_kernels[kernel].num_surfaces,
		664	kernels[0], kernels[1], kernels[2]));
		665
		666	OUT_BATCH(GEN6_3DSTATE_WM \| (9 - 2));
		667	OUT_BATCH(kernels[0] ?: kernels[1] ?: kernels[2]);
		668	OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT \|
		669	wm_kernels[kernel].num_surfaces << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
		670	OUT_BATCH(0); /* scratch space */
		671	OUT_BATCH((kernels[0] ? 4 : kernels[1] ? 6 : 8) << GEN6_3DSTATE_WM_DISPATCH_0_START_GRF_SHIFT \|
		672	8 << GEN6_3DSTATE_WM_DISPATCH_1_START_GRF_SHIFT \|
		673	6 << GEN6_3DSTATE_WM_DISPATCH_2_START_GRF_SHIFT);
		674	OUT_BATCH((sna->render_state.gen6.info->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT \|
		675	(kernels[0] ? GEN6_3DSTATE_WM_8_DISPATCH_ENABLE : 0) \|
		676	(kernels[1] ? GEN6_3DSTATE_WM_16_DISPATCH_ENABLE : 0) \|
		677	(kernels[2] ? GEN6_3DSTATE_WM_32_DISPATCH_ENABLE : 0) \|
		678	GEN6_3DSTATE_WM_DISPATCH_ENABLE);
		679	OUT_BATCH((1 + has_mask) << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT \|
		680	GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
		681	OUT_BATCH(kernels[2]);
		682	OUT_BATCH(kernels[1]);
		683	}
		684
		685	static bool
		686	gen6_emit_binding_table(struct sna *sna, uint16_t offset)
		687	{
		688	if (sna->render_state.gen6.surface_table == offset)
		689	return false;
		690
		691	/* Binding table pointers */
		692	OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS \|
		693	GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS \|
		694	(4 - 2));
		695	OUT_BATCH(0); /* vs */
		696	OUT_BATCH(0); /* gs */
		697	/* Only the PS uses the binding table */
		698	OUT_BATCH(offset*4);
		699
		700	sna->render_state.gen6.surface_table = offset;
		701	return true;
		702	}
		703
		704	static bool
		705	gen6_emit_drawing_rectangle(struct sna *sna,
		706	const struct sna_composite_op *op)
		707	{
		708	uint32_t limit = (op->dst.height - 1) << 16 \| (op->dst.width - 1);
		709	uint32_t offset = (uint16_t)op->dst.y << 16 \| (uint16_t)op->dst.x;
		710
		711	assert(!too_large(op->dst.x, op->dst.y));
		712	assert(!too_large(op->dst.width, op->dst.height));
		713
		714	if (sna->render_state.gen6.drawrect_limit == limit &&
		715	sna->render_state.gen6.drawrect_offset == offset)
		716	return false;
		717
		718	/* [DevSNB-C+{W/A}] Before any depth stall flush (including those
		719	* produced by non-pipelined state commands), software needs to first
		720	* send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
		721	* 0.
		722	*
		723	* [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
		724	* BEFORE the pipe-control with a post-sync op and no write-cache
		725	* flushes.
		726	*/
		727	if (!sna->render_state.gen6.first_state_packet) {
		728	OUT_BATCH(GEN6_PIPE_CONTROL \| (4 - 2));
		729	OUT_BATCH(GEN6_PIPE_CONTROL_CS_STALL \|
		730	GEN6_PIPE_CONTROL_STALL_AT_SCOREBOARD);
		731	OUT_BATCH(0);
		732	OUT_BATCH(0);
		733	}
		734
		735	OUT_BATCH(GEN6_PIPE_CONTROL \| (4 - 2));
		736	OUT_BATCH(GEN6_PIPE_CONTROL_WRITE_TIME);
		737	OUT_BATCH(kgem_add_reloc(&sna->kgem, sna->kgem.nbatch,
		738	sna->render_state.gen6.general_bo,
		739	I915_GEM_DOMAIN_INSTRUCTION << 16 \|
		740	I915_GEM_DOMAIN_INSTRUCTION,
		741	64));
		742	OUT_BATCH(0);
		743
		744	OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE \| (4 - 2));
		745	OUT_BATCH(0);
		746	OUT_BATCH(limit);
		747	OUT_BATCH(offset);
		748
		749	sna->render_state.gen6.drawrect_offset = offset;
		750	sna->render_state.gen6.drawrect_limit = limit;
		751	return true;
		752	}
		753
		754	static void
		755	gen6_emit_vertex_elements(struct sna *sna,
		756	const struct sna_composite_op *op)
		757	{
		758	/*
		759	* vertex data in vertex buffer
		760	* position: (x, y)
		761	* texture coordinate 0: (u0, v0) if (is_affine is true) else (u0, v0, w0)
		762	* texture coordinate 1 if (has_mask is true): same as above
		763	*/
		764	struct gen6_render_state *render = &sna->render_state.gen6;
		765	uint32_t src_format, dw;
		766	int id = GEN6_VERTEX(op->u.gen6.flags);
		767	bool has_mask;
		768
		769	DBG(("%s: setup id=%d\n", __FUNCTION__, id));
		770
		771	if (render->ve_id == id)
		772	return;
		773	render->ve_id = id;
		774
		775	/* The VUE layout
		776	* dword 0-3: pad (0.0, 0.0, 0.0. 0.0)
		777	* dword 4-7: position (x, y, 1.0, 1.0),
		778	* dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0)
		779	* dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0)
		780	*
		781	* dword 4-15 are fetched from vertex buffer
		782	*/
		783	has_mask = (id >> 2) != 0;
		784	OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS \|
		785	((2 * (3 + has_mask)) + 1 - 2));
		786
		787	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|
		788	GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT \|
		789
		790	OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT \|
		791	GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT \|
		792	GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT \|
		793	GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
		794
		795	/* x,y */
		796	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|
		797	GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT \|
		798
		799	OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT \|
		800	GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT \|
		801	GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT \|
		802	GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
		803
		804	/* u0, v0, w0 */
		805	DBG(("%s: first channel %d floats, offset=4b\n", __FUNCTION__, id & 3));
		806	dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
		807	switch (id & 3) {
		808	default:
		809	assert(0);
		810	case 0:
		811	src_format = GEN6_SURFACEFORMAT_R16G16_SSCALED;
		812	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		813	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		814	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		815	break;
		816	case 1:
		817	src_format = GEN6_SURFACEFORMAT_R32_FLOAT;
		818	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		819	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT;
		820	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		821	break;
		822	case 2:
		823	src_format = GEN6_SURFACEFORMAT_R32G32_FLOAT;
		824	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		825	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		826	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		827	break;
		828	case 3:
		829	src_format = GEN6_SURFACEFORMAT_R32G32B32_FLOAT;
		830	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		831	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		832	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_2_SHIFT;
		833	break;
		834	}
		835	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|
		836	src_format << VE0_FORMAT_SHIFT \|
		837	4 << VE0_OFFSET_SHIFT);
		838	OUT_BATCH(dw);
		839
		840	/* u1, v1, w1 */
		841	if (has_mask) {
		842	unsigned offset = 4 + ((id & 3) ?: 1) * sizeof(float);
		843	DBG(("%s: second channel %d floats, offset=%db\n", __FUNCTION__, id >> 2, offset));
		844	dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
		845	switch (id >> 2) {
		846	case 1:
		847	src_format = GEN6_SURFACEFORMAT_R32_FLOAT;
		848	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		849	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT;
		850	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		851	break;
		852	default:
		853	assert(0);
		854	case 2:
		855	src_format = GEN6_SURFACEFORMAT_R32G32_FLOAT;
		856	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		857	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		858	dw \|= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT;
		859	break;
		860	case 3:
		861	src_format = GEN6_SURFACEFORMAT_R32G32B32_FLOAT;
		862	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT;
		863	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT;
		864	dw \|= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_2_SHIFT;
		865	break;
		866	}
		867	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|
		868	src_format << VE0_FORMAT_SHIFT \|
		869	offset << VE0_OFFSET_SHIFT);
		870	OUT_BATCH(dw);
		871	}
		872	}
		873
		874	static void
		875	gen6_emit_flush(struct sna *sna)
		876	{
		877	OUT_BATCH(GEN6_PIPE_CONTROL \| (4 - 2));
		878	OUT_BATCH(GEN6_PIPE_CONTROL_WC_FLUSH \|
		879	GEN6_PIPE_CONTROL_TC_FLUSH \|
		880	GEN6_PIPE_CONTROL_CS_STALL);
		881	OUT_BATCH(0);
		882	OUT_BATCH(0);
		883	}
		884
		885	static void
		886	gen6_emit_state(struct sna *sna,
		887	const struct sna_composite_op *op,
		888	uint16_t wm_binding_table)
		889	{
		890	bool need_stall = wm_binding_table & 1;
		891
		892	if (gen6_emit_cc(sna, GEN6_BLEND(op->u.gen6.flags)))
		893	need_stall = false;
		894	gen6_emit_sampler(sna, GEN6_SAMPLER(op->u.gen6.flags));
		895	gen6_emit_sf(sna, GEN6_VERTEX(op->u.gen6.flags) >> 2);
		896	gen6_emit_wm(sna, GEN6_KERNEL(op->u.gen6.flags), GEN6_VERTEX(op->u.gen6.flags) >> 2);
		897	gen6_emit_vertex_elements(sna, op);
		898
		899	need_stall \|= gen6_emit_binding_table(sna, wm_binding_table & ~1);
		900	if (gen6_emit_drawing_rectangle(sna, op))
		901	need_stall = false;
		902	if (kgem_bo_is_dirty(op->src.bo) \|\| kgem_bo_is_dirty(op->mask.bo)) {
		903	gen6_emit_flush(sna);
		904	kgem_clear_dirty(&sna->kgem);
		905	if (op->dst.bo->exec)
		906	kgem_bo_mark_dirty(op->dst.bo);
		907	need_stall = false;
		908	}
		909	if (need_stall) {
		910	OUT_BATCH(GEN6_PIPE_CONTROL \| (4 - 2));
		911	OUT_BATCH(GEN6_PIPE_CONTROL_CS_STALL \|
		912	GEN6_PIPE_CONTROL_STALL_AT_SCOREBOARD);
		913	OUT_BATCH(0);
		914	OUT_BATCH(0);
		915	}
		916	sna->render_state.gen6.first_state_packet = false;
		917	}
		918
		919	static bool gen6_magic_ca_pass(struct sna *sna,
		920	const struct sna_composite_op *op)
		921	{
		922	struct gen6_render_state *state = &sna->render_state.gen6;
		923
		924	if (!op->need_magic_ca_pass)
		925	return false;
		926
		927	DBG(("%s: CA fixup (%d -> %d)\n", __FUNCTION__,
		928	sna->render.vertex_start, sna->render.vertex_index));
		929
		930	gen6_emit_flush(sna);
		931
		932	gen6_emit_cc(sna, gen6_get_blend(PictOpAdd, true, op->dst.format));
		933	gen6_emit_wm(sna,
		934	gen6_choose_composite_kernel(PictOpAdd,
		935	true, true,
		936	op->is_affine),
		937	true);
		938
		939	OUT_BATCH(GEN6_3DPRIMITIVE \|
		940	GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL \|
		941	_3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT \|
		942
		943	4);
		944	OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
		945	OUT_BATCH(sna->render.vertex_start);
		946	OUT_BATCH(1); /* single instance */
		947	OUT_BATCH(0); /* start instance location */
		948	OUT_BATCH(0); /* index buffer offset, ignored */
		949
		950	state->last_primitive = sna->kgem.nbatch;
		951	return true;
		952	}
		953
		954	typedef struct gen6_surface_state_padded {
		955	struct gen6_surface_state state;
		956	char pad[32 - sizeof(struct gen6_surface_state)];
		957	} gen6_surface_state_padded;
		958
		959	static void null_create(struct sna_static_stream *stream)
		960	{
		961	/* A bunch of zeros useful for legacy border color and depth-stencil */
		962	sna_static_stream_map(stream, 64, 64);
		963	}
		964
		965	static void scratch_create(struct sna_static_stream *stream)
		966	{
		967	/* 64 bytes of scratch space for random writes, such as
		968	* the pipe-control w/a.
		969	*/
		970	sna_static_stream_map(stream, 64, 64);
		971	}
		972
		973	static void
		974	sampler_state_init(struct gen6_sampler_state *sampler_state,
		975	sampler_filter_t filter,
		976	sampler_extend_t extend)
		977	{
		978	sampler_state->ss0.lod_preclamp = 1; /* GL mode */
		979
		980	/* We use the legacy mode to get the semantics specified by
		981	* the Render extension. */
		982	sampler_state->ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY;
		983
		984	switch (filter) {
		985	default:
		986	case SAMPLER_FILTER_NEAREST:
		987	sampler_state->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
		988	sampler_state->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
		989	break;
		990	case SAMPLER_FILTER_BILINEAR:
		991	sampler_state->ss0.min_filter = GEN6_MAPFILTER_LINEAR;
		992	sampler_state->ss0.mag_filter = GEN6_MAPFILTER_LINEAR;
		993	break;
		994	}
		995
		996	switch (extend) {
		997	default:
		998	case SAMPLER_EXTEND_NONE:
		999	sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
		1000	sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
		1001	sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
		1002	break;
		1003	case SAMPLER_EXTEND_REPEAT:
		1004	sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
		1005	sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
		1006	sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
		1007	break;
		1008	case SAMPLER_EXTEND_PAD:
		1009	sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
		1010	sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
		1011	sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
		1012	break;
		1013	case SAMPLER_EXTEND_REFLECT:
		1014	sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
		1015	sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
		1016	sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
		1017	break;
		1018	}
		1019	}
		1020
		1021	static void
		1022	sampler_copy_init(struct gen6_sampler_state *ss)
		1023	{
		1024	sampler_state_init(ss, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
		1025	ss->ss3.non_normalized_coord = 1;
		1026
		1027	sampler_state_init(ss+1, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
		1028	}
		1029
		1030	static void
		1031	sampler_fill_init(struct gen6_sampler_state *ss)
		1032	{
		1033	sampler_state_init(ss, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_REPEAT);
		1034	ss->ss3.non_normalized_coord = 1;
		1035
		1036	sampler_state_init(ss+1, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
		1037	}
		1038
		1039	static uint32_t
		1040	gen6_tiling_bits(uint32_t tiling)
		1041	{
		1042	return 0;
		1043	/*
		1044	switch (tiling) {
		1045	default: assert(0);
		1046	case I915_TILING_NONE: return 0;
		1047	case I915_TILING_X: return GEN6_SURFACE_TILED;
		1048	case I915_TILING_Y: return GEN6_SURFACE_TILED \| GEN6_SURFACE_TILED_Y;
		1049	}
		1050	*/
		1051	}
		1052
		1053	/**
		1054	* Sets up the common fields for a surface state buffer for the given
		1055	* picture in the given surface state buffer.
		1056	*/
		1057	static int
		1058	gen6_bind_bo(struct sna *sna,
		1059	struct kgem_bo *bo,
		1060	uint32_t width,
		1061	uint32_t height,
		1062	uint32_t format,
		1063	bool is_dst)
		1064	{
		1065	uint32_t *ss;
		1066	uint32_t domains;
		1067	uint16_t offset;
		1068	uint32_t is_scanout = is_dst && bo->scanout;
		1069
		1070	/* After the first bind, we manage the cache domains within the batch */
		1071	offset = kgem_bo_get_binding(bo, format \| is_scanout << 31);
		1072	if (offset) {
		1073	DBG(("[%x] bo(handle=%d), format=%d, reuse %s binding\n",
		1074	offset, bo->handle, format,
		1075	is_dst ? "render" : "sampler"));
		1076	if (is_dst)
		1077	kgem_bo_mark_dirty(bo);
		1078	return offset * sizeof(uint32_t);
		1079	}
		1080
		1081	offset = sna->kgem.surface -=
		1082	sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		1083	ss = sna->kgem.batch + offset;
		1084	ss[0] = (GEN6_SURFACE_2D << GEN6_SURFACE_TYPE_SHIFT \|
		1085	GEN6_SURFACE_BLEND_ENABLED \|
		1086	format << GEN6_SURFACE_FORMAT_SHIFT);
		1087	if (is_dst)
		1088	domains = I915_GEM_DOMAIN_RENDER << 16 \|I915_GEM_DOMAIN_RENDER;
		1089	else
		1090	domains = I915_GEM_DOMAIN_SAMPLER << 16;
		1091	ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
		1092	ss[2] = ((width - 1) << GEN6_SURFACE_WIDTH_SHIFT \|
		1093	(height - 1) << GEN6_SURFACE_HEIGHT_SHIFT);
		1094	assert(bo->pitch <= (1 << 18));
		1095	ss[3] = (gen6_tiling_bits(bo->tiling) \|
		1096	(bo->pitch - 1) << GEN6_SURFACE_PITCH_SHIFT);
		1097	ss[4] = 0;
		1098	ss[5] = is_scanout ? 0 : 3 << 16;
		1099
		1100	kgem_bo_set_binding(bo, format \| is_scanout << 31, offset);
		1101
		1102	DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
		1103	offset, bo->handle, ss[1],
		1104	format, width, height, bo->pitch, bo->tiling,
		1105	domains & 0xffff ? "render" : "sampler"));
		1106
		1107	return offset * sizeof(uint32_t);
		1108	}
		1109
		1110	static void gen6_emit_vertex_buffer(struct sna *sna,
		1111	const struct sna_composite_op *op)
		1112	{
		1113	int id = GEN6_VERTEX(op->u.gen6.flags);
		1114
		1115	OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS \| 3);
		1116	OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT \| VB0_VERTEXDATA \|
		1117	4*op->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT);
		1118	sna->render.vertex_reloc[sna->render.nvertex_reloc++] = sna->kgem.nbatch;
		1119	OUT_BATCH(0);
		1120	OUT_BATCH(~0); /* max address: disabled */
		1121	OUT_BATCH(0);
		1122
		1123	sna->render.vb_id \|= 1 << id;
		1124	}
		1125
		1126	static void gen6_emit_primitive(struct sna *sna)
		1127	{
		1128	if (sna->kgem.nbatch == sna->render_state.gen6.last_primitive) {
		1129	DBG(("%s: continuing previous primitive, start=%d, index=%d\n",
		1130	__FUNCTION__,
		1131	sna->render.vertex_start,
		1132	sna->render.vertex_index));
		1133	sna->render.vertex_offset = sna->kgem.nbatch - 5;
		1134	return;
		1135	}
		1136
		1137	OUT_BATCH(GEN6_3DPRIMITIVE \|
		1138	GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL \|
		1139	_3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT \|
		1140
		1141	4);
		1142	sna->render.vertex_offset = sna->kgem.nbatch;
		1143	OUT_BATCH(0); /* vertex count, to be filled in later */
		1144	OUT_BATCH(sna->render.vertex_index);
		1145	OUT_BATCH(1); /* single instance */
		1146	OUT_BATCH(0); /* start instance location */
		1147	OUT_BATCH(0); /* index buffer offset, ignored */
		1148	sna->render.vertex_start = sna->render.vertex_index;
		1149	DBG(("%s: started new primitive: index=%d\n",
		1150	__FUNCTION__, sna->render.vertex_start));
		1151
		1152	sna->render_state.gen6.last_primitive = sna->kgem.nbatch;
		1153	}
		1154
		1155	static bool gen6_rectangle_begin(struct sna *sna,
		1156	const struct sna_composite_op *op)
		1157	{
		1158	int id = 1 << GEN6_VERTEX(op->u.gen6.flags);
		1159	int ndwords;
		1160
3263	Serge	1161	if (sna_vertex_wait__locked(&sna->render) && sna->render.vertex_offset)
		1162	return true;
		1163
3254	Serge	1164	ndwords = op->need_magic_ca_pass ? 60 : 6;
		1165	if ((sna->render.vb_id & id) == 0)
		1166	ndwords += 5;
		1167	if (!kgem_check_batch(&sna->kgem, ndwords))
		1168	return false;
		1169
		1170	if ((sna->render.vb_id & id) == 0)
		1171	gen6_emit_vertex_buffer(sna, op);
		1172
		1173	gen6_emit_primitive(sna);
		1174	return true;
		1175	}
		1176
		1177	static int gen6_get_rectangles__flush(struct sna *sna,
		1178	const struct sna_composite_op *op)
		1179	{
3263	Serge	1180	/* Preventing discarding new vbo after lock contention */
		1181	if (sna_vertex_wait__locked(&sna->render)) {
		1182	int rem = vertex_space(sna);
		1183	if (rem > op->floats_per_rect)
		1184	return rem;
		1185	}
3254	Serge	1186
		1187	if (!kgem_check_batch(&sna->kgem, op->need_magic_ca_pass ? 65 : 5))
		1188	return 0;
		1189	if (!kgem_check_reloc_and_exec(&sna->kgem, 2))
		1190	return 0;
		1191
		1192	if (sna->render.vertex_offset) {
		1193	gen4_vertex_flush(sna);
		1194	if (gen6_magic_ca_pass(sna, op)) {
		1195	gen6_emit_flush(sna);
		1196	gen6_emit_cc(sna, GEN6_BLEND(op->u.gen6.flags));
		1197	gen6_emit_wm(sna,
		1198	GEN6_KERNEL(op->u.gen6.flags),
		1199	GEN6_VERTEX(op->u.gen6.flags) >> 2);
		1200	}
		1201	}
		1202
		1203	return gen4_vertex_finish(sna);
		1204	}
		1205
		1206	inline static int gen6_get_rectangles(struct sna *sna,
		1207	const struct sna_composite_op *op,
		1208	int want,
		1209	void (emit_state)(struct sna , const struct sna_composite_op *op))
		1210	{
		1211	int rem;
		1212
		1213	start:
		1214	rem = vertex_space(sna);
		1215	if (unlikely(rem < op->floats_per_rect)) {
		1216	DBG(("flushing vbo for %s: %d < %d\n",
		1217	__FUNCTION__, rem, op->floats_per_rect));
		1218	rem = gen6_get_rectangles__flush(sna, op);
		1219	if (unlikely(rem == 0))
		1220	goto flush;
		1221	}
		1222
		1223	if (unlikely(sna->render.vertex_offset == 0 &&
		1224	!gen6_rectangle_begin(sna, op)))
		1225	goto flush;
		1226
		1227	if (want > 1 && want * op->floats_per_rect > rem)
		1228	want = rem / op->floats_per_rect;
		1229
		1230	assert(want > 0);
		1231	sna->render.vertex_index += 3*want;
		1232	return want;
		1233
		1234	flush:
		1235	if (sna->render.vertex_offset) {
		1236	gen4_vertex_flush(sna);
		1237	gen6_magic_ca_pass(sna, op);
		1238	}
3263	Serge	1239	sna_vertex_wait__locked(&sna->render);
3254	Serge	1240	_kgem_submit(&sna->kgem);
		1241	emit_state(sna, op);
		1242	goto start;
		1243	}
		1244
		1245	inline static uint32_t gen6_composite_get_binding_table(struct sna sna,
		1246	uint16_t *offset)
		1247	{
		1248	uint32_t *table;
		1249
		1250	sna->kgem.surface -=
		1251	sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		1252	/* Clear all surplus entries to zero in case of prefetch */
		1253	table = memset(sna->kgem.batch + sna->kgem.surface,
		1254	0, sizeof(struct gen6_surface_state_padded));
		1255
		1256	DBG(("%s(%x)\n", __FUNCTION__, 4*sna->kgem.surface));
		1257
		1258	*offset = sna->kgem.surface;
		1259	return table;
		1260	}
		1261
		1262	static bool
		1263	gen6_get_batch(struct sna sna, const struct sna_composite_op op)
		1264	{
		1265	kgem_set_mode(&sna->kgem, KGEM_RENDER, op->dst.bo);
		1266
		1267	if (!kgem_check_batch_with_surfaces(&sna->kgem, 150, 4)) {
		1268	DBG(("%s: flushing batch: %d < %d+%d\n",
		1269	__FUNCTION__, sna->kgem.surface - sna->kgem.nbatch,
		1270	150, 4*8));
		1271	kgem_submit(&sna->kgem);
		1272	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		1273	}
		1274
		1275	if (sna->render_state.gen6.needs_invariant)
		1276	gen6_emit_invariant(sna);
		1277
		1278	return kgem_bo_is_dirty(op->dst.bo);
		1279	}
		1280
		1281	static void gen6_emit_composite_state(struct sna *sna,
		1282	const struct sna_composite_op *op)
		1283	{
		1284	uint32_t *binding_table;
		1285	uint16_t offset;
		1286	bool dirty;
		1287
		1288	dirty = gen6_get_batch(sna, op);
		1289
		1290	binding_table = gen6_composite_get_binding_table(sna, &offset);
		1291
		1292	binding_table[0] =
		1293	gen6_bind_bo(sna,
		1294	op->dst.bo, op->dst.width, op->dst.height,
		1295	gen6_get_dest_format(op->dst.format),
		1296	true);
		1297	binding_table[1] =
		1298	gen6_bind_bo(sna,
		1299	op->src.bo, op->src.width, op->src.height,
		1300	op->src.card_format,
		1301	false);
		1302	if (op->mask.bo) {
		1303	binding_table[2] =
		1304	gen6_bind_bo(sna,
		1305	op->mask.bo,
		1306	op->mask.width,
		1307	op->mask.height,
		1308	op->mask.card_format,
		1309	false);
		1310	}
		1311
		1312	if (sna->kgem.surface == offset &&
		1313	(uint64_t )(sna->kgem.batch + sna->render_state.gen6.surface_table) == (uint64_t)binding_table &&
		1314	(op->mask.bo == NULL \|\|
		1315	sna->kgem.batch[sna->render_state.gen6.surface_table+2] == binding_table[2])) {
		1316	sna->kgem.surface += sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		1317	offset = sna->render_state.gen6.surface_table;
		1318	}
		1319
		1320	gen6_emit_state(sna, op, offset \| dirty);
		1321	}
		1322
		1323	static void
		1324	gen6_align_vertex(struct sna sna, const struct sna_composite_op op)
		1325	{
		1326	assert (sna->render.vertex_offset == 0);
		1327	if (op->floats_per_vertex != sna->render_state.gen6.floats_per_vertex) {
		1328	if (sna->render.vertex_size - sna->render.vertex_used < 2*op->floats_per_rect)
		1329	gen4_vertex_finish(sna);
		1330
		1331	DBG(("aligning vertex: was %d, now %d floats per vertex, %d->%d\n",
		1332	sna->render_state.gen6.floats_per_vertex,
		1333	op->floats_per_vertex,
		1334	sna->render.vertex_index,
		1335	(sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex));
		1336	sna->render.vertex_index = (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex;
		1337	sna->render.vertex_used = sna->render.vertex_index * op->floats_per_vertex;
		1338	sna->render_state.gen6.floats_per_vertex = op->floats_per_vertex;
		1339	}
		1340	assert((sna->render.vertex_used % op->floats_per_vertex) == 0);
		1341	}
		1342
		1343
		1344	fastcall static void
		1345	gen6_render_composite_blt(struct sna *sna,
		1346	const struct sna_composite_op *op,
		1347	const struct sna_composite_rectangles *r)
		1348	{
		1349	gen6_get_rectangles(sna, op, 1, gen6_emit_composite_state);
		1350	op->prim_emit(sna, op, r);
		1351	}
		1352
3278	Serge	1353	#if 0
		1354
3254	Serge	1355	fastcall static void
		1356	gen6_render_composite_box(struct sna *sna,
		1357	const struct sna_composite_op *op,
		1358	const BoxRec *box)
		1359	{
		1360	struct sna_composite_rectangles r;
		1361
		1362	gen6_get_rectangles(sna, op, 1, gen6_emit_composite_state);
		1363
		1364	DBG((" %s: (%d, %d), (%d, %d)\n",
		1365	__FUNCTION__,
		1366	box->x1, box->y1, box->x2, box->y2));
		1367
		1368	r.dst.x = box->x1;
		1369	r.dst.y = box->y1;
		1370	r.width = box->x2 - box->x1;
		1371	r.height = box->y2 - box->y1;
		1372	r.src = r.mask = r.dst;
		1373
		1374	op->prim_emit(sna, op, &r);
		1375	}
		1376
		1377	static void
		1378	gen6_render_composite_boxes__blt(struct sna *sna,
		1379	const struct sna_composite_op *op,
		1380	const BoxRec *box, int nbox)
		1381	{
		1382	DBG(("composite_boxes(%d)\n", nbox));
		1383
		1384	do {
		1385	int nbox_this_time;
		1386
		1387	nbox_this_time = gen6_get_rectangles(sna, op, nbox,
		1388	gen6_emit_composite_state);
		1389	nbox -= nbox_this_time;
		1390
		1391	do {
		1392	struct sna_composite_rectangles r;
		1393
		1394	DBG((" %s: (%d, %d), (%d, %d)\n",
		1395	__FUNCTION__,
		1396	box->x1, box->y1, box->x2, box->y2));
		1397
		1398	r.dst.x = box->x1;
		1399	r.dst.y = box->y1;
		1400	r.width = box->x2 - box->x1;
		1401	r.height = box->y2 - box->y1;
		1402	r.src = r.mask = r.dst;
		1403
		1404	op->prim_emit(sna, op, &r);
		1405	box++;
		1406	} while (--nbox_this_time);
		1407	} while (nbox);
		1408	}
		1409
		1410	static void
		1411	gen6_render_composite_boxes(struct sna *sna,
		1412	const struct sna_composite_op *op,
		1413	const BoxRec *box, int nbox)
		1414	{
		1415	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
		1416
		1417	do {
		1418	int nbox_this_time;
		1419	float *v;
		1420
		1421	nbox_this_time = gen6_get_rectangles(sna, op, nbox,
		1422	gen6_emit_composite_state);
		1423	assert(nbox_this_time);
		1424	nbox -= nbox_this_time;
		1425
		1426	v = sna->render.vertices + sna->render.vertex_used;
		1427	sna->render.vertex_used += nbox_this_time * op->floats_per_rect;
		1428
		1429	op->emit_boxes(op, box, nbox_this_time, v);
		1430	box += nbox_this_time;
		1431	} while (nbox);
		1432	}
		1433
		1434	static void
		1435	gen6_render_composite_boxes__thread(struct sna *sna,
		1436	const struct sna_composite_op *op,
		1437	const BoxRec *box, int nbox)
		1438	{
		1439	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
		1440
		1441	sna_vertex_lock(&sna->render);
		1442	do {
		1443	int nbox_this_time;
		1444	float *v;
		1445
		1446	nbox_this_time = gen6_get_rectangles(sna, op, nbox,
		1447	gen6_emit_composite_state);
		1448	assert(nbox_this_time);
		1449	nbox -= nbox_this_time;
		1450
		1451	v = sna->render.vertices + sna->render.vertex_used;
		1452	sna->render.vertex_used += nbox_this_time * op->floats_per_rect;
		1453
		1454	sna_vertex_acquire__locked(&sna->render);
		1455	sna_vertex_unlock(&sna->render);
		1456
		1457	op->emit_boxes(op, box, nbox_this_time, v);
		1458	box += nbox_this_time;
		1459
		1460	sna_vertex_lock(&sna->render);
		1461	sna_vertex_release__locked(&sna->render);
		1462	} while (nbox);
		1463	sna_vertex_unlock(&sna->render);
		1464	}
		1465
		1466	#endif
		1467
		1468	#ifndef MAX
		1469	#define MAX(a,b) ((a) > (b) ? (a) : (b))
		1470	#endif
		1471
		1472	static uint32_t
		1473	gen6_composite_create_blend_state(struct sna_static_stream *stream)
		1474	{
		1475	char base, ptr;
		1476	int src, dst;
		1477
		1478	base = sna_static_stream_map(stream,
		1479	GEN6_BLENDFACTOR_COUNT * GEN6_BLENDFACTOR_COUNT * GEN6_BLEND_STATE_PADDED_SIZE,
		1480	64);
		1481
		1482	ptr = base;
		1483	for (src = 0; src < GEN6_BLENDFACTOR_COUNT; src++) {
		1484	for (dst= 0; dst < GEN6_BLENDFACTOR_COUNT; dst++) {
		1485	struct gen6_blend_state *blend =
		1486	(struct gen6_blend_state *)ptr;
		1487
		1488	blend->blend0.dest_blend_factor = dst;
		1489	blend->blend0.source_blend_factor = src;
		1490	blend->blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
		1491	blend->blend0.blend_enable =
		1492	!(dst == GEN6_BLENDFACTOR_ZERO && src == GEN6_BLENDFACTOR_ONE);
		1493
		1494	blend->blend1.post_blend_clamp_enable = 1;
		1495	blend->blend1.pre_blend_clamp_enable = 1;
		1496
		1497	ptr += GEN6_BLEND_STATE_PADDED_SIZE;
		1498	}
		1499	}
		1500
		1501	return sna_static_stream_offsetof(stream, base);
		1502	}
		1503
		1504	#if 0
		1505
		1506	static uint32_t gen6_bind_video_source(struct sna *sna,
		1507	struct kgem_bo *src_bo,
		1508	uint32_t src_offset,
		1509	int src_width,
		1510	int src_height,
		1511	int src_pitch,
		1512	uint32_t src_surf_format)
		1513	{
		1514	struct gen6_surface_state *ss;
		1515
		1516	sna->kgem.surface -= sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		1517
		1518	ss = memset(sna->kgem.batch + sna->kgem.surface, 0, sizeof(*ss));
		1519	ss->ss0.surface_type = GEN6_SURFACE_2D;
		1520	ss->ss0.surface_format = src_surf_format;
		1521
		1522	ss->ss1.base_addr =
		1523	kgem_add_reloc(&sna->kgem,
		1524	sna->kgem.surface + 1,
		1525	src_bo,
		1526	I915_GEM_DOMAIN_SAMPLER << 16,
		1527	src_offset);
		1528
		1529	ss->ss2.width = src_width - 1;
		1530	ss->ss2.height = src_height - 1;
		1531	ss->ss3.pitch = src_pitch - 1;
		1532
		1533	return sna->kgem.surface * sizeof(uint32_t);
		1534	}
		1535
		1536	static void gen6_emit_video_state(struct sna *sna,
		1537	const struct sna_composite_op *op)
		1538	{
		1539	struct sna_video_frame *frame = op->priv;
		1540	uint32_t src_surf_format;
		1541	uint32_t src_surf_base[6];
		1542	int src_width[6];
		1543	int src_height[6];
		1544	int src_pitch[6];
		1545	uint32_t *binding_table;
		1546	uint16_t offset;
		1547	bool dirty;
		1548	int n_src, n;
		1549
		1550	dirty = gen6_get_batch(sna, op);
		1551
		1552	src_surf_base[0] = 0;
		1553	src_surf_base[1] = 0;
		1554	src_surf_base[2] = frame->VBufOffset;
		1555	src_surf_base[3] = frame->VBufOffset;
		1556	src_surf_base[4] = frame->UBufOffset;
		1557	src_surf_base[5] = frame->UBufOffset;
		1558
		1559	if (is_planar_fourcc(frame->id)) {
		1560	src_surf_format = GEN6_SURFACEFORMAT_R8_UNORM;
		1561	src_width[1] = src_width[0] = frame->width;
		1562	src_height[1] = src_height[0] = frame->height;
		1563	src_pitch[1] = src_pitch[0] = frame->pitch[1];
		1564	src_width[4] = src_width[5] = src_width[2] = src_width[3] =
		1565	frame->width / 2;
		1566	src_height[4] = src_height[5] = src_height[2] = src_height[3] =
		1567	frame->height / 2;
		1568	src_pitch[4] = src_pitch[5] = src_pitch[2] = src_pitch[3] =
		1569	frame->pitch[0];
		1570	n_src = 6;
		1571	} else {
		1572	if (frame->id == FOURCC_UYVY)
		1573	src_surf_format = GEN6_SURFACEFORMAT_YCRCB_SWAPY;
		1574	else
		1575	src_surf_format = GEN6_SURFACEFORMAT_YCRCB_NORMAL;
		1576
		1577	src_width[0] = frame->width;
		1578	src_height[0] = frame->height;
		1579	src_pitch[0] = frame->pitch[0];
		1580	n_src = 1;
		1581	}
		1582
		1583	binding_table = gen6_composite_get_binding_table(sna, &offset);
		1584
		1585	binding_table[0] =
		1586	gen6_bind_bo(sna,
		1587	op->dst.bo, op->dst.width, op->dst.height,
		1588	gen6_get_dest_format(op->dst.format),
		1589	true);
		1590	for (n = 0; n < n_src; n++) {
		1591	binding_table[1+n] =
		1592	gen6_bind_video_source(sna,
		1593	frame->bo,
		1594	src_surf_base[n],
		1595	src_width[n],
		1596	src_height[n],
		1597	src_pitch[n],
		1598	src_surf_format);
		1599	}
		1600
		1601	gen6_emit_state(sna, op, offset \| dirty);
		1602	}
		1603
		1604	static bool
		1605	gen6_render_video(struct sna *sna,
		1606	struct sna_video *video,
		1607	struct sna_video_frame *frame,
		1608	RegionPtr dstRegion,
		1609	short src_w, short src_h,
		1610	short drw_w, short drw_h,
		1611	short dx, short dy,
		1612	PixmapPtr pixmap)
		1613	{
		1614	struct sna_composite_op tmp;
		1615	int nbox, pix_xoff, pix_yoff;
		1616	float src_scale_x, src_scale_y;
		1617	struct sna_pixmap *priv;
		1618	unsigned filter;
		1619	BoxPtr box;
		1620
		1621	DBG(("%s: src=(%d, %d), dst=(%d, %d), %dx[(%d, %d), (%d, %d)...]\n",
		1622	__FUNCTION__, src_w, src_h, drw_w, drw_h,
		1623	REGION_NUM_RECTS(dstRegion),
		1624	REGION_EXTENTS(NULL, dstRegion)->x1,
		1625	REGION_EXTENTS(NULL, dstRegion)->y1,
		1626	REGION_EXTENTS(NULL, dstRegion)->x2,
		1627	REGION_EXTENTS(NULL, dstRegion)->y2));
		1628
		1629	priv = sna_pixmap_force_to_gpu(pixmap, MOVE_READ \| MOVE_WRITE);
		1630	if (priv == NULL)
		1631	return false;
		1632
		1633	memset(&tmp, 0, sizeof(tmp));
		1634
		1635	tmp.dst.pixmap = pixmap;
		1636	tmp.dst.width = pixmap->drawable.width;
		1637	tmp.dst.height = pixmap->drawable.height;
		1638	tmp.dst.format = sna_render_format_for_depth(pixmap->drawable.depth);
		1639	tmp.dst.bo = priv->gpu_bo;
		1640
		1641	tmp.src.bo = frame->bo;
		1642	tmp.mask.bo = NULL;
		1643
		1644	tmp.floats_per_vertex = 3;
		1645	tmp.floats_per_rect = 9;
		1646
		1647	if (src_w == drw_w && src_h == drw_h)
		1648	filter = SAMPLER_FILTER_NEAREST;
		1649	else
		1650	filter = SAMPLER_FILTER_BILINEAR;
		1651
		1652	tmp.u.gen6.flags =
		1653	GEN6_SET_FLAGS(SAMPLER_OFFSET(filter, SAMPLER_EXTEND_PAD,
		1654	SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE),
		1655	NO_BLEND,
		1656	is_planar_fourcc(frame->id) ?
		1657	GEN6_WM_KERNEL_VIDEO_PLANAR :
		1658	GEN6_WM_KERNEL_VIDEO_PACKED,
		1659	2);
		1660	tmp.priv = frame;
		1661
		1662	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp.dst.bo);
		1663	if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL)) {
		1664	kgem_submit(&sna->kgem);
		1665	assert(kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL));
		1666	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		1667	}
		1668
3258	Serge	1669	gen6_emit_video_state(sna, &tmp);
3254	Serge	1670	gen6_align_vertex(sna, &tmp);
		1671
		1672	/* Set up the offset for translating from the given region (in screen
		1673	* coordinates) to the backing pixmap.
		1674	*/
		1675	#ifdef COMPOSITE
		1676	pix_xoff = -pixmap->screen_x + pixmap->drawable.x;
		1677	pix_yoff = -pixmap->screen_y + pixmap->drawable.y;
		1678	#else
		1679	pix_xoff = 0;
		1680	pix_yoff = 0;
		1681	#endif
		1682
		1683	/* Use normalized texture coordinates */
		1684	src_scale_x = ((float)src_w / frame->width) / (float)drw_w;
		1685	src_scale_y = ((float)src_h / frame->height) / (float)drw_h;
		1686
		1687	box = REGION_RECTS(dstRegion);
		1688	nbox = REGION_NUM_RECTS(dstRegion);
		1689	while (nbox--) {
		1690	BoxRec r;
		1691
		1692	r.x1 = box->x1 + pix_xoff;
		1693	r.x2 = box->x2 + pix_xoff;
		1694	r.y1 = box->y1 + pix_yoff;
		1695	r.y2 = box->y2 + pix_yoff;
		1696
		1697	gen6_get_rectangles(sna, &tmp, 1, gen6_emit_video_state);
		1698
		1699	OUT_VERTEX(r.x2, r.y2);
		1700	OUT_VERTEX_F((box->x2 - dx) * src_scale_x);
		1701	OUT_VERTEX_F((box->y2 - dy) * src_scale_y);
		1702
		1703	OUT_VERTEX(r.x1, r.y2);
		1704	OUT_VERTEX_F((box->x1 - dx) * src_scale_x);
		1705	OUT_VERTEX_F((box->y2 - dy) * src_scale_y);
		1706
		1707	OUT_VERTEX(r.x1, r.y1);
		1708	OUT_VERTEX_F((box->x1 - dx) * src_scale_x);
		1709	OUT_VERTEX_F((box->y1 - dy) * src_scale_y);
		1710
		1711	if (!DAMAGE_IS_ALL(priv->gpu_damage)) {
		1712	sna_damage_add_box(&priv->gpu_damage, &r);
		1713	sna_damage_subtract_box(&priv->cpu_damage, &r);
		1714	}
		1715	box++;
		1716	}
		1717	priv->clear = false;
		1718
		1719	gen4_vertex_flush(sna);
		1720	return true;
		1721	}
		1722
		1723	static int
		1724	gen6_composite_picture(struct sna *sna,
		1725	PicturePtr picture,
		1726	struct sna_composite_channel *channel,
		1727	int x, int y,
		1728	int w, int h,
		1729	int dst_x, int dst_y,
		1730	bool precise)
		1731	{
		1732	PixmapPtr pixmap;
		1733	uint32_t color;
		1734	int16_t dx, dy;
		1735
		1736	DBG(("%s: (%d, %d)x(%d, %d), dst=(%d, %d)\n",
		1737	__FUNCTION__, x, y, w, h, dst_x, dst_y));
		1738
		1739	channel->is_solid = false;
		1740	channel->card_format = -1;
		1741
		1742	if (sna_picture_is_solid(picture, &color))
		1743	return gen4_channel_init_solid(sna, channel, color);
		1744
		1745	if (picture->pDrawable == NULL) {
		1746	int ret;
		1747
		1748	if (picture->pSourcePict->type == SourcePictTypeLinear)
		1749	return gen4_channel_init_linear(sna, picture, channel,
		1750	x, y,
		1751	w, h,
		1752	dst_x, dst_y);
		1753
		1754	DBG(("%s -- fixup, gradient\n", __FUNCTION__));
		1755	ret = -1;
		1756	if (!precise)
		1757	ret = sna_render_picture_approximate_gradient(sna, picture, channel,
		1758	x, y, w, h, dst_x, dst_y);
		1759	if (ret == -1)
		1760	ret = sna_render_picture_fixup(sna, picture, channel,
		1761	x, y, w, h, dst_x, dst_y);
		1762	return ret;
		1763	}
		1764
		1765	if (picture->alphaMap) {
		1766	DBG(("%s -- fixup, alphamap\n", __FUNCTION__));
		1767	return sna_render_picture_fixup(sna, picture, channel,
		1768	x, y, w, h, dst_x, dst_y);
		1769	}
		1770
		1771	if (!gen6_check_repeat(picture))
		1772	return sna_render_picture_fixup(sna, picture, channel,
		1773	x, y, w, h, dst_x, dst_y);
		1774
		1775	if (!gen6_check_filter(picture))
		1776	return sna_render_picture_fixup(sna, picture, channel,
		1777	x, y, w, h, dst_x, dst_y);
		1778
		1779	channel->repeat = picture->repeat ? picture->repeatType : RepeatNone;
		1780	channel->filter = picture->filter;
		1781
		1782	pixmap = get_drawable_pixmap(picture->pDrawable);
		1783	get_drawable_deltas(picture->pDrawable, pixmap, &dx, &dy);
		1784
		1785	x += dx + picture->pDrawable->x;
		1786	y += dy + picture->pDrawable->y;
		1787
		1788	channel->is_affine = sna_transform_is_affine(picture->transform);
		1789	if (sna_transform_is_integer_translation(picture->transform, &dx, &dy)) {
		1790	DBG(("%s: integer translation (%d, %d), removing\n",
		1791	__FUNCTION__, dx, dy));
		1792	x += dx;
		1793	y += dy;
		1794	channel->transform = NULL;
		1795	channel->filter = PictFilterNearest;
		1796	} else
		1797	channel->transform = picture->transform;
		1798
		1799	channel->pict_format = picture->format;
		1800	channel->card_format = gen6_get_card_format(picture->format);
		1801	if (channel->card_format == (unsigned)-1)
		1802	return sna_render_picture_convert(sna, picture, channel, pixmap,
		1803	x, y, w, h, dst_x, dst_y,
		1804	false);
		1805
		1806	if (too_large(pixmap->drawable.width, pixmap->drawable.height)) {
		1807	DBG(("%s: extracting from pixmap %dx%d\n", __FUNCTION__,
		1808	pixmap->drawable.width, pixmap->drawable.height));
		1809	return sna_render_picture_extract(sna, picture, channel,
		1810	x, y, w, h, dst_x, dst_y);
		1811	}
		1812
		1813	return sna_render_pixmap_bo(sna, channel, pixmap,
		1814	x, y, w, h, dst_x, dst_y);
		1815	}
		1816
		1817	inline static void gen6_composite_channel_convert(struct sna_composite_channel *channel)
		1818	{
		1819	channel->repeat = gen6_repeat(channel->repeat);
		1820	channel->filter = gen6_filter(channel->filter);
		1821	if (channel->card_format == (unsigned)-1)
		1822	channel->card_format = gen6_get_card_format(channel->pict_format);
		1823	assert(channel->card_format != (unsigned)-1);
		1824	}
		1825
3278	Serge	1826	#endif
		1827
3254	Serge	1828	static void gen6_render_composite_done(struct sna *sna,
		1829	const struct sna_composite_op *op)
		1830	{
		1831	DBG(("%s\n", __FUNCTION__));
		1832
		1833	assert(!sna->render.active);
		1834	if (sna->render.vertex_offset) {
		1835	gen4_vertex_flush(sna);
		1836	gen6_magic_ca_pass(sna, op);
		1837	}
		1838
		1839
		1840	// sna_render_composite_redirect_done(sna, op);
		1841	}
		1842
3278	Serge	1843	#if 0
		1844
3254	Serge	1845	static bool
		1846	gen6_composite_set_target(struct sna *sna,
		1847	struct sna_composite_op *op,
		1848	PicturePtr dst,
		1849	int x, int y, int w, int h)
		1850	{
		1851	BoxRec box;
		1852
		1853	op->dst.pixmap = get_drawable_pixmap(dst->pDrawable);
		1854	op->dst.format = dst->format;
		1855	op->dst.width = op->dst.pixmap->drawable.width;
		1856	op->dst.height = op->dst.pixmap->drawable.height;
		1857
		1858	if (w && h) {
		1859	box.x1 = x;
		1860	box.y1 = y;
		1861	box.x2 = x + w;
		1862	box.y2 = y + h;
		1863	} else
		1864	sna_render_picture_extents(dst, &box);
		1865
3278	Serge	1866	// op->dst.bo = sna_drawable_use_bo (dst->pDrawable,
		1867	// PREFER_GPU \| FORCE_GPU \| RENDER_GPU,
		1868	// &box, &op->damage);
3254	Serge	1869	if (op->dst.bo == NULL)
		1870	return false;
		1871
		1872	get_drawable_deltas(dst->pDrawable, op->dst.pixmap,
		1873	&op->dst.x, &op->dst.y);
		1874
		1875	DBG(("%s: pixmap=%p, format=%08x, size=%dx%d, pitch=%d, delta=(%d,%d),damage=%p\n",
		1876	__FUNCTION__,
		1877	op->dst.pixmap, (int)op->dst.format,
		1878	op->dst.width, op->dst.height,
		1879	op->dst.bo->pitch,
		1880	op->dst.x, op->dst.y,
		1881	op->damage ? op->damage : (void )-1));
		1882
		1883	assert(op->dst.bo->proxy == NULL);
		1884
		1885	if (too_large(op->dst.width, op->dst.height) &&
		1886	!sna_render_composite_redirect(sna, op, x, y, w, h))
		1887	return false;
		1888
		1889	return true;
		1890	}
		1891
		1892
		1893	static bool
		1894	gen6_render_composite(struct sna *sna,
		1895	uint8_t op,
		1896	PicturePtr src,
		1897	PicturePtr mask,
		1898	PicturePtr dst,
		1899	int16_t src_x, int16_t src_y,
		1900	int16_t msk_x, int16_t msk_y,
		1901	int16_t dst_x, int16_t dst_y,
		1902	int16_t width, int16_t height,
		1903	struct sna_composite_op *tmp)
		1904	{
		1905	if (op >= ARRAY_SIZE(gen6_blend_op))
		1906	return false;
		1907
		1908	DBG(("%s: %dx%d, current mode=%d\n", __FUNCTION__,
		1909	width, height, sna->kgem.ring));
		1910
		1911	if (op == PictOpClear)
		1912	op = PictOpSrc;
		1913	tmp->op = op;
		1914	if (!gen6_composite_set_target(sna, tmp, dst,
		1915	dst_x, dst_y, width, height))
		1916	return false;
		1917
		1918	switch (gen6_composite_picture(sna, src, &tmp->src,
		1919	src_x, src_y,
		1920	width, height,
		1921	dst_x, dst_y,
		1922	dst->polyMode == PolyModePrecise)) {
		1923	case -1:
		1924	goto cleanup_dst;
		1925	case 0:
		1926	if (!gen4_channel_init_solid(sna, &tmp->src, 0))
		1927	goto cleanup_dst;
		1928	/* fall through to fixup */
		1929	case 1:
		1930	/* Did we just switch rings to prepare the source? */
		1931	if (mask == NULL &&
		1932	prefer_blt_composite(sna, tmp) &&
		1933	sna_blt_composite__convert(sna,
		1934	dst_x, dst_y, width, height,
		1935	tmp))
		1936	return true;
		1937
		1938	gen6_composite_channel_convert(&tmp->src);
		1939	break;
		1940	}
		1941
		1942	tmp->is_affine = tmp->src.is_affine;
		1943	tmp->has_component_alpha = false;
		1944	tmp->need_magic_ca_pass = false;
		1945
		1946	tmp->mask.bo = NULL;
		1947	tmp->mask.filter = SAMPLER_FILTER_NEAREST;
		1948	tmp->mask.repeat = SAMPLER_EXTEND_NONE;
		1949
		1950	if (mask) {
		1951	if (mask->componentAlpha && PICT_FORMAT_RGB(mask->format)) {
		1952	tmp->has_component_alpha = true;
		1953
		1954	/* Check if it's component alpha that relies on a source alpha and on
		1955	* the source value. We can only get one of those into the single
		1956	* source value that we get to blend with.
		1957	*/
		1958	if (gen6_blend_op[op].src_alpha &&
		1959	(gen6_blend_op[op].src_blend != GEN6_BLENDFACTOR_ZERO)) {
		1960	if (op != PictOpOver)
		1961	goto cleanup_src;
		1962
		1963	tmp->need_magic_ca_pass = true;
		1964	tmp->op = PictOpOutReverse;
		1965	}
		1966	}
		1967
		1968	if (!reuse_source(sna,
		1969	src, &tmp->src, src_x, src_y,
		1970	mask, &tmp->mask, msk_x, msk_y)) {
		1971	switch (gen6_composite_picture(sna, mask, &tmp->mask,
		1972	msk_x, msk_y,
		1973	width, height,
		1974	dst_x, dst_y,
		1975	dst->polyMode == PolyModePrecise)) {
		1976	case -1:
		1977	goto cleanup_src;
		1978	case 0:
		1979	if (!gen4_channel_init_solid(sna, &tmp->mask, 0))
		1980	goto cleanup_src;
		1981	/* fall through to fixup */
		1982	case 1:
		1983	gen6_composite_channel_convert(&tmp->mask);
		1984	break;
		1985	}
		1986	}
		1987
		1988	tmp->is_affine &= tmp->mask.is_affine;
		1989	}
		1990
		1991	tmp->u.gen6.flags =
		1992	GEN6_SET_FLAGS(SAMPLER_OFFSET(tmp->src.filter,
		1993	tmp->src.repeat,
		1994	tmp->mask.filter,
		1995	tmp->mask.repeat),
		1996	gen6_get_blend(tmp->op,
		1997	tmp->has_component_alpha,
		1998	tmp->dst.format),
		1999	gen6_choose_composite_kernel(tmp->op,
		2000	tmp->mask.bo != NULL,
		2001	tmp->has_component_alpha,
		2002	tmp->is_affine),
		2003	gen4_choose_composite_emitter(tmp));
		2004
3278	Serge	2005	// tmp->blt = gen6_render_composite_blt;
		2006	// tmp->box = gen6_render_composite_box;
		2007	// tmp->boxes = gen6_render_composite_boxes__blt;
		2008	// if (tmp->emit_boxes) {
		2009	// tmp->boxes = gen6_render_composite_boxes;
		2010	// tmp->thread_boxes = gen6_render_composite_boxes__thread;
		2011	// }
3254	Serge	2012	tmp->done = gen6_render_composite_done;
		2013
3263	Serge	2014	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp->dst.bo);
		2015	if (!kgem_check_bo(&sna->kgem,
		2016	tmp->dst.bo, tmp->src.bo, tmp->mask.bo,
		2017	NULL)) {
		2018	kgem_submit(&sna->kgem);
		2019	if (!kgem_check_bo(&sna->kgem,
		2020	tmp->dst.bo, tmp->src.bo, tmp->mask.bo,
		2021	NULL))
		2022	goto cleanup_mask;
		2023	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2024	}
3254	Serge	2025
		2026	gen6_emit_composite_state(sna, tmp);
		2027	gen6_align_vertex(sna, tmp);
		2028	return true;
		2029
		2030	cleanup_mask:
		2031	if (tmp->mask.bo)
		2032	kgem_bo_destroy(&sna->kgem, tmp->mask.bo);
		2033	cleanup_src:
		2034	if (tmp->src.bo)
		2035	kgem_bo_destroy(&sna->kgem, tmp->src.bo);
		2036	cleanup_dst:
		2037	if (tmp->redirect.real_bo)
		2038	kgem_bo_destroy(&sna->kgem, tmp->dst.bo);
		2039	return false;
		2040	}
		2041
3278	Serge	2042
3254	Serge	2043	#if !NO_COMPOSITE_SPANS
		2044	fastcall static void
		2045	gen6_render_composite_spans_box(struct sna *sna,
		2046	const struct sna_composite_spans_op *op,
		2047	const BoxRec *box, float opacity)
		2048	{
		2049	DBG(("%s: src=+(%d, %d), opacity=%f, dst=+(%d, %d), box=(%d, %d) x (%d, %d)\n",
		2050	__FUNCTION__,
		2051	op->base.src.offset[0], op->base.src.offset[1],
		2052	opacity,
		2053	op->base.dst.x, op->base.dst.y,
		2054	box->x1, box->y1,
		2055	box->x2 - box->x1,
		2056	box->y2 - box->y1));
		2057
		2058	gen6_get_rectangles(sna, &op->base, 1, gen6_emit_composite_state);
		2059	op->prim_emit(sna, op, box, opacity);
		2060	}
		2061
		2062	static void
		2063	gen6_render_composite_spans_boxes(struct sna *sna,
		2064	const struct sna_composite_spans_op *op,
		2065	const BoxRec *box, int nbox,
		2066	float opacity)
		2067	{
		2068	DBG(("%s: nbox=%d, src=+(%d, %d), opacity=%f, dst=+(%d, %d)\n",
		2069	__FUNCTION__, nbox,
		2070	op->base.src.offset[0], op->base.src.offset[1],
		2071	opacity,
		2072	op->base.dst.x, op->base.dst.y));
		2073
		2074	do {
		2075	int nbox_this_time;
		2076
		2077	nbox_this_time = gen6_get_rectangles(sna, &op->base, nbox,
		2078	gen6_emit_composite_state);
		2079	nbox -= nbox_this_time;
		2080
		2081	do {
		2082	DBG((" %s: (%d, %d) x (%d, %d)\n", __FUNCTION__,
		2083	box->x1, box->y1,
		2084	box->x2 - box->x1,
		2085	box->y2 - box->y1));
		2086
		2087	op->prim_emit(sna, op, box++, opacity);
		2088	} while (--nbox_this_time);
		2089	} while (nbox);
		2090	}
		2091
		2092	fastcall static void
		2093	gen6_render_composite_spans_boxes__thread(struct sna *sna,
		2094	const struct sna_composite_spans_op *op,
		2095	const struct sna_opacity_box *box,
		2096	int nbox)
		2097	{
		2098	DBG(("%s: nbox=%d, src=+(%d, %d), dst=+(%d, %d)\n",
		2099	__FUNCTION__, nbox,
		2100	op->base.src.offset[0], op->base.src.offset[1],
		2101	op->base.dst.x, op->base.dst.y));
		2102
		2103	sna_vertex_lock(&sna->render);
		2104	do {
		2105	int nbox_this_time;
		2106	float *v;
		2107
		2108	nbox_this_time = gen6_get_rectangles(sna, &op->base, nbox,
		2109	gen6_emit_composite_state);
		2110	assert(nbox_this_time);
		2111	nbox -= nbox_this_time;
		2112
		2113	v = sna->render.vertices + sna->render.vertex_used;
		2114	sna->render.vertex_used += nbox_this_time * op->base.floats_per_rect;
		2115
		2116	sna_vertex_acquire__locked(&sna->render);
		2117	sna_vertex_unlock(&sna->render);
		2118
		2119	op->emit_boxes(op, box, nbox_this_time, v);
		2120	box += nbox_this_time;
		2121
		2122	sna_vertex_lock(&sna->render);
		2123	sna_vertex_release__locked(&sna->render);
		2124	} while (nbox);
		2125	sna_vertex_unlock(&sna->render);
		2126	}
		2127
		2128	fastcall static void
		2129	gen6_render_composite_spans_done(struct sna *sna,
		2130	const struct sna_composite_spans_op *op)
		2131	{
		2132	DBG(("%s()\n", __FUNCTION__));
		2133	assert(!sna->render.active);
		2134
		2135	if (sna->render.vertex_offset)
		2136	gen4_vertex_flush(sna);
		2137
		2138	if (op->base.src.bo)
		2139	kgem_bo_destroy(&sna->kgem, op->base.src.bo);
		2140
		2141	sna_render_composite_redirect_done(sna, &op->base);
		2142	}
		2143
		2144	static bool
		2145	gen6_check_composite_spans(struct sna *sna,
		2146	uint8_t op, PicturePtr src, PicturePtr dst,
		2147	int16_t width, int16_t height,
		2148	unsigned flags)
		2149	{
		2150	DBG(("%s: op=%d, width=%d, height=%d, flags=%x\n",
		2151	__FUNCTION__, op, width, height, flags));
		2152
		2153	if (op >= ARRAY_SIZE(gen6_blend_op))
		2154	return false;
		2155
		2156	if (gen6_composite_fallback(sna, src, NULL, dst)) {
		2157	DBG(("%s: operation would fallback\n", __FUNCTION__));
		2158	return false;
		2159	}
		2160
		2161	if (need_tiling(sna, width, height) &&
		2162	!is_gpu(sna, dst->pDrawable, PREFER_GPU_SPANS)) {
		2163	DBG(("%s: fallback, tiled operation not on GPU\n",
		2164	__FUNCTION__));
		2165	return false;
		2166	}
		2167
		2168	if ((flags & COMPOSITE_SPANS_RECTILINEAR) == 0) {
		2169	struct sna_pixmap *priv = sna_pixmap_from_drawable(dst->pDrawable);
		2170	assert(priv);
		2171
		2172	if (priv->cpu_bo && kgem_bo_is_busy(priv->cpu_bo))
		2173	return true;
		2174
		2175	if (flags & COMPOSITE_SPANS_INPLACE_HINT)
		2176	return false;
		2177
		2178	return priv->gpu_bo && kgem_bo_is_busy(priv->gpu_bo);
		2179	}
		2180
		2181	return true;
		2182	}
		2183
		2184	static bool
		2185	gen6_render_composite_spans(struct sna *sna,
		2186	uint8_t op,
		2187	PicturePtr src,
		2188	PicturePtr dst,
		2189	int16_t src_x, int16_t src_y,
		2190	int16_t dst_x, int16_t dst_y,
		2191	int16_t width, int16_t height,
		2192	unsigned flags,
		2193	struct sna_composite_spans_op *tmp)
		2194	{
		2195	DBG(("%s: %dx%d with flags=%x, current mode=%d\n", __FUNCTION__,
		2196	width, height, flags, sna->kgem.ring));
		2197
		2198	assert(gen6_check_composite_spans(sna, op, src, dst, width, height, flags));
		2199
		2200	if (need_tiling(sna, width, height)) {
		2201	DBG(("%s: tiling, operation (%dx%d) too wide for pipeline\n",
		2202	__FUNCTION__, width, height));
		2203	return sna_tiling_composite_spans(op, src, dst,
		2204	src_x, src_y, dst_x, dst_y,
		2205	width, height, flags, tmp);
		2206	}
		2207
		2208	tmp->base.op = op;
		2209	if (!gen6_composite_set_target(sna, &tmp->base, dst,
		2210	dst_x, dst_y, width, height))
		2211	return false;
		2212
		2213	switch (gen6_composite_picture(sna, src, &tmp->base.src,
		2214	src_x, src_y,
		2215	width, height,
		2216	dst_x, dst_y,
		2217	dst->polyMode == PolyModePrecise)) {
		2218	case -1:
		2219	goto cleanup_dst;
		2220	case 0:
		2221	if (!gen4_channel_init_solid(sna, &tmp->base.src, 0))
		2222	goto cleanup_dst;
		2223	/* fall through to fixup */
		2224	case 1:
		2225	gen6_composite_channel_convert(&tmp->base.src);
		2226	break;
		2227	}
		2228	tmp->base.mask.bo = NULL;
		2229
		2230	tmp->base.is_affine = tmp->base.src.is_affine;
		2231	tmp->base.need_magic_ca_pass = false;
		2232
		2233	tmp->base.u.gen6.flags =
		2234	GEN6_SET_FLAGS(SAMPLER_OFFSET(tmp->base.src.filter,
		2235	tmp->base.src.repeat,
		2236	SAMPLER_FILTER_NEAREST,
		2237	SAMPLER_EXTEND_PAD),
		2238	gen6_get_blend(tmp->base.op, false, tmp->base.dst.format),
		2239	GEN6_WM_KERNEL_OPACITY \| !tmp->base.is_affine,
		2240	gen4_choose_spans_emitter(tmp));
		2241
		2242	tmp->box = gen6_render_composite_spans_box;
		2243	tmp->boxes = gen6_render_composite_spans_boxes;
		2244	if (tmp->emit_boxes)
		2245	tmp->thread_boxes = gen6_render_composite_spans_boxes__thread;
		2246	tmp->done = gen6_render_composite_spans_done;
		2247
		2248	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp->base.dst.bo);
		2249	if (!kgem_check_bo(&sna->kgem,
		2250	tmp->base.dst.bo, tmp->base.src.bo,
		2251	NULL)) {
		2252	kgem_submit(&sna->kgem);
		2253	if (!kgem_check_bo(&sna->kgem,
		2254	tmp->base.dst.bo, tmp->base.src.bo,
		2255	NULL))
		2256	goto cleanup_src;
		2257	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2258	}
		2259
		2260	gen6_emit_composite_state(sna, &tmp->base);
		2261	gen6_align_vertex(sna, &tmp->base);
		2262	return true;
		2263
		2264	cleanup_src:
		2265	if (tmp->base.src.bo)
		2266	kgem_bo_destroy(&sna->kgem, tmp->base.src.bo);
		2267	cleanup_dst:
		2268	if (tmp->base.redirect.real_bo)
		2269	kgem_bo_destroy(&sna->kgem, tmp->base.dst.bo);
		2270	return false;
		2271	}
		2272	#endif
		2273
		2274
		2275	static void
		2276	gen6_emit_copy_state(struct sna *sna,
		2277	const struct sna_composite_op *op)
		2278	{
		2279	uint32_t *binding_table;
		2280	uint16_t offset;
		2281	bool dirty;
		2282
		2283	dirty = gen6_get_batch(sna, op);
		2284
		2285	binding_table = gen6_composite_get_binding_table(sna, &offset);
		2286
		2287	binding_table[0] =
		2288	gen6_bind_bo(sna,
		2289	op->dst.bo, op->dst.width, op->dst.height,
		2290	gen6_get_dest_format(op->dst.format),
		2291	true);
		2292	binding_table[1] =
		2293	gen6_bind_bo(sna,
		2294	op->src.bo, op->src.width, op->src.height,
		2295	op->src.card_format,
		2296	false);
		2297
		2298	if (sna->kgem.surface == offset &&
		2299	(uint64_t )(sna->kgem.batch + sna->render_state.gen6.surface_table) == (uint64_t)binding_table) {
		2300	sna->kgem.surface += sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t);
		2301	offset = sna->render_state.gen6.surface_table;
		2302	}
		2303
		2304	gen6_emit_state(sna, op, offset \| dirty);
		2305	}
		2306
		2307
		2308	static inline bool prefer_blt_copy(struct sna *sna,
		2309	struct kgem_bo *src_bo,
		2310	struct kgem_bo *dst_bo,
		2311	unsigned flags)
		2312	{
		2313	if (flags & COPY_SYNC)
		2314	return false;
		2315
		2316	if (PREFER_RENDER)
		2317	return PREFER_RENDER > 0;
		2318
		2319	if (sna->kgem.ring == KGEM_BLT)
		2320	return true;
		2321
		2322	if (src_bo == dst_bo && can_switch_to_blt(sna, dst_bo, flags))
		2323	return true;
		2324
		2325	if (untiled_tlb_miss(src_bo) \|\|
		2326	untiled_tlb_miss(dst_bo))
		2327	return true;
		2328
		2329	if (!prefer_blt_ring(sna, dst_bo, flags))
		2330	return false;
		2331
		2332	return (prefer_blt_bo(sna, src_bo) >= 0 &&
		2333	prefer_blt_bo(sna, dst_bo) > 0);
		2334	}
		2335
		2336	inline static void boxes_extents(const BoxRec box, int n, BoxRec extents)
		2337	{
		2338	*extents = box[0];
		2339	while (--n) {
		2340	box++;
		2341
		2342	if (box->x1 < extents->x1)
		2343	extents->x1 = box->x1;
		2344	if (box->x2 > extents->x2)
		2345	extents->x2 = box->x2;
		2346
		2347	if (box->y1 < extents->y1)
		2348	extents->y1 = box->y1;
		2349	if (box->y2 > extents->y2)
		2350	extents->y2 = box->y2;
		2351	}
		2352	}
		2353
		2354	static inline bool
		2355	overlaps(struct sna *sna,
		2356	struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
		2357	struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy,
		2358	const BoxRec box, int n, BoxRec extents)
		2359	{
		2360	if (src_bo != dst_bo)
		2361	return false;
		2362
		2363	boxes_extents(box, n, extents);
		2364	return (extents->x2 + src_dx > extents->x1 + dst_dx &&
		2365	extents->x1 + src_dx < extents->x2 + dst_dx &&
		2366	extents->y2 + src_dy > extents->y1 + dst_dy &&
		2367	extents->y1 + src_dy < extents->y2 + dst_dy);
		2368	}
		2369
		2370	static bool
		2371	gen6_render_copy_boxes(struct sna *sna, uint8_t alu,
		2372	PixmapPtr src, struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
		2373	PixmapPtr dst, struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy,
		2374	const BoxRec *box, int n, unsigned flags)
		2375	{
		2376	struct sna_composite_op tmp;
		2377	BoxRec extents;
		2378
		2379	DBG(("%s (%d, %d)->(%d, %d) x %d, alu=%x, self-copy=%d, overlaps? %d\n",
		2380	__FUNCTION__, src_dx, src_dy, dst_dx, dst_dy, n, alu,
		2381	src_bo == dst_bo,
		2382	overlaps(sna,
		2383	src_bo, src_dx, src_dy,
		2384	dst_bo, dst_dx, dst_dy,
		2385	box, n, &extents)));
		2386
		2387	if (prefer_blt_copy(sna, src_bo, dst_bo, flags) &&
		2388	sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
		2389	sna_blt_copy_boxes(sna, alu,
		2390	src_bo, src_dx, src_dy,
		2391	dst_bo, dst_dx, dst_dy,
		2392	dst->drawable.bitsPerPixel,
		2393	box, n))
		2394	return true;
		2395
		2396	if (!(alu == GXcopy \|\| alu == GXclear)) {
		2397	fallback_blt:
		2398	if (!sna_blt_compare_depth(&src->drawable, &dst->drawable))
		2399	return false;
		2400
		2401	return sna_blt_copy_boxes_fallback(sna, alu,
		2402	src, src_bo, src_dx, src_dy,
		2403	dst, dst_bo, dst_dx, dst_dy,
		2404	box, n);
		2405	}
		2406
		2407	if (overlaps(sna,
		2408	src_bo, src_dx, src_dy,
		2409	dst_bo, dst_dx, dst_dy,
		2410	box, n, &extents)) {
		2411	if (too_large(extents.x2-extents.x1, extents.y2-extents.y1))
		2412	goto fallback_blt;
		2413
		2414	if (can_switch_to_blt(sna, dst_bo, flags) &&
		2415	sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
		2416	sna_blt_copy_boxes(sna, alu,
		2417	src_bo, src_dx, src_dy,
		2418	dst_bo, dst_dx, dst_dy,
		2419	dst->drawable.bitsPerPixel,
		2420	box, n))
		2421	return true;
		2422
		2423	return sna_render_copy_boxes__overlap(sna, alu,
		2424	src, src_bo, src_dx, src_dy,
		2425	dst, dst_bo, dst_dx, dst_dy,
		2426	box, n, &extents);
		2427	}
		2428
		2429	if (dst->drawable.depth == src->drawable.depth) {
		2430	tmp.dst.format = sna_render_format_for_depth(dst->drawable.depth);
		2431	tmp.src.pict_format = tmp.dst.format;
		2432	} else {
		2433	tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
		2434	tmp.src.pict_format = sna_format_for_depth(src->drawable.depth);
		2435	}
		2436	if (!gen6_check_format(tmp.src.pict_format))
		2437	goto fallback_blt;
		2438
		2439	tmp.dst.pixmap = dst;
		2440	tmp.dst.width = dst->drawable.width;
		2441	tmp.dst.height = dst->drawable.height;
		2442	tmp.dst.bo = dst_bo;
		2443	tmp.dst.x = tmp.dst.y = 0;
		2444	tmp.damage = NULL;
		2445
		2446	sna_render_composite_redirect_init(&tmp);
		2447	if (too_large(tmp.dst.width, tmp.dst.height)) {
		2448	int i;
		2449
		2450	extents = box[0];
		2451	for (i = 1; i < n; i++) {
		2452	if (box[i].x1 < extents.x1)
		2453	extents.x1 = box[i].x1;
		2454	if (box[i].y1 < extents.y1)
		2455	extents.y1 = box[i].y1;
		2456
		2457	if (box[i].x2 > extents.x2)
		2458	extents.x2 = box[i].x2;
		2459	if (box[i].y2 > extents.y2)
		2460	extents.y2 = box[i].y2;
		2461	}
		2462
		2463	if (!sna_render_composite_redirect(sna, &tmp,
		2464	extents.x1 + dst_dx,
		2465	extents.y1 + dst_dy,
		2466	extents.x2 - extents.x1,
		2467	extents.y2 - extents.y1))
		2468	goto fallback_tiled;
		2469
		2470	dst_dx += tmp.dst.x;
		2471	dst_dy += tmp.dst.y;
		2472
		2473	tmp.dst.x = tmp.dst.y = 0;
		2474	}
		2475
		2476	tmp.src.card_format = gen6_get_card_format(tmp.src.pict_format);
		2477	if (too_large(src->drawable.width, src->drawable.height)) {
		2478	int i;
		2479
		2480	extents = box[0];
		2481	for (i = 1; i < n; i++) {
		2482	if (extents.x1 < box[i].x1)
		2483	extents.x1 = box[i].x1;
		2484	if (extents.y1 < box[i].y1)
		2485	extents.y1 = box[i].y1;
		2486
		2487	if (extents.x2 > box[i].x2)
		2488	extents.x2 = box[i].x2;
		2489	if (extents.y2 > box[i].y2)
		2490	extents.y2 = box[i].y2;
		2491	}
		2492
		2493	if (!sna_render_pixmap_partial(sna, src, src_bo, &tmp.src,
		2494	extents.x1 + src_dx,
		2495	extents.y1 + src_dy,
		2496	extents.x2 - extents.x1,
		2497	extents.y2 - extents.y1)) {
		2498	DBG(("%s: unable to extract partial pixmap\n", __FUNCTION__));
		2499	goto fallback_tiled_dst;
		2500	}
		2501
		2502	src_dx += tmp.src.offset[0];
		2503	src_dy += tmp.src.offset[1];
		2504	} else {
		2505	tmp.src.bo = src_bo;
		2506	tmp.src.width = src->drawable.width;
		2507	tmp.src.height = src->drawable.height;
		2508	}
		2509
		2510	tmp.mask.bo = NULL;
		2511
		2512	tmp.floats_per_vertex = 2;
		2513	tmp.floats_per_rect = 6;
		2514	tmp.need_magic_ca_pass = 0;
		2515
		2516	tmp.u.gen6.flags = COPY_FLAGS(alu);
		2517	assert(GEN6_KERNEL(tmp.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		2518	assert(GEN6_SAMPLER(tmp.u.gen6.flags) == COPY_SAMPLER);
		2519	assert(GEN6_VERTEX(tmp.u.gen6.flags) == COPY_VERTEX);
		2520
		2521	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp.dst.bo);
		2522	if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, tmp.src.bo, NULL)) {
		2523	kgem_submit(&sna->kgem);
		2524	if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, tmp.src.bo, NULL)) {
		2525	DBG(("%s: too large for a single operation\n",
		2526	__FUNCTION__));
		2527	goto fallback_tiled_src;
		2528	}
		2529	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2530	}
		2531
		2532	gen6_emit_copy_state(sna, &tmp);
		2533	gen6_align_vertex(sna, &tmp);
		2534
		2535	do {
		2536	int16_t *v;
		2537	int n_this_time;
		2538
		2539	n_this_time = gen6_get_rectangles(sna, &tmp, n,
		2540	gen6_emit_copy_state);
		2541	n -= n_this_time;
		2542
		2543	v = (int16_t *)(sna->render.vertices + sna->render.vertex_used);
		2544	sna->render.vertex_used += 6 * n_this_time;
		2545	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2546	do {
		2547
		2548	DBG((" (%d, %d) -> (%d, %d) + (%d, %d)\n",
		2549	box->x1 + src_dx, box->y1 + src_dy,
		2550	box->x1 + dst_dx, box->y1 + dst_dy,
		2551	box->x2 - box->x1, box->y2 - box->y1));
		2552	v[0] = box->x2 + dst_dx;
		2553	v[2] = box->x2 + src_dx;
		2554	v[1] = v[5] = box->y2 + dst_dy;
		2555	v[3] = v[7] = box->y2 + src_dy;
		2556	v[8] = v[4] = box->x1 + dst_dx;
		2557	v[10] = v[6] = box->x1 + src_dx;
		2558	v[9] = box->y1 + dst_dy;
		2559	v[11] = box->y1 + src_dy;
		2560	v += 12; box++;
		2561	} while (--n_this_time);
		2562	} while (n);
		2563
		2564	gen4_vertex_flush(sna);
		2565	sna_render_composite_redirect_done(sna, &tmp);
		2566	if (tmp.src.bo != src_bo)
		2567	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		2568	return true;
		2569
		2570	fallback_tiled_src:
		2571	if (tmp.src.bo != src_bo)
		2572	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		2573	fallback_tiled_dst:
		2574	if (tmp.redirect.real_bo)
		2575	kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
		2576	fallback_tiled:
		2577	if (sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
		2578	sna_blt_copy_boxes(sna, alu,
		2579	src_bo, src_dx, src_dy,
		2580	dst_bo, dst_dx, dst_dy,
		2581	dst->drawable.bitsPerPixel,
		2582	box, n))
		2583	return true;
		2584
		2585	return sna_tiling_copy_boxes(sna, alu,
		2586	src, src_bo, src_dx, src_dy,
		2587	dst, dst_bo, dst_dx, dst_dy,
		2588	box, n);
		2589	}
		2590
		2591	static void
		2592	gen6_render_copy_blt(struct sna *sna,
		2593	const struct sna_copy_op *op,
		2594	int16_t sx, int16_t sy,
		2595	int16_t w, int16_t h,
		2596	int16_t dx, int16_t dy)
		2597	{
		2598	int16_t *v;
		2599
		2600	gen6_get_rectangles(sna, &op->base, 1, gen6_emit_copy_state);
		2601
		2602	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		2603	sna->render.vertex_used += 6;
		2604	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2605
		2606	v[0] = dx+w; v[1] = dy+h;
		2607	v[2] = sx+w; v[3] = sy+h;
		2608	v[4] = dx; v[5] = dy+h;
		2609	v[6] = sx; v[7] = sy+h;
		2610	v[8] = dx; v[9] = dy;
		2611	v[10] = sx; v[11] = sy;
		2612	}
		2613
		2614	static void
		2615	gen6_render_copy_done(struct sna sna, const struct sna_copy_op op)
		2616	{
		2617	DBG(("%s()\n", __FUNCTION__));
		2618
		2619	assert(!sna->render.active);
		2620	if (sna->render.vertex_offset)
		2621	gen4_vertex_flush(sna);
		2622	}
		2623
		2624	static bool
		2625	gen6_render_copy(struct sna *sna, uint8_t alu,
		2626	PixmapPtr src, struct kgem_bo *src_bo,
		2627	PixmapPtr dst, struct kgem_bo *dst_bo,
		2628	struct sna_copy_op *op)
		2629	{
		2630	DBG(("%s (alu=%d, src=(%dx%d), dst=(%dx%d))\n",
		2631	__FUNCTION__, alu,
		2632	src->drawable.width, src->drawable.height,
		2633	dst->drawable.width, dst->drawable.height));
		2634
		2635	fallback:
		2636
		2637	op->base.dst.format = PIXMAN_a8r8g8b8;
		2638	op->base.src.pict_format = op->base.dst.format;
		2639
		2640	op->base.dst.pixmap = dst;
		2641	op->base.dst.width = dst->drawable.width;
		2642	op->base.dst.height = dst->drawable.height;
		2643	op->base.dst.bo = dst_bo;
		2644
		2645	op->base.src.bo = src_bo;
		2646	op->base.src.card_format =
		2647	gen6_get_card_format(op->base.src.pict_format);
		2648	op->base.src.width = src->drawable.width;
		2649	op->base.src.height = src->drawable.height;
		2650
		2651	op->base.mask.bo = NULL;
		2652
		2653	op->base.floats_per_vertex = 2;
		2654	op->base.floats_per_rect = 6;
		2655
		2656	op->base.u.gen6.flags = COPY_FLAGS(alu);
		2657	assert(GEN6_KERNEL(op->base.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		2658	assert(GEN6_SAMPLER(op->base.u.gen6.flags) == COPY_SAMPLER);
		2659	assert(GEN6_VERTEX(op->base.u.gen6.flags) == COPY_VERTEX);
		2660
3263	Serge	2661	kgem_set_mode(&sna->kgem, KGEM_RENDER, dst_bo);
		2662	if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL)) {
		2663	kgem_submit(&sna->kgem);
		2664	if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL))
		2665	goto fallback;
		2666	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2667	}
3254	Serge	2668
		2669	gen6_emit_copy_state(sna, &op->base);
		2670	gen6_align_vertex(sna, &op->base);
		2671
		2672	op->blt = gen6_render_copy_blt;
		2673	op->done = gen6_render_copy_done;
		2674	return true;
		2675	}
3769	Serge	2676	#endif
3254	Serge	2677
3278	Serge	2678
3280	Serge	2679	static bool
		2680	gen6_blit_tex(struct sna *sna,
3769	Serge	2681	uint8_t op, bool scale,
3278	Serge	2682	PixmapPtr src, struct kgem_bo *src_bo,
		2683	PixmapPtr mask,struct kgem_bo *mask_bo,
		2684	PixmapPtr dst, struct kgem_bo *dst_bo,
		2685	int32_t src_x, int32_t src_y,
		2686	int32_t msk_x, int32_t msk_y,
		2687	int32_t dst_x, int32_t dst_y,
		2688	int32_t width, int32_t height,
		2689	struct sna_composite_op *tmp)
		2690	{
		2691
		2692	DBG(("%s: %dx%d, current mode=%d\n", __FUNCTION__,
		2693	width, height, sna->kgem.ring));
		2694
		2695	tmp->op = PictOpSrc;
		2696
		2697	tmp->dst.pixmap = dst;
		2698	tmp->dst.bo = dst_bo;
		2699	tmp->dst.width = dst->drawable.width;
		2700	tmp->dst.height = dst->drawable.height;
		2701	tmp->dst.format = PICT_x8r8g8b8;
		2702
		2703
3291	Serge	2704	tmp->src.repeat = SAMPLER_EXTEND_NONE;
3278	Serge	2705	tmp->src.is_affine = true;
		2706
		2707	tmp->src.bo = src_bo;
		2708	tmp->src.pict_format = PICT_x8r8g8b8;
		2709	tmp->src.card_format = gen6_get_card_format(tmp->src.pict_format);
		2710	tmp->src.width = src->drawable.width;
		2711	tmp->src.height = src->drawable.height;
		2712
3291	Serge	2713	if ( (tmp->src.width == width) &&
		2714	(tmp->src.height == height) )
		2715	tmp->src.filter = SAMPLER_FILTER_NEAREST;
		2716	else
		2717	tmp->src.filter = SAMPLER_FILTER_BILINEAR;
		2718
3278	Serge	2719	tmp->is_affine = tmp->src.is_affine;
		2720	tmp->has_component_alpha = false;
		2721	tmp->need_magic_ca_pass = false;
		2722
		2723	tmp->mask.repeat = SAMPLER_EXTEND_NONE;
		2724	tmp->mask.filter = SAMPLER_FILTER_NEAREST;
		2725	tmp->mask.is_affine = true;
		2726
		2727	tmp->mask.bo = mask_bo;
		2728	tmp->mask.pict_format = PIXMAN_a8;
		2729	tmp->mask.card_format = gen6_get_card_format(tmp->mask.pict_format);
		2730	tmp->mask.width = mask->drawable.width;
		2731	tmp->mask.height = mask->drawable.height;
		2732
		2733
3769	Serge	2734	if( scale )
		2735	{
		2736	tmp->src.scale[0] = 1.f/width;
		2737	tmp->src.scale[1] = 1.f/height;
		2738	}
		2739	else
		2740	{
		2741	tmp->src.scale[0] = 1.f/src->drawable.width;
		2742	tmp->src.scale[1] = 1.f/src->drawable.height;
		2743	}
3278	Serge	2744	// tmp->src.offset[0] = -dst_x;
		2745	// tmp->src.offset[1] = -dst_y;
		2746
		2747
		2748	tmp->mask.scale[0] = 1.f/mask->drawable.width;
		2749	tmp->mask.scale[1] = 1.f/mask->drawable.height;
		2750	// tmp->mask.offset[0] = -dst_x;
		2751	// tmp->mask.offset[1] = -dst_y;
		2752
		2753	tmp->u.gen6.flags =
		2754	GEN6_SET_FLAGS(SAMPLER_OFFSET(tmp->src.filter,
		2755	tmp->src.repeat,
		2756	tmp->mask.filter,
		2757	tmp->mask.repeat),
		2758	gen6_get_blend(tmp->op,
		2759	tmp->has_component_alpha,
		2760	tmp->dst.format),
		2761	/* gen6_choose_composite_kernel(tmp->op,
		2762	tmp->mask.bo != NULL,
		2763	tmp->has_component_alpha,
		2764	tmp->is_affine),
		2765	*/
		2766	GEN6_WM_KERNEL_MASK,
		2767	gen4_choose_composite_emitter(tmp));
		2768
		2769	tmp->blt = gen6_render_composite_blt;
		2770	// tmp->box = gen6_render_composite_box;
		2771	tmp->done = gen6_render_composite_done;
		2772
		2773	kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp->dst.bo);
		2774	if (!kgem_check_bo(&sna->kgem,
		2775	tmp->dst.bo, tmp->src.bo, tmp->mask.bo,
		2776	NULL)) {
		2777	kgem_submit(&sna->kgem);
		2778	_kgem_set_mode(&sna->kgem, KGEM_RENDER);
		2779	}
		2780
		2781	gen6_emit_composite_state(sna, tmp);
		2782	gen6_align_vertex(sna, tmp);
		2783	return true;
		2784
		2785	}
		2786
		2787
		2788
3254	Serge	2789	#if 0
		2790
		2791	static void
		2792	gen6_emit_fill_state(struct sna sna, const struct sna_composite_op op)
		2793	{
		2794	uint32_t *binding_table;
		2795	uint16_t offset;
		2796	bool dirty;
		2797
		2798	dirty = gen6_get_batch(sna, op);
		2799
		2800	binding_table = gen6_composite_get_binding_table(sna, &offset);
		2801
		2802	binding_table[0] =
		2803	gen6_bind_bo(sna,
		2804	op->dst.bo, op->dst.width, op->dst.height,
		2805	gen6_get_dest_format(op->dst.format),
		2806	true);
		2807	binding_table[1] =
		2808	gen6_bind_bo(sna,
		2809	op->src.bo, 1, 1,
		2810	GEN6_SURFACEFORMAT_B8G8R8A8_UNORM,
		2811	false);
		2812
		2813	if (sna->kgem.surface == offset &&
		2814	(uint64_t )(sna->kgem.batch + sna->render_state.gen6.surface_table) == (uint64_t)binding_table) {
		2815	sna->kgem.surface +=
		2816	sizeof(struct gen6_surface_state_padded)/sizeof(uint32_t);
		2817	offset = sna->render_state.gen6.surface_table;
		2818	}
		2819
		2820	gen6_emit_state(sna, op, offset \| dirty);
		2821	}
		2822
		2823	static inline bool prefer_blt_fill(struct sna *sna,
		2824	struct kgem_bo *bo)
		2825	{
		2826	if (PREFER_RENDER)
		2827	return PREFER_RENDER < 0;
		2828
		2829	if (untiled_tlb_miss(bo))
		2830	return true;
		2831
		2832	return prefer_blt_ring(sna, bo, 0) \|\| prefer_blt_bo(sna, bo) >= 0;
		2833	}
		2834
		2835	static bool
		2836	gen6_render_fill_boxes(struct sna *sna,
		2837	CARD8 op,
		2838	PictFormat format,
		2839	const xRenderColor *color,
		2840	PixmapPtr dst, struct kgem_bo *dst_bo,
		2841	const BoxRec *box, int n)
		2842	{
		2843	struct sna_composite_op tmp;
		2844	uint32_t pixel;
		2845
		2846	DBG(("%s (op=%d, color=(%04x, %04x, %04x, %04x) [%08x])\n",
		2847	__FUNCTION__, op,
		2848	color->red, color->green, color->blue, color->alpha, (int)format));
		2849
		2850	if (op >= ARRAY_SIZE(gen6_blend_op)) {
		2851	DBG(("%s: fallback due to unhandled blend op: %d\n",
		2852	__FUNCTION__, op));
		2853	return false;
		2854	}
		2855
		2856	if (prefer_blt_fill(sna, dst_bo) \|\| !gen6_check_dst_format(format)) {
		2857	uint8_t alu = GXinvalid;
		2858
		2859	if (op <= PictOpSrc) {
		2860	pixel = 0;
		2861	if (op == PictOpClear)
		2862	alu = GXclear;
		2863	else if (sna_get_pixel_from_rgba(&pixel,
		2864	color->red,
		2865	color->green,
		2866	color->blue,
		2867	color->alpha,
		2868	format))
		2869	alu = GXcopy;
		2870	}
		2871
		2872	if (alu != GXinvalid &&
		2873	sna_blt_fill_boxes(sna, alu,
		2874	dst_bo, dst->drawable.bitsPerPixel,
		2875	pixel, box, n))
		2876	return true;
		2877
		2878	if (!gen6_check_dst_format(format))
		2879	return false;
		2880	}
		2881
		2882	if (op == PictOpClear) {
		2883	pixel = 0;
		2884	op = PictOpSrc;
		2885	} else if (!sna_get_pixel_from_rgba(&pixel,
		2886	color->red,
		2887	color->green,
		2888	color->blue,
		2889	color->alpha,
		2890	PICT_a8r8g8b8))
		2891	return false;
		2892
		2893	DBG(("%s(%08x x %d [(%d, %d), (%d, %d) ...])\n",
		2894	__FUNCTION__, pixel, n,
		2895	box[0].x1, box[0].y1, box[0].x2, box[0].y2));
		2896
		2897	tmp.dst.pixmap = dst;
		2898	tmp.dst.width = dst->drawable.width;
		2899	tmp.dst.height = dst->drawable.height;
		2900	tmp.dst.format = format;
		2901	tmp.dst.bo = dst_bo;
		2902	tmp.dst.x = tmp.dst.y = 0;
		2903	tmp.damage = NULL;
		2904
		2905	sna_render_composite_redirect_init(&tmp);
		2906	if (too_large(dst->drawable.width, dst->drawable.height)) {
		2907	BoxRec extents;
		2908
		2909	boxes_extents(box, n, &extents);
		2910	if (!sna_render_composite_redirect(sna, &tmp,
		2911	extents.x1, extents.y1,
		2912	extents.x2 - extents.x1,
		2913	extents.y2 - extents.y1))
		2914	return sna_tiling_fill_boxes(sna, op, format, color,
		2915	dst, dst_bo, box, n);
		2916	}
		2917
		2918	tmp.src.bo = sna_render_get_solid(sna, pixel);
		2919	tmp.mask.bo = NULL;
		2920
		2921	tmp.floats_per_vertex = 2;
		2922	tmp.floats_per_rect = 6;
		2923	tmp.need_magic_ca_pass = false;
		2924
		2925	tmp.u.gen6.flags = FILL_FLAGS(op, format);
		2926	assert(GEN6_KERNEL(tmp.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		2927	assert(GEN6_SAMPLER(tmp.u.gen6.flags) == FILL_SAMPLER);
		2928	assert(GEN6_VERTEX(tmp.u.gen6.flags) == FILL_VERTEX);
		2929
		2930	if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
		2931	kgem_submit(&sna->kgem);
		2932	assert(kgem_check_bo(&sna->kgem, dst_bo, NULL));
		2933	}
		2934
		2935	gen6_emit_fill_state(sna, &tmp);
		2936	gen6_align_vertex(sna, &tmp);
		2937
		2938	do {
		2939	int n_this_time;
		2940	int16_t *v;
		2941
		2942	n_this_time = gen6_get_rectangles(sna, &tmp, n,
		2943	gen6_emit_fill_state);
		2944	n -= n_this_time;
		2945
		2946	v = (int16_t *)(sna->render.vertices + sna->render.vertex_used);
		2947	sna->render.vertex_used += 6 * n_this_time;
		2948	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2949	do {
		2950	DBG((" (%d, %d), (%d, %d)\n",
		2951	box->x1, box->y1, box->x2, box->y2));
		2952
		2953	v[0] = box->x2;
		2954	v[5] = v[1] = box->y2;
		2955	v[8] = v[4] = box->x1;
		2956	v[9] = box->y1;
		2957	v[2] = v[3] = v[7] = 1;
		2958	v[6] = v[10] = v[11] = 0;
		2959	v += 12; box++;
		2960	} while (--n_this_time);
		2961	} while (n);
		2962
		2963	gen4_vertex_flush(sna);
		2964	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		2965	sna_render_composite_redirect_done(sna, &tmp);
		2966	return true;
		2967	}
		2968
		2969	static void
		2970	gen6_render_op_fill_blt(struct sna *sna,
		2971	const struct sna_fill_op *op,
		2972	int16_t x, int16_t y, int16_t w, int16_t h)
		2973	{
		2974	int16_t *v;
		2975
		2976	DBG(("%s: (%d, %d)x(%d, %d)\n", __FUNCTION__, x, y, w, h));
		2977
		2978	gen6_get_rectangles(sna, &op->base, 1, gen6_emit_fill_state);
		2979
		2980	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		2981	sna->render.vertex_used += 6;
		2982	assert(sna->render.vertex_used <= sna->render.vertex_size);
		2983
		2984	v[0] = x+w;
		2985	v[4] = v[8] = x;
		2986	v[1] = v[5] = y+h;
		2987	v[9] = y;
		2988
		2989	v[2] = v[3] = v[7] = 1;
		2990	v[6] = v[10] = v[11] = 0;
		2991	}
		2992
		2993	fastcall static void
		2994	gen6_render_op_fill_box(struct sna *sna,
		2995	const struct sna_fill_op *op,
		2996	const BoxRec *box)
		2997	{
		2998	int16_t *v;
		2999
		3000	DBG(("%s: (%d, %d),(%d, %d)\n", __FUNCTION__,
		3001	box->x1, box->y1, box->x2, box->y2));
		3002
		3003	gen6_get_rectangles(sna, &op->base, 1, gen6_emit_fill_state);
		3004
		3005	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		3006	sna->render.vertex_used += 6;
		3007	assert(sna->render.vertex_used <= sna->render.vertex_size);
		3008
		3009	v[0] = box->x2;
		3010	v[8] = v[4] = box->x1;
		3011	v[5] = v[1] = box->y2;
		3012	v[9] = box->y1;
		3013
		3014	v[7] = v[2] = v[3] = 1;
		3015	v[6] = v[10] = v[11] = 0;
		3016	}
		3017
		3018	fastcall static void
		3019	gen6_render_op_fill_boxes(struct sna *sna,
		3020	const struct sna_fill_op *op,
		3021	const BoxRec *box,
		3022	int nbox)
		3023	{
		3024	DBG(("%s: (%d, %d),(%d, %d)... x %d\n", __FUNCTION__,
		3025	box->x1, box->y1, box->x2, box->y2, nbox));
		3026
		3027	do {
		3028	int nbox_this_time;
		3029	int16_t *v;
		3030
		3031	nbox_this_time = gen6_get_rectangles(sna, &op->base, nbox,
		3032	gen6_emit_fill_state);
		3033	nbox -= nbox_this_time;
		3034
		3035	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		3036	sna->render.vertex_used += 6 * nbox_this_time;
		3037	assert(sna->render.vertex_used <= sna->render.vertex_size);
		3038
		3039	do {
		3040	v[0] = box->x2;
		3041	v[8] = v[4] = box->x1;
		3042	v[5] = v[1] = box->y2;
		3043	v[9] = box->y1;
		3044	v[7] = v[2] = v[3] = 1;
		3045	v[6] = v[10] = v[11] = 0;
		3046	box++; v += 12;
		3047	} while (--nbox_this_time);
		3048	} while (nbox);
		3049	}
		3050
		3051	static void
		3052	gen6_render_op_fill_done(struct sna sna, const struct sna_fill_op op)
		3053	{
		3054	DBG(("%s()\n", __FUNCTION__));
		3055
		3056	assert(!sna->render.active);
		3057	if (sna->render.vertex_offset)
		3058	gen4_vertex_flush(sna);
		3059	kgem_bo_destroy(&sna->kgem, op->base.src.bo);
		3060	}
		3061
		3062	static bool
		3063	gen6_render_fill(struct sna *sna, uint8_t alu,
		3064	PixmapPtr dst, struct kgem_bo *dst_bo,
		3065	uint32_t color,
		3066	struct sna_fill_op *op)
		3067	{
		3068	DBG(("%s: (alu=%d, color=%x)\n", __FUNCTION__, alu, color));
		3069
		3070	if (prefer_blt_fill(sna, dst_bo) &&
		3071	sna_blt_fill(sna, alu,
		3072	dst_bo, dst->drawable.bitsPerPixel,
		3073	color,
		3074	op))
		3075	return true;
		3076
		3077	if (!(alu == GXcopy \|\| alu == GXclear) \|\|
		3078	too_large(dst->drawable.width, dst->drawable.height))
		3079	return sna_blt_fill(sna, alu,
		3080	dst_bo, dst->drawable.bitsPerPixel,
		3081	color,
		3082	op);
		3083
		3084	if (alu == GXclear)
		3085	color = 0;
		3086
		3087	op->base.dst.pixmap = dst;
		3088	op->base.dst.width = dst->drawable.width;
		3089	op->base.dst.height = dst->drawable.height;
		3090	op->base.dst.format = sna_format_for_depth(dst->drawable.depth);
		3091	op->base.dst.bo = dst_bo;
		3092	op->base.dst.x = op->base.dst.y = 0;
		3093
		3094	op->base.src.bo =
		3095	sna_render_get_solid(sna,
		3096	sna_rgba_for_color(color,
		3097	dst->drawable.depth));
		3098	op->base.mask.bo = NULL;
		3099
		3100	op->base.need_magic_ca_pass = false;
		3101	op->base.floats_per_vertex = 2;
		3102	op->base.floats_per_rect = 6;
		3103
		3104	op->base.u.gen6.flags = FILL_FLAGS_NOBLEND;
		3105	assert(GEN6_KERNEL(op->base.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		3106	assert(GEN6_SAMPLER(op->base.u.gen6.flags) == FILL_SAMPLER);
		3107	assert(GEN6_VERTEX(op->base.u.gen6.flags) == FILL_VERTEX);
		3108
		3109	if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
		3110	kgem_submit(&sna->kgem);
		3111	assert(kgem_check_bo(&sna->kgem, dst_bo, NULL));
		3112	}
		3113
		3114	gen6_emit_fill_state(sna, &op->base);
		3115	gen6_align_vertex(sna, &op->base);
		3116
		3117	op->blt = gen6_render_op_fill_blt;
		3118	op->box = gen6_render_op_fill_box;
		3119	op->boxes = gen6_render_op_fill_boxes;
		3120	op->done = gen6_render_op_fill_done;
		3121	return true;
		3122	}
		3123
		3124	static bool
		3125	gen6_render_fill_one_try_blt(struct sna sna, PixmapPtr dst, struct kgem_bo bo,
		3126	uint32_t color,
		3127	int16_t x1, int16_t y1, int16_t x2, int16_t y2,
		3128	uint8_t alu)
		3129	{
		3130	BoxRec box;
		3131
		3132	box.x1 = x1;
		3133	box.y1 = y1;
		3134	box.x2 = x2;
		3135	box.y2 = y2;
		3136
		3137	return sna_blt_fill_boxes(sna, alu,
		3138	bo, dst->drawable.bitsPerPixel,
		3139	color, &box, 1);
		3140	}
		3141
		3142	static bool
		3143	gen6_render_fill_one(struct sna sna, PixmapPtr dst, struct kgem_bo bo,
		3144	uint32_t color,
		3145	int16_t x1, int16_t y1,
		3146	int16_t x2, int16_t y2,
		3147	uint8_t alu)
		3148	{
		3149	struct sna_composite_op tmp;
		3150	int16_t *v;
		3151
		3152	/* Prefer to use the BLT if already engaged */
		3153	if (prefer_blt_fill(sna, bo) &&
		3154	gen6_render_fill_one_try_blt(sna, dst, bo, color,
		3155	x1, y1, x2, y2, alu))
		3156	return true;
		3157
		3158	/* Must use the BLT if we can't RENDER... */
		3159	if (!(alu == GXcopy \|\| alu == GXclear) \|\|
		3160	too_large(dst->drawable.width, dst->drawable.height))
		3161	return gen6_render_fill_one_try_blt(sna, dst, bo, color,
		3162	x1, y1, x2, y2, alu);
		3163
		3164	if (alu == GXclear)
		3165	color = 0;
		3166
		3167	tmp.dst.pixmap = dst;
		3168	tmp.dst.width = dst->drawable.width;
		3169	tmp.dst.height = dst->drawable.height;
		3170	tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
		3171	tmp.dst.bo = bo;
		3172	tmp.dst.x = tmp.dst.y = 0;
		3173
		3174	tmp.src.bo =
		3175	sna_render_get_solid(sna,
		3176	sna_rgba_for_color(color,
		3177	dst->drawable.depth));
		3178	tmp.mask.bo = NULL;
		3179
		3180	tmp.floats_per_vertex = 2;
		3181	tmp.floats_per_rect = 6;
		3182	tmp.need_magic_ca_pass = false;
		3183
		3184	tmp.u.gen6.flags = FILL_FLAGS_NOBLEND;
		3185	assert(GEN6_KERNEL(tmp.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		3186	assert(GEN6_SAMPLER(tmp.u.gen6.flags) == FILL_SAMPLER);
		3187	assert(GEN6_VERTEX(tmp.u.gen6.flags) == FILL_VERTEX);
		3188
		3189	if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
		3190	kgem_submit(&sna->kgem);
		3191	if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
		3192	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		3193	return false;
		3194	}
		3195	}
		3196
		3197	gen6_emit_fill_state(sna, &tmp);
		3198	gen6_align_vertex(sna, &tmp);
		3199
		3200	gen6_get_rectangles(sna, &tmp, 1, gen6_emit_fill_state);
		3201
		3202	DBG((" (%d, %d), (%d, %d)\n", x1, y1, x2, y2));
		3203
		3204	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		3205	sna->render.vertex_used += 6;
		3206	assert(sna->render.vertex_used <= sna->render.vertex_size);
		3207
		3208	v[0] = x2;
		3209	v[8] = v[4] = x1;
		3210	v[5] = v[1] = y2;
		3211	v[9] = y1;
		3212	v[7] = v[2] = v[3] = 1;
		3213	v[6] = v[10] = v[11] = 0;
		3214
		3215	gen4_vertex_flush(sna);
		3216	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		3217
		3218	return true;
		3219	}
		3220
		3221	static bool
		3222	gen6_render_clear_try_blt(struct sna sna, PixmapPtr dst, struct kgem_bo bo)
		3223	{
		3224	BoxRec box;
		3225
		3226	box.x1 = 0;
		3227	box.y1 = 0;
		3228	box.x2 = dst->drawable.width;
		3229	box.y2 = dst->drawable.height;
		3230
		3231	return sna_blt_fill_boxes(sna, GXclear,
		3232	bo, dst->drawable.bitsPerPixel,
		3233	0, &box, 1);
		3234	}
		3235
		3236	static bool
		3237	gen6_render_clear(struct sna sna, PixmapPtr dst, struct kgem_bo bo)
		3238	{
		3239	struct sna_composite_op tmp;
		3240	int16_t *v;
		3241
		3242	DBG(("%s: %dx%d\n",
		3243	__FUNCTION__,
		3244	dst->drawable.width,
		3245	dst->drawable.height));
		3246
		3247	/* Prefer to use the BLT if, and only if, already engaged */
		3248	if (sna->kgem.ring == KGEM_BLT &&
		3249	gen6_render_clear_try_blt(sna, dst, bo))
		3250	return true;
		3251
		3252	/* Must use the BLT if we can't RENDER... */
		3253	if (too_large(dst->drawable.width, dst->drawable.height))
		3254	return gen6_render_clear_try_blt(sna, dst, bo);
		3255
		3256	tmp.dst.pixmap = dst;
		3257	tmp.dst.width = dst->drawable.width;
		3258	tmp.dst.height = dst->drawable.height;
		3259	tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
		3260	tmp.dst.bo = bo;
		3261	tmp.dst.x = tmp.dst.y = 0;
		3262
		3263	tmp.src.bo = sna_render_get_solid(sna, 0);
		3264	tmp.mask.bo = NULL;
		3265
		3266	tmp.floats_per_vertex = 2;
		3267	tmp.floats_per_rect = 6;
		3268	tmp.need_magic_ca_pass = false;
		3269
		3270	tmp.u.gen6.flags = FILL_FLAGS_NOBLEND;
		3271	assert(GEN6_KERNEL(tmp.u.gen6.flags) == GEN6_WM_KERNEL_NOMASK);
		3272	assert(GEN6_SAMPLER(tmp.u.gen6.flags) == FILL_SAMPLER);
		3273	assert(GEN6_VERTEX(tmp.u.gen6.flags) == FILL_VERTEX);
		3274
3263	Serge	3275	if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
		3276	kgem_submit(&sna->kgem);
		3277	if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
		3278	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		3279	return false;
		3280	}
		3281	}
3254	Serge	3282
		3283	gen6_emit_fill_state(sna, &tmp);
		3284	gen6_align_vertex(sna, &tmp);
		3285
		3286	gen6_get_rectangles(sna, &tmp, 1, gen6_emit_fill_state);
		3287
		3288	v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
		3289	sna->render.vertex_used += 6;
		3290	assert(sna->render.vertex_used <= sna->render.vertex_size);
		3291
		3292	v[0] = dst->drawable.width;
		3293	v[5] = v[1] = dst->drawable.height;
		3294	v[8] = v[4] = 0;
		3295	v[9] = 0;
		3296
		3297	v[7] = v[2] = v[3] = 1;
		3298	v[6] = v[10] = v[11] = 0;
		3299
		3300	gen4_vertex_flush(sna);
		3301	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
		3302
		3303	return true;
		3304	}
3263	Serge	3305	#endif
3254	Serge	3306
		3307	static void gen6_render_flush(struct sna *sna)
		3308	{
		3309	gen4_vertex_close(sna);
		3310
		3311	assert(sna->render.vb_id == 0);
		3312	assert(sna->render.vertex_offset == 0);
		3313	}
		3314
3263	Serge	3315	static void
		3316	gen6_render_context_switch(struct kgem *kgem,
		3317	int new_mode)
		3318	{
		3319	if (kgem->nbatch) {
		3320	DBG(("%s: from %d to %d\n", __FUNCTION__, kgem->mode, new_mode));
		3321	_kgem_submit(kgem);
		3322	}
3254	Serge	3323
3263	Serge	3324	kgem->ring = new_mode;
		3325	}
		3326
3254	Serge	3327	static void
		3328	gen6_render_retire(struct kgem *kgem)
		3329	{
		3330	struct sna *sna;
		3331
		3332	if (kgem->ring && (kgem->has_semaphores \|\| !kgem->need_retire))
		3333	kgem->ring = kgem->mode;
		3334
		3335	sna = container_of(kgem, struct sna, kgem);
		3336	if (kgem->nbatch == 0 && sna->render.vbo && !kgem_bo_is_busy(sna->render.vbo)) {
		3337	DBG(("%s: resetting idle vbo handle=%d\n", __FUNCTION__, sna->render.vbo->handle));
		3338	sna->render.vertex_used = 0;
		3339	sna->render.vertex_index = 0;
		3340	}
		3341	}
		3342
3263	Serge	3343	static void
		3344	gen6_render_expire(struct kgem *kgem)
		3345	{
		3346	struct sna *sna;
3254	Serge	3347
3263	Serge	3348	sna = container_of(kgem, struct sna, kgem);
		3349	if (sna->render.vbo && !sna->render.vertex_used) {
		3350	DBG(("%s: discarding vbo handle=%d\n", __FUNCTION__, sna->render.vbo->handle));
		3351	kgem_bo_destroy(kgem, sna->render.vbo);
		3352	assert(!sna->render.active);
		3353	sna->render.vbo = NULL;
		3354	sna->render.vertices = sna->render.vertex_data;
		3355	sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data);
		3356	sna->render.vertex_used = 0;
		3357	sna->render.vertex_index = 0;
		3358	}
		3359	}
		3360
3254	Serge	3361	static void gen6_render_reset(struct sna *sna)
		3362	{
		3363	sna->render_state.gen6.needs_invariant = true;
		3364	sna->render_state.gen6.first_state_packet = true;
		3365	sna->render_state.gen6.ve_id = 3 << 2;
		3366	sna->render_state.gen6.last_primitive = -1;
		3367
		3368	sna->render_state.gen6.num_sf_outputs = 0;
		3369	sna->render_state.gen6.samplers = -1;
		3370	sna->render_state.gen6.blend = -1;
		3371	sna->render_state.gen6.kernel = -1;
		3372	sna->render_state.gen6.drawrect_offset = -1;
		3373	sna->render_state.gen6.drawrect_limit = -1;
		3374	sna->render_state.gen6.surface_table = -1;
		3375
		3376	sna->render.vertex_offset = 0;
		3377	sna->render.nvertex_reloc = 0;
		3378	sna->render.vb_id = 0;
		3379	}
		3380
		3381	static void gen6_render_fini(struct sna *sna)
		3382	{
3258	Serge	3383	kgem_bo_destroy(&sna->kgem, sna->render_state.gen6.general_bo);
3254	Serge	3384	}
		3385
		3386	static bool is_gt2(struct sna *sna)
		3387	{
		3388	return DEVICE_ID(sna->PciInfo) & 0x30;
		3389	}
		3390
		3391	static bool is_mobile(struct sna *sna)
		3392	{
		3393	return (DEVICE_ID(sna->PciInfo) & 0xf) == 0x6;
		3394	}
		3395
		3396	static bool gen6_render_setup(struct sna *sna)
		3397	{
		3398	struct gen6_render_state *state = &sna->render_state.gen6;
		3399	struct sna_static_stream general;
		3400	struct gen6_sampler_state *ss;
		3401	int i, j, k, l, m;
		3402
		3403	state->info = >1_info;
		3404	if (is_gt2(sna))
		3405	state->info = >2_info; /* XXX requires GT_MODE WiZ disabled */
		3406
		3407	sna_static_stream_init(&general);
		3408
		3409	/* Zero pad the start. If you see an offset of 0x0 in the batchbuffer
		3410	* dumps, you know it points to zero.
		3411	*/
		3412	null_create(&general);
		3413	scratch_create(&general);
		3414
		3415	for (m = 0; m < GEN6_KERNEL_COUNT; m++) {
		3416	if (wm_kernels[m].size) {
		3417	state->wm_kernel[m][1] =
		3418	sna_static_stream_add(&general,
		3419	wm_kernels[m].data,
		3420	wm_kernels[m].size,
		3421	64);
		3422	} else {
		3423	if (USE_8_PIXEL_DISPATCH) {
		3424	state->wm_kernel[m][0] =
		3425	sna_static_stream_compile_wm(sna, &general,
		3426	wm_kernels[m].data, 8);
		3427	}
		3428
		3429	if (USE_16_PIXEL_DISPATCH) {
		3430	state->wm_kernel[m][1] =
		3431	sna_static_stream_compile_wm(sna, &general,
		3432	wm_kernels[m].data, 16);
		3433	}
		3434
		3435	if (USE_32_PIXEL_DISPATCH) {
		3436	state->wm_kernel[m][2] =
		3437	sna_static_stream_compile_wm(sna, &general,
		3438	wm_kernels[m].data, 32);
		3439	}
		3440	}
		3441	if ((state->wm_kernel[m][0]\|state->wm_kernel[m][1]\|state->wm_kernel[m][2]) == 0) {
		3442	state->wm_kernel[m][1] =
		3443	sna_static_stream_compile_wm(sna, &general,
		3444	wm_kernels[m].data, 16);
		3445	}
		3446	}
		3447
		3448	ss = sna_static_stream_map(&general,
		3449	2 * sizeof(ss)
		3450	(2 +
		3451	FILTER_COUNT * EXTEND_COUNT *
		3452	FILTER_COUNT * EXTEND_COUNT),
		3453	32);
		3454	state->wm_state = sna_static_stream_offsetof(&general, ss);
		3455	sampler_copy_init(ss); ss += 2;
		3456	sampler_fill_init(ss); ss += 2;
		3457	for (i = 0; i < FILTER_COUNT; i++) {
		3458	for (j = 0; j < EXTEND_COUNT; j++) {
		3459	for (k = 0; k < FILTER_COUNT; k++) {
		3460	for (l = 0; l < EXTEND_COUNT; l++) {
		3461	sampler_state_init(ss++, i, j);
		3462	sampler_state_init(ss++, k, l);
		3463	}
		3464	}
		3465	}
		3466	}
		3467
		3468	state->cc_blend = gen6_composite_create_blend_state(&general);
		3469
		3470	state->general_bo = sna_static_stream_fini(sna, &general);
		3471	return state->general_bo != NULL;
		3472	}
		3473
		3474	bool gen6_render_init(struct sna *sna)
		3475	{
		3476	if (!gen6_render_setup(sna))
		3477	return false;
		3478
3263	Serge	3479	sna->kgem.context_switch = gen6_render_context_switch;
3254	Serge	3480	sna->kgem.retire = gen6_render_retire;
3263	Serge	3481	sna->kgem.expire = gen6_render_expire;
3254	Serge	3482
		3483	// sna->render.composite = gen6_render_composite;
		3484	// sna->render.video = gen6_render_video;
		3485
		3486	// sna->render.copy_boxes = gen6_render_copy_boxes;
		3487
3280	Serge	3488	sna->render.blit_tex = gen6_blit_tex;
		3489
		3490	// sna->render.copy = gen6_render_copy;
		3491
3254	Serge	3492	// sna->render.fill_boxes = gen6_render_fill_boxes;
		3493	// sna->render.fill = gen6_render_fill;
		3494	// sna->render.fill_one = gen6_render_fill_one;
		3495	// sna->render.clear = gen6_render_clear;
		3496
3258	Serge	3497	sna->render.flush = gen6_render_flush;
3254	Serge	3498	sna->render.reset = gen6_render_reset;
		3499	sna->render.fini = gen6_render_fini;
		3500
		3501	sna->render.max_3d_size = GEN6_MAX_SIZE;
		3502	sna->render.max_3d_pitch = 1 << 18;
3291	Serge	3503	sna->render.caps = HW_BIT_BLIT \| HW_TEX_BLIT;
		3504
3254	Serge	3505	return true;
		3506	}
3256	Serge	3507

Subversion Repositories Kolibri OS

(root)/drivers/video/Intel-2D/gen6_render.c – Rev 3769