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Rev | Author | Line No. | Line |
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1029 | serge | 1 | |
2 | #define UHCI_USBCMD 0 /* command register */ |
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3 | #define UHCI_USBINTR 4 /* interrupt register */ |
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4 | #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
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5 | #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ |
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6 | #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ |
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7 | #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ |
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8 | #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ |
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9 | #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ |
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10 | #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ |
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11 | |||
12 | |||
13 | |||
14 | #define USBCMD_RS 0x0001 /* Run/Stop */ |
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15 | #define USBCMD_HCRESET 0x0002 /* Host reset */ |
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16 | #define USBCMD_GRESET 0x0004 /* Global reset */ |
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17 | #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ |
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18 | #define USBCMD_FGR 0x0010 /* Force Global Resume */ |
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19 | #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ |
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20 | #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ |
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21 | #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ |
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22 | |||
23 | |||
24 | #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ |
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25 | #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ |
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26 | #define USBSTS_RD 0x0004 /* Resume Detect */ |
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27 | #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ |
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28 | #define USBSTS_HCPE 0x0010 /* Host Controller Process Error: |
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29 | * the schedule is buggy */ |
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30 | #define USBSTS_HCH 0x0020 /* HC Halted */ |
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31 | |||
32 | |||
33 | |||
34 | #define USBFLBASEADD 8 |
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35 | #define USBSOF 12 |
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36 | #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ |
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37 | |||
38 | |||
39 | #define USBPORTSC2 18 |
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40 | |||
41 | |||
42 | |||
43 | |||
44 | |||
45 | * Make sure the controller is completely inactive, unable to |
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46 | * generate interrupts or do DMA. |
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47 | */ |
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48 | void uhci_reset_hc(hc_t *hc) |
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49 | { |
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50 | /* Turn off PIRQ enable and SMI enable. (This also turns off the |
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51 | * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. |
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52 | */ |
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53 | pciWriteWord(hc->PciTag, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); |
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54 | |||
55 | |||
56 | * new notification of any already connected |
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57 | * ports due to the virtual disconnect that it |
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58 | * implies. |
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59 | */ |
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60 | out16(hc->iobase + UHCI_USBCMD, UHCI_USBCMD_HCRESET); |
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61 | __asm__ __volatile__ ("":::"memory"); |
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62 | |||
63 | |||
64 | |||
65 | |||
66 | dbgprintf("HCRESET not completed yet!\n"); |
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67 | |||
68 | |||
69 | * make sure the controller is stopped. |
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70 | */ |
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71 | out16(hc->iobase + UHCI_USBINTR, 0); |
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72 | out16(hc->iobase + UHCI_USBCMD, 0); |
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73 | }; |
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74 | |||
75 | |||
76 | { |
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77 | u16_t legsup; |
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78 | unsigned int cmd, intr; |
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79 | |||
80 | |||
81 | * When restarting a suspended controller, we expect all the |
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82 | * settings to be the same as we left them: |
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83 | * |
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84 | * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; |
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85 | * Controller is stopped and configured with EGSM set; |
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86 | * No interrupts enabled except possibly Resume Detect. |
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87 | * |
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88 | * If any of these conditions are violated we do a complete reset. |
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89 | */ |
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90 | legsup = pciReadWord(hc->PciTag, UHCI_USBLEGSUP); |
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91 | if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { |
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92 | dbgprintf("%s: legsup = 0x%04x\n",__FUNCTION__, legsup); |
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93 | goto reset_needed; |
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94 | } |
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95 | |||
96 | |||
97 | if ( (cmd & UHCI_USBCMD_RUN) || |
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98 | !(cmd & UHCI_USBCMD_CONFIGURE) || |
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99 | !(cmd & UHCI_USBCMD_EGSM)) |
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100 | { |
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101 | dbgprintf("%s: cmd = 0x%04x\n", __FUNCTION__, cmd); |
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102 | goto reset_needed; |
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103 | } |
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104 | |||
105 | |||
106 | if (intr & (~UHCI_USBINTR_RESUME)) |
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107 | { |
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108 | dbgprintf("%s: intr = 0x%04x\n", __FUNCTION__, intr); |
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109 | goto reset_needed; |
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110 | } |
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111 | return 0; |
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112 | |||
113 | |||
114 | dbgprintf("Performing full reset\n"); |
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115 | uhci_reset_hc(hc); |
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116 | return 1; |
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117 | } |
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118 | |||
119 | |||
120 | |||
1600 | serge | 121 | { |
1029 | serge | 122 | int port; |
1600 | serge | 123 | u32_t ifl; |
124 | u16_t dev_status; |
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125 | int i; |
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1029 | serge | 126 | |
127 | |||
128 | |||
129 | |||
130 | { |
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131 | if(hc->ioBase[i]){ |
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132 | hc->iobase = hc->ioBase[i]; |
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133 | // dbgprintf("Io base_%d 0x%x\n", i,hc->ioBase[i]); |
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134 | break; |
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135 | }; |
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136 | }; |
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137 | |||
138 | |||
139 | * they may have more but gives no way to determine how many there |
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140 | * are. However according to the UHCI spec, Bit 7 of the port |
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141 | * status and control register is always set to 1. So we try to |
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142 | * use this to our advantage. Another common failure mode when |
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143 | * a nonexistent register is addressed is to return all ones, so |
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144 | * we test for that also. |
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145 | */ |
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146 | for (port = 0; port < 2; port++) |
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147 | { |
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148 | u32_t status; |
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149 | |||
150 | |||
151 | dbgprintf("port%d status %x\n", port, status); |
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152 | if (!(status & 0x0080) || status == 0xffff) |
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153 | break; |
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154 | } |
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155 | dbgprintf("detected %d ports\n\n", port); |
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156 | |||
157 | |||
158 | |||
159 | |||
160 | * isn't already safely quiescent. |
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161 | */ |
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162 | uhci_check_and_reset_hc(hc); |
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163 | |||
164 | |||
165 | hc->frame_dma = GetPgAddr(hc->frame_base); |
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166 | hc->frame_number = 0; |
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167 | |||
168 | |||
169 | |||
170 | |||
171 | qh->qelem = 1; |
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172 | |||
173 | |||
174 | |||
175 | |||
176 | |||
177 | |||
178 | hc->frame_base[i] = qh->dma | 2; |
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179 | |||
180 | |||
181 | |||
182 | out8(hc->iobase + USBSOF, USBSOF_DEFAULT); |
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183 | |||
184 | |||
185 | out32(hc->iobase + USBFLBASEADD, hc->frame_dma); |
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186 | |||
187 | |||
188 | out16(hc->iobase + USBFRNUM, 0); |
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189 | |||
190 | |||
191 | out16(hc->iobase + USBCMD, USBCMD_RS | USBCMD_CF | |
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192 | USBCMD_MAXP); |
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193 | |||
194 | |||
195 | out16(hc->iobase + USBPORTSC1 + (port * 2), 0x200); |
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196 | delay(100/10); |
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197 | |||
198 | |||
199 | { |
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200 | time_t timeout; |
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201 | |||
202 | |||
203 | dbgprintf("port%d status %x\n", port, status); |
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204 | |||
205 | |||
206 | |||
207 | |||
208 | while(timeout--) |
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209 | { |
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210 | delay(10/10); |
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211 | status = in16(hc->iobase + USBPORTSC1 + (port * 2)); |
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212 | if(status & 1) |
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213 | { |
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214 | udev_t *dev = kmalloc(sizeof(udev_t),0); |
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1600 | serge | 215 | |
1029 | serge | 216 | |
217 | |||
218 | |||
219 | |||
220 | |||
221 | status = in16(hc->iobase + USBPORTSC1 + (port * 2)); |
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222 | dbgprintf("port%d status %x\n", port, status); |
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223 | |||
224 | |||
1600 | serge | 225 | |
226 | |||
1029 | serge | 227 | dev->port = port; |
228 | dev->ep0_size = 8; |
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229 | dev->status = status; |
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230 | |||
231 | |||
232 | if(status & 4) |
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233 | dbgprintf(" enabled"); |
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234 | else |
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235 | dbgprintf(" disabled"); |
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236 | if(status & 0x100){ |
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237 | dev->speed = 0x4000000; |
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238 | dbgprintf(" low speed\n"); |
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239 | } else { |
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240 | dev->speed = 0; |
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241 | dbgprintf(" full speed\n"); |
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242 | }; |
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243 | |||
244 | |||
245 | list_add_tail(&dev->list, &newdev_list); |
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1600 | serge | 246 | hc->port_map |= 1< |
1029 | serge | 247 | } |
248 | else { |
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249 | free(dev); |
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250 | out16(hc->iobase + USBPORTSC1 + (port * 2), 0); |
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251 | } |
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252 | break; |
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253 | }; |
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254 | }; |
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255 | }; |
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256 | return true; |
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1600 | serge | 257 | }; |
1029 | serge | 258 | |
259 | |||
260 | req_descr[4] = {0x0680,0x0100,0x0000,8}; |
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261 | |||
262 | |||
263 | IN(69) OUT(E1) SETUP(2D) |
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264 | SETUP(0) IN(1) |
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265 | SETUP(0) OUT(1) OUT(0) OUT(1)...IN(1) |
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266 | SETUP(0) IN(1) IN(0) IN(1)...OUT(0) |
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267 | */ |
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268 | |||
269 | |||
270 | |||
1600 | serge | 271 | { |
1029 | serge | 272 | static udev_id = 0; |
273 | static udev_addr = 0; |
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274 | static u16_t __attribute__((aligned(16))) |
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275 | req_addr[4] = {0x0500,0x0001,0x0000,0x0000}; |
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276 | |||
277 | |||
278 | req_descr[4] = {0x0680,0x0100,0x0000,8}; |
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279 | |||
280 | |||
281 | |||
282 | |||
283 | td_t *td0, *td1, *td2; |
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284 | u32_t dev_status; |
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285 | count_t timeout; |
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286 | int address; |
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287 | |||
288 | |||
289 | |||
290 | |||
291 | |||
292 | |||
293 | return false; |
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1600 | serge | 294 | |
1029 | serge | 295 | |
296 | dev->id = (++udev_id << 8) | address; |
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297 | |||
298 | |||
299 | |||
300 | |||
301 | data[1] = 0; |
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302 | |||
303 | |||
304 | return false; |
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1600 | serge | 305 | |
1029 | serge | 306 | |
307 | dev->ep0_size = descr->bMaxPacketSize0; |
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308 | |||
309 | |||
1600 | serge | 310 | } |
1029 | serge | 311 | |
312 | |||
313 | void *data, size_t req_size) |
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314 | { |
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315 | td_t *td, *td_prev; |
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316 | addr_t data_dma; |
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317 | |||
318 | |||
1600 | serge | 319 | size_t size = req_size; |
320 | |||
1029 | serge | 321 | |
1600 | serge | 322 | |
1029 | serge | 323 | |
1600 | serge | 324 | |
1029 | serge | 325 | |
326 | rq->size = req_size; |
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327 | rq->dev = dev; |
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1600 | serge | 328 | |
1029 | serge | 329 | |
330 | data_dma = DMA(data); |
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331 | |||
332 | |||
333 | |||
334 | |||
1600 | serge | 335 | { |
1029 | serge | 336 | if ( size < packet_size) |
1600 | serge | 337 | { |
338 | packet_size = size; |
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339 | }; |
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340 | |||
341 | |||
1029 | serge | 342 | td->link = 1; |
1600 | serge | 343 | |
1029 | serge | 344 | |
345 | rq->td_head = td; |
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346 | |||
347 | |||
348 | td_prev->link = td->dma | 4; |
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349 | td->status = 0x00800000 | dev->speed; |
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350 | td->token = TOKEN(packet_size,enp->toggle,enp->address, |
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1600 | serge | 351 | dev->addr,dir); |
1029 | serge | 352 | td->buffer = data_dma; |
353 | td->bk = td_prev; |
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354 | |||
355 | |||
356 | |||
357 | |||
1600 | serge | 358 | size-= packet_size; |
359 | enp->toggle ^= DATA1; |
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1029 | serge | 360 | } |
361 | rq->td_tail = td; |
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362 | /* |
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363 | dbgprintf("create request %x\n" |
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364 | "head %x\n" |
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365 | "tail %x\n" |
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366 | "data %x\n" |
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367 | "size %x\n", |
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368 | rq, rq->td_head, rq->td_tail, |
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369 | rq->data, rq->size); |
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370 | */ |
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371 | return rq; |
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372 | } |
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373 | |||
374 | |||
1600 | serge | 375 | void *data, size_t req_size) |
1029 | serge | 376 | { |
377 | size_t packet_size = dev->ep0_size; |
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378 | size_t size = req_size; |
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379 | u32_t toggle = DATA1; |
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380 | |||
381 | |||
382 | qh_t *qh; |
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383 | addr_t data_dma = 0; |
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384 | bool retval; |
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1600 | serge | 385 | |
1029 | serge | 386 | |
387 | |||
388 | |||
389 | td0->token = TOKEN( 8, DATA0, 0, dev->addr, 0x2D); |
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390 | td0->buffer = DMA(req); |
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391 | td0->bk = NULL; |
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392 | |||
393 | |||
394 | data_dma = DMA(data); |
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395 | |||
396 | |||
397 | |||
398 | |||
1600 | serge | 399 | { |
1029 | serge | 400 | if ( size < packet_size) |
1600 | serge | 401 | { |
402 | packet_size = size; |
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403 | }; |
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404 | |||
405 | |||
1029 | serge | 406 | td_prev->link = td->dma | 4; |
407 | td->status = 0x00800000 | dev->speed; |
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408 | td->token = TOKEN(packet_size, toggle, 0,dev->addr, pid); |
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409 | td->buffer = data_dma; |
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410 | td->bk = td_prev; |
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411 | |||
412 | |||
413 | |||
414 | |||
415 | size-= packet_size; |
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416 | toggle ^= DATA1; |
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417 | } |
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418 | |||
419 | |||
420 | td_prev->link = td->dma | 4; |
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421 | |||
422 | |||
423 | |||
424 | |||
425 | td->status = 0x00800000 | dev->speed; |
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426 | td->token = (0x7FF<<21)|DATA1|(dev->addr<<8)|pid; |
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427 | td->buffer = 0; |
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428 | td->bk = td_prev; |
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429 | |||
430 | |||
431 | |||
432 | |||
433 | __asm__ __volatile__ ("":::"memory"); |
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434 | |||
435 | |||
436 | while(timeout--){ |
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437 | delay(10/10); |
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438 | if( !(td->status & TD_CTRL_ACTIVE)) |
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439 | break; |
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440 | } |
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441 | |||
442 | |||
443 | (td_prev->status & TD_ANY_ERROR) || |
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444 | (td->status & TD_ANY_ERROR)) |
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445 | { |
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446 | u32_t dev_status = in16(dev->host->iobase + USBSTS); |
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447 | |||
448 | |||
449 | in16(dev->host->iobase + USBFRNUM), |
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450 | in16(dev->host->iobase + USBCMD), |
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451 | dev_status); |
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452 | dbgprintf("td0 status %x\n",td0->status); |
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453 | dbgprintf("td_prev status %x\n",td_prev->status); |
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454 | dbgprintf("td status %x\n",td->status); |
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455 | dbgprintf("qh %x \n", qh->qelem); |
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456 | |||
457 | |||
1600 | serge | 458 | } else retval = true; |
459 | |||
1029 | serge | 460 | |
461 | { |
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462 | td_prev = td->bk; |
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463 | free_td(td); |
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464 | td = td_prev; |
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465 | }while( td != NULL); |
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466 | |||
467 | |||
468 | }; |
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469 | |||
470 | |||
471 | |||
1600 | serge | 472 | { |
1029 | serge | 473 | static u16_t __attribute__((aligned(16))) |
474 | req_descr[4] = {0x0680,0x0100,0x0000,18}; |
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475 | |||
476 | |||
477 | req_conf[4] = {0x0680,0x0200,0x0000,9}; |
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478 | |||
479 | |||
480 | |||
481 | |||
482 | |||
483 | |||
484 | |||
485 | |||
486 | conf_descr_t *conf; |
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487 | |||
488 | |||
489 | dev->id, dev->host->pciId, dev->port); |
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490 | |||
491 | |||
492 | return; |
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493 | |||
494 | |||
495 | |||
496 | |||
497 | "bLength %d\n" |
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498 | "bDescriptorType %d\n" |
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499 | "bcdUSB %x\n" |
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500 | "bDeviceClass %x\n" |
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501 | "bDeviceSubClass %x\n" |
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502 | "bDeviceProtocol %x\n" |
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503 | "bMaxPacketSize0 %d\n" |
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504 | "idVendor %x\n" |
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505 | "idProduct %x\n" |
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506 | "bcdDevice %x\n" |
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507 | "iManufacturer %x\n" |
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508 | "iProduct %x\n" |
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509 | "iSerialNumber %x\n" |
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510 | "bNumConfigurations %d\n\n", |
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511 | descr.bLength, descr.bDescriptorType, |
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512 | descr.bcdUSB, descr.bDeviceClass, |
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513 | descr.bDeviceSubClass, descr.bDeviceProtocol, |
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514 | descr.bMaxPacketSize0, descr.idVendor, |
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515 | descr.idProduct, descr.bcdDevice, |
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516 | descr.iManufacturer, descr.iProduct, |
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517 | descr.iSerialNumber, descr.bNumConfigurations); |
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518 | |||
519 | |||
520 | if( !ctrl_request(dev, req_conf, DIN, &data, 8)) |
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521 | return; |
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522 | |||
523 | |||
524 | |||
525 | |||
526 | |||
527 | |||
528 | conf = malloc(conf_size); |
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529 | |||
530 | |||
531 | return; |
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532 | |||
533 | |||
534 | dptr+= conf->bLength; |
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535 | |||
536 | |||
537 | "bLength %d\n" |
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538 | "bDescriptorType %d\n" |
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539 | "wTotalLength %d\n" |
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540 | "bNumInterfaces %d\n" |
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541 | "bConfigurationValue %x\n" |
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542 | "iConfiguration %d\n" |
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543 | "bmAttributes %x\n" |
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544 | "bMaxPower %dmA\n\n", |
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545 | conf->bLength, |
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546 | conf->bDescriptorType, |
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547 | conf->wTotalLength, |
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548 | conf->bNumInterfaces, |
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549 | conf->bConfigurationValue, |
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550 | conf->iConfiguration, |
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551 | conf->bmAttributes, |
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552 | conf->bMaxPower*2); |
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553 | |||
554 | |||
555 | |||
556 | |||
557 | { |
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558 | case USB_CLASS_AUDIO: |
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559 | dbgprintf( "audio device\n"); |
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560 | break; |
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561 | case USB_CLASS_HID: |
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562 | dev->conf = conf; |
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563 | list_del(&dev->list); |
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1600 | serge | 564 | return init_hid(dev); |
1029 | serge | 565 | |
566 | |||
567 | dbgprintf("printer\n"); |
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568 | break; |
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569 | case USB_CLASS_MASS_STORAGE: |
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570 | dbgprintf("mass storage device\n"); |
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571 | break; |
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572 | case USB_CLASS_HUB: |
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573 | dbgprintf("hub device\n"); |
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574 | break; |
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575 | default: |
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576 | dbgprintf("unknown device\n"); |
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577 | }; |
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578 | };8)|pid; |
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579 | ><8)|pid; |